LegalizeIntegerTypes.cpp revision 9f6079fd9db5614db7c3fdfd2d2142192eba7c66
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22#include "llvm/CodeGen/PseudoSourceValue.h" 23using namespace llvm; 24 25//===----------------------------------------------------------------------===// 26// Integer Result Promotion 27//===----------------------------------------------------------------------===// 28 29/// PromoteIntegerResult - This method is called when a result of a node is 30/// found to be in need of promotion to a larger type. At this point, the node 31/// may also have invalid operands or may have other results that need 32/// expansion, we just know that (at least) one result needs promotion. 33void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 34 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n"); 35 SDValue Res = SDValue(); 36 37 // See if the target wants to custom expand this node. 38 if (CustomLowerResults(N, N->getValueType(ResNo), true)) 39 return; 40 41 switch (N->getOpcode()) { 42 default: 43#ifndef NDEBUG 44 cerr << "PromoteIntegerResult #" << ResNo << ": "; 45 N->dump(&DAG); cerr << "\n"; 46#endif 47 assert(0 && "Do not know how to promote this operator!"); 48 abort(); 49 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 50 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 51 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break; 52 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 53 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 54 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 55 case ISD::CONVERT_RNDSAT: 56 Res = PromoteIntRes_CONVERT_RNDSAT(N); break; 57 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; 58 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break; 59 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; 60 case ISD::EXTRACT_VECTOR_ELT: 61 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 62 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 63 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break; 64 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; 65 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 66 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; 67 case ISD::SIGN_EXTEND_INREG: 68 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 69 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 70 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; 71 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; 72 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break; 73 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break; 74 75 case ISD::SIGN_EXTEND: 76 case ISD::ZERO_EXTEND: 77 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; 78 79 case ISD::FP_TO_SINT: 80 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; 81 82 case ISD::AND: 83 case ISD::OR: 84 case ISD::XOR: 85 case ISD::ADD: 86 case ISD::SUB: 87 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break; 88 89 case ISD::SDIV: 90 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; 91 92 case ISD::UDIV: 93 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break; 94 95 case ISD::SADDO: 96 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; 97 case ISD::UADDO: 98 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; 99 case ISD::SMULO: 100 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; 101 102 case ISD::ATOMIC_LOAD_ADD: 103 case ISD::ATOMIC_LOAD_SUB: 104 case ISD::ATOMIC_LOAD_AND: 105 case ISD::ATOMIC_LOAD_OR: 106 case ISD::ATOMIC_LOAD_XOR: 107 case ISD::ATOMIC_LOAD_NAND: 108 case ISD::ATOMIC_LOAD_MIN: 109 case ISD::ATOMIC_LOAD_MAX: 110 case ISD::ATOMIC_LOAD_UMIN: 111 case ISD::ATOMIC_LOAD_UMAX: 112 case ISD::ATOMIC_SWAP: 113 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 114 115 case ISD::ATOMIC_CMP_SWAP: 116 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 117 } 118 119 // If the result is null then the sub-method took care of registering it. 120 if (Res.getNode()) 121 SetPromotedInteger(SDValue(N, ResNo), Res); 122} 123 124SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 125 // Sign-extend the new bits, and continue the assertion. 126 SDValue Op = SExtPromotedInteger(N->getOperand(0)); 127 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(), 128 Op.getValueType(), Op, N->getOperand(1)); 129} 130 131SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 132 // Zero the new bits, and continue the assertion. 133 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 134 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), 135 Op.getValueType(), Op, N->getOperand(1)); 136} 137 138SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 139 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 140 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 141 N->getMemoryVT(), 142 N->getChain(), N->getBasePtr(), 143 Op2, N->getSrcValue(), N->getAlignment()); 144 // Legalized the chain result - switch anything that used the old chain to 145 // use the new one. 146 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 147 return Res; 148} 149 150SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 151 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 152 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 153 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 154 N->getMemoryVT(), N->getChain(), N->getBasePtr(), 155 Op2, Op3, N->getSrcValue(), N->getAlignment()); 156 // Legalized the chain result - switch anything that used the old chain to 157 // use the new one. 158 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 159 return Res; 160} 161 162SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 163 SDValue InOp = N->getOperand(0); 164 MVT InVT = InOp.getValueType(); 165 MVT NInVT = TLI.getTypeToTransformTo(InVT); 166 MVT OutVT = N->getValueType(0); 167 MVT NOutVT = TLI.getTypeToTransformTo(OutVT); 168 DebugLoc dl = N->getDebugLoc(); 169 170 switch (getTypeAction(InVT)) { 171 default: 172 assert(false && "Unknown type action!"); 173 break; 174 case Legal: 175 break; 176 case PromoteInteger: 177 if (NOutVT.bitsEq(NInVT)) 178 // The input promotes to the same size. Convert the promoted value. 179 return DAG.getNode(ISD::BIT_CONVERT, dl, 180 NOutVT, GetPromotedInteger(InOp)); 181 break; 182 case SoftenFloat: 183 // Promote the integer operand by hand. 184 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); 185 case ExpandInteger: 186 case ExpandFloat: 187 break; 188 case ScalarizeVector: 189 // Convert the element to an integer and promote it by hand. 190 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 191 BitConvertToInteger(GetScalarizedVector(InOp))); 192 case SplitVector: { 193 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 194 // pieces of the input into integers and reassemble in the final type. 195 SDValue Lo, Hi; 196 GetSplitVector(N->getOperand(0), Lo, Hi); 197 Lo = BitConvertToInteger(Lo); 198 Hi = BitConvertToInteger(Hi); 199 200 if (TLI.isBigEndian()) 201 std::swap(Lo, Hi); 202 203 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, 204 MVT::getIntegerVT(NOutVT.getSizeInBits()), 205 JoinIntegers(Lo, Hi)); 206 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp); 207 } 208 case WidenVector: 209 if (OutVT.bitsEq(NInVT)) 210 // The input is widened to the same size. Convert to the widened value. 211 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp)); 212 } 213 214 // Otherwise, lower the bit-convert to a store/load from the stack. 215 // Create the stack frame object. Make sure it is aligned for both 216 // the source and destination types. 217 SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT); 218 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 219 const Value *SV = PseudoSourceValue::getFixedStack(FI); 220 221 // Emit a store to the stack slot. 222 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0); 223 224 // Result is an extending load from the stack slot. 225 return DAG.getExtLoad(ISD::EXTLOAD, dl, NOutVT, Store, FIPtr, SV, 0, OutVT); 226} 227 228SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 229 SDValue Op = GetPromotedInteger(N->getOperand(0)); 230 MVT OVT = N->getValueType(0); 231 MVT NVT = Op.getValueType(); 232 DebugLoc dl = N->getDebugLoc(); 233 234 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 235 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 236 DAG.getConstant(DiffBits, TLI.getPointerTy())); 237} 238 239SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 240 // The pair element type may be legal, or may not promote to the same type as 241 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 242 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), 243 TLI.getTypeToTransformTo(N->getValueType(0)), 244 JoinIntegers(N->getOperand(0), N->getOperand(1))); 245} 246 247SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 248 MVT VT = N->getValueType(0); 249 // Zero extend things like i1, sign extend everything else. It shouldn't 250 // matter in theory which one we pick, but this tends to give better code? 251 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 252 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), 253 SDValue(N, 0)); 254 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 255 return Result; 256} 257 258SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 259 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 260 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 261 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 262 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 263 "can only promote integers"); 264 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 265 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0), 266 N->getOperand(1), N->getOperand(2), 267 N->getOperand(3), N->getOperand(4), CvtCode); 268} 269 270SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 271 // Zero extend to the promoted type and do the count there. 272 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 273 MVT OVT = N->getValueType(0); 274 MVT NVT = Op.getValueType(); 275 Op = DAG.getNode(ISD::CTLZ, NVT, Op); 276 // Subtract off the extra leading bits in the bigger type. 277 return DAG.getNode(ISD::SUB, N->getDebugLoc(), NVT, Op, 278 DAG.getConstant(NVT.getSizeInBits() - 279 OVT.getSizeInBits(), NVT)); 280} 281 282SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 283 // Zero extend to the promoted type and do the count there. 284 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 285 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op); 286} 287 288SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 289 SDValue Op = GetPromotedInteger(N->getOperand(0)); 290 MVT OVT = N->getValueType(0); 291 MVT NVT = Op.getValueType(); 292 DebugLoc dl = N->getDebugLoc(); 293 // The count is the same in the promoted type except if the original 294 // value was zero. This can be handled by setting the bit just off 295 // the top of the original type. 296 APInt TopBit(NVT.getSizeInBits(), 0); 297 TopBit.set(OVT.getSizeInBits()); 298 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT)); 299 return DAG.getNode(ISD::CTTZ, dl, NVT, Op); 300} 301 302SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 303 MVT OldVT = N->getValueType(0); 304 SDValue OldVec = N->getOperand(0); 305 if (getTypeAction(OldVec.getValueType()) == WidenVector) 306 OldVec = GetWidenedVector(N->getOperand(0)); 307 unsigned OldElts = OldVec.getValueType().getVectorNumElements(); 308 DebugLoc dl = N->getDebugLoc(); 309 310 if (OldElts == 1) { 311 assert(!isTypeLegal(OldVec.getValueType()) && 312 "Legal one-element vector of a type needing promotion!"); 313 // It is tempting to follow GetScalarizedVector by a call to 314 // GetPromotedInteger, but this would be wrong because the 315 // scalarized value may not yet have been processed. 316 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), 317 GetScalarizedVector(OldVec)); 318 } 319 320 // Convert to a vector half as long with an element type of twice the width, 321 // for example <4 x i16> -> <2 x i32>. 322 assert(!(OldElts & 1) && "Odd length vectors not supported!"); 323 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 324 assert(OldVT.isSimple() && NewVT.isSimple()); 325 326 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl, 327 MVT::getVectorVT(NewVT, OldElts / 2), 328 OldVec); 329 330 // Extract the element at OldIdx / 2 from the new vector. 331 SDValue OldIdx = N->getOperand(1); 332 SDValue NewIdx = DAG.getNode(ISD::SRL, dl, OldIdx.getValueType(), OldIdx, 333 DAG.getConstant(1, TLI.getPointerTy())); 334 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, NewIdx); 335 336 // Select the appropriate half of the element: Lo if OldIdx was even, 337 // Hi if it was odd. 338 SDValue Lo = Elt; 339 SDValue Hi = DAG.getNode(ISD::SRL, dl, NewVT, Elt, 340 DAG.getConstant(OldVT.getSizeInBits(), 341 TLI.getPointerTy())); 342 if (TLI.isBigEndian()) 343 std::swap(Lo, Hi); 344 345 // Extend to the promoted type. 346 SDValue Odd = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, OldIdx); 347 SDValue Res = DAG.getNode(ISD::SELECT, dl, NewVT, Odd, Hi, Lo); 348 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), Res); 349} 350 351SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 352 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 353 unsigned NewOpc = N->getOpcode(); 354 DebugLoc dl = N->getDebugLoc(); 355 356 // If we're promoting a UINT to a larger size, check to see if the new node 357 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 358 // we can use that instead. This allows us to generate better code for 359 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 360 // legal, such as PowerPC. 361 if (N->getOpcode() == ISD::FP_TO_UINT && 362 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) && 363 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) 364 NewOpc = ISD::FP_TO_SINT; 365 366 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); 367 368 // Assert that the converted value fits in the original type. If it doesn't 369 // (eg: because the value being converted is too big), then the result of the 370 // original operation was undefined anyway, so the assert is still correct. 371 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 372 ISD::AssertZext : ISD::AssertSext, dl, 373 NVT, Res, DAG.getValueType(N->getValueType(0))); 374} 375 376SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 377 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 378 DebugLoc dl = N->getDebugLoc(); 379 380 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 381 SDValue Res = GetPromotedInteger(N->getOperand(0)); 382 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 383 384 // If the result and operand types are the same after promotion, simplify 385 // to an in-register extension. 386 if (NVT == Res.getValueType()) { 387 // The high bits are not guaranteed to be anything. Insert an extend. 388 if (N->getOpcode() == ISD::SIGN_EXTEND) 389 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 390 DAG.getValueType(N->getOperand(0).getValueType())); 391 if (N->getOpcode() == ISD::ZERO_EXTEND) 392 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); 393 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 394 return Res; 395 } 396 } 397 398 // Otherwise, just extend the original operand all the way to the larger type. 399 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 400} 401 402SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 403 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 404 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 405 ISD::LoadExtType ExtType = 406 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 407 DebugLoc dl = N->getDebugLoc(); 408 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), 409 N->getSrcValue(), N->getSrcValueOffset(), 410 N->getMemoryVT(), N->isVolatile(), 411 N->getAlignment()); 412 413 // Legalized the chain result - switch anything that used the old chain to 414 // use the new one. 415 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 416 return Res; 417} 418 419/// Promote the overflow flag of an overflowing arithmetic node. 420SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { 421 // Simply change the return type of the boolean result. 422 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); 423 MVT ValueVTs[] = { N->getValueType(0), NVT }; 424 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) }; 425 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), 426 DAG.getVTList(ValueVTs, 2), Ops, 2); 427 428 // Modified the sum result - switch anything that used the old sum to use 429 // the new one. 430 ReplaceValueWith(SDValue(N, 0), Res); 431 432 return SDValue(Res.getNode(), 1); 433} 434 435SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { 436 if (ResNo == 1) 437 return PromoteIntRes_Overflow(N); 438 439 // The operation overflowed iff the result in the larger type is not the 440 // sign extension of its truncation to the original type. 441 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 442 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 443 MVT OVT = N->getOperand(0).getValueType(); 444 MVT NVT = LHS.getValueType(); 445 DebugLoc dl = N->getDebugLoc(); 446 447 // Do the arithmetic in the larger type. 448 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 449 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 450 451 // Calculate the overflow flag: sign extend the arithmetic result from 452 // the original type. 453 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 454 DAG.getValueType(OVT)); 455 // Overflowed if and only if this is not equal to Res. 456 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 457 458 // Use the calculated overflow everywhere. 459 ReplaceValueWith(SDValue(N, 1), Ofl); 460 461 return Res; 462} 463 464SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 465 // Sign extend the input. 466 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 467 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 468 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 469 LHS.getValueType(), LHS, RHS); 470} 471 472SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 473 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 474 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 475 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 476 LHS.getValueType(), N->getOperand(0),LHS,RHS); 477} 478 479SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 480 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 481 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 482 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 483 LHS.getValueType(), N->getOperand(0), 484 N->getOperand(1), LHS, RHS, N->getOperand(4)); 485} 486 487SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 488 MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); 489 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 490 DebugLoc dl = N->getDebugLoc(); 491 492 // Get the SETCC result using the canonical SETCC type. 493 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0), 494 N->getOperand(1), N->getOperand(2)); 495 496 // Convert to the expected type. 497 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 498 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 499 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 500} 501 502SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 503 return DAG.getNode(ISD::SHL, N->getDebugLoc(), 504 TLI.getTypeToTransformTo(N->getValueType(0)), 505 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 506} 507 508SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 509 SDValue Op = GetPromotedInteger(N->getOperand(0)); 510 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), 511 Op.getValueType(), Op, N->getOperand(1)); 512} 513 514SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 515 // The input may have strange things in the top bits of the registers, but 516 // these operations don't care. They may have weird bits going out, but 517 // that too is okay if they are integer operations. 518 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 519 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 520 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 521 LHS.getValueType(), LHS, RHS); 522} 523 524SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 525 // The input value must be properly sign extended. 526 SDValue Res = SExtPromotedInteger(N->getOperand(0)); 527 return DAG.getNode(ISD::SRA, N->getDebugLoc(), 528 Res.getValueType(), Res, N->getOperand(1)); 529} 530 531SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 532 // The input value must be properly zero extended. 533 MVT VT = N->getValueType(0); 534 MVT NVT = TLI.getTypeToTransformTo(VT); 535 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 536 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1)); 537} 538 539SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 540 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 541 SDValue Res; 542 543 switch (getTypeAction(N->getOperand(0).getValueType())) { 544 default: assert(0 && "Unknown type action!"); 545 case Legal: 546 case ExpandInteger: 547 Res = N->getOperand(0); 548 break; 549 case PromoteInteger: 550 Res = GetPromotedInteger(N->getOperand(0)); 551 break; 552 } 553 554 // Truncate to NVT instead of VT 555 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res); 556} 557 558SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) { 559 if (ResNo == 1) 560 return PromoteIntRes_Overflow(N); 561 562 // The operation overflowed iff the result in the larger type is not the 563 // zero extension of its truncation to the original type. 564 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 565 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 566 MVT OVT = N->getOperand(0).getValueType(); 567 MVT NVT = LHS.getValueType(); 568 DebugLoc dl = N->getDebugLoc(); 569 570 // Do the arithmetic in the larger type. 571 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 572 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 573 574 // Calculate the overflow flag: zero extend the arithmetic result from 575 // the original type. 576 SDValue Ofl = DAG.getZeroExtendInReg(Res, OVT); 577 // Overflowed if and only if this is not equal to Res. 578 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 579 580 // Use the calculated overflow everywhere. 581 ReplaceValueWith(SDValue(N, 1), Ofl); 582 583 return Res; 584} 585 586SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 587 // Zero extend the input. 588 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 589 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 590 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 591 LHS.getValueType(), LHS, RHS); 592} 593 594SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 595 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), 596 TLI.getTypeToTransformTo(N->getValueType(0))); 597} 598 599SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 600 SDValue Chain = N->getOperand(0); // Get the chain. 601 SDValue Ptr = N->getOperand(1); // Get the pointer. 602 MVT VT = N->getValueType(0); 603 DebugLoc dl = N->getDebugLoc(); 604 605 MVT RegVT = TLI.getRegisterType(VT); 606 unsigned NumRegs = TLI.getNumRegisters(VT); 607 // The argument is passed as NumRegs registers of type RegVT. 608 609 SmallVector<SDValue, 8> Parts(NumRegs); 610 for (unsigned i = 0; i < NumRegs; ++i) { 611 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2)); 612 Chain = Parts[i].getValue(1); 613 } 614 615 // Handle endianness of the load. 616 if (TLI.isBigEndian()) 617 std::reverse(Parts.begin(), Parts.end()); 618 619 // Assemble the parts in the promoted type. 620 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 621 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); 622 for (unsigned i = 1; i < NumRegs; ++i) { 623 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); 624 // Shift it to the right position and "or" it in. 625 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, 626 DAG.getConstant(i * RegVT.getSizeInBits(), 627 TLI.getPointerTy())); 628 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part); 629 } 630 631 // Modified the chain result - switch anything that used the old chain to 632 // use the new one. 633 ReplaceValueWith(SDValue(N, 1), Chain); 634 635 return Res; 636} 637 638SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) { 639 assert(ResNo == 1 && "Only boolean result promotion currently supported!"); 640 return PromoteIntRes_Overflow(N); 641} 642 643//===----------------------------------------------------------------------===// 644// Integer Operand Promotion 645//===----------------------------------------------------------------------===// 646 647/// PromoteIntegerOperand - This method is called when the specified operand of 648/// the specified node is found to need promotion. At this point, all of the 649/// result types of the node are known to be legal, but other operands of the 650/// node may need promotion or expansion as well as the specified one. 651bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 652 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n"); 653 SDValue Res = SDValue(); 654 655 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false)) 656 return false; 657 658 switch (N->getOpcode()) { 659 default: 660 #ifndef NDEBUG 661 cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; 662 N->dump(&DAG); cerr << "\n"; 663 #endif 664 assert(0 && "Do not know how to promote this operator's operand!"); 665 abort(); 666 667 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 668 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 669 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 670 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 671 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 672 case ISD::CONVERT_RNDSAT: 673 Res = PromoteIntOp_CONVERT_RNDSAT(N); break; 674 case ISD::INSERT_VECTOR_ELT: 675 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 676 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 677 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 678 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 679 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 680 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 681 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; 682 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 683 OpNo); break; 684 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 685 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; 686 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 687 688 case ISD::SHL: 689 case ISD::SRA: 690 case ISD::SRL: 691 case ISD::ROTL: 692 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break; 693 } 694 695 // If the result is null, the sub-method took care of registering results etc. 696 if (!Res.getNode()) return false; 697 698 // If the result is N, the sub-method updated N in place. Tell the legalizer 699 // core about this. 700 if (Res.getNode() == N) 701 return true; 702 703 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 704 "Invalid operand expansion"); 705 706 ReplaceValueWith(SDValue(N, 0), Res); 707 return false; 708} 709 710/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 711/// shared among BR_CC, SELECT_CC, and SETCC handlers. 712void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 713 ISD::CondCode CCCode) { 714 // We have to insert explicit sign or zero extends. Note that we could 715 // insert sign extends for ALL conditions, but zero extend is cheaper on 716 // many machines (an AND instead of two shifts), so prefer it. 717 switch (CCCode) { 718 default: assert(0 && "Unknown integer comparison!"); 719 case ISD::SETEQ: 720 case ISD::SETNE: 721 case ISD::SETUGE: 722 case ISD::SETUGT: 723 case ISD::SETULE: 724 case ISD::SETULT: 725 // ALL of these operations will work if we either sign or zero extend 726 // the operands (including the unsigned comparisons!). Zero extend is 727 // usually a simpler/cheaper operation, so prefer it. 728 NewLHS = ZExtPromotedInteger(NewLHS); 729 NewRHS = ZExtPromotedInteger(NewRHS); 730 break; 731 case ISD::SETGE: 732 case ISD::SETGT: 733 case ISD::SETLT: 734 case ISD::SETLE: 735 NewLHS = SExtPromotedInteger(NewLHS); 736 NewRHS = SExtPromotedInteger(NewRHS); 737 break; 738 } 739} 740 741SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 742 SDValue Op = GetPromotedInteger(N->getOperand(0)); 743 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); 744} 745 746SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 747 assert(OpNo == 2 && "Don't know how to promote this operand!"); 748 749 SDValue LHS = N->getOperand(2); 750 SDValue RHS = N->getOperand(3); 751 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 752 753 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 754 // legal types. 755 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 756 N->getOperand(1), LHS, RHS, N->getOperand(4)); 757} 758 759SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 760 assert(OpNo == 1 && "only know how to promote condition"); 761 762 // Promote all the way up to the canonical SetCC type. 763 MVT SVT = TLI.getSetCCResultType(MVT::Other); 764 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT); 765 766 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 767 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond, 768 N->getOperand(2)); 769} 770 771SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 772 // Since the result type is legal, the operands must promote to it. 773 MVT OVT = N->getOperand(0).getValueType(); 774 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); 775 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 776 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 777 DebugLoc dl = N->getDebugLoc(); 778 779 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, 780 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy())); 781 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); 782} 783 784SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 785 // The vector type is legal but the element type is not. This implies 786 // that the vector is a power-of-two in length and that the element 787 // type does not have a strange size (eg: it is not i1). 788 MVT VecVT = N->getValueType(0); 789 unsigned NumElts = VecVT.getVectorNumElements(); 790 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 791 DebugLoc dl = N->getDebugLoc(); 792 793 // Build a vector of half the length out of elements of twice the bitwidth. 794 // For example <4 x i16> -> <2 x i32>. 795 MVT OldVT = N->getOperand(0).getValueType(); 796 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 797 assert(OldVT.isSimple() && NewVT.isSimple()); 798 799 std::vector<SDValue> NewElts; 800 NewElts.reserve(NumElts/2); 801 802 for (unsigned i = 0; i < NumElts; i += 2) { 803 // Combine two successive elements into one promoted element. 804 SDValue Lo = N->getOperand(i); 805 SDValue Hi = N->getOperand(i+1); 806 if (TLI.isBigEndian()) 807 std::swap(Lo, Hi); 808 NewElts.push_back(JoinIntegers(Lo, Hi)); 809 } 810 811 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, 812 MVT::getVectorVT(NewVT, NewElts.size()), 813 &NewElts[0], NewElts.size()); 814 815 // Convert the new vector to the old vector type. 816 return DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, NewVec); 817} 818 819SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { 820 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 821 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 822 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 823 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && 824 "can only promote integer arguments"); 825 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 826 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp, 827 N->getOperand(1), N->getOperand(2), 828 N->getOperand(3), N->getOperand(4), CvtCode); 829} 830 831SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 832 unsigned OpNo) { 833 if (OpNo == 1) { 834 // Promote the inserted value. This is valid because the type does not 835 // have to match the vector element type. 836 837 // Check that any extra bits introduced will be truncated away. 838 assert(N->getOperand(1).getValueType().getSizeInBits() >= 839 N->getValueType(0).getVectorElementType().getSizeInBits() && 840 "Type of inserted value narrower than vector element type!"); 841 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 842 GetPromotedInteger(N->getOperand(1)), 843 N->getOperand(2)); 844 } 845 846 assert(OpNo == 2 && "Different operand and result vector types?"); 847 848 // Promote the index. 849 SDValue Idx = ZExtPromotedInteger(N->getOperand(2)); 850 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 851 N->getOperand(1), Idx); 852} 853 854SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 855 SDValue NewOps[6]; 856 NewOps[0] = N->getOperand(0); 857 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 858 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 859 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1); 860 } 861 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, 862 array_lengthof(NewOps)); 863} 864 865SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 866 assert(OpNo == 0 && "Only know how to promote condition"); 867 868 // Promote all the way up to the canonical SetCC type. 869 MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType()); 870 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT); 871 872 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, 873 N->getOperand(1), N->getOperand(2)); 874} 875 876SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 877 assert(OpNo == 0 && "Don't know how to promote this operand!"); 878 879 SDValue LHS = N->getOperand(0); 880 SDValue RHS = N->getOperand(1); 881 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 882 883 // The CC (#4) and the possible return values (#2 and #3) have legal types. 884 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2), 885 N->getOperand(3), N->getOperand(4)); 886} 887 888SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 889 assert(OpNo == 0 && "Don't know how to promote this operand!"); 890 891 SDValue LHS = N->getOperand(0); 892 SDValue RHS = N->getOperand(1); 893 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 894 895 // The CC (#2) is always legal. 896 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2)); 897} 898 899SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) { 900 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 901 ZExtPromotedInteger(N->getOperand(1))); 902} 903 904SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 905 SDValue Op = GetPromotedInteger(N->getOperand(0)); 906 DebugLoc dl = N->getDebugLoc(); 907 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 908 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), 909 Op, DAG.getValueType(N->getOperand(0).getValueType())); 910} 911 912SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) { 913 return DAG.UpdateNodeOperands(SDValue(N, 0), 914 SExtPromotedInteger(N->getOperand(0))); 915} 916 917SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 918 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 919 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 920 int SVOffset = N->getSrcValueOffset(); 921 unsigned Alignment = N->getAlignment(); 922 bool isVolatile = N->isVolatile(); 923 DebugLoc dl = N->getDebugLoc(); 924 925 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 926 927 // Truncate the value and store the result. 928 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(), 929 SVOffset, N->getMemoryVT(), 930 isVolatile, Alignment); 931} 932 933SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 934 SDValue Op = GetPromotedInteger(N->getOperand(0)); 935 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op); 936} 937 938SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { 939 return DAG.UpdateNodeOperands(SDValue(N, 0), 940 ZExtPromotedInteger(N->getOperand(0))); 941} 942 943SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 944 SDValue Op = GetPromotedInteger(N->getOperand(0)); 945 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); 946 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); 947} 948 949 950//===----------------------------------------------------------------------===// 951// Integer Result Expansion 952//===----------------------------------------------------------------------===// 953 954/// ExpandIntegerResult - This method is called when the specified result of the 955/// specified node is found to need expansion. At this point, the node may also 956/// have invalid operands or may have other results that need promotion, we just 957/// know that (at least) one result needs expansion. 958void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 959 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n"); 960 SDValue Lo, Hi; 961 Lo = Hi = SDValue(); 962 963 // See if the target wants to custom expand this node. 964 if (CustomLowerResults(N, N->getValueType(ResNo), true)) 965 return; 966 967 switch (N->getOpcode()) { 968 default: 969#ifndef NDEBUG 970 cerr << "ExpandIntegerResult #" << ResNo << ": "; 971 N->dump(&DAG); cerr << "\n"; 972#endif 973 assert(0 && "Do not know how to expand the result of this operator!"); 974 abort(); 975 976 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 977 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 978 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 979 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 980 981 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 982 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 983 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 984 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 985 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 986 987 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 988 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 989 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 990 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 991 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 992 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 993 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 994 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 995 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 996 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 997 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 998 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 999 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 1000 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 1001 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 1002 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 1003 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 1004 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 1005 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 1006 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 1007 1008 case ISD::AND: 1009 case ISD::OR: 1010 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 1011 1012 case ISD::ADD: 1013 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1014 1015 case ISD::ADDC: 1016 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 1017 1018 case ISD::ADDE: 1019 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 1020 1021 case ISD::SHL: 1022 case ISD::SRA: 1023 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1024 } 1025 1026 // If Lo/Hi is null, the sub-method took care of registering results etc. 1027 if (Lo.getNode()) 1028 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1029} 1030 1031/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1032/// and the shift amount is a constant 'Amt'. Expand the operation. 1033void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1034 SDValue &Lo, SDValue &Hi) { 1035 DebugLoc dl = N->getDebugLoc(); 1036 // Expand the incoming operand to be shifted, so that we have its parts 1037 SDValue InL, InH; 1038 GetExpandedInteger(N->getOperand(0), InL, InH); 1039 1040 MVT NVT = InL.getValueType(); 1041 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1042 unsigned NVTBits = NVT.getSizeInBits(); 1043 MVT ShTy = N->getOperand(1).getValueType(); 1044 1045 if (N->getOpcode() == ISD::SHL) { 1046 if (Amt > VTBits) { 1047 Lo = Hi = DAG.getConstant(0, NVT); 1048 } else if (Amt > NVTBits) { 1049 Lo = DAG.getConstant(0, NVT); 1050 Hi = DAG.getNode(ISD::SHL, dl, 1051 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1052 } else if (Amt == NVTBits) { 1053 Lo = DAG.getConstant(0, NVT); 1054 Hi = InL; 1055 } else if (Amt == 1 && 1056 TLI.isOperationLegalOrCustom(ISD::ADDC, 1057 TLI.getTypeToExpandTo(NVT))) { 1058 // Emit this X << 1 as X+X. 1059 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1060 SDValue LoOps[2] = { InL, InL }; 1061 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1062 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1063 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1064 } else { 1065 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy)); 1066 Hi = DAG.getNode(ISD::OR, dl, NVT, 1067 DAG.getNode(ISD::SHL, dl, NVT, InH, 1068 DAG.getConstant(Amt, ShTy)), 1069 DAG.getNode(ISD::SRL, dl, NVT, InL, 1070 DAG.getConstant(NVTBits-Amt, ShTy))); 1071 } 1072 return; 1073 } 1074 1075 if (N->getOpcode() == ISD::SRL) { 1076 if (Amt > VTBits) { 1077 Lo = DAG.getConstant(0, NVT); 1078 Hi = DAG.getConstant(0, NVT); 1079 } else if (Amt > NVTBits) { 1080 Lo = DAG.getNode(ISD::SRL, dl, 1081 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1082 Hi = DAG.getConstant(0, NVT); 1083 } else if (Amt == NVTBits) { 1084 Lo = InH; 1085 Hi = DAG.getConstant(0, NVT); 1086 } else { 1087 Lo = DAG.getNode(ISD::OR, dl, NVT, 1088 DAG.getNode(ISD::SRL, dl, NVT, InL, 1089 DAG.getConstant(Amt, ShTy)), 1090 DAG.getNode(ISD::SHL, dl, NVT, InH, 1091 DAG.getConstant(NVTBits-Amt, ShTy))); 1092 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); 1093 } 1094 return; 1095 } 1096 1097 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1098 if (Amt > VTBits) { 1099 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 1100 DAG.getConstant(NVTBits-1, ShTy)); 1101 } else if (Amt > NVTBits) { 1102 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 1103 DAG.getConstant(Amt-NVTBits, ShTy)); 1104 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 1105 DAG.getConstant(NVTBits-1, ShTy)); 1106 } else if (Amt == NVTBits) { 1107 Lo = InH; 1108 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 1109 DAG.getConstant(NVTBits-1, ShTy)); 1110 } else { 1111 Lo = DAG.getNode(ISD::OR, NVT, 1112 DAG.getNode(ISD::SRL, dl, NVT, InL, 1113 DAG.getConstant(Amt, ShTy)), 1114 DAG.getNode(ISD::SHL, dl, NVT, InH, 1115 DAG.getConstant(NVTBits-Amt, ShTy))); 1116 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); 1117 } 1118} 1119 1120/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1121/// this shift based on knowledge of the high bit of the shift amount. If we 1122/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1123/// shift amount. 1124bool DAGTypeLegalizer:: 1125ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1126 SDValue Amt = N->getOperand(1); 1127 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1128 MVT ShTy = Amt.getValueType(); 1129 unsigned ShBits = ShTy.getSizeInBits(); 1130 unsigned NVTBits = NVT.getSizeInBits(); 1131 assert(isPowerOf2_32(NVTBits) && 1132 "Expanded integer type size not a power of two!"); 1133 DebugLoc dl = N->getDebugLoc(); 1134 1135 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1136 APInt KnownZero, KnownOne; 1137 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1138 1139 // If we don't know anything about the high bits, exit. 1140 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1141 return false; 1142 1143 // Get the incoming operand to be shifted. 1144 SDValue InL, InH; 1145 GetExpandedInteger(N->getOperand(0), InL, InH); 1146 1147 // If we know that any of the high bits of the shift amount are one, then we 1148 // can do this as a couple of simple shifts. 1149 if (KnownOne.intersects(HighBitMask)) { 1150 // Mask out the high bit, which we know is set. 1151 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, 1152 DAG.getConstant(~HighBitMask, ShTy)); 1153 1154 switch (N->getOpcode()) { 1155 default: assert(0 && "Unknown shift"); 1156 case ISD::SHL: 1157 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1158 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 1159 return true; 1160 case ISD::SRL: 1161 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1162 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 1163 return true; 1164 case ISD::SRA: 1165 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 1166 DAG.getConstant(NVTBits-1, ShTy)); 1167 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 1168 return true; 1169 } 1170 } 1171 1172#if 0 1173 // FIXME: This code is broken for shifts with a zero amount! 1174 // If we know that all of the high bits of the shift amount are zero, then we 1175 // can do this as a couple of simple shifts. 1176 if ((KnownZero & HighBitMask) == HighBitMask) { 1177 // Compute 32-amt. 1178 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1179 DAG.getConstant(NVTBits, ShTy), 1180 Amt); 1181 unsigned Op1, Op2; 1182 switch (N->getOpcode()) { 1183 default: assert(0 && "Unknown shift"); 1184 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1185 case ISD::SRL: 1186 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1187 } 1188 1189 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1190 Hi = DAG.getNode(ISD::OR, NVT, 1191 DAG.getNode(Op1, NVT, InH, Amt), 1192 DAG.getNode(Op2, NVT, InL, Amt2)); 1193 return true; 1194 } 1195#endif 1196 1197 return false; 1198} 1199 1200void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1201 SDValue &Lo, SDValue &Hi) { 1202 DebugLoc dl = N->getDebugLoc(); 1203 // Expand the subcomponents. 1204 SDValue LHSL, LHSH, RHSL, RHSH; 1205 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1206 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1207 1208 MVT NVT = LHSL.getValueType(); 1209 SDValue LoOps[2] = { LHSL, RHSL }; 1210 SDValue HiOps[3] = { LHSH, RHSH }; 1211 1212 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1213 // them. TODO: Teach operation legalization how to expand unsupported 1214 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1215 // a carry of type MVT::Flag, but there doesn't seem to be any way to 1216 // generate a value of this type in the expanded code sequence. 1217 bool hasCarry = 1218 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? 1219 ISD::ADDC : ISD::SUBC, 1220 TLI.getTypeToExpandTo(NVT)); 1221 1222 if (hasCarry) { 1223 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1224 if (N->getOpcode() == ISD::ADD) { 1225 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1226 HiOps[2] = Lo.getValue(1); 1227 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1228 } else { 1229 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1230 HiOps[2] = Lo.getValue(1); 1231 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1232 } 1233 } else { 1234 if (N->getOpcode() == ISD::ADD) { 1235 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); 1236 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); 1237 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0], 1238 ISD::SETULT); 1239 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1, 1240 DAG.getConstant(1, NVT), 1241 DAG.getConstant(0, NVT)); 1242 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1], 1243 ISD::SETULT); 1244 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2, 1245 DAG.getConstant(1, NVT), Carry1); 1246 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); 1247 } else { 1248 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); 1249 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); 1250 SDValue Cmp = 1251 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()), 1252 LoOps[0], LoOps[1], ISD::SETULT); 1253 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, 1254 DAG.getConstant(1, NVT), 1255 DAG.getConstant(0, NVT)); 1256 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); 1257 } 1258 } 1259} 1260 1261void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1262 SDValue &Lo, SDValue &Hi) { 1263 // Expand the subcomponents. 1264 SDValue LHSL, LHSH, RHSL, RHSH; 1265 DebugLoc dl = N->getDebugLoc(); 1266 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1267 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1268 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1269 SDValue LoOps[2] = { LHSL, RHSL }; 1270 SDValue HiOps[3] = { LHSH, RHSH }; 1271 1272 if (N->getOpcode() == ISD::ADDC) { 1273 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1274 HiOps[2] = Lo.getValue(1); 1275 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1276 } else { 1277 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1278 HiOps[2] = Lo.getValue(1); 1279 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1280 } 1281 1282 // Legalized the flag result - switch anything that used the old flag to 1283 // use the new one. 1284 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1285} 1286 1287void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1288 SDValue &Lo, SDValue &Hi) { 1289 // Expand the subcomponents. 1290 SDValue LHSL, LHSH, RHSL, RHSH; 1291 DebugLoc dl = N->getDebugLoc(); 1292 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1293 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1294 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1295 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1296 SDValue HiOps[3] = { LHSH, RHSH }; 1297 1298 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3); 1299 HiOps[2] = Lo.getValue(1); 1300 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); 1301 1302 // Legalized the flag result - switch anything that used the old flag to 1303 // use the new one. 1304 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1305} 1306 1307void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1308 SDValue &Lo, SDValue &Hi) { 1309 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1310 DebugLoc dl = N->getDebugLoc(); 1311 SDValue Op = N->getOperand(0); 1312 if (Op.getValueType().bitsLE(NVT)) { 1313 // The low part is any extension of the input (which degenerates to a copy). 1314 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op); 1315 Hi = DAG.getNode(ISD::UNDEF, dl, NVT); // The high part is undefined. 1316 } else { 1317 // For example, extension of an i48 to an i64. The operand type necessarily 1318 // promotes to the result type, so will end up being expanded too. 1319 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1320 "Only know how to promote this result!"); 1321 SDValue Res = GetPromotedInteger(Op); 1322 assert(Res.getValueType() == N->getValueType(0) && 1323 "Operand over promoted?"); 1324 // Split the promoted operand. This will simplify when it is expanded. 1325 SplitInteger(Res, Lo, Hi); 1326 } 1327} 1328 1329void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1330 SDValue &Lo, SDValue &Hi) { 1331 DebugLoc dl = N->getDebugLoc(); 1332 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1333 MVT NVT = Lo.getValueType(); 1334 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1335 unsigned NVTBits = NVT.getSizeInBits(); 1336 unsigned EVTBits = EVT.getSizeInBits(); 1337 1338 if (NVTBits < EVTBits) { 1339 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, 1340 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1341 } else { 1342 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); 1343 // The high part replicates the sign bit of Lo, make it explicit. 1344 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1345 DAG.getConstant(NVTBits-1, TLI.getPointerTy())); 1346 } 1347} 1348 1349void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1350 SDValue &Lo, SDValue &Hi) { 1351 DebugLoc dl = N->getDebugLoc(); 1352 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1353 MVT NVT = Lo.getValueType(); 1354 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1355 unsigned NVTBits = NVT.getSizeInBits(); 1356 unsigned EVTBits = EVT.getSizeInBits(); 1357 1358 if (NVTBits < EVTBits) { 1359 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, 1360 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1361 } else { 1362 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); 1363 // The high part must be zero, make it explicit. 1364 Hi = DAG.getConstant(0, NVT); 1365 } 1366} 1367 1368void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1369 SDValue &Lo, SDValue &Hi) { 1370 DebugLoc dl = N->getDebugLoc(); 1371 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1372 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo); 1373 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi); 1374} 1375 1376void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1377 SDValue &Lo, SDValue &Hi) { 1378 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1379 unsigned NBitWidth = NVT.getSizeInBits(); 1380 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1381 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 1382 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1383} 1384 1385void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1386 SDValue &Lo, SDValue &Hi) { 1387 DebugLoc dl = N->getDebugLoc(); 1388 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1389 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1390 MVT NVT = Lo.getValueType(); 1391 1392 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi, 1393 DAG.getConstant(0, NVT), ISD::SETNE); 1394 1395 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo); 1396 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi); 1397 1398 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ, 1399 DAG.getNode(ISD::ADD, dl, NVT, LoLZ, 1400 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1401 Hi = DAG.getConstant(0, NVT); 1402} 1403 1404void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1405 SDValue &Lo, SDValue &Hi) { 1406 DebugLoc dl = N->getDebugLoc(); 1407 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1408 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1409 MVT NVT = Lo.getValueType(); 1410 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), 1411 DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); 1412 Hi = DAG.getConstant(0, NVT); 1413} 1414 1415void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1416 SDValue &Lo, SDValue &Hi) { 1417 DebugLoc dl = N->getDebugLoc(); 1418 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1419 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1420 MVT NVT = Lo.getValueType(); 1421 1422 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, 1423 DAG.getConstant(0, NVT), ISD::SETNE); 1424 1425 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo); 1426 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi); 1427 1428 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ, 1429 DAG.getNode(ISD::ADD, dl, NVT, HiLZ, 1430 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1431 Hi = DAG.getConstant(0, NVT); 1432} 1433 1434void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1435 SDValue &Hi) { 1436 DebugLoc dl = N->getDebugLoc(); 1437 MVT VT = N->getValueType(0); 1438 SDValue Op = N->getOperand(0); 1439 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1440 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1441 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi); 1442} 1443 1444void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1445 SDValue &Hi) { 1446 DebugLoc dl = N->getDebugLoc(); 1447 MVT VT = N->getValueType(0); 1448 SDValue Op = N->getOperand(0); 1449 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1450 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1451 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi); 1452} 1453 1454void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1455 SDValue &Lo, SDValue &Hi) { 1456 if (ISD::isNormalLoad(N)) { 1457 ExpandRes_NormalLoad(N, Lo, Hi); 1458 return; 1459 } 1460 1461 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1462 1463 MVT VT = N->getValueType(0); 1464 MVT NVT = TLI.getTypeToTransformTo(VT); 1465 SDValue Ch = N->getChain(); 1466 SDValue Ptr = N->getBasePtr(); 1467 ISD::LoadExtType ExtType = N->getExtensionType(); 1468 int SVOffset = N->getSrcValueOffset(); 1469 unsigned Alignment = N->getAlignment(); 1470 bool isVolatile = N->isVolatile(); 1471 DebugLoc dl = N->getDebugLoc(); 1472 1473 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1474 1475 if (N->getMemoryVT().bitsLE(NVT)) { 1476 MVT EVT = N->getMemoryVT(); 1477 1478 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1479 EVT, isVolatile, Alignment); 1480 1481 // Remember the chain. 1482 Ch = Lo.getValue(1); 1483 1484 if (ExtType == ISD::SEXTLOAD) { 1485 // The high part is obtained by SRA'ing all but one of the bits of the 1486 // lo part. 1487 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1488 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1489 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1490 } else if (ExtType == ISD::ZEXTLOAD) { 1491 // The high part is just a zero. 1492 Hi = DAG.getConstant(0, NVT); 1493 } else { 1494 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1495 // The high part is undefined. 1496 Hi = DAG.getNode(ISD::UNDEF, dl, NVT); 1497 } 1498 } else if (TLI.isLittleEndian()) { 1499 // Little-endian - low bits are at low addresses. 1500 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset, 1501 isVolatile, Alignment); 1502 1503 unsigned ExcessBits = 1504 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1505 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1506 1507 // Increment the pointer to the other half. 1508 unsigned IncrementSize = NVT.getSizeInBits()/8; 1509 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1510 DAG.getIntPtrConstant(IncrementSize)); 1511 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), 1512 SVOffset+IncrementSize, NEVT, 1513 isVolatile, MinAlign(Alignment, IncrementSize)); 1514 1515 // Build a factor node to remember that this load is independent of the 1516 // other one. 1517 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1518 Hi.getValue(1)); 1519 } else { 1520 // Big-endian - high bits are at low addresses. Favor aligned loads at 1521 // the cost of some bit-fiddling. 1522 MVT EVT = N->getMemoryVT(); 1523 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1524 unsigned IncrementSize = NVT.getSizeInBits()/8; 1525 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1526 1527 // Load both the high bits and maybe some of the low bits. 1528 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1529 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), 1530 isVolatile, Alignment); 1531 1532 // Increment the pointer to the other half. 1533 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1534 DAG.getIntPtrConstant(IncrementSize)); 1535 // Load the rest of the low bits. 1536 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(), 1537 SVOffset+IncrementSize, 1538 MVT::getIntegerVT(ExcessBits), 1539 isVolatile, MinAlign(Alignment, IncrementSize)); 1540 1541 // Build a factor node to remember that this load is independent of the 1542 // other one. 1543 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1544 Hi.getValue(1)); 1545 1546 if (ExcessBits < NVT.getSizeInBits()) { 1547 // Transfer low bits from the bottom of Hi to the top of Lo. 1548 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, 1549 DAG.getNode(ISD::SHL, dl, NVT, Hi, 1550 DAG.getConstant(ExcessBits, 1551 TLI.getPointerTy()))); 1552 // Move high bits to the right position in Hi. 1553 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, 1554 NVT, Hi, 1555 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1556 TLI.getPointerTy())); 1557 } 1558 } 1559 1560 // Legalized the chain result - switch anything that used the old chain to 1561 // use the new one. 1562 ReplaceValueWith(SDValue(N, 1), Ch); 1563} 1564 1565void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1566 SDValue &Lo, SDValue &Hi) { 1567 DebugLoc dl = N->getDebugLoc(); 1568 SDValue LL, LH, RL, RH; 1569 GetExpandedInteger(N->getOperand(0), LL, LH); 1570 GetExpandedInteger(N->getOperand(1), RL, RH); 1571 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL); 1572 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); 1573} 1574 1575void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1576 SDValue &Lo, SDValue &Hi) { 1577 MVT VT = N->getValueType(0); 1578 MVT NVT = TLI.getTypeToTransformTo(VT); 1579 DebugLoc dl = N->getDebugLoc(); 1580 1581 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); 1582 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); 1583 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); 1584 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); 1585 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1586 SDValue LL, LH, RL, RH; 1587 GetExpandedInteger(N->getOperand(0), LL, LH); 1588 GetExpandedInteger(N->getOperand(1), RL, RH); 1589 unsigned OuterBitSize = VT.getSizeInBits(); 1590 unsigned InnerBitSize = NVT.getSizeInBits(); 1591 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1592 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1593 1594 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1595 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1596 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1597 // The inputs are both zero-extended. 1598 if (HasUMUL_LOHI) { 1599 // We can emit a umul_lohi. 1600 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1601 Hi = SDValue(Lo.getNode(), 1); 1602 return; 1603 } 1604 if (HasMULHU) { 1605 // We can emit a mulhu+mul. 1606 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1607 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1608 return; 1609 } 1610 } 1611 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1612 // The input values are both sign-extended. 1613 if (HasSMUL_LOHI) { 1614 // We can emit a smul_lohi. 1615 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1616 Hi = SDValue(Lo.getNode(), 1); 1617 return; 1618 } 1619 if (HasMULHS) { 1620 // We can emit a mulhs+mul. 1621 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1622 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); 1623 return; 1624 } 1625 } 1626 if (HasUMUL_LOHI) { 1627 // Lo,Hi = umul LHS, RHS. 1628 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, 1629 DAG.getVTList(NVT, NVT), LL, RL); 1630 Lo = UMulLOHI; 1631 Hi = UMulLOHI.getValue(1); 1632 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1633 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1634 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1635 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1636 return; 1637 } 1638 if (HasMULHU) { 1639 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1640 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1641 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1642 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1643 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1644 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1645 return; 1646 } 1647 } 1648 1649 // If nothing else, we can make a libcall. 1650 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1651 if (VT == MVT::i16) 1652 LC = RTLIB::MUL_I16; 1653 else if (VT == MVT::i32) 1654 LC = RTLIB::MUL_I32; 1655 else if (VT == MVT::i64) 1656 LC = RTLIB::MUL_I64; 1657 else if (VT == MVT::i128) 1658 LC = RTLIB::MUL_I128; 1659 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1660 1661 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1662 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi); 1663} 1664 1665void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1666 SDValue &Lo, SDValue &Hi) { 1667 MVT VT = N->getValueType(0); 1668 DebugLoc dl = N->getDebugLoc(); 1669 1670 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1671 if (VT == MVT::i32) 1672 LC = RTLIB::SDIV_I32; 1673 else if (VT == MVT::i64) 1674 LC = RTLIB::SDIV_I64; 1675 else if (VT == MVT::i128) 1676 LC = RTLIB::SDIV_I128; 1677 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1678 1679 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1680 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1681} 1682 1683void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1684 SDValue &Lo, SDValue &Hi) { 1685 MVT VT = N->getValueType(0); 1686 DebugLoc dl = N->getDebugLoc(); 1687 1688 // If we can emit an efficient shift operation, do so now. Check to see if 1689 // the RHS is a constant. 1690 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1691 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1692 1693 // If we can determine that the high bit of the shift is zero or one, even if 1694 // the low bits are variable, emit this shift in an optimized form. 1695 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1696 return; 1697 1698 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1699 unsigned PartsOpc; 1700 if (N->getOpcode() == ISD::SHL) { 1701 PartsOpc = ISD::SHL_PARTS; 1702 } else if (N->getOpcode() == ISD::SRL) { 1703 PartsOpc = ISD::SRL_PARTS; 1704 } else { 1705 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1706 PartsOpc = ISD::SRA_PARTS; 1707 } 1708 1709 // Next check to see if the target supports this SHL_PARTS operation or if it 1710 // will custom expand it. 1711 MVT NVT = TLI.getTypeToTransformTo(VT); 1712 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1713 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1714 Action == TargetLowering::Custom) { 1715 // Expand the subcomponents. 1716 SDValue LHSL, LHSH; 1717 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1718 1719 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1720 MVT VT = LHSL.getValueType(); 1721 Lo = DAG.getNode(PartsOpc, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 1722 Hi = Lo.getValue(1); 1723 return; 1724 } 1725 1726 // Otherwise, emit a libcall. 1727 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1728 bool isSigned; 1729 if (N->getOpcode() == ISD::SHL) { 1730 isSigned = false; /*sign irrelevant*/ 1731 if (VT == MVT::i16) 1732 LC = RTLIB::SHL_I16; 1733 else if (VT == MVT::i32) 1734 LC = RTLIB::SHL_I32; 1735 else if (VT == MVT::i64) 1736 LC = RTLIB::SHL_I64; 1737 else if (VT == MVT::i128) 1738 LC = RTLIB::SHL_I128; 1739 } else if (N->getOpcode() == ISD::SRL) { 1740 isSigned = false; 1741 if (VT == MVT::i16) 1742 LC = RTLIB::SRL_I16; 1743 else if (VT == MVT::i32) 1744 LC = RTLIB::SRL_I32; 1745 else if (VT == MVT::i64) 1746 LC = RTLIB::SRL_I64; 1747 else if (VT == MVT::i128) 1748 LC = RTLIB::SRL_I128; 1749 } else { 1750 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1751 isSigned = true; 1752 if (VT == MVT::i16) 1753 LC = RTLIB::SRA_I16; 1754 else if (VT == MVT::i32) 1755 LC = RTLIB::SRA_I32; 1756 else if (VT == MVT::i64) 1757 LC = RTLIB::SRA_I64; 1758 else if (VT == MVT::i128) 1759 LC = RTLIB::SRA_I128; 1760 } 1761 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!"); 1762 1763 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1764 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi); 1765} 1766 1767void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 1768 SDValue &Lo, SDValue &Hi) { 1769 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1770 DebugLoc dl = N->getDebugLoc(); 1771 SDValue Op = N->getOperand(0); 1772 if (Op.getValueType().bitsLE(NVT)) { 1773 // The low part is sign extension of the input (degenerates to a copy). 1774 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); 1775 // The high part is obtained by SRA'ing all but one of the bits of low part. 1776 unsigned LoSize = NVT.getSizeInBits(); 1777 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1778 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1779 } else { 1780 // For example, extension of an i48 to an i64. The operand type necessarily 1781 // promotes to the result type, so will end up being expanded too. 1782 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1783 "Only know how to promote this result!"); 1784 SDValue Res = GetPromotedInteger(Op); 1785 assert(Res.getValueType() == N->getValueType(0) && 1786 "Operand over promoted?"); 1787 // Split the promoted operand. This will simplify when it is expanded. 1788 SplitInteger(Res, Lo, Hi); 1789 unsigned ExcessBits = 1790 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1791 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 1792 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1793 } 1794} 1795 1796void DAGTypeLegalizer:: 1797ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 1798 DebugLoc dl = N->getDebugLoc(); 1799 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1800 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1801 1802 if (EVT.bitsLE(Lo.getValueType())) { 1803 // sext_inreg the low part if needed. 1804 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, 1805 N->getOperand(1)); 1806 1807 // The high part gets the sign extension from the lo-part. This handles 1808 // things like sextinreg V:i64 from i8. 1809 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo, 1810 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 1811 TLI.getPointerTy())); 1812 } else { 1813 // For example, extension of an i48 to an i64. Leave the low part alone, 1814 // sext_inreg the high part. 1815 unsigned ExcessBits = 1816 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 1817 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 1818 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1819 } 1820} 1821 1822void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1823 SDValue &Lo, SDValue &Hi) { 1824 MVT VT = N->getValueType(0); 1825 DebugLoc dl = N->getDebugLoc(); 1826 1827 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1828 if (VT == MVT::i32) 1829 LC = RTLIB::SREM_I32; 1830 else if (VT == MVT::i64) 1831 LC = RTLIB::SREM_I64; 1832 else if (VT == MVT::i128) 1833 LC = RTLIB::SREM_I128; 1834 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1835 1836 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1837 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1838} 1839 1840void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 1841 SDValue &Lo, SDValue &Hi) { 1842 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1843 DebugLoc dl = N->getDebugLoc(); 1844 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); 1845 Hi = DAG.getNode(ISD::SRL, dl, 1846 N->getOperand(0).getValueType(), N->getOperand(0), 1847 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy())); 1848 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); 1849} 1850 1851void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1852 SDValue &Lo, SDValue &Hi) { 1853 MVT VT = N->getValueType(0); 1854 DebugLoc dl = N->getDebugLoc(); 1855 1856 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1857 if (VT == MVT::i32) 1858 LC = RTLIB::UDIV_I32; 1859 else if (VT == MVT::i64) 1860 LC = RTLIB::UDIV_I64; 1861 else if (VT == MVT::i128) 1862 LC = RTLIB::UDIV_I128; 1863 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 1864 1865 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1866 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 1867} 1868 1869void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 1870 SDValue &Lo, SDValue &Hi) { 1871 MVT VT = N->getValueType(0); 1872 DebugLoc dl = N->getDebugLoc(); 1873 1874 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1875 if (VT == MVT::i32) 1876 LC = RTLIB::UREM_I32; 1877 else if (VT == MVT::i64) 1878 LC = RTLIB::UREM_I64; 1879 else if (VT == MVT::i128) 1880 LC = RTLIB::UREM_I128; 1881 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 1882 1883 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1884 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 1885} 1886 1887void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 1888 SDValue &Lo, SDValue &Hi) { 1889 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1890 DebugLoc dl = N->getDebugLoc(); 1891 SDValue Op = N->getOperand(0); 1892 if (Op.getValueType().bitsLE(NVT)) { 1893 // The low part is zero extension of the input (degenerates to a copy). 1894 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); 1895 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 1896 } else { 1897 // For example, extension of an i48 to an i64. The operand type necessarily 1898 // promotes to the result type, so will end up being expanded too. 1899 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1900 "Only know how to promote this result!"); 1901 SDValue Res = GetPromotedInteger(Op); 1902 assert(Res.getValueType() == N->getValueType(0) && 1903 "Operand over promoted?"); 1904 // Split the promoted operand. This will simplify when it is expanded. 1905 SplitInteger(Res, Lo, Hi); 1906 unsigned ExcessBits = 1907 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1908 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); 1909 } 1910} 1911 1912 1913//===----------------------------------------------------------------------===// 1914// Integer Operand Expansion 1915//===----------------------------------------------------------------------===// 1916 1917/// ExpandIntegerOperand - This method is called when the specified operand of 1918/// the specified node is found to need expansion. At this point, all of the 1919/// result types of the node are known to be legal, but other operands of the 1920/// node may need promotion or expansion as well as the specified one. 1921bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 1922 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n"); 1923 SDValue Res = SDValue(); 1924 1925 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false)) 1926 return false; 1927 1928 switch (N->getOpcode()) { 1929 default: 1930 #ifndef NDEBUG 1931 cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; 1932 N->dump(&DAG); cerr << "\n"; 1933 #endif 1934 assert(0 && "Do not know how to expand this operator's operand!"); 1935 abort(); 1936 1937 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 1938 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 1939 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 1940 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 1941 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 1942 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; 1943 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 1944 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 1945 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 1946 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break; 1947 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 1948 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 1949 1950 case ISD::SHL: 1951 case ISD::SRA: 1952 case ISD::SRL: 1953 case ISD::ROTL: 1954 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break; 1955 } 1956 1957 // If the result is null, the sub-method took care of registering results etc. 1958 if (!Res.getNode()) return false; 1959 1960 // If the result is N, the sub-method updated N in place. Tell the legalizer 1961 // core about this. 1962 if (Res.getNode() == N) 1963 return true; 1964 1965 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1966 "Invalid operand expansion"); 1967 1968 ReplaceValueWith(SDValue(N, 0), Res); 1969 return false; 1970} 1971 1972/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 1973/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1974void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 1975 SDValue &NewRHS, 1976 ISD::CondCode &CCCode, 1977 DebugLoc dl) { 1978 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 1979 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 1980 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 1981 1982 MVT VT = NewLHS.getValueType(); 1983 1984 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 1985 if (RHSLo == RHSHi) { 1986 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 1987 if (RHSCST->isAllOnesValue()) { 1988 // Equality comparison to -1. 1989 NewLHS = DAG.getNode(ISD::AND, dl, 1990 LHSLo.getValueType(), LHSLo, LHSHi); 1991 NewRHS = RHSLo; 1992 return; 1993 } 1994 } 1995 } 1996 1997 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); 1998 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); 1999 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS); 2000 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2001 return; 2002 } 2003 2004 // If this is a comparison of the sign bit, just look at the top part. 2005 // X > -1, x < 0 2006 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 2007 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 2008 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 2009 NewLHS = LHSHi; 2010 NewRHS = RHSHi; 2011 return; 2012 } 2013 2014 // FIXME: This generated code sucks. 2015 ISD::CondCode LowCC; 2016 switch (CCCode) { 2017 default: assert(0 && "Unknown integer setcc!"); 2018 case ISD::SETLT: 2019 case ISD::SETULT: LowCC = ISD::SETULT; break; 2020 case ISD::SETGT: 2021 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2022 case ISD::SETLE: 2023 case ISD::SETULE: LowCC = ISD::SETULE; break; 2024 case ISD::SETGE: 2025 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2026 } 2027 2028 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2029 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2030 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2031 2032 // NOTE: on targets without efficient SELECT of bools, we can always use 2033 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2034 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 2035 SDValue Tmp1, Tmp2; 2036 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), 2037 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl); 2038 if (!Tmp1.getNode()) 2039 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 2040 LHSLo, RHSLo, LowCC); 2041 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2042 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl); 2043 if (!Tmp2.getNode()) 2044 Tmp2 = DAG.getNode(ISD::SETCC, dl, 2045 TLI.getSetCCResultType(LHSHi.getValueType()), 2046 LHSHi, RHSHi, DAG.getCondCode(CCCode)); 2047 2048 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2049 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2050 if ((Tmp1C && Tmp1C->isNullValue()) || 2051 (Tmp2C && Tmp2C->isNullValue() && 2052 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2053 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2054 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2055 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2056 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2057 // low part is known false, returns high part. 2058 // For LE / GE, if high part is known false, ignore the low part. 2059 // For LT / GT, if high part is known true, ignore the low part. 2060 NewLHS = Tmp2; 2061 NewRHS = SDValue(); 2062 return; 2063 } 2064 2065 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2066 LHSHi, RHSHi, ISD::SETEQ, false, 2067 DagCombineInfo, dl); 2068 if (!NewLHS.getNode()) 2069 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 2070 LHSHi, RHSHi, ISD::SETEQ); 2071 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), 2072 NewLHS, Tmp1, Tmp2); 2073 NewRHS = SDValue(); 2074} 2075 2076SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2077 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2078 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2079 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2080 2081 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2082 // against zero to select between true and false values. 2083 if (NewRHS.getNode() == 0) { 2084 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2085 CCCode = ISD::SETNE; 2086 } 2087 2088 // Update N to have the operands specified. 2089 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 2090 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2091 N->getOperand(4)); 2092} 2093 2094SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2095 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2096 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2097 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2098 2099 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2100 // against zero to select between true and false values. 2101 if (NewRHS.getNode() == 0) { 2102 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2103 CCCode = ISD::SETNE; 2104 } 2105 2106 // Update N to have the operands specified. 2107 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2108 N->getOperand(2), N->getOperand(3), 2109 DAG.getCondCode(CCCode)); 2110} 2111 2112SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2113 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2114 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2115 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2116 2117 // If ExpandSetCCOperands returned a scalar, use it. 2118 if (NewRHS.getNode() == 0) { 2119 assert(NewLHS.getValueType() == N->getValueType(0) && 2120 "Unexpected setcc expansion!"); 2121 return NewLHS; 2122 } 2123 2124 // Otherwise, update N to have the operands specified. 2125 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2126 DAG.getCondCode(CCCode)); 2127} 2128 2129SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) { 2130 // The value being shifted is legal, but the shift amount is too big. 2131 // It follows that either the result of the shift is undefined, or the 2132 // upper half of the shift amount is zero. Just use the lower half. 2133 SDValue Lo, Hi; 2134 GetExpandedInteger(N->getOperand(1), Lo, Hi); 2135 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo); 2136} 2137 2138SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2139 SDValue Op = N->getOperand(0); 2140 MVT DstVT = N->getValueType(0); 2141 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2142 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2143 "Don't know how to expand this SINT_TO_FP!"); 2144 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc()); 2145} 2146 2147SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2148 if (ISD::isNormalStore(N)) 2149 return ExpandOp_NormalStore(N, OpNo); 2150 2151 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2152 assert(OpNo == 1 && "Can only expand the stored value so far"); 2153 2154 MVT VT = N->getOperand(1).getValueType(); 2155 MVT NVT = TLI.getTypeToTransformTo(VT); 2156 SDValue Ch = N->getChain(); 2157 SDValue Ptr = N->getBasePtr(); 2158 int SVOffset = N->getSrcValueOffset(); 2159 unsigned Alignment = N->getAlignment(); 2160 bool isVolatile = N->isVolatile(); 2161 DebugLoc dl = N->getDebugLoc(); 2162 SDValue Lo, Hi; 2163 2164 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2165 2166 if (N->getMemoryVT().bitsLE(NVT)) { 2167 GetExpandedInteger(N->getValue(), Lo, Hi); 2168 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, 2169 N->getMemoryVT(), isVolatile, Alignment); 2170 } else if (TLI.isLittleEndian()) { 2171 // Little-endian - low bits are at low addresses. 2172 GetExpandedInteger(N->getValue(), Lo, Hi); 2173 2174 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, 2175 isVolatile, Alignment); 2176 2177 unsigned ExcessBits = 2178 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2179 MVT NEVT = MVT::getIntegerVT(ExcessBits); 2180 2181 // Increment the pointer to the other half. 2182 unsigned IncrementSize = NVT.getSizeInBits()/8; 2183 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2184 DAG.getIntPtrConstant(IncrementSize)); 2185 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), 2186 SVOffset+IncrementSize, NEVT, 2187 isVolatile, MinAlign(Alignment, IncrementSize)); 2188 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2189 } else { 2190 // Big-endian - high bits are at low addresses. Favor aligned stores at 2191 // the cost of some bit-fiddling. 2192 GetExpandedInteger(N->getValue(), Lo, Hi); 2193 2194 MVT EVT = N->getMemoryVT(); 2195 unsigned EBytes = EVT.getStoreSizeInBits()/8; 2196 unsigned IncrementSize = NVT.getSizeInBits()/8; 2197 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2198 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); 2199 2200 if (ExcessBits < NVT.getSizeInBits()) { 2201 // Transfer high bits from the top of Lo to the bottom of Hi. 2202 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, 2203 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2204 TLI.getPointerTy())); 2205 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, 2206 DAG.getNode(ISD::SRL, NVT, Lo, 2207 DAG.getConstant(ExcessBits, 2208 TLI.getPointerTy()))); 2209 } 2210 2211 // Store both the high bits and maybe some of the low bits. 2212 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), 2213 SVOffset, HiVT, isVolatile, Alignment); 2214 2215 // Increment the pointer to the other half. 2216 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2217 DAG.getIntPtrConstant(IncrementSize)); 2218 // Store the lowest ExcessBits bits in the second half. 2219 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), 2220 SVOffset+IncrementSize, 2221 MVT::getIntegerVT(ExcessBits), 2222 isVolatile, MinAlign(Alignment, IncrementSize)); 2223 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2224 } 2225} 2226 2227SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2228 SDValue InL, InH; 2229 GetExpandedInteger(N->getOperand(0), InL, InH); 2230 // Just truncate the low part of the source. 2231 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL); 2232} 2233 2234SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2235 SDValue Op = N->getOperand(0); 2236 MVT SrcVT = Op.getValueType(); 2237 MVT DstVT = N->getValueType(0); 2238 DebugLoc dl = N->getDebugLoc(); 2239 2240 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2241 // Do a signed conversion then adjust the result. 2242 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); 2243 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2244 2245 // The result of the signed conversion needs adjusting if the 'sign bit' of 2246 // the incoming integer was set. To handle this, we dynamically test to see 2247 // if it is set, and, if so, add a fudge factor. 2248 2249 const uint64_t F32TwoE32 = 0x4F800000ULL; 2250 const uint64_t F32TwoE64 = 0x5F800000ULL; 2251 const uint64_t F32TwoE128 = 0x7F800000ULL; 2252 2253 APInt FF(32, 0); 2254 if (SrcVT == MVT::i32) 2255 FF = APInt(32, F32TwoE32); 2256 else if (SrcVT == MVT::i64) 2257 FF = APInt(32, F32TwoE64); 2258 else if (SrcVT == MVT::i128) 2259 FF = APInt(32, F32TwoE128); 2260 else 2261 assert(false && "Unsupported UINT_TO_FP!"); 2262 2263 // Check whether the sign bit is set. 2264 SDValue Lo, Hi; 2265 GetExpandedInteger(Op, Lo, Hi); 2266 SDValue SignSet = DAG.getSetCC(dl, 2267 TLI.getSetCCResultType(Hi.getValueType()), 2268 Hi, DAG.getConstant(0, Hi.getValueType()), 2269 ISD::SETLT); 2270 2271 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2272 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)), 2273 TLI.getPointerTy()); 2274 2275 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2276 SDValue Zero = DAG.getIntPtrConstant(0); 2277 SDValue Four = DAG.getIntPtrConstant(4); 2278 if (TLI.isBigEndian()) std::swap(Zero, Four); 2279 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 2280 Zero, Four); 2281 unsigned Alignment = 2282 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2283 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset); 2284 Alignment = std::min(Alignment, 4u); 2285 2286 // Load the value out, extending it from f32 to the destination float type. 2287 // FIXME: Avoid the extend by constructing the right constant pool? 2288 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), 2289 FudgePtr, NULL, 0, MVT::f32, 2290 false, Alignment); 2291 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); 2292 } 2293 2294 // Otherwise, use a libcall. 2295 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2296 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2297 "Don't know how to expand this UINT_TO_FP!"); 2298 return MakeLibCall(LC, DstVT, &Op, 1, true, dl); 2299} 2300