LegalizeIntegerTypes.cpp revision cef41b324c8fe02da3e6232762aac79a4b893f8b
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22using namespace llvm; 23 24//===----------------------------------------------------------------------===// 25// Integer Result Promotion 26//===----------------------------------------------------------------------===// 27 28/// PromoteIntegerResult - This method is called when a result of a node is 29/// found to be in need of promotion to a larger type. At this point, the node 30/// may also have invalid operands or may have other results that need 31/// expansion, we just know that (at least) one result needs promotion. 32void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n"); 34 SDOperand Result = SDOperand(); 35 36 // See if the target wants to custom expand this node. 37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 38 TargetLowering::Custom) { 39 // If the target wants to, allow it to lower this itself. 40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 41 // Everything that once used N now uses P. We are guaranteed that the 42 // result value types of N and the result value types of P match. 43 ReplaceNodeWith(N, P); 44 return; 45 } 46 } 47 48 switch (N->getOpcode()) { 49 default: 50#ifndef NDEBUG 51 cerr << "PromoteIntegerResult #" << ResNo << ": "; 52 N->dump(&DAG); cerr << "\n"; 53#endif 54 assert(0 && "Do not know how to promote this operator!"); 55 abort(); 56 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break; 57 case ISD::Constant: Result = PromoteIntRes_Constant(N); break; 58 59 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break; 60 case ISD::SIGN_EXTEND: 61 case ISD::ZERO_EXTEND: 62 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break; 63 case ISD::FP_ROUND: Result = PromoteIntRes_FP_ROUND(N); break; 64 case ISD::FP_TO_SINT: 65 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break; 66 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break; 67 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break; 68 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break; 69 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break; 70 71 case ISD::AND: 72 case ISD::OR: 73 case ISD::XOR: 74 case ISD::ADD: 75 case ISD::SUB: 76 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break; 77 78 case ISD::SDIV: 79 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break; 80 81 case ISD::UDIV: 82 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break; 83 84 case ISD::SHL: Result = PromoteIntRes_SHL(N); break; 85 case ISD::SRA: Result = PromoteIntRes_SRA(N); break; 86 case ISD::SRL: Result = PromoteIntRes_SRL(N); break; 87 88 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break; 89 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break; 90 91 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break; 92 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break; 93 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break; 94 95 case ISD::EXTRACT_VECTOR_ELT: 96 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); 97 break; 98 99 case ISD::VAARG : Result = PromoteIntRes_VAARG(N); break; 100 } 101 102 // If Result is null, the sub-method took care of registering the result. 103 if (Result.Val) 104 SetPromotedInteger(SDOperand(N, ResNo), Result); 105} 106 107SDOperand DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 108 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0))); 109} 110 111SDOperand DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 112 MVT VT = N->getValueType(0); 113 // Zero extend things like i1, sign extend everything else. It shouldn't 114 // matter in theory which one we pick, but this tends to give better code? 115 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 116 SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), 117 SDOperand(N, 0)); 118 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 119 return Result; 120} 121 122SDOperand DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 123 SDOperand Res; 124 125 switch (getTypeAction(N->getOperand(0).getValueType())) { 126 default: assert(0 && "Unknown type action!"); 127 case Legal: 128 case ExpandInteger: 129 Res = N->getOperand(0); 130 break; 131 case PromoteInteger: 132 Res = GetPromotedInteger(N->getOperand(0)); 133 break; 134 } 135 136 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 137 assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() && 138 "Truncation doesn't make sense!"); 139 if (Res.getValueType() == NVT) 140 return Res; 141 142 // Truncate to NVT instead of VT 143 return DAG.getNode(ISD::TRUNCATE, NVT, Res); 144} 145 146SDOperand DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 147 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 148 149 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 150 SDOperand Res = GetPromotedInteger(N->getOperand(0)); 151 assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() && 152 "Extension doesn't make sense!"); 153 154 // If the result and operand types are the same after promotion, simplify 155 // to an in-register extension. 156 if (NVT == Res.getValueType()) { 157 // The high bits are not guaranteed to be anything. Insert an extend. 158 if (N->getOpcode() == ISD::SIGN_EXTEND) 159 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, 160 DAG.getValueType(N->getOperand(0).getValueType())); 161 if (N->getOpcode() == ISD::ZERO_EXTEND) 162 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); 163 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 164 return Res; 165 } 166 } 167 168 // Otherwise, just extend the original operand all the way to the larger type. 169 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0)); 170} 171 172SDOperand DAGTypeLegalizer::PromoteIntRes_FP_ROUND(SDNode *N) { 173 // NOTE: Assumes input is legal. 174 if (N->getConstantOperandVal(1) == 0) 175 return DAG.getNode(ISD::FP_ROUND_INREG, N->getOperand(0).getValueType(), 176 N->getOperand(0), DAG.getValueType(N->getValueType(0))); 177 // If the precision discard isn't needed, just return the operand unrounded. 178 return N->getOperand(0); 179} 180 181SDOperand DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 182 unsigned NewOpc = N->getOpcode(); 183 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 184 185 // If we're promoting a UINT to a larger size, check to see if the new node 186 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 187 // we can use that instead. This allows us to generate better code for 188 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 189 // legal, such as PowerPC. 190 if (N->getOpcode() == ISD::FP_TO_UINT) { 191 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 192 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 193 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)) 194 NewOpc = ISD::FP_TO_SINT; 195 } 196 197 return DAG.getNode(NewOpc, NVT, N->getOperand(0)); 198} 199 200SDOperand DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 201 assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0))) 202 && "SetCC type is not legal??"); 203 return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)), 204 N->getOperand(0), N->getOperand(1), N->getOperand(2)); 205} 206 207SDOperand DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 208 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 209 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 210 ISD::LoadExtType ExtType = 211 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 212 SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(), 213 N->getSrcValue(), N->getSrcValueOffset(), 214 N->getMemoryVT(), N->isVolatile(), 215 N->getAlignment()); 216 217 // Legalized the chain result - switch anything that used the old chain to 218 // use the new one. 219 ReplaceValueWith(SDOperand(N, 1), Res.getValue(1)); 220 return Res; 221} 222 223SDOperand DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 224 // The pair element type may be legal, or may not promote to the same type as 225 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 226 return DAG.getNode(ISD::ANY_EXTEND, 227 TLI.getTypeToTransformTo(N->getValueType(0)), 228 JoinIntegers(N->getOperand(0), N->getOperand(1))); 229} 230 231SDOperand DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 232 SDOperand InOp = N->getOperand(0); 233 MVT InVT = InOp.getValueType(); 234 MVT NInVT = TLI.getTypeToTransformTo(InVT); 235 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 236 237 switch (getTypeAction(InVT)) { 238 default: 239 assert(false && "Unknown type action!"); 240 break; 241 case Legal: 242 break; 243 case PromoteInteger: 244 if (OutVT.getSizeInBits() == NInVT.getSizeInBits()) 245 // The input promotes to the same size. Convert the promoted value. 246 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp)); 247 break; 248 case SoftenFloat: 249 // Promote the integer operand by hand. 250 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp)); 251 case ExpandInteger: 252 case ExpandFloat: 253 break; 254 case Scalarize: 255 // Convert the element to an integer and promote it by hand. 256 return DAG.getNode(ISD::ANY_EXTEND, OutVT, 257 BitConvertToInteger(GetScalarizedVector(InOp))); 258 case Split: 259 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 260 // pieces of the input into integers and reassemble in the final type. 261 SDOperand Lo, Hi; 262 GetSplitVector(N->getOperand(0), Lo, Hi); 263 Lo = BitConvertToInteger(Lo); 264 Hi = BitConvertToInteger(Hi); 265 266 if (TLI.isBigEndian()) 267 std::swap(Lo, Hi); 268 269 InOp = DAG.getNode(ISD::ANY_EXTEND, 270 MVT::getIntegerVT(OutVT.getSizeInBits()), 271 JoinIntegers(Lo, Hi)); 272 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp); 273 } 274 275 // Otherwise, lower the bit-convert to a store/load from the stack, then 276 // promote the load. 277 SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0)); 278 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val)); 279} 280 281SDOperand DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 282 // The input may have strange things in the top bits of the registers, but 283 // these operations don't care. They may have weird bits going out, but 284 // that too is okay if they are integer operations. 285 SDOperand LHS = GetPromotedInteger(N->getOperand(0)); 286 SDOperand RHS = GetPromotedInteger(N->getOperand(1)); 287 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 288} 289 290SDOperand DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 291 // Sign extend the input. 292 SDOperand LHS = GetPromotedInteger(N->getOperand(0)); 293 SDOperand RHS = GetPromotedInteger(N->getOperand(1)); 294 MVT VT = N->getValueType(0); 295 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS, 296 DAG.getValueType(VT)); 297 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS, 298 DAG.getValueType(VT)); 299 300 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 301} 302 303SDOperand DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 304 // Zero extend the input. 305 SDOperand LHS = GetPromotedInteger(N->getOperand(0)); 306 SDOperand RHS = GetPromotedInteger(N->getOperand(1)); 307 MVT VT = N->getValueType(0); 308 LHS = DAG.getZeroExtendInReg(LHS, VT); 309 RHS = DAG.getZeroExtendInReg(RHS, VT); 310 311 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 312} 313 314SDOperand DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 315 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)), 316 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 317} 318 319SDOperand DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 320 // The input value must be properly sign extended. 321 MVT VT = N->getValueType(0); 322 MVT NVT = TLI.getTypeToTransformTo(VT); 323 SDOperand Res = GetPromotedInteger(N->getOperand(0)); 324 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT)); 325 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1)); 326} 327 328SDOperand DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 329 // The input value must be properly zero extended. 330 MVT VT = N->getValueType(0); 331 MVT NVT = TLI.getTypeToTransformTo(VT); 332 SDOperand Res = ZExtPromotedInteger(N->getOperand(0)); 333 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1)); 334} 335 336SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 337 SDOperand LHS = GetPromotedInteger(N->getOperand(1)); 338 SDOperand RHS = GetPromotedInteger(N->getOperand(2)); 339 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS); 340} 341 342SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 343 SDOperand LHS = GetPromotedInteger(N->getOperand(2)); 344 SDOperand RHS = GetPromotedInteger(N->getOperand(3)); 345 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0), 346 N->getOperand(1), LHS, RHS, N->getOperand(4)); 347} 348 349SDOperand DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 350 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 351 MVT OVT = N->getValueType(0); 352 MVT NVT = Op.getValueType(); 353 // Zero extend to the promoted type and do the count there. 354 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT)); 355 // Subtract off the extra leading bits in the bigger type. 356 return DAG.getNode(ISD::SUB, NVT, Op, 357 DAG.getConstant(NVT.getSizeInBits() - 358 OVT.getSizeInBits(), NVT)); 359} 360 361SDOperand DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 362 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 363 MVT OVT = N->getValueType(0); 364 MVT NVT = Op.getValueType(); 365 // Zero extend to the promoted type and do the count there. 366 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT)); 367} 368 369SDOperand DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 370 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 371 MVT OVT = N->getValueType(0); 372 MVT NVT = Op.getValueType(); 373 // The count is the same in the promoted type except if the original 374 // value was zero. This can be handled by setting the bit just off 375 // the top of the original type. 376 Op = DAG.getNode(ISD::OR, NVT, Op, 377 // FIXME: Do this using an APINT constant. 378 DAG.getConstant(1UL << OVT.getSizeInBits(), NVT)); 379 return DAG.getNode(ISD::CTTZ, NVT, Op); 380} 381 382SDOperand DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 383 MVT OldVT = N->getValueType(0); 384 SDOperand OldVec = N->getOperand(0); 385 unsigned OldElts = OldVec.getValueType().getVectorNumElements(); 386 387 if (OldElts == 1) { 388 assert(!isTypeLegal(OldVec.getValueType()) && 389 "Legal one-element vector of a type needing promotion!"); 390 // It is tempting to follow GetScalarizedVector by a call to 391 // GetPromotedInteger, but this would be wrong because the 392 // scalarized value may not yet have been processed. 393 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT), 394 GetScalarizedVector(OldVec)); 395 } 396 397 // Convert to a vector half as long with an element type of twice the width, 398 // for example <4 x i16> -> <2 x i32>. 399 assert(!(OldElts & 1) && "Odd length vectors not supported!"); 400 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 401 assert(OldVT.isSimple() && NewVT.isSimple()); 402 403 SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT, 404 MVT::getVectorVT(NewVT, OldElts / 2), 405 OldVec); 406 407 // Extract the element at OldIdx / 2 from the new vector. 408 SDOperand OldIdx = N->getOperand(1); 409 SDOperand NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx, 410 DAG.getConstant(1, TLI.getShiftAmountTy())); 411 SDOperand Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx); 412 413 // Select the appropriate half of the element: Lo if OldIdx was even, 414 // Hi if it was odd. 415 SDOperand Lo = Elt; 416 SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt, 417 DAG.getConstant(OldVT.getSizeInBits(), 418 TLI.getShiftAmountTy())); 419 if (TLI.isBigEndian()) 420 std::swap(Lo, Hi); 421 422 SDOperand Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx, 423 DAG.getConstant(1, TLI.getShiftAmountTy())); 424 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo); 425} 426 427SDOperand DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 428 SDOperand Chain = N->getOperand(0); // Get the chain. 429 SDOperand Ptr = N->getOperand(1); // Get the pointer. 430 MVT VT = N->getValueType(0); 431 432 const Value *V = cast<SrcValueSDNode>(N->getOperand(2))->getValue(); 433 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Chain, Ptr, V, 0); 434 435 // Increment the arg pointer, VAList, to the next vaarg 436 // FIXME: should the ABI size be used for the increment? Think of 437 // x86 long double (10 bytes long, but aligned on 4 or 8 bytes) or 438 // integers of unusual size (such MVT::i1, which gives an increment 439 // of zero here!). 440 unsigned Increment = VT.getSizeInBits() / 8; 441 SDOperand Tmp = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 442 DAG.getConstant(Increment, TLI.getPointerTy())); 443 444 // Store the incremented VAList to the pointer. 445 Tmp = DAG.getStore(VAList.getValue(1), Tmp, Ptr, V, 0); 446 447 // Load the actual argument out of the arg pointer VAList. 448 Tmp = DAG.getExtLoad(ISD::EXTLOAD, TLI.getTypeToTransformTo(VT), Tmp, 449 VAList, NULL, 0, VT); 450 451 // Legalized the chain result - switch anything that used the old chain to 452 // use the new one. 453 ReplaceValueWith(SDOperand(N, 1), Tmp.getValue(1)); 454 return Tmp; 455} 456 457//===----------------------------------------------------------------------===// 458// Integer Operand Promotion 459//===----------------------------------------------------------------------===// 460 461/// PromoteIntegerOperand - This method is called when the specified operand of 462/// the specified node is found to need promotion. At this point, all of the 463/// result types of the node are known to be legal, but other operands of the 464/// node may need promotion or expansion as well as the specified one. 465bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 466 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n"); 467 SDOperand Res = SDOperand(); 468 469 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 470 == TargetLowering::Custom) 471 Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG); 472 473 if (Res.Val == 0) { 474 switch (N->getOpcode()) { 475 default: 476 #ifndef NDEBUG 477 cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; 478 N->dump(&DAG); cerr << "\n"; 479 #endif 480 assert(0 && "Do not know how to promote this operator's operand!"); 481 abort(); 482 483 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 484 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 485 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 486 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 487 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break; 488 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break; 489 case ISD::SINT_TO_FP: 490 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break; 491 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 492 493 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 494 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 495 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 496 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 497 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 498 499 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 500 OpNo); break; 501 502 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 503 case ISD::INSERT_VECTOR_ELT: 504 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo); 505 break; 506 507 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 508 } 509 } 510 511 // If the result is null, the sub-method took care of registering results etc. 512 if (!Res.Val) return false; 513 // If the result is N, the sub-method updated N in place. 514 if (Res.Val == N) { 515 // Mark N as new and remark N and its operands. This allows us to correctly 516 // revisit N if it needs another step of promotion and allows us to visit 517 // any new operands to N. 518 ReanalyzeNode(N); 519 return true; 520 } 521 522 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 523 "Invalid operand expansion"); 524 525 ReplaceValueWith(SDOperand(N, 0), Res); 526 return false; 527} 528 529SDOperand DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 530 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 531 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 532} 533 534SDOperand DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 535 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 536 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 537 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); 538} 539 540SDOperand DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 541 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 542 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 543 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), 544 Op, DAG.getValueType(N->getOperand(0).getValueType())); 545} 546 547SDOperand DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 548 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 549 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op); 550} 551 552SDOperand DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) { 553 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 554 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op); 555} 556 557SDOperand DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) { 558 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 559 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op, 560 DAG.getIntPtrConstant(0)); 561} 562 563SDOperand DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) { 564 SDOperand In = GetPromotedInteger(N->getOperand(0)); 565 MVT OpVT = N->getOperand(0).getValueType(); 566 if (N->getOpcode() == ISD::UINT_TO_FP) 567 In = DAG.getZeroExtendInReg(In, OpVT); 568 else 569 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), 570 In, DAG.getValueType(OpVT)); 571 572 return DAG.UpdateNodeOperands(SDOperand(N, 0), In); 573} 574 575SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 576 // Since the result type is legal, the operands must promote to it. 577 MVT OVT = N->getOperand(0).getValueType(); 578 SDOperand Lo = GetPromotedInteger(N->getOperand(0)); 579 SDOperand Hi = GetPromotedInteger(N->getOperand(1)); 580 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 581 582 Lo = DAG.getZeroExtendInReg(Lo, OVT); 583 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi, 584 DAG.getConstant(OVT.getSizeInBits(), 585 TLI.getShiftAmountTy())); 586 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi); 587} 588 589SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 590 assert(OpNo == 0 && "Only know how to promote condition"); 591 SDOperand Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition. 592 593 // The top bits of the promoted condition are not necessarily zero, ensure 594 // that the value is properly zero extended. 595 unsigned BitWidth = Cond.getValueSizeInBits(); 596 if (!DAG.MaskedValueIsZero(Cond, 597 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 598 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); 599 600 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 601 return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1), 602 N->getOperand(2)); 603} 604 605SDOperand DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 606 assert(OpNo == 1 && "only know how to promote condition"); 607 SDOperand Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition. 608 609 // The top bits of the promoted condition are not necessarily zero, ensure 610 // that the value is properly zero extended. 611 unsigned BitWidth = Cond.getValueSizeInBits(); 612 if (!DAG.MaskedValueIsZero(Cond, 613 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 614 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); 615 616 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 617 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond, 618 N->getOperand(2)); 619} 620 621SDOperand DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 622 assert(OpNo == 2 && "Don't know how to promote this operand!"); 623 624 SDOperand LHS = N->getOperand(2); 625 SDOperand RHS = N->getOperand(3); 626 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 627 628 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 629 // legal types. 630 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), 631 N->getOperand(1), LHS, RHS, N->getOperand(4)); 632} 633 634SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 635 assert(OpNo == 0 && "Don't know how to promote this operand!"); 636 637 SDOperand LHS = N->getOperand(0); 638 SDOperand RHS = N->getOperand(1); 639 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 640 641 // The CC (#4) and the possible return values (#2 and #3) have legal types. 642 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2), 643 N->getOperand(3), N->getOperand(4)); 644} 645 646SDOperand DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 647 assert(OpNo == 0 && "Don't know how to promote this operand!"); 648 649 SDOperand LHS = N->getOperand(0); 650 SDOperand RHS = N->getOperand(1); 651 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 652 653 // The CC (#2) is always legal. 654 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2)); 655} 656 657/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 658/// shared among BR_CC, SELECT_CC, and SETCC handlers. 659void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS, 660 ISD::CondCode CCCode) { 661 MVT VT = NewLHS.getValueType(); 662 663 // Get the promoted values. 664 NewLHS = GetPromotedInteger(NewLHS); 665 NewRHS = GetPromotedInteger(NewRHS); 666 667 // Otherwise, we have to insert explicit sign or zero extends. Note 668 // that we could insert sign extends for ALL conditions, but zero extend 669 // is cheaper on many machines (an AND instead of two shifts), so prefer 670 // it. 671 switch (CCCode) { 672 default: assert(0 && "Unknown integer comparison!"); 673 case ISD::SETEQ: 674 case ISD::SETNE: 675 case ISD::SETUGE: 676 case ISD::SETUGT: 677 case ISD::SETULE: 678 case ISD::SETULT: 679 // ALL of these operations will work if we either sign or zero extend 680 // the operands (including the unsigned comparisons!). Zero extend is 681 // usually a simpler/cheaper operation, so prefer it. 682 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT); 683 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT); 684 break; 685 case ISD::SETGE: 686 case ISD::SETGT: 687 case ISD::SETLT: 688 case ISD::SETLE: 689 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS, 690 DAG.getValueType(VT)); 691 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS, 692 DAG.getValueType(VT)); 693 break; 694 } 695} 696 697SDOperand DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 698 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 699 SDOperand Ch = N->getChain(), Ptr = N->getBasePtr(); 700 int SVOffset = N->getSrcValueOffset(); 701 unsigned Alignment = N->getAlignment(); 702 bool isVolatile = N->isVolatile(); 703 704 SDOperand Val = GetPromotedInteger(N->getValue()); // Get promoted value. 705 706 assert(!N->isTruncatingStore() && "Cannot promote this store operand!"); 707 708 // Truncate the value and store the result. 709 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(), 710 SVOffset, N->getMemoryVT(), 711 isVolatile, Alignment); 712} 713 714SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 715 // The vector type is legal but the element type is not. This implies 716 // that the vector is a power-of-two in length and that the element 717 // type does not have a strange size (eg: it is not i1). 718 MVT VecVT = N->getValueType(0); 719 unsigned NumElts = VecVT.getVectorNumElements(); 720 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 721 722 // Build a vector of half the length out of elements of twice the bitwidth. 723 // For example <4 x i16> -> <2 x i32>. 724 MVT OldVT = N->getOperand(0).getValueType(); 725 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 726 assert(OldVT.isSimple() && NewVT.isSimple()); 727 728 std::vector<SDOperand> NewElts; 729 NewElts.reserve(NumElts/2); 730 731 for (unsigned i = 0; i < NumElts; i += 2) { 732 // Combine two successive elements into one promoted element. 733 SDOperand Lo = N->getOperand(i); 734 SDOperand Hi = N->getOperand(i+1); 735 if (TLI.isBigEndian()) 736 std::swap(Lo, Hi); 737 NewElts.push_back(JoinIntegers(Lo, Hi)); 738 } 739 740 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR, 741 MVT::getVectorVT(NewVT, NewElts.size()), 742 &NewElts[0], NewElts.size()); 743 744 // Convert the new vector to the old vector type. 745 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec); 746} 747 748SDOperand DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 749 unsigned OpNo) { 750 if (OpNo == 1) { 751 // Promote the inserted value. This is valid because the type does not 752 // have to match the vector element type. 753 754 // Check that any extra bits introduced will be truncated away. 755 assert(N->getOperand(1).getValueType().getSizeInBits() >= 756 N->getValueType(0).getVectorElementType().getSizeInBits() && 757 "Type of inserted value narrower than vector element type!"); 758 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), 759 GetPromotedInteger(N->getOperand(1)), 760 N->getOperand(2)); 761 } 762 763 assert(OpNo == 2 && "Different operand and result vector types?"); 764 765 // Promote the index. 766 SDOperand Idx = N->getOperand(2); 767 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType()); 768 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), 769 N->getOperand(1), Idx); 770} 771 772SDOperand DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 773 SDOperand NewOps[6]; 774 NewOps[0] = N->getOperand(0); 775 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 776 SDOperand Flag = GetPromotedInteger(N->getOperand(i)); 777 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1); 778 } 779 return DAG.UpdateNodeOperands(SDOperand (N, 0), NewOps, 780 array_lengthof(NewOps)); 781} 782 783 784//===----------------------------------------------------------------------===// 785// Integer Result Expansion 786//===----------------------------------------------------------------------===// 787 788/// ExpandIntegerResult - This method is called when the specified result of the 789/// specified node is found to need expansion. At this point, the node may also 790/// have invalid operands or may have other results that need promotion, we just 791/// know that (at least) one result needs expansion. 792void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 793 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n"); 794 SDOperand Lo, Hi; 795 Lo = Hi = SDOperand(); 796 797 // See if the target wants to custom expand this node. 798 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 799 TargetLowering::Custom) { 800 // If the target wants to, allow it to lower this itself. 801 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 802 // Everything that once used N now uses P. We are guaranteed that the 803 // result value types of N and the result value types of P match. 804 ReplaceNodeWith(N, P); 805 return; 806 } 807 } 808 809 switch (N->getOpcode()) { 810 default: 811#ifndef NDEBUG 812 cerr << "ExpandIntegerResult #" << ResNo << ": "; 813 N->dump(&DAG); cerr << "\n"; 814#endif 815 assert(0 && "Do not know how to expand the result of this operator!"); 816 abort(); 817 818 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 819 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 820 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 821 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 822 823 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 824 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 825 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 826 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 827 828 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 829 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 830 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 831 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 832 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 833 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 834 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 835 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 836 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 837 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 838 839 case ISD::AND: 840 case ISD::OR: 841 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 842 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 843 case ISD::ADD: 844 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 845 case ISD::ADDC: 846 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 847 case ISD::ADDE: 848 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 849 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 850 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 851 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 852 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 853 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 854 case ISD::SHL: 855 case ISD::SRA: 856 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 857 858 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 859 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 860 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 861 } 862 863 // If Lo/Hi is null, the sub-method took care of registering results etc. 864 if (Lo.Val) 865 SetExpandedInteger(SDOperand(N, ResNo), Lo, Hi); 866} 867 868void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 869 SDOperand &Lo, SDOperand &Hi) { 870 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 871 unsigned NBitWidth = NVT.getSizeInBits(); 872 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 873 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 874 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 875} 876 877void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 878 SDOperand &Lo, SDOperand &Hi) { 879 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 880 SDOperand Op = N->getOperand(0); 881 if (Op.getValueType().bitsLE(NVT)) { 882 // The low part is any extension of the input (which degenerates to a copy). 883 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op); 884 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined. 885 } else { 886 // For example, extension of an i48 to an i64. The operand type necessarily 887 // promotes to the result type, so will end up being expanded too. 888 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 889 "Only know how to promote this result!"); 890 SDOperand Res = GetPromotedInteger(Op); 891 assert(Res.getValueType() == N->getValueType(0) && 892 "Operand over promoted?"); 893 // Split the promoted operand. This will simplify when it is expanded. 894 SplitInteger(Res, Lo, Hi); 895 } 896} 897 898void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 899 SDOperand &Lo, SDOperand &Hi) { 900 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 901 SDOperand Op = N->getOperand(0); 902 if (Op.getValueType().bitsLE(NVT)) { 903 // The low part is zero extension of the input (which degenerates to a copy). 904 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0)); 905 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 906 } else { 907 // For example, extension of an i48 to an i64. The operand type necessarily 908 // promotes to the result type, so will end up being expanded too. 909 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 910 "Only know how to promote this result!"); 911 SDOperand Res = GetPromotedInteger(Op); 912 assert(Res.getValueType() == N->getValueType(0) && 913 "Operand over promoted?"); 914 // Split the promoted operand. This will simplify when it is expanded. 915 SplitInteger(Res, Lo, Hi); 916 unsigned ExcessBits = 917 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 918 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); 919 } 920} 921 922void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 923 SDOperand &Lo, SDOperand &Hi) { 924 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 925 SDOperand Op = N->getOperand(0); 926 if (Op.getValueType().bitsLE(NVT)) { 927 // The low part is sign extension of the input (which degenerates to a copy). 928 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0)); 929 // The high part is obtained by SRA'ing all but one of the bits of low part. 930 unsigned LoSize = NVT.getSizeInBits(); 931 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 932 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 933 } else { 934 // For example, extension of an i48 to an i64. The operand type necessarily 935 // promotes to the result type, so will end up being expanded too. 936 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 937 "Only know how to promote this result!"); 938 SDOperand Res = GetPromotedInteger(Op); 939 assert(Res.getValueType() == N->getValueType(0) && 940 "Operand over promoted?"); 941 // Split the promoted operand. This will simplify when it is expanded. 942 SplitInteger(Res, Lo, Hi); 943 unsigned ExcessBits = 944 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 945 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 946 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 947 } 948} 949 950void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 951 SDOperand &Lo, SDOperand &Hi) { 952 GetExpandedInteger(N->getOperand(0), Lo, Hi); 953 MVT NVT = Lo.getValueType(); 954 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 955 unsigned NVTBits = NVT.getSizeInBits(); 956 unsigned EVTBits = EVT.getSizeInBits(); 957 958 if (NVTBits < EVTBits) { 959 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi, 960 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 961 } else { 962 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT)); 963 // The high part must be zero, make it explicit. 964 Hi = DAG.getConstant(0, NVT); 965 } 966} 967 968void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 969 SDOperand &Lo, SDOperand &Hi) { 970 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 971 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0)); 972 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0), 973 DAG.getConstant(NVT.getSizeInBits(), 974 TLI.getShiftAmountTy())); 975 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi); 976} 977 978void DAGTypeLegalizer:: 979ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) { 980 GetExpandedInteger(N->getOperand(0), Lo, Hi); 981 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 982 983 if (EVT.bitsLE(Lo.getValueType())) { 984 // sext_inreg the low part if needed. 985 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo, 986 N->getOperand(1)); 987 988 // The high part gets the sign extension from the lo-part. This handles 989 // things like sextinreg V:i64 from i8. 990 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo, 991 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 992 TLI.getShiftAmountTy())); 993 } else { 994 // For example, extension of an i48 to an i64. Leave the low part alone, 995 // sext_inreg the high part. 996 unsigned ExcessBits = 997 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 998 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 999 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1000 } 1001} 1002 1003void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDOperand &Lo, 1004 SDOperand &Hi) { 1005 MVT VT = N->getValueType(0); 1006 SDOperand Op = N->getOperand(0); 1007 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1008 if (VT == MVT::i64) { 1009 if (Op.getValueType() == MVT::f32) 1010 LC = RTLIB::FPTOSINT_F32_I64; 1011 else if (Op.getValueType() == MVT::f64) 1012 LC = RTLIB::FPTOSINT_F64_I64; 1013 else if (Op.getValueType() == MVT::f80) 1014 LC = RTLIB::FPTOSINT_F80_I64; 1015 else if (Op.getValueType() == MVT::ppcf128) 1016 LC = RTLIB::FPTOSINT_PPCF128_I64; 1017 } else if (VT == MVT::i128) { 1018 if (Op.getValueType() == MVT::f32) 1019 LC = RTLIB::FPTOSINT_F32_I128; 1020 else if (Op.getValueType() == MVT::f64) 1021 LC = RTLIB::FPTOSINT_F64_I128; 1022 else if (Op.getValueType() == MVT::f80) 1023 LC = RTLIB::FPTOSINT_F80_I128; 1024 else if (Op.getValueType() == MVT::ppcf128) 1025 LC = RTLIB::FPTOSINT_PPCF128_I128; 1026 } else { 1027 assert(0 && "Unexpected fp-to-sint conversion!"); 1028 } 1029 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi); 1030} 1031 1032void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDOperand &Lo, 1033 SDOperand &Hi) { 1034 MVT VT = N->getValueType(0); 1035 SDOperand Op = N->getOperand(0); 1036 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1037 if (VT == MVT::i64) { 1038 if (Op.getValueType() == MVT::f32) 1039 LC = RTLIB::FPTOUINT_F32_I64; 1040 else if (Op.getValueType() == MVT::f64) 1041 LC = RTLIB::FPTOUINT_F64_I64; 1042 else if (Op.getValueType() == MVT::f80) 1043 LC = RTLIB::FPTOUINT_F80_I64; 1044 else if (Op.getValueType() == MVT::ppcf128) 1045 LC = RTLIB::FPTOUINT_PPCF128_I64; 1046 } else if (VT == MVT::i128) { 1047 if (Op.getValueType() == MVT::f32) 1048 LC = RTLIB::FPTOUINT_F32_I128; 1049 else if (Op.getValueType() == MVT::f64) 1050 LC = RTLIB::FPTOUINT_F64_I128; 1051 else if (Op.getValueType() == MVT::f80) 1052 LC = RTLIB::FPTOUINT_F80_I128; 1053 else if (Op.getValueType() == MVT::ppcf128) 1054 LC = RTLIB::FPTOUINT_PPCF128_I128; 1055 } else { 1056 assert(0 && "Unexpected fp-to-uint conversion!"); 1057 } 1058 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi); 1059} 1060 1061void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1062 SDOperand &Lo, SDOperand &Hi) { 1063 if (ISD::isNormalLoad(N)) { 1064 ExpandRes_NormalLoad(N, Lo, Hi); 1065 return; 1066 } 1067 1068 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1069 1070 MVT VT = N->getValueType(0); 1071 MVT NVT = TLI.getTypeToTransformTo(VT); 1072 SDOperand Ch = N->getChain(); // Legalize the chain. 1073 SDOperand Ptr = N->getBasePtr(); // Legalize the pointer. 1074 ISD::LoadExtType ExtType = N->getExtensionType(); 1075 int SVOffset = N->getSrcValueOffset(); 1076 unsigned Alignment = N->getAlignment(); 1077 bool isVolatile = N->isVolatile(); 1078 1079 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1080 1081 if (N->getMemoryVT().bitsLE(NVT)) { 1082 MVT EVT = N->getMemoryVT(); 1083 1084 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT, 1085 isVolatile, Alignment); 1086 1087 // Remember the chain. 1088 Ch = Lo.getValue(1); 1089 1090 if (ExtType == ISD::SEXTLOAD) { 1091 // The high part is obtained by SRA'ing all but one of the bits of the 1092 // lo part. 1093 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1094 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1095 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1096 } else if (ExtType == ISD::ZEXTLOAD) { 1097 // The high part is just a zero. 1098 Hi = DAG.getConstant(0, NVT); 1099 } else { 1100 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1101 // The high part is undefined. 1102 Hi = DAG.getNode(ISD::UNDEF, NVT); 1103 } 1104 } else if (TLI.isLittleEndian()) { 1105 // Little-endian - low bits are at low addresses. 1106 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1107 isVolatile, Alignment); 1108 1109 unsigned ExcessBits = 1110 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1111 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1112 1113 // Increment the pointer to the other half. 1114 unsigned IncrementSize = NVT.getSizeInBits()/8; 1115 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1116 DAG.getIntPtrConstant(IncrementSize)); 1117 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), 1118 SVOffset+IncrementSize, NEVT, 1119 isVolatile, MinAlign(Alignment, IncrementSize)); 1120 1121 // Build a factor node to remember that this load is independent of the 1122 // other one. 1123 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1124 Hi.getValue(1)); 1125 } else { 1126 // Big-endian - high bits are at low addresses. Favor aligned loads at 1127 // the cost of some bit-fiddling. 1128 MVT EVT = N->getMemoryVT(); 1129 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1130 unsigned IncrementSize = NVT.getSizeInBits()/8; 1131 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1132 1133 // Load both the high bits and maybe some of the low bits. 1134 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1135 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), 1136 isVolatile, Alignment); 1137 1138 // Increment the pointer to the other half. 1139 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1140 DAG.getIntPtrConstant(IncrementSize)); 1141 // Load the rest of the low bits. 1142 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(), 1143 SVOffset+IncrementSize, 1144 MVT::getIntegerVT(ExcessBits), 1145 isVolatile, MinAlign(Alignment, IncrementSize)); 1146 1147 // Build a factor node to remember that this load is independent of the 1148 // other one. 1149 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1150 Hi.getValue(1)); 1151 1152 if (ExcessBits < NVT.getSizeInBits()) { 1153 // Transfer low bits from the bottom of Hi to the top of Lo. 1154 Lo = DAG.getNode(ISD::OR, NVT, Lo, 1155 DAG.getNode(ISD::SHL, NVT, Hi, 1156 DAG.getConstant(ExcessBits, 1157 TLI.getShiftAmountTy()))); 1158 // Move high bits to the right position in Hi. 1159 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi, 1160 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1161 TLI.getShiftAmountTy())); 1162 } 1163 } 1164 1165 // Legalized the chain result - switch anything that used the old chain to 1166 // use the new one. 1167 ReplaceValueWith(SDOperand(N, 1), Ch); 1168} 1169 1170void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1171 SDOperand &Lo, SDOperand &Hi) { 1172 SDOperand LL, LH, RL, RH; 1173 GetExpandedInteger(N->getOperand(0), LL, LH); 1174 GetExpandedInteger(N->getOperand(1), RL, RH); 1175 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL); 1176 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH); 1177} 1178 1179void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1180 SDOperand &Lo, SDOperand &Hi) { 1181 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1182 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo); 1183 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi); 1184} 1185 1186void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1187 SDOperand &Lo, SDOperand &Hi) { 1188 // Expand the subcomponents. 1189 SDOperand LHSL, LHSH, RHSL, RHSH; 1190 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1191 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1192 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1193 SDOperand LoOps[2] = { LHSL, RHSL }; 1194 SDOperand HiOps[3] = { LHSH, RHSH }; 1195 1196 if (N->getOpcode() == ISD::ADD) { 1197 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1198 HiOps[2] = Lo.getValue(1); 1199 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1200 } else { 1201 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1202 HiOps[2] = Lo.getValue(1); 1203 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1204 } 1205} 1206 1207void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1208 SDOperand &Lo, SDOperand &Hi) { 1209 // Expand the subcomponents. 1210 SDOperand LHSL, LHSH, RHSL, RHSH; 1211 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1212 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1213 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1214 SDOperand LoOps[2] = { LHSL, RHSL }; 1215 SDOperand HiOps[3] = { LHSH, RHSH }; 1216 1217 if (N->getOpcode() == ISD::ADDC) { 1218 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1219 HiOps[2] = Lo.getValue(1); 1220 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1221 } else { 1222 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1223 HiOps[2] = Lo.getValue(1); 1224 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1225 } 1226 1227 // Legalized the flag result - switch anything that used the old flag to 1228 // use the new one. 1229 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1)); 1230} 1231 1232void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1233 SDOperand &Lo, SDOperand &Hi) { 1234 // Expand the subcomponents. 1235 SDOperand LHSL, LHSH, RHSL, RHSH; 1236 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1237 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1238 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1239 SDOperand LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1240 SDOperand HiOps[3] = { LHSH, RHSH }; 1241 1242 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3); 1243 HiOps[2] = Lo.getValue(1); 1244 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3); 1245 1246 // Legalized the flag result - switch anything that used the old flag to 1247 // use the new one. 1248 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1)); 1249} 1250 1251void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1252 SDOperand &Lo, SDOperand &Hi) { 1253 MVT VT = N->getValueType(0); 1254 MVT NVT = TLI.getTypeToTransformTo(VT); 1255 1256 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 1257 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 1258 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 1259 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 1260 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1261 SDOperand LL, LH, RL, RH; 1262 GetExpandedInteger(N->getOperand(0), LL, LH); 1263 GetExpandedInteger(N->getOperand(1), RL, RH); 1264 unsigned OuterBitSize = VT.getSizeInBits(); 1265 unsigned InnerBitSize = NVT.getSizeInBits(); 1266 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1267 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1268 1269 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1270 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1271 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1272 // The inputs are both zero-extended. 1273 if (HasUMUL_LOHI) { 1274 // We can emit a umul_lohi. 1275 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1276 Hi = SDOperand(Lo.Val, 1); 1277 return; 1278 } 1279 if (HasMULHU) { 1280 // We can emit a mulhu+mul. 1281 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1282 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1283 return; 1284 } 1285 } 1286 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1287 // The input values are both sign-extended. 1288 if (HasSMUL_LOHI) { 1289 // We can emit a smul_lohi. 1290 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1291 Hi = SDOperand(Lo.Val, 1); 1292 return; 1293 } 1294 if (HasMULHS) { 1295 // We can emit a mulhs+mul. 1296 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1297 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 1298 return; 1299 } 1300 } 1301 if (HasUMUL_LOHI) { 1302 // Lo,Hi = umul LHS, RHS. 1303 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 1304 DAG.getVTList(NVT, NVT), LL, RL); 1305 Lo = UMulLOHI; 1306 Hi = UMulLOHI.getValue(1); 1307 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1308 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1309 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1310 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1311 return; 1312 } 1313 if (HasMULHU) { 1314 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1315 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1316 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1317 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1318 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1319 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1320 return; 1321 } 1322 } 1323 1324 // If nothing else, we can make a libcall. 1325 RTLIB::Libcall LC; 1326 switch (VT.getSimpleVT()) { 1327 default: 1328 assert(false && "Unsupported MUL!"); 1329 case MVT::i64: 1330 LC = RTLIB::MUL_I64; 1331 break; 1332 } 1333 1334 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1335 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi); 1336} 1337 1338void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1339 SDOperand &Lo, SDOperand &Hi) { 1340 assert(N->getValueType(0) == MVT::i64 && "Unsupported sdiv!"); 1341 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1342 SplitInteger(MakeLibCall(RTLIB::SDIV_I64, N->getValueType(0), Ops, 2, true), 1343 Lo, Hi); 1344} 1345 1346void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1347 SDOperand &Lo, SDOperand &Hi) { 1348 assert(N->getValueType(0) == MVT::i64 && "Unsupported srem!"); 1349 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1350 SplitInteger(MakeLibCall(RTLIB::SREM_I64, N->getValueType(0), Ops, 2, true), 1351 Lo, Hi); 1352} 1353 1354void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1355 SDOperand &Lo, SDOperand &Hi) { 1356 assert(N->getValueType(0) == MVT::i64 && "Unsupported udiv!"); 1357 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1358 SplitInteger(MakeLibCall(RTLIB::UDIV_I64, N->getValueType(0), Ops, 2, false), 1359 Lo, Hi); 1360} 1361 1362void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 1363 SDOperand &Lo, SDOperand &Hi) { 1364 assert(N->getValueType(0) == MVT::i64 && "Unsupported urem!"); 1365 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1366 SplitInteger(MakeLibCall(RTLIB::UREM_I64, N->getValueType(0), Ops, 2, false), 1367 Lo, Hi); 1368} 1369 1370void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1371 SDOperand &Lo, SDOperand &Hi) { 1372 MVT VT = N->getValueType(0); 1373 1374 // If we can emit an efficient shift operation, do so now. Check to see if 1375 // the RHS is a constant. 1376 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1377 return ExpandShiftByConstant(N, CN->getValue(), Lo, Hi); 1378 1379 // If we can determine that the high bit of the shift is zero or one, even if 1380 // the low bits are variable, emit this shift in an optimized form. 1381 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1382 return; 1383 1384 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1385 unsigned PartsOpc; 1386 if (N->getOpcode() == ISD::SHL) { 1387 PartsOpc = ISD::SHL_PARTS; 1388 } else if (N->getOpcode() == ISD::SRL) { 1389 PartsOpc = ISD::SRL_PARTS; 1390 } else { 1391 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1392 PartsOpc = ISD::SRA_PARTS; 1393 } 1394 1395 // Next check to see if the target supports this SHL_PARTS operation or if it 1396 // will custom expand it. 1397 MVT NVT = TLI.getTypeToTransformTo(VT); 1398 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1399 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1400 Action == TargetLowering::Custom) { 1401 // Expand the subcomponents. 1402 SDOperand LHSL, LHSH; 1403 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1404 1405 SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1406 MVT VT = LHSL.getValueType(); 1407 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 1408 Hi = Lo.getValue(1); 1409 return; 1410 } 1411 1412 // Otherwise, emit a libcall. 1413 assert(VT == MVT::i64 && "Unsupported shift!"); 1414 1415 RTLIB::Libcall LC; 1416 bool isSigned; 1417 if (N->getOpcode() == ISD::SHL) { 1418 LC = RTLIB::SHL_I64; 1419 isSigned = false; /*sign irrelevant*/ 1420 } else if (N->getOpcode() == ISD::SRL) { 1421 LC = RTLIB::SRL_I64; 1422 isSigned = false; 1423 } else { 1424 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1425 LC = RTLIB::SRA_I64; 1426 isSigned = true; 1427 } 1428 1429 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1430 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi); 1431} 1432 1433void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1434 SDOperand &Lo, SDOperand &Hi) { 1435 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1436 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1437 MVT NVT = Lo.getValueType(); 1438 1439 SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 1440 DAG.getConstant(0, NVT), ISD::SETNE); 1441 1442 SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo); 1443 SDOperand HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 1444 1445 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ, 1446 DAG.getNode(ISD::ADD, NVT, LoLZ, 1447 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1448 Hi = DAG.getConstant(0, NVT); 1449} 1450 1451void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1452 SDOperand &Lo, SDOperand &Hi) { 1453 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1454 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1455 MVT NVT = Lo.getValueType(); 1456 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), 1457 DAG.getNode(ISD::CTPOP, NVT, Hi)); 1458 Hi = DAG.getConstant(0, NVT); 1459} 1460 1461void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1462 SDOperand &Lo, SDOperand &Hi) { 1463 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1464 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1465 MVT NVT = Lo.getValueType(); 1466 1467 SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, 1468 DAG.getConstant(0, NVT), ISD::SETNE); 1469 1470 SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 1471 SDOperand HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi); 1472 1473 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ, 1474 DAG.getNode(ISD::ADD, NVT, HiLZ, 1475 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1476 Hi = DAG.getConstant(0, NVT); 1477} 1478 1479/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1480/// and the shift amount is a constant 'Amt'. Expand the operation. 1481void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1482 SDOperand &Lo, SDOperand &Hi) { 1483 // Expand the incoming operand to be shifted, so that we have its parts 1484 SDOperand InL, InH; 1485 GetExpandedInteger(N->getOperand(0), InL, InH); 1486 1487 MVT NVT = InL.getValueType(); 1488 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1489 unsigned NVTBits = NVT.getSizeInBits(); 1490 MVT ShTy = N->getOperand(1).getValueType(); 1491 1492 if (N->getOpcode() == ISD::SHL) { 1493 if (Amt > VTBits) { 1494 Lo = Hi = DAG.getConstant(0, NVT); 1495 } else if (Amt > NVTBits) { 1496 Lo = DAG.getConstant(0, NVT); 1497 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1498 } else if (Amt == NVTBits) { 1499 Lo = DAG.getConstant(0, NVT); 1500 Hi = InL; 1501 } else { 1502 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1503 Hi = DAG.getNode(ISD::OR, NVT, 1504 DAG.getNode(ISD::SHL, NVT, InH, 1505 DAG.getConstant(Amt, ShTy)), 1506 DAG.getNode(ISD::SRL, NVT, InL, 1507 DAG.getConstant(NVTBits-Amt, ShTy))); 1508 } 1509 return; 1510 } 1511 1512 if (N->getOpcode() == ISD::SRL) { 1513 if (Amt > VTBits) { 1514 Lo = DAG.getConstant(0, NVT); 1515 Hi = DAG.getConstant(0, NVT); 1516 } else if (Amt > NVTBits) { 1517 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1518 Hi = DAG.getConstant(0, NVT); 1519 } else if (Amt == NVTBits) { 1520 Lo = InH; 1521 Hi = DAG.getConstant(0, NVT); 1522 } else { 1523 Lo = DAG.getNode(ISD::OR, NVT, 1524 DAG.getNode(ISD::SRL, NVT, InL, 1525 DAG.getConstant(Amt, ShTy)), 1526 DAG.getNode(ISD::SHL, NVT, InH, 1527 DAG.getConstant(NVTBits-Amt, ShTy))); 1528 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1529 } 1530 return; 1531 } 1532 1533 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1534 if (Amt > VTBits) { 1535 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 1536 DAG.getConstant(NVTBits-1, ShTy)); 1537 } else if (Amt > NVTBits) { 1538 Lo = DAG.getNode(ISD::SRA, NVT, InH, 1539 DAG.getConstant(Amt-NVTBits, ShTy)); 1540 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1541 DAG.getConstant(NVTBits-1, ShTy)); 1542 } else if (Amt == NVTBits) { 1543 Lo = InH; 1544 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1545 DAG.getConstant(NVTBits-1, ShTy)); 1546 } else { 1547 Lo = DAG.getNode(ISD::OR, NVT, 1548 DAG.getNode(ISD::SRL, NVT, InL, 1549 DAG.getConstant(Amt, ShTy)), 1550 DAG.getNode(ISD::SHL, NVT, InH, 1551 DAG.getConstant(NVTBits-Amt, ShTy))); 1552 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy)); 1553 } 1554} 1555 1556/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1557/// this shift based on knowledge of the high bit of the shift amount. If we 1558/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1559/// shift amount. 1560bool DAGTypeLegalizer:: 1561ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) { 1562 SDOperand Amt = N->getOperand(1); 1563 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1564 MVT ShTy = Amt.getValueType(); 1565 unsigned ShBits = ShTy.getSizeInBits(); 1566 unsigned NVTBits = NVT.getSizeInBits(); 1567 assert(isPowerOf2_32(NVTBits) && 1568 "Expanded integer type size not a power of two!"); 1569 1570 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1571 APInt KnownZero, KnownOne; 1572 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1573 1574 // If we don't know anything about the high bits, exit. 1575 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1576 return false; 1577 1578 // Get the incoming operand to be shifted. 1579 SDOperand InL, InH; 1580 GetExpandedInteger(N->getOperand(0), InL, InH); 1581 1582 // If we know that any of the high bits of the shift amount are one, then we 1583 // can do this as a couple of simple shifts. 1584 if (KnownOne.intersects(HighBitMask)) { 1585 // Mask out the high bit, which we know is set. 1586 Amt = DAG.getNode(ISD::AND, ShTy, Amt, 1587 DAG.getConstant(~HighBitMask, ShTy)); 1588 1589 switch (N->getOpcode()) { 1590 default: assert(0 && "Unknown shift"); 1591 case ISD::SHL: 1592 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1593 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 1594 return true; 1595 case ISD::SRL: 1596 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1597 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 1598 return true; 1599 case ISD::SRA: 1600 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 1601 DAG.getConstant(NVTBits-1, ShTy)); 1602 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 1603 return true; 1604 } 1605 } 1606 1607 // If we know that all of the high bits of the shift amount are zero, then we 1608 // can do this as a couple of simple shifts. 1609 if ((KnownZero & HighBitMask) == HighBitMask) { 1610 // Compute 32-amt. 1611 SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy, 1612 DAG.getConstant(NVTBits, ShTy), 1613 Amt); 1614 unsigned Op1, Op2; 1615 switch (N->getOpcode()) { 1616 default: assert(0 && "Unknown shift"); 1617 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1618 case ISD::SRL: 1619 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1620 } 1621 1622 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1623 Hi = DAG.getNode(ISD::OR, NVT, 1624 DAG.getNode(Op1, NVT, InH, Amt), 1625 DAG.getNode(Op2, NVT, InL, Amt2)); 1626 return true; 1627 } 1628 1629 return false; 1630} 1631 1632 1633//===----------------------------------------------------------------------===// 1634// Integer Operand Expansion 1635//===----------------------------------------------------------------------===// 1636 1637/// ExpandIntegerOperand - This method is called when the specified operand of 1638/// the specified node is found to need expansion. At this point, all of the 1639/// result types of the node are known to be legal, but other operands of the 1640/// node may need promotion or expansion as well as the specified one. 1641bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 1642 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n"); 1643 SDOperand Res = SDOperand(); 1644 1645 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 1646 == TargetLowering::Custom) 1647 Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG); 1648 1649 if (Res.Val == 0) { 1650 switch (N->getOpcode()) { 1651 default: 1652 #ifndef NDEBUG 1653 cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; 1654 N->dump(&DAG); cerr << "\n"; 1655 #endif 1656 assert(0 && "Do not know how to expand this operator's operand!"); 1657 abort(); 1658 1659 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 1660 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 1661 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 1662 1663 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 1664 1665 case ISD::SINT_TO_FP: 1666 Res = ExpandIntOp_SINT_TO_FP(N->getOperand(0), N->getValueType(0)); 1667 break; 1668 case ISD::UINT_TO_FP: 1669 Res = ExpandIntOp_UINT_TO_FP(N->getOperand(0), N->getValueType(0)); 1670 break; 1671 1672 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 1673 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 1674 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 1675 1676 case ISD::STORE: 1677 Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); 1678 break; 1679 } 1680 } 1681 1682 // If the result is null, the sub-method took care of registering results etc. 1683 if (!Res.Val) return false; 1684 // If the result is N, the sub-method updated N in place. Check to see if any 1685 // operands are new, and if so, mark them. 1686 if (Res.Val == N) { 1687 // Mark N as new and remark N and its operands. This allows us to correctly 1688 // revisit N if it needs another step of expansion and allows us to visit 1689 // any new operands to N. 1690 ReanalyzeNode(N); 1691 return true; 1692 } 1693 1694 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1695 "Invalid operand expansion"); 1696 1697 ReplaceValueWith(SDOperand(N, 0), Res); 1698 return false; 1699} 1700 1701SDOperand DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 1702 SDOperand InL, InH; 1703 GetExpandedInteger(N->getOperand(0), InL, InH); 1704 // Just truncate the low part of the source. 1705 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL); 1706} 1707 1708SDOperand DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDOperand Source, 1709 MVT DestTy) { 1710 // We know the destination is legal, but that the input needs to be expanded. 1711 MVT SourceVT = Source.getValueType(); 1712 1713 // Check to see if the target has a custom way to lower this. If so, use it. 1714 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 1715 default: assert(0 && "This action not implemented for this operation!"); 1716 case TargetLowering::Legal: 1717 case TargetLowering::Expand: 1718 break; // This case is handled below. 1719 case TargetLowering::Custom: 1720 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 1721 Source), DAG); 1722 if (NV.Val) return NV; 1723 break; // The target lowered this. 1724 } 1725 1726 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1727 if (SourceVT == MVT::i64) { 1728 if (DestTy == MVT::f32) 1729 LC = RTLIB::SINTTOFP_I64_F32; 1730 else { 1731 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 1732 LC = RTLIB::SINTTOFP_I64_F64; 1733 } 1734 } else if (SourceVT == MVT::i128) { 1735 if (DestTy == MVT::f32) 1736 LC = RTLIB::SINTTOFP_I128_F32; 1737 else if (DestTy == MVT::f64) 1738 LC = RTLIB::SINTTOFP_I128_F64; 1739 else if (DestTy == MVT::f80) 1740 LC = RTLIB::SINTTOFP_I128_F80; 1741 else { 1742 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 1743 LC = RTLIB::SINTTOFP_I128_PPCF128; 1744 } 1745 } else { 1746 assert(0 && "Unknown int value type!"); 1747 } 1748 1749 assert(LC != RTLIB::UNKNOWN_LIBCALL && 1750 "Don't know how to expand this SINT_TO_FP!"); 1751 return MakeLibCall(LC, DestTy, &Source, 1, true); 1752} 1753 1754SDOperand DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDOperand Source, 1755 MVT DestTy) { 1756 // We know the destination is legal, but that the input needs to be expanded. 1757 assert(getTypeAction(Source.getValueType()) == ExpandInteger && 1758 "This is not an expansion!"); 1759 1760 // If this is unsigned, and not supported, first perform the conversion to 1761 // signed, then adjust the result if the sign bit is set. 1762 SDOperand SignedConv = ExpandIntOp_SINT_TO_FP(Source, DestTy); 1763 1764 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 1765 // incoming integer is set. To handle this, we dynamically test to see if 1766 // it is set, and, if so, add a fudge factor. 1767 SDOperand Lo, Hi; 1768 GetExpandedInteger(Source, Lo, Hi); 1769 1770 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 1771 DAG.getConstant(0, Hi.getValueType()), 1772 ISD::SETLT); 1773 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 1774 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 1775 SignSet, Four, Zero); 1776 uint64_t FF = 0x5f800000ULL; 1777 if (TLI.isLittleEndian()) FF <<= 32; 1778 Constant *FudgeFactor = ConstantInt::get((Type*)Type::Int64Ty, FF); 1779 1780 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 1781 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 1782 SDOperand FudgeInReg; 1783 if (DestTy == MVT::f32) 1784 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 1785 else if (DestTy.bitsGT(MVT::f32)) 1786 // FIXME: Avoid the extend by construction the right constantpool? 1787 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 1788 CPIdx, NULL, 0, MVT::f32); 1789 else 1790 assert(0 && "Unexpected conversion"); 1791 1792 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 1793} 1794 1795SDOperand DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 1796 SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 1797 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 1798 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 1799 1800 // If ExpandSetCCOperands returned a scalar, we need to compare the result 1801 // against zero to select between true and false values. 1802 if (NewRHS.Val == 0) { 1803 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1804 CCCode = ISD::SETNE; 1805 } 1806 1807 // Update N to have the operands specified. 1808 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), 1809 DAG.getCondCode(CCCode), NewLHS, NewRHS, 1810 N->getOperand(4)); 1811} 1812 1813SDOperand DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 1814 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 1815 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 1816 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 1817 1818 // If ExpandSetCCOperands returned a scalar, we need to compare the result 1819 // against zero to select between true and false values. 1820 if (NewRHS.Val == 0) { 1821 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1822 CCCode = ISD::SETNE; 1823 } 1824 1825 // Update N to have the operands specified. 1826 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS, 1827 N->getOperand(2), N->getOperand(3), 1828 DAG.getCondCode(CCCode)); 1829} 1830 1831SDOperand DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 1832 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 1833 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 1834 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 1835 1836 // If ExpandSetCCOperands returned a scalar, use it. 1837 if (NewRHS.Val == 0) { 1838 assert(NewLHS.getValueType() == N->getValueType(0) && 1839 "Unexpected setcc expansion!"); 1840 return NewLHS; 1841 } 1842 1843 // Otherwise, update N to have the operands specified. 1844 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS, 1845 DAG.getCondCode(CCCode)); 1846} 1847 1848/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 1849/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1850void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDOperand &NewLHS, 1851 SDOperand &NewRHS, 1852 ISD::CondCode &CCCode) { 1853 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1854 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 1855 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 1856 1857 MVT VT = NewLHS.getValueType(); 1858 1859 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 1860 if (RHSLo == RHSHi) { 1861 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 1862 if (RHSCST->isAllOnesValue()) { 1863 // Equality comparison to -1. 1864 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1865 NewRHS = RHSLo; 1866 return; 1867 } 1868 } 1869 } 1870 1871 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1872 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1873 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS); 1874 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1875 return; 1876 } 1877 1878 // If this is a comparison of the sign bit, just look at the top part. 1879 // X > -1, x < 0 1880 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 1881 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 1882 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 1883 NewLHS = LHSHi; 1884 NewRHS = RHSHi; 1885 return; 1886 } 1887 1888 // FIXME: This generated code sucks. 1889 ISD::CondCode LowCC; 1890 switch (CCCode) { 1891 default: assert(0 && "Unknown integer setcc!"); 1892 case ISD::SETLT: 1893 case ISD::SETULT: LowCC = ISD::SETULT; break; 1894 case ISD::SETGT: 1895 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1896 case ISD::SETLE: 1897 case ISD::SETULE: LowCC = ISD::SETULE; break; 1898 case ISD::SETGE: 1899 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1900 } 1901 1902 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1903 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1904 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1905 1906 // NOTE: on targets without efficient SELECT of bools, we can always use 1907 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1908 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 1909 SDOperand Tmp1, Tmp2; 1910 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC, 1911 false, DagCombineInfo); 1912 if (!Tmp1.Val) 1913 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 1914 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1915 CCCode, false, DagCombineInfo); 1916 if (!Tmp2.Val) 1917 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1918 DAG.getCondCode(CCCode)); 1919 1920 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 1921 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 1922 if ((Tmp1C && Tmp1C->isNullValue()) || 1923 (Tmp2C && Tmp2C->isNullValue() && 1924 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 1925 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 1926 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 1927 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 1928 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 1929 // low part is known false, returns high part. 1930 // For LE / GE, if high part is known false, ignore the low part. 1931 // For LT / GT, if high part is known true, ignore the low part. 1932 NewLHS = Tmp2; 1933 NewRHS = SDOperand(); 1934 return; 1935 } 1936 1937 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1938 ISD::SETEQ, false, DagCombineInfo); 1939 if (!NewLHS.Val) 1940 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1941 ISD::SETEQ); 1942 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1943 NewLHS, Tmp1, Tmp2); 1944 NewRHS = SDOperand(); 1945} 1946 1947SDOperand DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 1948 if (ISD::isNormalStore(N)) 1949 return ExpandOp_NormalStore(N, OpNo); 1950 1951 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 1952 assert(OpNo == 1 && "Can only expand the stored value so far"); 1953 1954 MVT VT = N->getOperand(1).getValueType(); 1955 MVT NVT = TLI.getTypeToTransformTo(VT); 1956 SDOperand Ch = N->getChain(); 1957 SDOperand Ptr = N->getBasePtr(); 1958 int SVOffset = N->getSrcValueOffset(); 1959 unsigned Alignment = N->getAlignment(); 1960 bool isVolatile = N->isVolatile(); 1961 SDOperand Lo, Hi; 1962 1963 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1964 1965 if (N->getMemoryVT().bitsLE(NVT)) { 1966 GetExpandedInteger(N->getValue(), Lo, Hi); 1967 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 1968 N->getMemoryVT(), isVolatile, Alignment); 1969 } else if (TLI.isLittleEndian()) { 1970 // Little-endian - low bits are at low addresses. 1971 GetExpandedInteger(N->getValue(), Lo, Hi); 1972 1973 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 1974 isVolatile, Alignment); 1975 1976 unsigned ExcessBits = 1977 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1978 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1979 1980 // Increment the pointer to the other half. 1981 unsigned IncrementSize = NVT.getSizeInBits()/8; 1982 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1983 DAG.getIntPtrConstant(IncrementSize)); 1984 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 1985 SVOffset+IncrementSize, NEVT, 1986 isVolatile, MinAlign(Alignment, IncrementSize)); 1987 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1988 } else { 1989 // Big-endian - high bits are at low addresses. Favor aligned stores at 1990 // the cost of some bit-fiddling. 1991 GetExpandedInteger(N->getValue(), Lo, Hi); 1992 1993 MVT EVT = N->getMemoryVT(); 1994 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1995 unsigned IncrementSize = NVT.getSizeInBits()/8; 1996 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1997 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); 1998 1999 if (ExcessBits < NVT.getSizeInBits()) { 2000 // Transfer high bits from the top of Lo to the bottom of Hi. 2001 Hi = DAG.getNode(ISD::SHL, NVT, Hi, 2002 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2003 TLI.getShiftAmountTy())); 2004 Hi = DAG.getNode(ISD::OR, NVT, Hi, 2005 DAG.getNode(ISD::SRL, NVT, Lo, 2006 DAG.getConstant(ExcessBits, 2007 TLI.getShiftAmountTy()))); 2008 } 2009 2010 // Store both the high bits and maybe some of the low bits. 2011 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2012 SVOffset, HiVT, isVolatile, Alignment); 2013 2014 // Increment the pointer to the other half. 2015 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2016 DAG.getIntPtrConstant(IncrementSize)); 2017 // Store the lowest ExcessBits bits in the second half. 2018 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), 2019 SVOffset+IncrementSize, 2020 MVT::getIntegerVT(ExcessBits), 2021 isVolatile, MinAlign(Alignment, IncrementSize)); 2022 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2023 } 2024} 2025