LegalizeIntegerTypes.cpp revision dc5901ac9279b8635acf1ed8d8877e5bd82eb45d
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22using namespace llvm; 23 24//===----------------------------------------------------------------------===// 25// Integer Result Promotion 26//===----------------------------------------------------------------------===// 27 28/// PromoteIntegerResult - This method is called when a result of a node is 29/// found to be in need of promotion to a larger type. At this point, the node 30/// may also have invalid operands or may have other results that need 31/// expansion, we just know that (at least) one result needs promotion. 32void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n"); 34 SDValue Result = SDValue(); 35 36 // See if the target wants to custom expand this node. 37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 38 TargetLowering::Custom) { 39 // If the target wants to, allow it to lower this itself. 40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 41 // Everything that once used N now uses P. We are guaranteed that the 42 // result value types of N and the result value types of P match. 43 ReplaceNodeWith(N, P); 44 return; 45 } 46 } 47 48 switch (N->getOpcode()) { 49 default: 50#ifndef NDEBUG 51 cerr << "PromoteIntegerResult #" << ResNo << ": "; 52 N->dump(&DAG); cerr << "\n"; 53#endif 54 assert(0 && "Do not know how to promote this operator!"); 55 abort(); 56 case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break; 57 case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break; 58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break; 59 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break; 60 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break; 61 case ISD::Constant: Result = PromoteIntRes_Constant(N); break; 62 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break; 63 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break; 64 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break; 65 case ISD::EXTRACT_VECTOR_ELT: 66 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 67 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 68 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break; 69 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break; 70 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break; 71 case ISD::SHL: Result = PromoteIntRes_SHL(N); break; 72 case ISD::SIGN_EXTEND_INREG: 73 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 74 case ISD::SRA: Result = PromoteIntRes_SRA(N); break; 75 case ISD::SRL: Result = PromoteIntRes_SRL(N); break; 76 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break; 77 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break; 78 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break; 79 80 case ISD::SIGN_EXTEND: 81 case ISD::ZERO_EXTEND: 82 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break; 83 84 case ISD::FP_TO_SINT: 85 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break; 86 87 case ISD::AND: 88 case ISD::OR: 89 case ISD::XOR: 90 case ISD::ADD: 91 case ISD::SUB: 92 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break; 93 94 case ISD::SDIV: 95 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break; 96 97 case ISD::UDIV: 98 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break; 99 } 100 101 // If Result is null, the sub-method took care of registering the result. 102 if (Result.getNode()) 103 SetPromotedInteger(SDValue(N, ResNo), Result); 104} 105 106SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 107 // Sign-extend the new bits, and continue the assertion. 108 MVT OldVT = N->getValueType(0); 109 SDValue Op = GetPromotedInteger(N->getOperand(0)); 110 return DAG.getNode(ISD::AssertSext, Op.getValueType(), 111 DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, 112 DAG.getValueType(OldVT)), N->getOperand(1)); 113} 114 115SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 116 // Zero the new bits, and continue the assertion. 117 MVT OldVT = N->getValueType(0); 118 SDValue Op = GetPromotedInteger(N->getOperand(0)); 119 return DAG.getNode(ISD::AssertZext, Op.getValueType(), 120 DAG.getZeroExtendInReg(Op, OldVT), N->getOperand(1)); 121} 122 123SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 124 SDValue InOp = N->getOperand(0); 125 MVT InVT = InOp.getValueType(); 126 MVT NInVT = TLI.getTypeToTransformTo(InVT); 127 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 128 129 switch (getTypeAction(InVT)) { 130 default: 131 assert(false && "Unknown type action!"); 132 break; 133 case Legal: 134 break; 135 case PromoteInteger: 136 if (OutVT.getSizeInBits() == NInVT.getSizeInBits()) 137 // The input promotes to the same size. Convert the promoted value. 138 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp)); 139 break; 140 case SoftenFloat: 141 // Promote the integer operand by hand. 142 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp)); 143 case ExpandInteger: 144 case ExpandFloat: 145 break; 146 case ScalarizeVector: 147 // Convert the element to an integer and promote it by hand. 148 return DAG.getNode(ISD::ANY_EXTEND, OutVT, 149 BitConvertToInteger(GetScalarizedVector(InOp))); 150 case SplitVector: 151 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 152 // pieces of the input into integers and reassemble in the final type. 153 SDValue Lo, Hi; 154 GetSplitVector(N->getOperand(0), Lo, Hi); 155 Lo = BitConvertToInteger(Lo); 156 Hi = BitConvertToInteger(Hi); 157 158 if (TLI.isBigEndian()) 159 std::swap(Lo, Hi); 160 161 InOp = DAG.getNode(ISD::ANY_EXTEND, 162 MVT::getIntegerVT(OutVT.getSizeInBits()), 163 JoinIntegers(Lo, Hi)); 164 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp); 165 } 166 167 // Otherwise, lower the bit-convert to a store/load from the stack, then 168 // promote the load. 169 SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0)); 170 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode())); 171} 172 173SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 174 SDValue Op = GetPromotedInteger(N->getOperand(0)); 175 MVT OVT = N->getValueType(0); 176 MVT NVT = Op.getValueType(); 177 178 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 179 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op), 180 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 181} 182 183SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 184 // The pair element type may be legal, or may not promote to the same type as 185 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 186 return DAG.getNode(ISD::ANY_EXTEND, 187 TLI.getTypeToTransformTo(N->getValueType(0)), 188 JoinIntegers(N->getOperand(0), N->getOperand(1))); 189} 190 191SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 192 MVT VT = N->getValueType(0); 193 // Zero extend things like i1, sign extend everything else. It shouldn't 194 // matter in theory which one we pick, but this tends to give better code? 195 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 196 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), 197 SDValue(N, 0)); 198 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 199 return Result; 200} 201 202SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 203 SDValue Op = GetPromotedInteger(N->getOperand(0)); 204 MVT OVT = N->getValueType(0); 205 MVT NVT = Op.getValueType(); 206 // Zero extend to the promoted type and do the count there. 207 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT)); 208 // Subtract off the extra leading bits in the bigger type. 209 return DAG.getNode(ISD::SUB, NVT, Op, 210 DAG.getConstant(NVT.getSizeInBits() - 211 OVT.getSizeInBits(), NVT)); 212} 213 214SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 215 SDValue Op = GetPromotedInteger(N->getOperand(0)); 216 MVT OVT = N->getValueType(0); 217 MVT NVT = Op.getValueType(); 218 // Zero extend to the promoted type and do the count there. 219 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT)); 220} 221 222SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 223 SDValue Op = GetPromotedInteger(N->getOperand(0)); 224 MVT OVT = N->getValueType(0); 225 MVT NVT = Op.getValueType(); 226 // The count is the same in the promoted type except if the original 227 // value was zero. This can be handled by setting the bit just off 228 // the top of the original type. 229 APInt TopBit(NVT.getSizeInBits(), 0); 230 TopBit.set(OVT.getSizeInBits()); 231 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT)); 232 return DAG.getNode(ISD::CTTZ, NVT, Op); 233} 234 235SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 236 MVT OldVT = N->getValueType(0); 237 SDValue OldVec = N->getOperand(0); 238 unsigned OldElts = OldVec.getValueType().getVectorNumElements(); 239 240 if (OldElts == 1) { 241 assert(!isTypeLegal(OldVec.getValueType()) && 242 "Legal one-element vector of a type needing promotion!"); 243 // It is tempting to follow GetScalarizedVector by a call to 244 // GetPromotedInteger, but this would be wrong because the 245 // scalarized value may not yet have been processed. 246 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT), 247 GetScalarizedVector(OldVec)); 248 } 249 250 // Convert to a vector half as long with an element type of twice the width, 251 // for example <4 x i16> -> <2 x i32>. 252 assert(!(OldElts & 1) && "Odd length vectors not supported!"); 253 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 254 assert(OldVT.isSimple() && NewVT.isSimple()); 255 256 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, 257 MVT::getVectorVT(NewVT, OldElts / 2), 258 OldVec); 259 260 // Extract the element at OldIdx / 2 from the new vector. 261 SDValue OldIdx = N->getOperand(1); 262 SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx, 263 DAG.getConstant(1, TLI.getShiftAmountTy())); 264 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx); 265 266 // Select the appropriate half of the element: Lo if OldIdx was even, 267 // Hi if it was odd. 268 SDValue Lo = Elt; 269 SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt, 270 DAG.getConstant(OldVT.getSizeInBits(), 271 TLI.getShiftAmountTy())); 272 if (TLI.isBigEndian()) 273 std::swap(Lo, Hi); 274 275 SDValue Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx, 276 DAG.getConstant(1, TLI.getShiftAmountTy())); 277 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo); 278} 279 280SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 281 unsigned NewOpc = N->getOpcode(); 282 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 283 284 // If we're promoting a UINT to a larger size, check to see if the new node 285 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 286 // we can use that instead. This allows us to generate better code for 287 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 288 // legal, such as PowerPC. 289 if (N->getOpcode() == ISD::FP_TO_UINT) { 290 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 291 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 292 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)) 293 NewOpc = ISD::FP_TO_SINT; 294 } 295 296 return DAG.getNode(NewOpc, NVT, N->getOperand(0)); 297} 298 299SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 300 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 301 302 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 303 SDValue Res = GetPromotedInteger(N->getOperand(0)); 304 assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() && 305 "Extension doesn't make sense!"); 306 307 // If the result and operand types are the same after promotion, simplify 308 // to an in-register extension. 309 if (NVT == Res.getValueType()) { 310 // The high bits are not guaranteed to be anything. Insert an extend. 311 if (N->getOpcode() == ISD::SIGN_EXTEND) 312 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, 313 DAG.getValueType(N->getOperand(0).getValueType())); 314 if (N->getOpcode() == ISD::ZERO_EXTEND) 315 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); 316 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 317 return Res; 318 } 319 } 320 321 // Otherwise, just extend the original operand all the way to the larger type. 322 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0)); 323} 324 325SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 326 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 327 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 328 ISD::LoadExtType ExtType = 329 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 330 SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(), 331 N->getSrcValue(), N->getSrcValueOffset(), 332 N->getMemoryVT(), N->isVolatile(), 333 N->getAlignment()); 334 335 // Legalized the chain result - switch anything that used the old chain to 336 // use the new one. 337 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 338 return Res; 339} 340 341SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 342 // Sign extend the input. 343 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 344 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 345 MVT VT = N->getValueType(0); 346 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS, 347 DAG.getValueType(VT)); 348 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS, 349 DAG.getValueType(VT)); 350 351 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 352} 353 354SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 355 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 356 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 357 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS); 358} 359 360SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 361 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 362 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 363 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0), 364 N->getOperand(1), LHS, RHS, N->getOperand(4)); 365} 366 367SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 368 assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0))) 369 && "SetCC type is not legal??"); 370 return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)), 371 N->getOperand(0), N->getOperand(1), N->getOperand(2)); 372} 373 374SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 375 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)), 376 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 377} 378 379SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 380 SDValue Op = GetPromotedInteger(N->getOperand(0)); 381 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, 382 N->getOperand(1)); 383} 384 385SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 386 // The input may have strange things in the top bits of the registers, but 387 // these operations don't care. They may have weird bits going out, but 388 // that too is okay if they are integer operations. 389 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 390 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 391 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 392} 393 394SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 395 // The input value must be properly sign extended. 396 MVT VT = N->getValueType(0); 397 MVT NVT = TLI.getTypeToTransformTo(VT); 398 SDValue Res = GetPromotedInteger(N->getOperand(0)); 399 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT)); 400 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1)); 401} 402 403SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 404 // The input value must be properly zero extended. 405 MVT VT = N->getValueType(0); 406 MVT NVT = TLI.getTypeToTransformTo(VT); 407 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 408 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1)); 409} 410 411SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 412 SDValue Res; 413 414 switch (getTypeAction(N->getOperand(0).getValueType())) { 415 default: assert(0 && "Unknown type action!"); 416 case Legal: 417 case ExpandInteger: 418 Res = N->getOperand(0); 419 break; 420 case PromoteInteger: 421 Res = GetPromotedInteger(N->getOperand(0)); 422 break; 423 } 424 425 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 426 assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() && 427 "Truncation doesn't make sense!"); 428 if (Res.getValueType() == NVT) 429 return Res; 430 431 // Truncate to NVT instead of VT 432 return DAG.getNode(ISD::TRUNCATE, NVT, Res); 433} 434 435SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 436 // Zero extend the input. 437 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 438 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 439 MVT VT = N->getValueType(0); 440 LHS = DAG.getZeroExtendInReg(LHS, VT); 441 RHS = DAG.getZeroExtendInReg(RHS, VT); 442 443 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 444} 445 446SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 447 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0))); 448} 449 450SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 451 SDValue Chain = N->getOperand(0); // Get the chain. 452 SDValue Ptr = N->getOperand(1); // Get the pointer. 453 MVT VT = N->getValueType(0); 454 455 const Value *V = cast<SrcValueSDNode>(N->getOperand(2))->getValue(); 456 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Chain, Ptr, V, 0); 457 458 // Increment the arg pointer, VAList, to the next vaarg 459 // FIXME: should the ABI size be used for the increment? Think of 460 // x86 long double (10 bytes long, but aligned on 4 or 8 bytes) or 461 // integers of unusual size (such MVT::i1, which gives an increment 462 // of zero here!). 463 unsigned Increment = VT.getSizeInBits() / 8; 464 SDValue Tmp = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 465 DAG.getConstant(Increment, TLI.getPointerTy())); 466 467 // Store the incremented VAList to the pointer. 468 Tmp = DAG.getStore(VAList.getValue(1), Tmp, Ptr, V, 0); 469 470 // Load the actual argument out of the arg pointer VAList. 471 Tmp = DAG.getExtLoad(ISD::EXTLOAD, TLI.getTypeToTransformTo(VT), Tmp, 472 VAList, NULL, 0, VT); 473 474 // Legalized the chain result - switch anything that used the old chain to 475 // use the new one. 476 ReplaceValueWith(SDValue(N, 1), Tmp.getValue(1)); 477 return Tmp; 478} 479 480 481//===----------------------------------------------------------------------===// 482// Integer Operand Promotion 483//===----------------------------------------------------------------------===// 484 485/// PromoteIntegerOperand - This method is called when the specified operand of 486/// the specified node is found to need promotion. At this point, all of the 487/// result types of the node are known to be legal, but other operands of the 488/// node may need promotion or expansion as well as the specified one. 489bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 490 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n"); 491 SDValue Res = SDValue(); 492 493 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 494 == TargetLowering::Custom) 495 Res = TLI.LowerOperation(SDValue(N, OpNo), DAG); 496 497 if (Res.getNode() == 0) { 498 switch (N->getOpcode()) { 499 default: 500 #ifndef NDEBUG 501 cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; 502 N->dump(&DAG); cerr << "\n"; 503 #endif 504 assert(0 && "Do not know how to promote this operator's operand!"); 505 abort(); 506 507 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 508 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 509 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 510 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 511 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 512 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break; 513 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break; 514 case ISD::INSERT_VECTOR_ELT: 515 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 516 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 517 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 518 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 519 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 520 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 521 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 522 OpNo); break; 523 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 524 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 525 526 case ISD::SINT_TO_FP: 527 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break; 528 } 529 } 530 531 // If the result is null, the sub-method took care of registering results etc. 532 if (!Res.getNode()) return false; 533 // If the result is N, the sub-method updated N in place. 534 if (Res.getNode() == N) { 535 // Mark N as new and remark N and its operands. This allows us to correctly 536 // revisit N if it needs another step of promotion and allows us to visit 537 // any new operands to N. 538 ReanalyzeNode(N); 539 return true; 540 } 541 542 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 543 "Invalid operand expansion"); 544 545 ReplaceValueWith(SDValue(N, 0), Res); 546 return false; 547} 548 549/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 550/// shared among BR_CC, SELECT_CC, and SETCC handlers. 551void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 552 ISD::CondCode CCCode) { 553 MVT VT = NewLHS.getValueType(); 554 555 // Get the promoted values. 556 NewLHS = GetPromotedInteger(NewLHS); 557 NewRHS = GetPromotedInteger(NewRHS); 558 559 // Otherwise, we have to insert explicit sign or zero extends. Note 560 // that we could insert sign extends for ALL conditions, but zero extend 561 // is cheaper on many machines (an AND instead of two shifts), so prefer 562 // it. 563 switch (CCCode) { 564 default: assert(0 && "Unknown integer comparison!"); 565 case ISD::SETEQ: 566 case ISD::SETNE: 567 case ISD::SETUGE: 568 case ISD::SETUGT: 569 case ISD::SETULE: 570 case ISD::SETULT: 571 // ALL of these operations will work if we either sign or zero extend 572 // the operands (including the unsigned comparisons!). Zero extend is 573 // usually a simpler/cheaper operation, so prefer it. 574 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT); 575 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT); 576 break; 577 case ISD::SETGE: 578 case ISD::SETGT: 579 case ISD::SETLT: 580 case ISD::SETLE: 581 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS, 582 DAG.getValueType(VT)); 583 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS, 584 DAG.getValueType(VT)); 585 break; 586 } 587} 588 589SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 590 SDValue Op = GetPromotedInteger(N->getOperand(0)); 591 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 592} 593 594SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 595 assert(OpNo == 2 && "Don't know how to promote this operand!"); 596 597 SDValue LHS = N->getOperand(2); 598 SDValue RHS = N->getOperand(3); 599 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 600 601 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 602 // legal types. 603 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 604 N->getOperand(1), LHS, RHS, N->getOperand(4)); 605} 606 607SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 608 assert(OpNo == 1 && "only know how to promote condition"); 609 SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition. 610 611 // The top bits of the promoted condition are not necessarily zero, ensure 612 // that the value is properly zero extended. 613 unsigned BitWidth = Cond.getValueSizeInBits(); 614 if (!DAG.MaskedValueIsZero(Cond, 615 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 616 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); 617 618 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 619 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond, 620 N->getOperand(2)); 621} 622 623SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 624 // Since the result type is legal, the operands must promote to it. 625 MVT OVT = N->getOperand(0).getValueType(); 626 SDValue Lo = GetPromotedInteger(N->getOperand(0)); 627 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 628 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 629 630 Lo = DAG.getZeroExtendInReg(Lo, OVT); 631 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi, 632 DAG.getConstant(OVT.getSizeInBits(), 633 TLI.getShiftAmountTy())); 634 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi); 635} 636 637SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 638 // The vector type is legal but the element type is not. This implies 639 // that the vector is a power-of-two in length and that the element 640 // type does not have a strange size (eg: it is not i1). 641 MVT VecVT = N->getValueType(0); 642 unsigned NumElts = VecVT.getVectorNumElements(); 643 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 644 645 // Build a vector of half the length out of elements of twice the bitwidth. 646 // For example <4 x i16> -> <2 x i32>. 647 MVT OldVT = N->getOperand(0).getValueType(); 648 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 649 assert(OldVT.isSimple() && NewVT.isSimple()); 650 651 std::vector<SDValue> NewElts; 652 NewElts.reserve(NumElts/2); 653 654 for (unsigned i = 0; i < NumElts; i += 2) { 655 // Combine two successive elements into one promoted element. 656 SDValue Lo = N->getOperand(i); 657 SDValue Hi = N->getOperand(i+1); 658 if (TLI.isBigEndian()) 659 std::swap(Lo, Hi); 660 NewElts.push_back(JoinIntegers(Lo, Hi)); 661 } 662 663 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, 664 MVT::getVectorVT(NewVT, NewElts.size()), 665 &NewElts[0], NewElts.size()); 666 667 // Convert the new vector to the old vector type. 668 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec); 669} 670 671SDValue DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) { 672 SDValue Op = GetPromotedInteger(N->getOperand(0)); 673 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op); 674} 675 676SDValue DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) { 677 SDValue Op = GetPromotedInteger(N->getOperand(0)); 678 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op, 679 DAG.getIntPtrConstant(0)); 680} 681 682SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 683 unsigned OpNo) { 684 if (OpNo == 1) { 685 // Promote the inserted value. This is valid because the type does not 686 // have to match the vector element type. 687 688 // Check that any extra bits introduced will be truncated away. 689 assert(N->getOperand(1).getValueType().getSizeInBits() >= 690 N->getValueType(0).getVectorElementType().getSizeInBits() && 691 "Type of inserted value narrower than vector element type!"); 692 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 693 GetPromotedInteger(N->getOperand(1)), 694 N->getOperand(2)); 695 } 696 697 assert(OpNo == 2 && "Different operand and result vector types?"); 698 699 // Promote the index. 700 SDValue Idx = N->getOperand(2); 701 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType()); 702 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 703 N->getOperand(1), Idx); 704} 705 706SDValue DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) { 707 SDValue In = GetPromotedInteger(N->getOperand(0)); 708 MVT OpVT = N->getOperand(0).getValueType(); 709 if (N->getOpcode() == ISD::UINT_TO_FP) 710 In = DAG.getZeroExtendInReg(In, OpVT); 711 else 712 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), 713 In, DAG.getValueType(OpVT)); 714 715 return DAG.UpdateNodeOperands(SDValue(N, 0), In); 716} 717 718SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 719 SDValue NewOps[6]; 720 NewOps[0] = N->getOperand(0); 721 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 722 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 723 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1); 724 } 725 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, 726 array_lengthof(NewOps)); 727} 728 729SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 730 assert(OpNo == 0 && "Only know how to promote condition"); 731 SDValue Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition. 732 733 // The top bits of the promoted condition are not necessarily zero, ensure 734 // that the value is properly zero extended. 735 unsigned BitWidth = Cond.getValueSizeInBits(); 736 if (!DAG.MaskedValueIsZero(Cond, 737 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 738 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); 739 740 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 741 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, N->getOperand(1), 742 N->getOperand(2)); 743} 744 745SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 746 assert(OpNo == 0 && "Don't know how to promote this operand!"); 747 748 SDValue LHS = N->getOperand(0); 749 SDValue RHS = N->getOperand(1); 750 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 751 752 // The CC (#4) and the possible return values (#2 and #3) have legal types. 753 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2), 754 N->getOperand(3), N->getOperand(4)); 755} 756 757SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 758 assert(OpNo == 0 && "Don't know how to promote this operand!"); 759 760 SDValue LHS = N->getOperand(0); 761 SDValue RHS = N->getOperand(1); 762 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 763 764 // The CC (#2) is always legal. 765 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2)); 766} 767 768SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 769 SDValue Op = GetPromotedInteger(N->getOperand(0)); 770 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), 772 Op, DAG.getValueType(N->getOperand(0).getValueType())); 773} 774 775SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 776 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 777 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 778 int SVOffset = N->getSrcValueOffset(); 779 unsigned Alignment = N->getAlignment(); 780 bool isVolatile = N->isVolatile(); 781 782 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 783 784 assert(!N->isTruncatingStore() && "Cannot promote this store operand!"); 785 786 // Truncate the value and store the result. 787 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(), 788 SVOffset, N->getMemoryVT(), 789 isVolatile, Alignment); 790} 791 792SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 793 SDValue Op = GetPromotedInteger(N->getOperand(0)); 794 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op); 795} 796 797SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 798 SDValue Op = GetPromotedInteger(N->getOperand(0)); 799 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 800 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); 801} 802 803 804//===----------------------------------------------------------------------===// 805// Integer Result Expansion 806//===----------------------------------------------------------------------===// 807 808/// ExpandIntegerResult - This method is called when the specified result of the 809/// specified node is found to need expansion. At this point, the node may also 810/// have invalid operands or may have other results that need promotion, we just 811/// know that (at least) one result needs expansion. 812void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 813 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n"); 814 SDValue Lo, Hi; 815 Lo = Hi = SDValue(); 816 817 // See if the target wants to custom expand this node. 818 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 819 TargetLowering::Custom) { 820 // If the target wants to, allow it to lower this itself. 821 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 822 // Everything that once used N now uses P. We are guaranteed that the 823 // result value types of N and the result value types of P match. 824 ReplaceNodeWith(N, P); 825 return; 826 } 827 } 828 829 switch (N->getOpcode()) { 830 default: 831#ifndef NDEBUG 832 cerr << "ExpandIntegerResult #" << ResNo << ": "; 833 N->dump(&DAG); cerr << "\n"; 834#endif 835 assert(0 && "Do not know how to expand the result of this operator!"); 836 abort(); 837 838 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 839 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 840 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 841 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 842 843 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 844 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 845 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 846 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 847 848 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 849 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 850 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 851 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 852 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 853 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 854 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 855 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 856 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 857 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 858 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 859 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 860 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 861 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 862 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 863 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 864 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 865 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 866 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 867 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 868 869 case ISD::AND: 870 case ISD::OR: 871 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 872 873 case ISD::ADD: 874 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 875 876 case ISD::ADDC: 877 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 878 879 case ISD::ADDE: 880 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 881 882 case ISD::SHL: 883 case ISD::SRA: 884 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 885 } 886 887 // If Lo/Hi is null, the sub-method took care of registering results etc. 888 if (Lo.getNode()) 889 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 890} 891 892/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 893/// and the shift amount is a constant 'Amt'. Expand the operation. 894void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 895 SDValue &Lo, SDValue &Hi) { 896 // Expand the incoming operand to be shifted, so that we have its parts 897 SDValue InL, InH; 898 GetExpandedInteger(N->getOperand(0), InL, InH); 899 900 MVT NVT = InL.getValueType(); 901 unsigned VTBits = N->getValueType(0).getSizeInBits(); 902 unsigned NVTBits = NVT.getSizeInBits(); 903 MVT ShTy = N->getOperand(1).getValueType(); 904 905 if (N->getOpcode() == ISD::SHL) { 906 if (Amt > VTBits) { 907 Lo = Hi = DAG.getConstant(0, NVT); 908 } else if (Amt > NVTBits) { 909 Lo = DAG.getConstant(0, NVT); 910 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 911 } else if (Amt == NVTBits) { 912 Lo = DAG.getConstant(0, NVT); 913 Hi = InL; 914 } else if (Amt == 1) { 915 // Emit this X << 1 as X+X. 916 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 917 SDValue LoOps[2] = { InL, InL }; 918 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 919 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 920 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 921 } else { 922 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy)); 923 Hi = DAG.getNode(ISD::OR, NVT, 924 DAG.getNode(ISD::SHL, NVT, InH, 925 DAG.getConstant(Amt, ShTy)), 926 DAG.getNode(ISD::SRL, NVT, InL, 927 DAG.getConstant(NVTBits-Amt, ShTy))); 928 } 929 return; 930 } 931 932 if (N->getOpcode() == ISD::SRL) { 933 if (Amt > VTBits) { 934 Lo = DAG.getConstant(0, NVT); 935 Hi = DAG.getConstant(0, NVT); 936 } else if (Amt > NVTBits) { 937 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 938 Hi = DAG.getConstant(0, NVT); 939 } else if (Amt == NVTBits) { 940 Lo = InH; 941 Hi = DAG.getConstant(0, NVT); 942 } else { 943 Lo = DAG.getNode(ISD::OR, NVT, 944 DAG.getNode(ISD::SRL, NVT, InL, 945 DAG.getConstant(Amt, ShTy)), 946 DAG.getNode(ISD::SHL, NVT, InH, 947 DAG.getConstant(NVTBits-Amt, ShTy))); 948 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy)); 949 } 950 return; 951 } 952 953 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 954 if (Amt > VTBits) { 955 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 956 DAG.getConstant(NVTBits-1, ShTy)); 957 } else if (Amt > NVTBits) { 958 Lo = DAG.getNode(ISD::SRA, NVT, InH, 959 DAG.getConstant(Amt-NVTBits, ShTy)); 960 Hi = DAG.getNode(ISD::SRA, NVT, InH, 961 DAG.getConstant(NVTBits-1, ShTy)); 962 } else if (Amt == NVTBits) { 963 Lo = InH; 964 Hi = DAG.getNode(ISD::SRA, NVT, InH, 965 DAG.getConstant(NVTBits-1, ShTy)); 966 } else { 967 Lo = DAG.getNode(ISD::OR, NVT, 968 DAG.getNode(ISD::SRL, NVT, InL, 969 DAG.getConstant(Amt, ShTy)), 970 DAG.getNode(ISD::SHL, NVT, InH, 971 DAG.getConstant(NVTBits-Amt, ShTy))); 972 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy)); 973 } 974} 975 976/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 977/// this shift based on knowledge of the high bit of the shift amount. If we 978/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 979/// shift amount. 980bool DAGTypeLegalizer:: 981ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 982 SDValue Amt = N->getOperand(1); 983 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 984 MVT ShTy = Amt.getValueType(); 985 unsigned ShBits = ShTy.getSizeInBits(); 986 unsigned NVTBits = NVT.getSizeInBits(); 987 assert(isPowerOf2_32(NVTBits) && 988 "Expanded integer type size not a power of two!"); 989 990 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 991 APInt KnownZero, KnownOne; 992 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 993 994 // If we don't know anything about the high bits, exit. 995 if (((KnownZero|KnownOne) & HighBitMask) == 0) 996 return false; 997 998 // Get the incoming operand to be shifted. 999 SDValue InL, InH; 1000 GetExpandedInteger(N->getOperand(0), InL, InH); 1001 1002 // If we know that any of the high bits of the shift amount are one, then we 1003 // can do this as a couple of simple shifts. 1004 if (KnownOne.intersects(HighBitMask)) { 1005 // Mask out the high bit, which we know is set. 1006 Amt = DAG.getNode(ISD::AND, ShTy, Amt, 1007 DAG.getConstant(~HighBitMask, ShTy)); 1008 1009 switch (N->getOpcode()) { 1010 default: assert(0 && "Unknown shift"); 1011 case ISD::SHL: 1012 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1013 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 1014 return true; 1015 case ISD::SRL: 1016 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1017 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 1018 return true; 1019 case ISD::SRA: 1020 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 1021 DAG.getConstant(NVTBits-1, ShTy)); 1022 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 1023 return true; 1024 } 1025 } 1026 1027 // If we know that all of the high bits of the shift amount are zero, then we 1028 // can do this as a couple of simple shifts. 1029 if ((KnownZero & HighBitMask) == HighBitMask) { 1030 // Compute 32-amt. 1031 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1032 DAG.getConstant(NVTBits, ShTy), 1033 Amt); 1034 unsigned Op1, Op2; 1035 switch (N->getOpcode()) { 1036 default: assert(0 && "Unknown shift"); 1037 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1038 case ISD::SRL: 1039 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1040 } 1041 1042 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1043 Hi = DAG.getNode(ISD::OR, NVT, 1044 DAG.getNode(Op1, NVT, InH, Amt), 1045 DAG.getNode(Op2, NVT, InL, Amt2)); 1046 return true; 1047 } 1048 1049 return false; 1050} 1051 1052void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1053 SDValue &Lo, SDValue &Hi) { 1054 // Expand the subcomponents. 1055 SDValue LHSL, LHSH, RHSL, RHSH; 1056 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1057 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1058 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1059 SDValue LoOps[2] = { LHSL, RHSL }; 1060 SDValue HiOps[3] = { LHSH, RHSH }; 1061 1062 if (N->getOpcode() == ISD::ADD) { 1063 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1064 HiOps[2] = Lo.getValue(1); 1065 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1066 } else { 1067 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1068 HiOps[2] = Lo.getValue(1); 1069 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1070 } 1071} 1072 1073void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1074 SDValue &Lo, SDValue &Hi) { 1075 // Expand the subcomponents. 1076 SDValue LHSL, LHSH, RHSL, RHSH; 1077 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1078 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1079 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1080 SDValue LoOps[2] = { LHSL, RHSL }; 1081 SDValue HiOps[3] = { LHSH, RHSH }; 1082 1083 if (N->getOpcode() == ISD::ADDC) { 1084 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1085 HiOps[2] = Lo.getValue(1); 1086 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1087 } else { 1088 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1089 HiOps[2] = Lo.getValue(1); 1090 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1091 } 1092 1093 // Legalized the flag result - switch anything that used the old flag to 1094 // use the new one. 1095 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1096} 1097 1098void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1099 SDValue &Lo, SDValue &Hi) { 1100 // Expand the subcomponents. 1101 SDValue LHSL, LHSH, RHSL, RHSH; 1102 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1103 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1104 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1105 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1106 SDValue HiOps[3] = { LHSH, RHSH }; 1107 1108 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3); 1109 HiOps[2] = Lo.getValue(1); 1110 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3); 1111 1112 // Legalized the flag result - switch anything that used the old flag to 1113 // use the new one. 1114 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1115} 1116 1117void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1118 SDValue &Lo, SDValue &Hi) { 1119 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1120 SDValue Op = N->getOperand(0); 1121 if (Op.getValueType().bitsLE(NVT)) { 1122 // The low part is any extension of the input (which degenerates to a copy). 1123 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op); 1124 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined. 1125 } else { 1126 // For example, extension of an i48 to an i64. The operand type necessarily 1127 // promotes to the result type, so will end up being expanded too. 1128 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1129 "Only know how to promote this result!"); 1130 SDValue Res = GetPromotedInteger(Op); 1131 assert(Res.getValueType() == N->getValueType(0) && 1132 "Operand over promoted?"); 1133 // Split the promoted operand. This will simplify when it is expanded. 1134 SplitInteger(Res, Lo, Hi); 1135 } 1136} 1137 1138void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1139 SDValue &Lo, SDValue &Hi) { 1140 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1141 MVT NVT = Lo.getValueType(); 1142 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1143 unsigned NVTBits = NVT.getSizeInBits(); 1144 unsigned EVTBits = EVT.getSizeInBits(); 1145 1146 if (NVTBits < EVTBits) { 1147 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi, 1148 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1149 } else { 1150 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT)); 1151 // The high part replicates the sign bit of Lo, make it explicit. 1152 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1153 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy())); 1154 } 1155} 1156 1157void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1158 SDValue &Lo, SDValue &Hi) { 1159 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1160 MVT NVT = Lo.getValueType(); 1161 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1162 unsigned NVTBits = NVT.getSizeInBits(); 1163 unsigned EVTBits = EVT.getSizeInBits(); 1164 1165 if (NVTBits < EVTBits) { 1166 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi, 1167 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1168 } else { 1169 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT)); 1170 // The high part must be zero, make it explicit. 1171 Hi = DAG.getConstant(0, NVT); 1172 } 1173} 1174 1175void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1176 SDValue &Lo, SDValue &Hi) { 1177 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1178 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo); 1179 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi); 1180} 1181 1182void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1183 SDValue &Lo, SDValue &Hi) { 1184 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1185 unsigned NBitWidth = NVT.getSizeInBits(); 1186 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1187 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 1188 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1189} 1190 1191void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1192 SDValue &Lo, SDValue &Hi) { 1193 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1194 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1195 MVT NVT = Lo.getValueType(); 1196 1197 SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 1198 DAG.getConstant(0, NVT), ISD::SETNE); 1199 1200 SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo); 1201 SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 1202 1203 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ, 1204 DAG.getNode(ISD::ADD, NVT, LoLZ, 1205 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1206 Hi = DAG.getConstant(0, NVT); 1207} 1208 1209void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1210 SDValue &Lo, SDValue &Hi) { 1211 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1212 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1213 MVT NVT = Lo.getValueType(); 1214 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), 1215 DAG.getNode(ISD::CTPOP, NVT, Hi)); 1216 Hi = DAG.getConstant(0, NVT); 1217} 1218 1219void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1220 SDValue &Lo, SDValue &Hi) { 1221 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1222 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1223 MVT NVT = Lo.getValueType(); 1224 1225 SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, 1226 DAG.getConstant(0, NVT), ISD::SETNE); 1227 1228 SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 1229 SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi); 1230 1231 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ, 1232 DAG.getNode(ISD::ADD, NVT, HiLZ, 1233 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1234 Hi = DAG.getConstant(0, NVT); 1235} 1236 1237void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1238 SDValue &Hi) { 1239 MVT VT = N->getValueType(0); 1240 SDValue Op = N->getOperand(0); 1241 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1242 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1243 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi); 1244} 1245 1246void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1247 SDValue &Hi) { 1248 MVT VT = N->getValueType(0); 1249 SDValue Op = N->getOperand(0); 1250 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1251 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1252 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi); 1253} 1254 1255void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1256 SDValue &Lo, SDValue &Hi) { 1257 if (ISD::isNormalLoad(N)) { 1258 ExpandRes_NormalLoad(N, Lo, Hi); 1259 return; 1260 } 1261 1262 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1263 1264 MVT VT = N->getValueType(0); 1265 MVT NVT = TLI.getTypeToTransformTo(VT); 1266 SDValue Ch = N->getChain(); 1267 SDValue Ptr = N->getBasePtr(); 1268 ISD::LoadExtType ExtType = N->getExtensionType(); 1269 int SVOffset = N->getSrcValueOffset(); 1270 unsigned Alignment = N->getAlignment(); 1271 bool isVolatile = N->isVolatile(); 1272 1273 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1274 1275 if (N->getMemoryVT().bitsLE(NVT)) { 1276 MVT EVT = N->getMemoryVT(); 1277 1278 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT, 1279 isVolatile, Alignment); 1280 1281 // Remember the chain. 1282 Ch = Lo.getValue(1); 1283 1284 if (ExtType == ISD::SEXTLOAD) { 1285 // The high part is obtained by SRA'ing all but one of the bits of the 1286 // lo part. 1287 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1288 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1289 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1290 } else if (ExtType == ISD::ZEXTLOAD) { 1291 // The high part is just a zero. 1292 Hi = DAG.getConstant(0, NVT); 1293 } else { 1294 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1295 // The high part is undefined. 1296 Hi = DAG.getNode(ISD::UNDEF, NVT); 1297 } 1298 } else if (TLI.isLittleEndian()) { 1299 // Little-endian - low bits are at low addresses. 1300 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1301 isVolatile, Alignment); 1302 1303 unsigned ExcessBits = 1304 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1305 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1306 1307 // Increment the pointer to the other half. 1308 unsigned IncrementSize = NVT.getSizeInBits()/8; 1309 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1310 DAG.getIntPtrConstant(IncrementSize)); 1311 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), 1312 SVOffset+IncrementSize, NEVT, 1313 isVolatile, MinAlign(Alignment, IncrementSize)); 1314 1315 // Build a factor node to remember that this load is independent of the 1316 // other one. 1317 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1318 Hi.getValue(1)); 1319 } else { 1320 // Big-endian - high bits are at low addresses. Favor aligned loads at 1321 // the cost of some bit-fiddling. 1322 MVT EVT = N->getMemoryVT(); 1323 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1324 unsigned IncrementSize = NVT.getSizeInBits()/8; 1325 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1326 1327 // Load both the high bits and maybe some of the low bits. 1328 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1329 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), 1330 isVolatile, Alignment); 1331 1332 // Increment the pointer to the other half. 1333 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1334 DAG.getIntPtrConstant(IncrementSize)); 1335 // Load the rest of the low bits. 1336 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(), 1337 SVOffset+IncrementSize, 1338 MVT::getIntegerVT(ExcessBits), 1339 isVolatile, MinAlign(Alignment, IncrementSize)); 1340 1341 // Build a factor node to remember that this load is independent of the 1342 // other one. 1343 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1344 Hi.getValue(1)); 1345 1346 if (ExcessBits < NVT.getSizeInBits()) { 1347 // Transfer low bits from the bottom of Hi to the top of Lo. 1348 Lo = DAG.getNode(ISD::OR, NVT, Lo, 1349 DAG.getNode(ISD::SHL, NVT, Hi, 1350 DAG.getConstant(ExcessBits, 1351 TLI.getShiftAmountTy()))); 1352 // Move high bits to the right position in Hi. 1353 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi, 1354 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1355 TLI.getShiftAmountTy())); 1356 } 1357 } 1358 1359 // Legalized the chain result - switch anything that used the old chain to 1360 // use the new one. 1361 ReplaceValueWith(SDValue(N, 1), Ch); 1362} 1363 1364void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1365 SDValue &Lo, SDValue &Hi) { 1366 SDValue LL, LH, RL, RH; 1367 GetExpandedInteger(N->getOperand(0), LL, LH); 1368 GetExpandedInteger(N->getOperand(1), RL, RH); 1369 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL); 1370 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH); 1371} 1372 1373void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1374 SDValue &Lo, SDValue &Hi) { 1375 MVT VT = N->getValueType(0); 1376 MVT NVT = TLI.getTypeToTransformTo(VT); 1377 1378 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 1379 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 1380 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 1381 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 1382 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1383 SDValue LL, LH, RL, RH; 1384 GetExpandedInteger(N->getOperand(0), LL, LH); 1385 GetExpandedInteger(N->getOperand(1), RL, RH); 1386 unsigned OuterBitSize = VT.getSizeInBits(); 1387 unsigned InnerBitSize = NVT.getSizeInBits(); 1388 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1389 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1390 1391 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1392 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1393 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1394 // The inputs are both zero-extended. 1395 if (HasUMUL_LOHI) { 1396 // We can emit a umul_lohi. 1397 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1398 Hi = SDValue(Lo.getNode(), 1); 1399 return; 1400 } 1401 if (HasMULHU) { 1402 // We can emit a mulhu+mul. 1403 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1404 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1405 return; 1406 } 1407 } 1408 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1409 // The input values are both sign-extended. 1410 if (HasSMUL_LOHI) { 1411 // We can emit a smul_lohi. 1412 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1413 Hi = SDValue(Lo.getNode(), 1); 1414 return; 1415 } 1416 if (HasMULHS) { 1417 // We can emit a mulhs+mul. 1418 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1419 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 1420 return; 1421 } 1422 } 1423 if (HasUMUL_LOHI) { 1424 // Lo,Hi = umul LHS, RHS. 1425 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 1426 DAG.getVTList(NVT, NVT), LL, RL); 1427 Lo = UMulLOHI; 1428 Hi = UMulLOHI.getValue(1); 1429 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1430 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1431 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1432 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1433 return; 1434 } 1435 if (HasMULHU) { 1436 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1437 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1438 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1439 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1440 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1441 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1442 return; 1443 } 1444 } 1445 1446 // If nothing else, we can make a libcall. 1447 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1448 if (VT == MVT::i32) 1449 LC = RTLIB::MUL_I32; 1450 else if (VT == MVT::i64) 1451 LC = RTLIB::MUL_I64; 1452 else if (VT == MVT::i128) 1453 LC = RTLIB::MUL_I128; 1454 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1455 1456 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1457 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi); 1458} 1459 1460void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1461 SDValue &Lo, SDValue &Hi) { 1462 MVT VT = N->getValueType(0); 1463 1464 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1465 if (VT == MVT::i32) 1466 LC = RTLIB::SDIV_I32; 1467 else if (VT == MVT::i64) 1468 LC = RTLIB::SDIV_I64; 1469 else if (VT == MVT::i128) 1470 LC = RTLIB::SDIV_I128; 1471 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1472 1473 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1474 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1475} 1476 1477void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1478 SDValue &Lo, SDValue &Hi) { 1479 MVT VT = N->getValueType(0); 1480 1481 // If we can emit an efficient shift operation, do so now. Check to see if 1482 // the RHS is a constant. 1483 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1484 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1485 1486 // If we can determine that the high bit of the shift is zero or one, even if 1487 // the low bits are variable, emit this shift in an optimized form. 1488 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1489 return; 1490 1491 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1492 unsigned PartsOpc; 1493 if (N->getOpcode() == ISD::SHL) { 1494 PartsOpc = ISD::SHL_PARTS; 1495 } else if (N->getOpcode() == ISD::SRL) { 1496 PartsOpc = ISD::SRL_PARTS; 1497 } else { 1498 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1499 PartsOpc = ISD::SRA_PARTS; 1500 } 1501 1502 // Next check to see if the target supports this SHL_PARTS operation or if it 1503 // will custom expand it. 1504 MVT NVT = TLI.getTypeToTransformTo(VT); 1505 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1506 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1507 Action == TargetLowering::Custom) { 1508 // Expand the subcomponents. 1509 SDValue LHSL, LHSH; 1510 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1511 1512 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1513 MVT VT = LHSL.getValueType(); 1514 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 1515 Hi = Lo.getValue(1); 1516 return; 1517 } 1518 1519 // Otherwise, emit a libcall. 1520 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1521 bool isSigned; 1522 if (N->getOpcode() == ISD::SHL) { 1523 isSigned = false; /*sign irrelevant*/ 1524 if (VT == MVT::i32) 1525 LC = RTLIB::SHL_I32; 1526 else if (VT == MVT::i64) 1527 LC = RTLIB::SHL_I64; 1528 else if (VT == MVT::i128) 1529 LC = RTLIB::SHL_I128; 1530 } else if (N->getOpcode() == ISD::SRL) { 1531 isSigned = false; 1532 if (VT == MVT::i32) 1533 LC = RTLIB::SRL_I32; 1534 else if (VT == MVT::i64) 1535 LC = RTLIB::SRL_I64; 1536 else if (VT == MVT::i128) 1537 LC = RTLIB::SRL_I128; 1538 } else { 1539 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1540 isSigned = true; 1541 if (VT == MVT::i32) 1542 LC = RTLIB::SRA_I32; 1543 else if (VT == MVT::i64) 1544 LC = RTLIB::SRA_I64; 1545 else if (VT == MVT::i128) 1546 LC = RTLIB::SRA_I128; 1547 } 1548 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!"); 1549 1550 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1551 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi); 1552} 1553 1554void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 1555 SDValue &Lo, SDValue &Hi) { 1556 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1557 SDValue Op = N->getOperand(0); 1558 if (Op.getValueType().bitsLE(NVT)) { 1559 // The low part is sign extension of the input (which degenerates to a copy). 1560 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0)); 1561 // The high part is obtained by SRA'ing all but one of the bits of low part. 1562 unsigned LoSize = NVT.getSizeInBits(); 1563 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1564 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1565 } else { 1566 // For example, extension of an i48 to an i64. The operand type necessarily 1567 // promotes to the result type, so will end up being expanded too. 1568 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1569 "Only know how to promote this result!"); 1570 SDValue Res = GetPromotedInteger(Op); 1571 assert(Res.getValueType() == N->getValueType(0) && 1572 "Operand over promoted?"); 1573 // Split the promoted operand. This will simplify when it is expanded. 1574 SplitInteger(Res, Lo, Hi); 1575 unsigned ExcessBits = 1576 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1577 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 1578 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1579 } 1580} 1581 1582void DAGTypeLegalizer:: 1583ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 1584 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1585 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1586 1587 if (EVT.bitsLE(Lo.getValueType())) { 1588 // sext_inreg the low part if needed. 1589 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo, 1590 N->getOperand(1)); 1591 1592 // The high part gets the sign extension from the lo-part. This handles 1593 // things like sextinreg V:i64 from i8. 1594 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo, 1595 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 1596 TLI.getShiftAmountTy())); 1597 } else { 1598 // For example, extension of an i48 to an i64. Leave the low part alone, 1599 // sext_inreg the high part. 1600 unsigned ExcessBits = 1601 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 1602 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 1603 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1604 } 1605} 1606 1607void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1608 SDValue &Lo, SDValue &Hi) { 1609 MVT VT = N->getValueType(0); 1610 1611 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1612 if (VT == MVT::i32) 1613 LC = RTLIB::SREM_I32; 1614 else if (VT == MVT::i64) 1615 LC = RTLIB::SREM_I64; 1616 else if (VT == MVT::i128) 1617 LC = RTLIB::SREM_I128; 1618 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1619 1620 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1621 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1622} 1623 1624void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 1625 SDValue &Lo, SDValue &Hi) { 1626 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1627 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0)); 1628 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0), 1629 DAG.getConstant(NVT.getSizeInBits(), 1630 TLI.getShiftAmountTy())); 1631 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi); 1632} 1633 1634void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1635 SDValue &Lo, SDValue &Hi) { 1636 MVT VT = N->getValueType(0); 1637 1638 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1639 if (VT == MVT::i32) 1640 LC = RTLIB::UDIV_I32; 1641 else if (VT == MVT::i64) 1642 LC = RTLIB::UDIV_I64; 1643 else if (VT == MVT::i128) 1644 LC = RTLIB::UDIV_I128; 1645 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 1646 1647 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1648 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1649} 1650 1651void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 1652 SDValue &Lo, SDValue &Hi) { 1653 MVT VT = N->getValueType(0); 1654 1655 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1656 if (VT == MVT::i32) 1657 LC = RTLIB::UREM_I32; 1658 else if (VT == MVT::i64) 1659 LC = RTLIB::UREM_I64; 1660 else if (VT == MVT::i128) 1661 LC = RTLIB::UREM_I128; 1662 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 1663 1664 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1665 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1666} 1667 1668void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 1669 SDValue &Lo, SDValue &Hi) { 1670 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1671 SDValue Op = N->getOperand(0); 1672 if (Op.getValueType().bitsLE(NVT)) { 1673 // The low part is zero extension of the input (which degenerates to a copy). 1674 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0)); 1675 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 1676 } else { 1677 // For example, extension of an i48 to an i64. The operand type necessarily 1678 // promotes to the result type, so will end up being expanded too. 1679 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1680 "Only know how to promote this result!"); 1681 SDValue Res = GetPromotedInteger(Op); 1682 assert(Res.getValueType() == N->getValueType(0) && 1683 "Operand over promoted?"); 1684 // Split the promoted operand. This will simplify when it is expanded. 1685 SplitInteger(Res, Lo, Hi); 1686 unsigned ExcessBits = 1687 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1688 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); 1689 } 1690} 1691 1692 1693//===----------------------------------------------------------------------===// 1694// Integer Operand Expansion 1695//===----------------------------------------------------------------------===// 1696 1697/// ExpandIntegerOperand - This method is called when the specified operand of 1698/// the specified node is found to need expansion. At this point, all of the 1699/// result types of the node are known to be legal, but other operands of the 1700/// node may need promotion or expansion as well as the specified one. 1701bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 1702 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n"); 1703 SDValue Res = SDValue(); 1704 1705 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 1706 == TargetLowering::Custom) 1707 Res = TLI.LowerOperation(SDValue(N, OpNo), DAG); 1708 1709 if (Res.getNode() == 0) { 1710 switch (N->getOpcode()) { 1711 default: 1712 #ifndef NDEBUG 1713 cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; 1714 N->dump(&DAG); cerr << "\n"; 1715 #endif 1716 assert(0 && "Do not know how to expand this operator's operand!"); 1717 abort(); 1718 1719 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 1720 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 1721 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 1722 1723 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 1724 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 1725 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 1726 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 1727 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); 1728 break; 1729 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 1730 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 1731 } 1732 } 1733 1734 // If the result is null, the sub-method took care of registering results etc. 1735 if (!Res.getNode()) return false; 1736 // If the result is N, the sub-method updated N in place. Check to see if any 1737 // operands are new, and if so, mark them. 1738 if (Res.getNode() == N) { 1739 // Mark N as new and remark N and its operands. This allows us to correctly 1740 // revisit N if it needs another step of expansion and allows us to visit 1741 // any new operands to N. 1742 ReanalyzeNode(N); 1743 return true; 1744 } 1745 1746 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1747 "Invalid operand expansion"); 1748 1749 ReplaceValueWith(SDValue(N, 0), Res); 1750 return false; 1751} 1752 1753/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 1754/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1755void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 1756 SDValue &NewRHS, 1757 ISD::CondCode &CCCode) { 1758 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 1759 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 1760 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 1761 1762 MVT VT = NewLHS.getValueType(); 1763 1764 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 1765 if (RHSLo == RHSHi) { 1766 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 1767 if (RHSCST->isAllOnesValue()) { 1768 // Equality comparison to -1. 1769 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1770 NewRHS = RHSLo; 1771 return; 1772 } 1773 } 1774 } 1775 1776 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1777 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1778 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS); 1779 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1780 return; 1781 } 1782 1783 // If this is a comparison of the sign bit, just look at the top part. 1784 // X > -1, x < 0 1785 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 1786 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 1787 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 1788 NewLHS = LHSHi; 1789 NewRHS = RHSHi; 1790 return; 1791 } 1792 1793 // FIXME: This generated code sucks. 1794 ISD::CondCode LowCC; 1795 switch (CCCode) { 1796 default: assert(0 && "Unknown integer setcc!"); 1797 case ISD::SETLT: 1798 case ISD::SETULT: LowCC = ISD::SETULT; break; 1799 case ISD::SETGT: 1800 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1801 case ISD::SETLE: 1802 case ISD::SETULE: LowCC = ISD::SETULE; break; 1803 case ISD::SETGE: 1804 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1805 } 1806 1807 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1808 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1809 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1810 1811 // NOTE: on targets without efficient SELECT of bools, we can always use 1812 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1813 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 1814 SDValue Tmp1, Tmp2; 1815 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC, 1816 false, DagCombineInfo); 1817 if (!Tmp1.getNode()) 1818 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 1819 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1820 CCCode, false, DagCombineInfo); 1821 if (!Tmp2.getNode()) 1822 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1823 DAG.getCondCode(CCCode)); 1824 1825 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 1826 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 1827 if ((Tmp1C && Tmp1C->isNullValue()) || 1828 (Tmp2C && Tmp2C->isNullValue() && 1829 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 1830 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 1831 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 1832 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 1833 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 1834 // low part is known false, returns high part. 1835 // For LE / GE, if high part is known false, ignore the low part. 1836 // For LT / GT, if high part is known true, ignore the low part. 1837 NewLHS = Tmp2; 1838 NewRHS = SDValue(); 1839 return; 1840 } 1841 1842 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1843 ISD::SETEQ, false, DagCombineInfo); 1844 if (!NewLHS.getNode()) 1845 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1846 ISD::SETEQ); 1847 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1848 NewLHS, Tmp1, Tmp2); 1849 NewRHS = SDValue(); 1850} 1851 1852SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 1853 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 1854 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 1855 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 1856 1857 // If ExpandSetCCOperands returned a scalar, we need to compare the result 1858 // against zero to select between true and false values. 1859 if (NewRHS.getNode() == 0) { 1860 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1861 CCCode = ISD::SETNE; 1862 } 1863 1864 // Update N to have the operands specified. 1865 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 1866 DAG.getCondCode(CCCode), NewLHS, NewRHS, 1867 N->getOperand(4)); 1868} 1869 1870SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 1871 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 1872 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 1873 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 1874 1875 // If ExpandSetCCOperands returned a scalar, we need to compare the result 1876 // against zero to select between true and false values. 1877 if (NewRHS.getNode() == 0) { 1878 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1879 CCCode = ISD::SETNE; 1880 } 1881 1882 // Update N to have the operands specified. 1883 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 1884 N->getOperand(2), N->getOperand(3), 1885 DAG.getCondCode(CCCode)); 1886} 1887 1888SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 1889 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 1890 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 1891 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 1892 1893 // If ExpandSetCCOperands returned a scalar, use it. 1894 if (NewRHS.getNode() == 0) { 1895 assert(NewLHS.getValueType() == N->getValueType(0) && 1896 "Unexpected setcc expansion!"); 1897 return NewLHS; 1898 } 1899 1900 // Otherwise, update N to have the operands specified. 1901 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 1902 DAG.getCondCode(CCCode)); 1903} 1904 1905SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 1906 SDValue Op = N->getOperand(0); 1907 MVT DstVT = N->getValueType(0); 1908 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 1909 assert(LC != RTLIB::UNKNOWN_LIBCALL && 1910 "Don't know how to expand this SINT_TO_FP!"); 1911 return MakeLibCall(LC, DstVT, &Op, 1, true); 1912} 1913 1914SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 1915 if (ISD::isNormalStore(N)) 1916 return ExpandOp_NormalStore(N, OpNo); 1917 1918 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 1919 assert(OpNo == 1 && "Can only expand the stored value so far"); 1920 1921 MVT VT = N->getOperand(1).getValueType(); 1922 MVT NVT = TLI.getTypeToTransformTo(VT); 1923 SDValue Ch = N->getChain(); 1924 SDValue Ptr = N->getBasePtr(); 1925 int SVOffset = N->getSrcValueOffset(); 1926 unsigned Alignment = N->getAlignment(); 1927 bool isVolatile = N->isVolatile(); 1928 SDValue Lo, Hi; 1929 1930 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1931 1932 if (N->getMemoryVT().bitsLE(NVT)) { 1933 GetExpandedInteger(N->getValue(), Lo, Hi); 1934 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 1935 N->getMemoryVT(), isVolatile, Alignment); 1936 } else if (TLI.isLittleEndian()) { 1937 // Little-endian - low bits are at low addresses. 1938 GetExpandedInteger(N->getValue(), Lo, Hi); 1939 1940 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 1941 isVolatile, Alignment); 1942 1943 unsigned ExcessBits = 1944 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1945 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1946 1947 // Increment the pointer to the other half. 1948 unsigned IncrementSize = NVT.getSizeInBits()/8; 1949 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1950 DAG.getIntPtrConstant(IncrementSize)); 1951 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 1952 SVOffset+IncrementSize, NEVT, 1953 isVolatile, MinAlign(Alignment, IncrementSize)); 1954 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1955 } else { 1956 // Big-endian - high bits are at low addresses. Favor aligned stores at 1957 // the cost of some bit-fiddling. 1958 GetExpandedInteger(N->getValue(), Lo, Hi); 1959 1960 MVT EVT = N->getMemoryVT(); 1961 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1962 unsigned IncrementSize = NVT.getSizeInBits()/8; 1963 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1964 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); 1965 1966 if (ExcessBits < NVT.getSizeInBits()) { 1967 // Transfer high bits from the top of Lo to the bottom of Hi. 1968 Hi = DAG.getNode(ISD::SHL, NVT, Hi, 1969 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1970 TLI.getShiftAmountTy())); 1971 Hi = DAG.getNode(ISD::OR, NVT, Hi, 1972 DAG.getNode(ISD::SRL, NVT, Lo, 1973 DAG.getConstant(ExcessBits, 1974 TLI.getShiftAmountTy()))); 1975 } 1976 1977 // Store both the high bits and maybe some of the low bits. 1978 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 1979 SVOffset, HiVT, isVolatile, Alignment); 1980 1981 // Increment the pointer to the other half. 1982 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1983 DAG.getIntPtrConstant(IncrementSize)); 1984 // Store the lowest ExcessBits bits in the second half. 1985 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), 1986 SVOffset+IncrementSize, 1987 MVT::getIntegerVT(ExcessBits), 1988 isVolatile, MinAlign(Alignment, IncrementSize)); 1989 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1990 } 1991} 1992 1993SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 1994 SDValue InL, InH; 1995 GetExpandedInteger(N->getOperand(0), InL, InH); 1996 // Just truncate the low part of the source. 1997 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL); 1998} 1999 2000SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2001 SDValue Op = N->getOperand(0); 2002 MVT SrcVT = Op.getValueType(); 2003 MVT DstVT = N->getValueType(0); 2004 2005 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2006 // Do a signed conversion then adjust the result. 2007 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op); 2008 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2009 2010 // The result of the signed conversion needs adjusting if the 'sign bit' of 2011 // the incoming integer was set. To handle this, we dynamically test to see 2012 // if it is set, and, if so, add a fudge factor. 2013 2014 const uint64_t F32TwoE32 = 0x4F800000ULL; 2015 const uint64_t F32TwoE64 = 0x5F800000ULL; 2016 const uint64_t F32TwoE128 = 0x7F800000ULL; 2017 2018 APInt FF(32, 0); 2019 if (SrcVT == MVT::i32) 2020 FF = APInt(32, F32TwoE32); 2021 else if (SrcVT == MVT::i64) 2022 FF = APInt(32, F32TwoE64); 2023 else if (SrcVT == MVT::i128) 2024 FF = APInt(32, F32TwoE128); 2025 else 2026 assert(false && "Unsupported UINT_TO_FP!"); 2027 2028 // Check whether the sign bit is set. 2029 SDValue Lo, Hi; 2030 GetExpandedInteger(Op, Lo, Hi); 2031 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 2032 DAG.getConstant(0, Hi.getValueType()), 2033 ISD::SETLT); 2034 2035 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2036 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)), 2037 TLI.getPointerTy()); 2038 2039 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2040 SDValue Zero = DAG.getIntPtrConstant(0); 2041 SDValue Four = DAG.getIntPtrConstant(4); 2042 if (TLI.isBigEndian()) std::swap(Zero, Four); 2043 SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet, 2044 Zero, Four); 2045 unsigned Alignment = 2046 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2047 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset); 2048 Alignment = std::min(Alignment, 4u); 2049 2050 // Load the value out, extending it from f32 to the destination float type. 2051 // FIXME: Avoid the extend by constructing the right constant pool? 2052 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(), 2053 FudgePtr, NULL, 0, MVT::f32, 2054 false, Alignment); 2055 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge); 2056 } 2057 2058 // Otherwise, use a libcall. 2059 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2060 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2061 "Don't know how to expand this UINT_TO_FP!"); 2062 return MakeLibCall(LC, DstVT, &Op, 1, true); 2063} 2064