LegalizeIntegerTypes.cpp revision e6c2a8329d13cf67e91852d40f848fbb21edb401
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22using namespace llvm; 23 24//===----------------------------------------------------------------------===// 25// Integer Result Promotion 26//===----------------------------------------------------------------------===// 27 28/// PromoteIntegerResult - This method is called when a result of a node is 29/// found to be in need of promotion to a larger type. At this point, the node 30/// may also have invalid operands or may have other results that need 31/// expansion, we just know that (at least) one result needs promotion. 32void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n"); 34 SDValue Res = SDValue(); 35 36 // See if the target wants to custom expand this node. 37 if (CustomLowerResults(N, N->getValueType(ResNo), true)) 38 return; 39 40 switch (N->getOpcode()) { 41 default: 42#ifndef NDEBUG 43 cerr << "PromoteIntegerResult #" << ResNo << ": "; 44 N->dump(&DAG); cerr << "\n"; 45#endif 46 assert(0 && "Do not know how to promote this operator!"); 47 abort(); 48 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 49 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 50 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break; 51 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 52 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 53 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 54 case ISD::CONVERT_RNDSAT: 55 Res = PromoteIntRes_CONVERT_RNDSAT(N); break; 56 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; 57 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break; 58 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; 59 case ISD::EXTRACT_VECTOR_ELT: 60 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 61 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 62 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break; 63 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; 64 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 65 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; 66 case ISD::SIGN_EXTEND_INREG: 67 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 68 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 69 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; 70 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; 71 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break; 72 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break; 73 74 case ISD::SIGN_EXTEND: 75 case ISD::ZERO_EXTEND: 76 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; 77 78 case ISD::FP_TO_SINT: 79 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; 80 81 case ISD::AND: 82 case ISD::OR: 83 case ISD::XOR: 84 case ISD::ADD: 85 case ISD::SUB: 86 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break; 87 88 case ISD::SDIV: 89 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; 90 91 case ISD::UDIV: 92 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break; 93 94 case ISD::SADDO: 95 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; 96 case ISD::UADDO: 97 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; 98 case ISD::SMULO: 99 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; 100 101 case ISD::ATOMIC_LOAD_ADD: 102 case ISD::ATOMIC_LOAD_SUB: 103 case ISD::ATOMIC_LOAD_AND: 104 case ISD::ATOMIC_LOAD_OR: 105 case ISD::ATOMIC_LOAD_XOR: 106 case ISD::ATOMIC_LOAD_NAND: 107 case ISD::ATOMIC_LOAD_MIN: 108 case ISD::ATOMIC_LOAD_MAX: 109 case ISD::ATOMIC_LOAD_UMIN: 110 case ISD::ATOMIC_LOAD_UMAX: 111 case ISD::ATOMIC_SWAP: 112 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 113 114 case ISD::ATOMIC_CMP_SWAP: 115 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 116 } 117 118 // If the result is null then the sub-method took care of registering it. 119 if (Res.getNode()) 120 SetPromotedInteger(SDValue(N, ResNo), Res); 121} 122 123SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 124 // Sign-extend the new bits, and continue the assertion. 125 SDValue Op = SExtPromotedInteger(N->getOperand(0)); 126 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(), 127 Op.getValueType(), Op, N->getOperand(1)); 128} 129 130SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 131 // Zero the new bits, and continue the assertion. 132 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 133 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), 134 Op.getValueType(), Op, N->getOperand(1)); 135} 136 137SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 138 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 139 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 140 N->getMemoryVT(), 141 N->getChain(), N->getBasePtr(), 142 Op2, N->getSrcValue(), N->getAlignment()); 143 // Legalized the chain result - switch anything that used the old chain to 144 // use the new one. 145 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 146 return Res; 147} 148 149SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 150 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 151 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 152 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getMemoryVT(), 153 N->getChain(), N->getBasePtr(), 154 Op2, Op3, N->getSrcValue(), N->getAlignment()); 155 // Legalized the chain result - switch anything that used the old chain to 156 // use the new one. 157 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 158 return Res; 159} 160 161SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 162 SDValue InOp = N->getOperand(0); 163 MVT InVT = InOp.getValueType(); 164 MVT NInVT = TLI.getTypeToTransformTo(InVT); 165 MVT OutVT = N->getValueType(0); 166 MVT NOutVT = TLI.getTypeToTransformTo(OutVT); 167 DebugLoc dl = N->getDebugLoc(); 168 169 switch (getTypeAction(InVT)) { 170 default: 171 assert(false && "Unknown type action!"); 172 break; 173 case Legal: 174 break; 175 case PromoteInteger: 176 if (NOutVT.bitsEq(NInVT)) 177 // The input promotes to the same size. Convert the promoted value. 178 return DAG.getNode(ISD::BIT_CONVERT, dl, 179 NOutVT, GetPromotedInteger(InOp)); 180 break; 181 case SoftenFloat: 182 // Promote the integer operand by hand. 183 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); 184 case ExpandInteger: 185 case ExpandFloat: 186 break; 187 case ScalarizeVector: 188 // Convert the element to an integer and promote it by hand. 189 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 190 BitConvertToInteger(GetScalarizedVector(InOp))); 191 case SplitVector: { 192 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 193 // pieces of the input into integers and reassemble in the final type. 194 SDValue Lo, Hi; 195 GetSplitVector(N->getOperand(0), Lo, Hi); 196 Lo = BitConvertToInteger(Lo); 197 Hi = BitConvertToInteger(Hi); 198 199 if (TLI.isBigEndian()) 200 std::swap(Lo, Hi); 201 202 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, 203 MVT::getIntegerVT(NOutVT.getSizeInBits()), 204 JoinIntegers(Lo, Hi)); 205 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp); 206 } 207 case WidenVector: 208 if (OutVT.bitsEq(NInVT)) 209 // The input is widened to the same size. Convert to the widened value. 210 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp)); 211 } 212 213 // Otherwise, lower the bit-convert to a store/load from the stack. 214 // Create the stack frame object. Make sure it is aligned for both 215 // the source and destination types. 216 SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT); 217 218 // Emit a store to the stack slot. 219 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, NULL, 0); 220 221 // Result is an extending load from the stack slot. 222 return DAG.getExtLoad(ISD::EXTLOAD, dl, NOutVT, Store, FIPtr, NULL, 0, OutVT); 223} 224 225SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 226 SDValue Op = GetPromotedInteger(N->getOperand(0)); 227 MVT OVT = N->getValueType(0); 228 MVT NVT = Op.getValueType(); 229 DebugLoc dl = N->getDebugLoc(); 230 231 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 232 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 233 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 234} 235 236SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 237 // The pair element type may be legal, or may not promote to the same type as 238 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 239 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), 240 TLI.getTypeToTransformTo(N->getValueType(0)), 241 JoinIntegers(N->getOperand(0), N->getOperand(1))); 242} 243 244SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 245 MVT VT = N->getValueType(0); 246 // Zero extend things like i1, sign extend everything else. It shouldn't 247 // matter in theory which one we pick, but this tends to give better code? 248 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 249 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), 250 SDValue(N, 0)); 251 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 252 return Result; 253} 254 255SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 256 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 257 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 258 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 259 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 260 "can only promote integers"); 261 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 262 return DAG.getConvertRndSat(OutVT, N->getOperand(0), 263 N->getOperand(1), N->getOperand(2), 264 N->getOperand(3), N->getOperand(4), CvtCode); 265} 266 267SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 268 // Zero extend to the promoted type and do the count there. 269 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 270 MVT OVT = N->getValueType(0); 271 MVT NVT = Op.getValueType(); 272 Op = DAG.getNode(ISD::CTLZ, NVT, Op); 273 // Subtract off the extra leading bits in the bigger type. 274 return DAG.getNode(ISD::SUB, N->getDebugLoc(), NVT, Op, 275 DAG.getConstant(NVT.getSizeInBits() - 276 OVT.getSizeInBits(), NVT)); 277} 278 279SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 280 // Zero extend to the promoted type and do the count there. 281 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 282 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op); 283} 284 285SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 286 SDValue Op = GetPromotedInteger(N->getOperand(0)); 287 MVT OVT = N->getValueType(0); 288 MVT NVT = Op.getValueType(); 289 DebugLoc dl = N->getDebugLoc(); 290 // The count is the same in the promoted type except if the original 291 // value was zero. This can be handled by setting the bit just off 292 // the top of the original type. 293 APInt TopBit(NVT.getSizeInBits(), 0); 294 TopBit.set(OVT.getSizeInBits()); 295 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT)); 296 return DAG.getNode(ISD::CTTZ, dl, NVT, Op); 297} 298 299SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 300 MVT OldVT = N->getValueType(0); 301 SDValue OldVec = N->getOperand(0); 302 if (getTypeAction(OldVec.getValueType()) == WidenVector) 303 OldVec = GetWidenedVector(N->getOperand(0)); 304 unsigned OldElts = OldVec.getValueType().getVectorNumElements(); 305 DebugLoc dl = N->getDebugLoc(); 306 307 if (OldElts == 1) { 308 assert(!isTypeLegal(OldVec.getValueType()) && 309 "Legal one-element vector of a type needing promotion!"); 310 // It is tempting to follow GetScalarizedVector by a call to 311 // GetPromotedInteger, but this would be wrong because the 312 // scalarized value may not yet have been processed. 313 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), 314 GetScalarizedVector(OldVec)); 315 } 316 317 // Convert to a vector half as long with an element type of twice the width, 318 // for example <4 x i16> -> <2 x i32>. 319 assert(!(OldElts & 1) && "Odd length vectors not supported!"); 320 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 321 assert(OldVT.isSimple() && NewVT.isSimple()); 322 323 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl, 324 MVT::getVectorVT(NewVT, OldElts / 2), 325 OldVec); 326 327 // Extract the element at OldIdx / 2 from the new vector. 328 SDValue OldIdx = N->getOperand(1); 329 SDValue NewIdx = DAG.getNode(ISD::SRL, dl, OldIdx.getValueType(), OldIdx, 330 DAG.getConstant(1, TLI.getShiftAmountTy())); 331 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, NewIdx); 332 333 // Select the appropriate half of the element: Lo if OldIdx was even, 334 // Hi if it was odd. 335 SDValue Lo = Elt; 336 SDValue Hi = DAG.getNode(ISD::SRL, dl, NewVT, Elt, 337 DAG.getConstant(OldVT.getSizeInBits(), 338 TLI.getShiftAmountTy())); 339 if (TLI.isBigEndian()) 340 std::swap(Lo, Hi); 341 342 // Extend to the promoted type. 343 SDValue Odd = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, OldIdx); 344 SDValue Res = DAG.getNode(ISD::SELECT, dl, NewVT, Odd, Hi, Lo); 345 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), Res); 346} 347 348SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 349 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 350 unsigned NewOpc = N->getOpcode(); 351 DebugLoc dl = N->getDebugLoc(); 352 353 // If we're promoting a UINT to a larger size, check to see if the new node 354 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 355 // we can use that instead. This allows us to generate better code for 356 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 357 // legal, such as PowerPC. 358 if (N->getOpcode() == ISD::FP_TO_UINT && 359 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) && 360 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) 361 NewOpc = ISD::FP_TO_SINT; 362 363 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); 364 365 // Assert that the converted value fits in the original type. If it doesn't 366 // (eg: because the value being converted is too big), then the result of the 367 // original operation was undefined anyway, so the assert is still correct. 368 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 369 ISD::AssertZext : ISD::AssertSext, dl, 370 NVT, Res, DAG.getValueType(N->getValueType(0))); 371} 372 373SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 374 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 375 DebugLoc dl = N->getDebugLoc(); 376 377 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 378 SDValue Res = GetPromotedInteger(N->getOperand(0)); 379 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 380 381 // If the result and operand types are the same after promotion, simplify 382 // to an in-register extension. 383 if (NVT == Res.getValueType()) { 384 // The high bits are not guaranteed to be anything. Insert an extend. 385 if (N->getOpcode() == ISD::SIGN_EXTEND) 386 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 387 DAG.getValueType(N->getOperand(0).getValueType())); 388 if (N->getOpcode() == ISD::ZERO_EXTEND) 389 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); 390 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 391 return Res; 392 } 393 } 394 395 // Otherwise, just extend the original operand all the way to the larger type. 396 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 397} 398 399SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 400 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 401 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 402 ISD::LoadExtType ExtType = 403 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 404 DebugLoc dl = N->getDebugLoc(); 405 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), 406 N->getSrcValue(), N->getSrcValueOffset(), 407 N->getMemoryVT(), N->isVolatile(), 408 N->getAlignment()); 409 410 // Legalized the chain result - switch anything that used the old chain to 411 // use the new one. 412 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 413 return Res; 414} 415 416/// Promote the overflow flag of an overflowing arithmetic node. 417SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { 418 // Simply change the return type of the boolean result. 419 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); 420 MVT ValueVTs[] = { N->getValueType(0), NVT }; 421 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) }; 422 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), 423 DAG.getVTList(ValueVTs, 2), Ops, 2); 424 425 // Modified the sum result - switch anything that used the old sum to use 426 // the new one. 427 ReplaceValueWith(SDValue(N, 0), Res); 428 429 return SDValue(Res.getNode(), 1); 430} 431 432SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { 433 if (ResNo == 1) 434 return PromoteIntRes_Overflow(N); 435 436 // The operation overflowed iff the result in the larger type is not the 437 // sign extension of its truncation to the original type. 438 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 439 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 440 MVT OVT = N->getOperand(0).getValueType(); 441 MVT NVT = LHS.getValueType(); 442 DebugLoc dl = N->getDebugLoc(); 443 444 // Do the arithmetic in the larger type. 445 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 446 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 447 448 // Calculate the overflow flag: sign extend the arithmetic result from 449 // the original type. 450 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 451 DAG.getValueType(OVT)); 452 // Overflowed if and only if this is not equal to Res. 453 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 454 455 // Use the calculated overflow everywhere. 456 ReplaceValueWith(SDValue(N, 1), Ofl); 457 458 return Res; 459} 460 461SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 462 // Sign extend the input. 463 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 464 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 465 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 466 LHS.getValueType(), LHS, RHS); 467} 468 469SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 470 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 471 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 472 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 473 LHS.getValueType(), N->getOperand(0),LHS,RHS); 474} 475 476SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 477 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 478 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 479 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 480 LHS.getValueType(), N->getOperand(0), 481 N->getOperand(1), LHS, RHS, N->getOperand(4)); 482} 483 484SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 485 MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); 486 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 487 DebugLoc dl = N->getDebugLoc(); 488 489 // Get the SETCC result using the canonical SETCC type. 490 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0), 491 N->getOperand(1), N->getOperand(2)); 492 493 // Convert to the expected type. 494 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 495 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 496 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 497} 498 499SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 500 return DAG.getNode(ISD::SHL, N->getDebugLoc(), 501 TLI.getTypeToTransformTo(N->getValueType(0)), 502 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 503} 504 505SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 506 SDValue Op = GetPromotedInteger(N->getOperand(0)); 507 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), 508 Op.getValueType(), Op, N->getOperand(1)); 509} 510 511SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 512 // The input may have strange things in the top bits of the registers, but 513 // these operations don't care. They may have weird bits going out, but 514 // that too is okay if they are integer operations. 515 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 516 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 517 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 518 LHS.getValueType(), LHS, RHS); 519} 520 521SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 522 // The input value must be properly sign extended. 523 SDValue Res = SExtPromotedInteger(N->getOperand(0)); 524 return DAG.getNode(ISD::SRA, N->getDebugLoc(), 525 Res.getValueType(), Res, N->getOperand(1)); 526} 527 528SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 529 // The input value must be properly zero extended. 530 MVT VT = N->getValueType(0); 531 MVT NVT = TLI.getTypeToTransformTo(VT); 532 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 533 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1)); 534} 535 536SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 537 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 538 SDValue Res; 539 540 switch (getTypeAction(N->getOperand(0).getValueType())) { 541 default: assert(0 && "Unknown type action!"); 542 case Legal: 543 case ExpandInteger: 544 Res = N->getOperand(0); 545 break; 546 case PromoteInteger: 547 Res = GetPromotedInteger(N->getOperand(0)); 548 break; 549 } 550 551 // Truncate to NVT instead of VT 552 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res); 553} 554 555SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) { 556 if (ResNo == 1) 557 return PromoteIntRes_Overflow(N); 558 559 // The operation overflowed iff the result in the larger type is not the 560 // zero extension of its truncation to the original type. 561 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 562 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 563 MVT OVT = N->getOperand(0).getValueType(); 564 MVT NVT = LHS.getValueType(); 565 DebugLoc dl = N->getDebugLoc(); 566 567 // Do the arithmetic in the larger type. 568 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 569 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 570 571 // Calculate the overflow flag: zero extend the arithmetic result from 572 // the original type. 573 SDValue Ofl = DAG.getZeroExtendInReg(Res, OVT); 574 // Overflowed if and only if this is not equal to Res. 575 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 576 577 // Use the calculated overflow everywhere. 578 ReplaceValueWith(SDValue(N, 1), Ofl); 579 580 return Res; 581} 582 583SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 584 // Zero extend the input. 585 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 586 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 587 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 588 LHS.getValueType(), LHS, RHS); 589} 590 591SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 592 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), 593 TLI.getTypeToTransformTo(N->getValueType(0))); 594} 595 596SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 597 SDValue Chain = N->getOperand(0); // Get the chain. 598 SDValue Ptr = N->getOperand(1); // Get the pointer. 599 MVT VT = N->getValueType(0); 600 DebugLoc dl = N->getDebugLoc(); 601 602 MVT RegVT = TLI.getRegisterType(VT); 603 unsigned NumRegs = TLI.getNumRegisters(VT); 604 // The argument is passed as NumRegs registers of type RegVT. 605 606 SmallVector<SDValue, 8> Parts(NumRegs); 607 for (unsigned i = 0; i < NumRegs; ++i) { 608 Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2)); 609 Chain = Parts[i].getValue(1); 610 } 611 612 // Handle endianness of the load. 613 if (TLI.isBigEndian()) 614 std::reverse(Parts.begin(), Parts.end()); 615 616 // Assemble the parts in the promoted type. 617 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 618 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); 619 for (unsigned i = 1; i < NumRegs; ++i) { 620 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); 621 // Shift it to the right position and "or" it in. 622 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, 623 DAG.getConstant(i * RegVT.getSizeInBits(), 624 TLI.getShiftAmountTy())); 625 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part); 626 } 627 628 // Modified the chain result - switch anything that used the old chain to 629 // use the new one. 630 ReplaceValueWith(SDValue(N, 1), Chain); 631 632 return Res; 633} 634 635SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) { 636 assert(ResNo == 1 && "Only boolean result promotion currently supported!"); 637 return PromoteIntRes_Overflow(N); 638} 639 640//===----------------------------------------------------------------------===// 641// Integer Operand Promotion 642//===----------------------------------------------------------------------===// 643 644/// PromoteIntegerOperand - This method is called when the specified operand of 645/// the specified node is found to need promotion. At this point, all of the 646/// result types of the node are known to be legal, but other operands of the 647/// node may need promotion or expansion as well as the specified one. 648bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 649 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n"); 650 SDValue Res = SDValue(); 651 652 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false)) 653 return false; 654 655 switch (N->getOpcode()) { 656 default: 657 #ifndef NDEBUG 658 cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; 659 N->dump(&DAG); cerr << "\n"; 660 #endif 661 assert(0 && "Do not know how to promote this operator's operand!"); 662 abort(); 663 664 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 665 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 666 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 667 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 668 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 669 case ISD::CONVERT_RNDSAT: 670 Res = PromoteIntOp_CONVERT_RNDSAT(N); break; 671 case ISD::INSERT_VECTOR_ELT: 672 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 673 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 674 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 675 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 676 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 677 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 678 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; 679 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 680 OpNo); break; 681 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 682 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; 683 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 684 } 685 686 // If the result is null, the sub-method took care of registering results etc. 687 if (!Res.getNode()) return false; 688 689 // If the result is N, the sub-method updated N in place. Tell the legalizer 690 // core about this. 691 if (Res.getNode() == N) 692 return true; 693 694 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 695 "Invalid operand expansion"); 696 697 ReplaceValueWith(SDValue(N, 0), Res); 698 return false; 699} 700 701/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 702/// shared among BR_CC, SELECT_CC, and SETCC handlers. 703void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 704 ISD::CondCode CCCode) { 705 // We have to insert explicit sign or zero extends. Note that we could 706 // insert sign extends for ALL conditions, but zero extend is cheaper on 707 // many machines (an AND instead of two shifts), so prefer it. 708 switch (CCCode) { 709 default: assert(0 && "Unknown integer comparison!"); 710 case ISD::SETEQ: 711 case ISD::SETNE: 712 case ISD::SETUGE: 713 case ISD::SETUGT: 714 case ISD::SETULE: 715 case ISD::SETULT: 716 // ALL of these operations will work if we either sign or zero extend 717 // the operands (including the unsigned comparisons!). Zero extend is 718 // usually a simpler/cheaper operation, so prefer it. 719 NewLHS = ZExtPromotedInteger(NewLHS); 720 NewRHS = ZExtPromotedInteger(NewRHS); 721 break; 722 case ISD::SETGE: 723 case ISD::SETGT: 724 case ISD::SETLT: 725 case ISD::SETLE: 726 NewLHS = SExtPromotedInteger(NewLHS); 727 NewRHS = SExtPromotedInteger(NewRHS); 728 break; 729 } 730} 731 732SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 733 SDValue Op = GetPromotedInteger(N->getOperand(0)); 734 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); 735} 736 737SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 738 assert(OpNo == 2 && "Don't know how to promote this operand!"); 739 740 SDValue LHS = N->getOperand(2); 741 SDValue RHS = N->getOperand(3); 742 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 743 744 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 745 // legal types. 746 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 747 N->getOperand(1), LHS, RHS, N->getOperand(4)); 748} 749 750SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 751 assert(OpNo == 1 && "only know how to promote condition"); 752 753 // Promote all the way up to the canonical SetCC type. 754 MVT SVT = TLI.getSetCCResultType(MVT::Other); 755 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT); 756 757 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 758 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond, 759 N->getOperand(2)); 760} 761 762SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 763 // Since the result type is legal, the operands must promote to it. 764 MVT OVT = N->getOperand(0).getValueType(); 765 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); 766 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 767 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 768 DebugLoc dl = N->getDebugLoc(); 769 770 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, 771 DAG.getConstant(OVT.getSizeInBits(), 772 TLI.getShiftAmountTy())); 773 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); 774} 775 776SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 777 // The vector type is legal but the element type is not. This implies 778 // that the vector is a power-of-two in length and that the element 779 // type does not have a strange size (eg: it is not i1). 780 MVT VecVT = N->getValueType(0); 781 unsigned NumElts = VecVT.getVectorNumElements(); 782 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 783 DebugLoc dl = N->getDebugLoc(); 784 785 // Build a vector of half the length out of elements of twice the bitwidth. 786 // For example <4 x i16> -> <2 x i32>. 787 MVT OldVT = N->getOperand(0).getValueType(); 788 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 789 assert(OldVT.isSimple() && NewVT.isSimple()); 790 791 std::vector<SDValue> NewElts; 792 NewElts.reserve(NumElts/2); 793 794 for (unsigned i = 0; i < NumElts; i += 2) { 795 // Combine two successive elements into one promoted element. 796 SDValue Lo = N->getOperand(i); 797 SDValue Hi = N->getOperand(i+1); 798 if (TLI.isBigEndian()) 799 std::swap(Lo, Hi); 800 NewElts.push_back(JoinIntegers(Lo, Hi)); 801 } 802 803 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, 804 MVT::getVectorVT(NewVT, NewElts.size()), 805 &NewElts[0], NewElts.size()); 806 807 // Convert the new vector to the old vector type. 808 return DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, NewVec); 809} 810 811SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { 812 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 813 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 814 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 815 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && 816 "can only promote integer arguments"); 817 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 818 return DAG.getConvertRndSat(N->getValueType(0), InOp, 819 N->getOperand(1), N->getOperand(2), 820 N->getOperand(3), N->getOperand(4), CvtCode); 821} 822 823SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 824 unsigned OpNo) { 825 if (OpNo == 1) { 826 // Promote the inserted value. This is valid because the type does not 827 // have to match the vector element type. 828 829 // Check that any extra bits introduced will be truncated away. 830 assert(N->getOperand(1).getValueType().getSizeInBits() >= 831 N->getValueType(0).getVectorElementType().getSizeInBits() && 832 "Type of inserted value narrower than vector element type!"); 833 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 834 GetPromotedInteger(N->getOperand(1)), 835 N->getOperand(2)); 836 } 837 838 assert(OpNo == 2 && "Different operand and result vector types?"); 839 840 // Promote the index. 841 SDValue Idx = ZExtPromotedInteger(N->getOperand(2)); 842 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 843 N->getOperand(1), Idx); 844} 845 846SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 847 SDValue NewOps[6]; 848 NewOps[0] = N->getOperand(0); 849 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 850 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 851 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1); 852 } 853 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, 854 array_lengthof(NewOps)); 855} 856 857SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 858 assert(OpNo == 0 && "Only know how to promote condition"); 859 860 // Promote all the way up to the canonical SetCC type. 861 MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType()); 862 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT); 863 864 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, 865 N->getOperand(1), N->getOperand(2)); 866} 867 868SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 869 assert(OpNo == 0 && "Don't know how to promote this operand!"); 870 871 SDValue LHS = N->getOperand(0); 872 SDValue RHS = N->getOperand(1); 873 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 874 875 // The CC (#4) and the possible return values (#2 and #3) have legal types. 876 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2), 877 N->getOperand(3), N->getOperand(4)); 878} 879 880SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 881 assert(OpNo == 0 && "Don't know how to promote this operand!"); 882 883 SDValue LHS = N->getOperand(0); 884 SDValue RHS = N->getOperand(1); 885 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 886 887 // The CC (#2) is always legal. 888 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2)); 889} 890 891SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 892 SDValue Op = GetPromotedInteger(N->getOperand(0)); 893 DebugLoc dl = N->getDebugLoc(); 894 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 895 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), 896 Op, DAG.getValueType(N->getOperand(0).getValueType())); 897} 898 899SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) { 900 return DAG.UpdateNodeOperands(SDValue(N, 0), 901 SExtPromotedInteger(N->getOperand(0))); 902} 903 904SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 905 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 906 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 907 int SVOffset = N->getSrcValueOffset(); 908 unsigned Alignment = N->getAlignment(); 909 bool isVolatile = N->isVolatile(); 910 DebugLoc dl = N->getDebugLoc(); 911 912 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 913 914 // Truncate the value and store the result. 915 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(), 916 SVOffset, N->getMemoryVT(), 917 isVolatile, Alignment); 918} 919 920SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 921 SDValue Op = GetPromotedInteger(N->getOperand(0)); 922 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op); 923} 924 925SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { 926 return DAG.UpdateNodeOperands(SDValue(N, 0), 927 ZExtPromotedInteger(N->getOperand(0))); 928} 929 930SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 931 SDValue Op = GetPromotedInteger(N->getOperand(0)); 932 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); 933 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); 934} 935 936 937//===----------------------------------------------------------------------===// 938// Integer Result Expansion 939//===----------------------------------------------------------------------===// 940 941/// ExpandIntegerResult - This method is called when the specified result of the 942/// specified node is found to need expansion. At this point, the node may also 943/// have invalid operands or may have other results that need promotion, we just 944/// know that (at least) one result needs expansion. 945void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 946 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n"); 947 SDValue Lo, Hi; 948 Lo = Hi = SDValue(); 949 950 // See if the target wants to custom expand this node. 951 if (CustomLowerResults(N, N->getValueType(ResNo), true)) 952 return; 953 954 switch (N->getOpcode()) { 955 default: 956#ifndef NDEBUG 957 cerr << "ExpandIntegerResult #" << ResNo << ": "; 958 N->dump(&DAG); cerr << "\n"; 959#endif 960 assert(0 && "Do not know how to expand the result of this operator!"); 961 abort(); 962 963 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 964 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 965 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 966 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 967 968 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 969 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 970 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 971 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 972 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 973 974 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 975 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 976 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 977 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 978 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 979 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 980 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 981 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 982 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 983 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 984 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 985 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 986 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 987 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 988 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 989 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 990 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 991 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 992 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 993 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 994 995 case ISD::AND: 996 case ISD::OR: 997 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 998 999 case ISD::ADD: 1000 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1001 1002 case ISD::ADDC: 1003 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 1004 1005 case ISD::ADDE: 1006 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 1007 1008 case ISD::SHL: 1009 case ISD::SRA: 1010 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1011 } 1012 1013 // If Lo/Hi is null, the sub-method took care of registering results etc. 1014 if (Lo.getNode()) 1015 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1016} 1017 1018/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1019/// and the shift amount is a constant 'Amt'. Expand the operation. 1020void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1021 SDValue &Lo, SDValue &Hi) { 1022 DebugLoc dl = N->getDebugLoc(); 1023 // Expand the incoming operand to be shifted, so that we have its parts 1024 SDValue InL, InH; 1025 GetExpandedInteger(N->getOperand(0), InL, InH); 1026 1027 MVT NVT = InL.getValueType(); 1028 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1029 unsigned NVTBits = NVT.getSizeInBits(); 1030 MVT ShTy = N->getOperand(1).getValueType(); 1031 1032 if (N->getOpcode() == ISD::SHL) { 1033 if (Amt > VTBits) { 1034 Lo = Hi = DAG.getConstant(0, NVT); 1035 } else if (Amt > NVTBits) { 1036 Lo = DAG.getConstant(0, NVT); 1037 Hi = DAG.getNode(ISD::SHL, dl, 1038 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1039 } else if (Amt == NVTBits) { 1040 Lo = DAG.getConstant(0, NVT); 1041 Hi = InL; 1042 } else if (Amt == 1 && 1043 TLI.isOperationLegalOrCustom(ISD::ADDC, 1044 TLI.getTypeToExpandTo(NVT))) { 1045 // Emit this X << 1 as X+X. 1046 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1047 SDValue LoOps[2] = { InL, InL }; 1048 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1049 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1050 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1051 } else { 1052 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy)); 1053 Hi = DAG.getNode(ISD::OR, dl, NVT, 1054 DAG.getNode(ISD::SHL, dl, NVT, InH, 1055 DAG.getConstant(Amt, ShTy)), 1056 DAG.getNode(ISD::SRL, dl, NVT, InL, 1057 DAG.getConstant(NVTBits-Amt, ShTy))); 1058 } 1059 return; 1060 } 1061 1062 if (N->getOpcode() == ISD::SRL) { 1063 if (Amt > VTBits) { 1064 Lo = DAG.getConstant(0, NVT); 1065 Hi = DAG.getConstant(0, NVT); 1066 } else if (Amt > NVTBits) { 1067 Lo = DAG.getNode(ISD::SRL, dl, 1068 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1069 Hi = DAG.getConstant(0, NVT); 1070 } else if (Amt == NVTBits) { 1071 Lo = InH; 1072 Hi = DAG.getConstant(0, NVT); 1073 } else { 1074 Lo = DAG.getNode(ISD::OR, dl, NVT, 1075 DAG.getNode(ISD::SRL, dl, NVT, InL, 1076 DAG.getConstant(Amt, ShTy)), 1077 DAG.getNode(ISD::SHL, dl, NVT, InH, 1078 DAG.getConstant(NVTBits-Amt, ShTy))); 1079 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); 1080 } 1081 return; 1082 } 1083 1084 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1085 if (Amt > VTBits) { 1086 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 1087 DAG.getConstant(NVTBits-1, ShTy)); 1088 } else if (Amt > NVTBits) { 1089 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 1090 DAG.getConstant(Amt-NVTBits, ShTy)); 1091 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 1092 DAG.getConstant(NVTBits-1, ShTy)); 1093 } else if (Amt == NVTBits) { 1094 Lo = InH; 1095 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 1096 DAG.getConstant(NVTBits-1, ShTy)); 1097 } else { 1098 Lo = DAG.getNode(ISD::OR, NVT, 1099 DAG.getNode(ISD::SRL, dl, NVT, InL, 1100 DAG.getConstant(Amt, ShTy)), 1101 DAG.getNode(ISD::SHL, dl, NVT, InH, 1102 DAG.getConstant(NVTBits-Amt, ShTy))); 1103 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); 1104 } 1105} 1106 1107/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1108/// this shift based on knowledge of the high bit of the shift amount. If we 1109/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1110/// shift amount. 1111bool DAGTypeLegalizer:: 1112ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1113 SDValue Amt = N->getOperand(1); 1114 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1115 MVT ShTy = Amt.getValueType(); 1116 unsigned ShBits = ShTy.getSizeInBits(); 1117 unsigned NVTBits = NVT.getSizeInBits(); 1118 assert(isPowerOf2_32(NVTBits) && 1119 "Expanded integer type size not a power of two!"); 1120 DebugLoc dl = N->getDebugLoc(); 1121 1122 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1123 APInt KnownZero, KnownOne; 1124 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1125 1126 // If we don't know anything about the high bits, exit. 1127 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1128 return false; 1129 1130 // Get the incoming operand to be shifted. 1131 SDValue InL, InH; 1132 GetExpandedInteger(N->getOperand(0), InL, InH); 1133 1134 // If we know that any of the high bits of the shift amount are one, then we 1135 // can do this as a couple of simple shifts. 1136 if (KnownOne.intersects(HighBitMask)) { 1137 // Mask out the high bit, which we know is set. 1138 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, 1139 DAG.getConstant(~HighBitMask, ShTy)); 1140 1141 switch (N->getOpcode()) { 1142 default: assert(0 && "Unknown shift"); 1143 case ISD::SHL: 1144 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1145 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 1146 return true; 1147 case ISD::SRL: 1148 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1149 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 1150 return true; 1151 case ISD::SRA: 1152 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 1153 DAG.getConstant(NVTBits-1, ShTy)); 1154 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 1155 return true; 1156 } 1157 } 1158 1159#if 0 1160 // FIXME: This code is broken for shifts with a zero amount! 1161 // If we know that all of the high bits of the shift amount are zero, then we 1162 // can do this as a couple of simple shifts. 1163 if ((KnownZero & HighBitMask) == HighBitMask) { 1164 // Compute 32-amt. 1165 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1166 DAG.getConstant(NVTBits, ShTy), 1167 Amt); 1168 unsigned Op1, Op2; 1169 switch (N->getOpcode()) { 1170 default: assert(0 && "Unknown shift"); 1171 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1172 case ISD::SRL: 1173 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1174 } 1175 1176 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1177 Hi = DAG.getNode(ISD::OR, NVT, 1178 DAG.getNode(Op1, NVT, InH, Amt), 1179 DAG.getNode(Op2, NVT, InL, Amt2)); 1180 return true; 1181 } 1182#endif 1183 1184 return false; 1185} 1186 1187void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1188 SDValue &Lo, SDValue &Hi) { 1189 DebugLoc dl = N->getDebugLoc(); 1190 // Expand the subcomponents. 1191 SDValue LHSL, LHSH, RHSL, RHSH; 1192 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1193 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1194 1195 MVT NVT = LHSL.getValueType(); 1196 SDValue LoOps[2] = { LHSL, RHSL }; 1197 SDValue HiOps[3] = { LHSH, RHSH }; 1198 1199 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1200 // them. TODO: Teach operation legalization how to expand unsupported 1201 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1202 // a carry of type MVT::Flag, but there doesn't seem to be any way to 1203 // generate a value of this type in the expanded code sequence. 1204 bool hasCarry = 1205 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? 1206 ISD::ADDC : ISD::SUBC, 1207 TLI.getTypeToExpandTo(NVT)); 1208 1209 if (hasCarry) { 1210 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1211 if (N->getOpcode() == ISD::ADD) { 1212 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1213 HiOps[2] = Lo.getValue(1); 1214 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1215 } else { 1216 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1217 HiOps[2] = Lo.getValue(1); 1218 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1219 } 1220 } else { 1221 if (N->getOpcode() == ISD::ADD) { 1222 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); 1223 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); 1224 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0], 1225 ISD::SETULT); 1226 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1, 1227 DAG.getConstant(1, NVT), 1228 DAG.getConstant(0, NVT)); 1229 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1], 1230 ISD::SETULT); 1231 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2, 1232 DAG.getConstant(1, NVT), Carry1); 1233 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); 1234 } else { 1235 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); 1236 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); 1237 SDValue Cmp = 1238 DAG.getSetCC(TLI.getSetCCResultType(LoOps[0].getValueType()), 1239 LoOps[0], LoOps[1], ISD::SETULT); 1240 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, 1241 DAG.getConstant(1, NVT), 1242 DAG.getConstant(0, NVT)); 1243 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); 1244 } 1245 } 1246} 1247 1248void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1249 SDValue &Lo, SDValue &Hi) { 1250 // Expand the subcomponents. 1251 SDValue LHSL, LHSH, RHSL, RHSH; 1252 DebugLoc dl = N->getDebugLoc(); 1253 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1254 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1255 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1256 SDValue LoOps[2] = { LHSL, RHSL }; 1257 SDValue HiOps[3] = { LHSH, RHSH }; 1258 1259 if (N->getOpcode() == ISD::ADDC) { 1260 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1261 HiOps[2] = Lo.getValue(1); 1262 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1263 } else { 1264 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1265 HiOps[2] = Lo.getValue(1); 1266 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1267 } 1268 1269 // Legalized the flag result - switch anything that used the old flag to 1270 // use the new one. 1271 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1272} 1273 1274void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1275 SDValue &Lo, SDValue &Hi) { 1276 // Expand the subcomponents. 1277 SDValue LHSL, LHSH, RHSL, RHSH; 1278 DebugLoc dl = N->getDebugLoc(); 1279 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1280 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1281 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1282 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1283 SDValue HiOps[3] = { LHSH, RHSH }; 1284 1285 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3); 1286 HiOps[2] = Lo.getValue(1); 1287 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); 1288 1289 // Legalized the flag result - switch anything that used the old flag to 1290 // use the new one. 1291 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1292} 1293 1294void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1295 SDValue &Lo, SDValue &Hi) { 1296 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1297 DebugLoc dl = N->getDebugLoc(); 1298 SDValue Op = N->getOperand(0); 1299 if (Op.getValueType().bitsLE(NVT)) { 1300 // The low part is any extension of the input (which degenerates to a copy). 1301 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op); 1302 Hi = DAG.getNode(ISD::UNDEF, dl, NVT); // The high part is undefined. 1303 } else { 1304 // For example, extension of an i48 to an i64. The operand type necessarily 1305 // promotes to the result type, so will end up being expanded too. 1306 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1307 "Only know how to promote this result!"); 1308 SDValue Res = GetPromotedInteger(Op); 1309 assert(Res.getValueType() == N->getValueType(0) && 1310 "Operand over promoted?"); 1311 // Split the promoted operand. This will simplify when it is expanded. 1312 SplitInteger(Res, Lo, Hi); 1313 } 1314} 1315 1316void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1317 SDValue &Lo, SDValue &Hi) { 1318 DebugLoc dl = N->getDebugLoc(); 1319 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1320 MVT NVT = Lo.getValueType(); 1321 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1322 unsigned NVTBits = NVT.getSizeInBits(); 1323 unsigned EVTBits = EVT.getSizeInBits(); 1324 1325 if (NVTBits < EVTBits) { 1326 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, 1327 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1328 } else { 1329 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); 1330 // The high part replicates the sign bit of Lo, make it explicit. 1331 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1332 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy())); 1333 } 1334} 1335 1336void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1337 SDValue &Lo, SDValue &Hi) { 1338 DebugLoc dl = N->getDebugLoc(); 1339 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1340 MVT NVT = Lo.getValueType(); 1341 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1342 unsigned NVTBits = NVT.getSizeInBits(); 1343 unsigned EVTBits = EVT.getSizeInBits(); 1344 1345 if (NVTBits < EVTBits) { 1346 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, 1347 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1348 } else { 1349 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); 1350 // The high part must be zero, make it explicit. 1351 Hi = DAG.getConstant(0, NVT); 1352 } 1353} 1354 1355void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1356 SDValue &Lo, SDValue &Hi) { 1357 DebugLoc dl = N->getDebugLoc(); 1358 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1359 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo); 1360 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi); 1361} 1362 1363void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1364 SDValue &Lo, SDValue &Hi) { 1365 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1366 unsigned NBitWidth = NVT.getSizeInBits(); 1367 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1368 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 1369 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1370} 1371 1372void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1373 SDValue &Lo, SDValue &Hi) { 1374 DebugLoc dl = N->getDebugLoc(); 1375 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1376 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1377 MVT NVT = Lo.getValueType(); 1378 1379 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi, 1380 DAG.getConstant(0, NVT), ISD::SETNE); 1381 1382 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo); 1383 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi); 1384 1385 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ, 1386 DAG.getNode(ISD::ADD, dl, NVT, LoLZ, 1387 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1388 Hi = DAG.getConstant(0, NVT); 1389} 1390 1391void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1392 SDValue &Lo, SDValue &Hi) { 1393 DebugLoc dl = N->getDebugLoc(); 1394 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1395 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1396 MVT NVT = Lo.getValueType(); 1397 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), 1398 DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); 1399 Hi = DAG.getConstant(0, NVT); 1400} 1401 1402void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1403 SDValue &Lo, SDValue &Hi) { 1404 DebugLoc dl = N->getDebugLoc(); 1405 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1406 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1407 MVT NVT = Lo.getValueType(); 1408 1409 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, 1410 DAG.getConstant(0, NVT), ISD::SETNE); 1411 1412 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo); 1413 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi); 1414 1415 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ, 1416 DAG.getNode(ISD::ADD, dl, NVT, HiLZ, 1417 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1418 Hi = DAG.getConstant(0, NVT); 1419} 1420 1421void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1422 SDValue &Hi) { 1423 DebugLoc dl = N->getDebugLoc(); 1424 MVT VT = N->getValueType(0); 1425 SDValue Op = N->getOperand(0); 1426 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1427 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1428 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi); 1429} 1430 1431void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1432 SDValue &Hi) { 1433 DebugLoc dl = N->getDebugLoc(); 1434 MVT VT = N->getValueType(0); 1435 SDValue Op = N->getOperand(0); 1436 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1437 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1438 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi); 1439} 1440 1441void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1442 SDValue &Lo, SDValue &Hi) { 1443 if (ISD::isNormalLoad(N)) { 1444 ExpandRes_NormalLoad(N, Lo, Hi); 1445 return; 1446 } 1447 1448 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1449 1450 MVT VT = N->getValueType(0); 1451 MVT NVT = TLI.getTypeToTransformTo(VT); 1452 SDValue Ch = N->getChain(); 1453 SDValue Ptr = N->getBasePtr(); 1454 ISD::LoadExtType ExtType = N->getExtensionType(); 1455 int SVOffset = N->getSrcValueOffset(); 1456 unsigned Alignment = N->getAlignment(); 1457 bool isVolatile = N->isVolatile(); 1458 DebugLoc dl = N->getDebugLoc(); 1459 1460 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1461 1462 if (N->getMemoryVT().bitsLE(NVT)) { 1463 MVT EVT = N->getMemoryVT(); 1464 1465 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1466 EVT, isVolatile, Alignment); 1467 1468 // Remember the chain. 1469 Ch = Lo.getValue(1); 1470 1471 if (ExtType == ISD::SEXTLOAD) { 1472 // The high part is obtained by SRA'ing all but one of the bits of the 1473 // lo part. 1474 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1475 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1476 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1477 } else if (ExtType == ISD::ZEXTLOAD) { 1478 // The high part is just a zero. 1479 Hi = DAG.getConstant(0, NVT); 1480 } else { 1481 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1482 // The high part is undefined. 1483 Hi = DAG.getNode(ISD::UNDEF, dl, NVT); 1484 } 1485 } else if (TLI.isLittleEndian()) { 1486 // Little-endian - low bits are at low addresses. 1487 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset, 1488 isVolatile, Alignment); 1489 1490 unsigned ExcessBits = 1491 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1492 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1493 1494 // Increment the pointer to the other half. 1495 unsigned IncrementSize = NVT.getSizeInBits()/8; 1496 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1497 DAG.getIntPtrConstant(IncrementSize)); 1498 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), 1499 SVOffset+IncrementSize, NEVT, 1500 isVolatile, MinAlign(Alignment, IncrementSize)); 1501 1502 // Build a factor node to remember that this load is independent of the 1503 // other one. 1504 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1505 Hi.getValue(1)); 1506 } else { 1507 // Big-endian - high bits are at low addresses. Favor aligned loads at 1508 // the cost of some bit-fiddling. 1509 MVT EVT = N->getMemoryVT(); 1510 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1511 unsigned IncrementSize = NVT.getSizeInBits()/8; 1512 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1513 1514 // Load both the high bits and maybe some of the low bits. 1515 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1516 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), 1517 isVolatile, Alignment); 1518 1519 // Increment the pointer to the other half. 1520 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1521 DAG.getIntPtrConstant(IncrementSize)); 1522 // Load the rest of the low bits. 1523 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(), 1524 SVOffset+IncrementSize, 1525 MVT::getIntegerVT(ExcessBits), 1526 isVolatile, MinAlign(Alignment, IncrementSize)); 1527 1528 // Build a factor node to remember that this load is independent of the 1529 // other one. 1530 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1531 Hi.getValue(1)); 1532 1533 if (ExcessBits < NVT.getSizeInBits()) { 1534 // Transfer low bits from the bottom of Hi to the top of Lo. 1535 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, 1536 DAG.getNode(ISD::SHL, dl, NVT, Hi, 1537 DAG.getConstant(ExcessBits, 1538 TLI.getShiftAmountTy()))); 1539 // Move high bits to the right position in Hi. 1540 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, 1541 NVT, Hi, 1542 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1543 TLI.getShiftAmountTy())); 1544 } 1545 } 1546 1547 // Legalized the chain result - switch anything that used the old chain to 1548 // use the new one. 1549 ReplaceValueWith(SDValue(N, 1), Ch); 1550} 1551 1552void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1553 SDValue &Lo, SDValue &Hi) { 1554 DebugLoc dl = N->getDebugLoc(); 1555 SDValue LL, LH, RL, RH; 1556 GetExpandedInteger(N->getOperand(0), LL, LH); 1557 GetExpandedInteger(N->getOperand(1), RL, RH); 1558 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL); 1559 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); 1560} 1561 1562void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1563 SDValue &Lo, SDValue &Hi) { 1564 MVT VT = N->getValueType(0); 1565 MVT NVT = TLI.getTypeToTransformTo(VT); 1566 DebugLoc dl = N->getDebugLoc(); 1567 1568 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); 1569 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); 1570 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); 1571 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); 1572 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1573 SDValue LL, LH, RL, RH; 1574 GetExpandedInteger(N->getOperand(0), LL, LH); 1575 GetExpandedInteger(N->getOperand(1), RL, RH); 1576 unsigned OuterBitSize = VT.getSizeInBits(); 1577 unsigned InnerBitSize = NVT.getSizeInBits(); 1578 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1579 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1580 1581 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1582 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1583 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1584 // The inputs are both zero-extended. 1585 if (HasUMUL_LOHI) { 1586 // We can emit a umul_lohi. 1587 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1588 Hi = SDValue(Lo.getNode(), 1); 1589 return; 1590 } 1591 if (HasMULHU) { 1592 // We can emit a mulhu+mul. 1593 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1594 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1595 return; 1596 } 1597 } 1598 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1599 // The input values are both sign-extended. 1600 if (HasSMUL_LOHI) { 1601 // We can emit a smul_lohi. 1602 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1603 Hi = SDValue(Lo.getNode(), 1); 1604 return; 1605 } 1606 if (HasMULHS) { 1607 // We can emit a mulhs+mul. 1608 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1609 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); 1610 return; 1611 } 1612 } 1613 if (HasUMUL_LOHI) { 1614 // Lo,Hi = umul LHS, RHS. 1615 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, 1616 DAG.getVTList(NVT, NVT), LL, RL); 1617 Lo = UMulLOHI; 1618 Hi = UMulLOHI.getValue(1); 1619 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1620 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1621 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1622 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1623 return; 1624 } 1625 if (HasMULHU) { 1626 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1627 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1628 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1629 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1630 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1631 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1632 return; 1633 } 1634 } 1635 1636 // If nothing else, we can make a libcall. 1637 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1638 if (VT == MVT::i16) 1639 LC = RTLIB::MUL_I16; 1640 else if (VT == MVT::i32) 1641 LC = RTLIB::MUL_I32; 1642 else if (VT == MVT::i64) 1643 LC = RTLIB::MUL_I64; 1644 else if (VT == MVT::i128) 1645 LC = RTLIB::MUL_I128; 1646 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1647 1648 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1649 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi); 1650} 1651 1652void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1653 SDValue &Lo, SDValue &Hi) { 1654 MVT VT = N->getValueType(0); 1655 DebugLoc dl = N->getDebugLoc(); 1656 1657 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1658 if (VT == MVT::i32) 1659 LC = RTLIB::SDIV_I32; 1660 else if (VT == MVT::i64) 1661 LC = RTLIB::SDIV_I64; 1662 else if (VT == MVT::i128) 1663 LC = RTLIB::SDIV_I128; 1664 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1665 1666 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1667 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1668} 1669 1670void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1671 SDValue &Lo, SDValue &Hi) { 1672 MVT VT = N->getValueType(0); 1673 DebugLoc dl = N->getDebugLoc(); 1674 1675 // If we can emit an efficient shift operation, do so now. Check to see if 1676 // the RHS is a constant. 1677 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1678 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1679 1680 // If we can determine that the high bit of the shift is zero or one, even if 1681 // the low bits are variable, emit this shift in an optimized form. 1682 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1683 return; 1684 1685 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1686 unsigned PartsOpc; 1687 if (N->getOpcode() == ISD::SHL) { 1688 PartsOpc = ISD::SHL_PARTS; 1689 } else if (N->getOpcode() == ISD::SRL) { 1690 PartsOpc = ISD::SRL_PARTS; 1691 } else { 1692 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1693 PartsOpc = ISD::SRA_PARTS; 1694 } 1695 1696 // Next check to see if the target supports this SHL_PARTS operation or if it 1697 // will custom expand it. 1698 MVT NVT = TLI.getTypeToTransformTo(VT); 1699 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1700 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1701 Action == TargetLowering::Custom) { 1702 // Expand the subcomponents. 1703 SDValue LHSL, LHSH; 1704 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1705 1706 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1707 MVT VT = LHSL.getValueType(); 1708 Lo = DAG.getNode(PartsOpc, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 1709 Hi = Lo.getValue(1); 1710 return; 1711 } 1712 1713 // Otherwise, emit a libcall. 1714 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1715 bool isSigned; 1716 if (N->getOpcode() == ISD::SHL) { 1717 isSigned = false; /*sign irrelevant*/ 1718 if (VT == MVT::i16) 1719 LC = RTLIB::SHL_I16; 1720 else if (VT == MVT::i32) 1721 LC = RTLIB::SHL_I32; 1722 else if (VT == MVT::i64) 1723 LC = RTLIB::SHL_I64; 1724 else if (VT == MVT::i128) 1725 LC = RTLIB::SHL_I128; 1726 } else if (N->getOpcode() == ISD::SRL) { 1727 isSigned = false; 1728 if (VT == MVT::i16) 1729 LC = RTLIB::SRL_I16; 1730 else if (VT == MVT::i32) 1731 LC = RTLIB::SRL_I32; 1732 else if (VT == MVT::i64) 1733 LC = RTLIB::SRL_I64; 1734 else if (VT == MVT::i128) 1735 LC = RTLIB::SRL_I128; 1736 } else { 1737 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1738 isSigned = true; 1739 if (VT == MVT::i16) 1740 LC = RTLIB::SRA_I16; 1741 else if (VT == MVT::i32) 1742 LC = RTLIB::SRA_I32; 1743 else if (VT == MVT::i64) 1744 LC = RTLIB::SRA_I64; 1745 else if (VT == MVT::i128) 1746 LC = RTLIB::SRA_I128; 1747 } 1748 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!"); 1749 1750 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1751 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi); 1752} 1753 1754void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 1755 SDValue &Lo, SDValue &Hi) { 1756 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1757 DebugLoc dl = N->getDebugLoc(); 1758 SDValue Op = N->getOperand(0); 1759 if (Op.getValueType().bitsLE(NVT)) { 1760 // The low part is sign extension of the input (degenerates to a copy). 1761 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); 1762 // The high part is obtained by SRA'ing all but one of the bits of low part. 1763 unsigned LoSize = NVT.getSizeInBits(); 1764 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1765 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1766 } else { 1767 // For example, extension of an i48 to an i64. The operand type necessarily 1768 // promotes to the result type, so will end up being expanded too. 1769 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1770 "Only know how to promote this result!"); 1771 SDValue Res = GetPromotedInteger(Op); 1772 assert(Res.getValueType() == N->getValueType(0) && 1773 "Operand over promoted?"); 1774 // Split the promoted operand. This will simplify when it is expanded. 1775 SplitInteger(Res, Lo, Hi); 1776 unsigned ExcessBits = 1777 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1778 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 1779 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1780 } 1781} 1782 1783void DAGTypeLegalizer:: 1784ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 1785 DebugLoc dl = N->getDebugLoc(); 1786 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1787 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1788 1789 if (EVT.bitsLE(Lo.getValueType())) { 1790 // sext_inreg the low part if needed. 1791 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, 1792 N->getOperand(1)); 1793 1794 // The high part gets the sign extension from the lo-part. This handles 1795 // things like sextinreg V:i64 from i8. 1796 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo, 1797 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 1798 TLI.getShiftAmountTy())); 1799 } else { 1800 // For example, extension of an i48 to an i64. Leave the low part alone, 1801 // sext_inreg the high part. 1802 unsigned ExcessBits = 1803 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 1804 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 1805 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1806 } 1807} 1808 1809void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1810 SDValue &Lo, SDValue &Hi) { 1811 MVT VT = N->getValueType(0); 1812 DebugLoc dl = N->getDebugLoc(); 1813 1814 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1815 if (VT == MVT::i32) 1816 LC = RTLIB::SREM_I32; 1817 else if (VT == MVT::i64) 1818 LC = RTLIB::SREM_I64; 1819 else if (VT == MVT::i128) 1820 LC = RTLIB::SREM_I128; 1821 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1822 1823 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1824 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1825} 1826 1827void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 1828 SDValue &Lo, SDValue &Hi) { 1829 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1830 DebugLoc dl = N->getDebugLoc(); 1831 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); 1832 Hi = DAG.getNode(ISD::SRL, dl, 1833 N->getOperand(0).getValueType(), N->getOperand(0), 1834 DAG.getConstant(NVT.getSizeInBits(), 1835 TLI.getShiftAmountTy())); 1836 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); 1837} 1838 1839void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1840 SDValue &Lo, SDValue &Hi) { 1841 MVT VT = N->getValueType(0); 1842 DebugLoc dl = N->getDebugLoc(); 1843 1844 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1845 if (VT == MVT::i32) 1846 LC = RTLIB::UDIV_I32; 1847 else if (VT == MVT::i64) 1848 LC = RTLIB::UDIV_I64; 1849 else if (VT == MVT::i128) 1850 LC = RTLIB::UDIV_I128; 1851 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 1852 1853 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1854 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 1855} 1856 1857void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 1858 SDValue &Lo, SDValue &Hi) { 1859 MVT VT = N->getValueType(0); 1860 DebugLoc dl = N->getDebugLoc(); 1861 1862 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1863 if (VT == MVT::i32) 1864 LC = RTLIB::UREM_I32; 1865 else if (VT == MVT::i64) 1866 LC = RTLIB::UREM_I64; 1867 else if (VT == MVT::i128) 1868 LC = RTLIB::UREM_I128; 1869 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 1870 1871 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1872 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 1873} 1874 1875void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 1876 SDValue &Lo, SDValue &Hi) { 1877 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1878 DebugLoc dl = N->getDebugLoc(); 1879 SDValue Op = N->getOperand(0); 1880 if (Op.getValueType().bitsLE(NVT)) { 1881 // The low part is zero extension of the input (degenerates to a copy). 1882 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); 1883 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 1884 } else { 1885 // For example, extension of an i48 to an i64. The operand type necessarily 1886 // promotes to the result type, so will end up being expanded too. 1887 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1888 "Only know how to promote this result!"); 1889 SDValue Res = GetPromotedInteger(Op); 1890 assert(Res.getValueType() == N->getValueType(0) && 1891 "Operand over promoted?"); 1892 // Split the promoted operand. This will simplify when it is expanded. 1893 SplitInteger(Res, Lo, Hi); 1894 unsigned ExcessBits = 1895 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1896 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); 1897 } 1898} 1899 1900 1901//===----------------------------------------------------------------------===// 1902// Integer Operand Expansion 1903//===----------------------------------------------------------------------===// 1904 1905/// ExpandIntegerOperand - This method is called when the specified operand of 1906/// the specified node is found to need expansion. At this point, all of the 1907/// result types of the node are known to be legal, but other operands of the 1908/// node may need promotion or expansion as well as the specified one. 1909bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 1910 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n"); 1911 SDValue Res = SDValue(); 1912 1913 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false)) 1914 return false; 1915 1916 switch (N->getOpcode()) { 1917 default: 1918 #ifndef NDEBUG 1919 cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; 1920 N->dump(&DAG); cerr << "\n"; 1921 #endif 1922 assert(0 && "Do not know how to expand this operator's operand!"); 1923 abort(); 1924 1925 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 1926 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 1927 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 1928 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 1929 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; 1930 1931 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 1932 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 1933 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 1934 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 1935 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); 1936 break; 1937 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 1938 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 1939 } 1940 1941 // If the result is null, the sub-method took care of registering results etc. 1942 if (!Res.getNode()) return false; 1943 1944 // If the result is N, the sub-method updated N in place. Tell the legalizer 1945 // core about this. 1946 if (Res.getNode() == N) 1947 return true; 1948 1949 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1950 "Invalid operand expansion"); 1951 1952 ReplaceValueWith(SDValue(N, 0), Res); 1953 return false; 1954} 1955 1956/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 1957/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1958void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 1959 SDValue &NewRHS, 1960 ISD::CondCode &CCCode, 1961 DebugLoc dl) { 1962 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 1963 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 1964 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 1965 1966 MVT VT = NewLHS.getValueType(); 1967 1968 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 1969 if (RHSLo == RHSHi) { 1970 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 1971 if (RHSCST->isAllOnesValue()) { 1972 // Equality comparison to -1. 1973 NewLHS = DAG.getNode(ISD::AND, dl, 1974 LHSLo.getValueType(), LHSLo, LHSHi); 1975 NewRHS = RHSLo; 1976 return; 1977 } 1978 } 1979 } 1980 1981 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); 1982 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); 1983 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS); 1984 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1985 return; 1986 } 1987 1988 // If this is a comparison of the sign bit, just look at the top part. 1989 // X > -1, x < 0 1990 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 1991 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 1992 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 1993 NewLHS = LHSHi; 1994 NewRHS = RHSHi; 1995 return; 1996 } 1997 1998 // FIXME: This generated code sucks. 1999 ISD::CondCode LowCC; 2000 switch (CCCode) { 2001 default: assert(0 && "Unknown integer setcc!"); 2002 case ISD::SETLT: 2003 case ISD::SETULT: LowCC = ISD::SETULT; break; 2004 case ISD::SETGT: 2005 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2006 case ISD::SETLE: 2007 case ISD::SETULE: LowCC = ISD::SETULE; break; 2008 case ISD::SETGE: 2009 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2010 } 2011 2012 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2013 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2014 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2015 2016 // NOTE: on targets without efficient SELECT of bools, we can always use 2017 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2018 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 2019 SDValue Tmp1, Tmp2; 2020 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), 2021 LHSLo, RHSLo, LowCC, false, DagCombineInfo); 2022 if (!Tmp1.getNode()) 2023 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 2024 LHSLo, RHSLo, LowCC); 2025 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2026 LHSHi, RHSHi, CCCode, false, DagCombineInfo); 2027 if (!Tmp2.getNode()) 2028 Tmp2 = DAG.getNode(ISD::SETCC, dl, 2029 TLI.getSetCCResultType(LHSHi.getValueType()), 2030 LHSHi, RHSHi, DAG.getCondCode(CCCode)); 2031 2032 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2033 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2034 if ((Tmp1C && Tmp1C->isNullValue()) || 2035 (Tmp2C && Tmp2C->isNullValue() && 2036 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2037 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2038 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2039 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2040 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2041 // low part is known false, returns high part. 2042 // For LE / GE, if high part is known false, ignore the low part. 2043 // For LT / GT, if high part is known true, ignore the low part. 2044 NewLHS = Tmp2; 2045 NewRHS = SDValue(); 2046 return; 2047 } 2048 2049 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2050 LHSHi, RHSHi, ISD::SETEQ, false, DagCombineInfo); 2051 if (!NewLHS.getNode()) 2052 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 2053 LHSHi, RHSHi, ISD::SETEQ); 2054 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), 2055 NewLHS, Tmp1, Tmp2); 2056 NewRHS = SDValue(); 2057} 2058 2059SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2060 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2061 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2062 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2063 2064 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2065 // against zero to select between true and false values. 2066 if (NewRHS.getNode() == 0) { 2067 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2068 CCCode = ISD::SETNE; 2069 } 2070 2071 // Update N to have the operands specified. 2072 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 2073 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2074 N->getOperand(4)); 2075} 2076 2077SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2078 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2079 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2080 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2081 2082 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2083 // against zero to select between true and false values. 2084 if (NewRHS.getNode() == 0) { 2085 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2086 CCCode = ISD::SETNE; 2087 } 2088 2089 // Update N to have the operands specified. 2090 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2091 N->getOperand(2), N->getOperand(3), 2092 DAG.getCondCode(CCCode)); 2093} 2094 2095SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2096 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2097 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2098 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2099 2100 // If ExpandSetCCOperands returned a scalar, use it. 2101 if (NewRHS.getNode() == 0) { 2102 assert(NewLHS.getValueType() == N->getValueType(0) && 2103 "Unexpected setcc expansion!"); 2104 return NewLHS; 2105 } 2106 2107 // Otherwise, update N to have the operands specified. 2108 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2109 DAG.getCondCode(CCCode)); 2110} 2111 2112SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2113 SDValue Op = N->getOperand(0); 2114 MVT DstVT = N->getValueType(0); 2115 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2116 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2117 "Don't know how to expand this SINT_TO_FP!"); 2118 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc()); 2119} 2120 2121SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2122 if (ISD::isNormalStore(N)) 2123 return ExpandOp_NormalStore(N, OpNo); 2124 2125 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2126 assert(OpNo == 1 && "Can only expand the stored value so far"); 2127 2128 MVT VT = N->getOperand(1).getValueType(); 2129 MVT NVT = TLI.getTypeToTransformTo(VT); 2130 SDValue Ch = N->getChain(); 2131 SDValue Ptr = N->getBasePtr(); 2132 int SVOffset = N->getSrcValueOffset(); 2133 unsigned Alignment = N->getAlignment(); 2134 bool isVolatile = N->isVolatile(); 2135 DebugLoc dl = N->getDebugLoc(); 2136 SDValue Lo, Hi; 2137 2138 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2139 2140 if (N->getMemoryVT().bitsLE(NVT)) { 2141 GetExpandedInteger(N->getValue(), Lo, Hi); 2142 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, 2143 N->getMemoryVT(), isVolatile, Alignment); 2144 } else if (TLI.isLittleEndian()) { 2145 // Little-endian - low bits are at low addresses. 2146 GetExpandedInteger(N->getValue(), Lo, Hi); 2147 2148 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, 2149 isVolatile, Alignment); 2150 2151 unsigned ExcessBits = 2152 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2153 MVT NEVT = MVT::getIntegerVT(ExcessBits); 2154 2155 // Increment the pointer to the other half. 2156 unsigned IncrementSize = NVT.getSizeInBits()/8; 2157 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2158 DAG.getIntPtrConstant(IncrementSize)); 2159 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), 2160 SVOffset+IncrementSize, NEVT, 2161 isVolatile, MinAlign(Alignment, IncrementSize)); 2162 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2163 } else { 2164 // Big-endian - high bits are at low addresses. Favor aligned stores at 2165 // the cost of some bit-fiddling. 2166 GetExpandedInteger(N->getValue(), Lo, Hi); 2167 2168 MVT EVT = N->getMemoryVT(); 2169 unsigned EBytes = EVT.getStoreSizeInBits()/8; 2170 unsigned IncrementSize = NVT.getSizeInBits()/8; 2171 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2172 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); 2173 2174 if (ExcessBits < NVT.getSizeInBits()) { 2175 // Transfer high bits from the top of Lo to the bottom of Hi. 2176 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, 2177 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2178 TLI.getShiftAmountTy())); 2179 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, 2180 DAG.getNode(ISD::SRL, NVT, Lo, 2181 DAG.getConstant(ExcessBits, 2182 TLI.getShiftAmountTy()))); 2183 } 2184 2185 // Store both the high bits and maybe some of the low bits. 2186 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), 2187 SVOffset, HiVT, isVolatile, Alignment); 2188 2189 // Increment the pointer to the other half. 2190 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2191 DAG.getIntPtrConstant(IncrementSize)); 2192 // Store the lowest ExcessBits bits in the second half. 2193 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), 2194 SVOffset+IncrementSize, 2195 MVT::getIntegerVT(ExcessBits), 2196 isVolatile, MinAlign(Alignment, IncrementSize)); 2197 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2198 } 2199} 2200 2201SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2202 SDValue InL, InH; 2203 GetExpandedInteger(N->getOperand(0), InL, InH); 2204 // Just truncate the low part of the source. 2205 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL); 2206} 2207 2208SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2209 SDValue Op = N->getOperand(0); 2210 MVT SrcVT = Op.getValueType(); 2211 MVT DstVT = N->getValueType(0); 2212 DebugLoc dl = N->getDebugLoc(); 2213 2214 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2215 // Do a signed conversion then adjust the result. 2216 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); 2217 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2218 2219 // The result of the signed conversion needs adjusting if the 'sign bit' of 2220 // the incoming integer was set. To handle this, we dynamically test to see 2221 // if it is set, and, if so, add a fudge factor. 2222 2223 const uint64_t F32TwoE32 = 0x4F800000ULL; 2224 const uint64_t F32TwoE64 = 0x5F800000ULL; 2225 const uint64_t F32TwoE128 = 0x7F800000ULL; 2226 2227 APInt FF(32, 0); 2228 if (SrcVT == MVT::i32) 2229 FF = APInt(32, F32TwoE32); 2230 else if (SrcVT == MVT::i64) 2231 FF = APInt(32, F32TwoE64); 2232 else if (SrcVT == MVT::i128) 2233 FF = APInt(32, F32TwoE128); 2234 else 2235 assert(false && "Unsupported UINT_TO_FP!"); 2236 2237 // Check whether the sign bit is set. 2238 SDValue Lo, Hi; 2239 GetExpandedInteger(Op, Lo, Hi); 2240 SDValue SignSet = DAG.getSetCC(dl, 2241 TLI.getSetCCResultType(Hi.getValueType()), 2242 Hi, DAG.getConstant(0, Hi.getValueType()), 2243 ISD::SETLT); 2244 2245 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2246 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)), 2247 TLI.getPointerTy()); 2248 2249 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2250 SDValue Zero = DAG.getIntPtrConstant(0); 2251 SDValue Four = DAG.getIntPtrConstant(4); 2252 if (TLI.isBigEndian()) std::swap(Zero, Four); 2253 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 2254 Zero, Four); 2255 unsigned Alignment = 2256 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2257 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset); 2258 Alignment = std::min(Alignment, 4u); 2259 2260 // Load the value out, extending it from f32 to the destination float type. 2261 // FIXME: Avoid the extend by constructing the right constant pool? 2262 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), 2263 FudgePtr, NULL, 0, MVT::f32, 2264 false, Alignment); 2265 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); 2266 } 2267 2268 // Otherwise, use a libcall. 2269 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2270 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2271 "Don't know how to expand this UINT_TO_FP!"); 2272 return MakeLibCall(LC, DstVT, &Op, 1, true, dl); 2273} 2274