LegalizeIntegerTypes.cpp revision f1896f2694f5bc4aa4d10c3007821e0772889f24
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22#include "llvm/CodeGen/PseudoSourceValue.h" 23using namespace llvm; 24 25//===----------------------------------------------------------------------===// 26// Integer Result Promotion 27//===----------------------------------------------------------------------===// 28 29/// PromoteIntegerResult - This method is called when a result of a node is 30/// found to be in need of promotion to a larger type. At this point, the node 31/// may also have invalid operands or may have other results that need 32/// expansion, we just know that (at least) one result needs promotion. 33void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 34 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n"); 35 SDValue Res = SDValue(); 36 37 // See if the target wants to custom expand this node. 38 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 39 return; 40 41 switch (N->getOpcode()) { 42 default: 43#ifndef NDEBUG 44 cerr << "PromoteIntegerResult #" << ResNo << ": "; 45 N->dump(&DAG); cerr << "\n"; 46#endif 47 assert(0 && "Do not know how to promote this operator!"); 48 abort(); 49 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 50 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 51 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break; 52 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 53 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 54 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 55 case ISD::CONVERT_RNDSAT: 56 Res = PromoteIntRes_CONVERT_RNDSAT(N); break; 57 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; 58 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break; 59 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; 60 case ISD::EXTRACT_VECTOR_ELT: 61 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 62 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 63 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break; 64 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; 65 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 66 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; 67 case ISD::SIGN_EXTEND_INREG: 68 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 69 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 70 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; 71 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; 72 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break; 73 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break; 74 75 case ISD::SIGN_EXTEND: 76 case ISD::ZERO_EXTEND: 77 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; 78 79 case ISD::FP_TO_SINT: 80 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; 81 82 case ISD::AND: 83 case ISD::OR: 84 case ISD::XOR: 85 case ISD::ADD: 86 case ISD::SUB: 87 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break; 88 89 case ISD::SDIV: 90 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; 91 92 case ISD::UDIV: 93 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break; 94 95 case ISD::SADDO: 96 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; 97 case ISD::UADDO: 98 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; 99 case ISD::SMULO: 100 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; 101 102 case ISD::ATOMIC_LOAD_ADD: 103 case ISD::ATOMIC_LOAD_SUB: 104 case ISD::ATOMIC_LOAD_AND: 105 case ISD::ATOMIC_LOAD_OR: 106 case ISD::ATOMIC_LOAD_XOR: 107 case ISD::ATOMIC_LOAD_NAND: 108 case ISD::ATOMIC_LOAD_MIN: 109 case ISD::ATOMIC_LOAD_MAX: 110 case ISD::ATOMIC_LOAD_UMIN: 111 case ISD::ATOMIC_LOAD_UMAX: 112 case ISD::ATOMIC_SWAP: 113 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 114 115 case ISD::ATOMIC_CMP_SWAP: 116 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 117 } 118 119 // If the result is null then the sub-method took care of registering it. 120 if (Res.getNode()) 121 SetPromotedInteger(SDValue(N, ResNo), Res); 122} 123 124SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 125 // Sign-extend the new bits, and continue the assertion. 126 SDValue Op = SExtPromotedInteger(N->getOperand(0)); 127 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(), 128 Op.getValueType(), Op, N->getOperand(1)); 129} 130 131SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 132 // Zero the new bits, and continue the assertion. 133 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 134 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), 135 Op.getValueType(), Op, N->getOperand(1)); 136} 137 138SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 139 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 140 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 141 N->getMemoryVT(), 142 N->getChain(), N->getBasePtr(), 143 Op2, N->getSrcValue(), N->getAlignment()); 144 // Legalized the chain result - switch anything that used the old chain to 145 // use the new one. 146 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 147 return Res; 148} 149 150SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 151 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 152 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 153 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 154 N->getMemoryVT(), N->getChain(), N->getBasePtr(), 155 Op2, Op3, N->getSrcValue(), N->getAlignment()); 156 // Legalized the chain result - switch anything that used the old chain to 157 // use the new one. 158 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 159 return Res; 160} 161 162SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 163 SDValue InOp = N->getOperand(0); 164 MVT InVT = InOp.getValueType(); 165 MVT NInVT = TLI.getTypeToTransformTo(InVT); 166 MVT OutVT = N->getValueType(0); 167 MVT NOutVT = TLI.getTypeToTransformTo(OutVT); 168 DebugLoc dl = N->getDebugLoc(); 169 170 switch (getTypeAction(InVT)) { 171 default: 172 assert(false && "Unknown type action!"); 173 break; 174 case Legal: 175 break; 176 case PromoteInteger: 177 if (NOutVT.bitsEq(NInVT)) 178 // The input promotes to the same size. Convert the promoted value. 179 return DAG.getNode(ISD::BIT_CONVERT, dl, 180 NOutVT, GetPromotedInteger(InOp)); 181 break; 182 case SoftenFloat: 183 // Promote the integer operand by hand. 184 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); 185 case ExpandInteger: 186 case ExpandFloat: 187 break; 188 case ScalarizeVector: 189 // Convert the element to an integer and promote it by hand. 190 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 191 BitConvertToInteger(GetScalarizedVector(InOp))); 192 case SplitVector: { 193 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 194 // pieces of the input into integers and reassemble in the final type. 195 SDValue Lo, Hi; 196 GetSplitVector(N->getOperand(0), Lo, Hi); 197 Lo = BitConvertToInteger(Lo); 198 Hi = BitConvertToInteger(Hi); 199 200 if (TLI.isBigEndian()) 201 std::swap(Lo, Hi); 202 203 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, 204 MVT::getIntegerVT(NOutVT.getSizeInBits()), 205 JoinIntegers(Lo, Hi)); 206 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp); 207 } 208 case WidenVector: 209 if (OutVT.bitsEq(NInVT)) 210 // The input is widened to the same size. Convert to the widened value. 211 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp)); 212 } 213 214 // Otherwise, lower the bit-convert to a store/load from the stack. 215 // Create the stack frame object. Make sure it is aligned for both 216 // the source and destination types. 217 SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT); 218 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 219 const Value *SV = PseudoSourceValue::getFixedStack(FI); 220 221 // Emit a store to the stack slot. 222 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0); 223 224 // Result is an extending load from the stack slot. 225 return DAG.getExtLoad(ISD::EXTLOAD, dl, NOutVT, Store, FIPtr, SV, 0, OutVT); 226} 227 228SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 229 SDValue Op = GetPromotedInteger(N->getOperand(0)); 230 MVT OVT = N->getValueType(0); 231 MVT NVT = Op.getValueType(); 232 DebugLoc dl = N->getDebugLoc(); 233 234 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 235 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 236 DAG.getConstant(DiffBits, TLI.getPointerTy())); 237} 238 239SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 240 // The pair element type may be legal, or may not promote to the same type as 241 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 242 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), 243 TLI.getTypeToTransformTo(N->getValueType(0)), 244 JoinIntegers(N->getOperand(0), N->getOperand(1))); 245} 246 247SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 248 MVT VT = N->getValueType(0); 249 // FIXME there is no actual debug info here 250 DebugLoc dl = N->getDebugLoc(); 251 // Zero extend things like i1, sign extend everything else. It shouldn't 252 // matter in theory which one we pick, but this tends to give better code? 253 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 254 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(VT), 255 SDValue(N, 0)); 256 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 257 return Result; 258} 259 260SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 261 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 262 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 263 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 264 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 265 "can only promote integers"); 266 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 267 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0), 268 N->getOperand(1), N->getOperand(2), 269 N->getOperand(3), N->getOperand(4), CvtCode); 270} 271 272SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 273 // Zero extend to the promoted type and do the count there. 274 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 275 DebugLoc dl = N->getDebugLoc(); 276 MVT OVT = N->getValueType(0); 277 MVT NVT = Op.getValueType(); 278 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op); 279 // Subtract off the extra leading bits in the bigger type. 280 return DAG.getNode(ISD::SUB, dl, NVT, Op, 281 DAG.getConstant(NVT.getSizeInBits() - 282 OVT.getSizeInBits(), NVT)); 283} 284 285SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 286 // Zero extend to the promoted type and do the count there. 287 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 288 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op); 289} 290 291SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 292 SDValue Op = GetPromotedInteger(N->getOperand(0)); 293 MVT OVT = N->getValueType(0); 294 MVT NVT = Op.getValueType(); 295 DebugLoc dl = N->getDebugLoc(); 296 // The count is the same in the promoted type except if the original 297 // value was zero. This can be handled by setting the bit just off 298 // the top of the original type. 299 APInt TopBit(NVT.getSizeInBits(), 0); 300 TopBit.set(OVT.getSizeInBits()); 301 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT)); 302 return DAG.getNode(ISD::CTTZ, dl, NVT, Op); 303} 304 305SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 306 DebugLoc dl = N->getDebugLoc(); 307 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 308 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0), 309 N->getOperand(1)); 310} 311 312SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 313 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 314 unsigned NewOpc = N->getOpcode(); 315 DebugLoc dl = N->getDebugLoc(); 316 317 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is 318 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT 319 // and SINT conversions are Custom, there is no way to tell which is preferable. 320 // We choose SINT because that's the right thing on PPC.) 321 if (N->getOpcode() == ISD::FP_TO_UINT && 322 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 323 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) 324 NewOpc = ISD::FP_TO_SINT; 325 326 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); 327 328 // Assert that the converted value fits in the original type. If it doesn't 329 // (eg: because the value being converted is too big), then the result of the 330 // original operation was undefined anyway, so the assert is still correct. 331 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 332 ISD::AssertZext : ISD::AssertSext, dl, 333 NVT, Res, DAG.getValueType(N->getValueType(0))); 334} 335 336SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 337 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 338 DebugLoc dl = N->getDebugLoc(); 339 340 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 341 SDValue Res = GetPromotedInteger(N->getOperand(0)); 342 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 343 344 // If the result and operand types are the same after promotion, simplify 345 // to an in-register extension. 346 if (NVT == Res.getValueType()) { 347 // The high bits are not guaranteed to be anything. Insert an extend. 348 if (N->getOpcode() == ISD::SIGN_EXTEND) 349 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 350 DAG.getValueType(N->getOperand(0).getValueType())); 351 if (N->getOpcode() == ISD::ZERO_EXTEND) 352 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType()); 353 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 354 return Res; 355 } 356 } 357 358 // Otherwise, just extend the original operand all the way to the larger type. 359 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 360} 361 362SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 363 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 364 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 365 ISD::LoadExtType ExtType = 366 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 367 DebugLoc dl = N->getDebugLoc(); 368 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), 369 N->getSrcValue(), N->getSrcValueOffset(), 370 N->getMemoryVT(), N->isVolatile(), 371 N->getAlignment()); 372 373 // Legalized the chain result - switch anything that used the old chain to 374 // use the new one. 375 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 376 return Res; 377} 378 379/// Promote the overflow flag of an overflowing arithmetic node. 380SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { 381 // Simply change the return type of the boolean result. 382 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); 383 MVT ValueVTs[] = { N->getValueType(0), NVT }; 384 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) }; 385 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), 386 DAG.getVTList(ValueVTs, 2), Ops, 2); 387 388 // Modified the sum result - switch anything that used the old sum to use 389 // the new one. 390 ReplaceValueWith(SDValue(N, 0), Res); 391 392 return SDValue(Res.getNode(), 1); 393} 394 395SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { 396 if (ResNo == 1) 397 return PromoteIntRes_Overflow(N); 398 399 // The operation overflowed iff the result in the larger type is not the 400 // sign extension of its truncation to the original type. 401 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 402 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 403 MVT OVT = N->getOperand(0).getValueType(); 404 MVT NVT = LHS.getValueType(); 405 DebugLoc dl = N->getDebugLoc(); 406 407 // Do the arithmetic in the larger type. 408 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 409 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 410 411 // Calculate the overflow flag: sign extend the arithmetic result from 412 // the original type. 413 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 414 DAG.getValueType(OVT)); 415 // Overflowed if and only if this is not equal to Res. 416 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 417 418 // Use the calculated overflow everywhere. 419 ReplaceValueWith(SDValue(N, 1), Ofl); 420 421 return Res; 422} 423 424SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 425 // Sign extend the input. 426 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 427 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 428 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 429 LHS.getValueType(), LHS, RHS); 430} 431 432SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 433 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 434 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 435 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 436 LHS.getValueType(), N->getOperand(0),LHS,RHS); 437} 438 439SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 440 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 441 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 442 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 443 LHS.getValueType(), N->getOperand(0), 444 N->getOperand(1), LHS, RHS, N->getOperand(4)); 445} 446 447SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 448 MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); 449 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 450 DebugLoc dl = N->getDebugLoc(); 451 452 // Get the SETCC result using the canonical SETCC type. 453 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0), 454 N->getOperand(1), N->getOperand(2)); 455 456 // Convert to the expected type. 457 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 458 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 459 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 460} 461 462SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 463 return DAG.getNode(ISD::SHL, N->getDebugLoc(), 464 TLI.getTypeToTransformTo(N->getValueType(0)), 465 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 466} 467 468SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 469 SDValue Op = GetPromotedInteger(N->getOperand(0)); 470 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), 471 Op.getValueType(), Op, N->getOperand(1)); 472} 473 474SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 475 // The input may have strange things in the top bits of the registers, but 476 // these operations don't care. They may have weird bits going out, but 477 // that too is okay if they are integer operations. 478 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 479 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 480 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 481 LHS.getValueType(), LHS, RHS); 482} 483 484SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 485 // The input value must be properly sign extended. 486 SDValue Res = SExtPromotedInteger(N->getOperand(0)); 487 return DAG.getNode(ISD::SRA, N->getDebugLoc(), 488 Res.getValueType(), Res, N->getOperand(1)); 489} 490 491SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 492 // The input value must be properly zero extended. 493 MVT VT = N->getValueType(0); 494 MVT NVT = TLI.getTypeToTransformTo(VT); 495 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 496 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1)); 497} 498 499SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 500 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 501 SDValue Res; 502 503 switch (getTypeAction(N->getOperand(0).getValueType())) { 504 default: assert(0 && "Unknown type action!"); 505 case Legal: 506 case ExpandInteger: 507 Res = N->getOperand(0); 508 break; 509 case PromoteInteger: 510 Res = GetPromotedInteger(N->getOperand(0)); 511 break; 512 } 513 514 // Truncate to NVT instead of VT 515 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res); 516} 517 518SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) { 519 if (ResNo == 1) 520 return PromoteIntRes_Overflow(N); 521 522 // The operation overflowed iff the result in the larger type is not the 523 // zero extension of its truncation to the original type. 524 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 525 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 526 MVT OVT = N->getOperand(0).getValueType(); 527 MVT NVT = LHS.getValueType(); 528 DebugLoc dl = N->getDebugLoc(); 529 530 // Do the arithmetic in the larger type. 531 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 532 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 533 534 // Calculate the overflow flag: zero extend the arithmetic result from 535 // the original type. 536 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); 537 // Overflowed if and only if this is not equal to Res. 538 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 539 540 // Use the calculated overflow everywhere. 541 ReplaceValueWith(SDValue(N, 1), Ofl); 542 543 return Res; 544} 545 546SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 547 // Zero extend the input. 548 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 549 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 550 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 551 LHS.getValueType(), LHS, RHS); 552} 553 554SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 555 return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0))); 556} 557 558SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 559 SDValue Chain = N->getOperand(0); // Get the chain. 560 SDValue Ptr = N->getOperand(1); // Get the pointer. 561 MVT VT = N->getValueType(0); 562 DebugLoc dl = N->getDebugLoc(); 563 564 MVT RegVT = TLI.getRegisterType(VT); 565 unsigned NumRegs = TLI.getNumRegisters(VT); 566 // The argument is passed as NumRegs registers of type RegVT. 567 568 SmallVector<SDValue, 8> Parts(NumRegs); 569 for (unsigned i = 0; i < NumRegs; ++i) { 570 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2)); 571 Chain = Parts[i].getValue(1); 572 } 573 574 // Handle endianness of the load. 575 if (TLI.isBigEndian()) 576 std::reverse(Parts.begin(), Parts.end()); 577 578 // Assemble the parts in the promoted type. 579 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 580 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); 581 for (unsigned i = 1; i < NumRegs; ++i) { 582 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); 583 // Shift it to the right position and "or" it in. 584 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, 585 DAG.getConstant(i * RegVT.getSizeInBits(), 586 TLI.getPointerTy())); 587 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part); 588 } 589 590 // Modified the chain result - switch anything that used the old chain to 591 // use the new one. 592 ReplaceValueWith(SDValue(N, 1), Chain); 593 594 return Res; 595} 596 597SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) { 598 assert(ResNo == 1 && "Only boolean result promotion currently supported!"); 599 return PromoteIntRes_Overflow(N); 600} 601 602//===----------------------------------------------------------------------===// 603// Integer Operand Promotion 604//===----------------------------------------------------------------------===// 605 606/// PromoteIntegerOperand - This method is called when the specified operand of 607/// the specified node is found to need promotion. At this point, all of the 608/// result types of the node are known to be legal, but other operands of the 609/// node may need promotion or expansion as well as the specified one. 610bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 611 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n"); 612 SDValue Res = SDValue(); 613 614 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 615 return false; 616 617 switch (N->getOpcode()) { 618 default: 619 #ifndef NDEBUG 620 cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; 621 N->dump(&DAG); cerr << "\n"; 622 #endif 623 assert(0 && "Do not know how to promote this operator's operand!"); 624 abort(); 625 626 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 627 case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break; 628 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 629 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 630 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 631 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 632 case ISD::CONVERT_RNDSAT: 633 Res = PromoteIntOp_CONVERT_RNDSAT(N); break; 634 case ISD::INSERT_VECTOR_ELT: 635 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 636 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 637 case ISD::SCALAR_TO_VECTOR: 638 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break; 639 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 640 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 641 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 642 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 643 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; 644 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 645 OpNo); break; 646 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 647 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; 648 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 649 650 case ISD::SHL: 651 case ISD::SRA: 652 case ISD::SRL: 653 case ISD::ROTL: 654 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break; 655 } 656 657 // If the result is null, the sub-method took care of registering results etc. 658 if (!Res.getNode()) return false; 659 660 // If the result is N, the sub-method updated N in place. Tell the legalizer 661 // core about this. 662 if (Res.getNode() == N) 663 return true; 664 665 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 666 "Invalid operand expansion"); 667 668 ReplaceValueWith(SDValue(N, 0), Res); 669 return false; 670} 671 672/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 673/// shared among BR_CC, SELECT_CC, and SETCC handlers. 674void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 675 ISD::CondCode CCCode) { 676 // We have to insert explicit sign or zero extends. Note that we could 677 // insert sign extends for ALL conditions, but zero extend is cheaper on 678 // many machines (an AND instead of two shifts), so prefer it. 679 switch (CCCode) { 680 default: assert(0 && "Unknown integer comparison!"); 681 case ISD::SETEQ: 682 case ISD::SETNE: 683 case ISD::SETUGE: 684 case ISD::SETUGT: 685 case ISD::SETULE: 686 case ISD::SETULT: 687 // ALL of these operations will work if we either sign or zero extend 688 // the operands (including the unsigned comparisons!). Zero extend is 689 // usually a simpler/cheaper operation, so prefer it. 690 NewLHS = ZExtPromotedInteger(NewLHS); 691 NewRHS = ZExtPromotedInteger(NewRHS); 692 break; 693 case ISD::SETGE: 694 case ISD::SETGT: 695 case ISD::SETLT: 696 case ISD::SETLE: 697 NewLHS = SExtPromotedInteger(NewLHS); 698 NewRHS = SExtPromotedInteger(NewRHS); 699 break; 700 } 701} 702 703SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 704 SDValue Op = GetPromotedInteger(N->getOperand(0)); 705 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); 706} 707 708SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) { 709 // This should only occur in unusual situations like bitcasting to an 710 // x86_fp80, so just turn it into a store+load 711 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0)); 712} 713 714SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 715 assert(OpNo == 2 && "Don't know how to promote this operand!"); 716 717 SDValue LHS = N->getOperand(2); 718 SDValue RHS = N->getOperand(3); 719 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 720 721 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 722 // legal types. 723 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 724 N->getOperand(1), LHS, RHS, N->getOperand(4)); 725} 726 727SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 728 assert(OpNo == 1 && "only know how to promote condition"); 729 730 // Promote all the way up to the canonical SetCC type. 731 MVT SVT = TLI.getSetCCResultType(MVT::Other); 732 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT); 733 734 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 735 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond, 736 N->getOperand(2)); 737} 738 739SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 740 // Since the result type is legal, the operands must promote to it. 741 MVT OVT = N->getOperand(0).getValueType(); 742 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); 743 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 744 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 745 DebugLoc dl = N->getDebugLoc(); 746 747 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, 748 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy())); 749 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); 750} 751 752SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 753 // The vector type is legal but the element type is not. This implies 754 // that the vector is a power-of-two in length and that the element 755 // type does not have a strange size (eg: it is not i1). 756 MVT VecVT = N->getValueType(0); 757 unsigned NumElts = VecVT.getVectorNumElements(); 758 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 759 760 // Promote the inserted value. The type does not need to match the 761 // vector element type. Check that any extra bits introduced will be 762 // truncated away. 763 assert(N->getOperand(0).getValueType().getSizeInBits() >= 764 N->getValueType(0).getVectorElementType().getSizeInBits() && 765 "Type of inserted value narrower than vector element type!"); 766 767 SmallVector<SDValue, 16> NewOps; 768 for (unsigned i = 0; i < NumElts; ++i) 769 NewOps.push_back(GetPromotedInteger(N->getOperand(i))); 770 771 return DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NumElts); 772} 773 774SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { 775 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 776 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 777 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 778 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && 779 "can only promote integer arguments"); 780 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 781 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp, 782 N->getOperand(1), N->getOperand(2), 783 N->getOperand(3), N->getOperand(4), CvtCode); 784} 785 786SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 787 unsigned OpNo) { 788 if (OpNo == 1) { 789 // Promote the inserted value. This is valid because the type does not 790 // have to match the vector element type. 791 792 // Check that any extra bits introduced will be truncated away. 793 assert(N->getOperand(1).getValueType().getSizeInBits() >= 794 N->getValueType(0).getVectorElementType().getSizeInBits() && 795 "Type of inserted value narrower than vector element type!"); 796 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 797 GetPromotedInteger(N->getOperand(1)), 798 N->getOperand(2)); 799 } 800 801 assert(OpNo == 2 && "Different operand and result vector types?"); 802 803 // Promote the index. 804 SDValue Idx = ZExtPromotedInteger(N->getOperand(2)); 805 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 806 N->getOperand(1), Idx); 807} 808 809SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 810 SDValue NewOps[6]; 811 DebugLoc dl = N->getDebugLoc(); 812 NewOps[0] = N->getOperand(0); 813 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 814 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 815 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1); 816 } 817 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, 818 array_lengthof(NewOps)); 819} 820 821SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) { 822 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote 823 // the operand in place. 824 return DAG.UpdateNodeOperands(SDValue(N, 0), 825 GetPromotedInteger(N->getOperand(0))); 826} 827 828SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 829 assert(OpNo == 0 && "Only know how to promote condition"); 830 831 // Promote all the way up to the canonical SetCC type. 832 MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType()); 833 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT); 834 835 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, 836 N->getOperand(1), N->getOperand(2)); 837} 838 839SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 840 assert(OpNo == 0 && "Don't know how to promote this operand!"); 841 842 SDValue LHS = N->getOperand(0); 843 SDValue RHS = N->getOperand(1); 844 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 845 846 // The CC (#4) and the possible return values (#2 and #3) have legal types. 847 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2), 848 N->getOperand(3), N->getOperand(4)); 849} 850 851SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 852 assert(OpNo == 0 && "Don't know how to promote this operand!"); 853 854 SDValue LHS = N->getOperand(0); 855 SDValue RHS = N->getOperand(1); 856 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 857 858 // The CC (#2) is always legal. 859 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2)); 860} 861 862SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) { 863 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 864 ZExtPromotedInteger(N->getOperand(1))); 865} 866 867SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 868 SDValue Op = GetPromotedInteger(N->getOperand(0)); 869 DebugLoc dl = N->getDebugLoc(); 870 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 871 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), 872 Op, DAG.getValueType(N->getOperand(0).getValueType())); 873} 874 875SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) { 876 return DAG.UpdateNodeOperands(SDValue(N, 0), 877 SExtPromotedInteger(N->getOperand(0))); 878} 879 880SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 881 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 882 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 883 int SVOffset = N->getSrcValueOffset(); 884 unsigned Alignment = N->getAlignment(); 885 bool isVolatile = N->isVolatile(); 886 DebugLoc dl = N->getDebugLoc(); 887 888 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 889 890 // Truncate the value and store the result. 891 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(), 892 SVOffset, N->getMemoryVT(), 893 isVolatile, Alignment); 894} 895 896SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 897 SDValue Op = GetPromotedInteger(N->getOperand(0)); 898 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op); 899} 900 901SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { 902 return DAG.UpdateNodeOperands(SDValue(N, 0), 903 ZExtPromotedInteger(N->getOperand(0))); 904} 905 906SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 907 DebugLoc dl = N->getDebugLoc(); 908 SDValue Op = GetPromotedInteger(N->getOperand(0)); 909 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 910 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType()); 911} 912 913 914//===----------------------------------------------------------------------===// 915// Integer Result Expansion 916//===----------------------------------------------------------------------===// 917 918/// ExpandIntegerResult - This method is called when the specified result of the 919/// specified node is found to need expansion. At this point, the node may also 920/// have invalid operands or may have other results that need promotion, we just 921/// know that (at least) one result needs expansion. 922void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 923 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n"); 924 SDValue Lo, Hi; 925 Lo = Hi = SDValue(); 926 927 // See if the target wants to custom expand this node. 928 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 929 return; 930 931 switch (N->getOpcode()) { 932 default: 933#ifndef NDEBUG 934 cerr << "ExpandIntegerResult #" << ResNo << ": "; 935 N->dump(&DAG); cerr << "\n"; 936#endif 937 assert(0 && "Do not know how to expand the result of this operator!"); 938 abort(); 939 940 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 941 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 942 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 943 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 944 945 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 946 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 947 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 948 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 949 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 950 951 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 952 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 953 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 954 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 955 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 956 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 957 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 958 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 959 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 960 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 961 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 962 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 963 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 964 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 965 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 966 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 967 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 968 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 969 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 970 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 971 972 case ISD::AND: 973 case ISD::OR: 974 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 975 976 case ISD::ADD: 977 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 978 979 case ISD::ADDC: 980 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 981 982 case ISD::ADDE: 983 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 984 985 case ISD::SHL: 986 case ISD::SRA: 987 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 988 } 989 990 // If Lo/Hi is null, the sub-method took care of registering results etc. 991 if (Lo.getNode()) 992 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 993} 994 995/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 996/// and the shift amount is a constant 'Amt'. Expand the operation. 997void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 998 SDValue &Lo, SDValue &Hi) { 999 DebugLoc dl = N->getDebugLoc(); 1000 // Expand the incoming operand to be shifted, so that we have its parts 1001 SDValue InL, InH; 1002 GetExpandedInteger(N->getOperand(0), InL, InH); 1003 1004 MVT NVT = InL.getValueType(); 1005 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1006 unsigned NVTBits = NVT.getSizeInBits(); 1007 MVT ShTy = N->getOperand(1).getValueType(); 1008 1009 if (N->getOpcode() == ISD::SHL) { 1010 if (Amt > VTBits) { 1011 Lo = Hi = DAG.getConstant(0, NVT); 1012 } else if (Amt > NVTBits) { 1013 Lo = DAG.getConstant(0, NVT); 1014 Hi = DAG.getNode(ISD::SHL, dl, 1015 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1016 } else if (Amt == NVTBits) { 1017 Lo = DAG.getConstant(0, NVT); 1018 Hi = InL; 1019 } else if (Amt == 1 && 1020 TLI.isOperationLegalOrCustom(ISD::ADDC, 1021 TLI.getTypeToExpandTo(NVT))) { 1022 // Emit this X << 1 as X+X. 1023 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1024 SDValue LoOps[2] = { InL, InL }; 1025 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1026 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1027 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1028 } else { 1029 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy)); 1030 Hi = DAG.getNode(ISD::OR, dl, NVT, 1031 DAG.getNode(ISD::SHL, dl, NVT, InH, 1032 DAG.getConstant(Amt, ShTy)), 1033 DAG.getNode(ISD::SRL, dl, NVT, InL, 1034 DAG.getConstant(NVTBits-Amt, ShTy))); 1035 } 1036 return; 1037 } 1038 1039 if (N->getOpcode() == ISD::SRL) { 1040 if (Amt > VTBits) { 1041 Lo = DAG.getConstant(0, NVT); 1042 Hi = DAG.getConstant(0, NVT); 1043 } else if (Amt > NVTBits) { 1044 Lo = DAG.getNode(ISD::SRL, dl, 1045 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1046 Hi = DAG.getConstant(0, NVT); 1047 } else if (Amt == NVTBits) { 1048 Lo = InH; 1049 Hi = DAG.getConstant(0, NVT); 1050 } else { 1051 Lo = DAG.getNode(ISD::OR, dl, NVT, 1052 DAG.getNode(ISD::SRL, dl, NVT, InL, 1053 DAG.getConstant(Amt, ShTy)), 1054 DAG.getNode(ISD::SHL, dl, NVT, InH, 1055 DAG.getConstant(NVTBits-Amt, ShTy))); 1056 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); 1057 } 1058 return; 1059 } 1060 1061 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1062 if (Amt > VTBits) { 1063 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 1064 DAG.getConstant(NVTBits-1, ShTy)); 1065 } else if (Amt > NVTBits) { 1066 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 1067 DAG.getConstant(Amt-NVTBits, ShTy)); 1068 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 1069 DAG.getConstant(NVTBits-1, ShTy)); 1070 } else if (Amt == NVTBits) { 1071 Lo = InH; 1072 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 1073 DAG.getConstant(NVTBits-1, ShTy)); 1074 } else { 1075 Lo = DAG.getNode(ISD::OR, dl, NVT, 1076 DAG.getNode(ISD::SRL, dl, NVT, InL, 1077 DAG.getConstant(Amt, ShTy)), 1078 DAG.getNode(ISD::SHL, dl, NVT, InH, 1079 DAG.getConstant(NVTBits-Amt, ShTy))); 1080 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); 1081 } 1082} 1083 1084/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1085/// this shift based on knowledge of the high bit of the shift amount. If we 1086/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1087/// shift amount. 1088bool DAGTypeLegalizer:: 1089ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1090 SDValue Amt = N->getOperand(1); 1091 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1092 MVT ShTy = Amt.getValueType(); 1093 unsigned ShBits = ShTy.getSizeInBits(); 1094 unsigned NVTBits = NVT.getSizeInBits(); 1095 assert(isPowerOf2_32(NVTBits) && 1096 "Expanded integer type size not a power of two!"); 1097 DebugLoc dl = N->getDebugLoc(); 1098 1099 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1100 APInt KnownZero, KnownOne; 1101 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1102 1103 // If we don't know anything about the high bits, exit. 1104 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1105 return false; 1106 1107 // Get the incoming operand to be shifted. 1108 SDValue InL, InH; 1109 GetExpandedInteger(N->getOperand(0), InL, InH); 1110 1111 // If we know that any of the high bits of the shift amount are one, then we 1112 // can do this as a couple of simple shifts. 1113 if (KnownOne.intersects(HighBitMask)) { 1114 // Mask out the high bit, which we know is set. 1115 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, 1116 DAG.getConstant(~HighBitMask, ShTy)); 1117 1118 switch (N->getOpcode()) { 1119 default: assert(0 && "Unknown shift"); 1120 case ISD::SHL: 1121 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1122 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 1123 return true; 1124 case ISD::SRL: 1125 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1126 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 1127 return true; 1128 case ISD::SRA: 1129 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 1130 DAG.getConstant(NVTBits-1, ShTy)); 1131 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 1132 return true; 1133 } 1134 } 1135 1136#if 0 1137 // FIXME: This code is broken for shifts with a zero amount! 1138 // If we know that all of the high bits of the shift amount are zero, then we 1139 // can do this as a couple of simple shifts. 1140 if ((KnownZero & HighBitMask) == HighBitMask) { 1141 // Compute 32-amt. 1142 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1143 DAG.getConstant(NVTBits, ShTy), 1144 Amt); 1145 unsigned Op1, Op2; 1146 switch (N->getOpcode()) { 1147 default: assert(0 && "Unknown shift"); 1148 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1149 case ISD::SRL: 1150 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1151 } 1152 1153 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1154 Hi = DAG.getNode(ISD::OR, NVT, 1155 DAG.getNode(Op1, NVT, InH, Amt), 1156 DAG.getNode(Op2, NVT, InL, Amt2)); 1157 return true; 1158 } 1159#endif 1160 1161 return false; 1162} 1163 1164/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift 1165/// of any size. 1166bool DAGTypeLegalizer:: 1167ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1168 SDValue Amt = N->getOperand(1); 1169 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1170 MVT ShTy = Amt.getValueType(); 1171 unsigned NVTBits = NVT.getSizeInBits(); 1172 assert(isPowerOf2_32(NVTBits) && 1173 "Expanded integer type size not a power of two!"); 1174 DebugLoc dl = N->getDebugLoc(); 1175 1176 // Get the incoming operand to be shifted. 1177 SDValue InL, InH; 1178 GetExpandedInteger(N->getOperand(0), InL, InH); 1179 1180 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy); 1181 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt); 1182 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy), 1183 Amt, NVBitsNode, ISD::SETULT); 1184 1185 SDValue Lo1, Hi1, Lo2, Hi2; 1186 switch (N->getOpcode()) { 1187 default: assert(0 && "Unknown shift"); 1188 case ISD::SHL: 1189 // ShAmt < NVTBits 1190 Lo1 = DAG.getConstant(0, NVT); // Low part is zero. 1191 Hi1 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 1192 1193 // ShAmt >= NVTBits 1194 Lo2 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); 1195 Hi2 = DAG.getNode(ISD::OR, dl, NVT, 1196 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt), 1197 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2)); 1198 1199 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2); 1200 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2); 1201 return true; 1202 case ISD::SRL: 1203 // ShAmt < NVTBits 1204 Hi1 = DAG.getConstant(0, NVT); // Hi part is zero. 1205 Lo1 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 1206 1207 // ShAmt >= NVTBits 1208 Hi2 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); 1209 Lo2 = DAG.getNode(ISD::OR, dl, NVT, 1210 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1211 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2)); 1212 1213 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2); 1214 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2); 1215 return true; 1216 case ISD::SRA: 1217 // ShAmt < NVTBits 1218 Hi1 = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 1219 DAG.getConstant(NVTBits-1, ShTy)); 1220 Lo1 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 1221 1222 // ShAmt >= NVTBits 1223 Hi2 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); 1224 Lo2 = DAG.getNode(ISD::OR, dl, NVT, 1225 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1226 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2)); 1227 1228 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2); 1229 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2); 1230 return true; 1231 } 1232 1233 return false; 1234} 1235 1236void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1237 SDValue &Lo, SDValue &Hi) { 1238 DebugLoc dl = N->getDebugLoc(); 1239 // Expand the subcomponents. 1240 SDValue LHSL, LHSH, RHSL, RHSH; 1241 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1242 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1243 1244 MVT NVT = LHSL.getValueType(); 1245 SDValue LoOps[2] = { LHSL, RHSL }; 1246 SDValue HiOps[3] = { LHSH, RHSH }; 1247 1248 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1249 // them. TODO: Teach operation legalization how to expand unsupported 1250 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1251 // a carry of type MVT::Flag, but there doesn't seem to be any way to 1252 // generate a value of this type in the expanded code sequence. 1253 bool hasCarry = 1254 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? 1255 ISD::ADDC : ISD::SUBC, 1256 TLI.getTypeToExpandTo(NVT)); 1257 1258 if (hasCarry) { 1259 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1260 if (N->getOpcode() == ISD::ADD) { 1261 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1262 HiOps[2] = Lo.getValue(1); 1263 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1264 } else { 1265 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1266 HiOps[2] = Lo.getValue(1); 1267 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1268 } 1269 } else { 1270 if (N->getOpcode() == ISD::ADD) { 1271 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); 1272 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); 1273 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0], 1274 ISD::SETULT); 1275 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1, 1276 DAG.getConstant(1, NVT), 1277 DAG.getConstant(0, NVT)); 1278 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1], 1279 ISD::SETULT); 1280 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2, 1281 DAG.getConstant(1, NVT), Carry1); 1282 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); 1283 } else { 1284 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); 1285 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); 1286 SDValue Cmp = 1287 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()), 1288 LoOps[0], LoOps[1], ISD::SETULT); 1289 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, 1290 DAG.getConstant(1, NVT), 1291 DAG.getConstant(0, NVT)); 1292 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); 1293 } 1294 } 1295} 1296 1297void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1298 SDValue &Lo, SDValue &Hi) { 1299 // Expand the subcomponents. 1300 SDValue LHSL, LHSH, RHSL, RHSH; 1301 DebugLoc dl = N->getDebugLoc(); 1302 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1303 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1304 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1305 SDValue LoOps[2] = { LHSL, RHSL }; 1306 SDValue HiOps[3] = { LHSH, RHSH }; 1307 1308 if (N->getOpcode() == ISD::ADDC) { 1309 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1310 HiOps[2] = Lo.getValue(1); 1311 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1312 } else { 1313 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1314 HiOps[2] = Lo.getValue(1); 1315 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1316 } 1317 1318 // Legalized the flag result - switch anything that used the old flag to 1319 // use the new one. 1320 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1321} 1322 1323void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1324 SDValue &Lo, SDValue &Hi) { 1325 // Expand the subcomponents. 1326 SDValue LHSL, LHSH, RHSL, RHSH; 1327 DebugLoc dl = N->getDebugLoc(); 1328 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1329 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1330 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1331 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1332 SDValue HiOps[3] = { LHSH, RHSH }; 1333 1334 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3); 1335 HiOps[2] = Lo.getValue(1); 1336 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); 1337 1338 // Legalized the flag result - switch anything that used the old flag to 1339 // use the new one. 1340 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1341} 1342 1343void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1344 SDValue &Lo, SDValue &Hi) { 1345 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1346 DebugLoc dl = N->getDebugLoc(); 1347 SDValue Op = N->getOperand(0); 1348 if (Op.getValueType().bitsLE(NVT)) { 1349 // The low part is any extension of the input (which degenerates to a copy). 1350 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op); 1351 Hi = DAG.getUNDEF(NVT); // The high part is undefined. 1352 } else { 1353 // For example, extension of an i48 to an i64. The operand type necessarily 1354 // promotes to the result type, so will end up being expanded too. 1355 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1356 "Only know how to promote this result!"); 1357 SDValue Res = GetPromotedInteger(Op); 1358 assert(Res.getValueType() == N->getValueType(0) && 1359 "Operand over promoted?"); 1360 // Split the promoted operand. This will simplify when it is expanded. 1361 SplitInteger(Res, Lo, Hi); 1362 } 1363} 1364 1365void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1366 SDValue &Lo, SDValue &Hi) { 1367 DebugLoc dl = N->getDebugLoc(); 1368 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1369 MVT NVT = Lo.getValueType(); 1370 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1371 unsigned NVTBits = NVT.getSizeInBits(); 1372 unsigned EVTBits = EVT.getSizeInBits(); 1373 1374 if (NVTBits < EVTBits) { 1375 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, 1376 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1377 } else { 1378 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); 1379 // The high part replicates the sign bit of Lo, make it explicit. 1380 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1381 DAG.getConstant(NVTBits-1, TLI.getPointerTy())); 1382 } 1383} 1384 1385void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1386 SDValue &Lo, SDValue &Hi) { 1387 DebugLoc dl = N->getDebugLoc(); 1388 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1389 MVT NVT = Lo.getValueType(); 1390 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1391 unsigned NVTBits = NVT.getSizeInBits(); 1392 unsigned EVTBits = EVT.getSizeInBits(); 1393 1394 if (NVTBits < EVTBits) { 1395 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, 1396 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1397 } else { 1398 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); 1399 // The high part must be zero, make it explicit. 1400 Hi = DAG.getConstant(0, NVT); 1401 } 1402} 1403 1404void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1405 SDValue &Lo, SDValue &Hi) { 1406 DebugLoc dl = N->getDebugLoc(); 1407 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1408 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo); 1409 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi); 1410} 1411 1412void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1413 SDValue &Lo, SDValue &Hi) { 1414 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1415 unsigned NBitWidth = NVT.getSizeInBits(); 1416 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1417 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 1418 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1419} 1420 1421void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1422 SDValue &Lo, SDValue &Hi) { 1423 DebugLoc dl = N->getDebugLoc(); 1424 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1425 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1426 MVT NVT = Lo.getValueType(); 1427 1428 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi, 1429 DAG.getConstant(0, NVT), ISD::SETNE); 1430 1431 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo); 1432 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi); 1433 1434 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ, 1435 DAG.getNode(ISD::ADD, dl, NVT, LoLZ, 1436 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1437 Hi = DAG.getConstant(0, NVT); 1438} 1439 1440void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1441 SDValue &Lo, SDValue &Hi) { 1442 DebugLoc dl = N->getDebugLoc(); 1443 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1444 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1445 MVT NVT = Lo.getValueType(); 1446 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), 1447 DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); 1448 Hi = DAG.getConstant(0, NVT); 1449} 1450 1451void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1452 SDValue &Lo, SDValue &Hi) { 1453 DebugLoc dl = N->getDebugLoc(); 1454 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1455 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1456 MVT NVT = Lo.getValueType(); 1457 1458 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, 1459 DAG.getConstant(0, NVT), ISD::SETNE); 1460 1461 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo); 1462 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi); 1463 1464 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ, 1465 DAG.getNode(ISD::ADD, dl, NVT, HiLZ, 1466 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1467 Hi = DAG.getConstant(0, NVT); 1468} 1469 1470void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1471 SDValue &Hi) { 1472 DebugLoc dl = N->getDebugLoc(); 1473 MVT VT = N->getValueType(0); 1474 SDValue Op = N->getOperand(0); 1475 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1476 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1477 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi); 1478} 1479 1480void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1481 SDValue &Hi) { 1482 DebugLoc dl = N->getDebugLoc(); 1483 MVT VT = N->getValueType(0); 1484 SDValue Op = N->getOperand(0); 1485 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1486 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1487 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi); 1488} 1489 1490void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1491 SDValue &Lo, SDValue &Hi) { 1492 if (ISD::isNormalLoad(N)) { 1493 ExpandRes_NormalLoad(N, Lo, Hi); 1494 return; 1495 } 1496 1497 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1498 1499 MVT VT = N->getValueType(0); 1500 MVT NVT = TLI.getTypeToTransformTo(VT); 1501 SDValue Ch = N->getChain(); 1502 SDValue Ptr = N->getBasePtr(); 1503 ISD::LoadExtType ExtType = N->getExtensionType(); 1504 int SVOffset = N->getSrcValueOffset(); 1505 unsigned Alignment = N->getAlignment(); 1506 bool isVolatile = N->isVolatile(); 1507 DebugLoc dl = N->getDebugLoc(); 1508 1509 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1510 1511 if (N->getMemoryVT().bitsLE(NVT)) { 1512 MVT EVT = N->getMemoryVT(); 1513 1514 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1515 EVT, isVolatile, Alignment); 1516 1517 // Remember the chain. 1518 Ch = Lo.getValue(1); 1519 1520 if (ExtType == ISD::SEXTLOAD) { 1521 // The high part is obtained by SRA'ing all but one of the bits of the 1522 // lo part. 1523 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1524 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1525 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1526 } else if (ExtType == ISD::ZEXTLOAD) { 1527 // The high part is just a zero. 1528 Hi = DAG.getConstant(0, NVT); 1529 } else { 1530 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1531 // The high part is undefined. 1532 Hi = DAG.getUNDEF(NVT); 1533 } 1534 } else if (TLI.isLittleEndian()) { 1535 // Little-endian - low bits are at low addresses. 1536 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset, 1537 isVolatile, Alignment); 1538 1539 unsigned ExcessBits = 1540 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1541 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1542 1543 // Increment the pointer to the other half. 1544 unsigned IncrementSize = NVT.getSizeInBits()/8; 1545 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1546 DAG.getIntPtrConstant(IncrementSize)); 1547 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), 1548 SVOffset+IncrementSize, NEVT, 1549 isVolatile, MinAlign(Alignment, IncrementSize)); 1550 1551 // Build a factor node to remember that this load is independent of the 1552 // other one. 1553 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1554 Hi.getValue(1)); 1555 } else { 1556 // Big-endian - high bits are at low addresses. Favor aligned loads at 1557 // the cost of some bit-fiddling. 1558 MVT EVT = N->getMemoryVT(); 1559 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1560 unsigned IncrementSize = NVT.getSizeInBits()/8; 1561 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1562 1563 // Load both the high bits and maybe some of the low bits. 1564 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1565 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), 1566 isVolatile, Alignment); 1567 1568 // Increment the pointer to the other half. 1569 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1570 DAG.getIntPtrConstant(IncrementSize)); 1571 // Load the rest of the low bits. 1572 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(), 1573 SVOffset+IncrementSize, 1574 MVT::getIntegerVT(ExcessBits), 1575 isVolatile, MinAlign(Alignment, IncrementSize)); 1576 1577 // Build a factor node to remember that this load is independent of the 1578 // other one. 1579 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1580 Hi.getValue(1)); 1581 1582 if (ExcessBits < NVT.getSizeInBits()) { 1583 // Transfer low bits from the bottom of Hi to the top of Lo. 1584 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, 1585 DAG.getNode(ISD::SHL, dl, NVT, Hi, 1586 DAG.getConstant(ExcessBits, 1587 TLI.getPointerTy()))); 1588 // Move high bits to the right position in Hi. 1589 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, 1590 NVT, Hi, 1591 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1592 TLI.getPointerTy())); 1593 } 1594 } 1595 1596 // Legalized the chain result - switch anything that used the old chain to 1597 // use the new one. 1598 ReplaceValueWith(SDValue(N, 1), Ch); 1599} 1600 1601void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1602 SDValue &Lo, SDValue &Hi) { 1603 DebugLoc dl = N->getDebugLoc(); 1604 SDValue LL, LH, RL, RH; 1605 GetExpandedInteger(N->getOperand(0), LL, LH); 1606 GetExpandedInteger(N->getOperand(1), RL, RH); 1607 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL); 1608 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); 1609} 1610 1611void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1612 SDValue &Lo, SDValue &Hi) { 1613 MVT VT = N->getValueType(0); 1614 MVT NVT = TLI.getTypeToTransformTo(VT); 1615 DebugLoc dl = N->getDebugLoc(); 1616 1617 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); 1618 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); 1619 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); 1620 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); 1621 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1622 SDValue LL, LH, RL, RH; 1623 GetExpandedInteger(N->getOperand(0), LL, LH); 1624 GetExpandedInteger(N->getOperand(1), RL, RH); 1625 unsigned OuterBitSize = VT.getSizeInBits(); 1626 unsigned InnerBitSize = NVT.getSizeInBits(); 1627 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1628 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1629 1630 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1631 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1632 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1633 // The inputs are both zero-extended. 1634 if (HasUMUL_LOHI) { 1635 // We can emit a umul_lohi. 1636 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1637 Hi = SDValue(Lo.getNode(), 1); 1638 return; 1639 } 1640 if (HasMULHU) { 1641 // We can emit a mulhu+mul. 1642 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1643 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1644 return; 1645 } 1646 } 1647 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1648 // The input values are both sign-extended. 1649 if (HasSMUL_LOHI) { 1650 // We can emit a smul_lohi. 1651 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1652 Hi = SDValue(Lo.getNode(), 1); 1653 return; 1654 } 1655 if (HasMULHS) { 1656 // We can emit a mulhs+mul. 1657 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1658 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); 1659 return; 1660 } 1661 } 1662 if (HasUMUL_LOHI) { 1663 // Lo,Hi = umul LHS, RHS. 1664 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, 1665 DAG.getVTList(NVT, NVT), LL, RL); 1666 Lo = UMulLOHI; 1667 Hi = UMulLOHI.getValue(1); 1668 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1669 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1670 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1671 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1672 return; 1673 } 1674 if (HasMULHU) { 1675 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1676 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1677 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1678 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1679 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1680 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1681 return; 1682 } 1683 } 1684 1685 // If nothing else, we can make a libcall. 1686 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1687 if (VT == MVT::i16) 1688 LC = RTLIB::MUL_I16; 1689 else if (VT == MVT::i32) 1690 LC = RTLIB::MUL_I32; 1691 else if (VT == MVT::i64) 1692 LC = RTLIB::MUL_I64; 1693 else if (VT == MVT::i128) 1694 LC = RTLIB::MUL_I128; 1695 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1696 1697 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1698 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi); 1699} 1700 1701void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1702 SDValue &Lo, SDValue &Hi) { 1703 MVT VT = N->getValueType(0); 1704 DebugLoc dl = N->getDebugLoc(); 1705 1706 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1707 if (VT == MVT::i16) 1708 LC = RTLIB::SDIV_I16; 1709 else if (VT == MVT::i32) 1710 LC = RTLIB::SDIV_I32; 1711 else if (VT == MVT::i64) 1712 LC = RTLIB::SDIV_I64; 1713 else if (VT == MVT::i128) 1714 LC = RTLIB::SDIV_I128; 1715 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1716 1717 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1718 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1719} 1720 1721void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1722 SDValue &Lo, SDValue &Hi) { 1723 MVT VT = N->getValueType(0); 1724 DebugLoc dl = N->getDebugLoc(); 1725 1726 // If we can emit an efficient shift operation, do so now. Check to see if 1727 // the RHS is a constant. 1728 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1729 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1730 1731 // If we can determine that the high bit of the shift is zero or one, even if 1732 // the low bits are variable, emit this shift in an optimized form. 1733 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1734 return; 1735 1736 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1737 unsigned PartsOpc; 1738 if (N->getOpcode() == ISD::SHL) { 1739 PartsOpc = ISD::SHL_PARTS; 1740 } else if (N->getOpcode() == ISD::SRL) { 1741 PartsOpc = ISD::SRL_PARTS; 1742 } else { 1743 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1744 PartsOpc = ISD::SRA_PARTS; 1745 } 1746 1747 // Next check to see if the target supports this SHL_PARTS operation or if it 1748 // will custom expand it. 1749 MVT NVT = TLI.getTypeToTransformTo(VT); 1750 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1751 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1752 Action == TargetLowering::Custom) { 1753 // Expand the subcomponents. 1754 SDValue LHSL, LHSH; 1755 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1756 1757 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1758 MVT VT = LHSL.getValueType(); 1759 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3); 1760 Hi = Lo.getValue(1); 1761 return; 1762 } 1763 1764 // Otherwise, emit a libcall. 1765 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1766 bool isSigned; 1767 if (N->getOpcode() == ISD::SHL) { 1768 isSigned = false; /*sign irrelevant*/ 1769 if (VT == MVT::i16) 1770 LC = RTLIB::SHL_I16; 1771 else if (VT == MVT::i32) 1772 LC = RTLIB::SHL_I32; 1773 else if (VT == MVT::i64) 1774 LC = RTLIB::SHL_I64; 1775 else if (VT == MVT::i128) 1776 LC = RTLIB::SHL_I128; 1777 } else if (N->getOpcode() == ISD::SRL) { 1778 isSigned = false; 1779 if (VT == MVT::i16) 1780 LC = RTLIB::SRL_I16; 1781 else if (VT == MVT::i32) 1782 LC = RTLIB::SRL_I32; 1783 else if (VT == MVT::i64) 1784 LC = RTLIB::SRL_I64; 1785 else if (VT == MVT::i128) 1786 LC = RTLIB::SRL_I128; 1787 } else { 1788 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1789 isSigned = true; 1790 if (VT == MVT::i16) 1791 LC = RTLIB::SRA_I16; 1792 else if (VT == MVT::i32) 1793 LC = RTLIB::SRA_I32; 1794 else if (VT == MVT::i64) 1795 LC = RTLIB::SRA_I64; 1796 else if (VT == MVT::i128) 1797 LC = RTLIB::SRA_I128; 1798 } 1799 1800 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) { 1801 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1802 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi); 1803 return; 1804 } 1805 1806 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi)) 1807 assert(0 && "Unsupported shift!"); 1808} 1809 1810void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 1811 SDValue &Lo, SDValue &Hi) { 1812 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1813 DebugLoc dl = N->getDebugLoc(); 1814 SDValue Op = N->getOperand(0); 1815 if (Op.getValueType().bitsLE(NVT)) { 1816 // The low part is sign extension of the input (degenerates to a copy). 1817 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); 1818 // The high part is obtained by SRA'ing all but one of the bits of low part. 1819 unsigned LoSize = NVT.getSizeInBits(); 1820 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1821 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1822 } else { 1823 // For example, extension of an i48 to an i64. The operand type necessarily 1824 // promotes to the result type, so will end up being expanded too. 1825 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1826 "Only know how to promote this result!"); 1827 SDValue Res = GetPromotedInteger(Op); 1828 assert(Res.getValueType() == N->getValueType(0) && 1829 "Operand over promoted?"); 1830 // Split the promoted operand. This will simplify when it is expanded. 1831 SplitInteger(Res, Lo, Hi); 1832 unsigned ExcessBits = 1833 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1834 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 1835 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1836 } 1837} 1838 1839void DAGTypeLegalizer:: 1840ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 1841 DebugLoc dl = N->getDebugLoc(); 1842 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1843 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1844 1845 if (EVT.bitsLE(Lo.getValueType())) { 1846 // sext_inreg the low part if needed. 1847 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, 1848 N->getOperand(1)); 1849 1850 // The high part gets the sign extension from the lo-part. This handles 1851 // things like sextinreg V:i64 from i8. 1852 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo, 1853 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 1854 TLI.getPointerTy())); 1855 } else { 1856 // For example, extension of an i48 to an i64. Leave the low part alone, 1857 // sext_inreg the high part. 1858 unsigned ExcessBits = 1859 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 1860 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 1861 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1862 } 1863} 1864 1865void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1866 SDValue &Lo, SDValue &Hi) { 1867 MVT VT = N->getValueType(0); 1868 DebugLoc dl = N->getDebugLoc(); 1869 1870 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1871 if (VT == MVT::i16) 1872 LC = RTLIB::SREM_I16; 1873 else if (VT == MVT::i32) 1874 LC = RTLIB::SREM_I32; 1875 else if (VT == MVT::i64) 1876 LC = RTLIB::SREM_I64; 1877 else if (VT == MVT::i128) 1878 LC = RTLIB::SREM_I128; 1879 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1880 1881 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1882 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1883} 1884 1885void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 1886 SDValue &Lo, SDValue &Hi) { 1887 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1888 DebugLoc dl = N->getDebugLoc(); 1889 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); 1890 Hi = DAG.getNode(ISD::SRL, dl, 1891 N->getOperand(0).getValueType(), N->getOperand(0), 1892 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy())); 1893 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); 1894} 1895 1896void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1897 SDValue &Lo, SDValue &Hi) { 1898 MVT VT = N->getValueType(0); 1899 DebugLoc dl = N->getDebugLoc(); 1900 1901 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1902 if (VT == MVT::i16) 1903 LC = RTLIB::UDIV_I16; 1904 else if (VT == MVT::i32) 1905 LC = RTLIB::UDIV_I32; 1906 else if (VT == MVT::i64) 1907 LC = RTLIB::UDIV_I64; 1908 else if (VT == MVT::i128) 1909 LC = RTLIB::UDIV_I128; 1910 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 1911 1912 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1913 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 1914} 1915 1916void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 1917 SDValue &Lo, SDValue &Hi) { 1918 MVT VT = N->getValueType(0); 1919 DebugLoc dl = N->getDebugLoc(); 1920 1921 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1922 if (VT == MVT::i16) 1923 LC = RTLIB::UREM_I16; 1924 else if (VT == MVT::i32) 1925 LC = RTLIB::UREM_I32; 1926 else if (VT == MVT::i64) 1927 LC = RTLIB::UREM_I64; 1928 else if (VT == MVT::i128) 1929 LC = RTLIB::UREM_I128; 1930 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 1931 1932 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1933 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 1934} 1935 1936void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 1937 SDValue &Lo, SDValue &Hi) { 1938 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1939 DebugLoc dl = N->getDebugLoc(); 1940 SDValue Op = N->getOperand(0); 1941 if (Op.getValueType().bitsLE(NVT)) { 1942 // The low part is zero extension of the input (degenerates to a copy). 1943 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); 1944 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 1945 } else { 1946 // For example, extension of an i48 to an i64. The operand type necessarily 1947 // promotes to the result type, so will end up being expanded too. 1948 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1949 "Only know how to promote this result!"); 1950 SDValue Res = GetPromotedInteger(Op); 1951 assert(Res.getValueType() == N->getValueType(0) && 1952 "Operand over promoted?"); 1953 // Split the promoted operand. This will simplify when it is expanded. 1954 SplitInteger(Res, Lo, Hi); 1955 unsigned ExcessBits = 1956 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1957 Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits)); 1958 } 1959} 1960 1961 1962//===----------------------------------------------------------------------===// 1963// Integer Operand Expansion 1964//===----------------------------------------------------------------------===// 1965 1966/// ExpandIntegerOperand - This method is called when the specified operand of 1967/// the specified node is found to need expansion. At this point, all of the 1968/// result types of the node are known to be legal, but other operands of the 1969/// node may need promotion or expansion as well as the specified one. 1970bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 1971 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n"); 1972 SDValue Res = SDValue(); 1973 1974 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 1975 return false; 1976 1977 switch (N->getOpcode()) { 1978 default: 1979 #ifndef NDEBUG 1980 cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; 1981 N->dump(&DAG); cerr << "\n"; 1982 #endif 1983 assert(0 && "Do not know how to expand this operator's operand!"); 1984 abort(); 1985 1986 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 1987 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 1988 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 1989 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 1990 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 1991 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; 1992 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 1993 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 1994 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 1995 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break; 1996 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 1997 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 1998 1999 case ISD::SHL: 2000 case ISD::SRA: 2001 case ISD::SRL: 2002 case ISD::ROTL: 2003 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break; 2004 } 2005 2006 // If the result is null, the sub-method took care of registering results etc. 2007 if (!Res.getNode()) return false; 2008 2009 // If the result is N, the sub-method updated N in place. Tell the legalizer 2010 // core about this. 2011 if (Res.getNode() == N) 2012 return true; 2013 2014 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2015 "Invalid operand expansion"); 2016 2017 ReplaceValueWith(SDValue(N, 0), Res); 2018 return false; 2019} 2020 2021/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 2022/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 2023void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 2024 SDValue &NewRHS, 2025 ISD::CondCode &CCCode, 2026 DebugLoc dl) { 2027 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 2028 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 2029 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 2030 2031 MVT VT = NewLHS.getValueType(); 2032 2033 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 2034 if (RHSLo == RHSHi) { 2035 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 2036 if (RHSCST->isAllOnesValue()) { 2037 // Equality comparison to -1. 2038 NewLHS = DAG.getNode(ISD::AND, dl, 2039 LHSLo.getValueType(), LHSLo, LHSHi); 2040 NewRHS = RHSLo; 2041 return; 2042 } 2043 } 2044 } 2045 2046 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); 2047 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); 2048 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS); 2049 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2050 return; 2051 } 2052 2053 // If this is a comparison of the sign bit, just look at the top part. 2054 // X > -1, x < 0 2055 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 2056 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 2057 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 2058 NewLHS = LHSHi; 2059 NewRHS = RHSHi; 2060 return; 2061 } 2062 2063 // FIXME: This generated code sucks. 2064 ISD::CondCode LowCC; 2065 switch (CCCode) { 2066 default: assert(0 && "Unknown integer setcc!"); 2067 case ISD::SETLT: 2068 case ISD::SETULT: LowCC = ISD::SETULT; break; 2069 case ISD::SETGT: 2070 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2071 case ISD::SETLE: 2072 case ISD::SETULE: LowCC = ISD::SETULE; break; 2073 case ISD::SETGE: 2074 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2075 } 2076 2077 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2078 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2079 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2080 2081 // NOTE: on targets without efficient SELECT of bools, we can always use 2082 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2083 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 2084 SDValue Tmp1, Tmp2; 2085 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), 2086 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl); 2087 if (!Tmp1.getNode()) 2088 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 2089 LHSLo, RHSLo, LowCC); 2090 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2091 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl); 2092 if (!Tmp2.getNode()) 2093 Tmp2 = DAG.getNode(ISD::SETCC, dl, 2094 TLI.getSetCCResultType(LHSHi.getValueType()), 2095 LHSHi, RHSHi, DAG.getCondCode(CCCode)); 2096 2097 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2098 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2099 if ((Tmp1C && Tmp1C->isNullValue()) || 2100 (Tmp2C && Tmp2C->isNullValue() && 2101 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2102 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2103 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2104 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2105 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2106 // low part is known false, returns high part. 2107 // For LE / GE, if high part is known false, ignore the low part. 2108 // For LT / GT, if high part is known true, ignore the low part. 2109 NewLHS = Tmp2; 2110 NewRHS = SDValue(); 2111 return; 2112 } 2113 2114 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2115 LHSHi, RHSHi, ISD::SETEQ, false, 2116 DagCombineInfo, dl); 2117 if (!NewLHS.getNode()) 2118 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 2119 LHSHi, RHSHi, ISD::SETEQ); 2120 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), 2121 NewLHS, Tmp1, Tmp2); 2122 NewRHS = SDValue(); 2123} 2124 2125SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2126 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2127 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2128 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2129 2130 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2131 // against zero to select between true and false values. 2132 if (NewRHS.getNode() == 0) { 2133 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2134 CCCode = ISD::SETNE; 2135 } 2136 2137 // Update N to have the operands specified. 2138 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 2139 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2140 N->getOperand(4)); 2141} 2142 2143SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2144 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2145 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2146 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2147 2148 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2149 // against zero to select between true and false values. 2150 if (NewRHS.getNode() == 0) { 2151 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2152 CCCode = ISD::SETNE; 2153 } 2154 2155 // Update N to have the operands specified. 2156 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2157 N->getOperand(2), N->getOperand(3), 2158 DAG.getCondCode(CCCode)); 2159} 2160 2161SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2162 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2163 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2164 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2165 2166 // If ExpandSetCCOperands returned a scalar, use it. 2167 if (NewRHS.getNode() == 0) { 2168 assert(NewLHS.getValueType() == N->getValueType(0) && 2169 "Unexpected setcc expansion!"); 2170 return NewLHS; 2171 } 2172 2173 // Otherwise, update N to have the operands specified. 2174 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2175 DAG.getCondCode(CCCode)); 2176} 2177 2178SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) { 2179 // The value being shifted is legal, but the shift amount is too big. 2180 // It follows that either the result of the shift is undefined, or the 2181 // upper half of the shift amount is zero. Just use the lower half. 2182 SDValue Lo, Hi; 2183 GetExpandedInteger(N->getOperand(1), Lo, Hi); 2184 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo); 2185} 2186 2187SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2188 SDValue Op = N->getOperand(0); 2189 MVT DstVT = N->getValueType(0); 2190 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2191 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2192 "Don't know how to expand this SINT_TO_FP!"); 2193 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc()); 2194} 2195 2196SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2197 if (ISD::isNormalStore(N)) 2198 return ExpandOp_NormalStore(N, OpNo); 2199 2200 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2201 assert(OpNo == 1 && "Can only expand the stored value so far"); 2202 2203 MVT VT = N->getOperand(1).getValueType(); 2204 MVT NVT = TLI.getTypeToTransformTo(VT); 2205 SDValue Ch = N->getChain(); 2206 SDValue Ptr = N->getBasePtr(); 2207 int SVOffset = N->getSrcValueOffset(); 2208 unsigned Alignment = N->getAlignment(); 2209 bool isVolatile = N->isVolatile(); 2210 DebugLoc dl = N->getDebugLoc(); 2211 SDValue Lo, Hi; 2212 2213 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2214 2215 if (N->getMemoryVT().bitsLE(NVT)) { 2216 GetExpandedInteger(N->getValue(), Lo, Hi); 2217 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, 2218 N->getMemoryVT(), isVolatile, Alignment); 2219 } else if (TLI.isLittleEndian()) { 2220 // Little-endian - low bits are at low addresses. 2221 GetExpandedInteger(N->getValue(), Lo, Hi); 2222 2223 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, 2224 isVolatile, Alignment); 2225 2226 unsigned ExcessBits = 2227 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2228 MVT NEVT = MVT::getIntegerVT(ExcessBits); 2229 2230 // Increment the pointer to the other half. 2231 unsigned IncrementSize = NVT.getSizeInBits()/8; 2232 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2233 DAG.getIntPtrConstant(IncrementSize)); 2234 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), 2235 SVOffset+IncrementSize, NEVT, 2236 isVolatile, MinAlign(Alignment, IncrementSize)); 2237 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2238 } else { 2239 // Big-endian - high bits are at low addresses. Favor aligned stores at 2240 // the cost of some bit-fiddling. 2241 GetExpandedInteger(N->getValue(), Lo, Hi); 2242 2243 MVT EVT = N->getMemoryVT(); 2244 unsigned EBytes = EVT.getStoreSizeInBits()/8; 2245 unsigned IncrementSize = NVT.getSizeInBits()/8; 2246 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2247 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); 2248 2249 if (ExcessBits < NVT.getSizeInBits()) { 2250 // Transfer high bits from the top of Lo to the bottom of Hi. 2251 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, 2252 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2253 TLI.getPointerTy())); 2254 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, 2255 DAG.getNode(ISD::SRL, dl, NVT, Lo, 2256 DAG.getConstant(ExcessBits, 2257 TLI.getPointerTy()))); 2258 } 2259 2260 // Store both the high bits and maybe some of the low bits. 2261 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), 2262 SVOffset, HiVT, isVolatile, Alignment); 2263 2264 // Increment the pointer to the other half. 2265 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2266 DAG.getIntPtrConstant(IncrementSize)); 2267 // Store the lowest ExcessBits bits in the second half. 2268 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), 2269 SVOffset+IncrementSize, 2270 MVT::getIntegerVT(ExcessBits), 2271 isVolatile, MinAlign(Alignment, IncrementSize)); 2272 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2273 } 2274} 2275 2276SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2277 SDValue InL, InH; 2278 GetExpandedInteger(N->getOperand(0), InL, InH); 2279 // Just truncate the low part of the source. 2280 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL); 2281} 2282 2283SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2284 SDValue Op = N->getOperand(0); 2285 MVT SrcVT = Op.getValueType(); 2286 MVT DstVT = N->getValueType(0); 2287 DebugLoc dl = N->getDebugLoc(); 2288 2289 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2290 // Do a signed conversion then adjust the result. 2291 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); 2292 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2293 2294 // The result of the signed conversion needs adjusting if the 'sign bit' of 2295 // the incoming integer was set. To handle this, we dynamically test to see 2296 // if it is set, and, if so, add a fudge factor. 2297 2298 const uint64_t F32TwoE32 = 0x4F800000ULL; 2299 const uint64_t F32TwoE64 = 0x5F800000ULL; 2300 const uint64_t F32TwoE128 = 0x7F800000ULL; 2301 2302 APInt FF(32, 0); 2303 if (SrcVT == MVT::i32) 2304 FF = APInt(32, F32TwoE32); 2305 else if (SrcVT == MVT::i64) 2306 FF = APInt(32, F32TwoE64); 2307 else if (SrcVT == MVT::i128) 2308 FF = APInt(32, F32TwoE128); 2309 else 2310 assert(false && "Unsupported UINT_TO_FP!"); 2311 2312 // Check whether the sign bit is set. 2313 SDValue Lo, Hi; 2314 GetExpandedInteger(Op, Lo, Hi); 2315 SDValue SignSet = DAG.getSetCC(dl, 2316 TLI.getSetCCResultType(Hi.getValueType()), 2317 Hi, DAG.getConstant(0, Hi.getValueType()), 2318 ISD::SETLT); 2319 2320 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2321 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)), 2322 TLI.getPointerTy()); 2323 2324 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2325 SDValue Zero = DAG.getIntPtrConstant(0); 2326 SDValue Four = DAG.getIntPtrConstant(4); 2327 if (TLI.isBigEndian()) std::swap(Zero, Four); 2328 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 2329 Zero, Four); 2330 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2331 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset); 2332 Alignment = std::min(Alignment, 4u); 2333 2334 // Load the value out, extending it from f32 to the destination float type. 2335 // FIXME: Avoid the extend by constructing the right constant pool? 2336 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), 2337 FudgePtr, NULL, 0, MVT::f32, 2338 false, Alignment); 2339 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); 2340 } 2341 2342 // Otherwise, use a libcall. 2343 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2344 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2345 "Don't know how to expand this UINT_TO_FP!"); 2346 return MakeLibCall(LC, DstVT, &Op, 1, true, dl); 2347} 2348