LegalizeIntegerTypes.cpp revision f1b4eafbfec976f939ec0ea3e8acf91cef5363e3
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22#include "llvm/CodeGen/PseudoSourceValue.h" 23#include "llvm/Support/ErrorHandling.h" 24#include "llvm/Support/raw_ostream.h" 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28// Integer Result Promotion 29//===----------------------------------------------------------------------===// 30 31/// PromoteIntegerResult - This method is called when a result of a node is 32/// found to be in need of promotion to a larger type. At this point, the node 33/// may also have invalid operands or may have other results that need 34/// expansion, we just know that (at least) one result needs promotion. 35void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n"); 37 SDValue Res = SDValue(); 38 39 // See if the target wants to custom expand this node. 40 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 41 return; 42 43 switch (N->getOpcode()) { 44 default: 45#ifndef NDEBUG 46 dbgs() << "PromoteIntegerResult #" << ResNo << ": "; 47 N->dump(&DAG); dbgs() << "\n"; 48#endif 49 llvm_unreachable("Do not know how to promote this operator!"); 50 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 51 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 52 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; 53 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 54 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 55 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 56 case ISD::CONVERT_RNDSAT: 57 Res = PromoteIntRes_CONVERT_RNDSAT(N); break; 58 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; 59 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break; 60 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; 61 case ISD::EXTRACT_VECTOR_ELT: 62 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 63 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 64 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break; 65 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; 66 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 67 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; 68 case ISD::SIGN_EXTEND_INREG: 69 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 70 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 71 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; 72 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; 73 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break; 74 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break; 75 76 case ISD::SIGN_EXTEND: 77 case ISD::ZERO_EXTEND: 78 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; 79 80 case ISD::FP_TO_SINT: 81 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; 82 83 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break; 84 85 case ISD::AND: 86 case ISD::OR: 87 case ISD::XOR: 88 case ISD::ADD: 89 case ISD::SUB: 90 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break; 91 92 case ISD::SDIV: 93 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; 94 95 case ISD::UDIV: 96 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break; 97 98 case ISD::SADDO: 99 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; 100 case ISD::UADDO: 101 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; 102 case ISD::SMULO: 103 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; 104 105 case ISD::ATOMIC_LOAD_ADD: 106 case ISD::ATOMIC_LOAD_SUB: 107 case ISD::ATOMIC_LOAD_AND: 108 case ISD::ATOMIC_LOAD_OR: 109 case ISD::ATOMIC_LOAD_XOR: 110 case ISD::ATOMIC_LOAD_NAND: 111 case ISD::ATOMIC_LOAD_MIN: 112 case ISD::ATOMIC_LOAD_MAX: 113 case ISD::ATOMIC_LOAD_UMIN: 114 case ISD::ATOMIC_LOAD_UMAX: 115 case ISD::ATOMIC_SWAP: 116 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 117 118 case ISD::ATOMIC_CMP_SWAP: 119 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 120 } 121 122 // If the result is null then the sub-method took care of registering it. 123 if (Res.getNode()) 124 SetPromotedInteger(SDValue(N, ResNo), Res); 125} 126 127SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 128 // Sign-extend the new bits, and continue the assertion. 129 SDValue Op = SExtPromotedInteger(N->getOperand(0)); 130 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(), 131 Op.getValueType(), Op, N->getOperand(1)); 132} 133 134SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 135 // Zero the new bits, and continue the assertion. 136 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 137 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), 138 Op.getValueType(), Op, N->getOperand(1)); 139} 140 141SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 142 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 143 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 144 N->getMemoryVT(), 145 N->getChain(), N->getBasePtr(), 146 Op2, N->getMemOperand()); 147 // Legalized the chain result - switch anything that used the old chain to 148 // use the new one. 149 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 150 return Res; 151} 152 153SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 154 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 155 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 156 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 157 N->getMemoryVT(), N->getChain(), N->getBasePtr(), 158 Op2, Op3, N->getMemOperand()); 159 // Legalized the chain result - switch anything that used the old chain to 160 // use the new one. 161 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 162 return Res; 163} 164 165SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) { 166 SDValue InOp = N->getOperand(0); 167 EVT InVT = InOp.getValueType(); 168 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); 169 EVT OutVT = N->getValueType(0); 170 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 171 DebugLoc dl = N->getDebugLoc(); 172 173 switch (getTypeAction(InVT)) { 174 default: 175 assert(false && "Unknown type action!"); 176 break; 177 case Legal: 178 break; 179 case PromoteInteger: 180 if (NOutVT.bitsEq(NInVT)) 181 // The input promotes to the same size. Convert the promoted value. 182 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); 183 break; 184 case SoftenFloat: 185 // Promote the integer operand by hand. 186 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); 187 case ExpandInteger: 188 case ExpandFloat: 189 break; 190 case ScalarizeVector: 191 // Convert the element to an integer and promote it by hand. 192 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 193 BitConvertToInteger(GetScalarizedVector(InOp))); 194 case SplitVector: { 195 // For example, i32 = BITCAST v2i16 on alpha. Convert the split 196 // pieces of the input into integers and reassemble in the final type. 197 SDValue Lo, Hi; 198 GetSplitVector(N->getOperand(0), Lo, Hi); 199 Lo = BitConvertToInteger(Lo); 200 Hi = BitConvertToInteger(Hi); 201 202 if (TLI.isBigEndian()) 203 std::swap(Lo, Hi); 204 205 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, 206 EVT::getIntegerVT(*DAG.getContext(), 207 NOutVT.getSizeInBits()), 208 JoinIntegers(Lo, Hi)); 209 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); 210 } 211 case WidenVector: 212 if (OutVT.bitsEq(NInVT)) 213 // The input is widened to the same size. Convert to the widened value. 214 return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp)); 215 } 216 217 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 218 CreateStackStoreLoad(InOp, OutVT)); 219} 220 221SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 222 SDValue Op = GetPromotedInteger(N->getOperand(0)); 223 EVT OVT = N->getValueType(0); 224 EVT NVT = Op.getValueType(); 225 DebugLoc dl = N->getDebugLoc(); 226 227 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 228 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 229 DAG.getConstant(DiffBits, TLI.getPointerTy())); 230} 231 232SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 233 // The pair element type may be legal, or may not promote to the same type as 234 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 235 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), 236 TLI.getTypeToTransformTo(*DAG.getContext(), 237 N->getValueType(0)), JoinIntegers(N->getOperand(0), 238 N->getOperand(1))); 239} 240 241SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 242 EVT VT = N->getValueType(0); 243 // FIXME there is no actual debug info here 244 DebugLoc dl = N->getDebugLoc(); 245 // Zero extend things like i1, sign extend everything else. It shouldn't 246 // matter in theory which one we pick, but this tends to give better code? 247 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 248 SDValue Result = DAG.getNode(Opc, dl, 249 TLI.getTypeToTransformTo(*DAG.getContext(), VT), 250 SDValue(N, 0)); 251 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 252 return Result; 253} 254 255SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 256 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 257 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 258 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 259 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 260 "can only promote integers"); 261 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 262 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0), 263 N->getOperand(1), N->getOperand(2), 264 N->getOperand(3), N->getOperand(4), CvtCode); 265} 266 267SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 268 // Zero extend to the promoted type and do the count there. 269 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 270 DebugLoc dl = N->getDebugLoc(); 271 EVT OVT = N->getValueType(0); 272 EVT NVT = Op.getValueType(); 273 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op); 274 // Subtract off the extra leading bits in the bigger type. 275 return DAG.getNode(ISD::SUB, dl, NVT, Op, 276 DAG.getConstant(NVT.getSizeInBits() - 277 OVT.getSizeInBits(), NVT)); 278} 279 280SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 281 // Zero extend to the promoted type and do the count there. 282 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 283 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op); 284} 285 286SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 287 SDValue Op = GetPromotedInteger(N->getOperand(0)); 288 EVT OVT = N->getValueType(0); 289 EVT NVT = Op.getValueType(); 290 DebugLoc dl = N->getDebugLoc(); 291 // The count is the same in the promoted type except if the original 292 // value was zero. This can be handled by setting the bit just off 293 // the top of the original type. 294 APInt TopBit(NVT.getSizeInBits(), 0); 295 TopBit.setBit(OVT.getSizeInBits()); 296 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT)); 297 return DAG.getNode(ISD::CTTZ, dl, NVT, Op); 298} 299 300SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 301 DebugLoc dl = N->getDebugLoc(); 302 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 303 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0), 304 N->getOperand(1)); 305} 306 307SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 308 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 309 unsigned NewOpc = N->getOpcode(); 310 DebugLoc dl = N->getDebugLoc(); 311 312 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is 313 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT 314 // and SINT conversions are Custom, there is no way to tell which is 315 // preferable. We choose SINT because that's the right thing on PPC.) 316 if (N->getOpcode() == ISD::FP_TO_UINT && 317 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 318 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) 319 NewOpc = ISD::FP_TO_SINT; 320 321 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); 322 323 // Assert that the converted value fits in the original type. If it doesn't 324 // (eg: because the value being converted is too big), then the result of the 325 // original operation was undefined anyway, so the assert is still correct. 326 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 327 ISD::AssertZext : ISD::AssertSext, dl, 328 NVT, Res, DAG.getValueType(N->getValueType(0))); 329} 330 331SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) { 332 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 333 DebugLoc dl = N->getDebugLoc(); 334 335 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 336 337 return DAG.getNode(ISD::AssertZext, dl, 338 NVT, Res, DAG.getValueType(N->getValueType(0))); 339} 340 341SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 342 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 343 DebugLoc dl = N->getDebugLoc(); 344 345 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 346 SDValue Res = GetPromotedInteger(N->getOperand(0)); 347 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 348 349 // If the result and operand types are the same after promotion, simplify 350 // to an in-register extension. 351 if (NVT == Res.getValueType()) { 352 // The high bits are not guaranteed to be anything. Insert an extend. 353 if (N->getOpcode() == ISD::SIGN_EXTEND) 354 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 355 DAG.getValueType(N->getOperand(0).getValueType())); 356 if (N->getOpcode() == ISD::ZERO_EXTEND) 357 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType()); 358 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 359 return Res; 360 } 361 } 362 363 // Otherwise, just extend the original operand all the way to the larger type. 364 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 365} 366 367SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 368 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 369 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 370 ISD::LoadExtType ExtType = 371 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 372 DebugLoc dl = N->getDebugLoc(); 373 SDValue Res = DAG.getExtLoad(ExtType, NVT, dl, N->getChain(), N->getBasePtr(), 374 N->getPointerInfo(), 375 N->getMemoryVT(), N->isVolatile(), 376 N->isNonTemporal(), N->getAlignment()); 377 378 // Legalized the chain result - switch anything that used the old chain to 379 // use the new one. 380 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 381 return Res; 382} 383 384/// Promote the overflow flag of an overflowing arithmetic node. 385SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { 386 // Simply change the return type of the boolean result. 387 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1)); 388 EVT ValueVTs[] = { N->getValueType(0), NVT }; 389 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) }; 390 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), 391 DAG.getVTList(ValueVTs, 2), Ops, 2); 392 393 // Modified the sum result - switch anything that used the old sum to use 394 // the new one. 395 ReplaceValueWith(SDValue(N, 0), Res); 396 397 return SDValue(Res.getNode(), 1); 398} 399 400SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { 401 if (ResNo == 1) 402 return PromoteIntRes_Overflow(N); 403 404 // The operation overflowed iff the result in the larger type is not the 405 // sign extension of its truncation to the original type. 406 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 407 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 408 EVT OVT = N->getOperand(0).getValueType(); 409 EVT NVT = LHS.getValueType(); 410 DebugLoc dl = N->getDebugLoc(); 411 412 // Do the arithmetic in the larger type. 413 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 414 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 415 416 // Calculate the overflow flag: sign extend the arithmetic result from 417 // the original type. 418 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 419 DAG.getValueType(OVT)); 420 // Overflowed if and only if this is not equal to Res. 421 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 422 423 // Use the calculated overflow everywhere. 424 ReplaceValueWith(SDValue(N, 1), Ofl); 425 426 return Res; 427} 428 429SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 430 // Sign extend the input. 431 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 432 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 433 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 434 LHS.getValueType(), LHS, RHS); 435} 436 437SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 438 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 439 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 440 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 441 LHS.getValueType(), N->getOperand(0),LHS,RHS); 442} 443 444SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 445 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 446 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 447 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 448 LHS.getValueType(), N->getOperand(0), 449 N->getOperand(1), LHS, RHS, N->getOperand(4)); 450} 451 452SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 453 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); 454 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 455 DebugLoc dl = N->getDebugLoc(); 456 457 // Get the SETCC result using the canonical SETCC type. 458 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0), 459 N->getOperand(1), N->getOperand(2)); 460 461 // Convert to the expected type. 462 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 463 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 464 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 465} 466 467SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 468 return DAG.getNode(ISD::SHL, N->getDebugLoc(), 469 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)), 470 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 471} 472 473SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 474 SDValue Op = GetPromotedInteger(N->getOperand(0)); 475 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), 476 Op.getValueType(), Op, N->getOperand(1)); 477} 478 479SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 480 // The input may have strange things in the top bits of the registers, but 481 // these operations don't care. They may have weird bits going out, but 482 // that too is okay if they are integer operations. 483 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 484 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 485 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 486 LHS.getValueType(), LHS, RHS); 487} 488 489SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 490 // The input value must be properly sign extended. 491 SDValue Res = SExtPromotedInteger(N->getOperand(0)); 492 return DAG.getNode(ISD::SRA, N->getDebugLoc(), 493 Res.getValueType(), Res, N->getOperand(1)); 494} 495 496SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 497 // The input value must be properly zero extended. 498 EVT VT = N->getValueType(0); 499 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 500 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 501 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1)); 502} 503 504SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 505 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 506 SDValue Res; 507 508 switch (getTypeAction(N->getOperand(0).getValueType())) { 509 default: llvm_unreachable("Unknown type action!"); 510 case Legal: 511 case ExpandInteger: 512 Res = N->getOperand(0); 513 break; 514 case PromoteInteger: 515 Res = GetPromotedInteger(N->getOperand(0)); 516 break; 517 } 518 519 // Truncate to NVT instead of VT 520 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res); 521} 522 523SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) { 524 if (ResNo == 1) 525 return PromoteIntRes_Overflow(N); 526 527 // The operation overflowed iff the result in the larger type is not the 528 // zero extension of its truncation to the original type. 529 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 530 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 531 EVT OVT = N->getOperand(0).getValueType(); 532 EVT NVT = LHS.getValueType(); 533 DebugLoc dl = N->getDebugLoc(); 534 535 // Do the arithmetic in the larger type. 536 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 537 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 538 539 // Calculate the overflow flag: zero extend the arithmetic result from 540 // the original type. 541 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); 542 // Overflowed if and only if this is not equal to Res. 543 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 544 545 // Use the calculated overflow everywhere. 546 ReplaceValueWith(SDValue(N, 1), Ofl); 547 548 return Res; 549} 550 551 552SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) { 553 // Promote the overflow bit trivially. 554 if (ResNo == 1) 555 return PromoteIntRes_Overflow(N); 556 557 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1); 558 DebugLoc DL = N->getDebugLoc(); 559 unsigned SmallSize = LHS.getValueType().getSizeInBits(); 560 561 // To determine if the result overflowed in a larger type, we extend the input 562 // to the larger type, do the multiply, then check the high bits of the result 563 // to see if the overflow happened. 564 if (N->getOpcode() == ISD::SMULO) { 565 LHS = SExtPromotedInteger(LHS); 566 RHS = SExtPromotedInteger(RHS); 567 } else { 568 LHS = ZExtPromotedInteger(LHS); 569 RHS = ZExtPromotedInteger(RHS); 570 } 571 572 SDValue Mul = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS); 573 574 575 // For an unsigned overflow, we check to see if the high part is != 0; 576 SDValue Overflow; 577 if (N->getOpcode() == ISD::UMULO) { 578 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, 579 DAG.getIntPtrConstant(SmallSize)); 580 // Overflowed if and only if this is not equal to Res. 581 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi, 582 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE); 583 } else { 584 // Signed multiply overflowed if the high part is not 0 and not -1. 585 SDValue Hi = DAG.getNode(ISD::SRA, DL, Mul.getValueType(), Mul, 586 DAG.getIntPtrConstant(SmallSize)); 587 Hi = DAG.getNode(ISD::ADD, DL, Hi.getValueType(), Hi, 588 DAG.getConstant(1, Hi.getValueType())); 589 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi, 590 DAG.getConstant(1, Hi.getValueType()), ISD::SETUGT); 591 } 592 593 // Use the calculated overflow everywhere. 594 ReplaceValueWith(SDValue(N, 1), Overflow); 595 return Mul; 596} 597 598 599SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 600 // Zero extend the input. 601 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 602 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 603 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 604 LHS.getValueType(), LHS, RHS); 605} 606 607SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 608 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(), 609 N->getValueType(0))); 610} 611 612SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 613 SDValue Chain = N->getOperand(0); // Get the chain. 614 SDValue Ptr = N->getOperand(1); // Get the pointer. 615 EVT VT = N->getValueType(0); 616 DebugLoc dl = N->getDebugLoc(); 617 618 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); 619 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT); 620 // The argument is passed as NumRegs registers of type RegVT. 621 622 SmallVector<SDValue, 8> Parts(NumRegs); 623 for (unsigned i = 0; i < NumRegs; ++i) { 624 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), 625 N->getConstantOperandVal(3)); 626 Chain = Parts[i].getValue(1); 627 } 628 629 // Handle endianness of the load. 630 if (TLI.isBigEndian()) 631 std::reverse(Parts.begin(), Parts.end()); 632 633 // Assemble the parts in the promoted type. 634 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 635 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); 636 for (unsigned i = 1; i < NumRegs; ++i) { 637 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); 638 // Shift it to the right position and "or" it in. 639 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, 640 DAG.getConstant(i * RegVT.getSizeInBits(), 641 TLI.getPointerTy())); 642 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part); 643 } 644 645 // Modified the chain result - switch anything that used the old chain to 646 // use the new one. 647 ReplaceValueWith(SDValue(N, 1), Chain); 648 649 return Res; 650} 651 652//===----------------------------------------------------------------------===// 653// Integer Operand Promotion 654//===----------------------------------------------------------------------===// 655 656/// PromoteIntegerOperand - This method is called when the specified operand of 657/// the specified node is found to need promotion. At this point, all of the 658/// result types of the node are known to be legal, but other operands of the 659/// node may need promotion or expansion as well as the specified one. 660bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 661 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n"); 662 SDValue Res = SDValue(); 663 664 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 665 return false; 666 667 switch (N->getOpcode()) { 668 default: 669 #ifndef NDEBUG 670 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": "; 671 N->dump(&DAG); dbgs() << "\n"; 672 #endif 673 llvm_unreachable("Do not know how to promote this operator's operand!"); 674 675 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 676 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break; 677 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 678 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 679 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 680 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 681 case ISD::CONVERT_RNDSAT: 682 Res = PromoteIntOp_CONVERT_RNDSAT(N); break; 683 case ISD::INSERT_VECTOR_ELT: 684 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 685 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 686 case ISD::SCALAR_TO_VECTOR: 687 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break; 688 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 689 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 690 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 691 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 692 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; 693 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 694 OpNo); break; 695 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 696 case ISD::FP16_TO_FP32: 697 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; 698 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 699 700 case ISD::SHL: 701 case ISD::SRA: 702 case ISD::SRL: 703 case ISD::ROTL: 704 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break; 705 } 706 707 // If the result is null, the sub-method took care of registering results etc. 708 if (!Res.getNode()) return false; 709 710 // If the result is N, the sub-method updated N in place. Tell the legalizer 711 // core about this. 712 if (Res.getNode() == N) 713 return true; 714 715 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 716 "Invalid operand expansion"); 717 718 ReplaceValueWith(SDValue(N, 0), Res); 719 return false; 720} 721 722/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 723/// shared among BR_CC, SELECT_CC, and SETCC handlers. 724void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 725 ISD::CondCode CCCode) { 726 // We have to insert explicit sign or zero extends. Note that we could 727 // insert sign extends for ALL conditions, but zero extend is cheaper on 728 // many machines (an AND instead of two shifts), so prefer it. 729 switch (CCCode) { 730 default: llvm_unreachable("Unknown integer comparison!"); 731 case ISD::SETEQ: 732 case ISD::SETNE: 733 case ISD::SETUGE: 734 case ISD::SETUGT: 735 case ISD::SETULE: 736 case ISD::SETULT: 737 // ALL of these operations will work if we either sign or zero extend 738 // the operands (including the unsigned comparisons!). Zero extend is 739 // usually a simpler/cheaper operation, so prefer it. 740 NewLHS = ZExtPromotedInteger(NewLHS); 741 NewRHS = ZExtPromotedInteger(NewRHS); 742 break; 743 case ISD::SETGE: 744 case ISD::SETGT: 745 case ISD::SETLT: 746 case ISD::SETLE: 747 NewLHS = SExtPromotedInteger(NewLHS); 748 NewRHS = SExtPromotedInteger(NewRHS); 749 break; 750 } 751} 752 753SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 754 SDValue Op = GetPromotedInteger(N->getOperand(0)); 755 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); 756} 757 758SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) { 759 // This should only occur in unusual situations like bitcasting to an 760 // x86_fp80, so just turn it into a store+load 761 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0)); 762} 763 764SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 765 assert(OpNo == 2 && "Don't know how to promote this operand!"); 766 767 SDValue LHS = N->getOperand(2); 768 SDValue RHS = N->getOperand(3); 769 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 770 771 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 772 // legal types. 773 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 774 N->getOperand(1), LHS, RHS, N->getOperand(4)), 775 0); 776} 777 778SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 779 assert(OpNo == 1 && "only know how to promote condition"); 780 781 // Promote all the way up to the canonical SetCC type. 782 EVT SVT = TLI.getSetCCResultType(MVT::Other); 783 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT); 784 785 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 786 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond, 787 N->getOperand(2)), 0); 788} 789 790SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 791 // Since the result type is legal, the operands must promote to it. 792 EVT OVT = N->getOperand(0).getValueType(); 793 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); 794 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 795 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 796 DebugLoc dl = N->getDebugLoc(); 797 798 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, 799 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy())); 800 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); 801} 802 803SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 804 // The vector type is legal but the element type is not. This implies 805 // that the vector is a power-of-two in length and that the element 806 // type does not have a strange size (eg: it is not i1). 807 EVT VecVT = N->getValueType(0); 808 unsigned NumElts = VecVT.getVectorNumElements(); 809 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 810 811 // Promote the inserted value. The type does not need to match the 812 // vector element type. Check that any extra bits introduced will be 813 // truncated away. 814 assert(N->getOperand(0).getValueType().getSizeInBits() >= 815 N->getValueType(0).getVectorElementType().getSizeInBits() && 816 "Type of inserted value narrower than vector element type!"); 817 818 SmallVector<SDValue, 16> NewOps; 819 for (unsigned i = 0; i < NumElts; ++i) 820 NewOps.push_back(GetPromotedInteger(N->getOperand(i))); 821 822 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0); 823} 824 825SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { 826 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 827 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 828 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 829 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && 830 "can only promote integer arguments"); 831 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 832 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp, 833 N->getOperand(1), N->getOperand(2), 834 N->getOperand(3), N->getOperand(4), CvtCode); 835} 836 837SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 838 unsigned OpNo) { 839 if (OpNo == 1) { 840 // Promote the inserted value. This is valid because the type does not 841 // have to match the vector element type. 842 843 // Check that any extra bits introduced will be truncated away. 844 assert(N->getOperand(1).getValueType().getSizeInBits() >= 845 N->getValueType(0).getVectorElementType().getSizeInBits() && 846 "Type of inserted value narrower than vector element type!"); 847 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 848 GetPromotedInteger(N->getOperand(1)), 849 N->getOperand(2)), 850 0); 851 } 852 853 assert(OpNo == 2 && "Different operand and result vector types?"); 854 855 // Promote the index. 856 SDValue Idx = ZExtPromotedInteger(N->getOperand(2)); 857 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 858 N->getOperand(1), Idx), 0); 859} 860 861SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 862 SDValue NewOps[6]; 863 DebugLoc dl = N->getDebugLoc(); 864 NewOps[0] = N->getOperand(0); 865 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 866 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 867 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1); 868 } 869 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0); 870} 871 872SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) { 873 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote 874 // the operand in place. 875 return SDValue(DAG.UpdateNodeOperands(N, 876 GetPromotedInteger(N->getOperand(0))), 0); 877} 878 879SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 880 assert(OpNo == 0 && "Only know how to promote condition"); 881 882 // Promote all the way up to the canonical SetCC type. 883 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType()); 884 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT); 885 886 return SDValue(DAG.UpdateNodeOperands(N, Cond, 887 N->getOperand(1), N->getOperand(2)), 0); 888} 889 890SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 891 assert(OpNo == 0 && "Don't know how to promote this operand!"); 892 893 SDValue LHS = N->getOperand(0); 894 SDValue RHS = N->getOperand(1); 895 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 896 897 // The CC (#4) and the possible return values (#2 and #3) have legal types. 898 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2), 899 N->getOperand(3), N->getOperand(4)), 0); 900} 901 902SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 903 assert(OpNo == 0 && "Don't know how to promote this operand!"); 904 905 SDValue LHS = N->getOperand(0); 906 SDValue RHS = N->getOperand(1); 907 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 908 909 // The CC (#2) is always legal. 910 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0); 911} 912 913SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) { 914 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 915 ZExtPromotedInteger(N->getOperand(1))), 0); 916} 917 918SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 919 SDValue Op = GetPromotedInteger(N->getOperand(0)); 920 DebugLoc dl = N->getDebugLoc(); 921 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 922 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), 923 Op, DAG.getValueType(N->getOperand(0).getValueType())); 924} 925 926SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) { 927 return SDValue(DAG.UpdateNodeOperands(N, 928 SExtPromotedInteger(N->getOperand(0))), 0); 929} 930 931SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 932 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 933 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 934 unsigned Alignment = N->getAlignment(); 935 bool isVolatile = N->isVolatile(); 936 bool isNonTemporal = N->isNonTemporal(); 937 DebugLoc dl = N->getDebugLoc(); 938 939 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 940 941 // Truncate the value and store the result. 942 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(), 943 N->getMemoryVT(), 944 isVolatile, isNonTemporal, Alignment); 945} 946 947SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 948 SDValue Op = GetPromotedInteger(N->getOperand(0)); 949 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op); 950} 951 952SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { 953 return SDValue(DAG.UpdateNodeOperands(N, 954 ZExtPromotedInteger(N->getOperand(0))), 0); 955} 956 957SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 958 DebugLoc dl = N->getDebugLoc(); 959 SDValue Op = GetPromotedInteger(N->getOperand(0)); 960 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 961 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType()); 962} 963 964 965//===----------------------------------------------------------------------===// 966// Integer Result Expansion 967//===----------------------------------------------------------------------===// 968 969/// ExpandIntegerResult - This method is called when the specified result of the 970/// specified node is found to need expansion. At this point, the node may also 971/// have invalid operands or may have other results that need promotion, we just 972/// know that (at least) one result needs expansion. 973void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 974 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n"); 975 SDValue Lo, Hi; 976 Lo = Hi = SDValue(); 977 978 // See if the target wants to custom expand this node. 979 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 980 return; 981 982 switch (N->getOpcode()) { 983 default: 984#ifndef NDEBUG 985 dbgs() << "ExpandIntegerResult #" << ResNo << ": "; 986 N->dump(&DAG); dbgs() << "\n"; 987#endif 988 llvm_unreachable("Do not know how to expand the result of this operator!"); 989 990 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 991 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 992 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 993 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 994 995 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break; 996 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 997 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 998 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 999 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 1000 1001 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 1002 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 1003 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 1004 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 1005 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 1006 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 1007 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 1008 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 1009 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 1010 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 1011 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 1012 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 1013 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 1014 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 1015 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 1016 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 1017 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 1018 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 1019 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 1020 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 1021 1022 case ISD::AND: 1023 case ISD::OR: 1024 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 1025 1026 case ISD::ADD: 1027 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1028 1029 case ISD::ADDC: 1030 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 1031 1032 case ISD::ADDE: 1033 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 1034 1035 case ISD::SHL: 1036 case ISD::SRA: 1037 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1038 1039 case ISD::SADDO: 1040 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break; 1041 case ISD::UADDO: 1042 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break; 1043 } 1044 1045 // If Lo/Hi is null, the sub-method took care of registering results etc. 1046 if (Lo.getNode()) 1047 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1048} 1049 1050/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1051/// and the shift amount is a constant 'Amt'. Expand the operation. 1052void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1053 SDValue &Lo, SDValue &Hi) { 1054 DebugLoc dl = N->getDebugLoc(); 1055 // Expand the incoming operand to be shifted, so that we have its parts 1056 SDValue InL, InH; 1057 GetExpandedInteger(N->getOperand(0), InL, InH); 1058 1059 EVT NVT = InL.getValueType(); 1060 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1061 unsigned NVTBits = NVT.getSizeInBits(); 1062 EVT ShTy = N->getOperand(1).getValueType(); 1063 1064 if (N->getOpcode() == ISD::SHL) { 1065 if (Amt > VTBits) { 1066 Lo = Hi = DAG.getConstant(0, NVT); 1067 } else if (Amt > NVTBits) { 1068 Lo = DAG.getConstant(0, NVT); 1069 Hi = DAG.getNode(ISD::SHL, dl, 1070 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1071 } else if (Amt == NVTBits) { 1072 Lo = DAG.getConstant(0, NVT); 1073 Hi = InL; 1074 } else if (Amt == 1 && 1075 TLI.isOperationLegalOrCustom(ISD::ADDC, 1076 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) { 1077 // Emit this X << 1 as X+X. 1078 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue); 1079 SDValue LoOps[2] = { InL, InL }; 1080 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1081 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1082 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1083 } else { 1084 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy)); 1085 Hi = DAG.getNode(ISD::OR, dl, NVT, 1086 DAG.getNode(ISD::SHL, dl, NVT, InH, 1087 DAG.getConstant(Amt, ShTy)), 1088 DAG.getNode(ISD::SRL, dl, NVT, InL, 1089 DAG.getConstant(NVTBits-Amt, ShTy))); 1090 } 1091 return; 1092 } 1093 1094 if (N->getOpcode() == ISD::SRL) { 1095 if (Amt > VTBits) { 1096 Lo = DAG.getConstant(0, NVT); 1097 Hi = DAG.getConstant(0, NVT); 1098 } else if (Amt > NVTBits) { 1099 Lo = DAG.getNode(ISD::SRL, dl, 1100 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1101 Hi = DAG.getConstant(0, NVT); 1102 } else if (Amt == NVTBits) { 1103 Lo = InH; 1104 Hi = DAG.getConstant(0, NVT); 1105 } else { 1106 Lo = DAG.getNode(ISD::OR, dl, NVT, 1107 DAG.getNode(ISD::SRL, dl, NVT, InL, 1108 DAG.getConstant(Amt, ShTy)), 1109 DAG.getNode(ISD::SHL, dl, NVT, InH, 1110 DAG.getConstant(NVTBits-Amt, ShTy))); 1111 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); 1112 } 1113 return; 1114 } 1115 1116 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1117 if (Amt > VTBits) { 1118 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 1119 DAG.getConstant(NVTBits-1, ShTy)); 1120 } else if (Amt > NVTBits) { 1121 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 1122 DAG.getConstant(Amt-NVTBits, ShTy)); 1123 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 1124 DAG.getConstant(NVTBits-1, ShTy)); 1125 } else if (Amt == NVTBits) { 1126 Lo = InH; 1127 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 1128 DAG.getConstant(NVTBits-1, ShTy)); 1129 } else { 1130 Lo = DAG.getNode(ISD::OR, dl, NVT, 1131 DAG.getNode(ISD::SRL, dl, NVT, InL, 1132 DAG.getConstant(Amt, ShTy)), 1133 DAG.getNode(ISD::SHL, dl, NVT, InH, 1134 DAG.getConstant(NVTBits-Amt, ShTy))); 1135 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); 1136 } 1137} 1138 1139/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1140/// this shift based on knowledge of the high bit of the shift amount. If we 1141/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1142/// shift amount. 1143bool DAGTypeLegalizer:: 1144ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1145 SDValue Amt = N->getOperand(1); 1146 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1147 EVT ShTy = Amt.getValueType(); 1148 unsigned ShBits = ShTy.getScalarType().getSizeInBits(); 1149 unsigned NVTBits = NVT.getScalarType().getSizeInBits(); 1150 assert(isPowerOf2_32(NVTBits) && 1151 "Expanded integer type size not a power of two!"); 1152 DebugLoc dl = N->getDebugLoc(); 1153 1154 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1155 APInt KnownZero, KnownOne; 1156 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1157 1158 // If we don't know anything about the high bits, exit. 1159 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1160 return false; 1161 1162 // Get the incoming operand to be shifted. 1163 SDValue InL, InH; 1164 GetExpandedInteger(N->getOperand(0), InL, InH); 1165 1166 // If we know that any of the high bits of the shift amount are one, then we 1167 // can do this as a couple of simple shifts. 1168 if (KnownOne.intersects(HighBitMask)) { 1169 // Mask out the high bit, which we know is set. 1170 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, 1171 DAG.getConstant(~HighBitMask, ShTy)); 1172 1173 switch (N->getOpcode()) { 1174 default: llvm_unreachable("Unknown shift"); 1175 case ISD::SHL: 1176 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1177 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 1178 return true; 1179 case ISD::SRL: 1180 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1181 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 1182 return true; 1183 case ISD::SRA: 1184 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 1185 DAG.getConstant(NVTBits-1, ShTy)); 1186 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 1187 return true; 1188 } 1189 } 1190 1191#if 0 1192 // FIXME: This code is broken for shifts with a zero amount! 1193 // If we know that all of the high bits of the shift amount are zero, then we 1194 // can do this as a couple of simple shifts. 1195 if ((KnownZero & HighBitMask) == HighBitMask) { 1196 // Compute 32-amt. 1197 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1198 DAG.getConstant(NVTBits, ShTy), 1199 Amt); 1200 unsigned Op1, Op2; 1201 switch (N->getOpcode()) { 1202 default: llvm_unreachable("Unknown shift"); 1203 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1204 case ISD::SRL: 1205 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1206 } 1207 1208 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1209 Hi = DAG.getNode(ISD::OR, NVT, 1210 DAG.getNode(Op1, NVT, InH, Amt), 1211 DAG.getNode(Op2, NVT, InL, Amt2)); 1212 return true; 1213 } 1214#endif 1215 1216 return false; 1217} 1218 1219/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift 1220/// of any size. 1221bool DAGTypeLegalizer:: 1222ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1223 SDValue Amt = N->getOperand(1); 1224 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1225 EVT ShTy = Amt.getValueType(); 1226 unsigned NVTBits = NVT.getSizeInBits(); 1227 assert(isPowerOf2_32(NVTBits) && 1228 "Expanded integer type size not a power of two!"); 1229 DebugLoc dl = N->getDebugLoc(); 1230 1231 // Get the incoming operand to be shifted. 1232 SDValue InL, InH; 1233 GetExpandedInteger(N->getOperand(0), InL, InH); 1234 1235 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy); 1236 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode); 1237 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt); 1238 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy), 1239 Amt, NVBitsNode, ISD::SETULT); 1240 1241 SDValue LoS, HiS, LoL, HiL; 1242 switch (N->getOpcode()) { 1243 default: llvm_unreachable("Unknown shift"); 1244 case ISD::SHL: 1245 // Short: ShAmt < NVTBits 1246 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); 1247 HiS = DAG.getNode(ISD::OR, dl, NVT, 1248 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt), 1249 // FIXME: If Amt is zero, the following shift generates an undefined result 1250 // on some architectures. 1251 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack)); 1252 1253 // Long: ShAmt >= NVTBits 1254 LoL = DAG.getConstant(0, NVT); // Lo part is zero. 1255 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part. 1256 1257 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1258 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1259 return true; 1260 case ISD::SRL: 1261 // Short: ShAmt < NVTBits 1262 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); 1263 LoS = DAG.getNode(ISD::OR, dl, NVT, 1264 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1265 // FIXME: If Amt is zero, the following shift generates an undefined result 1266 // on some architectures. 1267 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack)); 1268 1269 // Long: ShAmt >= NVTBits 1270 HiL = DAG.getConstant(0, NVT); // Hi part is zero. 1271 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part. 1272 1273 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1274 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1275 return true; 1276 case ISD::SRA: 1277 // Short: ShAmt < NVTBits 1278 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); 1279 LoS = DAG.getNode(ISD::OR, dl, NVT, 1280 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1281 // FIXME: If Amt is zero, the following shift generates an undefined result 1282 // on some architectures. 1283 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack)); 1284 1285 // Long: ShAmt >= NVTBits 1286 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part. 1287 DAG.getConstant(NVTBits-1, ShTy)); 1288 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part. 1289 1290 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1291 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1292 return true; 1293 } 1294 1295 return false; 1296} 1297 1298void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1299 SDValue &Lo, SDValue &Hi) { 1300 DebugLoc dl = N->getDebugLoc(); 1301 // Expand the subcomponents. 1302 SDValue LHSL, LHSH, RHSL, RHSH; 1303 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1304 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1305 1306 EVT NVT = LHSL.getValueType(); 1307 SDValue LoOps[2] = { LHSL, RHSL }; 1308 SDValue HiOps[3] = { LHSH, RHSH }; 1309 1310 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1311 // them. TODO: Teach operation legalization how to expand unsupported 1312 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1313 // a carry of type MVT::Glue, but there doesn't seem to be any way to 1314 // generate a value of this type in the expanded code sequence. 1315 bool hasCarry = 1316 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? 1317 ISD::ADDC : ISD::SUBC, 1318 TLI.getTypeToExpandTo(*DAG.getContext(), NVT)); 1319 1320 if (hasCarry) { 1321 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue); 1322 if (N->getOpcode() == ISD::ADD) { 1323 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1324 HiOps[2] = Lo.getValue(1); 1325 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1326 } else { 1327 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1328 HiOps[2] = Lo.getValue(1); 1329 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1330 } 1331 return; 1332 } 1333 1334 if (N->getOpcode() == ISD::ADD) { 1335 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); 1336 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); 1337 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0], 1338 ISD::SETULT); 1339 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1, 1340 DAG.getConstant(1, NVT), 1341 DAG.getConstant(0, NVT)); 1342 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1], 1343 ISD::SETULT); 1344 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2, 1345 DAG.getConstant(1, NVT), Carry1); 1346 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); 1347 } else { 1348 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); 1349 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); 1350 SDValue Cmp = 1351 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()), 1352 LoOps[0], LoOps[1], ISD::SETULT); 1353 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, 1354 DAG.getConstant(1, NVT), 1355 DAG.getConstant(0, NVT)); 1356 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); 1357 } 1358} 1359 1360void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1361 SDValue &Lo, SDValue &Hi) { 1362 // Expand the subcomponents. 1363 SDValue LHSL, LHSH, RHSL, RHSH; 1364 DebugLoc dl = N->getDebugLoc(); 1365 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1366 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1367 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue); 1368 SDValue LoOps[2] = { LHSL, RHSL }; 1369 SDValue HiOps[3] = { LHSH, RHSH }; 1370 1371 if (N->getOpcode() == ISD::ADDC) { 1372 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1373 HiOps[2] = Lo.getValue(1); 1374 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1375 } else { 1376 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1377 HiOps[2] = Lo.getValue(1); 1378 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1379 } 1380 1381 // Legalized the flag result - switch anything that used the old flag to 1382 // use the new one. 1383 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1384} 1385 1386void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1387 SDValue &Lo, SDValue &Hi) { 1388 // Expand the subcomponents. 1389 SDValue LHSL, LHSH, RHSL, RHSH; 1390 DebugLoc dl = N->getDebugLoc(); 1391 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1392 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1393 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue); 1394 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1395 SDValue HiOps[3] = { LHSH, RHSH }; 1396 1397 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3); 1398 HiOps[2] = Lo.getValue(1); 1399 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); 1400 1401 // Legalized the flag result - switch anything that used the old flag to 1402 // use the new one. 1403 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1404} 1405 1406void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1407 SDValue &Lo, SDValue &Hi) { 1408 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1409 DebugLoc dl = N->getDebugLoc(); 1410 SDValue Op = N->getOperand(0); 1411 if (Op.getValueType().bitsLE(NVT)) { 1412 // The low part is any extension of the input (which degenerates to a copy). 1413 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op); 1414 Hi = DAG.getUNDEF(NVT); // The high part is undefined. 1415 } else { 1416 // For example, extension of an i48 to an i64. The operand type necessarily 1417 // promotes to the result type, so will end up being expanded too. 1418 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1419 "Only know how to promote this result!"); 1420 SDValue Res = GetPromotedInteger(Op); 1421 assert(Res.getValueType() == N->getValueType(0) && 1422 "Operand over promoted?"); 1423 // Split the promoted operand. This will simplify when it is expanded. 1424 SplitInteger(Res, Lo, Hi); 1425 } 1426} 1427 1428void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1429 SDValue &Lo, SDValue &Hi) { 1430 DebugLoc dl = N->getDebugLoc(); 1431 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1432 EVT NVT = Lo.getValueType(); 1433 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1434 unsigned NVTBits = NVT.getSizeInBits(); 1435 unsigned EVTBits = EVT.getSizeInBits(); 1436 1437 if (NVTBits < EVTBits) { 1438 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, 1439 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1440 EVTBits - NVTBits))); 1441 } else { 1442 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); 1443 // The high part replicates the sign bit of Lo, make it explicit. 1444 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1445 DAG.getConstant(NVTBits-1, TLI.getPointerTy())); 1446 } 1447} 1448 1449void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1450 SDValue &Lo, SDValue &Hi) { 1451 DebugLoc dl = N->getDebugLoc(); 1452 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1453 EVT NVT = Lo.getValueType(); 1454 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1455 unsigned NVTBits = NVT.getSizeInBits(); 1456 unsigned EVTBits = EVT.getSizeInBits(); 1457 1458 if (NVTBits < EVTBits) { 1459 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, 1460 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1461 EVTBits - NVTBits))); 1462 } else { 1463 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); 1464 // The high part must be zero, make it explicit. 1465 Hi = DAG.getConstant(0, NVT); 1466 } 1467} 1468 1469void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1470 SDValue &Lo, SDValue &Hi) { 1471 DebugLoc dl = N->getDebugLoc(); 1472 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1473 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo); 1474 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi); 1475} 1476 1477void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1478 SDValue &Lo, SDValue &Hi) { 1479 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1480 unsigned NBitWidth = NVT.getSizeInBits(); 1481 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1482 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT); 1483 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1484} 1485 1486void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1487 SDValue &Lo, SDValue &Hi) { 1488 DebugLoc dl = N->getDebugLoc(); 1489 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1490 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1491 EVT NVT = Lo.getValueType(); 1492 1493 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi, 1494 DAG.getConstant(0, NVT), ISD::SETNE); 1495 1496 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo); 1497 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi); 1498 1499 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ, 1500 DAG.getNode(ISD::ADD, dl, NVT, LoLZ, 1501 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1502 Hi = DAG.getConstant(0, NVT); 1503} 1504 1505void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1506 SDValue &Lo, SDValue &Hi) { 1507 DebugLoc dl = N->getDebugLoc(); 1508 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1509 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1510 EVT NVT = Lo.getValueType(); 1511 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), 1512 DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); 1513 Hi = DAG.getConstant(0, NVT); 1514} 1515 1516void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1517 SDValue &Lo, SDValue &Hi) { 1518 DebugLoc dl = N->getDebugLoc(); 1519 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1520 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1521 EVT NVT = Lo.getValueType(); 1522 1523 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, 1524 DAG.getConstant(0, NVT), ISD::SETNE); 1525 1526 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo); 1527 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi); 1528 1529 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ, 1530 DAG.getNode(ISD::ADD, dl, NVT, HiLZ, 1531 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1532 Hi = DAG.getConstant(0, NVT); 1533} 1534 1535void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1536 SDValue &Hi) { 1537 DebugLoc dl = N->getDebugLoc(); 1538 EVT VT = N->getValueType(0); 1539 SDValue Op = N->getOperand(0); 1540 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1541 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1542 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi); 1543} 1544 1545void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1546 SDValue &Hi) { 1547 DebugLoc dl = N->getDebugLoc(); 1548 EVT VT = N->getValueType(0); 1549 SDValue Op = N->getOperand(0); 1550 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1551 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1552 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi); 1553} 1554 1555void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1556 SDValue &Lo, SDValue &Hi) { 1557 if (ISD::isNormalLoad(N)) { 1558 ExpandRes_NormalLoad(N, Lo, Hi); 1559 return; 1560 } 1561 1562 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1563 1564 EVT VT = N->getValueType(0); 1565 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1566 SDValue Ch = N->getChain(); 1567 SDValue Ptr = N->getBasePtr(); 1568 ISD::LoadExtType ExtType = N->getExtensionType(); 1569 unsigned Alignment = N->getAlignment(); 1570 bool isVolatile = N->isVolatile(); 1571 bool isNonTemporal = N->isNonTemporal(); 1572 DebugLoc dl = N->getDebugLoc(); 1573 1574 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1575 1576 if (N->getMemoryVT().bitsLE(NVT)) { 1577 EVT MemVT = N->getMemoryVT(); 1578 1579 Lo = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getPointerInfo(), 1580 MemVT, isVolatile, isNonTemporal, Alignment); 1581 1582 // Remember the chain. 1583 Ch = Lo.getValue(1); 1584 1585 if (ExtType == ISD::SEXTLOAD) { 1586 // The high part is obtained by SRA'ing all but one of the bits of the 1587 // lo part. 1588 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1589 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1590 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1591 } else if (ExtType == ISD::ZEXTLOAD) { 1592 // The high part is just a zero. 1593 Hi = DAG.getConstant(0, NVT); 1594 } else { 1595 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1596 // The high part is undefined. 1597 Hi = DAG.getUNDEF(NVT); 1598 } 1599 } else if (TLI.isLittleEndian()) { 1600 // Little-endian - low bits are at low addresses. 1601 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(), 1602 isVolatile, isNonTemporal, Alignment); 1603 1604 unsigned ExcessBits = 1605 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1606 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits); 1607 1608 // Increment the pointer to the other half. 1609 unsigned IncrementSize = NVT.getSizeInBits()/8; 1610 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1611 DAG.getIntPtrConstant(IncrementSize)); 1612 Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, 1613 N->getPointerInfo().getWithOffset(IncrementSize), NEVT, 1614 isVolatile, isNonTemporal, 1615 MinAlign(Alignment, IncrementSize)); 1616 1617 // Build a factor node to remember that this load is independent of the 1618 // other one. 1619 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1620 Hi.getValue(1)); 1621 } else { 1622 // Big-endian - high bits are at low addresses. Favor aligned loads at 1623 // the cost of some bit-fiddling. 1624 EVT MemVT = N->getMemoryVT(); 1625 unsigned EBytes = MemVT.getStoreSize(); 1626 unsigned IncrementSize = NVT.getSizeInBits()/8; 1627 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1628 1629 // Load both the high bits and maybe some of the low bits. 1630 Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getPointerInfo(), 1631 EVT::getIntegerVT(*DAG.getContext(), 1632 MemVT.getSizeInBits() - ExcessBits), 1633 isVolatile, isNonTemporal, Alignment); 1634 1635 // Increment the pointer to the other half. 1636 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1637 DAG.getIntPtrConstant(IncrementSize)); 1638 // Load the rest of the low bits. 1639 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, dl, Ch, Ptr, 1640 N->getPointerInfo().getWithOffset(IncrementSize), 1641 EVT::getIntegerVT(*DAG.getContext(), ExcessBits), 1642 isVolatile, isNonTemporal, 1643 MinAlign(Alignment, IncrementSize)); 1644 1645 // Build a factor node to remember that this load is independent of the 1646 // other one. 1647 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1648 Hi.getValue(1)); 1649 1650 if (ExcessBits < NVT.getSizeInBits()) { 1651 // Transfer low bits from the bottom of Hi to the top of Lo. 1652 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, 1653 DAG.getNode(ISD::SHL, dl, NVT, Hi, 1654 DAG.getConstant(ExcessBits, 1655 TLI.getPointerTy()))); 1656 // Move high bits to the right position in Hi. 1657 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, 1658 NVT, Hi, 1659 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1660 TLI.getPointerTy())); 1661 } 1662 } 1663 1664 // Legalized the chain result - switch anything that used the old chain to 1665 // use the new one. 1666 ReplaceValueWith(SDValue(N, 1), Ch); 1667} 1668 1669void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1670 SDValue &Lo, SDValue &Hi) { 1671 DebugLoc dl = N->getDebugLoc(); 1672 SDValue LL, LH, RL, RH; 1673 GetExpandedInteger(N->getOperand(0), LL, LH); 1674 GetExpandedInteger(N->getOperand(1), RL, RH); 1675 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL); 1676 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); 1677} 1678 1679void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1680 SDValue &Lo, SDValue &Hi) { 1681 EVT VT = N->getValueType(0); 1682 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1683 DebugLoc dl = N->getDebugLoc(); 1684 1685 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); 1686 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); 1687 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); 1688 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); 1689 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1690 SDValue LL, LH, RL, RH; 1691 GetExpandedInteger(N->getOperand(0), LL, LH); 1692 GetExpandedInteger(N->getOperand(1), RL, RH); 1693 unsigned OuterBitSize = VT.getSizeInBits(); 1694 unsigned InnerBitSize = NVT.getSizeInBits(); 1695 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1696 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1697 1698 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1699 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1700 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1701 // The inputs are both zero-extended. 1702 if (HasUMUL_LOHI) { 1703 // We can emit a umul_lohi. 1704 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1705 Hi = SDValue(Lo.getNode(), 1); 1706 return; 1707 } 1708 if (HasMULHU) { 1709 // We can emit a mulhu+mul. 1710 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1711 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1712 return; 1713 } 1714 } 1715 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1716 // The input values are both sign-extended. 1717 if (HasSMUL_LOHI) { 1718 // We can emit a smul_lohi. 1719 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1720 Hi = SDValue(Lo.getNode(), 1); 1721 return; 1722 } 1723 if (HasMULHS) { 1724 // We can emit a mulhs+mul. 1725 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1726 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); 1727 return; 1728 } 1729 } 1730 if (HasUMUL_LOHI) { 1731 // Lo,Hi = umul LHS, RHS. 1732 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, 1733 DAG.getVTList(NVT, NVT), LL, RL); 1734 Lo = UMulLOHI; 1735 Hi = UMulLOHI.getValue(1); 1736 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1737 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1738 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1739 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1740 return; 1741 } 1742 if (HasMULHU) { 1743 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1744 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1745 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1746 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1747 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1748 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1749 return; 1750 } 1751 } 1752 1753 // If nothing else, we can make a libcall. 1754 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1755 if (VT == MVT::i16) 1756 LC = RTLIB::MUL_I16; 1757 else if (VT == MVT::i32) 1758 LC = RTLIB::MUL_I32; 1759 else if (VT == MVT::i64) 1760 LC = RTLIB::MUL_I64; 1761 else if (VT == MVT::i128) 1762 LC = RTLIB::MUL_I128; 1763 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1764 1765 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1766 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi); 1767} 1768 1769void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node, 1770 SDValue &Lo, SDValue &Hi) { 1771 SDValue LHS = Node->getOperand(0); 1772 SDValue RHS = Node->getOperand(1); 1773 DebugLoc dl = Node->getDebugLoc(); 1774 1775 // Expand the result by simply replacing it with the equivalent 1776 // non-overflow-checking operation. 1777 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 1778 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 1779 LHS, RHS); 1780 SplitInteger(Sum, Lo, Hi); 1781 1782 // Compute the overflow. 1783 // 1784 // LHSSign -> LHS >= 0 1785 // RHSSign -> RHS >= 0 1786 // SumSign -> Sum >= 0 1787 // 1788 // Add: 1789 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 1790 // Sub: 1791 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 1792 // 1793 EVT OType = Node->getValueType(1); 1794 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 1795 1796 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 1797 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 1798 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 1799 Node->getOpcode() == ISD::SADDO ? 1800 ISD::SETEQ : ISD::SETNE); 1801 1802 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 1803 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 1804 1805 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 1806 1807 // Use the calculated overflow everywhere. 1808 ReplaceValueWith(SDValue(Node, 1), Cmp); 1809} 1810 1811void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1812 SDValue &Lo, SDValue &Hi) { 1813 EVT VT = N->getValueType(0); 1814 DebugLoc dl = N->getDebugLoc(); 1815 1816 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1817 if (VT == MVT::i16) 1818 LC = RTLIB::SDIV_I16; 1819 else if (VT == MVT::i32) 1820 LC = RTLIB::SDIV_I32; 1821 else if (VT == MVT::i64) 1822 LC = RTLIB::SDIV_I64; 1823 else if (VT == MVT::i128) 1824 LC = RTLIB::SDIV_I128; 1825 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1826 1827 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1828 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1829} 1830 1831void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1832 SDValue &Lo, SDValue &Hi) { 1833 EVT VT = N->getValueType(0); 1834 DebugLoc dl = N->getDebugLoc(); 1835 1836 // If we can emit an efficient shift operation, do so now. Check to see if 1837 // the RHS is a constant. 1838 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1839 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1840 1841 // If we can determine that the high bit of the shift is zero or one, even if 1842 // the low bits are variable, emit this shift in an optimized form. 1843 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1844 return; 1845 1846 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1847 unsigned PartsOpc; 1848 if (N->getOpcode() == ISD::SHL) { 1849 PartsOpc = ISD::SHL_PARTS; 1850 } else if (N->getOpcode() == ISD::SRL) { 1851 PartsOpc = ISD::SRL_PARTS; 1852 } else { 1853 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1854 PartsOpc = ISD::SRA_PARTS; 1855 } 1856 1857 // Next check to see if the target supports this SHL_PARTS operation or if it 1858 // will custom expand it. 1859 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1860 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1861 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1862 Action == TargetLowering::Custom) { 1863 // Expand the subcomponents. 1864 SDValue LHSL, LHSH; 1865 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1866 1867 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1868 EVT VT = LHSL.getValueType(); 1869 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3); 1870 Hi = Lo.getValue(1); 1871 return; 1872 } 1873 1874 // Otherwise, emit a libcall. 1875 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1876 bool isSigned; 1877 if (N->getOpcode() == ISD::SHL) { 1878 isSigned = false; /*sign irrelevant*/ 1879 if (VT == MVT::i16) 1880 LC = RTLIB::SHL_I16; 1881 else if (VT == MVT::i32) 1882 LC = RTLIB::SHL_I32; 1883 else if (VT == MVT::i64) 1884 LC = RTLIB::SHL_I64; 1885 else if (VT == MVT::i128) 1886 LC = RTLIB::SHL_I128; 1887 } else if (N->getOpcode() == ISD::SRL) { 1888 isSigned = false; 1889 if (VT == MVT::i16) 1890 LC = RTLIB::SRL_I16; 1891 else if (VT == MVT::i32) 1892 LC = RTLIB::SRL_I32; 1893 else if (VT == MVT::i64) 1894 LC = RTLIB::SRL_I64; 1895 else if (VT == MVT::i128) 1896 LC = RTLIB::SRL_I128; 1897 } else { 1898 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1899 isSigned = true; 1900 if (VT == MVT::i16) 1901 LC = RTLIB::SRA_I16; 1902 else if (VT == MVT::i32) 1903 LC = RTLIB::SRA_I32; 1904 else if (VT == MVT::i64) 1905 LC = RTLIB::SRA_I64; 1906 else if (VT == MVT::i128) 1907 LC = RTLIB::SRA_I128; 1908 } 1909 1910 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) { 1911 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1912 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi); 1913 return; 1914 } 1915 1916 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi)) 1917 llvm_unreachable("Unsupported shift!"); 1918} 1919 1920void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 1921 SDValue &Lo, SDValue &Hi) { 1922 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1923 DebugLoc dl = N->getDebugLoc(); 1924 SDValue Op = N->getOperand(0); 1925 if (Op.getValueType().bitsLE(NVT)) { 1926 // The low part is sign extension of the input (degenerates to a copy). 1927 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); 1928 // The high part is obtained by SRA'ing all but one of the bits of low part. 1929 unsigned LoSize = NVT.getSizeInBits(); 1930 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1931 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1932 } else { 1933 // For example, extension of an i48 to an i64. The operand type necessarily 1934 // promotes to the result type, so will end up being expanded too. 1935 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1936 "Only know how to promote this result!"); 1937 SDValue Res = GetPromotedInteger(Op); 1938 assert(Res.getValueType() == N->getValueType(0) && 1939 "Operand over promoted?"); 1940 // Split the promoted operand. This will simplify when it is expanded. 1941 SplitInteger(Res, Lo, Hi); 1942 unsigned ExcessBits = 1943 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1944 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 1945 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1946 ExcessBits))); 1947 } 1948} 1949 1950void DAGTypeLegalizer:: 1951ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 1952 DebugLoc dl = N->getDebugLoc(); 1953 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1954 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1955 1956 if (EVT.bitsLE(Lo.getValueType())) { 1957 // sext_inreg the low part if needed. 1958 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, 1959 N->getOperand(1)); 1960 1961 // The high part gets the sign extension from the lo-part. This handles 1962 // things like sextinreg V:i64 from i8. 1963 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo, 1964 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 1965 TLI.getPointerTy())); 1966 } else { 1967 // For example, extension of an i48 to an i64. Leave the low part alone, 1968 // sext_inreg the high part. 1969 unsigned ExcessBits = 1970 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 1971 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 1972 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1973 ExcessBits))); 1974 } 1975} 1976 1977void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1978 SDValue &Lo, SDValue &Hi) { 1979 EVT VT = N->getValueType(0); 1980 DebugLoc dl = N->getDebugLoc(); 1981 1982 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1983 if (VT == MVT::i16) 1984 LC = RTLIB::SREM_I16; 1985 else if (VT == MVT::i32) 1986 LC = RTLIB::SREM_I32; 1987 else if (VT == MVT::i64) 1988 LC = RTLIB::SREM_I64; 1989 else if (VT == MVT::i128) 1990 LC = RTLIB::SREM_I128; 1991 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1992 1993 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1994 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1995} 1996 1997void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 1998 SDValue &Lo, SDValue &Hi) { 1999 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2000 DebugLoc dl = N->getDebugLoc(); 2001 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); 2002 Hi = DAG.getNode(ISD::SRL, dl, 2003 N->getOperand(0).getValueType(), N->getOperand(0), 2004 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy())); 2005 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); 2006} 2007 2008void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N, 2009 SDValue &Lo, SDValue &Hi) { 2010 SDValue LHS = N->getOperand(0); 2011 SDValue RHS = N->getOperand(1); 2012 DebugLoc dl = N->getDebugLoc(); 2013 2014 // Expand the result by simply replacing it with the equivalent 2015 // non-overflow-checking operation. 2016 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ? 2017 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2018 LHS, RHS); 2019 SplitInteger(Sum, Lo, Hi); 2020 2021 // Calculate the overflow: addition overflows iff a + b < a, and subtraction 2022 // overflows iff a - b > a. 2023 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, 2024 N->getOpcode () == ISD::UADDO ? 2025 ISD::SETULT : ISD::SETUGT); 2026 2027 // Use the calculated overflow everywhere. 2028 ReplaceValueWith(SDValue(N, 1), Ofl); 2029} 2030 2031void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 2032 SDValue &Lo, SDValue &Hi) { 2033 EVT VT = N->getValueType(0); 2034 DebugLoc dl = N->getDebugLoc(); 2035 2036 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2037 if (VT == MVT::i16) 2038 LC = RTLIB::UDIV_I16; 2039 else if (VT == MVT::i32) 2040 LC = RTLIB::UDIV_I32; 2041 else if (VT == MVT::i64) 2042 LC = RTLIB::UDIV_I64; 2043 else if (VT == MVT::i128) 2044 LC = RTLIB::UDIV_I128; 2045 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 2046 2047 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2048 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 2049} 2050 2051void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 2052 SDValue &Lo, SDValue &Hi) { 2053 EVT VT = N->getValueType(0); 2054 DebugLoc dl = N->getDebugLoc(); 2055 2056 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2057 if (VT == MVT::i16) 2058 LC = RTLIB::UREM_I16; 2059 else if (VT == MVT::i32) 2060 LC = RTLIB::UREM_I32; 2061 else if (VT == MVT::i64) 2062 LC = RTLIB::UREM_I64; 2063 else if (VT == MVT::i128) 2064 LC = RTLIB::UREM_I128; 2065 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 2066 2067 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2068 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 2069} 2070 2071void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 2072 SDValue &Lo, SDValue &Hi) { 2073 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2074 DebugLoc dl = N->getDebugLoc(); 2075 SDValue Op = N->getOperand(0); 2076 if (Op.getValueType().bitsLE(NVT)) { 2077 // The low part is zero extension of the input (degenerates to a copy). 2078 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); 2079 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 2080 } else { 2081 // For example, extension of an i48 to an i64. The operand type necessarily 2082 // promotes to the result type, so will end up being expanded too. 2083 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 2084 "Only know how to promote this result!"); 2085 SDValue Res = GetPromotedInteger(Op); 2086 assert(Res.getValueType() == N->getValueType(0) && 2087 "Operand over promoted?"); 2088 // Split the promoted operand. This will simplify when it is expanded. 2089 SplitInteger(Res, Lo, Hi); 2090 unsigned ExcessBits = 2091 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 2092 Hi = DAG.getZeroExtendInReg(Hi, dl, 2093 EVT::getIntegerVT(*DAG.getContext(), 2094 ExcessBits)); 2095 } 2096} 2097 2098 2099//===----------------------------------------------------------------------===// 2100// Integer Operand Expansion 2101//===----------------------------------------------------------------------===// 2102 2103/// ExpandIntegerOperand - This method is called when the specified operand of 2104/// the specified node is found to need expansion. At this point, all of the 2105/// result types of the node are known to be legal, but other operands of the 2106/// node may need promotion or expansion as well as the specified one. 2107bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 2108 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n"); 2109 SDValue Res = SDValue(); 2110 2111 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 2112 return false; 2113 2114 switch (N->getOpcode()) { 2115 default: 2116 #ifndef NDEBUG 2117 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": "; 2118 N->dump(&DAG); dbgs() << "\n"; 2119 #endif 2120 llvm_unreachable("Do not know how to expand this operator's operand!"); 2121 2122 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break; 2123 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 2124 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 2125 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 2126 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 2127 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; 2128 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 2129 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 2130 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 2131 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break; 2132 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 2133 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 2134 2135 case ISD::SHL: 2136 case ISD::SRA: 2137 case ISD::SRL: 2138 case ISD::ROTL: 2139 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break; 2140 case ISD::RETURNADDR: 2141 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break; 2142 } 2143 2144 // If the result is null, the sub-method took care of registering results etc. 2145 if (!Res.getNode()) return false; 2146 2147 // If the result is N, the sub-method updated N in place. Tell the legalizer 2148 // core about this. 2149 if (Res.getNode() == N) 2150 return true; 2151 2152 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2153 "Invalid operand expansion"); 2154 2155 ReplaceValueWith(SDValue(N, 0), Res); 2156 return false; 2157} 2158 2159/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 2160/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 2161void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 2162 SDValue &NewRHS, 2163 ISD::CondCode &CCCode, 2164 DebugLoc dl) { 2165 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 2166 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 2167 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 2168 2169 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 2170 if (RHSLo == RHSHi) { 2171 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 2172 if (RHSCST->isAllOnesValue()) { 2173 // Equality comparison to -1. 2174 NewLHS = DAG.getNode(ISD::AND, dl, 2175 LHSLo.getValueType(), LHSLo, LHSHi); 2176 NewRHS = RHSLo; 2177 return; 2178 } 2179 } 2180 } 2181 2182 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); 2183 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); 2184 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS); 2185 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2186 return; 2187 } 2188 2189 // If this is a comparison of the sign bit, just look at the top part. 2190 // X > -1, x < 0 2191 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 2192 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 2193 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 2194 NewLHS = LHSHi; 2195 NewRHS = RHSHi; 2196 return; 2197 } 2198 2199 // FIXME: This generated code sucks. 2200 ISD::CondCode LowCC; 2201 switch (CCCode) { 2202 default: llvm_unreachable("Unknown integer setcc!"); 2203 case ISD::SETLT: 2204 case ISD::SETULT: LowCC = ISD::SETULT; break; 2205 case ISD::SETGT: 2206 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2207 case ISD::SETLE: 2208 case ISD::SETULE: LowCC = ISD::SETULE; break; 2209 case ISD::SETGE: 2210 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2211 } 2212 2213 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2214 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2215 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2216 2217 // NOTE: on targets without efficient SELECT of bools, we can always use 2218 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2219 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL); 2220 SDValue Tmp1, Tmp2; 2221 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), 2222 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl); 2223 if (!Tmp1.getNode()) 2224 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 2225 LHSLo, RHSLo, LowCC); 2226 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2227 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl); 2228 if (!Tmp2.getNode()) 2229 Tmp2 = DAG.getNode(ISD::SETCC, dl, 2230 TLI.getSetCCResultType(LHSHi.getValueType()), 2231 LHSHi, RHSHi, DAG.getCondCode(CCCode)); 2232 2233 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2234 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2235 if ((Tmp1C && Tmp1C->isNullValue()) || 2236 (Tmp2C && Tmp2C->isNullValue() && 2237 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2238 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2239 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2240 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2241 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2242 // low part is known false, returns high part. 2243 // For LE / GE, if high part is known false, ignore the low part. 2244 // For LT / GT, if high part is known true, ignore the low part. 2245 NewLHS = Tmp2; 2246 NewRHS = SDValue(); 2247 return; 2248 } 2249 2250 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2251 LHSHi, RHSHi, ISD::SETEQ, false, 2252 DagCombineInfo, dl); 2253 if (!NewLHS.getNode()) 2254 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 2255 LHSHi, RHSHi, ISD::SETEQ); 2256 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), 2257 NewLHS, Tmp1, Tmp2); 2258 NewRHS = SDValue(); 2259} 2260 2261SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2262 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2263 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2264 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2265 2266 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2267 // against zero to select between true and false values. 2268 if (NewRHS.getNode() == 0) { 2269 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2270 CCCode = ISD::SETNE; 2271 } 2272 2273 // Update N to have the operands specified. 2274 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 2275 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2276 N->getOperand(4)), 0); 2277} 2278 2279SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2280 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2281 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2282 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2283 2284 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2285 // against zero to select between true and false values. 2286 if (NewRHS.getNode() == 0) { 2287 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2288 CCCode = ISD::SETNE; 2289 } 2290 2291 // Update N to have the operands specified. 2292 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, 2293 N->getOperand(2), N->getOperand(3), 2294 DAG.getCondCode(CCCode)), 0); 2295} 2296 2297SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2298 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2299 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2300 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2301 2302 // If ExpandSetCCOperands returned a scalar, use it. 2303 if (NewRHS.getNode() == 0) { 2304 assert(NewLHS.getValueType() == N->getValueType(0) && 2305 "Unexpected setcc expansion!"); 2306 return NewLHS; 2307 } 2308 2309 // Otherwise, update N to have the operands specified. 2310 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, 2311 DAG.getCondCode(CCCode)), 0); 2312} 2313 2314SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) { 2315 // The value being shifted is legal, but the shift amount is too big. 2316 // It follows that either the result of the shift is undefined, or the 2317 // upper half of the shift amount is zero. Just use the lower half. 2318 SDValue Lo, Hi; 2319 GetExpandedInteger(N->getOperand(1), Lo, Hi); 2320 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0); 2321} 2322 2323SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) { 2324 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This 2325 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this 2326 // constant to valid type. 2327 SDValue Lo, Hi; 2328 GetExpandedInteger(N->getOperand(0), Lo, Hi); 2329 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0); 2330} 2331 2332SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2333 SDValue Op = N->getOperand(0); 2334 EVT DstVT = N->getValueType(0); 2335 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2336 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2337 "Don't know how to expand this SINT_TO_FP!"); 2338 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc()); 2339} 2340 2341SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2342 if (ISD::isNormalStore(N)) 2343 return ExpandOp_NormalStore(N, OpNo); 2344 2345 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2346 assert(OpNo == 1 && "Can only expand the stored value so far"); 2347 2348 EVT VT = N->getOperand(1).getValueType(); 2349 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2350 SDValue Ch = N->getChain(); 2351 SDValue Ptr = N->getBasePtr(); 2352 unsigned Alignment = N->getAlignment(); 2353 bool isVolatile = N->isVolatile(); 2354 bool isNonTemporal = N->isNonTemporal(); 2355 DebugLoc dl = N->getDebugLoc(); 2356 SDValue Lo, Hi; 2357 2358 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2359 2360 if (N->getMemoryVT().bitsLE(NVT)) { 2361 GetExpandedInteger(N->getValue(), Lo, Hi); 2362 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), 2363 N->getMemoryVT(), isVolatile, isNonTemporal, 2364 Alignment); 2365 } 2366 2367 if (TLI.isLittleEndian()) { 2368 // Little-endian - low bits are at low addresses. 2369 GetExpandedInteger(N->getValue(), Lo, Hi); 2370 2371 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), 2372 isVolatile, isNonTemporal, Alignment); 2373 2374 unsigned ExcessBits = 2375 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2376 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits); 2377 2378 // Increment the pointer to the other half. 2379 unsigned IncrementSize = NVT.getSizeInBits()/8; 2380 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2381 DAG.getIntPtrConstant(IncrementSize)); 2382 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, 2383 N->getPointerInfo().getWithOffset(IncrementSize), 2384 NEVT, isVolatile, isNonTemporal, 2385 MinAlign(Alignment, IncrementSize)); 2386 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2387 } 2388 2389 // Big-endian - high bits are at low addresses. Favor aligned stores at 2390 // the cost of some bit-fiddling. 2391 GetExpandedInteger(N->getValue(), Lo, Hi); 2392 2393 EVT ExtVT = N->getMemoryVT(); 2394 unsigned EBytes = ExtVT.getStoreSize(); 2395 unsigned IncrementSize = NVT.getSizeInBits()/8; 2396 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2397 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(), 2398 ExtVT.getSizeInBits() - ExcessBits); 2399 2400 if (ExcessBits < NVT.getSizeInBits()) { 2401 // Transfer high bits from the top of Lo to the bottom of Hi. 2402 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, 2403 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2404 TLI.getPointerTy())); 2405 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, 2406 DAG.getNode(ISD::SRL, dl, NVT, Lo, 2407 DAG.getConstant(ExcessBits, 2408 TLI.getPointerTy()))); 2409 } 2410 2411 // Store both the high bits and maybe some of the low bits. 2412 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(), 2413 HiVT, isVolatile, isNonTemporal, Alignment); 2414 2415 // Increment the pointer to the other half. 2416 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2417 DAG.getIntPtrConstant(IncrementSize)); 2418 // Store the lowest ExcessBits bits in the second half. 2419 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, 2420 N->getPointerInfo().getWithOffset(IncrementSize), 2421 EVT::getIntegerVT(*DAG.getContext(), ExcessBits), 2422 isVolatile, isNonTemporal, 2423 MinAlign(Alignment, IncrementSize)); 2424 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2425} 2426 2427SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2428 SDValue InL, InH; 2429 GetExpandedInteger(N->getOperand(0), InL, InH); 2430 // Just truncate the low part of the source. 2431 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL); 2432} 2433 2434static const fltSemantics *EVTToAPFloatSemantics(EVT VT) { 2435 switch (VT.getSimpleVT().SimpleTy) { 2436 default: llvm_unreachable("Unknown FP format"); 2437 case MVT::f32: return &APFloat::IEEEsingle; 2438 case MVT::f64: return &APFloat::IEEEdouble; 2439 case MVT::f80: return &APFloat::x87DoubleExtended; 2440 case MVT::f128: return &APFloat::IEEEquad; 2441 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 2442 } 2443} 2444 2445SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2446 SDValue Op = N->getOperand(0); 2447 EVT SrcVT = Op.getValueType(); 2448 EVT DstVT = N->getValueType(0); 2449 DebugLoc dl = N->getDebugLoc(); 2450 2451 // The following optimization is valid only if every value in SrcVT (when 2452 // treated as signed) is representable in DstVT. Check that the mantissa 2453 // size of DstVT is >= than the number of bits in SrcVT -1. 2454 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT); 2455 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 && 2456 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2457 // Do a signed conversion then adjust the result. 2458 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); 2459 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2460 2461 // The result of the signed conversion needs adjusting if the 'sign bit' of 2462 // the incoming integer was set. To handle this, we dynamically test to see 2463 // if it is set, and, if so, add a fudge factor. 2464 2465 const uint64_t F32TwoE32 = 0x4F800000ULL; 2466 const uint64_t F32TwoE64 = 0x5F800000ULL; 2467 const uint64_t F32TwoE128 = 0x7F800000ULL; 2468 2469 APInt FF(32, 0); 2470 if (SrcVT == MVT::i32) 2471 FF = APInt(32, F32TwoE32); 2472 else if (SrcVT == MVT::i64) 2473 FF = APInt(32, F32TwoE64); 2474 else if (SrcVT == MVT::i128) 2475 FF = APInt(32, F32TwoE128); 2476 else 2477 assert(false && "Unsupported UINT_TO_FP!"); 2478 2479 // Check whether the sign bit is set. 2480 SDValue Lo, Hi; 2481 GetExpandedInteger(Op, Lo, Hi); 2482 SDValue SignSet = DAG.getSetCC(dl, 2483 TLI.getSetCCResultType(Hi.getValueType()), 2484 Hi, DAG.getConstant(0, Hi.getValueType()), 2485 ISD::SETLT); 2486 2487 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2488 SDValue FudgePtr = DAG.getConstantPool( 2489 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 2490 TLI.getPointerTy()); 2491 2492 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2493 SDValue Zero = DAG.getIntPtrConstant(0); 2494 SDValue Four = DAG.getIntPtrConstant(4); 2495 if (TLI.isBigEndian()) std::swap(Zero, Four); 2496 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 2497 Zero, Four); 2498 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2499 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset); 2500 Alignment = std::min(Alignment, 4u); 2501 2502 // Load the value out, extending it from f32 to the destination float type. 2503 // FIXME: Avoid the extend by constructing the right constant pool? 2504 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, dl, DAG.getEntryNode(), 2505 FudgePtr, 2506 MachinePointerInfo::getConstantPool(), 2507 MVT::f32, 2508 false, false, Alignment); 2509 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); 2510 } 2511 2512 // Otherwise, use a libcall. 2513 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2514 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2515 "Don't know how to expand this UINT_TO_FP!"); 2516 return MakeLibCall(LC, DstVT, &Op, 1, true, dl); 2517} 2518