LegalizeIntegerTypes.cpp revision fc3623bc50aa9e2a56736775edbd3ae919565351
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22#include "llvm/CodeGen/PseudoSourceValue.h" 23#include "llvm/Support/ErrorHandling.h" 24#include "llvm/Support/raw_ostream.h" 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28// Integer Result Promotion 29//===----------------------------------------------------------------------===// 30 31/// PromoteIntegerResult - This method is called when a result of a node is 32/// found to be in need of promotion to a larger type. At this point, the node 33/// may also have invalid operands or may have other results that need 34/// expansion, we just know that (at least) one result needs promotion. 35void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n"); 37 SDValue Res = SDValue(); 38 39 // See if the target wants to custom expand this node. 40 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 41 return; 42 43 switch (N->getOpcode()) { 44 default: 45#ifndef NDEBUG 46 dbgs() << "PromoteIntegerResult #" << ResNo << ": "; 47 N->dump(&DAG); dbgs() << "\n"; 48#endif 49 llvm_unreachable("Do not know how to promote this operator!"); 50 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 51 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 52 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; 53 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 54 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 55 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 56 case ISD::CONVERT_RNDSAT: 57 Res = PromoteIntRes_CONVERT_RNDSAT(N); break; 58 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; 59 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break; 60 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; 61 case ISD::EXTRACT_VECTOR_ELT: 62 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 63 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 64 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break; 65 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; 66 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 67 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; 68 case ISD::SIGN_EXTEND_INREG: 69 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 70 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 71 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; 72 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; 73 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break; 74 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break; 75 76 case ISD::EXTRACT_SUBVECTOR: 77 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break; 78 case ISD::VECTOR_SHUFFLE: 79 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break; 80 case ISD::INSERT_VECTOR_ELT: 81 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break; 82 case ISD::BUILD_VECTOR: 83 Res = PromoteIntRes_BUILD_VECTOR(N); break; 84 case ISD::SCALAR_TO_VECTOR: 85 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break; 86 87 case ISD::SIGN_EXTEND: 88 case ISD::ZERO_EXTEND: 89 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; 90 91 case ISD::FP_TO_SINT: 92 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; 93 94 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break; 95 96 case ISD::AND: 97 case ISD::OR: 98 case ISD::XOR: 99 case ISD::ADD: 100 case ISD::SUB: 101 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break; 102 103 case ISD::SDIV: 104 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; 105 106 case ISD::UDIV: 107 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break; 108 109 case ISD::SADDO: 110 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; 111 case ISD::UADDO: 112 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; 113 case ISD::SMULO: 114 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; 115 116 case ISD::ATOMIC_LOAD_ADD: 117 case ISD::ATOMIC_LOAD_SUB: 118 case ISD::ATOMIC_LOAD_AND: 119 case ISD::ATOMIC_LOAD_OR: 120 case ISD::ATOMIC_LOAD_XOR: 121 case ISD::ATOMIC_LOAD_NAND: 122 case ISD::ATOMIC_LOAD_MIN: 123 case ISD::ATOMIC_LOAD_MAX: 124 case ISD::ATOMIC_LOAD_UMIN: 125 case ISD::ATOMIC_LOAD_UMAX: 126 case ISD::ATOMIC_SWAP: 127 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 128 129 case ISD::ATOMIC_CMP_SWAP: 130 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 131 } 132 133 // If the result is null then the sub-method took care of registering it. 134 if (Res.getNode()) 135 SetPromotedInteger(SDValue(N, ResNo), Res); 136} 137 138SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 139 // Sign-extend the new bits, and continue the assertion. 140 SDValue Op = SExtPromotedInteger(N->getOperand(0)); 141 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(), 142 Op.getValueType(), Op, N->getOperand(1)); 143} 144 145SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 146 // Zero the new bits, and continue the assertion. 147 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 148 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), 149 Op.getValueType(), Op, N->getOperand(1)); 150} 151 152SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 153 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 154 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 155 N->getMemoryVT(), 156 N->getChain(), N->getBasePtr(), 157 Op2, N->getMemOperand()); 158 // Legalized the chain result - switch anything that used the old chain to 159 // use the new one. 160 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 161 return Res; 162} 163 164SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 165 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 166 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 167 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 168 N->getMemoryVT(), N->getChain(), N->getBasePtr(), 169 Op2, Op3, N->getMemOperand()); 170 // Legalized the chain result - switch anything that used the old chain to 171 // use the new one. 172 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 173 return Res; 174} 175 176SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) { 177 SDValue InOp = N->getOperand(0); 178 EVT InVT = InOp.getValueType(); 179 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); 180 EVT OutVT = N->getValueType(0); 181 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 182 DebugLoc dl = N->getDebugLoc(); 183 184 switch (getTypeAction(InVT)) { 185 default: 186 assert(false && "Unknown type action!"); 187 break; 188 case TargetLowering::TypeLegal: 189 break; 190 case TargetLowering::TypePromoteInteger: 191 if (NOutVT.bitsEq(NInVT)) 192 // The input promotes to the same size. Convert the promoted value. 193 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); 194 if (NInVT.isVector()) 195 // Promote vector element via memory load/store. 196 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 197 CreateStackStoreLoad(InOp, OutVT)); 198 break; 199 case TargetLowering::TypeSoftenFloat: 200 // Promote the integer operand by hand. 201 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); 202 case TargetLowering::TypeExpandInteger: 203 case TargetLowering::TypeExpandFloat: 204 break; 205 case TargetLowering::TypeScalarizeVector: 206 // Convert the element to an integer and promote it by hand. 207 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 208 BitConvertToInteger(GetScalarizedVector(InOp))); 209 case TargetLowering::TypeSplitVector: { 210 // For example, i32 = BITCAST v2i16 on alpha. Convert the split 211 // pieces of the input into integers and reassemble in the final type. 212 SDValue Lo, Hi; 213 GetSplitVector(N->getOperand(0), Lo, Hi); 214 Lo = BitConvertToInteger(Lo); 215 Hi = BitConvertToInteger(Hi); 216 217 if (TLI.isBigEndian()) 218 std::swap(Lo, Hi); 219 220 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, 221 EVT::getIntegerVT(*DAG.getContext(), 222 NOutVT.getSizeInBits()), 223 JoinIntegers(Lo, Hi)); 224 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); 225 } 226 case TargetLowering::TypeWidenVector: 227 if (OutVT.bitsEq(NInVT)) 228 // The input is widened to the same size. Convert to the widened value. 229 return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp)); 230 } 231 232 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 233 CreateStackStoreLoad(InOp, OutVT)); 234} 235 236SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 237 SDValue Op = GetPromotedInteger(N->getOperand(0)); 238 EVT OVT = N->getValueType(0); 239 EVT NVT = Op.getValueType(); 240 DebugLoc dl = N->getDebugLoc(); 241 242 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 243 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 244 DAG.getConstant(DiffBits, TLI.getPointerTy())); 245} 246 247SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 248 // The pair element type may be legal, or may not promote to the same type as 249 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 250 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), 251 TLI.getTypeToTransformTo(*DAG.getContext(), 252 N->getValueType(0)), JoinIntegers(N->getOperand(0), 253 N->getOperand(1))); 254} 255 256SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 257 EVT VT = N->getValueType(0); 258 // FIXME there is no actual debug info here 259 DebugLoc dl = N->getDebugLoc(); 260 // Zero extend things like i1, sign extend everything else. It shouldn't 261 // matter in theory which one we pick, but this tends to give better code? 262 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 263 SDValue Result = DAG.getNode(Opc, dl, 264 TLI.getTypeToTransformTo(*DAG.getContext(), VT), 265 SDValue(N, 0)); 266 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 267 return Result; 268} 269 270SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 271 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 272 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 273 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 274 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 275 "can only promote integers"); 276 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 277 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0), 278 N->getOperand(1), N->getOperand(2), 279 N->getOperand(3), N->getOperand(4), CvtCode); 280} 281 282SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 283 // Zero extend to the promoted type and do the count there. 284 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 285 DebugLoc dl = N->getDebugLoc(); 286 EVT OVT = N->getValueType(0); 287 EVT NVT = Op.getValueType(); 288 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op); 289 // Subtract off the extra leading bits in the bigger type. 290 return DAG.getNode(ISD::SUB, dl, NVT, Op, 291 DAG.getConstant(NVT.getSizeInBits() - 292 OVT.getSizeInBits(), NVT)); 293} 294 295SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 296 // Zero extend to the promoted type and do the count there. 297 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 298 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op); 299} 300 301SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 302 SDValue Op = GetPromotedInteger(N->getOperand(0)); 303 EVT OVT = N->getValueType(0); 304 EVT NVT = Op.getValueType(); 305 DebugLoc dl = N->getDebugLoc(); 306 // The count is the same in the promoted type except if the original 307 // value was zero. This can be handled by setting the bit just off 308 // the top of the original type. 309 APInt TopBit(NVT.getSizeInBits(), 0); 310 TopBit.setBit(OVT.getSizeInBits()); 311 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT)); 312 return DAG.getNode(ISD::CTTZ, dl, NVT, Op); 313} 314 315SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 316 DebugLoc dl = N->getDebugLoc(); 317 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 318 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0), 319 N->getOperand(1)); 320} 321 322SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 323 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 324 unsigned NewOpc = N->getOpcode(); 325 DebugLoc dl = N->getDebugLoc(); 326 327 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is 328 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT 329 // and SINT conversions are Custom, there is no way to tell which is 330 // preferable. We choose SINT because that's the right thing on PPC.) 331 if (N->getOpcode() == ISD::FP_TO_UINT && 332 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 333 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) 334 NewOpc = ISD::FP_TO_SINT; 335 336 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); 337 338 // Assert that the converted value fits in the original type. If it doesn't 339 // (eg: because the value being converted is too big), then the result of the 340 // original operation was undefined anyway, so the assert is still correct. 341 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 342 ISD::AssertZext : ISD::AssertSext, dl, 343 NVT, Res, DAG.getValueType(N->getValueType(0))); 344} 345 346SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) { 347 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 348 DebugLoc dl = N->getDebugLoc(); 349 350 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 351 352 return DAG.getNode(ISD::AssertZext, dl, 353 NVT, Res, DAG.getValueType(N->getValueType(0))); 354} 355 356SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 357 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 358 DebugLoc dl = N->getDebugLoc(); 359 360 if (getTypeAction(N->getOperand(0).getValueType()) 361 == TargetLowering::TypePromoteInteger) { 362 SDValue Res = GetPromotedInteger(N->getOperand(0)); 363 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 364 365 // If the result and operand types are the same after promotion, simplify 366 // to an in-register extension. 367 if (NVT == Res.getValueType()) { 368 // The high bits are not guaranteed to be anything. Insert an extend. 369 if (N->getOpcode() == ISD::SIGN_EXTEND) 370 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 371 DAG.getValueType(N->getOperand(0).getValueType())); 372 if (N->getOpcode() == ISD::ZERO_EXTEND) 373 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType()); 374 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 375 return Res; 376 } 377 } 378 379 // Otherwise, just extend the original operand all the way to the larger type. 380 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 381} 382 383SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 384 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 385 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 386 ISD::LoadExtType ExtType = 387 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 388 DebugLoc dl = N->getDebugLoc(); 389 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), 390 N->getPointerInfo(), 391 N->getMemoryVT(), N->isVolatile(), 392 N->isNonTemporal(), N->getAlignment()); 393 394 // Legalized the chain result - switch anything that used the old chain to 395 // use the new one. 396 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 397 return Res; 398} 399 400/// Promote the overflow flag of an overflowing arithmetic node. 401SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { 402 // Simply change the return type of the boolean result. 403 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1)); 404 EVT ValueVTs[] = { N->getValueType(0), NVT }; 405 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) }; 406 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), 407 DAG.getVTList(ValueVTs, 2), Ops, 2); 408 409 // Modified the sum result - switch anything that used the old sum to use 410 // the new one. 411 ReplaceValueWith(SDValue(N, 0), Res); 412 413 return SDValue(Res.getNode(), 1); 414} 415 416SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { 417 if (ResNo == 1) 418 return PromoteIntRes_Overflow(N); 419 420 // The operation overflowed iff the result in the larger type is not the 421 // sign extension of its truncation to the original type. 422 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 423 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 424 EVT OVT = N->getOperand(0).getValueType(); 425 EVT NVT = LHS.getValueType(); 426 DebugLoc dl = N->getDebugLoc(); 427 428 // Do the arithmetic in the larger type. 429 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 430 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 431 432 // Calculate the overflow flag: sign extend the arithmetic result from 433 // the original type. 434 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 435 DAG.getValueType(OVT)); 436 // Overflowed if and only if this is not equal to Res. 437 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 438 439 // Use the calculated overflow everywhere. 440 ReplaceValueWith(SDValue(N, 1), Ofl); 441 442 return Res; 443} 444 445SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 446 // Sign extend the input. 447 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 448 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 449 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 450 LHS.getValueType(), LHS, RHS); 451} 452 453SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 454 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 455 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 456 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 457 LHS.getValueType(), N->getOperand(0),LHS,RHS); 458} 459 460SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 461 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 462 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 463 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 464 LHS.getValueType(), N->getOperand(0), 465 N->getOperand(1), LHS, RHS, N->getOperand(4)); 466} 467 468SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 469 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); 470 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 471 DebugLoc dl = N->getDebugLoc(); 472 473 // Get the SETCC result using the canonical SETCC type. 474 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0), 475 N->getOperand(1), N->getOperand(2)); 476 477 // Convert to the expected type. 478 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 479 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 480 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 481} 482 483SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 484 return DAG.getNode(ISD::SHL, N->getDebugLoc(), 485 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)), 486 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 487} 488 489SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 490 SDValue Op = GetPromotedInteger(N->getOperand(0)); 491 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), 492 Op.getValueType(), Op, N->getOperand(1)); 493} 494 495SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 496 // The input may have strange things in the top bits of the registers, but 497 // these operations don't care. They may have weird bits going out, but 498 // that too is okay if they are integer operations. 499 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 500 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 501 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 502 LHS.getValueType(), LHS, RHS); 503} 504 505SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 506 // The input value must be properly sign extended. 507 SDValue Res = SExtPromotedInteger(N->getOperand(0)); 508 return DAG.getNode(ISD::SRA, N->getDebugLoc(), 509 Res.getValueType(), Res, N->getOperand(1)); 510} 511 512SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 513 // The input value must be properly zero extended. 514 EVT VT = N->getValueType(0); 515 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 516 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 517 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1)); 518} 519 520SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 521 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 522 SDValue Res; 523 524 switch (getTypeAction(N->getOperand(0).getValueType())) { 525 default: llvm_unreachable("Unknown type action!"); 526 case TargetLowering::TypeLegal: 527 case TargetLowering::TypeExpandInteger: 528 Res = N->getOperand(0); 529 break; 530 case TargetLowering::TypePromoteInteger: 531 Res = GetPromotedInteger(N->getOperand(0)); 532 break; 533 } 534 535 // Truncate to NVT instead of VT 536 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res); 537} 538 539SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) { 540 if (ResNo == 1) 541 return PromoteIntRes_Overflow(N); 542 543 // The operation overflowed iff the result in the larger type is not the 544 // zero extension of its truncation to the original type. 545 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 546 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 547 EVT OVT = N->getOperand(0).getValueType(); 548 EVT NVT = LHS.getValueType(); 549 DebugLoc dl = N->getDebugLoc(); 550 551 // Do the arithmetic in the larger type. 552 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 553 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 554 555 // Calculate the overflow flag: zero extend the arithmetic result from 556 // the original type. 557 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); 558 // Overflowed if and only if this is not equal to Res. 559 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 560 561 // Use the calculated overflow everywhere. 562 ReplaceValueWith(SDValue(N, 1), Ofl); 563 564 return Res; 565} 566 567SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) { 568 // Promote the overflow bit trivially. 569 if (ResNo == 1) 570 return PromoteIntRes_Overflow(N); 571 572 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1); 573 DebugLoc DL = N->getDebugLoc(); 574 EVT SmallVT = LHS.getValueType(); 575 576 // To determine if the result overflowed in a larger type, we extend the input 577 // to the larger type, do the multiply, then check the high bits of the result 578 // to see if the overflow happened. 579 if (N->getOpcode() == ISD::SMULO) { 580 LHS = SExtPromotedInteger(LHS); 581 RHS = SExtPromotedInteger(RHS); 582 } else { 583 LHS = ZExtPromotedInteger(LHS); 584 RHS = ZExtPromotedInteger(RHS); 585 } 586 SDValue Mul = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS); 587 588 // Overflow occurred iff the high part of the result does not zero/sign-extend 589 // the low part. 590 SDValue Overflow; 591 if (N->getOpcode() == ISD::UMULO) { 592 // Unsigned overflow occurred iff the high part is non-zero. 593 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, 594 DAG.getIntPtrConstant(SmallVT.getSizeInBits())); 595 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi, 596 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE); 597 } else { 598 // Signed overflow occurred iff the high part does not sign extend the low. 599 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), 600 Mul, DAG.getValueType(SmallVT)); 601 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE); 602 } 603 604 // Use the calculated overflow everywhere. 605 ReplaceValueWith(SDValue(N, 1), Overflow); 606 return Mul; 607} 608 609SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 610 // Zero extend the input. 611 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 612 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 613 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 614 LHS.getValueType(), LHS, RHS); 615} 616 617SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 618 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(), 619 N->getValueType(0))); 620} 621 622SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 623 SDValue Chain = N->getOperand(0); // Get the chain. 624 SDValue Ptr = N->getOperand(1); // Get the pointer. 625 EVT VT = N->getValueType(0); 626 DebugLoc dl = N->getDebugLoc(); 627 628 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); 629 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT); 630 // The argument is passed as NumRegs registers of type RegVT. 631 632 SmallVector<SDValue, 8> Parts(NumRegs); 633 for (unsigned i = 0; i < NumRegs; ++i) { 634 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), 635 N->getConstantOperandVal(3)); 636 Chain = Parts[i].getValue(1); 637 } 638 639 // Handle endianness of the load. 640 if (TLI.isBigEndian()) 641 std::reverse(Parts.begin(), Parts.end()); 642 643 // Assemble the parts in the promoted type. 644 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 645 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); 646 for (unsigned i = 1; i < NumRegs; ++i) { 647 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); 648 // Shift it to the right position and "or" it in. 649 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, 650 DAG.getConstant(i * RegVT.getSizeInBits(), 651 TLI.getPointerTy())); 652 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part); 653 } 654 655 // Modified the chain result - switch anything that used the old chain to 656 // use the new one. 657 ReplaceValueWith(SDValue(N, 1), Chain); 658 659 return Res; 660} 661 662//===----------------------------------------------------------------------===// 663// Integer Operand Promotion 664//===----------------------------------------------------------------------===// 665 666/// PromoteIntegerOperand - This method is called when the specified operand of 667/// the specified node is found to need promotion. At this point, all of the 668/// result types of the node are known to be legal, but other operands of the 669/// node may need promotion or expansion as well as the specified one. 670bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 671 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n"); 672 SDValue Res = SDValue(); 673 674 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 675 return false; 676 677 switch (N->getOpcode()) { 678 default: 679 #ifndef NDEBUG 680 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": "; 681 N->dump(&DAG); dbgs() << "\n"; 682 #endif 683 llvm_unreachable("Do not know how to promote this operator's operand!"); 684 685 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 686 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break; 687 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 688 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 689 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 690 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 691 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; 692 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break; 693 case ISD::CONVERT_RNDSAT: 694 Res = PromoteIntOp_CONVERT_RNDSAT(N); break; 695 case ISD::INSERT_VECTOR_ELT: 696 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 697 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 698 case ISD::SCALAR_TO_VECTOR: 699 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break; 700 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 701 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 702 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 703 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 704 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; 705 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 706 OpNo); break; 707 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 708 case ISD::FP16_TO_FP32: 709 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; 710 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 711 712 case ISD::SHL: 713 case ISD::SRA: 714 case ISD::SRL: 715 case ISD::ROTL: 716 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break; 717 } 718 719 // If the result is null, the sub-method took care of registering results etc. 720 if (!Res.getNode()) return false; 721 722 // If the result is N, the sub-method updated N in place. Tell the legalizer 723 // core about this. 724 if (Res.getNode() == N) 725 return true; 726 727 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 728 "Invalid operand expansion"); 729 730 ReplaceValueWith(SDValue(N, 0), Res); 731 return false; 732} 733 734/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 735/// shared among BR_CC, SELECT_CC, and SETCC handlers. 736void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 737 ISD::CondCode CCCode) { 738 // We have to insert explicit sign or zero extends. Note that we could 739 // insert sign extends for ALL conditions, but zero extend is cheaper on 740 // many machines (an AND instead of two shifts), so prefer it. 741 switch (CCCode) { 742 default: llvm_unreachable("Unknown integer comparison!"); 743 case ISD::SETEQ: 744 case ISD::SETNE: 745 case ISD::SETUGE: 746 case ISD::SETUGT: 747 case ISD::SETULE: 748 case ISD::SETULT: 749 // ALL of these operations will work if we either sign or zero extend 750 // the operands (including the unsigned comparisons!). Zero extend is 751 // usually a simpler/cheaper operation, so prefer it. 752 NewLHS = ZExtPromotedInteger(NewLHS); 753 NewRHS = ZExtPromotedInteger(NewRHS); 754 break; 755 case ISD::SETGE: 756 case ISD::SETGT: 757 case ISD::SETLT: 758 case ISD::SETLE: 759 NewLHS = SExtPromotedInteger(NewLHS); 760 NewRHS = SExtPromotedInteger(NewRHS); 761 break; 762 } 763} 764 765SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 766 SDValue Op = GetPromotedInteger(N->getOperand(0)); 767 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); 768} 769 770SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) { 771 // This should only occur in unusual situations like bitcasting to an 772 // x86_fp80, so just turn it into a store+load 773 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0)); 774} 775 776SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 777 assert(OpNo == 2 && "Don't know how to promote this operand!"); 778 779 SDValue LHS = N->getOperand(2); 780 SDValue RHS = N->getOperand(3); 781 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 782 783 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 784 // legal types. 785 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 786 N->getOperand(1), LHS, RHS, N->getOperand(4)), 787 0); 788} 789 790SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 791 assert(OpNo == 1 && "only know how to promote condition"); 792 793 // Promote all the way up to the canonical SetCC type. 794 EVT SVT = TLI.getSetCCResultType(MVT::Other); 795 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT); 796 797 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 798 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond, 799 N->getOperand(2)), 0); 800} 801 802SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 803 // Since the result type is legal, the operands must promote to it. 804 EVT OVT = N->getOperand(0).getValueType(); 805 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); 806 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 807 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 808 DebugLoc dl = N->getDebugLoc(); 809 810 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, 811 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy())); 812 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); 813} 814 815SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 816 // The vector type is legal but the element type is not. This implies 817 // that the vector is a power-of-two in length and that the element 818 // type does not have a strange size (eg: it is not i1). 819 EVT VecVT = N->getValueType(0); 820 unsigned NumElts = VecVT.getVectorNumElements(); 821 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 822 823 // Promote the inserted value. The type does not need to match the 824 // vector element type. Check that any extra bits introduced will be 825 // truncated away. 826 assert(N->getOperand(0).getValueType().getSizeInBits() >= 827 N->getValueType(0).getVectorElementType().getSizeInBits() && 828 "Type of inserted value narrower than vector element type!"); 829 830 SmallVector<SDValue, 16> NewOps; 831 for (unsigned i = 0; i < NumElts; ++i) 832 NewOps.push_back(GetPromotedInteger(N->getOperand(i))); 833 834 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0); 835} 836 837SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { 838 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 839 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 840 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 841 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && 842 "can only promote integer arguments"); 843 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 844 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp, 845 N->getOperand(1), N->getOperand(2), 846 N->getOperand(3), N->getOperand(4), CvtCode); 847} 848 849SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 850 unsigned OpNo) { 851 if (OpNo == 1) { 852 // Promote the inserted value. This is valid because the type does not 853 // have to match the vector element type. 854 855 // Check that any extra bits introduced will be truncated away. 856 assert(N->getOperand(1).getValueType().getSizeInBits() >= 857 N->getValueType(0).getVectorElementType().getSizeInBits() && 858 "Type of inserted value narrower than vector element type!"); 859 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 860 GetPromotedInteger(N->getOperand(1)), 861 N->getOperand(2)), 862 0); 863 } 864 865 assert(OpNo == 2 && "Different operand and result vector types?"); 866 867 // Promote the index. 868 SDValue Idx = ZExtPromotedInteger(N->getOperand(2)); 869 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 870 N->getOperand(1), Idx), 0); 871} 872 873SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 874 SDValue NewOps[6]; 875 DebugLoc dl = N->getDebugLoc(); 876 NewOps[0] = N->getOperand(0); 877 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 878 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 879 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1); 880 } 881 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0); 882} 883 884SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) { 885 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote 886 // the operand in place. 887 return SDValue(DAG.UpdateNodeOperands(N, 888 GetPromotedInteger(N->getOperand(0))), 0); 889} 890 891SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 892 assert(OpNo == 0 && "Only know how to promote condition"); 893 894 // Promote all the way up to the canonical SetCC type. 895 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType()); 896 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT); 897 898 return SDValue(DAG.UpdateNodeOperands(N, Cond, 899 N->getOperand(1), N->getOperand(2)), 0); 900} 901 902SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 903 assert(OpNo == 0 && "Don't know how to promote this operand!"); 904 905 SDValue LHS = N->getOperand(0); 906 SDValue RHS = N->getOperand(1); 907 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 908 909 // The CC (#4) and the possible return values (#2 and #3) have legal types. 910 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2), 911 N->getOperand(3), N->getOperand(4)), 0); 912} 913 914SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 915 assert(OpNo == 0 && "Don't know how to promote this operand!"); 916 917 SDValue LHS = N->getOperand(0); 918 SDValue RHS = N->getOperand(1); 919 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 920 921 // The CC (#2) is always legal. 922 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0); 923} 924 925SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) { 926 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 927 ZExtPromotedInteger(N->getOperand(1))), 0); 928} 929 930SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 931 SDValue Op = GetPromotedInteger(N->getOperand(0)); 932 DebugLoc dl = N->getDebugLoc(); 933 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 934 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), 935 Op, DAG.getValueType(N->getOperand(0).getValueType())); 936} 937 938SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) { 939 return SDValue(DAG.UpdateNodeOperands(N, 940 SExtPromotedInteger(N->getOperand(0))), 0); 941} 942 943SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 944 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 945 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 946 unsigned Alignment = N->getAlignment(); 947 bool isVolatile = N->isVolatile(); 948 bool isNonTemporal = N->isNonTemporal(); 949 DebugLoc dl = N->getDebugLoc(); 950 951 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 952 953 // Truncate the value and store the result. 954 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(), 955 N->getMemoryVT(), 956 isVolatile, isNonTemporal, Alignment); 957} 958 959SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 960 SDValue Op = GetPromotedInteger(N->getOperand(0)); 961 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op); 962} 963 964SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { 965 return SDValue(DAG.UpdateNodeOperands(N, 966 ZExtPromotedInteger(N->getOperand(0))), 0); 967} 968 969SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 970 DebugLoc dl = N->getDebugLoc(); 971 SDValue Op = GetPromotedInteger(N->getOperand(0)); 972 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 973 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType()); 974} 975 976 977//===----------------------------------------------------------------------===// 978// Integer Result Expansion 979//===----------------------------------------------------------------------===// 980 981/// ExpandIntegerResult - This method is called when the specified result of the 982/// specified node is found to need expansion. At this point, the node may also 983/// have invalid operands or may have other results that need promotion, we just 984/// know that (at least) one result needs expansion. 985void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 986 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n"); 987 SDValue Lo, Hi; 988 Lo = Hi = SDValue(); 989 990 // See if the target wants to custom expand this node. 991 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 992 return; 993 994 switch (N->getOpcode()) { 995 default: 996#ifndef NDEBUG 997 dbgs() << "ExpandIntegerResult #" << ResNo << ": "; 998 N->dump(&DAG); dbgs() << "\n"; 999#endif 1000 llvm_unreachable("Do not know how to expand the result of this operator!"); 1001 1002 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 1003 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 1004 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 1005 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 1006 1007 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break; 1008 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 1009 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 1010 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 1011 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 1012 1013 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 1014 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 1015 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 1016 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 1017 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 1018 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 1019 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 1020 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 1021 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 1022 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 1023 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 1024 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 1025 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 1026 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 1027 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 1028 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 1029 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 1030 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 1031 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 1032 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 1033 1034 case ISD::ATOMIC_LOAD_ADD: 1035 case ISD::ATOMIC_LOAD_SUB: 1036 case ISD::ATOMIC_LOAD_AND: 1037 case ISD::ATOMIC_LOAD_OR: 1038 case ISD::ATOMIC_LOAD_XOR: 1039 case ISD::ATOMIC_LOAD_NAND: 1040 case ISD::ATOMIC_LOAD_MIN: 1041 case ISD::ATOMIC_LOAD_MAX: 1042 case ISD::ATOMIC_LOAD_UMIN: 1043 case ISD::ATOMIC_LOAD_UMAX: 1044 case ISD::ATOMIC_SWAP: { 1045 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N); 1046 SplitInteger(Tmp.first, Lo, Hi); 1047 ReplaceValueWith(SDValue(N, 1), Tmp.second); 1048 break; 1049 } 1050 1051 case ISD::AND: 1052 case ISD::OR: 1053 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 1054 1055 case ISD::ADD: 1056 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1057 1058 case ISD::ADDC: 1059 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 1060 1061 case ISD::ADDE: 1062 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 1063 1064 case ISD::SHL: 1065 case ISD::SRA: 1066 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1067 1068 case ISD::SADDO: 1069 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break; 1070 case ISD::UADDO: 1071 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break; 1072 } 1073 1074 // If Lo/Hi is null, the sub-method took care of registering results etc. 1075 if (Lo.getNode()) 1076 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1077} 1078 1079/// Lower an atomic node to the appropriate builtin call. 1080std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) { 1081 unsigned Opc = Node->getOpcode(); 1082 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 1083 RTLIB::Libcall LC; 1084 1085 switch (Opc) { 1086 default: 1087 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 1088 break; 1089 case ISD::ATOMIC_SWAP: 1090 switch (VT.SimpleTy) { 1091 default: llvm_unreachable("Unexpected value type for atomic!"); 1092 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; 1093 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 1094 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; 1095 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; 1096 } 1097 break; 1098 case ISD::ATOMIC_CMP_SWAP: 1099 switch (VT.SimpleTy) { 1100 default: llvm_unreachable("Unexpected value type for atomic!"); 1101 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 1102 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 1103 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 1104 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 1105 } 1106 break; 1107 case ISD::ATOMIC_LOAD_ADD: 1108 switch (VT.SimpleTy) { 1109 default: llvm_unreachable("Unexpected value type for atomic!"); 1110 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 1111 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 1112 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 1113 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 1114 } 1115 break; 1116 case ISD::ATOMIC_LOAD_SUB: 1117 switch (VT.SimpleTy) { 1118 default: llvm_unreachable("Unexpected value type for atomic!"); 1119 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 1120 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 1121 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 1122 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 1123 } 1124 break; 1125 case ISD::ATOMIC_LOAD_AND: 1126 switch (VT.SimpleTy) { 1127 default: llvm_unreachable("Unexpected value type for atomic!"); 1128 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 1129 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 1130 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 1131 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 1132 } 1133 break; 1134 case ISD::ATOMIC_LOAD_OR: 1135 switch (VT.SimpleTy) { 1136 default: llvm_unreachable("Unexpected value type for atomic!"); 1137 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 1138 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 1139 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 1140 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 1141 } 1142 break; 1143 case ISD::ATOMIC_LOAD_XOR: 1144 switch (VT.SimpleTy) { 1145 default: llvm_unreachable("Unexpected value type for atomic!"); 1146 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 1147 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 1148 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 1149 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 1150 } 1151 break; 1152 case ISD::ATOMIC_LOAD_NAND: 1153 switch (VT.SimpleTy) { 1154 default: llvm_unreachable("Unexpected value type for atomic!"); 1155 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 1156 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 1157 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 1158 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 1159 } 1160 break; 1161 } 1162 1163 return ExpandChainLibCall(LC, Node, false); 1164} 1165 1166/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1167/// and the shift amount is a constant 'Amt'. Expand the operation. 1168void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1169 SDValue &Lo, SDValue &Hi) { 1170 DebugLoc DL = N->getDebugLoc(); 1171 // Expand the incoming operand to be shifted, so that we have its parts 1172 SDValue InL, InH; 1173 GetExpandedInteger(N->getOperand(0), InL, InH); 1174 1175 EVT NVT = InL.getValueType(); 1176 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1177 unsigned NVTBits = NVT.getSizeInBits(); 1178 EVT ShTy = N->getOperand(1).getValueType(); 1179 1180 if (N->getOpcode() == ISD::SHL) { 1181 if (Amt > VTBits) { 1182 Lo = Hi = DAG.getConstant(0, NVT); 1183 } else if (Amt > NVTBits) { 1184 Lo = DAG.getConstant(0, NVT); 1185 Hi = DAG.getNode(ISD::SHL, DL, 1186 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy)); 1187 } else if (Amt == NVTBits) { 1188 Lo = DAG.getConstant(0, NVT); 1189 Hi = InL; 1190 } else if (Amt == 1 && 1191 TLI.isOperationLegalOrCustom(ISD::ADDC, 1192 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) { 1193 // Emit this X << 1 as X+X. 1194 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue); 1195 SDValue LoOps[2] = { InL, InL }; 1196 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2); 1197 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1198 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3); 1199 } else { 1200 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1201 Hi = DAG.getNode(ISD::OR, DL, NVT, 1202 DAG.getNode(ISD::SHL, DL, NVT, InH, 1203 DAG.getConstant(Amt, ShTy)), 1204 DAG.getNode(ISD::SRL, DL, NVT, InL, 1205 DAG.getConstant(NVTBits-Amt, ShTy))); 1206 } 1207 return; 1208 } 1209 1210 if (N->getOpcode() == ISD::SRL) { 1211 if (Amt > VTBits) { 1212 Lo = DAG.getConstant(0, NVT); 1213 Hi = DAG.getConstant(0, NVT); 1214 } else if (Amt > NVTBits) { 1215 Lo = DAG.getNode(ISD::SRL, DL, 1216 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1217 Hi = DAG.getConstant(0, NVT); 1218 } else if (Amt == NVTBits) { 1219 Lo = InH; 1220 Hi = DAG.getConstant(0, NVT); 1221 } else { 1222 Lo = DAG.getNode(ISD::OR, DL, NVT, 1223 DAG.getNode(ISD::SRL, DL, NVT, InL, 1224 DAG.getConstant(Amt, ShTy)), 1225 DAG.getNode(ISD::SHL, DL, NVT, InH, 1226 DAG.getConstant(NVTBits-Amt, ShTy))); 1227 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1228 } 1229 return; 1230 } 1231 1232 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1233 if (Amt > VTBits) { 1234 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, 1235 DAG.getConstant(NVTBits-1, ShTy)); 1236 } else if (Amt > NVTBits) { 1237 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, 1238 DAG.getConstant(Amt-NVTBits, ShTy)); 1239 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, 1240 DAG.getConstant(NVTBits-1, ShTy)); 1241 } else if (Amt == NVTBits) { 1242 Lo = InH; 1243 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, 1244 DAG.getConstant(NVTBits-1, ShTy)); 1245 } else { 1246 Lo = DAG.getNode(ISD::OR, DL, NVT, 1247 DAG.getNode(ISD::SRL, DL, NVT, InL, 1248 DAG.getConstant(Amt, ShTy)), 1249 DAG.getNode(ISD::SHL, DL, NVT, InH, 1250 DAG.getConstant(NVTBits-Amt, ShTy))); 1251 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1252 } 1253} 1254 1255/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1256/// this shift based on knowledge of the high bit of the shift amount. If we 1257/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1258/// shift amount. 1259bool DAGTypeLegalizer:: 1260ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1261 SDValue Amt = N->getOperand(1); 1262 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1263 EVT ShTy = Amt.getValueType(); 1264 unsigned ShBits = ShTy.getScalarType().getSizeInBits(); 1265 unsigned NVTBits = NVT.getScalarType().getSizeInBits(); 1266 assert(isPowerOf2_32(NVTBits) && 1267 "Expanded integer type size not a power of two!"); 1268 DebugLoc dl = N->getDebugLoc(); 1269 1270 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1271 APInt KnownZero, KnownOne; 1272 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1273 1274 // If we don't know anything about the high bits, exit. 1275 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1276 return false; 1277 1278 // Get the incoming operand to be shifted. 1279 SDValue InL, InH; 1280 GetExpandedInteger(N->getOperand(0), InL, InH); 1281 1282 // If we know that any of the high bits of the shift amount are one, then we 1283 // can do this as a couple of simple shifts. 1284 if (KnownOne.intersects(HighBitMask)) { 1285 // Mask out the high bit, which we know is set. 1286 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, 1287 DAG.getConstant(~HighBitMask, ShTy)); 1288 1289 switch (N->getOpcode()) { 1290 default: llvm_unreachable("Unknown shift"); 1291 case ISD::SHL: 1292 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1293 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 1294 return true; 1295 case ISD::SRL: 1296 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1297 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 1298 return true; 1299 case ISD::SRA: 1300 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 1301 DAG.getConstant(NVTBits-1, ShTy)); 1302 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 1303 return true; 1304 } 1305 } 1306 1307#if 0 1308 // FIXME: This code is broken for shifts with a zero amount! 1309 // If we know that all of the high bits of the shift amount are zero, then we 1310 // can do this as a couple of simple shifts. 1311 if ((KnownZero & HighBitMask) == HighBitMask) { 1312 // Compute 32-amt. 1313 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1314 DAG.getConstant(NVTBits, ShTy), 1315 Amt); 1316 unsigned Op1, Op2; 1317 switch (N->getOpcode()) { 1318 default: llvm_unreachable("Unknown shift"); 1319 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1320 case ISD::SRL: 1321 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1322 } 1323 1324 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1325 Hi = DAG.getNode(ISD::OR, NVT, 1326 DAG.getNode(Op1, NVT, InH, Amt), 1327 DAG.getNode(Op2, NVT, InL, Amt2)); 1328 return true; 1329 } 1330#endif 1331 1332 return false; 1333} 1334 1335/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift 1336/// of any size. 1337bool DAGTypeLegalizer:: 1338ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1339 SDValue Amt = N->getOperand(1); 1340 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1341 EVT ShTy = Amt.getValueType(); 1342 unsigned NVTBits = NVT.getSizeInBits(); 1343 assert(isPowerOf2_32(NVTBits) && 1344 "Expanded integer type size not a power of two!"); 1345 DebugLoc dl = N->getDebugLoc(); 1346 1347 // Get the incoming operand to be shifted. 1348 SDValue InL, InH; 1349 GetExpandedInteger(N->getOperand(0), InL, InH); 1350 1351 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy); 1352 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode); 1353 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt); 1354 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy), 1355 Amt, NVBitsNode, ISD::SETULT); 1356 1357 SDValue LoS, HiS, LoL, HiL; 1358 switch (N->getOpcode()) { 1359 default: llvm_unreachable("Unknown shift"); 1360 case ISD::SHL: 1361 // Short: ShAmt < NVTBits 1362 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); 1363 HiS = DAG.getNode(ISD::OR, dl, NVT, 1364 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt), 1365 // FIXME: If Amt is zero, the following shift generates an undefined result 1366 // on some architectures. 1367 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack)); 1368 1369 // Long: ShAmt >= NVTBits 1370 LoL = DAG.getConstant(0, NVT); // Lo part is zero. 1371 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part. 1372 1373 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1374 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1375 return true; 1376 case ISD::SRL: 1377 // Short: ShAmt < NVTBits 1378 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); 1379 LoS = DAG.getNode(ISD::OR, dl, NVT, 1380 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1381 // FIXME: If Amt is zero, the following shift generates an undefined result 1382 // on some architectures. 1383 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack)); 1384 1385 // Long: ShAmt >= NVTBits 1386 HiL = DAG.getConstant(0, NVT); // Hi part is zero. 1387 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part. 1388 1389 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1390 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1391 return true; 1392 case ISD::SRA: 1393 // Short: ShAmt < NVTBits 1394 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); 1395 LoS = DAG.getNode(ISD::OR, dl, NVT, 1396 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1397 // FIXME: If Amt is zero, the following shift generates an undefined result 1398 // on some architectures. 1399 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack)); 1400 1401 // Long: ShAmt >= NVTBits 1402 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part. 1403 DAG.getConstant(NVTBits-1, ShTy)); 1404 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part. 1405 1406 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1407 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1408 return true; 1409 } 1410 1411 return false; 1412} 1413 1414void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1415 SDValue &Lo, SDValue &Hi) { 1416 DebugLoc dl = N->getDebugLoc(); 1417 // Expand the subcomponents. 1418 SDValue LHSL, LHSH, RHSL, RHSH; 1419 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1420 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1421 1422 EVT NVT = LHSL.getValueType(); 1423 SDValue LoOps[2] = { LHSL, RHSL }; 1424 SDValue HiOps[3] = { LHSH, RHSH }; 1425 1426 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1427 // them. TODO: Teach operation legalization how to expand unsupported 1428 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1429 // a carry of type MVT::Glue, but there doesn't seem to be any way to 1430 // generate a value of this type in the expanded code sequence. 1431 bool hasCarry = 1432 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? 1433 ISD::ADDC : ISD::SUBC, 1434 TLI.getTypeToExpandTo(*DAG.getContext(), NVT)); 1435 1436 if (hasCarry) { 1437 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue); 1438 if (N->getOpcode() == ISD::ADD) { 1439 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1440 HiOps[2] = Lo.getValue(1); 1441 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1442 } else { 1443 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1444 HiOps[2] = Lo.getValue(1); 1445 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1446 } 1447 return; 1448 } 1449 1450 if (N->getOpcode() == ISD::ADD) { 1451 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); 1452 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); 1453 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0], 1454 ISD::SETULT); 1455 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1, 1456 DAG.getConstant(1, NVT), 1457 DAG.getConstant(0, NVT)); 1458 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1], 1459 ISD::SETULT); 1460 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2, 1461 DAG.getConstant(1, NVT), Carry1); 1462 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); 1463 } else { 1464 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); 1465 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); 1466 SDValue Cmp = 1467 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()), 1468 LoOps[0], LoOps[1], ISD::SETULT); 1469 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, 1470 DAG.getConstant(1, NVT), 1471 DAG.getConstant(0, NVT)); 1472 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); 1473 } 1474} 1475 1476void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1477 SDValue &Lo, SDValue &Hi) { 1478 // Expand the subcomponents. 1479 SDValue LHSL, LHSH, RHSL, RHSH; 1480 DebugLoc dl = N->getDebugLoc(); 1481 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1482 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1483 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue); 1484 SDValue LoOps[2] = { LHSL, RHSL }; 1485 SDValue HiOps[3] = { LHSH, RHSH }; 1486 1487 if (N->getOpcode() == ISD::ADDC) { 1488 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1489 HiOps[2] = Lo.getValue(1); 1490 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1491 } else { 1492 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1493 HiOps[2] = Lo.getValue(1); 1494 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1495 } 1496 1497 // Legalized the flag result - switch anything that used the old flag to 1498 // use the new one. 1499 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1500} 1501 1502void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1503 SDValue &Lo, SDValue &Hi) { 1504 // Expand the subcomponents. 1505 SDValue LHSL, LHSH, RHSL, RHSH; 1506 DebugLoc dl = N->getDebugLoc(); 1507 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1508 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1509 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue); 1510 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1511 SDValue HiOps[3] = { LHSH, RHSH }; 1512 1513 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3); 1514 HiOps[2] = Lo.getValue(1); 1515 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); 1516 1517 // Legalized the flag result - switch anything that used the old flag to 1518 // use the new one. 1519 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1520} 1521 1522void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1523 SDValue &Lo, SDValue &Hi) { 1524 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1525 DebugLoc dl = N->getDebugLoc(); 1526 SDValue Op = N->getOperand(0); 1527 if (Op.getValueType().bitsLE(NVT)) { 1528 // The low part is any extension of the input (which degenerates to a copy). 1529 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op); 1530 Hi = DAG.getUNDEF(NVT); // The high part is undefined. 1531 } else { 1532 // For example, extension of an i48 to an i64. The operand type necessarily 1533 // promotes to the result type, so will end up being expanded too. 1534 assert(getTypeAction(Op.getValueType()) == 1535 TargetLowering::TypePromoteInteger && 1536 "Only know how to promote this result!"); 1537 SDValue Res = GetPromotedInteger(Op); 1538 assert(Res.getValueType() == N->getValueType(0) && 1539 "Operand over promoted?"); 1540 // Split the promoted operand. This will simplify when it is expanded. 1541 SplitInteger(Res, Lo, Hi); 1542 } 1543} 1544 1545void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1546 SDValue &Lo, SDValue &Hi) { 1547 DebugLoc dl = N->getDebugLoc(); 1548 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1549 EVT NVT = Lo.getValueType(); 1550 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1551 unsigned NVTBits = NVT.getSizeInBits(); 1552 unsigned EVTBits = EVT.getSizeInBits(); 1553 1554 if (NVTBits < EVTBits) { 1555 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, 1556 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1557 EVTBits - NVTBits))); 1558 } else { 1559 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); 1560 // The high part replicates the sign bit of Lo, make it explicit. 1561 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1562 DAG.getConstant(NVTBits-1, TLI.getPointerTy())); 1563 } 1564} 1565 1566void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1567 SDValue &Lo, SDValue &Hi) { 1568 DebugLoc dl = N->getDebugLoc(); 1569 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1570 EVT NVT = Lo.getValueType(); 1571 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1572 unsigned NVTBits = NVT.getSizeInBits(); 1573 unsigned EVTBits = EVT.getSizeInBits(); 1574 1575 if (NVTBits < EVTBits) { 1576 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, 1577 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1578 EVTBits - NVTBits))); 1579 } else { 1580 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); 1581 // The high part must be zero, make it explicit. 1582 Hi = DAG.getConstant(0, NVT); 1583 } 1584} 1585 1586void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1587 SDValue &Lo, SDValue &Hi) { 1588 DebugLoc dl = N->getDebugLoc(); 1589 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1590 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo); 1591 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi); 1592} 1593 1594void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1595 SDValue &Lo, SDValue &Hi) { 1596 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1597 unsigned NBitWidth = NVT.getSizeInBits(); 1598 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1599 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT); 1600 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1601} 1602 1603void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1604 SDValue &Lo, SDValue &Hi) { 1605 DebugLoc dl = N->getDebugLoc(); 1606 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1607 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1608 EVT NVT = Lo.getValueType(); 1609 1610 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi, 1611 DAG.getConstant(0, NVT), ISD::SETNE); 1612 1613 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo); 1614 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi); 1615 1616 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ, 1617 DAG.getNode(ISD::ADD, dl, NVT, LoLZ, 1618 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1619 Hi = DAG.getConstant(0, NVT); 1620} 1621 1622void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1623 SDValue &Lo, SDValue &Hi) { 1624 DebugLoc dl = N->getDebugLoc(); 1625 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1626 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1627 EVT NVT = Lo.getValueType(); 1628 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), 1629 DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); 1630 Hi = DAG.getConstant(0, NVT); 1631} 1632 1633void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1634 SDValue &Lo, SDValue &Hi) { 1635 DebugLoc dl = N->getDebugLoc(); 1636 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1637 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1638 EVT NVT = Lo.getValueType(); 1639 1640 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, 1641 DAG.getConstant(0, NVT), ISD::SETNE); 1642 1643 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo); 1644 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi); 1645 1646 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ, 1647 DAG.getNode(ISD::ADD, dl, NVT, HiLZ, 1648 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1649 Hi = DAG.getConstant(0, NVT); 1650} 1651 1652void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1653 SDValue &Hi) { 1654 DebugLoc dl = N->getDebugLoc(); 1655 EVT VT = N->getValueType(0); 1656 SDValue Op = N->getOperand(0); 1657 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1658 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1659 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi); 1660} 1661 1662void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1663 SDValue &Hi) { 1664 DebugLoc dl = N->getDebugLoc(); 1665 EVT VT = N->getValueType(0); 1666 SDValue Op = N->getOperand(0); 1667 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1668 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1669 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi); 1670} 1671 1672void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1673 SDValue &Lo, SDValue &Hi) { 1674 if (ISD::isNormalLoad(N)) { 1675 ExpandRes_NormalLoad(N, Lo, Hi); 1676 return; 1677 } 1678 1679 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1680 1681 EVT VT = N->getValueType(0); 1682 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1683 SDValue Ch = N->getChain(); 1684 SDValue Ptr = N->getBasePtr(); 1685 ISD::LoadExtType ExtType = N->getExtensionType(); 1686 unsigned Alignment = N->getAlignment(); 1687 bool isVolatile = N->isVolatile(); 1688 bool isNonTemporal = N->isNonTemporal(); 1689 DebugLoc dl = N->getDebugLoc(); 1690 1691 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1692 1693 if (N->getMemoryVT().bitsLE(NVT)) { 1694 EVT MemVT = N->getMemoryVT(); 1695 1696 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), 1697 MemVT, isVolatile, isNonTemporal, Alignment); 1698 1699 // Remember the chain. 1700 Ch = Lo.getValue(1); 1701 1702 if (ExtType == ISD::SEXTLOAD) { 1703 // The high part is obtained by SRA'ing all but one of the bits of the 1704 // lo part. 1705 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1706 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1707 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1708 } else if (ExtType == ISD::ZEXTLOAD) { 1709 // The high part is just a zero. 1710 Hi = DAG.getConstant(0, NVT); 1711 } else { 1712 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1713 // The high part is undefined. 1714 Hi = DAG.getUNDEF(NVT); 1715 } 1716 } else if (TLI.isLittleEndian()) { 1717 // Little-endian - low bits are at low addresses. 1718 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(), 1719 isVolatile, isNonTemporal, Alignment); 1720 1721 unsigned ExcessBits = 1722 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1723 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits); 1724 1725 // Increment the pointer to the other half. 1726 unsigned IncrementSize = NVT.getSizeInBits()/8; 1727 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1728 DAG.getIntPtrConstant(IncrementSize)); 1729 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, 1730 N->getPointerInfo().getWithOffset(IncrementSize), NEVT, 1731 isVolatile, isNonTemporal, 1732 MinAlign(Alignment, IncrementSize)); 1733 1734 // Build a factor node to remember that this load is independent of the 1735 // other one. 1736 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1737 Hi.getValue(1)); 1738 } else { 1739 // Big-endian - high bits are at low addresses. Favor aligned loads at 1740 // the cost of some bit-fiddling. 1741 EVT MemVT = N->getMemoryVT(); 1742 unsigned EBytes = MemVT.getStoreSize(); 1743 unsigned IncrementSize = NVT.getSizeInBits()/8; 1744 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1745 1746 // Load both the high bits and maybe some of the low bits. 1747 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), 1748 EVT::getIntegerVT(*DAG.getContext(), 1749 MemVT.getSizeInBits() - ExcessBits), 1750 isVolatile, isNonTemporal, Alignment); 1751 1752 // Increment the pointer to the other half. 1753 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1754 DAG.getIntPtrConstant(IncrementSize)); 1755 // Load the rest of the low bits. 1756 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, 1757 N->getPointerInfo().getWithOffset(IncrementSize), 1758 EVT::getIntegerVT(*DAG.getContext(), ExcessBits), 1759 isVolatile, isNonTemporal, 1760 MinAlign(Alignment, IncrementSize)); 1761 1762 // Build a factor node to remember that this load is independent of the 1763 // other one. 1764 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1765 Hi.getValue(1)); 1766 1767 if (ExcessBits < NVT.getSizeInBits()) { 1768 // Transfer low bits from the bottom of Hi to the top of Lo. 1769 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, 1770 DAG.getNode(ISD::SHL, dl, NVT, Hi, 1771 DAG.getConstant(ExcessBits, 1772 TLI.getPointerTy()))); 1773 // Move high bits to the right position in Hi. 1774 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, 1775 NVT, Hi, 1776 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1777 TLI.getPointerTy())); 1778 } 1779 } 1780 1781 // Legalized the chain result - switch anything that used the old chain to 1782 // use the new one. 1783 ReplaceValueWith(SDValue(N, 1), Ch); 1784} 1785 1786void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1787 SDValue &Lo, SDValue &Hi) { 1788 DebugLoc dl = N->getDebugLoc(); 1789 SDValue LL, LH, RL, RH; 1790 GetExpandedInteger(N->getOperand(0), LL, LH); 1791 GetExpandedInteger(N->getOperand(1), RL, RH); 1792 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL); 1793 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); 1794} 1795 1796void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1797 SDValue &Lo, SDValue &Hi) { 1798 EVT VT = N->getValueType(0); 1799 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1800 DebugLoc dl = N->getDebugLoc(); 1801 1802 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); 1803 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); 1804 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); 1805 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); 1806 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1807 SDValue LL, LH, RL, RH; 1808 GetExpandedInteger(N->getOperand(0), LL, LH); 1809 GetExpandedInteger(N->getOperand(1), RL, RH); 1810 unsigned OuterBitSize = VT.getSizeInBits(); 1811 unsigned InnerBitSize = NVT.getSizeInBits(); 1812 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1813 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1814 1815 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1816 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1817 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1818 // The inputs are both zero-extended. 1819 if (HasUMUL_LOHI) { 1820 // We can emit a umul_lohi. 1821 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1822 Hi = SDValue(Lo.getNode(), 1); 1823 return; 1824 } 1825 if (HasMULHU) { 1826 // We can emit a mulhu+mul. 1827 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1828 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1829 return; 1830 } 1831 } 1832 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1833 // The input values are both sign-extended. 1834 if (HasSMUL_LOHI) { 1835 // We can emit a smul_lohi. 1836 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1837 Hi = SDValue(Lo.getNode(), 1); 1838 return; 1839 } 1840 if (HasMULHS) { 1841 // We can emit a mulhs+mul. 1842 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1843 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); 1844 return; 1845 } 1846 } 1847 if (HasUMUL_LOHI) { 1848 // Lo,Hi = umul LHS, RHS. 1849 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, 1850 DAG.getVTList(NVT, NVT), LL, RL); 1851 Lo = UMulLOHI; 1852 Hi = UMulLOHI.getValue(1); 1853 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1854 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1855 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1856 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1857 return; 1858 } 1859 if (HasMULHU) { 1860 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1861 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1862 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1863 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1864 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1865 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1866 return; 1867 } 1868 } 1869 1870 // If nothing else, we can make a libcall. 1871 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1872 if (VT == MVT::i16) 1873 LC = RTLIB::MUL_I16; 1874 else if (VT == MVT::i32) 1875 LC = RTLIB::MUL_I32; 1876 else if (VT == MVT::i64) 1877 LC = RTLIB::MUL_I64; 1878 else if (VT == MVT::i128) 1879 LC = RTLIB::MUL_I128; 1880 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1881 1882 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1883 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi); 1884} 1885 1886void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node, 1887 SDValue &Lo, SDValue &Hi) { 1888 SDValue LHS = Node->getOperand(0); 1889 SDValue RHS = Node->getOperand(1); 1890 DebugLoc dl = Node->getDebugLoc(); 1891 1892 // Expand the result by simply replacing it with the equivalent 1893 // non-overflow-checking operation. 1894 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 1895 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 1896 LHS, RHS); 1897 SplitInteger(Sum, Lo, Hi); 1898 1899 // Compute the overflow. 1900 // 1901 // LHSSign -> LHS >= 0 1902 // RHSSign -> RHS >= 0 1903 // SumSign -> Sum >= 0 1904 // 1905 // Add: 1906 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 1907 // Sub: 1908 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 1909 // 1910 EVT OType = Node->getValueType(1); 1911 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 1912 1913 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 1914 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 1915 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 1916 Node->getOpcode() == ISD::SADDO ? 1917 ISD::SETEQ : ISD::SETNE); 1918 1919 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 1920 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 1921 1922 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 1923 1924 // Use the calculated overflow everywhere. 1925 ReplaceValueWith(SDValue(Node, 1), Cmp); 1926} 1927 1928void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1929 SDValue &Lo, SDValue &Hi) { 1930 EVT VT = N->getValueType(0); 1931 DebugLoc dl = N->getDebugLoc(); 1932 1933 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1934 if (VT == MVT::i16) 1935 LC = RTLIB::SDIV_I16; 1936 else if (VT == MVT::i32) 1937 LC = RTLIB::SDIV_I32; 1938 else if (VT == MVT::i64) 1939 LC = RTLIB::SDIV_I64; 1940 else if (VT == MVT::i128) 1941 LC = RTLIB::SDIV_I128; 1942 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1943 1944 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1945 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1946} 1947 1948void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1949 SDValue &Lo, SDValue &Hi) { 1950 EVT VT = N->getValueType(0); 1951 DebugLoc dl = N->getDebugLoc(); 1952 1953 // If we can emit an efficient shift operation, do so now. Check to see if 1954 // the RHS is a constant. 1955 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1956 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1957 1958 // If we can determine that the high bit of the shift is zero or one, even if 1959 // the low bits are variable, emit this shift in an optimized form. 1960 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1961 return; 1962 1963 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1964 unsigned PartsOpc; 1965 if (N->getOpcode() == ISD::SHL) { 1966 PartsOpc = ISD::SHL_PARTS; 1967 } else if (N->getOpcode() == ISD::SRL) { 1968 PartsOpc = ISD::SRL_PARTS; 1969 } else { 1970 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1971 PartsOpc = ISD::SRA_PARTS; 1972 } 1973 1974 // Next check to see if the target supports this SHL_PARTS operation or if it 1975 // will custom expand it. 1976 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1977 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1978 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1979 Action == TargetLowering::Custom) { 1980 // Expand the subcomponents. 1981 SDValue LHSL, LHSH; 1982 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1983 1984 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1985 EVT VT = LHSL.getValueType(); 1986 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3); 1987 Hi = Lo.getValue(1); 1988 return; 1989 } 1990 1991 // Otherwise, emit a libcall. 1992 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1993 bool isSigned; 1994 if (N->getOpcode() == ISD::SHL) { 1995 isSigned = false; /*sign irrelevant*/ 1996 if (VT == MVT::i16) 1997 LC = RTLIB::SHL_I16; 1998 else if (VT == MVT::i32) 1999 LC = RTLIB::SHL_I32; 2000 else if (VT == MVT::i64) 2001 LC = RTLIB::SHL_I64; 2002 else if (VT == MVT::i128) 2003 LC = RTLIB::SHL_I128; 2004 } else if (N->getOpcode() == ISD::SRL) { 2005 isSigned = false; 2006 if (VT == MVT::i16) 2007 LC = RTLIB::SRL_I16; 2008 else if (VT == MVT::i32) 2009 LC = RTLIB::SRL_I32; 2010 else if (VT == MVT::i64) 2011 LC = RTLIB::SRL_I64; 2012 else if (VT == MVT::i128) 2013 LC = RTLIB::SRL_I128; 2014 } else { 2015 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 2016 isSigned = true; 2017 if (VT == MVT::i16) 2018 LC = RTLIB::SRA_I16; 2019 else if (VT == MVT::i32) 2020 LC = RTLIB::SRA_I32; 2021 else if (VT == MVT::i64) 2022 LC = RTLIB::SRA_I64; 2023 else if (VT == MVT::i128) 2024 LC = RTLIB::SRA_I128; 2025 } 2026 2027 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) { 2028 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2029 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi); 2030 return; 2031 } 2032 2033 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi)) 2034 llvm_unreachable("Unsupported shift!"); 2035} 2036 2037void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 2038 SDValue &Lo, SDValue &Hi) { 2039 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2040 DebugLoc dl = N->getDebugLoc(); 2041 SDValue Op = N->getOperand(0); 2042 if (Op.getValueType().bitsLE(NVT)) { 2043 // The low part is sign extension of the input (degenerates to a copy). 2044 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); 2045 // The high part is obtained by SRA'ing all but one of the bits of low part. 2046 unsigned LoSize = NVT.getSizeInBits(); 2047 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 2048 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 2049 } else { 2050 // For example, extension of an i48 to an i64. The operand type necessarily 2051 // promotes to the result type, so will end up being expanded too. 2052 assert(getTypeAction(Op.getValueType()) == 2053 TargetLowering::TypePromoteInteger && 2054 "Only know how to promote this result!"); 2055 SDValue Res = GetPromotedInteger(Op); 2056 assert(Res.getValueType() == N->getValueType(0) && 2057 "Operand over promoted?"); 2058 // Split the promoted operand. This will simplify when it is expanded. 2059 SplitInteger(Res, Lo, Hi); 2060 unsigned ExcessBits = 2061 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 2062 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 2063 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 2064 ExcessBits))); 2065 } 2066} 2067 2068void DAGTypeLegalizer:: 2069ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 2070 DebugLoc dl = N->getDebugLoc(); 2071 GetExpandedInteger(N->getOperand(0), Lo, Hi); 2072 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2073 2074 if (EVT.bitsLE(Lo.getValueType())) { 2075 // sext_inreg the low part if needed. 2076 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, 2077 N->getOperand(1)); 2078 2079 // The high part gets the sign extension from the lo-part. This handles 2080 // things like sextinreg V:i64 from i8. 2081 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo, 2082 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 2083 TLI.getPointerTy())); 2084 } else { 2085 // For example, extension of an i48 to an i64. Leave the low part alone, 2086 // sext_inreg the high part. 2087 unsigned ExcessBits = 2088 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 2089 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 2090 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 2091 ExcessBits))); 2092 } 2093} 2094 2095void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 2096 SDValue &Lo, SDValue &Hi) { 2097 EVT VT = N->getValueType(0); 2098 DebugLoc dl = N->getDebugLoc(); 2099 2100 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2101 if (VT == MVT::i16) 2102 LC = RTLIB::SREM_I16; 2103 else if (VT == MVT::i32) 2104 LC = RTLIB::SREM_I32; 2105 else if (VT == MVT::i64) 2106 LC = RTLIB::SREM_I64; 2107 else if (VT == MVT::i128) 2108 LC = RTLIB::SREM_I128; 2109 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 2110 2111 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2112 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 2113} 2114 2115void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 2116 SDValue &Lo, SDValue &Hi) { 2117 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2118 DebugLoc dl = N->getDebugLoc(); 2119 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); 2120 Hi = DAG.getNode(ISD::SRL, dl, 2121 N->getOperand(0).getValueType(), N->getOperand(0), 2122 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy())); 2123 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); 2124} 2125 2126void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N, 2127 SDValue &Lo, SDValue &Hi) { 2128 SDValue LHS = N->getOperand(0); 2129 SDValue RHS = N->getOperand(1); 2130 DebugLoc dl = N->getDebugLoc(); 2131 2132 // Expand the result by simply replacing it with the equivalent 2133 // non-overflow-checking operation. 2134 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ? 2135 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2136 LHS, RHS); 2137 SplitInteger(Sum, Lo, Hi); 2138 2139 // Calculate the overflow: addition overflows iff a + b < a, and subtraction 2140 // overflows iff a - b > a. 2141 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, 2142 N->getOpcode () == ISD::UADDO ? 2143 ISD::SETULT : ISD::SETUGT); 2144 2145 // Use the calculated overflow everywhere. 2146 ReplaceValueWith(SDValue(N, 1), Ofl); 2147} 2148 2149void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 2150 SDValue &Lo, SDValue &Hi) { 2151 EVT VT = N->getValueType(0); 2152 DebugLoc dl = N->getDebugLoc(); 2153 2154 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2155 if (VT == MVT::i16) 2156 LC = RTLIB::UDIV_I16; 2157 else if (VT == MVT::i32) 2158 LC = RTLIB::UDIV_I32; 2159 else if (VT == MVT::i64) 2160 LC = RTLIB::UDIV_I64; 2161 else if (VT == MVT::i128) 2162 LC = RTLIB::UDIV_I128; 2163 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 2164 2165 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2166 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 2167} 2168 2169void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 2170 SDValue &Lo, SDValue &Hi) { 2171 EVT VT = N->getValueType(0); 2172 DebugLoc dl = N->getDebugLoc(); 2173 2174 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2175 if (VT == MVT::i16) 2176 LC = RTLIB::UREM_I16; 2177 else if (VT == MVT::i32) 2178 LC = RTLIB::UREM_I32; 2179 else if (VT == MVT::i64) 2180 LC = RTLIB::UREM_I64; 2181 else if (VT == MVT::i128) 2182 LC = RTLIB::UREM_I128; 2183 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 2184 2185 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2186 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 2187} 2188 2189void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 2190 SDValue &Lo, SDValue &Hi) { 2191 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2192 DebugLoc dl = N->getDebugLoc(); 2193 SDValue Op = N->getOperand(0); 2194 if (Op.getValueType().bitsLE(NVT)) { 2195 // The low part is zero extension of the input (degenerates to a copy). 2196 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); 2197 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 2198 } else { 2199 // For example, extension of an i48 to an i64. The operand type necessarily 2200 // promotes to the result type, so will end up being expanded too. 2201 assert(getTypeAction(Op.getValueType()) == 2202 TargetLowering::TypePromoteInteger && 2203 "Only know how to promote this result!"); 2204 SDValue Res = GetPromotedInteger(Op); 2205 assert(Res.getValueType() == N->getValueType(0) && 2206 "Operand over promoted?"); 2207 // Split the promoted operand. This will simplify when it is expanded. 2208 SplitInteger(Res, Lo, Hi); 2209 unsigned ExcessBits = 2210 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 2211 Hi = DAG.getZeroExtendInReg(Hi, dl, 2212 EVT::getIntegerVT(*DAG.getContext(), 2213 ExcessBits)); 2214 } 2215} 2216 2217 2218//===----------------------------------------------------------------------===// 2219// Integer Operand Expansion 2220//===----------------------------------------------------------------------===// 2221 2222/// ExpandIntegerOperand - This method is called when the specified operand of 2223/// the specified node is found to need expansion. At this point, all of the 2224/// result types of the node are known to be legal, but other operands of the 2225/// node may need promotion or expansion as well as the specified one. 2226bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 2227 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n"); 2228 SDValue Res = SDValue(); 2229 2230 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 2231 return false; 2232 2233 switch (N->getOpcode()) { 2234 default: 2235 #ifndef NDEBUG 2236 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": "; 2237 N->dump(&DAG); dbgs() << "\n"; 2238 #endif 2239 llvm_unreachable("Do not know how to expand this operator's operand!"); 2240 2241 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break; 2242 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 2243 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 2244 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 2245 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 2246 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; 2247 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 2248 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 2249 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 2250 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break; 2251 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 2252 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 2253 2254 case ISD::SHL: 2255 case ISD::SRA: 2256 case ISD::SRL: 2257 case ISD::ROTL: 2258 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break; 2259 case ISD::RETURNADDR: 2260 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break; 2261 } 2262 2263 // If the result is null, the sub-method took care of registering results etc. 2264 if (!Res.getNode()) return false; 2265 2266 // If the result is N, the sub-method updated N in place. Tell the legalizer 2267 // core about this. 2268 if (Res.getNode() == N) 2269 return true; 2270 2271 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2272 "Invalid operand expansion"); 2273 2274 ReplaceValueWith(SDValue(N, 0), Res); 2275 return false; 2276} 2277 2278/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 2279/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 2280void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 2281 SDValue &NewRHS, 2282 ISD::CondCode &CCCode, 2283 DebugLoc dl) { 2284 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 2285 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 2286 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 2287 2288 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 2289 if (RHSLo == RHSHi) { 2290 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 2291 if (RHSCST->isAllOnesValue()) { 2292 // Equality comparison to -1. 2293 NewLHS = DAG.getNode(ISD::AND, dl, 2294 LHSLo.getValueType(), LHSLo, LHSHi); 2295 NewRHS = RHSLo; 2296 return; 2297 } 2298 } 2299 } 2300 2301 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); 2302 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); 2303 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS); 2304 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2305 return; 2306 } 2307 2308 // If this is a comparison of the sign bit, just look at the top part. 2309 // X > -1, x < 0 2310 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 2311 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 2312 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 2313 NewLHS = LHSHi; 2314 NewRHS = RHSHi; 2315 return; 2316 } 2317 2318 // FIXME: This generated code sucks. 2319 ISD::CondCode LowCC; 2320 switch (CCCode) { 2321 default: llvm_unreachable("Unknown integer setcc!"); 2322 case ISD::SETLT: 2323 case ISD::SETULT: LowCC = ISD::SETULT; break; 2324 case ISD::SETGT: 2325 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2326 case ISD::SETLE: 2327 case ISD::SETULE: LowCC = ISD::SETULE; break; 2328 case ISD::SETGE: 2329 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2330 } 2331 2332 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2333 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2334 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2335 2336 // NOTE: on targets without efficient SELECT of bools, we can always use 2337 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2338 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL); 2339 SDValue Tmp1, Tmp2; 2340 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), 2341 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl); 2342 if (!Tmp1.getNode()) 2343 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 2344 LHSLo, RHSLo, LowCC); 2345 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2346 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl); 2347 if (!Tmp2.getNode()) 2348 Tmp2 = DAG.getNode(ISD::SETCC, dl, 2349 TLI.getSetCCResultType(LHSHi.getValueType()), 2350 LHSHi, RHSHi, DAG.getCondCode(CCCode)); 2351 2352 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2353 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2354 if ((Tmp1C && Tmp1C->isNullValue()) || 2355 (Tmp2C && Tmp2C->isNullValue() && 2356 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2357 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2358 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2359 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2360 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2361 // low part is known false, returns high part. 2362 // For LE / GE, if high part is known false, ignore the low part. 2363 // For LT / GT, if high part is known true, ignore the low part. 2364 NewLHS = Tmp2; 2365 NewRHS = SDValue(); 2366 return; 2367 } 2368 2369 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2370 LHSHi, RHSHi, ISD::SETEQ, false, 2371 DagCombineInfo, dl); 2372 if (!NewLHS.getNode()) 2373 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 2374 LHSHi, RHSHi, ISD::SETEQ); 2375 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), 2376 NewLHS, Tmp1, Tmp2); 2377 NewRHS = SDValue(); 2378} 2379 2380SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2381 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2382 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2383 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2384 2385 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2386 // against zero to select between true and false values. 2387 if (NewRHS.getNode() == 0) { 2388 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2389 CCCode = ISD::SETNE; 2390 } 2391 2392 // Update N to have the operands specified. 2393 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 2394 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2395 N->getOperand(4)), 0); 2396} 2397 2398SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2399 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2400 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2401 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2402 2403 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2404 // against zero to select between true and false values. 2405 if (NewRHS.getNode() == 0) { 2406 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2407 CCCode = ISD::SETNE; 2408 } 2409 2410 // Update N to have the operands specified. 2411 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, 2412 N->getOperand(2), N->getOperand(3), 2413 DAG.getCondCode(CCCode)), 0); 2414} 2415 2416SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2417 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2418 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2419 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2420 2421 // If ExpandSetCCOperands returned a scalar, use it. 2422 if (NewRHS.getNode() == 0) { 2423 assert(NewLHS.getValueType() == N->getValueType(0) && 2424 "Unexpected setcc expansion!"); 2425 return NewLHS; 2426 } 2427 2428 // Otherwise, update N to have the operands specified. 2429 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, 2430 DAG.getCondCode(CCCode)), 0); 2431} 2432 2433SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) { 2434 // The value being shifted is legal, but the shift amount is too big. 2435 // It follows that either the result of the shift is undefined, or the 2436 // upper half of the shift amount is zero. Just use the lower half. 2437 SDValue Lo, Hi; 2438 GetExpandedInteger(N->getOperand(1), Lo, Hi); 2439 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0); 2440} 2441 2442SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) { 2443 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This 2444 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this 2445 // constant to valid type. 2446 SDValue Lo, Hi; 2447 GetExpandedInteger(N->getOperand(0), Lo, Hi); 2448 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0); 2449} 2450 2451SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2452 SDValue Op = N->getOperand(0); 2453 EVT DstVT = N->getValueType(0); 2454 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2455 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2456 "Don't know how to expand this SINT_TO_FP!"); 2457 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc()); 2458} 2459 2460SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2461 if (ISD::isNormalStore(N)) 2462 return ExpandOp_NormalStore(N, OpNo); 2463 2464 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2465 assert(OpNo == 1 && "Can only expand the stored value so far"); 2466 2467 EVT VT = N->getOperand(1).getValueType(); 2468 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2469 SDValue Ch = N->getChain(); 2470 SDValue Ptr = N->getBasePtr(); 2471 unsigned Alignment = N->getAlignment(); 2472 bool isVolatile = N->isVolatile(); 2473 bool isNonTemporal = N->isNonTemporal(); 2474 DebugLoc dl = N->getDebugLoc(); 2475 SDValue Lo, Hi; 2476 2477 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2478 2479 if (N->getMemoryVT().bitsLE(NVT)) { 2480 GetExpandedInteger(N->getValue(), Lo, Hi); 2481 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), 2482 N->getMemoryVT(), isVolatile, isNonTemporal, 2483 Alignment); 2484 } 2485 2486 if (TLI.isLittleEndian()) { 2487 // Little-endian - low bits are at low addresses. 2488 GetExpandedInteger(N->getValue(), Lo, Hi); 2489 2490 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), 2491 isVolatile, isNonTemporal, Alignment); 2492 2493 unsigned ExcessBits = 2494 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2495 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits); 2496 2497 // Increment the pointer to the other half. 2498 unsigned IncrementSize = NVT.getSizeInBits()/8; 2499 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2500 DAG.getIntPtrConstant(IncrementSize)); 2501 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, 2502 N->getPointerInfo().getWithOffset(IncrementSize), 2503 NEVT, isVolatile, isNonTemporal, 2504 MinAlign(Alignment, IncrementSize)); 2505 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2506 } 2507 2508 // Big-endian - high bits are at low addresses. Favor aligned stores at 2509 // the cost of some bit-fiddling. 2510 GetExpandedInteger(N->getValue(), Lo, Hi); 2511 2512 EVT ExtVT = N->getMemoryVT(); 2513 unsigned EBytes = ExtVT.getStoreSize(); 2514 unsigned IncrementSize = NVT.getSizeInBits()/8; 2515 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2516 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(), 2517 ExtVT.getSizeInBits() - ExcessBits); 2518 2519 if (ExcessBits < NVT.getSizeInBits()) { 2520 // Transfer high bits from the top of Lo to the bottom of Hi. 2521 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, 2522 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2523 TLI.getPointerTy())); 2524 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, 2525 DAG.getNode(ISD::SRL, dl, NVT, Lo, 2526 DAG.getConstant(ExcessBits, 2527 TLI.getPointerTy()))); 2528 } 2529 2530 // Store both the high bits and maybe some of the low bits. 2531 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(), 2532 HiVT, isVolatile, isNonTemporal, Alignment); 2533 2534 // Increment the pointer to the other half. 2535 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2536 DAG.getIntPtrConstant(IncrementSize)); 2537 // Store the lowest ExcessBits bits in the second half. 2538 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, 2539 N->getPointerInfo().getWithOffset(IncrementSize), 2540 EVT::getIntegerVT(*DAG.getContext(), ExcessBits), 2541 isVolatile, isNonTemporal, 2542 MinAlign(Alignment, IncrementSize)); 2543 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2544} 2545 2546SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2547 SDValue InL, InH; 2548 GetExpandedInteger(N->getOperand(0), InL, InH); 2549 // Just truncate the low part of the source. 2550 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL); 2551} 2552 2553static const fltSemantics *EVTToAPFloatSemantics(EVT VT) { 2554 switch (VT.getSimpleVT().SimpleTy) { 2555 default: llvm_unreachable("Unknown FP format"); 2556 case MVT::f32: return &APFloat::IEEEsingle; 2557 case MVT::f64: return &APFloat::IEEEdouble; 2558 case MVT::f80: return &APFloat::x87DoubleExtended; 2559 case MVT::f128: return &APFloat::IEEEquad; 2560 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 2561 } 2562} 2563 2564SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2565 SDValue Op = N->getOperand(0); 2566 EVT SrcVT = Op.getValueType(); 2567 EVT DstVT = N->getValueType(0); 2568 DebugLoc dl = N->getDebugLoc(); 2569 2570 // The following optimization is valid only if every value in SrcVT (when 2571 // treated as signed) is representable in DstVT. Check that the mantissa 2572 // size of DstVT is >= than the number of bits in SrcVT -1. 2573 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT); 2574 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 && 2575 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2576 // Do a signed conversion then adjust the result. 2577 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); 2578 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2579 2580 // The result of the signed conversion needs adjusting if the 'sign bit' of 2581 // the incoming integer was set. To handle this, we dynamically test to see 2582 // if it is set, and, if so, add a fudge factor. 2583 2584 const uint64_t F32TwoE32 = 0x4F800000ULL; 2585 const uint64_t F32TwoE64 = 0x5F800000ULL; 2586 const uint64_t F32TwoE128 = 0x7F800000ULL; 2587 2588 APInt FF(32, 0); 2589 if (SrcVT == MVT::i32) 2590 FF = APInt(32, F32TwoE32); 2591 else if (SrcVT == MVT::i64) 2592 FF = APInt(32, F32TwoE64); 2593 else if (SrcVT == MVT::i128) 2594 FF = APInt(32, F32TwoE128); 2595 else 2596 assert(false && "Unsupported UINT_TO_FP!"); 2597 2598 // Check whether the sign bit is set. 2599 SDValue Lo, Hi; 2600 GetExpandedInteger(Op, Lo, Hi); 2601 SDValue SignSet = DAG.getSetCC(dl, 2602 TLI.getSetCCResultType(Hi.getValueType()), 2603 Hi, DAG.getConstant(0, Hi.getValueType()), 2604 ISD::SETLT); 2605 2606 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2607 SDValue FudgePtr = DAG.getConstantPool( 2608 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 2609 TLI.getPointerTy()); 2610 2611 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2612 SDValue Zero = DAG.getIntPtrConstant(0); 2613 SDValue Four = DAG.getIntPtrConstant(4); 2614 if (TLI.isBigEndian()) std::swap(Zero, Four); 2615 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 2616 Zero, Four); 2617 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2618 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset); 2619 Alignment = std::min(Alignment, 4u); 2620 2621 // Load the value out, extending it from f32 to the destination float type. 2622 // FIXME: Avoid the extend by constructing the right constant pool? 2623 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), 2624 FudgePtr, 2625 MachinePointerInfo::getConstantPool(), 2626 MVT::f32, 2627 false, false, Alignment); 2628 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); 2629 } 2630 2631 // Otherwise, use a libcall. 2632 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2633 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2634 "Don't know how to expand this UINT_TO_FP!"); 2635 return MakeLibCall(LC, DstVT, &Op, 1, true, dl); 2636} 2637 2638SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) { 2639 SDValue InOp0 = N->getOperand(0); 2640 EVT InVT = InOp0.getValueType(); 2641 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); 2642 2643 EVT OutVT = N->getValueType(0); 2644 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2645 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2646 unsigned OutNumElems = N->getValueType(0).getVectorNumElements(); 2647 EVT NOutVTElem = NOutVT.getVectorElementType(); 2648 2649 DebugLoc dl = N->getDebugLoc(); 2650 SDValue BaseIdx = N->getOperand(1); 2651 2652 SmallVector<SDValue, 8> Ops; 2653 for (unsigned i = 0; i != OutNumElems; ++i) { 2654 2655 // Extract the element from the original vector. 2656 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(), 2657 BaseIdx, DAG.getIntPtrConstant(i)); 2658 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 2659 InVT.getVectorElementType(), N->getOperand(0), Index); 2660 2661 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext); 2662 // Insert the converted element to the new vector. 2663 Ops.push_back(Op); 2664 } 2665 2666 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size()); 2667} 2668 2669 2670SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) { 2671 2672 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 2673 EVT VT = N->getValueType(0); 2674 DebugLoc dl = N->getDebugLoc(); 2675 2676 unsigned NumElts = VT.getVectorNumElements(); 2677 SmallVector<int, 8> NewMask; 2678 for (unsigned i = 0; i != NumElts; ++i) { 2679 NewMask.push_back(SV->getMaskElt(i)); 2680 } 2681 2682 SDValue V0 = GetPromotedInteger(N->getOperand(0)); 2683 SDValue V1 = GetPromotedInteger(N->getOperand(1)); 2684 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2685 2686 return DAG.getVectorShuffle(OutVT, dl, V0,V1, &NewMask[0]); 2687} 2688 2689 2690SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) { 2691 2692 SDValue InOp0 = N->getOperand(0); 2693 EVT InVT = InOp0.getValueType(); 2694 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); 2695 2696 EVT OutVT = N->getValueType(0); 2697 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2698 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2699 unsigned NumElems = N->getNumOperands(); 2700 EVT NOutVTElem = NOutVT.getVectorElementType(); 2701 2702 DebugLoc dl = N->getDebugLoc(); 2703 2704 SmallVector<SDValue, 8> Ops; 2705 for (unsigned i = 0; i != NumElems; ++i) { 2706 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i)); 2707 Ops.push_back(Op); 2708 } 2709 2710 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size()); 2711} 2712 2713SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) { 2714 2715 DebugLoc dl = N->getDebugLoc(); 2716 2717 SDValue InOp0 = N->getOperand(0); 2718 EVT InVT = InOp0.getValueType(); 2719 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); 2720 assert(!InVT.isVector() && "Input must not be a scalar"); 2721 2722 EVT OutVT = N->getValueType(0); 2723 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2724 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2725 EVT NOutVTElem = NOutVT.getVectorElementType(); 2726 2727 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0)); 2728 2729 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op); 2730} 2731 2732SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) { 2733 2734 SDValue InOp0 = N->getOperand(0); 2735 EVT InVT = InOp0.getValueType(); 2736 EVT InElVT = InVT.getVectorElementType(); 2737 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); 2738 2739 EVT OutVT = N->getValueType(0); 2740 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2741 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2742 2743 EVT NOutVTElem = NOutVT.getVectorElementType(); 2744 2745 DebugLoc dl = N->getDebugLoc(); 2746 2747 SDValue ConvertedVector = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp0); 2748 2749 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl, 2750 NOutVTElem, N->getOperand(1)); 2751 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,NOutVT, 2752 ConvertedVector, ConvElem, N->getOperand(2)); 2753} 2754 2755SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) { 2756 DebugLoc dl = N->getDebugLoc(); 2757 SDValue V0 = GetPromotedInteger(N->getOperand(0)); 2758 SDValue V1 = N->getOperand(1); 2759 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 2760 V0->getValueType(0).getScalarType(), V0, V1); 2761 2762 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext); 2763 2764} 2765 2766SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) { 2767 2768 DebugLoc dl = N->getDebugLoc(); 2769 2770 EVT RetSclrTy = N->getValueType(0).getVectorElementType(); 2771 2772 SmallVector<SDValue, 8> NewOps; 2773 2774 // For each incoming vector 2775 for (unsigned VecIdx = 0, E = N->getNumOperands(); VecIdx!= E; ++VecIdx) { 2776 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx)); 2777 EVT SclrTy = Incoming->getValueType(0).getVectorElementType(); 2778 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements(); 2779 2780 for (unsigned i=0; i<NumElem; ++i) { 2781 // Extract element from incoming vector 2782 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, 2783 Incoming, DAG.getIntPtrConstant(i)); 2784 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex); 2785 NewOps.push_back(Tr); 2786 } 2787 } 2788 2789 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), 2790 &NewOps[0], NewOps.size()); 2791 } 2792 2793