LegalizeVectorTypes.cpp revision 38b7a7cc96b46cee339eebbffb578e9e3945cf79
1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file performs vector type splitting and scalarization for LegalizeTypes. 11// Scalarization is the act of changing a computation in an illegal one-element 12// vector type to be a computation in its scalar element type. For example, 13// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed 14// as a base case when scalarizing vector arithmetic like <4 x f32>, which 15// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32 16// types. 17// Splitting is the act of changing a computation in an invalid vector type to 18// be a computation in multiple vectors of a smaller type. For example, 19// implementing <128 x f32> operations in terms of two <64 x f32> operations. 20// 21//===----------------------------------------------------------------------===// 22 23#include "LegalizeTypes.h" 24using namespace llvm; 25 26//===----------------------------------------------------------------------===// 27// Result Vector Scalarization: <1 x ty> -> ty. 28//===----------------------------------------------------------------------===// 29 30void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { 31 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG); 32 cerr << "\n"); 33 SDOperand R = SDOperand(); 34 35 switch (N->getOpcode()) { 36 default: 37#ifndef NDEBUG 38 cerr << "ScalarizeVectorResult #" << ResNo << ": "; 39 N->dump(&DAG); cerr << "\n"; 40#endif 41 assert(0 && "Do not know how to scalarize the result of this operator!"); 42 abort(); 43 44 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; 45 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N)); break; 46 47 case ISD::ADD: 48 case ISD::FADD: 49 case ISD::SUB: 50 case ISD::FSUB: 51 case ISD::MUL: 52 case ISD::FMUL: 53 case ISD::SDIV: 54 case ISD::UDIV: 55 case ISD::FDIV: 56 case ISD::SREM: 57 case ISD::UREM: 58 case ISD::FREM: 59 case ISD::FPOW: 60 case ISD::AND: 61 case ISD::OR: 62 case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break; 63 64 case ISD::FNEG: 65 case ISD::FABS: 66 case ISD::FSQRT: 67 case ISD::FSIN: 68 case ISD::FCOS: R = ScalarizeVecRes_UnaryOp(N); break; 69 70 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 71 case ISD::BUILD_VECTOR: R = N->getOperand(0); break; 72 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 73 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; 74 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break; 75 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break; 76 } 77 78 // If R is null, the sub-method took care of registering the result. 79 if (R.Val) 80 SetScalarizedVector(SDOperand(N, ResNo), R); 81} 82 83SDOperand DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { 84 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType()); 85} 86 87SDOperand DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { 88 assert(ISD::isNormalLoad(N) && "Extending load of one-element vector?"); 89 SDOperand Result = DAG.getLoad(N->getValueType(0).getVectorElementType(), 90 N->getChain(), N->getBasePtr(), 91 N->getSrcValue(), N->getSrcValueOffset(), 92 N->isVolatile(), N->getAlignment()); 93 94 // Legalized the chain result - switch anything that used the old chain to 95 // use the new one. 96 ReplaceValueWith(SDOperand(N, 1), Result.getValue(1)); 97 return Result; 98} 99 100SDOperand DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { 101 SDOperand LHS = GetScalarizedVector(N->getOperand(0)); 102 SDOperand RHS = GetScalarizedVector(N->getOperand(1)); 103 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 104} 105 106SDOperand DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { 107 SDOperand Op = GetScalarizedVector(N->getOperand(0)); 108 return DAG.getNode(N->getOpcode(), Op.getValueType(), Op); 109} 110 111SDOperand DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) { 112 SDOperand Op = GetScalarizedVector(N->getOperand(0)); 113 return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1)); 114} 115 116SDOperand DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { 117 // The value to insert may have a wider type than the vector element type, 118 // so be sure to truncate it to the element type if necessary. 119 SDOperand Op = N->getOperand(1); 120 MVT EltVT = N->getValueType(0).getVectorElementType(); 121 if (Op.getValueType() != EltVT) 122 // FIXME: Can this happen for floating point types? 123 Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op); 124 return Op; 125} 126 127SDOperand DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { 128 // Figure out if the scalar is the LHS or RHS and return it. 129 SDOperand EltNum = N->getOperand(2).getOperand(0); 130 unsigned Op = cast<ConstantSDNode>(EltNum)->getValue() != 0; 131 return GetScalarizedVector(N->getOperand(Op)); 132} 133 134SDOperand DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) { 135 MVT NewVT = N->getValueType(0).getVectorElementType(); 136 return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0)); 137} 138 139SDOperand DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) { 140 SDOperand LHS = GetScalarizedVector(N->getOperand(1)); 141 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS, 142 GetScalarizedVector(N->getOperand(2))); 143} 144 145 146//===----------------------------------------------------------------------===// 147// Operand Vector Scalarization <1 x ty> -> ty. 148//===----------------------------------------------------------------------===// 149 150bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { 151 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG); 152 cerr << "\n"); 153 SDOperand Res = SDOperand(); 154 155 if (Res.Val == 0) { 156 switch (N->getOpcode()) { 157 default: 158#ifndef NDEBUG 159 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": "; 160 N->dump(&DAG); cerr << "\n"; 161#endif 162 assert(0 && "Do not know how to scalarize this operator's operand!"); 163 abort(); 164 165 case ISD::BIT_CONVERT: 166 Res = ScalarizeVecOp_BIT_CONVERT(N); break; 167 168 case ISD::EXTRACT_VECTOR_ELT: 169 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break; 170 171 case ISD::STORE: 172 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break; 173 } 174 } 175 176 // If the result is null, the sub-method took care of registering results etc. 177 if (!Res.Val) return false; 178 179 // If the result is N, the sub-method updated N in place. Check to see if any 180 // operands are new, and if so, mark them. 181 if (Res.Val == N) { 182 // Mark N as new and remark N and its operands. This allows us to correctly 183 // revisit N if it needs another step of promotion and allows us to visit 184 // any new operands to N. 185 ReanalyzeNode(N); 186 return true; 187 } 188 189 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 190 "Invalid operand expansion"); 191 192 ReplaceValueWith(SDOperand(N, 0), Res); 193 return false; 194} 195 196/// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs 197/// to be scalarized, it must be <1 x ty>. Convert the element instead. 198SDOperand DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) { 199 SDOperand Elt = GetScalarizedVector(N->getOperand(0)); 200 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt); 201} 202 203/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to 204/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the 205/// index. 206SDOperand DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 207 return GetScalarizedVector(N->getOperand(0)); 208} 209 210/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be 211/// scalarized, it must be <1 x ty>. Just store the element. 212SDOperand DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ 213 assert(ISD::isNormalStore(N) && "Truncating store of one-element vector?"); 214 assert(OpNo == 1 && "Do not know how to scalarize this operand!"); 215 return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)), 216 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(), 217 N->isVolatile(), N->getAlignment()); 218} 219 220 221//===----------------------------------------------------------------------===// 222// Result Vector Splitting 223//===----------------------------------------------------------------------===// 224 225/// SplitVectorResult - This method is called when the specified result of the 226/// specified node is found to need vector splitting. At this point, the node 227/// may also have invalid operands or may have other results that need 228/// legalization, we just know that (at least) one result needs vector 229/// splitting. 230void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { 231 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n"); 232 SDOperand Lo, Hi; 233 234 switch (N->getOpcode()) { 235 default: 236#ifndef NDEBUG 237 cerr << "SplitVectorResult #" << ResNo << ": "; 238 N->dump(&DAG); cerr << "\n"; 239#endif 240 assert(0 && "Do not know how to split the result of this operator!"); 241 abort(); 242 243 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 244 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 245 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 246 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 247 248 case ISD::LOAD: 249 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); 250 break; 251 case ISD::BUILD_PAIR: SplitVecRes_BUILD_PAIR(N, Lo, Hi); break; 252 case ISD::INSERT_VECTOR_ELT:SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 253 case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break; 254 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 255 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 256 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break; 257 case ISD::CTTZ: 258 case ISD::CTLZ: 259 case ISD::CTPOP: 260 case ISD::FNEG: 261 case ISD::FABS: 262 case ISD::FSQRT: 263 case ISD::FSIN: 264 case ISD::FCOS: 265 case ISD::FP_TO_SINT: 266 case ISD::FP_TO_UINT: 267 case ISD::SINT_TO_FP: 268 case ISD::UINT_TO_FP: SplitVecRes_UnOp(N, Lo, Hi); break; 269 case ISD::ADD: 270 case ISD::SUB: 271 case ISD::MUL: 272 case ISD::FADD: 273 case ISD::FSUB: 274 case ISD::FMUL: 275 case ISD::SDIV: 276 case ISD::UDIV: 277 case ISD::FDIV: 278 case ISD::FPOW: 279 case ISD::AND: 280 case ISD::OR: 281 case ISD::XOR: 282 case ISD::UREM: 283 case ISD::SREM: 284 case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break; 285 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; 286 } 287 288 // If Lo/Hi is null, the sub-method took care of registering results etc. 289 if (Lo.Val) 290 SetSplitVector(SDOperand(N, ResNo), Lo, Hi); 291} 292 293void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDOperand &Lo, 294 SDOperand &Hi) { 295 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"); 296 MVT LoVT, HiVT; 297 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); 298 299 SDOperand Ch = LD->getChain(); 300 SDOperand Ptr = LD->getBasePtr(); 301 const Value *SV = LD->getSrcValue(); 302 int SVOffset = LD->getSrcValueOffset(); 303 unsigned Alignment = LD->getAlignment(); 304 bool isVolatile = LD->isVolatile(); 305 306 Lo = DAG.getLoad(LoVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 307 308 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 309 unsigned IncrementSize = LoVT.getSizeInBits()/8; 310 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 311 DAG.getIntPtrConstant(IncrementSize)); 312 SVOffset += IncrementSize; 313 Alignment = MinAlign(Alignment, IncrementSize); 314 Hi = DAG.getLoad(HiVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 315 316 // Build a factor node to remember that this load is independent of the 317 // other one. 318 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 319 Hi.getValue(1)); 320 } else { 321 assert(LD->getExtensionType() == ISD::EXTLOAD && 322 "Unsupported vector extending load!"); 323 Hi = DAG.getNode(ISD::UNDEF, HiVT); 324 Ch = Lo.getValue(1); 325 } 326 327 // Legalized the chain result - switch anything that used the old chain to 328 // use the new one. 329 ReplaceValueWith(SDOperand(LD, 1), Ch); 330} 331 332void DAGTypeLegalizer::SplitVecRes_BUILD_PAIR(SDNode *N, SDOperand &Lo, 333 SDOperand &Hi) { 334#ifndef NDEBUG 335 MVT LoVT, HiVT; 336 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 337 assert(LoVT == HiVT && "Non-power-of-two vectors not supported!"); 338#endif 339 Lo = N->getOperand(0); 340 Hi = N->getOperand(1); 341} 342 343void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo, 344 SDOperand &Hi) { 345 SDOperand Vec = N->getOperand(0); 346 SDOperand Elt = N->getOperand(1); 347 SDOperand Idx = N->getOperand(2); 348 GetSplitVector(Vec, Lo, Hi); 349 350 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 351 unsigned IdxVal = CIdx->getValue(); 352 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 353 if (IdxVal < LoNumElts) 354 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx); 355 else 356 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, Elt, 357 DAG.getIntPtrConstant(IdxVal - LoNumElts)); 358 return; 359 } 360 361 // Spill the vector to the stack. 362 MVT VecVT = Vec.getValueType(); 363 MVT EltVT = VecVT.getVectorElementType(); 364 SDOperand StackPtr = DAG.CreateStackTemporary(VecVT); 365 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 366 367 // Store the new element. This may be larger than the vector element type, 368 // so use a truncating store. 369 SDOperand EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 370 Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT); 371 372 // Reload the vector from the stack. 373 SDOperand Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0); 374 375 // Split it. 376 SplitVecRes_LOAD(cast<LoadSDNode>(Load.Val), Lo, Hi); 377} 378 379void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo, 380 SDOperand &Hi) { 381 // Build the low part. 382 SDOperand Mask = N->getOperand(2); 383 SmallVector<SDOperand, 16> Ops; 384 MVT LoVT, HiVT; 385 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 386 MVT EltVT = LoVT.getVectorElementType(); 387 unsigned LoNumElts = LoVT.getVectorNumElements(); 388 unsigned NumElements = Mask.getNumOperands(); 389 390 // Insert all of the elements from the input that are needed. We use 391 // buildvector of extractelement here because the input vectors will have 392 // to be legalized, so this makes the code simpler. 393 for (unsigned i = 0; i != LoNumElts; ++i) { 394 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 395 SDOperand InVec = N->getOperand(0); 396 if (Idx >= NumElements) { 397 InVec = N->getOperand(1); 398 Idx -= NumElements; 399 } 400 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec, 401 DAG.getIntPtrConstant(Idx))); 402 } 403 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &Ops[0], Ops.size()); 404 Ops.clear(); 405 406 for (unsigned i = LoNumElts; i != NumElements; ++i) { 407 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 408 SDOperand InVec = N->getOperand(0); 409 if (Idx >= NumElements) { 410 InVec = N->getOperand(1); 411 Idx -= NumElements; 412 } 413 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec, 414 DAG.getIntPtrConstant(Idx))); 415 } 416 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size()); 417} 418 419void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo, 420 SDOperand &Hi) { 421 MVT LoVT, HiVT; 422 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 423 unsigned LoNumElts = LoVT.getVectorNumElements(); 424 SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts); 425 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size()); 426 427 SmallVector<SDOperand, 8> HiOps(N->op_begin()+LoNumElts, N->op_end()); 428 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size()); 429} 430 431void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDOperand &Lo, 432 SDOperand &Hi) { 433 // FIXME: Handle non-power-of-two vectors? 434 unsigned NumSubvectors = N->getNumOperands() / 2; 435 if (NumSubvectors == 1) { 436 Lo = N->getOperand(0); 437 Hi = N->getOperand(1); 438 return; 439 } 440 441 MVT LoVT, HiVT; 442 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 443 444 SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); 445 Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size()); 446 447 SmallVector<SDOperand, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end()); 448 Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size()); 449} 450 451void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDOperand &Lo, 452 SDOperand &Hi) { 453 // We know the result is a vector. The input may be either a vector or a 454 // scalar value. 455 MVT LoVT, HiVT; 456 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 457 458 SDOperand InOp = N->getOperand(0); 459 MVT InVT = InOp.getValueType(); 460 461 // Handle some special cases efficiently. 462 switch (getTypeAction(InVT)) { 463 default: 464 assert(false && "Unknown type action!"); 465 case Legal: 466 case PromoteInteger: 467 case SoftenFloat: 468 case ScalarizeVector: 469 break; 470 case ExpandInteger: 471 case ExpandFloat: 472 // A scalar to vector conversion, where the scalar needs expansion. 473 // If the vector is being split in two then we can just convert the 474 // expanded pieces. 475 if (LoVT == HiVT) { 476 GetExpandedOp(InOp, Lo, Hi); 477 if (TLI.isBigEndian()) 478 std::swap(Lo, Hi); 479 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo); 480 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi); 481 return; 482 } 483 break; 484 case SplitVector: 485 // If the input is a vector that needs to be split, convert each split 486 // piece of the input now. 487 GetSplitVector(InOp, Lo, Hi); 488 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo); 489 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi); 490 return; 491 } 492 493 // In the general case, convert the input to an integer and split it by hand. 494 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits()); 495 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits()); 496 if (TLI.isBigEndian()) 497 std::swap(LoIntVT, HiIntVT); 498 499 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); 500 501 if (TLI.isBigEndian()) 502 std::swap(Lo, Hi); 503 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo); 504 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi); 505} 506 507void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDOperand &Lo, 508 SDOperand &Hi) { 509 SDOperand LHSLo, LHSHi; 510 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 511 SDOperand RHSLo, RHSHi; 512 GetSplitVector(N->getOperand(1), RHSLo, RHSHi); 513 514 Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo); 515 Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi); 516} 517 518void DAGTypeLegalizer::SplitVecRes_UnOp(SDNode *N, SDOperand &Lo, 519 SDOperand &Hi) { 520 // Get the dest types. This doesn't always match input types, e.g. int_to_fp. 521 MVT LoVT, HiVT; 522 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 523 524 GetSplitVector(N->getOperand(0), Lo, Hi); 525 Lo = DAG.getNode(N->getOpcode(), LoVT, Lo); 526 Hi = DAG.getNode(N->getOpcode(), HiVT, Hi); 527} 528 529void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDOperand &Lo, 530 SDOperand &Hi) { 531 GetSplitVector(N->getOperand(0), Lo, Hi); 532 Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1)); 533 Hi = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Hi, N->getOperand(1)); 534} 535 536 537//===----------------------------------------------------------------------===// 538// Operand Vector Splitting 539//===----------------------------------------------------------------------===// 540 541/// SplitVectorOperand - This method is called when the specified operand of the 542/// specified node is found to need vector splitting. At this point, all of the 543/// result types of the node are known to be legal, but other operands of the 544/// node may need legalization as well as the specified one. 545bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { 546 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n"); 547 SDOperand Res = SDOperand(); 548 549 if (Res.Val == 0) { 550 switch (N->getOpcode()) { 551 default: 552#ifndef NDEBUG 553 cerr << "SplitVectorOperand Op #" << OpNo << ": "; 554 N->dump(&DAG); cerr << "\n"; 555#endif 556 assert(0 && "Do not know how to split this operator's operand!"); 557 abort(); 558 case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo); break; 559 560 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break; 561 562 case ISD::EXTRACT_VECTOR_ELT: Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; 563 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; 564 case ISD::VECTOR_SHUFFLE: 565 Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo); 566 break; 567 } 568 } 569 570 // If the result is null, the sub-method took care of registering results etc. 571 if (!Res.Val) return false; 572 573 // If the result is N, the sub-method updated N in place. Check to see if any 574 // operands are new, and if so, mark them. 575 if (Res.Val == N) { 576 // Mark N as new and remark N and its operands. This allows us to correctly 577 // revisit N if it needs another step of promotion and allows us to visit 578 // any new operands to N. 579 ReanalyzeNode(N); 580 return true; 581 } 582 583 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 584 "Invalid operand expansion"); 585 586 ReplaceValueWith(SDOperand(N, 0), Res); 587 return false; 588} 589 590SDOperand DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { 591 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 592 assert(OpNo == 1 && "Can only split the stored value"); 593 594 SDOperand Ch = N->getChain(); 595 SDOperand Ptr = N->getBasePtr(); 596 int SVOffset = N->getSrcValueOffset(); 597 unsigned Alignment = N->getAlignment(); 598 bool isVol = N->isVolatile(); 599 SDOperand Lo, Hi; 600 GetSplitVector(N->getOperand(1), Lo, Hi); 601 602 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; 603 604 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, isVol, Alignment); 605 606 // Increment the pointer to the other half. 607 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 608 DAG.getIntPtrConstant(IncrementSize)); 609 610 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize, 611 isVol, MinAlign(Alignment, IncrementSize)); 612 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 613} 614 615SDOperand DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) { 616 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will 617 // end up being split all the way down to individual components. Convert the 618 // split pieces into integers and reassemble. 619 SDOperand Lo, Hi; 620 GetSplitVector(N->getOperand(0), Lo, Hi); 621 Lo = BitConvertToInteger(Lo); 622 Hi = BitConvertToInteger(Hi); 623 624 if (TLI.isBigEndian()) 625 std::swap(Lo, Hi); 626 627 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), 628 JoinIntegers(Lo, Hi)); 629} 630 631SDOperand DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 632 SDOperand Vec = N->getOperand(0); 633 SDOperand Idx = N->getOperand(1); 634 MVT VecVT = Vec.getValueType(); 635 636 if (isa<ConstantSDNode>(Idx)) { 637 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue(); 638 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); 639 640 SDOperand Lo, Hi; 641 GetSplitVector(Vec, Lo, Hi); 642 643 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 644 645 if (IdxVal < LoElts) 646 return DAG.UpdateNodeOperands(SDOperand(N, 0), Lo, Idx); 647 else 648 return DAG.UpdateNodeOperands(SDOperand(N, 0), Hi, 649 DAG.getConstant(IdxVal - LoElts, 650 Idx.getValueType())); 651 } 652 653 // Store the vector to the stack. 654 MVT EltVT = VecVT.getVectorElementType(); 655 SDOperand StackPtr = DAG.CreateStackTemporary(VecVT); 656 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 657 658 // Load back the required element. 659 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 660 return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0); 661} 662 663SDOperand DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 664 // We know that the extracted result type is legal. For now, assume the index 665 // is a constant. 666 MVT SubVT = N->getValueType(0); 667 SDOperand Idx = N->getOperand(1); 668 SDOperand Lo, Hi; 669 GetSplitVector(N->getOperand(0), Lo, Hi); 670 671 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 672 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue(); 673 674 if (IdxVal < LoElts) { 675 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && 676 "Extracted subvector crosses vector split!"); 677 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx); 678 } else { 679 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi, 680 DAG.getConstant(IdxVal - LoElts, Idx.getValueType())); 681 } 682} 683 684SDOperand DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo){ 685 assert(OpNo == 2 && "Shuffle source type differs from result type?"); 686 SDOperand Mask = N->getOperand(2); 687 unsigned MaskLength = Mask.getValueType().getVectorNumElements(); 688 unsigned LargestMaskEntryPlusOne = 2 * MaskLength; 689 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne); 690 691 // Look for a legal vector type to place the mask values in. 692 // Note that there may not be *any* legal vector-of-integer 693 // type for which the element type is legal! 694 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE; 695 EltVT <= MVT::LAST_INTEGER_VALUETYPE; 696 // Integer values types are consecutively numbered. Exploit this. 697 EltVT = MVT::SimpleValueType(EltVT + 1)) { 698 699 // Is the element type big enough to hold the values? 700 if (MVT(EltVT).getSizeInBits() < MinimumBitWidth) 701 // Nope. 702 continue; 703 704 // Is the vector type legal? 705 MVT VecVT = MVT::getVectorVT(EltVT, MaskLength); 706 if (!isTypeLegal(VecVT)) 707 // Nope. 708 continue; 709 710 // If the element type is not legal, find a larger legal type to use for 711 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work! 712 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic 713 // node where the shuffle mask is a list of integer operands, #2 .. #2+n. 714 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE; 715 // Integer values types are consecutively numbered. Exploit this. 716 OpVT = MVT::SimpleValueType(OpVT + 1)) { 717 if (!isTypeLegal(OpVT)) 718 continue; 719 720 // Success! Rebuild the vector using the legal types. 721 SmallVector<SDOperand, 16> Ops(MaskLength); 722 for (unsigned i = 0; i < MaskLength; ++i) { 723 uint64_t Idx = 724 cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 725 Ops[i] = DAG.getConstant(Idx, OpVT); 726 } 727 return DAG.UpdateNodeOperands(SDOperand(N,0), 728 N->getOperand(0), N->getOperand(1), 729 DAG.getNode(ISD::BUILD_VECTOR, 730 VecVT, &Ops[0], Ops.size())); 731 } 732 733 // Continuing is pointless - failure is certain. 734 break; 735 } 736 assert(false && "Failed to find an appropriate mask type!"); 737 return SDOperand(N, 0); 738} 739