LegalizeVectorTypes.cpp revision 46646572f76513e39bcdd0e06c66668ec1caf5bc
1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file performs vector type splitting and scalarization for LegalizeTypes. 11// Scalarization is the act of changing a computation in an illegal one-element 12// vector type to be a computation in its scalar element type. For example, 13// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed 14// as a base case when scalarizing vector arithmetic like <4 x f32>, which 15// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32 16// types. 17// Splitting is the act of changing a computation in an invalid vector type to 18// be a computation in two vectors of half the size. For example, implementing 19// <128 x f32> operations in terms of two <64 x f32> operations. 20// 21//===----------------------------------------------------------------------===// 22 23#include "LegalizeTypes.h" 24#include "llvm/Target/TargetData.h" 25#include "llvm/Support/ErrorHandling.h" 26#include "llvm/Support/raw_ostream.h" 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// Result Vector Scalarization: <1 x ty> -> ty. 31//===----------------------------------------------------------------------===// 32 33void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { 34 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; 35 N->dump(&DAG); 36 dbgs() << "\n"); 37 SDValue R = SDValue(); 38 39 switch (N->getOpcode()) { 40 default: 41#ifndef NDEBUG 42 dbgs() << "ScalarizeVectorResult #" << ResNo << ": "; 43 N->dump(&DAG); 44 dbgs() << "\n"; 45#endif 46 report_fatal_error("Do not know how to scalarize the result of this " 47 "operator!\n"); 48 49 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; 50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 51 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; 52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; 53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; 55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; 56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; 59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; 60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; 61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; 62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break; 63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; 65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; 66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; 67 case ISD::ANY_EXTEND: 68 case ISD::CTLZ: 69 case ISD::CTPOP: 70 case ISD::CTTZ: 71 case ISD::FABS: 72 case ISD::FCEIL: 73 case ISD::FCOS: 74 case ISD::FEXP: 75 case ISD::FEXP2: 76 case ISD::FFLOOR: 77 case ISD::FLOG: 78 case ISD::FLOG10: 79 case ISD::FLOG2: 80 case ISD::FNEARBYINT: 81 case ISD::FNEG: 82 case ISD::FP_EXTEND: 83 case ISD::FP_TO_SINT: 84 case ISD::FP_TO_UINT: 85 case ISD::FRINT: 86 case ISD::FSIN: 87 case ISD::FSQRT: 88 case ISD::FTRUNC: 89 case ISD::SIGN_EXTEND: 90 case ISD::SINT_TO_FP: 91 case ISD::TRUNCATE: 92 case ISD::UINT_TO_FP: 93 case ISD::ZERO_EXTEND: 94 R = ScalarizeVecRes_UnaryOp(N); 95 break; 96 97 case ISD::ADD: 98 case ISD::AND: 99 case ISD::FADD: 100 case ISD::FDIV: 101 case ISD::FMUL: 102 case ISD::FPOW: 103 case ISD::FREM: 104 case ISD::FSUB: 105 case ISD::MUL: 106 case ISD::OR: 107 case ISD::SDIV: 108 case ISD::SREM: 109 case ISD::SUB: 110 case ISD::UDIV: 111 case ISD::UREM: 112 case ISD::XOR: 113 case ISD::SHL: 114 case ISD::SRA: 115 case ISD::SRL: 116 R = ScalarizeVecRes_BinOp(N); 117 break; 118 case ISD::FMA: 119 R = ScalarizeVecRes_TernaryOp(N); 120 break; 121 } 122 123 // If R is null, the sub-method took care of registering the result. 124 if (R.getNode()) 125 SetScalarizedVector(SDValue(N, ResNo), R); 126} 127 128SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { 129 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 130 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 131 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 132 LHS.getValueType(), LHS, RHS); 133} 134 135SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) { 136 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); 137 SDValue Op1 = GetScalarizedVector(N->getOperand(1)); 138 SDValue Op2 = GetScalarizedVector(N->getOperand(2)); 139 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 140 Op0.getValueType(), Op0, Op1, Op2); 141} 142 143SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N, 144 unsigned ResNo) { 145 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); 146 return GetScalarizedVector(Op); 147} 148 149SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) { 150 EVT NewVT = N->getValueType(0).getVectorElementType(); 151 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 152 NewVT, N->getOperand(0)); 153} 154 155SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) { 156 EVT EltVT = N->getValueType(0).getVectorElementType(); 157 SDValue InOp = N->getOperand(0); 158 if (InOp.getValueType() != EltVT) 159 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp); 160 return InOp; 161} 162 163SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) { 164 EVT NewVT = N->getValueType(0).getVectorElementType(); 165 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); 166 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(), 167 Op0, DAG.getValueType(NewVT), 168 DAG.getValueType(Op0.getValueType()), 169 N->getOperand(3), 170 N->getOperand(4), 171 cast<CvtRndSatSDNode>(N)->getCvtCode()); 172} 173 174SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 175 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 176 N->getValueType(0).getVectorElementType(), 177 N->getOperand(0), N->getOperand(1)); 178} 179 180SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) { 181 EVT NewVT = N->getValueType(0).getVectorElementType(); 182 SDValue Op = GetScalarizedVector(N->getOperand(0)); 183 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), 184 NewVT, Op, N->getOperand(1)); 185} 186 187SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) { 188 SDValue Op = GetScalarizedVector(N->getOperand(0)); 189 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(), 190 Op.getValueType(), Op, N->getOperand(1)); 191} 192 193SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { 194 // The value to insert may have a wider type than the vector element type, 195 // so be sure to truncate it to the element type if necessary. 196 SDValue Op = N->getOperand(1); 197 EVT EltVT = N->getValueType(0).getVectorElementType(); 198 if (Op.getValueType() != EltVT) 199 // FIXME: Can this happen for floating point types? 200 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op); 201 return Op; 202} 203 204SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { 205 assert(N->isUnindexed() && "Indexed vector load?"); 206 207 SDValue Result = DAG.getLoad(ISD::UNINDEXED, 208 N->getExtensionType(), 209 N->getValueType(0).getVectorElementType(), 210 N->getDebugLoc(), 211 N->getChain(), N->getBasePtr(), 212 DAG.getUNDEF(N->getBasePtr().getValueType()), 213 N->getPointerInfo(), 214 N->getMemoryVT().getVectorElementType(), 215 N->isVolatile(), N->isNonTemporal(), 216 N->isInvariant(), N->getOriginalAlignment()); 217 218 // Legalized the chain result - switch anything that used the old chain to 219 // use the new one. 220 ReplaceValueWith(SDValue(N, 1), Result.getValue(1)); 221 return Result; 222} 223 224SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { 225 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp. 226 EVT DestVT = N->getValueType(0).getVectorElementType(); 227 SDValue Op = GetScalarizedVector(N->getOperand(0)); 228 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op); 229} 230 231SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) { 232 EVT EltVT = N->getValueType(0).getVectorElementType(); 233 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType(); 234 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 235 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT, 236 LHS, DAG.getValueType(ExtVT)); 237} 238 239SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) { 240 // If the operand is wider than the vector element type then it is implicitly 241 // truncated. Make that explicit here. 242 EVT EltVT = N->getValueType(0).getVectorElementType(); 243 SDValue InOp = N->getOperand(0); 244 if (InOp.getValueType() != EltVT) 245 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp); 246 return InOp; 247} 248 249SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) { 250 SDValue Cond = GetScalarizedVector(N->getOperand(0)); 251 SDValue LHS = GetScalarizedVector(N->getOperand(1)); 252 TargetLowering::BooleanContent ScalarBool = TLI.getBooleanContents(false); 253 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true); 254 if (ScalarBool != VecBool) { 255 EVT CondVT = Cond.getValueType(); 256 switch (ScalarBool) { 257 case TargetLowering::UndefinedBooleanContent: 258 break; 259 case TargetLowering::ZeroOrOneBooleanContent: 260 assert(VecBool == TargetLowering::UndefinedBooleanContent || 261 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent); 262 // Vector read from all ones, scalar expects a single 1 so mask. 263 Cond = DAG.getNode(ISD::AND, N->getDebugLoc(), CondVT, 264 Cond, DAG.getConstant(1, CondVT)); 265 break; 266 case TargetLowering::ZeroOrNegativeOneBooleanContent: 267 assert(VecBool == TargetLowering::UndefinedBooleanContent || 268 VecBool == TargetLowering::ZeroOrOneBooleanContent); 269 // Vector reads from a one, scalar from all ones so sign extend. 270 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), CondVT, 271 Cond, DAG.getValueType(MVT::i1)); 272 break; 273 } 274 } 275 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 276 LHS.getValueType(), Cond, LHS, 277 GetScalarizedVector(N->getOperand(2))); 278} 279 280SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) { 281 SDValue LHS = GetScalarizedVector(N->getOperand(1)); 282 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 283 LHS.getValueType(), N->getOperand(0), LHS, 284 GetScalarizedVector(N->getOperand(2))); 285} 286 287SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) { 288 SDValue LHS = GetScalarizedVector(N->getOperand(2)); 289 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(), 290 N->getOperand(0), N->getOperand(1), 291 LHS, GetScalarizedVector(N->getOperand(3)), 292 N->getOperand(4)); 293} 294 295SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) { 296 assert(N->getValueType(0).isVector() == 297 N->getOperand(0).getValueType().isVector() && 298 "Scalar/Vector type mismatch"); 299 300 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N); 301 302 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 303 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 304 DebugLoc DL = N->getDebugLoc(); 305 306 // Turn it into a scalar SETCC. 307 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); 308} 309 310SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { 311 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 312} 313 314SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { 315 // Figure out if the scalar is the LHS or RHS and return it. 316 SDValue Arg = N->getOperand(2).getOperand(0); 317 if (Arg.getOpcode() == ISD::UNDEF) 318 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 319 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue(); 320 return GetScalarizedVector(N->getOperand(Op)); 321} 322 323SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) { 324 assert(N->getValueType(0).isVector() && 325 N->getOperand(0).getValueType().isVector() && 326 "Operand types must be vectors"); 327 328 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 329 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 330 EVT NVT = N->getValueType(0).getVectorElementType(); 331 DebugLoc DL = N->getDebugLoc(); 332 333 // Turn it into a scalar SETCC. 334 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, 335 N->getOperand(2)); 336 // Vectors may have a different boolean contents to scalars. Promote the 337 // value appropriately. 338 ISD::NodeType ExtendCode = 339 TargetLowering::getExtendForContent(TLI.getBooleanContents(true)); 340 return DAG.getNode(ExtendCode, DL, NVT, Res); 341} 342 343 344//===----------------------------------------------------------------------===// 345// Operand Vector Scalarization <1 x ty> -> ty. 346//===----------------------------------------------------------------------===// 347 348bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { 349 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; 350 N->dump(&DAG); 351 dbgs() << "\n"); 352 SDValue Res = SDValue(); 353 354 if (Res.getNode() == 0) { 355 switch (N->getOpcode()) { 356 default: 357#ifndef NDEBUG 358 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": "; 359 N->dump(&DAG); 360 dbgs() << "\n"; 361#endif 362 llvm_unreachable("Do not know how to scalarize this operator's operand!"); 363 case ISD::BITCAST: 364 Res = ScalarizeVecOp_BITCAST(N); 365 break; 366 case ISD::CONCAT_VECTORS: 367 Res = ScalarizeVecOp_CONCAT_VECTORS(N); 368 break; 369 case ISD::EXTRACT_VECTOR_ELT: 370 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); 371 break; 372 case ISD::STORE: 373 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); 374 break; 375 } 376 } 377 378 // If the result is null, the sub-method took care of registering results etc. 379 if (!Res.getNode()) return false; 380 381 // If the result is N, the sub-method updated N in place. Tell the legalizer 382 // core about this. 383 if (Res.getNode() == N) 384 return true; 385 386 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 387 "Invalid operand expansion"); 388 389 ReplaceValueWith(SDValue(N, 0), Res); 390 return false; 391} 392 393/// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs 394/// to be scalarized, it must be <1 x ty>. Convert the element instead. 395SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) { 396 SDValue Elt = GetScalarizedVector(N->getOperand(0)); 397 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 398 N->getValueType(0), Elt); 399} 400 401/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one - 402/// use a BUILD_VECTOR instead. 403SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) { 404 SmallVector<SDValue, 8> Ops(N->getNumOperands()); 405 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 406 Ops[i] = GetScalarizedVector(N->getOperand(i)); 407 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0), 408 &Ops[0], Ops.size()); 409} 410 411/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to 412/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the 413/// index. 414SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 415 SDValue Res = GetScalarizedVector(N->getOperand(0)); 416 if (Res.getValueType() != N->getValueType(0)) 417 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), 418 Res); 419 return Res; 420} 421 422/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be 423/// scalarized, it must be <1 x ty>. Just store the element. 424SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ 425 assert(N->isUnindexed() && "Indexed store of one-element vector?"); 426 assert(OpNo == 1 && "Do not know how to scalarize this operand!"); 427 DebugLoc dl = N->getDebugLoc(); 428 429 if (N->isTruncatingStore()) 430 return DAG.getTruncStore(N->getChain(), dl, 431 GetScalarizedVector(N->getOperand(1)), 432 N->getBasePtr(), N->getPointerInfo(), 433 N->getMemoryVT().getVectorElementType(), 434 N->isVolatile(), N->isNonTemporal(), 435 N->getAlignment()); 436 437 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)), 438 N->getBasePtr(), N->getPointerInfo(), 439 N->isVolatile(), N->isNonTemporal(), 440 N->getOriginalAlignment()); 441} 442 443 444//===----------------------------------------------------------------------===// 445// Result Vector Splitting 446//===----------------------------------------------------------------------===// 447 448/// SplitVectorResult - This method is called when the specified result of the 449/// specified node is found to need vector splitting. At this point, the node 450/// may also have invalid operands or may have other results that need 451/// legalization, we just know that (at least) one result needs vector 452/// splitting. 453void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { 454 DEBUG(dbgs() << "Split node result: "; 455 N->dump(&DAG); 456 dbgs() << "\n"); 457 SDValue Lo, Hi; 458 459 // See if the target wants to custom expand this node. 460 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 461 return; 462 463 switch (N->getOpcode()) { 464 default: 465#ifndef NDEBUG 466 dbgs() << "SplitVectorResult #" << ResNo << ": "; 467 N->dump(&DAG); 468 dbgs() << "\n"; 469#endif 470 llvm_unreachable("Do not know how to split the result of this operator!"); 471 472 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 473 case ISD::VSELECT: 474 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 475 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 476 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 477 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; 478 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 479 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 480 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; 481 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 482 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; 483 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 484 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break; 485 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 486 case ISD::LOAD: 487 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); 488 break; 489 case ISD::SETCC: 490 SplitVecRes_SETCC(N, Lo, Hi); 491 break; 492 case ISD::VECTOR_SHUFFLE: 493 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); 494 break; 495 496 case ISD::ANY_EXTEND: 497 case ISD::CONVERT_RNDSAT: 498 case ISD::CTLZ: 499 case ISD::CTTZ: 500 case ISD::CTLZ_ZERO_UNDEF: 501 case ISD::CTTZ_ZERO_UNDEF: 502 case ISD::CTPOP: 503 case ISD::FABS: 504 case ISD::FCEIL: 505 case ISD::FCOS: 506 case ISD::FEXP: 507 case ISD::FEXP2: 508 case ISD::FFLOOR: 509 case ISD::FLOG: 510 case ISD::FLOG10: 511 case ISD::FLOG2: 512 case ISD::FNEARBYINT: 513 case ISD::FNEG: 514 case ISD::FP_EXTEND: 515 case ISD::FP_ROUND: 516 case ISD::FP_TO_SINT: 517 case ISD::FP_TO_UINT: 518 case ISD::FRINT: 519 case ISD::FSIN: 520 case ISD::FSQRT: 521 case ISD::FTRUNC: 522 case ISD::SIGN_EXTEND: 523 case ISD::SINT_TO_FP: 524 case ISD::TRUNCATE: 525 case ISD::UINT_TO_FP: 526 case ISD::ZERO_EXTEND: 527 SplitVecRes_UnaryOp(N, Lo, Hi); 528 break; 529 530 case ISD::ADD: 531 case ISD::SUB: 532 case ISD::MUL: 533 case ISD::FADD: 534 case ISD::FSUB: 535 case ISD::FMUL: 536 case ISD::SDIV: 537 case ISD::UDIV: 538 case ISD::FDIV: 539 case ISD::FPOW: 540 case ISD::AND: 541 case ISD::OR: 542 case ISD::XOR: 543 case ISD::SHL: 544 case ISD::SRA: 545 case ISD::SRL: 546 case ISD::UREM: 547 case ISD::SREM: 548 case ISD::FREM: 549 SplitVecRes_BinOp(N, Lo, Hi); 550 break; 551 case ISD::FMA: 552 SplitVecRes_TernaryOp(N, Lo, Hi); 553 break; 554 } 555 556 // If Lo/Hi is null, the sub-method took care of registering results etc. 557 if (Lo.getNode()) 558 SetSplitVector(SDValue(N, ResNo), Lo, Hi); 559} 560 561void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo, 562 SDValue &Hi) { 563 SDValue LHSLo, LHSHi; 564 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 565 SDValue RHSLo, RHSHi; 566 GetSplitVector(N->getOperand(1), RHSLo, RHSHi); 567 DebugLoc dl = N->getDebugLoc(); 568 569 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo); 570 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi); 571} 572 573void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, 574 SDValue &Hi) { 575 SDValue Op0Lo, Op0Hi; 576 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi); 577 SDValue Op1Lo, Op1Hi; 578 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi); 579 SDValue Op2Lo, Op2Hi; 580 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi); 581 DebugLoc dl = N->getDebugLoc(); 582 583 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(), 584 Op0Lo, Op1Lo, Op2Lo); 585 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(), 586 Op0Hi, Op1Hi, Op2Hi); 587} 588 589void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, 590 SDValue &Hi) { 591 // We know the result is a vector. The input may be either a vector or a 592 // scalar value. 593 EVT LoVT, HiVT; 594 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 595 DebugLoc dl = N->getDebugLoc(); 596 597 SDValue InOp = N->getOperand(0); 598 EVT InVT = InOp.getValueType(); 599 600 // Handle some special cases efficiently. 601 switch (getTypeAction(InVT)) { 602 case TargetLowering::TypeLegal: 603 case TargetLowering::TypePromoteInteger: 604 case TargetLowering::TypeSoftenFloat: 605 case TargetLowering::TypeScalarizeVector: 606 case TargetLowering::TypeWidenVector: 607 break; 608 case TargetLowering::TypeExpandInteger: 609 case TargetLowering::TypeExpandFloat: 610 // A scalar to vector conversion, where the scalar needs expansion. 611 // If the vector is being split in two then we can just convert the 612 // expanded pieces. 613 if (LoVT == HiVT) { 614 GetExpandedOp(InOp, Lo, Hi); 615 if (TLI.isBigEndian()) 616 std::swap(Lo, Hi); 617 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 618 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 619 return; 620 } 621 break; 622 case TargetLowering::TypeSplitVector: 623 // If the input is a vector that needs to be split, convert each split 624 // piece of the input now. 625 GetSplitVector(InOp, Lo, Hi); 626 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 627 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 628 return; 629 } 630 631 // In the general case, convert the input to an integer and split it by hand. 632 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits()); 633 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits()); 634 if (TLI.isBigEndian()) 635 std::swap(LoIntVT, HiIntVT); 636 637 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); 638 639 if (TLI.isBigEndian()) 640 std::swap(Lo, Hi); 641 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 642 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 643} 644 645void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, 646 SDValue &Hi) { 647 EVT LoVT, HiVT; 648 DebugLoc dl = N->getDebugLoc(); 649 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 650 unsigned LoNumElts = LoVT.getVectorNumElements(); 651 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts); 652 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size()); 653 654 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end()); 655 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size()); 656} 657 658void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, 659 SDValue &Hi) { 660 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"); 661 DebugLoc dl = N->getDebugLoc(); 662 unsigned NumSubvectors = N->getNumOperands() / 2; 663 if (NumSubvectors == 1) { 664 Lo = N->getOperand(0); 665 Hi = N->getOperand(1); 666 return; 667 } 668 669 EVT LoVT, HiVT; 670 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 671 672 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); 673 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size()); 674 675 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end()); 676 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size()); 677} 678 679void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, 680 SDValue &Hi) { 681 SDValue Vec = N->getOperand(0); 682 SDValue Idx = N->getOperand(1); 683 DebugLoc dl = N->getDebugLoc(); 684 685 EVT LoVT, HiVT; 686 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 687 688 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); 689 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 690 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, 691 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements())); 692} 693 694void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, 695 SDValue &Hi) { 696 DebugLoc dl = N->getDebugLoc(); 697 GetSplitVector(N->getOperand(0), Lo, Hi); 698 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1)); 699 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1)); 700} 701 702void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo, 703 SDValue &Hi) { 704 SDValue LHSLo, LHSHi; 705 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 706 DebugLoc dl = N->getDebugLoc(); 707 708 EVT LoVT, HiVT; 709 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT); 710 711 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, 712 DAG.getValueType(LoVT)); 713 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, 714 DAG.getValueType(HiVT)); 715} 716 717void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, 718 SDValue &Hi) { 719 SDValue Vec = N->getOperand(0); 720 SDValue Elt = N->getOperand(1); 721 SDValue Idx = N->getOperand(2); 722 DebugLoc dl = N->getDebugLoc(); 723 GetSplitVector(Vec, Lo, Hi); 724 725 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 726 unsigned IdxVal = CIdx->getZExtValue(); 727 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 728 if (IdxVal < LoNumElts) 729 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 730 Lo.getValueType(), Lo, Elt, Idx); 731 else 732 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, 733 DAG.getIntPtrConstant(IdxVal - LoNumElts)); 734 return; 735 } 736 737 // Spill the vector to the stack. 738 EVT VecVT = Vec.getValueType(); 739 EVT EltVT = VecVT.getVectorElementType(); 740 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 741 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 742 MachinePointerInfo(), false, false, 0); 743 744 // Store the new element. This may be larger than the vector element type, 745 // so use a truncating store. 746 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 747 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); 748 unsigned Alignment = 749 TLI.getTargetData()->getPrefTypeAlignment(VecType); 750 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT, 751 false, false, 0); 752 753 // Load the Lo part from the stack slot. 754 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 755 false, false, false, 0); 756 757 // Increment the pointer to the other part. 758 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; 759 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 760 DAG.getIntPtrConstant(IncrementSize)); 761 762 // Load the Hi part from the stack slot. 763 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 764 false, false, false, MinAlign(Alignment, IncrementSize)); 765} 766 767void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, 768 SDValue &Hi) { 769 EVT LoVT, HiVT; 770 DebugLoc dl = N->getDebugLoc(); 771 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 772 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0)); 773 Hi = DAG.getUNDEF(HiVT); 774} 775 776void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, 777 SDValue &Hi) { 778 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"); 779 EVT LoVT, HiVT; 780 DebugLoc dl = LD->getDebugLoc(); 781 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); 782 783 ISD::LoadExtType ExtType = LD->getExtensionType(); 784 SDValue Ch = LD->getChain(); 785 SDValue Ptr = LD->getBasePtr(); 786 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 787 EVT MemoryVT = LD->getMemoryVT(); 788 unsigned Alignment = LD->getOriginalAlignment(); 789 bool isVolatile = LD->isVolatile(); 790 bool isNonTemporal = LD->isNonTemporal(); 791 bool isInvariant = LD->isInvariant(); 792 793 EVT LoMemVT, HiMemVT; 794 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 795 796 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, 797 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal, 798 isInvariant, Alignment); 799 800 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 801 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 802 DAG.getIntPtrConstant(IncrementSize)); 803 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, 804 LD->getPointerInfo().getWithOffset(IncrementSize), 805 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment); 806 807 // Build a factor node to remember that this load is independent of the 808 // other one. 809 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 810 Hi.getValue(1)); 811 812 // Legalized the chain result - switch anything that used the old chain to 813 // use the new one. 814 ReplaceValueWith(SDValue(LD, 1), Ch); 815} 816 817void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) { 818 assert(N->getValueType(0).isVector() && 819 N->getOperand(0).getValueType().isVector() && 820 "Operand types must be vectors"); 821 822 EVT LoVT, HiVT; 823 DebugLoc DL = N->getDebugLoc(); 824 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 825 826 // Split the input. 827 EVT InVT = N->getOperand(0).getValueType(); 828 SDValue LL, LH, RL, RH; 829 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 830 LoVT.getVectorNumElements()); 831 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 832 DAG.getIntPtrConstant(0)); 833 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 834 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 835 836 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 837 DAG.getIntPtrConstant(0)); 838 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 839 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 840 841 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2)); 842 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2)); 843} 844 845void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, 846 SDValue &Hi) { 847 // Get the dest types - they may not match the input types, e.g. int_to_fp. 848 EVT LoVT, HiVT; 849 DebugLoc dl = N->getDebugLoc(); 850 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 851 852 // If the input also splits, handle it directly for a compile time speedup. 853 // Otherwise split it by hand. 854 EVT InVT = N->getOperand(0).getValueType(); 855 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) { 856 GetSplitVector(N->getOperand(0), Lo, Hi); 857 } else { 858 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 859 LoVT.getVectorNumElements()); 860 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 861 DAG.getIntPtrConstant(0)); 862 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 863 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 864 } 865 866 if (N->getOpcode() == ISD::FP_ROUND) { 867 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1)); 868 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1)); 869 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) { 870 SDValue DTyOpLo = DAG.getValueType(LoVT); 871 SDValue DTyOpHi = DAG.getValueType(HiVT); 872 SDValue STyOpLo = DAG.getValueType(Lo.getValueType()); 873 SDValue STyOpHi = DAG.getValueType(Hi.getValueType()); 874 SDValue RndOp = N->getOperand(3); 875 SDValue SatOp = N->getOperand(4); 876 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 877 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp, 878 CvtCode); 879 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp, 880 CvtCode); 881 } else { 882 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo); 883 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi); 884 } 885} 886 887void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, 888 SDValue &Lo, SDValue &Hi) { 889 // The low and high parts of the original input give four input vectors. 890 SDValue Inputs[4]; 891 DebugLoc dl = N->getDebugLoc(); 892 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]); 893 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]); 894 EVT NewVT = Inputs[0].getValueType(); 895 unsigned NewElts = NewVT.getVectorNumElements(); 896 897 // If Lo or Hi uses elements from at most two of the four input vectors, then 898 // express it as a vector shuffle of those two inputs. Otherwise extract the 899 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. 900 SmallVector<int, 16> Ops; 901 for (unsigned High = 0; High < 2; ++High) { 902 SDValue &Output = High ? Hi : Lo; 903 904 // Build a shuffle mask for the output, discovering on the fly which 905 // input vectors to use as shuffle operands (recorded in InputUsed). 906 // If building a suitable shuffle vector proves too hard, then bail 907 // out with useBuildVector set. 908 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered. 909 unsigned FirstMaskIdx = High * NewElts; 910 bool useBuildVector = false; 911 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 912 // The mask element. This indexes into the input. 913 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 914 915 // The input vector this mask element indexes into. 916 unsigned Input = (unsigned)Idx / NewElts; 917 918 if (Input >= array_lengthof(Inputs)) { 919 // The mask element does not index into any input vector. 920 Ops.push_back(-1); 921 continue; 922 } 923 924 // Turn the index into an offset from the start of the input vector. 925 Idx -= Input * NewElts; 926 927 // Find or create a shuffle vector operand to hold this input. 928 unsigned OpNo; 929 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 930 if (InputUsed[OpNo] == Input) { 931 // This input vector is already an operand. 932 break; 933 } else if (InputUsed[OpNo] == -1U) { 934 // Create a new operand for this input vector. 935 InputUsed[OpNo] = Input; 936 break; 937 } 938 } 939 940 if (OpNo >= array_lengthof(InputUsed)) { 941 // More than two input vectors used! Give up on trying to create a 942 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 943 useBuildVector = true; 944 break; 945 } 946 947 // Add the mask index for the new shuffle vector. 948 Ops.push_back(Idx + OpNo * NewElts); 949 } 950 951 if (useBuildVector) { 952 EVT EltVT = NewVT.getVectorElementType(); 953 SmallVector<SDValue, 16> SVOps; 954 955 // Extract the input elements by hand. 956 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 957 // The mask element. This indexes into the input. 958 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 959 960 // The input vector this mask element indexes into. 961 unsigned Input = (unsigned)Idx / NewElts; 962 963 if (Input >= array_lengthof(Inputs)) { 964 // The mask element is "undef" or indexes off the end of the input. 965 SVOps.push_back(DAG.getUNDEF(EltVT)); 966 continue; 967 } 968 969 // Turn the index into an offset from the start of the input vector. 970 Idx -= Input * NewElts; 971 972 // Extract the vector element by hand. 973 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 974 Inputs[Input], DAG.getIntPtrConstant(Idx))); 975 } 976 977 // Construct the Lo/Hi output using a BUILD_VECTOR. 978 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size()); 979 } else if (InputUsed[0] == -1U) { 980 // No input vectors were used! The result is undefined. 981 Output = DAG.getUNDEF(NewVT); 982 } else { 983 SDValue Op0 = Inputs[InputUsed[0]]; 984 // If only one input was used, use an undefined vector for the other. 985 SDValue Op1 = InputUsed[1] == -1U ? 986 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]]; 987 // At least one input vector was used. Create a new shuffle vector. 988 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]); 989 } 990 991 Ops.clear(); 992 } 993} 994 995 996//===----------------------------------------------------------------------===// 997// Operand Vector Splitting 998//===----------------------------------------------------------------------===// 999 1000/// SplitVectorOperand - This method is called when the specified operand of the 1001/// specified node is found to need vector splitting. At this point, all of the 1002/// result types of the node are known to be legal, but other operands of the 1003/// node may need legalization as well as the specified one. 1004bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { 1005 DEBUG(dbgs() << "Split node operand: "; 1006 N->dump(&DAG); 1007 dbgs() << "\n"); 1008 SDValue Res = SDValue(); 1009 1010 if (Res.getNode() == 0) { 1011 switch (N->getOpcode()) { 1012 default: 1013#ifndef NDEBUG 1014 dbgs() << "SplitVectorOperand Op #" << OpNo << ": "; 1015 N->dump(&DAG); 1016 dbgs() << "\n"; 1017#endif 1018 llvm_unreachable("Do not know how to split this operator's operand!"); 1019 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; 1020 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break; 1021 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; 1022 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; 1023 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; 1024 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; 1025 case ISD::STORE: 1026 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo); 1027 break; 1028 1029 case ISD::CTTZ: 1030 case ISD::CTLZ: 1031 case ISD::CTPOP: 1032 case ISD::FP_EXTEND: 1033 case ISD::FP_TO_SINT: 1034 case ISD::FP_TO_UINT: 1035 case ISD::SINT_TO_FP: 1036 case ISD::UINT_TO_FP: 1037 case ISD::FTRUNC: 1038 case ISD::TRUNCATE: 1039 case ISD::SIGN_EXTEND: 1040 case ISD::ZERO_EXTEND: 1041 case ISD::ANY_EXTEND: 1042 Res = SplitVecOp_UnaryOp(N); 1043 break; 1044 } 1045 } 1046 1047 // If the result is null, the sub-method took care of registering results etc. 1048 if (!Res.getNode()) return false; 1049 1050 // If the result is N, the sub-method updated N in place. Tell the legalizer 1051 // core about this. 1052 if (Res.getNode() == N) 1053 return true; 1054 1055 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1056 "Invalid operand expansion"); 1057 1058 ReplaceValueWith(SDValue(N, 0), Res); 1059 return false; 1060} 1061 1062SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) { 1063 // The result has a legal vector type, but the input needs splitting. 1064 EVT ResVT = N->getValueType(0); 1065 SDValue Lo, Hi; 1066 DebugLoc dl = N->getDebugLoc(); 1067 GetSplitVector(N->getOperand(0), Lo, Hi); 1068 EVT InVT = Lo.getValueType(); 1069 1070 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1071 InVT.getVectorNumElements()); 1072 1073 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); 1074 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); 1075 1076 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); 1077} 1078 1079SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) { 1080 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will 1081 // end up being split all the way down to individual components. Convert the 1082 // split pieces into integers and reassemble. 1083 SDValue Lo, Hi; 1084 GetSplitVector(N->getOperand(0), Lo, Hi); 1085 Lo = BitConvertToInteger(Lo); 1086 Hi = BitConvertToInteger(Hi); 1087 1088 if (TLI.isBigEndian()) 1089 std::swap(Lo, Hi); 1090 1091 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0), 1092 JoinIntegers(Lo, Hi)); 1093} 1094 1095SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 1096 // We know that the extracted result type is legal. 1097 EVT SubVT = N->getValueType(0); 1098 SDValue Idx = N->getOperand(1); 1099 DebugLoc dl = N->getDebugLoc(); 1100 SDValue Lo, Hi; 1101 GetSplitVector(N->getOperand(0), Lo, Hi); 1102 1103 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1104 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1105 1106 if (IdxVal < LoElts) { 1107 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && 1108 "Extracted subvector crosses vector split!"); 1109 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); 1110 } else { 1111 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, 1112 DAG.getConstant(IdxVal - LoElts, Idx.getValueType())); 1113 } 1114} 1115 1116SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 1117 SDValue Vec = N->getOperand(0); 1118 SDValue Idx = N->getOperand(1); 1119 EVT VecVT = Vec.getValueType(); 1120 1121 if (isa<ConstantSDNode>(Idx)) { 1122 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1123 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); 1124 1125 SDValue Lo, Hi; 1126 GetSplitVector(Vec, Lo, Hi); 1127 1128 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1129 1130 if (IdxVal < LoElts) 1131 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0); 1132 return SDValue(DAG.UpdateNodeOperands(N, Hi, 1133 DAG.getConstant(IdxVal - LoElts, 1134 Idx.getValueType())), 0); 1135 } 1136 1137 // Store the vector to the stack. 1138 EVT EltVT = VecVT.getVectorElementType(); 1139 DebugLoc dl = N->getDebugLoc(); 1140 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 1141 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 1142 MachinePointerInfo(), false, false, 0); 1143 1144 // Load back the required element. 1145 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 1146 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, 1147 MachinePointerInfo(), EltVT, false, false, 0); 1148} 1149 1150SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { 1151 assert(N->isUnindexed() && "Indexed store of vector?"); 1152 assert(OpNo == 1 && "Can only split the stored value"); 1153 DebugLoc DL = N->getDebugLoc(); 1154 1155 bool isTruncating = N->isTruncatingStore(); 1156 SDValue Ch = N->getChain(); 1157 SDValue Ptr = N->getBasePtr(); 1158 EVT MemoryVT = N->getMemoryVT(); 1159 unsigned Alignment = N->getOriginalAlignment(); 1160 bool isVol = N->isVolatile(); 1161 bool isNT = N->isNonTemporal(); 1162 SDValue Lo, Hi; 1163 GetSplitVector(N->getOperand(1), Lo, Hi); 1164 1165 EVT LoMemVT, HiMemVT; 1166 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 1167 1168 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 1169 1170 if (isTruncating) 1171 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1172 LoMemVT, isVol, isNT, Alignment); 1173 else 1174 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1175 isVol, isNT, Alignment); 1176 1177 // Increment the pointer to the other half. 1178 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, 1179 DAG.getIntPtrConstant(IncrementSize)); 1180 1181 if (isTruncating) 1182 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr, 1183 N->getPointerInfo().getWithOffset(IncrementSize), 1184 HiMemVT, isVol, isNT, Alignment); 1185 else 1186 Hi = DAG.getStore(Ch, DL, Hi, Ptr, 1187 N->getPointerInfo().getWithOffset(IncrementSize), 1188 isVol, isNT, Alignment); 1189 1190 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi); 1191} 1192 1193SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) { 1194 DebugLoc DL = N->getDebugLoc(); 1195 1196 // The input operands all must have the same type, and we know the result the 1197 // result type is valid. Convert this to a buildvector which extracts all the 1198 // input elements. 1199 // TODO: If the input elements are power-two vectors, we could convert this to 1200 // a new CONCAT_VECTORS node with elements that are half-wide. 1201 SmallVector<SDValue, 32> Elts; 1202 EVT EltVT = N->getValueType(0).getVectorElementType(); 1203 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1204 SDValue Op = N->getOperand(op); 1205 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements(); 1206 i != e; ++i) { 1207 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, 1208 Op, DAG.getIntPtrConstant(i))); 1209 1210 } 1211 } 1212 1213 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), 1214 &Elts[0], Elts.size()); 1215} 1216 1217SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { 1218 assert(N->getValueType(0).isVector() && 1219 N->getOperand(0).getValueType().isVector() && 1220 "Operand types must be vectors"); 1221 // The result has a legal vector type, but the input needs splitting. 1222 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes; 1223 DebugLoc DL = N->getDebugLoc(); 1224 GetSplitVector(N->getOperand(0), Lo0, Hi0); 1225 GetSplitVector(N->getOperand(1), Lo1, Hi1); 1226 unsigned PartElements = Lo0.getValueType().getVectorNumElements(); 1227 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements); 1228 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements); 1229 1230 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); 1231 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); 1232 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes); 1233 return PromoteTargetBoolean(Con, N->getValueType(0)); 1234} 1235 1236 1237SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) { 1238 // The result has a legal vector type, but the input needs splitting. 1239 EVT ResVT = N->getValueType(0); 1240 SDValue Lo, Hi; 1241 DebugLoc DL = N->getDebugLoc(); 1242 GetSplitVector(N->getOperand(0), Lo, Hi); 1243 EVT InVT = Lo.getValueType(); 1244 1245 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1246 InVT.getVectorNumElements()); 1247 1248 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); 1249 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); 1250 1251 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); 1252} 1253 1254 1255 1256//===----------------------------------------------------------------------===// 1257// Result Vector Widening 1258//===----------------------------------------------------------------------===// 1259 1260void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { 1261 DEBUG(dbgs() << "Widen node result " << ResNo << ": "; 1262 N->dump(&DAG); 1263 dbgs() << "\n"); 1264 1265 // See if the target wants to custom widen this node. 1266 if (CustomWidenLowerNode(N, N->getValueType(ResNo))) 1267 return; 1268 1269 SDValue Res = SDValue(); 1270 switch (N->getOpcode()) { 1271 default: 1272#ifndef NDEBUG 1273 dbgs() << "WidenVectorResult #" << ResNo << ": "; 1274 N->dump(&DAG); 1275 dbgs() << "\n"; 1276#endif 1277 llvm_unreachable("Do not know how to widen the result of this operator!"); 1278 1279 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break; 1280 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break; 1281 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; 1282 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break; 1283 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break; 1284 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; 1285 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break; 1286 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; 1287 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break; 1288 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break; 1289 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break; 1290 case ISD::VSELECT: 1291 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break; 1292 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; 1293 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; 1294 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break; 1295 case ISD::VECTOR_SHUFFLE: 1296 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N)); 1297 break; 1298 case ISD::ADD: 1299 case ISD::AND: 1300 case ISD::BSWAP: 1301 case ISD::FADD: 1302 case ISD::FCOPYSIGN: 1303 case ISD::FDIV: 1304 case ISD::FMUL: 1305 case ISD::FPOW: 1306 case ISD::FREM: 1307 case ISD::FSUB: 1308 case ISD::MUL: 1309 case ISD::MULHS: 1310 case ISD::MULHU: 1311 case ISD::OR: 1312 case ISD::SDIV: 1313 case ISD::SREM: 1314 case ISD::UDIV: 1315 case ISD::UREM: 1316 case ISD::SUB: 1317 case ISD::XOR: 1318 Res = WidenVecRes_Binary(N); 1319 break; 1320 1321 case ISD::FPOWI: 1322 Res = WidenVecRes_POWI(N); 1323 break; 1324 1325 case ISD::SHL: 1326 case ISD::SRA: 1327 case ISD::SRL: 1328 Res = WidenVecRes_Shift(N); 1329 break; 1330 1331 case ISD::ANY_EXTEND: 1332 case ISD::FP_EXTEND: 1333 case ISD::FP_ROUND: 1334 case ISD::FP_TO_SINT: 1335 case ISD::FP_TO_UINT: 1336 case ISD::SIGN_EXTEND: 1337 case ISD::SINT_TO_FP: 1338 case ISD::TRUNCATE: 1339 case ISD::UINT_TO_FP: 1340 case ISD::ZERO_EXTEND: 1341 Res = WidenVecRes_Convert(N); 1342 break; 1343 1344 case ISD::CTLZ: 1345 case ISD::CTPOP: 1346 case ISD::CTTZ: 1347 case ISD::FABS: 1348 case ISD::FCEIL: 1349 case ISD::FCOS: 1350 case ISD::FEXP: 1351 case ISD::FEXP2: 1352 case ISD::FFLOOR: 1353 case ISD::FLOG: 1354 case ISD::FLOG10: 1355 case ISD::FLOG2: 1356 case ISD::FNEARBYINT: 1357 case ISD::FNEG: 1358 case ISD::FRINT: 1359 case ISD::FSIN: 1360 case ISD::FSQRT: 1361 case ISD::FTRUNC: 1362 Res = WidenVecRes_Unary(N); 1363 break; 1364 } 1365 1366 // If Res is null, the sub-method took care of registering the result. 1367 if (Res.getNode()) 1368 SetWidenedVector(SDValue(N, ResNo), Res); 1369} 1370 1371SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) { 1372 // Binary op widening. 1373 unsigned Opcode = N->getOpcode(); 1374 DebugLoc dl = N->getDebugLoc(); 1375 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1376 EVT WidenEltVT = WidenVT.getVectorElementType(); 1377 EVT VT = WidenVT; 1378 unsigned NumElts = VT.getVectorNumElements(); 1379 while (!TLI.isTypeLegal(VT) && NumElts != 1) { 1380 NumElts = NumElts / 2; 1381 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1382 } 1383 1384 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) { 1385 // Operation doesn't trap so just widen as normal. 1386 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1387 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1388 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2); 1389 } 1390 1391 // No legal vector version so unroll the vector operation and then widen. 1392 if (NumElts == 1) 1393 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()); 1394 1395 // Since the operation can trap, apply operation on the original vector. 1396 EVT MaxVT = VT; 1397 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1398 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1399 unsigned CurNumElts = N->getValueType(0).getVectorNumElements(); 1400 1401 SmallVector<SDValue, 16> ConcatOps(CurNumElts); 1402 unsigned ConcatEnd = 0; // Current ConcatOps index. 1403 int Idx = 0; // Current Idx into input vectors. 1404 1405 // NumElts := greatest legal vector size (at most WidenVT) 1406 // while (orig. vector has unhandled elements) { 1407 // take munches of size NumElts from the beginning and add to ConcatOps 1408 // NumElts := next smaller supported vector size or 1 1409 // } 1410 while (CurNumElts != 0) { 1411 while (CurNumElts >= NumElts) { 1412 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, 1413 DAG.getIntPtrConstant(Idx)); 1414 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, 1415 DAG.getIntPtrConstant(Idx)); 1416 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2); 1417 Idx += NumElts; 1418 CurNumElts -= NumElts; 1419 } 1420 do { 1421 NumElts = NumElts / 2; 1422 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1423 } while (!TLI.isTypeLegal(VT) && NumElts != 1); 1424 1425 if (NumElts == 1) { 1426 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) { 1427 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1428 InOp1, DAG.getIntPtrConstant(Idx)); 1429 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1430 InOp2, DAG.getIntPtrConstant(Idx)); 1431 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT, 1432 EOp1, EOp2); 1433 } 1434 CurNumElts = 0; 1435 } 1436 } 1437 1438 // Check to see if we have a single operation with the widen type. 1439 if (ConcatEnd == 1) { 1440 VT = ConcatOps[0].getValueType(); 1441 if (VT == WidenVT) 1442 return ConcatOps[0]; 1443 } 1444 1445 // while (Some element of ConcatOps is not of type MaxVT) { 1446 // From the end of ConcatOps, collect elements of the same type and put 1447 // them into an op of the next larger supported type 1448 // } 1449 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) { 1450 Idx = ConcatEnd - 1; 1451 VT = ConcatOps[Idx--].getValueType(); 1452 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT) 1453 Idx--; 1454 1455 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1; 1456 EVT NextVT; 1457 do { 1458 NextSize *= 2; 1459 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize); 1460 } while (!TLI.isTypeLegal(NextVT)); 1461 1462 if (!VT.isVector()) { 1463 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT 1464 SDValue VecOp = DAG.getUNDEF(NextVT); 1465 unsigned NumToInsert = ConcatEnd - Idx - 1; 1466 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) { 1467 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, 1468 ConcatOps[OpIdx], DAG.getIntPtrConstant(i)); 1469 } 1470 ConcatOps[Idx+1] = VecOp; 1471 ConcatEnd = Idx + 2; 1472 } else { 1473 // Vector type, create a CONCAT_VECTORS of type NextVT 1474 SDValue undefVec = DAG.getUNDEF(VT); 1475 unsigned OpsToConcat = NextSize/VT.getVectorNumElements(); 1476 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat); 1477 unsigned RealVals = ConcatEnd - Idx - 1; 1478 unsigned SubConcatEnd = 0; 1479 unsigned SubConcatIdx = Idx + 1; 1480 while (SubConcatEnd < RealVals) 1481 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx]; 1482 while (SubConcatEnd < OpsToConcat) 1483 SubConcatOps[SubConcatEnd++] = undefVec; 1484 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1485 NextVT, &SubConcatOps[0], 1486 OpsToConcat); 1487 ConcatEnd = SubConcatIdx + 1; 1488 } 1489 } 1490 1491 // Check to see if we have a single operation with the widen type. 1492 if (ConcatEnd == 1) { 1493 VT = ConcatOps[0].getValueType(); 1494 if (VT == WidenVT) 1495 return ConcatOps[0]; 1496 } 1497 1498 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT 1499 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements(); 1500 if (NumOps != ConcatEnd ) { 1501 SDValue UndefVal = DAG.getUNDEF(MaxVT); 1502 for (unsigned j = ConcatEnd; j < NumOps; ++j) 1503 ConcatOps[j] = UndefVal; 1504 } 1505 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps); 1506} 1507 1508SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { 1509 SDValue InOp = N->getOperand(0); 1510 DebugLoc DL = N->getDebugLoc(); 1511 1512 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1513 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1514 1515 EVT InVT = InOp.getValueType(); 1516 EVT InEltVT = InVT.getVectorElementType(); 1517 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1518 1519 unsigned Opcode = N->getOpcode(); 1520 unsigned InVTNumElts = InVT.getVectorNumElements(); 1521 1522 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1523 InOp = GetWidenedVector(N->getOperand(0)); 1524 InVT = InOp.getValueType(); 1525 InVTNumElts = InVT.getVectorNumElements(); 1526 if (InVTNumElts == WidenNumElts) { 1527 if (N->getNumOperands() == 1) 1528 return DAG.getNode(Opcode, DL, WidenVT, InOp); 1529 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1)); 1530 } 1531 } 1532 1533 if (TLI.isTypeLegal(InWidenVT)) { 1534 // Because the result and the input are different vector types, widening 1535 // the result could create a legal type but widening the input might make 1536 // it an illegal type that might lead to repeatedly splitting the input 1537 // and then widening it. To avoid this, we widen the input only if 1538 // it results in a legal type. 1539 if (WidenNumElts % InVTNumElts == 0) { 1540 // Widen the input and call convert on the widened input vector. 1541 unsigned NumConcat = WidenNumElts/InVTNumElts; 1542 SmallVector<SDValue, 16> Ops(NumConcat); 1543 Ops[0] = InOp; 1544 SDValue UndefVal = DAG.getUNDEF(InVT); 1545 for (unsigned i = 1; i != NumConcat; ++i) 1546 Ops[i] = UndefVal; 1547 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, 1548 &Ops[0], NumConcat); 1549 if (N->getNumOperands() == 1) 1550 return DAG.getNode(Opcode, DL, WidenVT, InVec); 1551 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1)); 1552 } 1553 1554 if (InVTNumElts % WidenNumElts == 0) { 1555 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, 1556 InOp, DAG.getIntPtrConstant(0)); 1557 // Extract the input and convert the shorten input vector. 1558 if (N->getNumOperands() == 1) 1559 return DAG.getNode(Opcode, DL, WidenVT, InVal); 1560 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1)); 1561 } 1562 } 1563 1564 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1565 SmallVector<SDValue, 16> Ops(WidenNumElts); 1566 EVT EltVT = WidenVT.getVectorElementType(); 1567 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1568 unsigned i; 1569 for (i=0; i < MinElts; ++i) { 1570 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp, 1571 DAG.getIntPtrConstant(i)); 1572 if (N->getNumOperands() == 1) 1573 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val); 1574 else 1575 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1)); 1576 } 1577 1578 SDValue UndefVal = DAG.getUNDEF(EltVT); 1579 for (; i < WidenNumElts; ++i) 1580 Ops[i] = UndefVal; 1581 1582 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts); 1583} 1584 1585SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) { 1586 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1587 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1588 SDValue ShOp = N->getOperand(1); 1589 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1590} 1591 1592SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) { 1593 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1594 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1595 SDValue ShOp = N->getOperand(1); 1596 1597 EVT ShVT = ShOp.getValueType(); 1598 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) { 1599 ShOp = GetWidenedVector(ShOp); 1600 ShVT = ShOp.getValueType(); 1601 } 1602 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(), 1603 ShVT.getVectorElementType(), 1604 WidenVT.getVectorNumElements()); 1605 if (ShVT != ShWidenVT) 1606 ShOp = ModifyToType(ShOp, ShWidenVT); 1607 1608 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1609} 1610 1611SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) { 1612 // Unary op widening. 1613 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1614 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1615 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp); 1616} 1617 1618SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) { 1619 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1620 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), 1621 cast<VTSDNode>(N->getOperand(1))->getVT() 1622 .getVectorElementType(), 1623 WidenVT.getVectorNumElements()); 1624 SDValue WidenLHS = GetWidenedVector(N->getOperand(0)); 1625 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 1626 WidenVT, WidenLHS, DAG.getValueType(ExtVT)); 1627} 1628 1629SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) { 1630 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo); 1631 return GetWidenedVector(WidenVec); 1632} 1633 1634SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) { 1635 SDValue InOp = N->getOperand(0); 1636 EVT InVT = InOp.getValueType(); 1637 EVT VT = N->getValueType(0); 1638 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1639 DebugLoc dl = N->getDebugLoc(); 1640 1641 switch (getTypeAction(InVT)) { 1642 case TargetLowering::TypeLegal: 1643 break; 1644 case TargetLowering::TypePromoteInteger: 1645 // If the incoming type is a vector that is being promoted, then 1646 // we know that the elements are arranged differently and that we 1647 // must perform the conversion using a stack slot. 1648 if (InVT.isVector()) 1649 break; 1650 1651 // If the InOp is promoted to the same size, convert it. Otherwise, 1652 // fall out of the switch and widen the promoted input. 1653 InOp = GetPromotedInteger(InOp); 1654 InVT = InOp.getValueType(); 1655 if (WidenVT.bitsEq(InVT)) 1656 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1657 break; 1658 case TargetLowering::TypeSoftenFloat: 1659 case TargetLowering::TypeExpandInteger: 1660 case TargetLowering::TypeExpandFloat: 1661 case TargetLowering::TypeScalarizeVector: 1662 case TargetLowering::TypeSplitVector: 1663 break; 1664 case TargetLowering::TypeWidenVector: 1665 // If the InOp is widened to the same size, convert it. Otherwise, fall 1666 // out of the switch and widen the widened input. 1667 InOp = GetWidenedVector(InOp); 1668 InVT = InOp.getValueType(); 1669 if (WidenVT.bitsEq(InVT)) 1670 // The input widens to the same size. Convert to the widen value. 1671 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1672 break; 1673 } 1674 1675 unsigned WidenSize = WidenVT.getSizeInBits(); 1676 unsigned InSize = InVT.getSizeInBits(); 1677 // x86mmx is not an acceptable vector element type, so don't try. 1678 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) { 1679 // Determine new input vector type. The new input vector type will use 1680 // the same element type (if its a vector) or use the input type as a 1681 // vector. It is the same size as the type to widen to. 1682 EVT NewInVT; 1683 unsigned NewNumElts = WidenSize / InSize; 1684 if (InVT.isVector()) { 1685 EVT InEltVT = InVT.getVectorElementType(); 1686 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, 1687 WidenSize / InEltVT.getSizeInBits()); 1688 } else { 1689 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts); 1690 } 1691 1692 if (TLI.isTypeLegal(NewInVT)) { 1693 // Because the result and the input are different vector types, widening 1694 // the result could create a legal type but widening the input might make 1695 // it an illegal type that might lead to repeatedly splitting the input 1696 // and then widening it. To avoid this, we widen the input only if 1697 // it results in a legal type. 1698 SmallVector<SDValue, 16> Ops(NewNumElts); 1699 SDValue UndefVal = DAG.getUNDEF(InVT); 1700 Ops[0] = InOp; 1701 for (unsigned i = 1; i < NewNumElts; ++i) 1702 Ops[i] = UndefVal; 1703 1704 SDValue NewVec; 1705 if (InVT.isVector()) 1706 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1707 NewInVT, &Ops[0], NewNumElts); 1708 else 1709 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, 1710 NewInVT, &Ops[0], NewNumElts); 1711 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec); 1712 } 1713 } 1714 1715 return CreateStackStoreLoad(InOp, WidenVT); 1716} 1717 1718SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) { 1719 DebugLoc dl = N->getDebugLoc(); 1720 // Build a vector with undefined for the new nodes. 1721 EVT VT = N->getValueType(0); 1722 EVT EltVT = VT.getVectorElementType(); 1723 unsigned NumElts = VT.getVectorNumElements(); 1724 1725 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1726 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1727 1728 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end()); 1729 NewOps.reserve(WidenNumElts); 1730 for (unsigned i = NumElts; i < WidenNumElts; ++i) 1731 NewOps.push_back(DAG.getUNDEF(EltVT)); 1732 1733 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size()); 1734} 1735 1736SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) { 1737 EVT InVT = N->getOperand(0).getValueType(); 1738 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1739 DebugLoc dl = N->getDebugLoc(); 1740 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1741 unsigned NumInElts = InVT.getVectorNumElements(); 1742 unsigned NumOperands = N->getNumOperands(); 1743 1744 bool InputWidened = false; // Indicates we need to widen the input. 1745 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) { 1746 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) { 1747 // Add undef vectors to widen to correct length. 1748 unsigned NumConcat = WidenVT.getVectorNumElements() / 1749 InVT.getVectorNumElements(); 1750 SDValue UndefVal = DAG.getUNDEF(InVT); 1751 SmallVector<SDValue, 16> Ops(NumConcat); 1752 for (unsigned i=0; i < NumOperands; ++i) 1753 Ops[i] = N->getOperand(i); 1754 for (unsigned i = NumOperands; i != NumConcat; ++i) 1755 Ops[i] = UndefVal; 1756 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat); 1757 } 1758 } else { 1759 InputWidened = true; 1760 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) { 1761 // The inputs and the result are widen to the same value. 1762 unsigned i; 1763 for (i=1; i < NumOperands; ++i) 1764 if (N->getOperand(i).getOpcode() != ISD::UNDEF) 1765 break; 1766 1767 if (i == NumOperands) 1768 // Everything but the first operand is an UNDEF so just return the 1769 // widened first operand. 1770 return GetWidenedVector(N->getOperand(0)); 1771 1772 if (NumOperands == 2) { 1773 // Replace concat of two operands with a shuffle. 1774 SmallVector<int, 16> MaskOps(WidenNumElts, -1); 1775 for (unsigned i = 0; i < NumInElts; ++i) { 1776 MaskOps[i] = i; 1777 MaskOps[i + NumInElts] = i + WidenNumElts; 1778 } 1779 return DAG.getVectorShuffle(WidenVT, dl, 1780 GetWidenedVector(N->getOperand(0)), 1781 GetWidenedVector(N->getOperand(1)), 1782 &MaskOps[0]); 1783 } 1784 } 1785 } 1786 1787 // Fall back to use extracts and build vector. 1788 EVT EltVT = WidenVT.getVectorElementType(); 1789 SmallVector<SDValue, 16> Ops(WidenNumElts); 1790 unsigned Idx = 0; 1791 for (unsigned i=0; i < NumOperands; ++i) { 1792 SDValue InOp = N->getOperand(i); 1793 if (InputWidened) 1794 InOp = GetWidenedVector(InOp); 1795 for (unsigned j=0; j < NumInElts; ++j) 1796 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1797 DAG.getIntPtrConstant(j)); 1798 } 1799 SDValue UndefVal = DAG.getUNDEF(EltVT); 1800 for (; Idx < WidenNumElts; ++Idx) 1801 Ops[Idx] = UndefVal; 1802 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1803} 1804 1805SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { 1806 DebugLoc dl = N->getDebugLoc(); 1807 SDValue InOp = N->getOperand(0); 1808 SDValue RndOp = N->getOperand(3); 1809 SDValue SatOp = N->getOperand(4); 1810 1811 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1812 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1813 1814 EVT InVT = InOp.getValueType(); 1815 EVT InEltVT = InVT.getVectorElementType(); 1816 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1817 1818 SDValue DTyOp = DAG.getValueType(WidenVT); 1819 SDValue STyOp = DAG.getValueType(InWidenVT); 1820 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 1821 1822 unsigned InVTNumElts = InVT.getVectorNumElements(); 1823 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1824 InOp = GetWidenedVector(InOp); 1825 InVT = InOp.getValueType(); 1826 InVTNumElts = InVT.getVectorNumElements(); 1827 if (InVTNumElts == WidenNumElts) 1828 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1829 SatOp, CvtCode); 1830 } 1831 1832 if (TLI.isTypeLegal(InWidenVT)) { 1833 // Because the result and the input are different vector types, widening 1834 // the result could create a legal type but widening the input might make 1835 // it an illegal type that might lead to repeatedly splitting the input 1836 // and then widening it. To avoid this, we widen the input only if 1837 // it results in a legal type. 1838 if (WidenNumElts % InVTNumElts == 0) { 1839 // Widen the input and call convert on the widened input vector. 1840 unsigned NumConcat = WidenNumElts/InVTNumElts; 1841 SmallVector<SDValue, 16> Ops(NumConcat); 1842 Ops[0] = InOp; 1843 SDValue UndefVal = DAG.getUNDEF(InVT); 1844 for (unsigned i = 1; i != NumConcat; ++i) 1845 Ops[i] = UndefVal; 1846 1847 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat); 1848 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1849 SatOp, CvtCode); 1850 } 1851 1852 if (InVTNumElts % WidenNumElts == 0) { 1853 // Extract the input and convert the shorten input vector. 1854 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp, 1855 DAG.getIntPtrConstant(0)); 1856 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1857 SatOp, CvtCode); 1858 } 1859 } 1860 1861 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1862 SmallVector<SDValue, 16> Ops(WidenNumElts); 1863 EVT EltVT = WidenVT.getVectorElementType(); 1864 DTyOp = DAG.getValueType(EltVT); 1865 STyOp = DAG.getValueType(InEltVT); 1866 1867 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1868 unsigned i; 1869 for (i=0; i < MinElts; ++i) { 1870 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 1871 DAG.getIntPtrConstant(i)); 1872 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp, 1873 SatOp, CvtCode); 1874 } 1875 1876 SDValue UndefVal = DAG.getUNDEF(EltVT); 1877 for (; i < WidenNumElts; ++i) 1878 Ops[i] = UndefVal; 1879 1880 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1881} 1882 1883SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 1884 EVT VT = N->getValueType(0); 1885 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1886 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1887 SDValue InOp = N->getOperand(0); 1888 SDValue Idx = N->getOperand(1); 1889 DebugLoc dl = N->getDebugLoc(); 1890 1891 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 1892 InOp = GetWidenedVector(InOp); 1893 1894 EVT InVT = InOp.getValueType(); 1895 1896 // Check if we can just return the input vector after widening. 1897 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1898 if (IdxVal == 0 && InVT == WidenVT) 1899 return InOp; 1900 1901 // Check if we can extract from the vector. 1902 unsigned InNumElts = InVT.getVectorNumElements(); 1903 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts) 1904 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx); 1905 1906 // We could try widening the input to the right length but for now, extract 1907 // the original elements, fill the rest with undefs and build a vector. 1908 SmallVector<SDValue, 16> Ops(WidenNumElts); 1909 EVT EltVT = VT.getVectorElementType(); 1910 unsigned NumElts = VT.getVectorNumElements(); 1911 unsigned i; 1912 for (i=0; i < NumElts; ++i) 1913 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1914 DAG.getIntPtrConstant(IdxVal+i)); 1915 1916 SDValue UndefVal = DAG.getUNDEF(EltVT); 1917 for (; i < WidenNumElts; ++i) 1918 Ops[i] = UndefVal; 1919 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1920} 1921 1922SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) { 1923 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1924 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(), 1925 InOp.getValueType(), InOp, 1926 N->getOperand(1), N->getOperand(2)); 1927} 1928 1929SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) { 1930 LoadSDNode *LD = cast<LoadSDNode>(N); 1931 ISD::LoadExtType ExtType = LD->getExtensionType(); 1932 1933 SDValue Result; 1934 SmallVector<SDValue, 16> LdChain; // Chain for the series of load 1935 if (ExtType != ISD::NON_EXTLOAD) 1936 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); 1937 else 1938 Result = GenWidenVectorLoads(LdChain, LD); 1939 1940 // If we generate a single load, we can use that for the chain. Otherwise, 1941 // build a factor node to remember the multiple loads are independent and 1942 // chain to that. 1943 SDValue NewChain; 1944 if (LdChain.size() == 1) 1945 NewChain = LdChain[0]; 1946 else 1947 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other, 1948 &LdChain[0], LdChain.size()); 1949 1950 // Modified the chain - switch anything that used the old chain to use 1951 // the new one. 1952 ReplaceValueWith(SDValue(N, 1), NewChain); 1953 1954 return Result; 1955} 1956 1957SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) { 1958 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1959 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(), 1960 WidenVT, N->getOperand(0)); 1961} 1962 1963SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) { 1964 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1965 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1966 1967 SDValue Cond1 = N->getOperand(0); 1968 EVT CondVT = Cond1.getValueType(); 1969 if (CondVT.isVector()) { 1970 EVT CondEltVT = CondVT.getVectorElementType(); 1971 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), 1972 CondEltVT, WidenNumElts); 1973 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector) 1974 Cond1 = GetWidenedVector(Cond1); 1975 1976 if (Cond1.getValueType() != CondWidenVT) 1977 Cond1 = ModifyToType(Cond1, CondWidenVT); 1978 } 1979 1980 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 1981 SDValue InOp2 = GetWidenedVector(N->getOperand(2)); 1982 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT); 1983 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 1984 WidenVT, Cond1, InOp1, InOp2); 1985} 1986 1987SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) { 1988 SDValue InOp1 = GetWidenedVector(N->getOperand(2)); 1989 SDValue InOp2 = GetWidenedVector(N->getOperand(3)); 1990 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 1991 InOp1.getValueType(), N->getOperand(0), 1992 N->getOperand(1), InOp1, InOp2, N->getOperand(4)); 1993} 1994 1995SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) { 1996 assert(N->getValueType(0).isVector() == 1997 N->getOperand(0).getValueType().isVector() && 1998 "Scalar/Vector type mismatch"); 1999 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N); 2000 2001 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2002 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 2003 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 2004 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT, 2005 InOp1, InOp2, N->getOperand(2)); 2006} 2007 2008SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) { 2009 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2010 return DAG.getUNDEF(WidenVT); 2011} 2012 2013SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) { 2014 EVT VT = N->getValueType(0); 2015 DebugLoc dl = N->getDebugLoc(); 2016 2017 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2018 unsigned NumElts = VT.getVectorNumElements(); 2019 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2020 2021 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 2022 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 2023 2024 // Adjust mask based on new input vector length. 2025 SmallVector<int, 16> NewMask; 2026 for (unsigned i = 0; i != NumElts; ++i) { 2027 int Idx = N->getMaskElt(i); 2028 if (Idx < (int)NumElts) 2029 NewMask.push_back(Idx); 2030 else 2031 NewMask.push_back(Idx - NumElts + WidenNumElts); 2032 } 2033 for (unsigned i = NumElts; i != WidenNumElts; ++i) 2034 NewMask.push_back(-1); 2035 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]); 2036} 2037 2038SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) { 2039 assert(N->getValueType(0).isVector() && 2040 N->getOperand(0).getValueType().isVector() && 2041 "Operands must be vectors"); 2042 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2043 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2044 2045 SDValue InOp1 = N->getOperand(0); 2046 EVT InVT = InOp1.getValueType(); 2047 assert(InVT.isVector() && "can not widen non vector type"); 2048 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(), 2049 InVT.getVectorElementType(), WidenNumElts); 2050 InOp1 = GetWidenedVector(InOp1); 2051 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 2052 2053 // Assume that the input and output will be widen appropriately. If not, 2054 // we will have to unroll it at some point. 2055 assert(InOp1.getValueType() == WidenInVT && 2056 InOp2.getValueType() == WidenInVT && 2057 "Input not widened to expected type!"); 2058 (void)WidenInVT; 2059 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), 2060 WidenVT, InOp1, InOp2, N->getOperand(2)); 2061} 2062 2063 2064//===----------------------------------------------------------------------===// 2065// Widen Vector Operand 2066//===----------------------------------------------------------------------===// 2067bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) { 2068 DEBUG(dbgs() << "Widen node operand " << ResNo << ": "; 2069 N->dump(&DAG); 2070 dbgs() << "\n"); 2071 SDValue Res = SDValue(); 2072 2073 switch (N->getOpcode()) { 2074 default: 2075#ifndef NDEBUG 2076 dbgs() << "WidenVectorOperand op #" << ResNo << ": "; 2077 N->dump(&DAG); 2078 dbgs() << "\n"; 2079#endif 2080 llvm_unreachable("Do not know how to widen this operator's operand!"); 2081 2082 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break; 2083 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break; 2084 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break; 2085 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break; 2086 case ISD::STORE: Res = WidenVecOp_STORE(N); break; 2087 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break; 2088 2089 case ISD::FP_EXTEND: 2090 case ISD::FP_TO_SINT: 2091 case ISD::FP_TO_UINT: 2092 case ISD::SINT_TO_FP: 2093 case ISD::UINT_TO_FP: 2094 case ISD::TRUNCATE: 2095 case ISD::SIGN_EXTEND: 2096 case ISD::ZERO_EXTEND: 2097 case ISD::ANY_EXTEND: 2098 Res = WidenVecOp_Convert(N); 2099 break; 2100 } 2101 2102 // If Res is null, the sub-method took care of registering the result. 2103 if (!Res.getNode()) return false; 2104 2105 // If the result is N, the sub-method updated N in place. Tell the legalizer 2106 // core about this. 2107 if (Res.getNode() == N) 2108 return true; 2109 2110 2111 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2112 "Invalid operand expansion"); 2113 2114 ReplaceValueWith(SDValue(N, 0), Res); 2115 return false; 2116} 2117 2118SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) { 2119 // Since the result is legal and the input is illegal, it is unlikely 2120 // that we can fix the input to a legal type so unroll the convert 2121 // into some scalar code and create a nasty build vector. 2122 EVT VT = N->getValueType(0); 2123 EVT EltVT = VT.getVectorElementType(); 2124 DebugLoc dl = N->getDebugLoc(); 2125 unsigned NumElts = VT.getVectorNumElements(); 2126 SDValue InOp = N->getOperand(0); 2127 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2128 InOp = GetWidenedVector(InOp); 2129 EVT InVT = InOp.getValueType(); 2130 EVT InEltVT = InVT.getVectorElementType(); 2131 2132 unsigned Opcode = N->getOpcode(); 2133 SmallVector<SDValue, 16> Ops(NumElts); 2134 for (unsigned i=0; i < NumElts; ++i) 2135 Ops[i] = DAG.getNode(Opcode, dl, EltVT, 2136 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 2137 DAG.getIntPtrConstant(i))); 2138 2139 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2140} 2141 2142SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) { 2143 EVT VT = N->getValueType(0); 2144 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2145 EVT InWidenVT = InOp.getValueType(); 2146 DebugLoc dl = N->getDebugLoc(); 2147 2148 // Check if we can convert between two legal vector types and extract. 2149 unsigned InWidenSize = InWidenVT.getSizeInBits(); 2150 unsigned Size = VT.getSizeInBits(); 2151 // x86mmx is not an acceptable vector element type, so don't try. 2152 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) { 2153 unsigned NewNumElts = InWidenSize / Size; 2154 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); 2155 if (TLI.isTypeLegal(NewVT)) { 2156 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp); 2157 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, 2158 DAG.getIntPtrConstant(0)); 2159 } 2160 } 2161 2162 return CreateStackStoreLoad(InOp, VT); 2163} 2164 2165SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) { 2166 // If the input vector is not legal, it is likely that we will not find a 2167 // legal vector of the same size. Replace the concatenate vector with a 2168 // nasty build vector. 2169 EVT VT = N->getValueType(0); 2170 EVT EltVT = VT.getVectorElementType(); 2171 DebugLoc dl = N->getDebugLoc(); 2172 unsigned NumElts = VT.getVectorNumElements(); 2173 SmallVector<SDValue, 16> Ops(NumElts); 2174 2175 EVT InVT = N->getOperand(0).getValueType(); 2176 unsigned NumInElts = InVT.getVectorNumElements(); 2177 2178 unsigned Idx = 0; 2179 unsigned NumOperands = N->getNumOperands(); 2180 for (unsigned i=0; i < NumOperands; ++i) { 2181 SDValue InOp = N->getOperand(i); 2182 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2183 InOp = GetWidenedVector(InOp); 2184 for (unsigned j=0; j < NumInElts; ++j) 2185 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2186 DAG.getIntPtrConstant(j)); 2187 } 2188 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2189} 2190 2191SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 2192 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2193 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), 2194 N->getValueType(0), InOp, N->getOperand(1)); 2195} 2196 2197SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 2198 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2199 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 2200 N->getValueType(0), InOp, N->getOperand(1)); 2201} 2202 2203SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) { 2204 // We have to widen the value but we want only to store the original 2205 // vector type. 2206 StoreSDNode *ST = cast<StoreSDNode>(N); 2207 2208 SmallVector<SDValue, 16> StChain; 2209 if (ST->isTruncatingStore()) 2210 GenWidenVectorTruncStores(StChain, ST); 2211 else 2212 GenWidenVectorStores(StChain, ST); 2213 2214 if (StChain.size() == 1) 2215 return StChain[0]; 2216 else 2217 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(), 2218 MVT::Other,&StChain[0],StChain.size()); 2219} 2220 2221SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) { 2222 SDValue InOp0 = GetWidenedVector(N->getOperand(0)); 2223 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 2224 DebugLoc dl = N->getDebugLoc(); 2225 2226 // WARNING: In this code we widen the compare instruction with garbage. 2227 // This garbage may contain denormal floats which may be slow. Is this a real 2228 // concern ? Should we zero the unused lanes if this is a float compare ? 2229 2230 // Get a new SETCC node to compare the newly widened operands. 2231 // Only some of the compared elements are legal. 2232 EVT SVT = TLI.getSetCCResultType(InOp0.getValueType()); 2233 SDValue WideSETCC = DAG.getNode(ISD::SETCC, N->getDebugLoc(), 2234 SVT, InOp0, InOp1, N->getOperand(2)); 2235 2236 // Extract the needed results from the result vector. 2237 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), 2238 SVT.getVectorElementType(), 2239 N->getValueType(0).getVectorNumElements()); 2240 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, 2241 ResVT, WideSETCC, DAG.getIntPtrConstant(0)); 2242 2243 return PromoteTargetBoolean(CC, N->getValueType(0)); 2244} 2245 2246 2247//===----------------------------------------------------------------------===// 2248// Vector Widening Utilities 2249//===----------------------------------------------------------------------===// 2250 2251// Utility function to find the type to chop up a widen vector for load/store 2252// TLI: Target lowering used to determine legal types. 2253// Width: Width left need to load/store. 2254// WidenVT: The widen vector type to load to/store from 2255// Align: If 0, don't allow use of a wider type 2256// WidenEx: If Align is not 0, the amount additional we can load/store from. 2257 2258static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, 2259 unsigned Width, EVT WidenVT, 2260 unsigned Align = 0, unsigned WidenEx = 0) { 2261 EVT WidenEltVT = WidenVT.getVectorElementType(); 2262 unsigned WidenWidth = WidenVT.getSizeInBits(); 2263 unsigned WidenEltWidth = WidenEltVT.getSizeInBits(); 2264 unsigned AlignInBits = Align*8; 2265 2266 // If we have one element to load/store, return it. 2267 EVT RetVT = WidenEltVT; 2268 if (Width == WidenEltWidth) 2269 return RetVT; 2270 2271 // See if there is larger legal integer than the element type to load/store 2272 unsigned VT; 2273 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE; 2274 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) { 2275 EVT MemVT((MVT::SimpleValueType) VT); 2276 unsigned MemVTWidth = MemVT.getSizeInBits(); 2277 if (MemVT.getSizeInBits() <= WidenEltWidth) 2278 break; 2279 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 && 2280 isPowerOf2_32(WidenWidth / MemVTWidth) && 2281 (MemVTWidth <= Width || 2282 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2283 RetVT = MemVT; 2284 break; 2285 } 2286 } 2287 2288 // See if there is a larger vector type to load/store that has the same vector 2289 // element type and is evenly divisible with the WidenVT. 2290 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; 2291 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) { 2292 EVT MemVT = (MVT::SimpleValueType) VT; 2293 unsigned MemVTWidth = MemVT.getSizeInBits(); 2294 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() && 2295 (WidenWidth % MemVTWidth) == 0 && 2296 isPowerOf2_32(WidenWidth / MemVTWidth) && 2297 (MemVTWidth <= Width || 2298 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2299 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT) 2300 return MemVT; 2301 } 2302 } 2303 2304 return RetVT; 2305} 2306 2307// Builds a vector type from scalar loads 2308// VecTy: Resulting Vector type 2309// LDOps: Load operators to build a vector type 2310// [Start,End) the list of loads to use. 2311static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, 2312 SmallVector<SDValue, 16>& LdOps, 2313 unsigned Start, unsigned End) { 2314 DebugLoc dl = LdOps[Start].getDebugLoc(); 2315 EVT LdTy = LdOps[Start].getValueType(); 2316 unsigned Width = VecTy.getSizeInBits(); 2317 unsigned NumElts = Width / LdTy.getSizeInBits(); 2318 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts); 2319 2320 unsigned Idx = 1; 2321 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]); 2322 2323 for (unsigned i = Start + 1; i != End; ++i) { 2324 EVT NewLdTy = LdOps[i].getValueType(); 2325 if (NewLdTy != LdTy) { 2326 NumElts = Width / NewLdTy.getSizeInBits(); 2327 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts); 2328 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp); 2329 // Readjust position and vector position based on new load type 2330 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits(); 2331 LdTy = NewLdTy; 2332 } 2333 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], 2334 DAG.getIntPtrConstant(Idx++)); 2335 } 2336 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp); 2337} 2338 2339SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain, 2340 LoadSDNode *LD) { 2341 // The strategy assumes that we can efficiently load powers of two widths. 2342 // The routines chops the vector into the largest vector loads with the same 2343 // element type or scalar loads and then recombines it to the widen vector 2344 // type. 2345 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2346 unsigned WidenWidth = WidenVT.getSizeInBits(); 2347 EVT LdVT = LD->getMemoryVT(); 2348 DebugLoc dl = LD->getDebugLoc(); 2349 assert(LdVT.isVector() && WidenVT.isVector()); 2350 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType()); 2351 2352 // Load information 2353 SDValue Chain = LD->getChain(); 2354 SDValue BasePtr = LD->getBasePtr(); 2355 unsigned Align = LD->getAlignment(); 2356 bool isVolatile = LD->isVolatile(); 2357 bool isNonTemporal = LD->isNonTemporal(); 2358 bool isInvariant = LD->isInvariant(); 2359 2360 int LdWidth = LdVT.getSizeInBits(); 2361 int WidthDiff = WidenWidth - LdWidth; // Difference 2362 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads 2363 2364 // Find the vector type that can load from. 2365 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2366 int NewVTWidth = NewVT.getSizeInBits(); 2367 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(), 2368 isVolatile, isNonTemporal, isInvariant, Align); 2369 LdChain.push_back(LdOp.getValue(1)); 2370 2371 // Check if we can load the element with one instruction 2372 if (LdWidth <= NewVTWidth) { 2373 if (!NewVT.isVector()) { 2374 unsigned NumElts = WidenWidth / NewVTWidth; 2375 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2376 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp); 2377 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp); 2378 } 2379 if (NewVT == WidenVT) 2380 return LdOp; 2381 2382 assert(WidenWidth % NewVTWidth == 0); 2383 unsigned NumConcat = WidenWidth / NewVTWidth; 2384 SmallVector<SDValue, 16> ConcatOps(NumConcat); 2385 SDValue UndefVal = DAG.getUNDEF(NewVT); 2386 ConcatOps[0] = LdOp; 2387 for (unsigned i = 1; i != NumConcat; ++i) 2388 ConcatOps[i] = UndefVal; 2389 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], 2390 NumConcat); 2391 } 2392 2393 // Load vector by using multiple loads from largest vector to scalar 2394 SmallVector<SDValue, 16> LdOps; 2395 LdOps.push_back(LdOp); 2396 2397 LdWidth -= NewVTWidth; 2398 unsigned Offset = 0; 2399 2400 while (LdWidth > 0) { 2401 unsigned Increment = NewVTWidth / 8; 2402 Offset += Increment; 2403 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2404 DAG.getIntPtrConstant(Increment)); 2405 2406 SDValue L; 2407 if (LdWidth < NewVTWidth) { 2408 // Our current type we are using is too large, find a better size 2409 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2410 NewVTWidth = NewVT.getSizeInBits(); 2411 L = DAG.getLoad(NewVT, dl, Chain, BasePtr, 2412 LD->getPointerInfo().getWithOffset(Offset), 2413 isVolatile, 2414 isNonTemporal, isInvariant, 2415 MinAlign(Align, Increment)); 2416 LdChain.push_back(L.getValue(1)); 2417 if (L->getValueType(0).isVector()) { 2418 SmallVector<SDValue, 16> Loads; 2419 Loads.push_back(L); 2420 unsigned size = L->getValueSizeInBits(0); 2421 while (size < LdOp->getValueSizeInBits(0)) { 2422 Loads.push_back(DAG.getUNDEF(L->getValueType(0))); 2423 size += L->getValueSizeInBits(0); 2424 } 2425 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), 2426 &Loads[0], Loads.size()); 2427 } 2428 } else { 2429 L = DAG.getLoad(NewVT, dl, Chain, BasePtr, 2430 LD->getPointerInfo().getWithOffset(Offset), isVolatile, 2431 isNonTemporal, isInvariant, MinAlign(Align, Increment)); 2432 LdChain.push_back(L.getValue(1)); 2433 } 2434 2435 LdOps.push_back(L); 2436 2437 2438 LdWidth -= NewVTWidth; 2439 } 2440 2441 // Build the vector from the loads operations 2442 unsigned End = LdOps.size(); 2443 if (!LdOps[0].getValueType().isVector()) 2444 // All the loads are scalar loads. 2445 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End); 2446 2447 // If the load contains vectors, build the vector using concat vector. 2448 // All of the vectors used to loads are power of 2 and the scalars load 2449 // can be combined to make a power of 2 vector. 2450 SmallVector<SDValue, 16> ConcatOps(End); 2451 int i = End - 1; 2452 int Idx = End; 2453 EVT LdTy = LdOps[i].getValueType(); 2454 // First combine the scalar loads to a vector 2455 if (!LdTy.isVector()) { 2456 for (--i; i >= 0; --i) { 2457 LdTy = LdOps[i].getValueType(); 2458 if (LdTy.isVector()) 2459 break; 2460 } 2461 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End); 2462 } 2463 ConcatOps[--Idx] = LdOps[i]; 2464 for (--i; i >= 0; --i) { 2465 EVT NewLdTy = LdOps[i].getValueType(); 2466 if (NewLdTy != LdTy) { 2467 // Create a larger vector 2468 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy, 2469 &ConcatOps[Idx], End - Idx); 2470 Idx = End - 1; 2471 LdTy = NewLdTy; 2472 } 2473 ConcatOps[--Idx] = LdOps[i]; 2474 } 2475 2476 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx)) 2477 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, 2478 &ConcatOps[Idx], End - Idx); 2479 2480 // We need to fill the rest with undefs to build the vector 2481 unsigned NumOps = WidenWidth / LdTy.getSizeInBits(); 2482 SmallVector<SDValue, 16> WidenOps(NumOps); 2483 SDValue UndefVal = DAG.getUNDEF(LdTy); 2484 { 2485 unsigned i = 0; 2486 for (; i != End-Idx; ++i) 2487 WidenOps[i] = ConcatOps[Idx+i]; 2488 for (; i != NumOps; ++i) 2489 WidenOps[i] = UndefVal; 2490 } 2491 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps); 2492} 2493 2494SDValue 2495DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain, 2496 LoadSDNode * LD, 2497 ISD::LoadExtType ExtType) { 2498 // For extension loads, it may not be more efficient to chop up the vector 2499 // and then extended it. Instead, we unroll the load and build a new vector. 2500 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2501 EVT LdVT = LD->getMemoryVT(); 2502 DebugLoc dl = LD->getDebugLoc(); 2503 assert(LdVT.isVector() && WidenVT.isVector()); 2504 2505 // Load information 2506 SDValue Chain = LD->getChain(); 2507 SDValue BasePtr = LD->getBasePtr(); 2508 unsigned Align = LD->getAlignment(); 2509 bool isVolatile = LD->isVolatile(); 2510 bool isNonTemporal = LD->isNonTemporal(); 2511 2512 EVT EltVT = WidenVT.getVectorElementType(); 2513 EVT LdEltVT = LdVT.getVectorElementType(); 2514 unsigned NumElts = LdVT.getVectorNumElements(); 2515 2516 // Load each element and widen 2517 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2518 SmallVector<SDValue, 16> Ops(WidenNumElts); 2519 unsigned Increment = LdEltVT.getSizeInBits() / 8; 2520 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, 2521 LD->getPointerInfo(), 2522 LdEltVT, isVolatile, isNonTemporal, Align); 2523 LdChain.push_back(Ops[0].getValue(1)); 2524 unsigned i = 0, Offset = Increment; 2525 for (i=1; i < NumElts; ++i, Offset += Increment) { 2526 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2527 BasePtr, DAG.getIntPtrConstant(Offset)); 2528 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, 2529 LD->getPointerInfo().getWithOffset(Offset), LdEltVT, 2530 isVolatile, isNonTemporal, Align); 2531 LdChain.push_back(Ops[i].getValue(1)); 2532 } 2533 2534 // Fill the rest with undefs 2535 SDValue UndefVal = DAG.getUNDEF(EltVT); 2536 for (; i != WidenNumElts; ++i) 2537 Ops[i] = UndefVal; 2538 2539 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size()); 2540} 2541 2542 2543void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, 2544 StoreSDNode *ST) { 2545 // The strategy assumes that we can efficiently store powers of two widths. 2546 // The routines chops the vector into the largest vector stores with the same 2547 // element type or scalar stores. 2548 SDValue Chain = ST->getChain(); 2549 SDValue BasePtr = ST->getBasePtr(); 2550 unsigned Align = ST->getAlignment(); 2551 bool isVolatile = ST->isVolatile(); 2552 bool isNonTemporal = ST->isNonTemporal(); 2553 SDValue ValOp = GetWidenedVector(ST->getValue()); 2554 DebugLoc dl = ST->getDebugLoc(); 2555 2556 EVT StVT = ST->getMemoryVT(); 2557 unsigned StWidth = StVT.getSizeInBits(); 2558 EVT ValVT = ValOp.getValueType(); 2559 unsigned ValWidth = ValVT.getSizeInBits(); 2560 EVT ValEltVT = ValVT.getVectorElementType(); 2561 unsigned ValEltWidth = ValEltVT.getSizeInBits(); 2562 assert(StVT.getVectorElementType() == ValEltVT); 2563 2564 int Idx = 0; // current index to store 2565 unsigned Offset = 0; // offset from base to store 2566 while (StWidth != 0) { 2567 // Find the largest vector type we can store with 2568 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT); 2569 unsigned NewVTWidth = NewVT.getSizeInBits(); 2570 unsigned Increment = NewVTWidth / 8; 2571 if (NewVT.isVector()) { 2572 unsigned NumVTElts = NewVT.getVectorNumElements(); 2573 do { 2574 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, 2575 DAG.getIntPtrConstant(Idx)); 2576 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2577 ST->getPointerInfo().getWithOffset(Offset), 2578 isVolatile, isNonTemporal, 2579 MinAlign(Align, Offset))); 2580 StWidth -= NewVTWidth; 2581 Offset += Increment; 2582 Idx += NumVTElts; 2583 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2584 DAG.getIntPtrConstant(Increment)); 2585 } while (StWidth != 0 && StWidth >= NewVTWidth); 2586 } else { 2587 // Cast the vector to the scalar type we can store 2588 unsigned NumElts = ValWidth / NewVTWidth; 2589 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2590 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); 2591 // Readjust index position based on new vector type 2592 Idx = Idx * ValEltWidth / NewVTWidth; 2593 do { 2594 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp, 2595 DAG.getIntPtrConstant(Idx++)); 2596 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2597 ST->getPointerInfo().getWithOffset(Offset), 2598 isVolatile, isNonTemporal, 2599 MinAlign(Align, Offset))); 2600 StWidth -= NewVTWidth; 2601 Offset += Increment; 2602 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2603 DAG.getIntPtrConstant(Increment)); 2604 } while (StWidth != 0 && StWidth >= NewVTWidth); 2605 // Restore index back to be relative to the original widen element type 2606 Idx = Idx * NewVTWidth / ValEltWidth; 2607 } 2608 } 2609} 2610 2611void 2612DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain, 2613 StoreSDNode *ST) { 2614 // For extension loads, it may not be more efficient to truncate the vector 2615 // and then store it. Instead, we extract each element and then store it. 2616 SDValue Chain = ST->getChain(); 2617 SDValue BasePtr = ST->getBasePtr(); 2618 unsigned Align = ST->getAlignment(); 2619 bool isVolatile = ST->isVolatile(); 2620 bool isNonTemporal = ST->isNonTemporal(); 2621 SDValue ValOp = GetWidenedVector(ST->getValue()); 2622 DebugLoc dl = ST->getDebugLoc(); 2623 2624 EVT StVT = ST->getMemoryVT(); 2625 EVT ValVT = ValOp.getValueType(); 2626 2627 // It must be true that we the widen vector type is bigger than where 2628 // we need to store. 2629 assert(StVT.isVector() && ValOp.getValueType().isVector()); 2630 assert(StVT.bitsLT(ValOp.getValueType())); 2631 2632 // For truncating stores, we can not play the tricks of chopping legal 2633 // vector types and bit cast it to the right type. Instead, we unroll 2634 // the store. 2635 EVT StEltVT = StVT.getVectorElementType(); 2636 EVT ValEltVT = ValVT.getVectorElementType(); 2637 unsigned Increment = ValEltVT.getSizeInBits() / 8; 2638 unsigned NumElts = StVT.getVectorNumElements(); 2639 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2640 DAG.getIntPtrConstant(0)); 2641 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, 2642 ST->getPointerInfo(), StEltVT, 2643 isVolatile, isNonTemporal, Align)); 2644 unsigned Offset = Increment; 2645 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) { 2646 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2647 BasePtr, DAG.getIntPtrConstant(Offset)); 2648 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2649 DAG.getIntPtrConstant(0)); 2650 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, 2651 ST->getPointerInfo().getWithOffset(Offset), 2652 StEltVT, isVolatile, isNonTemporal, 2653 MinAlign(Align, Offset))); 2654 } 2655} 2656 2657/// Modifies a vector input (widen or narrows) to a vector of NVT. The 2658/// input vector must have the same element type as NVT. 2659SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) { 2660 // Note that InOp might have been widened so it might already have 2661 // the right width or it might need be narrowed. 2662 EVT InVT = InOp.getValueType(); 2663 assert(InVT.getVectorElementType() == NVT.getVectorElementType() && 2664 "input and widen element type must match"); 2665 DebugLoc dl = InOp.getDebugLoc(); 2666 2667 // Check if InOp already has the right width. 2668 if (InVT == NVT) 2669 return InOp; 2670 2671 unsigned InNumElts = InVT.getVectorNumElements(); 2672 unsigned WidenNumElts = NVT.getVectorNumElements(); 2673 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) { 2674 unsigned NumConcat = WidenNumElts / InNumElts; 2675 SmallVector<SDValue, 16> Ops(NumConcat); 2676 SDValue UndefVal = DAG.getUNDEF(InVT); 2677 Ops[0] = InOp; 2678 for (unsigned i = 1; i != NumConcat; ++i) 2679 Ops[i] = UndefVal; 2680 2681 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat); 2682 } 2683 2684 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts) 2685 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp, 2686 DAG.getIntPtrConstant(0)); 2687 2688 // Fall back to extract and build. 2689 SmallVector<SDValue, 16> Ops(WidenNumElts); 2690 EVT EltVT = NVT.getVectorElementType(); 2691 unsigned MinNumElts = std::min(WidenNumElts, InNumElts); 2692 unsigned Idx; 2693 for (Idx = 0; Idx < MinNumElts; ++Idx) 2694 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2695 DAG.getIntPtrConstant(Idx)); 2696 2697 SDValue UndefVal = DAG.getUNDEF(EltVT); 2698 for ( ; Idx < WidenNumElts; ++Idx) 2699 Ops[Idx] = UndefVal; 2700 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts); 2701} 2702