LegalizeVectorTypes.cpp revision 520b6e3fa5c9c01ed66e70c925e78d518504a983
1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file performs vector type splitting and scalarization for LegalizeTypes. 11// Scalarization is the act of changing a computation in an illegal one-element 12// vector type to be a computation in its scalar element type. For example, 13// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed 14// as a base case when scalarizing vector arithmetic like <4 x f32>, which 15// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32 16// types. 17// Splitting is the act of changing a computation in an invalid vector type to 18// be a computation in two vectors of half the size. For example, implementing 19// <128 x f32> operations in terms of two <64 x f32> operations. 20// 21//===----------------------------------------------------------------------===// 22 23#include "LegalizeTypes.h" 24#include "llvm/IR/DataLayout.h" 25#include "llvm/Support/ErrorHandling.h" 26#include "llvm/Support/raw_ostream.h" 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// Result Vector Scalarization: <1 x ty> -> ty. 31//===----------------------------------------------------------------------===// 32 33void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { 34 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; 35 N->dump(&DAG); 36 dbgs() << "\n"); 37 SDValue R = SDValue(); 38 39 switch (N->getOpcode()) { 40 default: 41#ifndef NDEBUG 42 dbgs() << "ScalarizeVectorResult #" << ResNo << ": "; 43 N->dump(&DAG); 44 dbgs() << "\n"; 45#endif 46 report_fatal_error("Do not know how to scalarize the result of this " 47 "operator!\n"); 48 49 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; 50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 51 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; 52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; 53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; 55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; 56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; 59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; 60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; 61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; 62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break; 63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; 65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; 66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; 67 case ISD::ANY_EXTEND: 68 case ISD::CTLZ: 69 case ISD::CTPOP: 70 case ISD::CTTZ: 71 case ISD::FABS: 72 case ISD::FCEIL: 73 case ISD::FCOS: 74 case ISD::FEXP: 75 case ISD::FEXP2: 76 case ISD::FFLOOR: 77 case ISD::FLOG: 78 case ISD::FLOG10: 79 case ISD::FLOG2: 80 case ISD::FNEARBYINT: 81 case ISD::FNEG: 82 case ISD::FP_EXTEND: 83 case ISD::FP_TO_SINT: 84 case ISD::FP_TO_UINT: 85 case ISD::FRINT: 86 case ISD::FSIN: 87 case ISD::FSQRT: 88 case ISD::FTRUNC: 89 case ISD::SIGN_EXTEND: 90 case ISD::SINT_TO_FP: 91 case ISD::TRUNCATE: 92 case ISD::UINT_TO_FP: 93 case ISD::ZERO_EXTEND: 94 R = ScalarizeVecRes_UnaryOp(N); 95 break; 96 97 case ISD::ADD: 98 case ISD::AND: 99 case ISD::FADD: 100 case ISD::FDIV: 101 case ISD::FMUL: 102 case ISD::FPOW: 103 case ISD::FREM: 104 case ISD::FSUB: 105 case ISD::MUL: 106 case ISD::OR: 107 case ISD::SDIV: 108 case ISD::SREM: 109 case ISD::SUB: 110 case ISD::UDIV: 111 case ISD::UREM: 112 case ISD::XOR: 113 case ISD::SHL: 114 case ISD::SRA: 115 case ISD::SRL: 116 R = ScalarizeVecRes_BinOp(N); 117 break; 118 case ISD::FMA: 119 R = ScalarizeVecRes_TernaryOp(N); 120 break; 121 } 122 123 // If R is null, the sub-method took care of registering the result. 124 if (R.getNode()) 125 SetScalarizedVector(SDValue(N, ResNo), R); 126} 127 128SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { 129 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 130 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 131 return DAG.getNode(N->getOpcode(), SDLoc(N), 132 LHS.getValueType(), LHS, RHS); 133} 134 135SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) { 136 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); 137 SDValue Op1 = GetScalarizedVector(N->getOperand(1)); 138 SDValue Op2 = GetScalarizedVector(N->getOperand(2)); 139 return DAG.getNode(N->getOpcode(), SDLoc(N), 140 Op0.getValueType(), Op0, Op1, Op2); 141} 142 143SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N, 144 unsigned ResNo) { 145 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); 146 return GetScalarizedVector(Op); 147} 148 149SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) { 150 EVT NewVT = N->getValueType(0).getVectorElementType(); 151 return DAG.getNode(ISD::BITCAST, SDLoc(N), 152 NewVT, N->getOperand(0)); 153} 154 155SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) { 156 EVT EltVT = N->getValueType(0).getVectorElementType(); 157 SDValue InOp = N->getOperand(0); 158 // The BUILD_VECTOR operands may be of wider element types and 159 // we may need to truncate them back to the requested return type. 160 if (EltVT.isInteger()) 161 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); 162 return InOp; 163} 164 165SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) { 166 EVT NewVT = N->getValueType(0).getVectorElementType(); 167 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); 168 return DAG.getConvertRndSat(NewVT, SDLoc(N), 169 Op0, DAG.getValueType(NewVT), 170 DAG.getValueType(Op0.getValueType()), 171 N->getOperand(3), 172 N->getOperand(4), 173 cast<CvtRndSatSDNode>(N)->getCvtCode()); 174} 175 176SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 177 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), 178 N->getValueType(0).getVectorElementType(), 179 N->getOperand(0), N->getOperand(1)); 180} 181 182SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) { 183 EVT NewVT = N->getValueType(0).getVectorElementType(); 184 SDValue Op = GetScalarizedVector(N->getOperand(0)); 185 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), 186 NewVT, Op, N->getOperand(1)); 187} 188 189SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) { 190 SDValue Op = GetScalarizedVector(N->getOperand(0)); 191 return DAG.getNode(ISD::FPOWI, SDLoc(N), 192 Op.getValueType(), Op, N->getOperand(1)); 193} 194 195SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { 196 // The value to insert may have a wider type than the vector element type, 197 // so be sure to truncate it to the element type if necessary. 198 SDValue Op = N->getOperand(1); 199 EVT EltVT = N->getValueType(0).getVectorElementType(); 200 if (Op.getValueType() != EltVT) 201 // FIXME: Can this happen for floating point types? 202 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op); 203 return Op; 204} 205 206SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { 207 assert(N->isUnindexed() && "Indexed vector load?"); 208 209 SDValue Result = DAG.getLoad(ISD::UNINDEXED, 210 N->getExtensionType(), 211 N->getValueType(0).getVectorElementType(), 212 SDLoc(N), 213 N->getChain(), N->getBasePtr(), 214 DAG.getUNDEF(N->getBasePtr().getValueType()), 215 N->getPointerInfo(), 216 N->getMemoryVT().getVectorElementType(), 217 N->isVolatile(), N->isNonTemporal(), 218 N->isInvariant(), N->getOriginalAlignment()); 219 220 // Legalized the chain result - switch anything that used the old chain to 221 // use the new one. 222 ReplaceValueWith(SDValue(N, 1), Result.getValue(1)); 223 return Result; 224} 225 226SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { 227 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp. 228 EVT DestVT = N->getValueType(0).getVectorElementType(); 229 SDValue Op = GetScalarizedVector(N->getOperand(0)); 230 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op); 231} 232 233SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) { 234 EVT EltVT = N->getValueType(0).getVectorElementType(); 235 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType(); 236 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 237 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT, 238 LHS, DAG.getValueType(ExtVT)); 239} 240 241SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) { 242 // If the operand is wider than the vector element type then it is implicitly 243 // truncated. Make that explicit here. 244 EVT EltVT = N->getValueType(0).getVectorElementType(); 245 SDValue InOp = N->getOperand(0); 246 if (InOp.getValueType() != EltVT) 247 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); 248 return InOp; 249} 250 251SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) { 252 SDValue Cond = GetScalarizedVector(N->getOperand(0)); 253 SDValue LHS = GetScalarizedVector(N->getOperand(1)); 254 TargetLowering::BooleanContent ScalarBool = TLI.getBooleanContents(false); 255 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true); 256 if (ScalarBool != VecBool) { 257 EVT CondVT = Cond.getValueType(); 258 switch (ScalarBool) { 259 case TargetLowering::UndefinedBooleanContent: 260 break; 261 case TargetLowering::ZeroOrOneBooleanContent: 262 assert(VecBool == TargetLowering::UndefinedBooleanContent || 263 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent); 264 // Vector read from all ones, scalar expects a single 1 so mask. 265 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT, 266 Cond, DAG.getConstant(1, CondVT)); 267 break; 268 case TargetLowering::ZeroOrNegativeOneBooleanContent: 269 assert(VecBool == TargetLowering::UndefinedBooleanContent || 270 VecBool == TargetLowering::ZeroOrOneBooleanContent); 271 // Vector reads from a one, scalar from all ones so sign extend. 272 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT, 273 Cond, DAG.getValueType(MVT::i1)); 274 break; 275 } 276 } 277 return DAG.getNode(ISD::SELECT, SDLoc(N), 278 LHS.getValueType(), Cond, LHS, 279 GetScalarizedVector(N->getOperand(2))); 280} 281 282SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) { 283 SDValue LHS = GetScalarizedVector(N->getOperand(1)); 284 return DAG.getNode(ISD::SELECT, SDLoc(N), 285 LHS.getValueType(), N->getOperand(0), LHS, 286 GetScalarizedVector(N->getOperand(2))); 287} 288 289SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) { 290 SDValue LHS = GetScalarizedVector(N->getOperand(2)); 291 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(), 292 N->getOperand(0), N->getOperand(1), 293 LHS, GetScalarizedVector(N->getOperand(3)), 294 N->getOperand(4)); 295} 296 297SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) { 298 assert(N->getValueType(0).isVector() == 299 N->getOperand(0).getValueType().isVector() && 300 "Scalar/Vector type mismatch"); 301 302 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N); 303 304 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 305 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 306 SDLoc DL(N); 307 308 // Turn it into a scalar SETCC. 309 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); 310} 311 312SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { 313 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 314} 315 316SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { 317 // Figure out if the scalar is the LHS or RHS and return it. 318 SDValue Arg = N->getOperand(2).getOperand(0); 319 if (Arg.getOpcode() == ISD::UNDEF) 320 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 321 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue(); 322 return GetScalarizedVector(N->getOperand(Op)); 323} 324 325SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) { 326 assert(N->getValueType(0).isVector() && 327 N->getOperand(0).getValueType().isVector() && 328 "Operand types must be vectors"); 329 330 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 331 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 332 EVT NVT = N->getValueType(0).getVectorElementType(); 333 SDLoc DL(N); 334 335 // Turn it into a scalar SETCC. 336 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, 337 N->getOperand(2)); 338 // Vectors may have a different boolean contents to scalars. Promote the 339 // value appropriately. 340 ISD::NodeType ExtendCode = 341 TargetLowering::getExtendForContent(TLI.getBooleanContents(true)); 342 return DAG.getNode(ExtendCode, DL, NVT, Res); 343} 344 345 346//===----------------------------------------------------------------------===// 347// Operand Vector Scalarization <1 x ty> -> ty. 348//===----------------------------------------------------------------------===// 349 350bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { 351 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; 352 N->dump(&DAG); 353 dbgs() << "\n"); 354 SDValue Res = SDValue(); 355 356 if (Res.getNode() == 0) { 357 switch (N->getOpcode()) { 358 default: 359#ifndef NDEBUG 360 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": "; 361 N->dump(&DAG); 362 dbgs() << "\n"; 363#endif 364 llvm_unreachable("Do not know how to scalarize this operator's operand!"); 365 case ISD::BITCAST: 366 Res = ScalarizeVecOp_BITCAST(N); 367 break; 368 case ISD::ANY_EXTEND: 369 case ISD::ZERO_EXTEND: 370 case ISD::SIGN_EXTEND: 371 Res = ScalarizeVecOp_EXTEND(N); 372 break; 373 case ISD::CONCAT_VECTORS: 374 Res = ScalarizeVecOp_CONCAT_VECTORS(N); 375 break; 376 case ISD::EXTRACT_VECTOR_ELT: 377 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); 378 break; 379 case ISD::STORE: 380 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); 381 break; 382 } 383 } 384 385 // If the result is null, the sub-method took care of registering results etc. 386 if (!Res.getNode()) return false; 387 388 // If the result is N, the sub-method updated N in place. Tell the legalizer 389 // core about this. 390 if (Res.getNode() == N) 391 return true; 392 393 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 394 "Invalid operand expansion"); 395 396 ReplaceValueWith(SDValue(N, 0), Res); 397 return false; 398} 399 400/// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs 401/// to be scalarized, it must be <1 x ty>. Convert the element instead. 402SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) { 403 SDValue Elt = GetScalarizedVector(N->getOperand(0)); 404 return DAG.getNode(ISD::BITCAST, SDLoc(N), 405 N->getValueType(0), Elt); 406} 407 408/// ScalarizeVecOp_EXTEND - If the value to extend is a vector that needs 409/// to be scalarized, it must be <1 x ty>. Extend the element instead. 410SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTEND(SDNode *N) { 411 assert(N->getValueType(0).getVectorNumElements() == 1 && 412 "Unexected vector type!"); 413 SDValue Elt = GetScalarizedVector(N->getOperand(0)); 414 SmallVector<SDValue, 1> Ops(1); 415 Ops[0] = DAG.getNode(N->getOpcode(), SDLoc(N), 416 N->getValueType(0).getScalarType(), Elt); 417 // Revectorize the result so the types line up with what the uses of this 418 // expression expect. 419 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), 420 &Ops[0], 1); 421} 422 423/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one - 424/// use a BUILD_VECTOR instead. 425SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) { 426 SmallVector<SDValue, 8> Ops(N->getNumOperands()); 427 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 428 Ops[i] = GetScalarizedVector(N->getOperand(i)); 429 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), 430 &Ops[0], Ops.size()); 431} 432 433/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to 434/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the 435/// index. 436SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 437 SDValue Res = GetScalarizedVector(N->getOperand(0)); 438 if (Res.getValueType() != N->getValueType(0)) 439 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), 440 Res); 441 return Res; 442} 443 444/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be 445/// scalarized, it must be <1 x ty>. Just store the element. 446SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ 447 assert(N->isUnindexed() && "Indexed store of one-element vector?"); 448 assert(OpNo == 1 && "Do not know how to scalarize this operand!"); 449 SDLoc dl(N); 450 451 if (N->isTruncatingStore()) 452 return DAG.getTruncStore(N->getChain(), dl, 453 GetScalarizedVector(N->getOperand(1)), 454 N->getBasePtr(), N->getPointerInfo(), 455 N->getMemoryVT().getVectorElementType(), 456 N->isVolatile(), N->isNonTemporal(), 457 N->getAlignment()); 458 459 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)), 460 N->getBasePtr(), N->getPointerInfo(), 461 N->isVolatile(), N->isNonTemporal(), 462 N->getOriginalAlignment()); 463} 464 465 466//===----------------------------------------------------------------------===// 467// Result Vector Splitting 468//===----------------------------------------------------------------------===// 469 470/// SplitVectorResult - This method is called when the specified result of the 471/// specified node is found to need vector splitting. At this point, the node 472/// may also have invalid operands or may have other results that need 473/// legalization, we just know that (at least) one result needs vector 474/// splitting. 475void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { 476 DEBUG(dbgs() << "Split node result: "; 477 N->dump(&DAG); 478 dbgs() << "\n"); 479 SDValue Lo, Hi; 480 481 // See if the target wants to custom expand this node. 482 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 483 return; 484 485 switch (N->getOpcode()) { 486 default: 487#ifndef NDEBUG 488 dbgs() << "SplitVectorResult #" << ResNo << ": "; 489 N->dump(&DAG); 490 dbgs() << "\n"; 491#endif 492 report_fatal_error("Do not know how to split the result of this " 493 "operator!\n"); 494 495 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 496 case ISD::VSELECT: 497 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 498 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 499 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 500 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; 501 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 502 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 503 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; 504 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 505 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; 506 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 507 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break; 508 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 509 case ISD::LOAD: 510 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); 511 break; 512 case ISD::SETCC: 513 SplitVecRes_SETCC(N, Lo, Hi); 514 break; 515 case ISD::VECTOR_SHUFFLE: 516 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); 517 break; 518 519 case ISD::ANY_EXTEND: 520 case ISD::CONVERT_RNDSAT: 521 case ISD::CTLZ: 522 case ISD::CTTZ: 523 case ISD::CTLZ_ZERO_UNDEF: 524 case ISD::CTTZ_ZERO_UNDEF: 525 case ISD::CTPOP: 526 case ISD::FABS: 527 case ISD::FCEIL: 528 case ISD::FCOS: 529 case ISD::FEXP: 530 case ISD::FEXP2: 531 case ISD::FFLOOR: 532 case ISD::FLOG: 533 case ISD::FLOG10: 534 case ISD::FLOG2: 535 case ISD::FNEARBYINT: 536 case ISD::FNEG: 537 case ISD::FP_EXTEND: 538 case ISD::FP_ROUND: 539 case ISD::FP_TO_SINT: 540 case ISD::FP_TO_UINT: 541 case ISD::FRINT: 542 case ISD::FSIN: 543 case ISD::FSQRT: 544 case ISD::FTRUNC: 545 case ISD::SIGN_EXTEND: 546 case ISD::SINT_TO_FP: 547 case ISD::TRUNCATE: 548 case ISD::UINT_TO_FP: 549 case ISD::ZERO_EXTEND: 550 SplitVecRes_UnaryOp(N, Lo, Hi); 551 break; 552 553 case ISD::ADD: 554 case ISD::SUB: 555 case ISD::MUL: 556 case ISD::FADD: 557 case ISD::FSUB: 558 case ISD::FMUL: 559 case ISD::SDIV: 560 case ISD::UDIV: 561 case ISD::FDIV: 562 case ISD::FPOW: 563 case ISD::AND: 564 case ISD::OR: 565 case ISD::XOR: 566 case ISD::SHL: 567 case ISD::SRA: 568 case ISD::SRL: 569 case ISD::UREM: 570 case ISD::SREM: 571 case ISD::FREM: 572 SplitVecRes_BinOp(N, Lo, Hi); 573 break; 574 case ISD::FMA: 575 SplitVecRes_TernaryOp(N, Lo, Hi); 576 break; 577 } 578 579 // If Lo/Hi is null, the sub-method took care of registering results etc. 580 if (Lo.getNode()) 581 SetSplitVector(SDValue(N, ResNo), Lo, Hi); 582} 583 584void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo, 585 SDValue &Hi) { 586 SDValue LHSLo, LHSHi; 587 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 588 SDValue RHSLo, RHSHi; 589 GetSplitVector(N->getOperand(1), RHSLo, RHSHi); 590 SDLoc dl(N); 591 592 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo); 593 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi); 594} 595 596void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, 597 SDValue &Hi) { 598 SDValue Op0Lo, Op0Hi; 599 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi); 600 SDValue Op1Lo, Op1Hi; 601 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi); 602 SDValue Op2Lo, Op2Hi; 603 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi); 604 SDLoc dl(N); 605 606 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(), 607 Op0Lo, Op1Lo, Op2Lo); 608 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(), 609 Op0Hi, Op1Hi, Op2Hi); 610} 611 612void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, 613 SDValue &Hi) { 614 // We know the result is a vector. The input may be either a vector or a 615 // scalar value. 616 EVT LoVT, HiVT; 617 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 618 SDLoc dl(N); 619 620 SDValue InOp = N->getOperand(0); 621 EVT InVT = InOp.getValueType(); 622 623 // Handle some special cases efficiently. 624 switch (getTypeAction(InVT)) { 625 case TargetLowering::TypeLegal: 626 case TargetLowering::TypePromoteInteger: 627 case TargetLowering::TypeSoftenFloat: 628 case TargetLowering::TypeScalarizeVector: 629 case TargetLowering::TypeWidenVector: 630 break; 631 case TargetLowering::TypeExpandInteger: 632 case TargetLowering::TypeExpandFloat: 633 // A scalar to vector conversion, where the scalar needs expansion. 634 // If the vector is being split in two then we can just convert the 635 // expanded pieces. 636 if (LoVT == HiVT) { 637 GetExpandedOp(InOp, Lo, Hi); 638 if (TLI.isBigEndian()) 639 std::swap(Lo, Hi); 640 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 641 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 642 return; 643 } 644 break; 645 case TargetLowering::TypeSplitVector: 646 // If the input is a vector that needs to be split, convert each split 647 // piece of the input now. 648 GetSplitVector(InOp, Lo, Hi); 649 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 650 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 651 return; 652 } 653 654 // In the general case, convert the input to an integer and split it by hand. 655 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits()); 656 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits()); 657 if (TLI.isBigEndian()) 658 std::swap(LoIntVT, HiIntVT); 659 660 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); 661 662 if (TLI.isBigEndian()) 663 std::swap(Lo, Hi); 664 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 665 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 666} 667 668void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, 669 SDValue &Hi) { 670 EVT LoVT, HiVT; 671 SDLoc dl(N); 672 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 673 unsigned LoNumElts = LoVT.getVectorNumElements(); 674 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts); 675 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size()); 676 677 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end()); 678 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size()); 679} 680 681void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, 682 SDValue &Hi) { 683 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"); 684 SDLoc dl(N); 685 unsigned NumSubvectors = N->getNumOperands() / 2; 686 if (NumSubvectors == 1) { 687 Lo = N->getOperand(0); 688 Hi = N->getOperand(1); 689 return; 690 } 691 692 EVT LoVT, HiVT; 693 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 694 695 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); 696 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size()); 697 698 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end()); 699 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size()); 700} 701 702void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, 703 SDValue &Hi) { 704 SDValue Vec = N->getOperand(0); 705 SDValue Idx = N->getOperand(1); 706 SDLoc dl(N); 707 708 EVT LoVT, HiVT; 709 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 710 711 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); 712 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 713 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, 714 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements())); 715} 716 717void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, 718 SDValue &Hi) { 719 SDLoc dl(N); 720 GetSplitVector(N->getOperand(0), Lo, Hi); 721 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1)); 722 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1)); 723} 724 725void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo, 726 SDValue &Hi) { 727 SDValue LHSLo, LHSHi; 728 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 729 SDLoc dl(N); 730 731 EVT LoVT, HiVT; 732 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT); 733 734 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, 735 DAG.getValueType(LoVT)); 736 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, 737 DAG.getValueType(HiVT)); 738} 739 740void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, 741 SDValue &Hi) { 742 SDValue Vec = N->getOperand(0); 743 SDValue Elt = N->getOperand(1); 744 SDValue Idx = N->getOperand(2); 745 SDLoc dl(N); 746 GetSplitVector(Vec, Lo, Hi); 747 748 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 749 unsigned IdxVal = CIdx->getZExtValue(); 750 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 751 if (IdxVal < LoNumElts) 752 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 753 Lo.getValueType(), Lo, Elt, Idx); 754 else 755 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, 756 DAG.getIntPtrConstant(IdxVal - LoNumElts)); 757 return; 758 } 759 760 // Spill the vector to the stack. 761 EVT VecVT = Vec.getValueType(); 762 EVT EltVT = VecVT.getVectorElementType(); 763 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 764 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 765 MachinePointerInfo(), false, false, 0); 766 767 // Store the new element. This may be larger than the vector element type, 768 // so use a truncating store. 769 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 770 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); 771 unsigned Alignment = 772 TLI.getDataLayout()->getPrefTypeAlignment(VecType); 773 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT, 774 false, false, 0); 775 776 // Load the Lo part from the stack slot. 777 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 778 false, false, false, 0); 779 780 // Increment the pointer to the other part. 781 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; 782 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 783 DAG.getIntPtrConstant(IncrementSize)); 784 785 // Load the Hi part from the stack slot. 786 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 787 false, false, false, MinAlign(Alignment, IncrementSize)); 788} 789 790void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, 791 SDValue &Hi) { 792 EVT LoVT, HiVT; 793 SDLoc dl(N); 794 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 795 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0)); 796 Hi = DAG.getUNDEF(HiVT); 797} 798 799void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, 800 SDValue &Hi) { 801 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"); 802 EVT LoVT, HiVT; 803 SDLoc dl(LD); 804 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); 805 806 ISD::LoadExtType ExtType = LD->getExtensionType(); 807 SDValue Ch = LD->getChain(); 808 SDValue Ptr = LD->getBasePtr(); 809 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 810 EVT MemoryVT = LD->getMemoryVT(); 811 unsigned Alignment = LD->getOriginalAlignment(); 812 bool isVolatile = LD->isVolatile(); 813 bool isNonTemporal = LD->isNonTemporal(); 814 bool isInvariant = LD->isInvariant(); 815 816 EVT LoMemVT, HiMemVT; 817 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 818 819 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, 820 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal, 821 isInvariant, Alignment); 822 823 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 824 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 825 DAG.getIntPtrConstant(IncrementSize)); 826 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, 827 LD->getPointerInfo().getWithOffset(IncrementSize), 828 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment); 829 830 // Build a factor node to remember that this load is independent of the 831 // other one. 832 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 833 Hi.getValue(1)); 834 835 // Legalized the chain result - switch anything that used the old chain to 836 // use the new one. 837 ReplaceValueWith(SDValue(LD, 1), Ch); 838} 839 840void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) { 841 assert(N->getValueType(0).isVector() && 842 N->getOperand(0).getValueType().isVector() && 843 "Operand types must be vectors"); 844 845 EVT LoVT, HiVT; 846 SDLoc DL(N); 847 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 848 849 // Split the input. 850 EVT InVT = N->getOperand(0).getValueType(); 851 SDValue LL, LH, RL, RH; 852 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 853 LoVT.getVectorNumElements()); 854 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 855 DAG.getIntPtrConstant(0)); 856 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 857 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 858 859 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 860 DAG.getIntPtrConstant(0)); 861 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 862 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 863 864 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2)); 865 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2)); 866} 867 868void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, 869 SDValue &Hi) { 870 // Get the dest types - they may not match the input types, e.g. int_to_fp. 871 EVT LoVT, HiVT; 872 SDLoc dl(N); 873 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 874 875 // If the input also splits, handle it directly for a compile time speedup. 876 // Otherwise split it by hand. 877 EVT InVT = N->getOperand(0).getValueType(); 878 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) { 879 GetSplitVector(N->getOperand(0), Lo, Hi); 880 } else { 881 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 882 LoVT.getVectorNumElements()); 883 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 884 DAG.getIntPtrConstant(0)); 885 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 886 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 887 } 888 889 if (N->getOpcode() == ISD::FP_ROUND) { 890 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1)); 891 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1)); 892 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) { 893 SDValue DTyOpLo = DAG.getValueType(LoVT); 894 SDValue DTyOpHi = DAG.getValueType(HiVT); 895 SDValue STyOpLo = DAG.getValueType(Lo.getValueType()); 896 SDValue STyOpHi = DAG.getValueType(Hi.getValueType()); 897 SDValue RndOp = N->getOperand(3); 898 SDValue SatOp = N->getOperand(4); 899 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 900 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp, 901 CvtCode); 902 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp, 903 CvtCode); 904 } else { 905 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo); 906 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi); 907 } 908} 909 910void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, 911 SDValue &Lo, SDValue &Hi) { 912 // The low and high parts of the original input give four input vectors. 913 SDValue Inputs[4]; 914 SDLoc dl(N); 915 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]); 916 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]); 917 EVT NewVT = Inputs[0].getValueType(); 918 unsigned NewElts = NewVT.getVectorNumElements(); 919 920 // If Lo or Hi uses elements from at most two of the four input vectors, then 921 // express it as a vector shuffle of those two inputs. Otherwise extract the 922 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. 923 SmallVector<int, 16> Ops; 924 for (unsigned High = 0; High < 2; ++High) { 925 SDValue &Output = High ? Hi : Lo; 926 927 // Build a shuffle mask for the output, discovering on the fly which 928 // input vectors to use as shuffle operands (recorded in InputUsed). 929 // If building a suitable shuffle vector proves too hard, then bail 930 // out with useBuildVector set. 931 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered. 932 unsigned FirstMaskIdx = High * NewElts; 933 bool useBuildVector = false; 934 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 935 // The mask element. This indexes into the input. 936 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 937 938 // The input vector this mask element indexes into. 939 unsigned Input = (unsigned)Idx / NewElts; 940 941 if (Input >= array_lengthof(Inputs)) { 942 // The mask element does not index into any input vector. 943 Ops.push_back(-1); 944 continue; 945 } 946 947 // Turn the index into an offset from the start of the input vector. 948 Idx -= Input * NewElts; 949 950 // Find or create a shuffle vector operand to hold this input. 951 unsigned OpNo; 952 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 953 if (InputUsed[OpNo] == Input) { 954 // This input vector is already an operand. 955 break; 956 } else if (InputUsed[OpNo] == -1U) { 957 // Create a new operand for this input vector. 958 InputUsed[OpNo] = Input; 959 break; 960 } 961 } 962 963 if (OpNo >= array_lengthof(InputUsed)) { 964 // More than two input vectors used! Give up on trying to create a 965 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 966 useBuildVector = true; 967 break; 968 } 969 970 // Add the mask index for the new shuffle vector. 971 Ops.push_back(Idx + OpNo * NewElts); 972 } 973 974 if (useBuildVector) { 975 EVT EltVT = NewVT.getVectorElementType(); 976 SmallVector<SDValue, 16> SVOps; 977 978 // Extract the input elements by hand. 979 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 980 // The mask element. This indexes into the input. 981 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 982 983 // The input vector this mask element indexes into. 984 unsigned Input = (unsigned)Idx / NewElts; 985 986 if (Input >= array_lengthof(Inputs)) { 987 // The mask element is "undef" or indexes off the end of the input. 988 SVOps.push_back(DAG.getUNDEF(EltVT)); 989 continue; 990 } 991 992 // Turn the index into an offset from the start of the input vector. 993 Idx -= Input * NewElts; 994 995 // Extract the vector element by hand. 996 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 997 Inputs[Input], DAG.getIntPtrConstant(Idx))); 998 } 999 1000 // Construct the Lo/Hi output using a BUILD_VECTOR. 1001 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size()); 1002 } else if (InputUsed[0] == -1U) { 1003 // No input vectors were used! The result is undefined. 1004 Output = DAG.getUNDEF(NewVT); 1005 } else { 1006 SDValue Op0 = Inputs[InputUsed[0]]; 1007 // If only one input was used, use an undefined vector for the other. 1008 SDValue Op1 = InputUsed[1] == -1U ? 1009 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]]; 1010 // At least one input vector was used. Create a new shuffle vector. 1011 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]); 1012 } 1013 1014 Ops.clear(); 1015 } 1016} 1017 1018 1019//===----------------------------------------------------------------------===// 1020// Operand Vector Splitting 1021//===----------------------------------------------------------------------===// 1022 1023/// SplitVectorOperand - This method is called when the specified operand of the 1024/// specified node is found to need vector splitting. At this point, all of the 1025/// result types of the node are known to be legal, but other operands of the 1026/// node may need legalization as well as the specified one. 1027bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { 1028 DEBUG(dbgs() << "Split node operand: "; 1029 N->dump(&DAG); 1030 dbgs() << "\n"); 1031 SDValue Res = SDValue(); 1032 1033 if (Res.getNode() == 0) { 1034 switch (N->getOpcode()) { 1035 default: 1036#ifndef NDEBUG 1037 dbgs() << "SplitVectorOperand Op #" << OpNo << ": "; 1038 N->dump(&DAG); 1039 dbgs() << "\n"; 1040#endif 1041 report_fatal_error("Do not know how to split this operator's " 1042 "operand!\n"); 1043 1044 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; 1045 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break; 1046 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; 1047 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; 1048 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; 1049 case ISD::TRUNCATE: Res = SplitVecOp_TRUNCATE(N); break; 1050 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; 1051 case ISD::STORE: 1052 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo); 1053 break; 1054 case ISD::VSELECT: 1055 Res = SplitVecOp_VSELECT(N, OpNo); 1056 break; 1057 case ISD::CTTZ: 1058 case ISD::CTLZ: 1059 case ISD::CTPOP: 1060 case ISD::FP_EXTEND: 1061 case ISD::FP_TO_SINT: 1062 case ISD::FP_TO_UINT: 1063 case ISD::SINT_TO_FP: 1064 case ISD::UINT_TO_FP: 1065 case ISD::FTRUNC: 1066 case ISD::SIGN_EXTEND: 1067 case ISD::ZERO_EXTEND: 1068 case ISD::ANY_EXTEND: 1069 Res = SplitVecOp_UnaryOp(N); 1070 break; 1071 } 1072 } 1073 1074 // If the result is null, the sub-method took care of registering results etc. 1075 if (!Res.getNode()) return false; 1076 1077 // If the result is N, the sub-method updated N in place. Tell the legalizer 1078 // core about this. 1079 if (Res.getNode() == N) 1080 return true; 1081 1082 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1083 "Invalid operand expansion"); 1084 1085 ReplaceValueWith(SDValue(N, 0), Res); 1086 return false; 1087} 1088 1089SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) { 1090 // The only possibility for an illegal operand is the mask, since result type 1091 // legalization would have handled this node already otherwise. 1092 assert(OpNo == 0 && "Illegal operand must be mask"); 1093 1094 SDValue Mask = N->getOperand(0); 1095 SDValue Src0 = N->getOperand(1); 1096 SDValue Src1 = N->getOperand(2); 1097 SDLoc DL(N); 1098 EVT MaskVT = Mask.getValueType(); 1099 assert(MaskVT.isVector() && "VSELECT without a vector mask?"); 1100 1101 SDValue Lo, Hi; 1102 GetSplitVector(N->getOperand(0), Lo, Hi); 1103 assert(Lo.getValueType() == Hi.getValueType() && 1104 "Lo and Hi have differing types"); 1105 1106 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 1107 unsigned HiNumElts = Hi.getValueType().getVectorNumElements(); 1108 assert(LoNumElts == HiNumElts && "Asymmetric vector split?"); 1109 1110 LLVMContext &Ctx = *DAG.getContext(); 1111 SDValue Zero = DAG.getIntPtrConstant(0); 1112 SDValue LoElts = DAG.getIntPtrConstant(LoNumElts); 1113 EVT Src0VT = Src0.getValueType(); 1114 EVT Src0EltTy = Src0VT.getVectorElementType(); 1115 EVT MaskEltTy = MaskVT.getVectorElementType(); 1116 1117 EVT LoOpVT = EVT::getVectorVT(Ctx, Src0EltTy, LoNumElts); 1118 EVT LoMaskVT = EVT::getVectorVT(Ctx, MaskEltTy, LoNumElts); 1119 EVT HiOpVT = EVT::getVectorVT(Ctx, Src0EltTy, HiNumElts); 1120 EVT HiMaskVT = EVT::getVectorVT(Ctx, MaskEltTy, HiNumElts); 1121 1122 SDValue LoOp0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoOpVT, Src0, Zero); 1123 SDValue LoOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoOpVT, Src1, Zero); 1124 1125 SDValue HiOp0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiOpVT, Src0, LoElts); 1126 SDValue HiOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiOpVT, Src1, LoElts); 1127 1128 SDValue LoMask = 1129 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoMaskVT, Mask, Zero); 1130 SDValue HiMask = 1131 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiMaskVT, Mask, LoElts); 1132 1133 SDValue LoSelect = 1134 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1); 1135 SDValue HiSelect = 1136 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1); 1137 1138 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect); 1139} 1140 1141SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) { 1142 // The result has a legal vector type, but the input needs splitting. 1143 EVT ResVT = N->getValueType(0); 1144 SDValue Lo, Hi; 1145 SDLoc dl(N); 1146 GetSplitVector(N->getOperand(0), Lo, Hi); 1147 EVT InVT = Lo.getValueType(); 1148 1149 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1150 InVT.getVectorNumElements()); 1151 1152 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); 1153 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); 1154 1155 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); 1156} 1157 1158SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) { 1159 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will 1160 // end up being split all the way down to individual components. Convert the 1161 // split pieces into integers and reassemble. 1162 SDValue Lo, Hi; 1163 GetSplitVector(N->getOperand(0), Lo, Hi); 1164 Lo = BitConvertToInteger(Lo); 1165 Hi = BitConvertToInteger(Hi); 1166 1167 if (TLI.isBigEndian()) 1168 std::swap(Lo, Hi); 1169 1170 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), 1171 JoinIntegers(Lo, Hi)); 1172} 1173 1174SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 1175 // We know that the extracted result type is legal. 1176 EVT SubVT = N->getValueType(0); 1177 SDValue Idx = N->getOperand(1); 1178 SDLoc dl(N); 1179 SDValue Lo, Hi; 1180 GetSplitVector(N->getOperand(0), Lo, Hi); 1181 1182 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1183 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1184 1185 if (IdxVal < LoElts) { 1186 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && 1187 "Extracted subvector crosses vector split!"); 1188 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); 1189 } else { 1190 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, 1191 DAG.getConstant(IdxVal - LoElts, Idx.getValueType())); 1192 } 1193} 1194 1195SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 1196 SDValue Vec = N->getOperand(0); 1197 SDValue Idx = N->getOperand(1); 1198 EVT VecVT = Vec.getValueType(); 1199 1200 if (isa<ConstantSDNode>(Idx)) { 1201 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1202 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); 1203 1204 SDValue Lo, Hi; 1205 GetSplitVector(Vec, Lo, Hi); 1206 1207 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1208 1209 if (IdxVal < LoElts) 1210 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0); 1211 return SDValue(DAG.UpdateNodeOperands(N, Hi, 1212 DAG.getConstant(IdxVal - LoElts, 1213 Idx.getValueType())), 0); 1214 } 1215 1216 // Store the vector to the stack. 1217 EVT EltVT = VecVT.getVectorElementType(); 1218 SDLoc dl(N); 1219 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 1220 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 1221 MachinePointerInfo(), false, false, 0); 1222 1223 // Load back the required element. 1224 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 1225 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, 1226 MachinePointerInfo(), EltVT, false, false, 0); 1227} 1228 1229SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { 1230 assert(N->isUnindexed() && "Indexed store of vector?"); 1231 assert(OpNo == 1 && "Can only split the stored value"); 1232 SDLoc DL(N); 1233 1234 bool isTruncating = N->isTruncatingStore(); 1235 SDValue Ch = N->getChain(); 1236 SDValue Ptr = N->getBasePtr(); 1237 EVT MemoryVT = N->getMemoryVT(); 1238 unsigned Alignment = N->getOriginalAlignment(); 1239 bool isVol = N->isVolatile(); 1240 bool isNT = N->isNonTemporal(); 1241 SDValue Lo, Hi; 1242 GetSplitVector(N->getOperand(1), Lo, Hi); 1243 1244 EVT LoMemVT, HiMemVT; 1245 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 1246 1247 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 1248 1249 if (isTruncating) 1250 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1251 LoMemVT, isVol, isNT, Alignment); 1252 else 1253 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1254 isVol, isNT, Alignment); 1255 1256 // Increment the pointer to the other half. 1257 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, 1258 DAG.getIntPtrConstant(IncrementSize)); 1259 1260 if (isTruncating) 1261 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr, 1262 N->getPointerInfo().getWithOffset(IncrementSize), 1263 HiMemVT, isVol, isNT, Alignment); 1264 else 1265 Hi = DAG.getStore(Ch, DL, Hi, Ptr, 1266 N->getPointerInfo().getWithOffset(IncrementSize), 1267 isVol, isNT, Alignment); 1268 1269 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi); 1270} 1271 1272SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) { 1273 SDLoc DL(N); 1274 1275 // The input operands all must have the same type, and we know the result 1276 // type is valid. Convert this to a buildvector which extracts all the 1277 // input elements. 1278 // TODO: If the input elements are power-two vectors, we could convert this to 1279 // a new CONCAT_VECTORS node with elements that are half-wide. 1280 SmallVector<SDValue, 32> Elts; 1281 EVT EltVT = N->getValueType(0).getVectorElementType(); 1282 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1283 SDValue Op = N->getOperand(op); 1284 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements(); 1285 i != e; ++i) { 1286 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, 1287 Op, DAG.getIntPtrConstant(i))); 1288 1289 } 1290 } 1291 1292 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), 1293 &Elts[0], Elts.size()); 1294} 1295 1296SDValue DAGTypeLegalizer::SplitVecOp_TRUNCATE(SDNode *N) { 1297 // The result type is legal, but the input type is illegal. If splitting 1298 // ends up with the result type of each half still being legal, just 1299 // do that. If, however, that would result in an illegal result type, 1300 // we can try to get more clever with power-two vectors. Specifically, 1301 // split the input type, but also widen the result element size, then 1302 // concatenate the halves and truncate again. For example, consider a target 1303 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit 1304 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do: 1305 // %inlo = v4i32 extract_subvector %in, 0 1306 // %inhi = v4i32 extract_subvector %in, 4 1307 // %lo16 = v4i16 trunc v4i32 %inlo 1308 // %hi16 = v4i16 trunc v4i32 %inhi 1309 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16 1310 // %res = v8i8 trunc v8i16 %in16 1311 // 1312 // Without this transform, the original truncate would end up being 1313 // scalarized, which is pretty much always a last resort. 1314 SDValue InVec = N->getOperand(0); 1315 EVT InVT = InVec->getValueType(0); 1316 EVT OutVT = N->getValueType(0); 1317 unsigned NumElements = OutVT.getVectorNumElements(); 1318 // Widening should have already made sure this is a power-two vector 1319 // if we're trying to split it at all. assert() that's true, just in case. 1320 assert(!(NumElements & 1) && "Splitting vector, but not in half!"); 1321 1322 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits(); 1323 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits(); 1324 1325 // If the input elements are only 1/2 the width of the result elements, 1326 // just use the normal splitting. Our trick only work if there's room 1327 // to split more than once. 1328 if (InElementSize <= OutElementSize * 2) 1329 return SplitVecOp_UnaryOp(N); 1330 SDLoc DL(N); 1331 1332 // Extract the halves of the input via extract_subvector. 1333 EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), 1334 InVT.getVectorElementType(), NumElements/2); 1335 SDValue InLoVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, InVec, 1336 DAG.getIntPtrConstant(0)); 1337 SDValue InHiVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, InVec, 1338 DAG.getIntPtrConstant(NumElements/2)); 1339 // Truncate them to 1/2 the element size. 1340 EVT HalfElementVT = EVT::getIntegerVT(*DAG.getContext(), InElementSize/2); 1341 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, 1342 NumElements/2); 1343 SDValue HalfLo = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InLoVec); 1344 SDValue HalfHi = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InHiVec); 1345 // Concatenate them to get the full intermediate truncation result. 1346 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements); 1347 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo, 1348 HalfHi); 1349 // Now finish up by truncating all the way down to the original result 1350 // type. This should normally be something that ends up being legal directly, 1351 // but in theory if a target has very wide vectors and an annoyingly 1352 // restricted set of legal types, this split can chain to build things up. 1353 return DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec); 1354} 1355 1356SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { 1357 assert(N->getValueType(0).isVector() && 1358 N->getOperand(0).getValueType().isVector() && 1359 "Operand types must be vectors"); 1360 // The result has a legal vector type, but the input needs splitting. 1361 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes; 1362 SDLoc DL(N); 1363 GetSplitVector(N->getOperand(0), Lo0, Hi0); 1364 GetSplitVector(N->getOperand(1), Lo1, Hi1); 1365 unsigned PartElements = Lo0.getValueType().getVectorNumElements(); 1366 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements); 1367 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements); 1368 1369 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); 1370 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); 1371 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes); 1372 return PromoteTargetBoolean(Con, N->getValueType(0)); 1373} 1374 1375 1376SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) { 1377 // The result has a legal vector type, but the input needs splitting. 1378 EVT ResVT = N->getValueType(0); 1379 SDValue Lo, Hi; 1380 SDLoc DL(N); 1381 GetSplitVector(N->getOperand(0), Lo, Hi); 1382 EVT InVT = Lo.getValueType(); 1383 1384 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1385 InVT.getVectorNumElements()); 1386 1387 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); 1388 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); 1389 1390 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); 1391} 1392 1393 1394 1395//===----------------------------------------------------------------------===// 1396// Result Vector Widening 1397//===----------------------------------------------------------------------===// 1398 1399void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { 1400 DEBUG(dbgs() << "Widen node result " << ResNo << ": "; 1401 N->dump(&DAG); 1402 dbgs() << "\n"); 1403 1404 // See if the target wants to custom widen this node. 1405 if (CustomWidenLowerNode(N, N->getValueType(ResNo))) 1406 return; 1407 1408 SDValue Res = SDValue(); 1409 switch (N->getOpcode()) { 1410 default: 1411#ifndef NDEBUG 1412 dbgs() << "WidenVectorResult #" << ResNo << ": "; 1413 N->dump(&DAG); 1414 dbgs() << "\n"; 1415#endif 1416 llvm_unreachable("Do not know how to widen the result of this operator!"); 1417 1418 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break; 1419 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break; 1420 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; 1421 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break; 1422 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break; 1423 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; 1424 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break; 1425 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; 1426 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break; 1427 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break; 1428 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break; 1429 case ISD::VSELECT: 1430 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break; 1431 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; 1432 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; 1433 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break; 1434 case ISD::VECTOR_SHUFFLE: 1435 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N)); 1436 break; 1437 case ISD::ADD: 1438 case ISD::AND: 1439 case ISD::BSWAP: 1440 case ISD::FADD: 1441 case ISD::FCOPYSIGN: 1442 case ISD::FDIV: 1443 case ISD::FMUL: 1444 case ISD::FPOW: 1445 case ISD::FREM: 1446 case ISD::FSUB: 1447 case ISD::MUL: 1448 case ISD::MULHS: 1449 case ISD::MULHU: 1450 case ISD::OR: 1451 case ISD::SDIV: 1452 case ISD::SREM: 1453 case ISD::UDIV: 1454 case ISD::UREM: 1455 case ISD::SUB: 1456 case ISD::XOR: 1457 Res = WidenVecRes_Binary(N); 1458 break; 1459 1460 case ISD::FPOWI: 1461 Res = WidenVecRes_POWI(N); 1462 break; 1463 1464 case ISD::SHL: 1465 case ISD::SRA: 1466 case ISD::SRL: 1467 Res = WidenVecRes_Shift(N); 1468 break; 1469 1470 case ISD::ANY_EXTEND: 1471 case ISD::FP_EXTEND: 1472 case ISD::FP_ROUND: 1473 case ISD::FP_TO_SINT: 1474 case ISD::FP_TO_UINT: 1475 case ISD::SIGN_EXTEND: 1476 case ISD::SINT_TO_FP: 1477 case ISD::TRUNCATE: 1478 case ISD::UINT_TO_FP: 1479 case ISD::ZERO_EXTEND: 1480 Res = WidenVecRes_Convert(N); 1481 break; 1482 1483 case ISD::CTLZ: 1484 case ISD::CTPOP: 1485 case ISD::CTTZ: 1486 case ISD::FABS: 1487 case ISD::FCEIL: 1488 case ISD::FCOS: 1489 case ISD::FEXP: 1490 case ISD::FEXP2: 1491 case ISD::FFLOOR: 1492 case ISD::FLOG: 1493 case ISD::FLOG10: 1494 case ISD::FLOG2: 1495 case ISD::FNEARBYINT: 1496 case ISD::FNEG: 1497 case ISD::FRINT: 1498 case ISD::FSIN: 1499 case ISD::FSQRT: 1500 case ISD::FTRUNC: 1501 Res = WidenVecRes_Unary(N); 1502 break; 1503 case ISD::FMA: 1504 Res = WidenVecRes_Ternary(N); 1505 break; 1506 } 1507 1508 // If Res is null, the sub-method took care of registering the result. 1509 if (Res.getNode()) 1510 SetWidenedVector(SDValue(N, ResNo), Res); 1511} 1512 1513SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) { 1514 // Ternary op widening. 1515 SDLoc dl(N); 1516 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1517 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1518 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1519 SDValue InOp3 = GetWidenedVector(N->getOperand(2)); 1520 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3); 1521} 1522 1523SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) { 1524 // Binary op widening. 1525 unsigned Opcode = N->getOpcode(); 1526 SDLoc dl(N); 1527 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1528 EVT WidenEltVT = WidenVT.getVectorElementType(); 1529 EVT VT = WidenVT; 1530 unsigned NumElts = VT.getVectorNumElements(); 1531 while (!TLI.isTypeLegal(VT) && NumElts != 1) { 1532 NumElts = NumElts / 2; 1533 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1534 } 1535 1536 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) { 1537 // Operation doesn't trap so just widen as normal. 1538 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1539 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1540 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2); 1541 } 1542 1543 // No legal vector version so unroll the vector operation and then widen. 1544 if (NumElts == 1) 1545 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()); 1546 1547 // Since the operation can trap, apply operation on the original vector. 1548 EVT MaxVT = VT; 1549 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1550 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1551 unsigned CurNumElts = N->getValueType(0).getVectorNumElements(); 1552 1553 SmallVector<SDValue, 16> ConcatOps(CurNumElts); 1554 unsigned ConcatEnd = 0; // Current ConcatOps index. 1555 int Idx = 0; // Current Idx into input vectors. 1556 1557 // NumElts := greatest legal vector size (at most WidenVT) 1558 // while (orig. vector has unhandled elements) { 1559 // take munches of size NumElts from the beginning and add to ConcatOps 1560 // NumElts := next smaller supported vector size or 1 1561 // } 1562 while (CurNumElts != 0) { 1563 while (CurNumElts >= NumElts) { 1564 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, 1565 DAG.getIntPtrConstant(Idx)); 1566 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, 1567 DAG.getIntPtrConstant(Idx)); 1568 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2); 1569 Idx += NumElts; 1570 CurNumElts -= NumElts; 1571 } 1572 do { 1573 NumElts = NumElts / 2; 1574 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1575 } while (!TLI.isTypeLegal(VT) && NumElts != 1); 1576 1577 if (NumElts == 1) { 1578 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) { 1579 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1580 InOp1, DAG.getIntPtrConstant(Idx)); 1581 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1582 InOp2, DAG.getIntPtrConstant(Idx)); 1583 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT, 1584 EOp1, EOp2); 1585 } 1586 CurNumElts = 0; 1587 } 1588 } 1589 1590 // Check to see if we have a single operation with the widen type. 1591 if (ConcatEnd == 1) { 1592 VT = ConcatOps[0].getValueType(); 1593 if (VT == WidenVT) 1594 return ConcatOps[0]; 1595 } 1596 1597 // while (Some element of ConcatOps is not of type MaxVT) { 1598 // From the end of ConcatOps, collect elements of the same type and put 1599 // them into an op of the next larger supported type 1600 // } 1601 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) { 1602 Idx = ConcatEnd - 1; 1603 VT = ConcatOps[Idx--].getValueType(); 1604 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT) 1605 Idx--; 1606 1607 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1; 1608 EVT NextVT; 1609 do { 1610 NextSize *= 2; 1611 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize); 1612 } while (!TLI.isTypeLegal(NextVT)); 1613 1614 if (!VT.isVector()) { 1615 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT 1616 SDValue VecOp = DAG.getUNDEF(NextVT); 1617 unsigned NumToInsert = ConcatEnd - Idx - 1; 1618 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) { 1619 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, 1620 ConcatOps[OpIdx], DAG.getIntPtrConstant(i)); 1621 } 1622 ConcatOps[Idx+1] = VecOp; 1623 ConcatEnd = Idx + 2; 1624 } else { 1625 // Vector type, create a CONCAT_VECTORS of type NextVT 1626 SDValue undefVec = DAG.getUNDEF(VT); 1627 unsigned OpsToConcat = NextSize/VT.getVectorNumElements(); 1628 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat); 1629 unsigned RealVals = ConcatEnd - Idx - 1; 1630 unsigned SubConcatEnd = 0; 1631 unsigned SubConcatIdx = Idx + 1; 1632 while (SubConcatEnd < RealVals) 1633 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx]; 1634 while (SubConcatEnd < OpsToConcat) 1635 SubConcatOps[SubConcatEnd++] = undefVec; 1636 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1637 NextVT, &SubConcatOps[0], 1638 OpsToConcat); 1639 ConcatEnd = SubConcatIdx + 1; 1640 } 1641 } 1642 1643 // Check to see if we have a single operation with the widen type. 1644 if (ConcatEnd == 1) { 1645 VT = ConcatOps[0].getValueType(); 1646 if (VT == WidenVT) 1647 return ConcatOps[0]; 1648 } 1649 1650 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT 1651 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements(); 1652 if (NumOps != ConcatEnd ) { 1653 SDValue UndefVal = DAG.getUNDEF(MaxVT); 1654 for (unsigned j = ConcatEnd; j < NumOps; ++j) 1655 ConcatOps[j] = UndefVal; 1656 } 1657 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps); 1658} 1659 1660SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { 1661 SDValue InOp = N->getOperand(0); 1662 SDLoc DL(N); 1663 1664 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1665 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1666 1667 EVT InVT = InOp.getValueType(); 1668 EVT InEltVT = InVT.getVectorElementType(); 1669 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1670 1671 unsigned Opcode = N->getOpcode(); 1672 unsigned InVTNumElts = InVT.getVectorNumElements(); 1673 1674 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1675 InOp = GetWidenedVector(N->getOperand(0)); 1676 InVT = InOp.getValueType(); 1677 InVTNumElts = InVT.getVectorNumElements(); 1678 if (InVTNumElts == WidenNumElts) { 1679 if (N->getNumOperands() == 1) 1680 return DAG.getNode(Opcode, DL, WidenVT, InOp); 1681 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1)); 1682 } 1683 } 1684 1685 if (TLI.isTypeLegal(InWidenVT)) { 1686 // Because the result and the input are different vector types, widening 1687 // the result could create a legal type but widening the input might make 1688 // it an illegal type that might lead to repeatedly splitting the input 1689 // and then widening it. To avoid this, we widen the input only if 1690 // it results in a legal type. 1691 if (WidenNumElts % InVTNumElts == 0) { 1692 // Widen the input and call convert on the widened input vector. 1693 unsigned NumConcat = WidenNumElts/InVTNumElts; 1694 SmallVector<SDValue, 16> Ops(NumConcat); 1695 Ops[0] = InOp; 1696 SDValue UndefVal = DAG.getUNDEF(InVT); 1697 for (unsigned i = 1; i != NumConcat; ++i) 1698 Ops[i] = UndefVal; 1699 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, 1700 &Ops[0], NumConcat); 1701 if (N->getNumOperands() == 1) 1702 return DAG.getNode(Opcode, DL, WidenVT, InVec); 1703 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1)); 1704 } 1705 1706 if (InVTNumElts % WidenNumElts == 0) { 1707 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, 1708 InOp, DAG.getIntPtrConstant(0)); 1709 // Extract the input and convert the shorten input vector. 1710 if (N->getNumOperands() == 1) 1711 return DAG.getNode(Opcode, DL, WidenVT, InVal); 1712 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1)); 1713 } 1714 } 1715 1716 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1717 SmallVector<SDValue, 16> Ops(WidenNumElts); 1718 EVT EltVT = WidenVT.getVectorElementType(); 1719 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1720 unsigned i; 1721 for (i=0; i < MinElts; ++i) { 1722 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp, 1723 DAG.getIntPtrConstant(i)); 1724 if (N->getNumOperands() == 1) 1725 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val); 1726 else 1727 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1)); 1728 } 1729 1730 SDValue UndefVal = DAG.getUNDEF(EltVT); 1731 for (; i < WidenNumElts; ++i) 1732 Ops[i] = UndefVal; 1733 1734 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts); 1735} 1736 1737SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) { 1738 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1739 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1740 SDValue ShOp = N->getOperand(1); 1741 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); 1742} 1743 1744SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) { 1745 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1746 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1747 SDValue ShOp = N->getOperand(1); 1748 1749 EVT ShVT = ShOp.getValueType(); 1750 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) { 1751 ShOp = GetWidenedVector(ShOp); 1752 ShVT = ShOp.getValueType(); 1753 } 1754 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(), 1755 ShVT.getVectorElementType(), 1756 WidenVT.getVectorNumElements()); 1757 if (ShVT != ShWidenVT) 1758 ShOp = ModifyToType(ShOp, ShWidenVT); 1759 1760 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); 1761} 1762 1763SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) { 1764 // Unary op widening. 1765 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1766 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1767 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp); 1768} 1769 1770SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) { 1771 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1772 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), 1773 cast<VTSDNode>(N->getOperand(1))->getVT() 1774 .getVectorElementType(), 1775 WidenVT.getVectorNumElements()); 1776 SDValue WidenLHS = GetWidenedVector(N->getOperand(0)); 1777 return DAG.getNode(N->getOpcode(), SDLoc(N), 1778 WidenVT, WidenLHS, DAG.getValueType(ExtVT)); 1779} 1780 1781SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) { 1782 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo); 1783 return GetWidenedVector(WidenVec); 1784} 1785 1786SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) { 1787 SDValue InOp = N->getOperand(0); 1788 EVT InVT = InOp.getValueType(); 1789 EVT VT = N->getValueType(0); 1790 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1791 SDLoc dl(N); 1792 1793 switch (getTypeAction(InVT)) { 1794 case TargetLowering::TypeLegal: 1795 break; 1796 case TargetLowering::TypePromoteInteger: 1797 // If the incoming type is a vector that is being promoted, then 1798 // we know that the elements are arranged differently and that we 1799 // must perform the conversion using a stack slot. 1800 if (InVT.isVector()) 1801 break; 1802 1803 // If the InOp is promoted to the same size, convert it. Otherwise, 1804 // fall out of the switch and widen the promoted input. 1805 InOp = GetPromotedInteger(InOp); 1806 InVT = InOp.getValueType(); 1807 if (WidenVT.bitsEq(InVT)) 1808 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1809 break; 1810 case TargetLowering::TypeSoftenFloat: 1811 case TargetLowering::TypeExpandInteger: 1812 case TargetLowering::TypeExpandFloat: 1813 case TargetLowering::TypeScalarizeVector: 1814 case TargetLowering::TypeSplitVector: 1815 break; 1816 case TargetLowering::TypeWidenVector: 1817 // If the InOp is widened to the same size, convert it. Otherwise, fall 1818 // out of the switch and widen the widened input. 1819 InOp = GetWidenedVector(InOp); 1820 InVT = InOp.getValueType(); 1821 if (WidenVT.bitsEq(InVT)) 1822 // The input widens to the same size. Convert to the widen value. 1823 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1824 break; 1825 } 1826 1827 unsigned WidenSize = WidenVT.getSizeInBits(); 1828 unsigned InSize = InVT.getSizeInBits(); 1829 // x86mmx is not an acceptable vector element type, so don't try. 1830 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) { 1831 // Determine new input vector type. The new input vector type will use 1832 // the same element type (if its a vector) or use the input type as a 1833 // vector. It is the same size as the type to widen to. 1834 EVT NewInVT; 1835 unsigned NewNumElts = WidenSize / InSize; 1836 if (InVT.isVector()) { 1837 EVT InEltVT = InVT.getVectorElementType(); 1838 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, 1839 WidenSize / InEltVT.getSizeInBits()); 1840 } else { 1841 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts); 1842 } 1843 1844 if (TLI.isTypeLegal(NewInVT)) { 1845 // Because the result and the input are different vector types, widening 1846 // the result could create a legal type but widening the input might make 1847 // it an illegal type that might lead to repeatedly splitting the input 1848 // and then widening it. To avoid this, we widen the input only if 1849 // it results in a legal type. 1850 SmallVector<SDValue, 16> Ops(NewNumElts); 1851 SDValue UndefVal = DAG.getUNDEF(InVT); 1852 Ops[0] = InOp; 1853 for (unsigned i = 1; i < NewNumElts; ++i) 1854 Ops[i] = UndefVal; 1855 1856 SDValue NewVec; 1857 if (InVT.isVector()) 1858 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1859 NewInVT, &Ops[0], NewNumElts); 1860 else 1861 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, 1862 NewInVT, &Ops[0], NewNumElts); 1863 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec); 1864 } 1865 } 1866 1867 return CreateStackStoreLoad(InOp, WidenVT); 1868} 1869 1870SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) { 1871 SDLoc dl(N); 1872 // Build a vector with undefined for the new nodes. 1873 EVT VT = N->getValueType(0); 1874 EVT EltVT = VT.getVectorElementType(); 1875 unsigned NumElts = VT.getVectorNumElements(); 1876 1877 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1878 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1879 1880 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end()); 1881 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!"); 1882 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT)); 1883 1884 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size()); 1885} 1886 1887SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) { 1888 EVT InVT = N->getOperand(0).getValueType(); 1889 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1890 SDLoc dl(N); 1891 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1892 unsigned NumInElts = InVT.getVectorNumElements(); 1893 unsigned NumOperands = N->getNumOperands(); 1894 1895 bool InputWidened = false; // Indicates we need to widen the input. 1896 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) { 1897 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) { 1898 // Add undef vectors to widen to correct length. 1899 unsigned NumConcat = WidenVT.getVectorNumElements() / 1900 InVT.getVectorNumElements(); 1901 SDValue UndefVal = DAG.getUNDEF(InVT); 1902 SmallVector<SDValue, 16> Ops(NumConcat); 1903 for (unsigned i=0; i < NumOperands; ++i) 1904 Ops[i] = N->getOperand(i); 1905 for (unsigned i = NumOperands; i != NumConcat; ++i) 1906 Ops[i] = UndefVal; 1907 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat); 1908 } 1909 } else { 1910 InputWidened = true; 1911 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) { 1912 // The inputs and the result are widen to the same value. 1913 unsigned i; 1914 for (i=1; i < NumOperands; ++i) 1915 if (N->getOperand(i).getOpcode() != ISD::UNDEF) 1916 break; 1917 1918 if (i == NumOperands) 1919 // Everything but the first operand is an UNDEF so just return the 1920 // widened first operand. 1921 return GetWidenedVector(N->getOperand(0)); 1922 1923 if (NumOperands == 2) { 1924 // Replace concat of two operands with a shuffle. 1925 SmallVector<int, 16> MaskOps(WidenNumElts, -1); 1926 for (unsigned i = 0; i < NumInElts; ++i) { 1927 MaskOps[i] = i; 1928 MaskOps[i + NumInElts] = i + WidenNumElts; 1929 } 1930 return DAG.getVectorShuffle(WidenVT, dl, 1931 GetWidenedVector(N->getOperand(0)), 1932 GetWidenedVector(N->getOperand(1)), 1933 &MaskOps[0]); 1934 } 1935 } 1936 } 1937 1938 // Fall back to use extracts and build vector. 1939 EVT EltVT = WidenVT.getVectorElementType(); 1940 SmallVector<SDValue, 16> Ops(WidenNumElts); 1941 unsigned Idx = 0; 1942 for (unsigned i=0; i < NumOperands; ++i) { 1943 SDValue InOp = N->getOperand(i); 1944 if (InputWidened) 1945 InOp = GetWidenedVector(InOp); 1946 for (unsigned j=0; j < NumInElts; ++j) 1947 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1948 DAG.getIntPtrConstant(j)); 1949 } 1950 SDValue UndefVal = DAG.getUNDEF(EltVT); 1951 for (; Idx < WidenNumElts; ++Idx) 1952 Ops[Idx] = UndefVal; 1953 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1954} 1955 1956SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { 1957 SDLoc dl(N); 1958 SDValue InOp = N->getOperand(0); 1959 SDValue RndOp = N->getOperand(3); 1960 SDValue SatOp = N->getOperand(4); 1961 1962 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1963 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1964 1965 EVT InVT = InOp.getValueType(); 1966 EVT InEltVT = InVT.getVectorElementType(); 1967 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1968 1969 SDValue DTyOp = DAG.getValueType(WidenVT); 1970 SDValue STyOp = DAG.getValueType(InWidenVT); 1971 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 1972 1973 unsigned InVTNumElts = InVT.getVectorNumElements(); 1974 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1975 InOp = GetWidenedVector(InOp); 1976 InVT = InOp.getValueType(); 1977 InVTNumElts = InVT.getVectorNumElements(); 1978 if (InVTNumElts == WidenNumElts) 1979 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1980 SatOp, CvtCode); 1981 } 1982 1983 if (TLI.isTypeLegal(InWidenVT)) { 1984 // Because the result and the input are different vector types, widening 1985 // the result could create a legal type but widening the input might make 1986 // it an illegal type that might lead to repeatedly splitting the input 1987 // and then widening it. To avoid this, we widen the input only if 1988 // it results in a legal type. 1989 if (WidenNumElts % InVTNumElts == 0) { 1990 // Widen the input and call convert on the widened input vector. 1991 unsigned NumConcat = WidenNumElts/InVTNumElts; 1992 SmallVector<SDValue, 16> Ops(NumConcat); 1993 Ops[0] = InOp; 1994 SDValue UndefVal = DAG.getUNDEF(InVT); 1995 for (unsigned i = 1; i != NumConcat; ++i) 1996 Ops[i] = UndefVal; 1997 1998 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat); 1999 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 2000 SatOp, CvtCode); 2001 } 2002 2003 if (InVTNumElts % WidenNumElts == 0) { 2004 // Extract the input and convert the shorten input vector. 2005 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp, 2006 DAG.getIntPtrConstant(0)); 2007 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 2008 SatOp, CvtCode); 2009 } 2010 } 2011 2012 // Otherwise unroll into some nasty scalar code and rebuild the vector. 2013 SmallVector<SDValue, 16> Ops(WidenNumElts); 2014 EVT EltVT = WidenVT.getVectorElementType(); 2015 DTyOp = DAG.getValueType(EltVT); 2016 STyOp = DAG.getValueType(InEltVT); 2017 2018 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 2019 unsigned i; 2020 for (i=0; i < MinElts; ++i) { 2021 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 2022 DAG.getIntPtrConstant(i)); 2023 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp, 2024 SatOp, CvtCode); 2025 } 2026 2027 SDValue UndefVal = DAG.getUNDEF(EltVT); 2028 for (; i < WidenNumElts; ++i) 2029 Ops[i] = UndefVal; 2030 2031 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 2032} 2033 2034SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 2035 EVT VT = N->getValueType(0); 2036 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2037 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2038 SDValue InOp = N->getOperand(0); 2039 SDValue Idx = N->getOperand(1); 2040 SDLoc dl(N); 2041 2042 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2043 InOp = GetWidenedVector(InOp); 2044 2045 EVT InVT = InOp.getValueType(); 2046 2047 // Check if we can just return the input vector after widening. 2048 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 2049 if (IdxVal == 0 && InVT == WidenVT) 2050 return InOp; 2051 2052 // Check if we can extract from the vector. 2053 unsigned InNumElts = InVT.getVectorNumElements(); 2054 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts) 2055 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx); 2056 2057 // We could try widening the input to the right length but for now, extract 2058 // the original elements, fill the rest with undefs and build a vector. 2059 SmallVector<SDValue, 16> Ops(WidenNumElts); 2060 EVT EltVT = VT.getVectorElementType(); 2061 unsigned NumElts = VT.getVectorNumElements(); 2062 unsigned i; 2063 for (i=0; i < NumElts; ++i) 2064 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2065 DAG.getIntPtrConstant(IdxVal+i)); 2066 2067 SDValue UndefVal = DAG.getUNDEF(EltVT); 2068 for (; i < WidenNumElts; ++i) 2069 Ops[i] = UndefVal; 2070 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 2071} 2072 2073SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) { 2074 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2075 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), 2076 InOp.getValueType(), InOp, 2077 N->getOperand(1), N->getOperand(2)); 2078} 2079 2080SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) { 2081 LoadSDNode *LD = cast<LoadSDNode>(N); 2082 ISD::LoadExtType ExtType = LD->getExtensionType(); 2083 2084 SDValue Result; 2085 SmallVector<SDValue, 16> LdChain; // Chain for the series of load 2086 if (ExtType != ISD::NON_EXTLOAD) 2087 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); 2088 else 2089 Result = GenWidenVectorLoads(LdChain, LD); 2090 2091 // If we generate a single load, we can use that for the chain. Otherwise, 2092 // build a factor node to remember the multiple loads are independent and 2093 // chain to that. 2094 SDValue NewChain; 2095 if (LdChain.size() == 1) 2096 NewChain = LdChain[0]; 2097 else 2098 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, 2099 &LdChain[0], LdChain.size()); 2100 2101 // Modified the chain - switch anything that used the old chain to use 2102 // the new one. 2103 ReplaceValueWith(SDValue(N, 1), NewChain); 2104 2105 return Result; 2106} 2107 2108SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) { 2109 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2110 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), 2111 WidenVT, N->getOperand(0)); 2112} 2113 2114SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) { 2115 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2116 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2117 2118 SDValue Cond1 = N->getOperand(0); 2119 EVT CondVT = Cond1.getValueType(); 2120 if (CondVT.isVector()) { 2121 EVT CondEltVT = CondVT.getVectorElementType(); 2122 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), 2123 CondEltVT, WidenNumElts); 2124 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector) 2125 Cond1 = GetWidenedVector(Cond1); 2126 2127 if (Cond1.getValueType() != CondWidenVT) 2128 Cond1 = ModifyToType(Cond1, CondWidenVT); 2129 } 2130 2131 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 2132 SDValue InOp2 = GetWidenedVector(N->getOperand(2)); 2133 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT); 2134 return DAG.getNode(N->getOpcode(), SDLoc(N), 2135 WidenVT, Cond1, InOp1, InOp2); 2136} 2137 2138SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) { 2139 SDValue InOp1 = GetWidenedVector(N->getOperand(2)); 2140 SDValue InOp2 = GetWidenedVector(N->getOperand(3)); 2141 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), 2142 InOp1.getValueType(), N->getOperand(0), 2143 N->getOperand(1), InOp1, InOp2, N->getOperand(4)); 2144} 2145 2146SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) { 2147 assert(N->getValueType(0).isVector() == 2148 N->getOperand(0).getValueType().isVector() && 2149 "Scalar/Vector type mismatch"); 2150 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N); 2151 2152 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2153 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 2154 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 2155 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT, 2156 InOp1, InOp2, N->getOperand(2)); 2157} 2158 2159SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) { 2160 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2161 return DAG.getUNDEF(WidenVT); 2162} 2163 2164SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) { 2165 EVT VT = N->getValueType(0); 2166 SDLoc dl(N); 2167 2168 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2169 unsigned NumElts = VT.getVectorNumElements(); 2170 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2171 2172 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 2173 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 2174 2175 // Adjust mask based on new input vector length. 2176 SmallVector<int, 16> NewMask; 2177 for (unsigned i = 0; i != NumElts; ++i) { 2178 int Idx = N->getMaskElt(i); 2179 if (Idx < (int)NumElts) 2180 NewMask.push_back(Idx); 2181 else 2182 NewMask.push_back(Idx - NumElts + WidenNumElts); 2183 } 2184 for (unsigned i = NumElts; i != WidenNumElts; ++i) 2185 NewMask.push_back(-1); 2186 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]); 2187} 2188 2189SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) { 2190 assert(N->getValueType(0).isVector() && 2191 N->getOperand(0).getValueType().isVector() && 2192 "Operands must be vectors"); 2193 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2194 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2195 2196 SDValue InOp1 = N->getOperand(0); 2197 EVT InVT = InOp1.getValueType(); 2198 assert(InVT.isVector() && "can not widen non vector type"); 2199 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(), 2200 InVT.getVectorElementType(), WidenNumElts); 2201 InOp1 = GetWidenedVector(InOp1); 2202 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 2203 2204 // Assume that the input and output will be widen appropriately. If not, 2205 // we will have to unroll it at some point. 2206 assert(InOp1.getValueType() == WidenInVT && 2207 InOp2.getValueType() == WidenInVT && 2208 "Input not widened to expected type!"); 2209 (void)WidenInVT; 2210 return DAG.getNode(ISD::SETCC, SDLoc(N), 2211 WidenVT, InOp1, InOp2, N->getOperand(2)); 2212} 2213 2214 2215//===----------------------------------------------------------------------===// 2216// Widen Vector Operand 2217//===----------------------------------------------------------------------===// 2218bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) { 2219 DEBUG(dbgs() << "Widen node operand " << OpNo << ": "; 2220 N->dump(&DAG); 2221 dbgs() << "\n"); 2222 SDValue Res = SDValue(); 2223 2224 // See if the target wants to custom widen this node. 2225 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 2226 return false; 2227 2228 switch (N->getOpcode()) { 2229 default: 2230#ifndef NDEBUG 2231 dbgs() << "WidenVectorOperand op #" << OpNo << ": "; 2232 N->dump(&DAG); 2233 dbgs() << "\n"; 2234#endif 2235 llvm_unreachable("Do not know how to widen this operator's operand!"); 2236 2237 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break; 2238 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break; 2239 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break; 2240 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break; 2241 case ISD::STORE: Res = WidenVecOp_STORE(N); break; 2242 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break; 2243 2244 case ISD::FP_EXTEND: 2245 case ISD::FP_TO_SINT: 2246 case ISD::FP_TO_UINT: 2247 case ISD::SINT_TO_FP: 2248 case ISD::UINT_TO_FP: 2249 case ISD::TRUNCATE: 2250 case ISD::SIGN_EXTEND: 2251 case ISD::ZERO_EXTEND: 2252 case ISD::ANY_EXTEND: 2253 Res = WidenVecOp_Convert(N); 2254 break; 2255 } 2256 2257 // If Res is null, the sub-method took care of registering the result. 2258 if (!Res.getNode()) return false; 2259 2260 // If the result is N, the sub-method updated N in place. Tell the legalizer 2261 // core about this. 2262 if (Res.getNode() == N) 2263 return true; 2264 2265 2266 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2267 "Invalid operand expansion"); 2268 2269 ReplaceValueWith(SDValue(N, 0), Res); 2270 return false; 2271} 2272 2273SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) { 2274 // Since the result is legal and the input is illegal, it is unlikely 2275 // that we can fix the input to a legal type so unroll the convert 2276 // into some scalar code and create a nasty build vector. 2277 EVT VT = N->getValueType(0); 2278 EVT EltVT = VT.getVectorElementType(); 2279 SDLoc dl(N); 2280 unsigned NumElts = VT.getVectorNumElements(); 2281 SDValue InOp = N->getOperand(0); 2282 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2283 InOp = GetWidenedVector(InOp); 2284 EVT InVT = InOp.getValueType(); 2285 EVT InEltVT = InVT.getVectorElementType(); 2286 2287 unsigned Opcode = N->getOpcode(); 2288 SmallVector<SDValue, 16> Ops(NumElts); 2289 for (unsigned i=0; i < NumElts; ++i) 2290 Ops[i] = DAG.getNode(Opcode, dl, EltVT, 2291 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 2292 DAG.getIntPtrConstant(i))); 2293 2294 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2295} 2296 2297SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) { 2298 EVT VT = N->getValueType(0); 2299 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2300 EVT InWidenVT = InOp.getValueType(); 2301 SDLoc dl(N); 2302 2303 // Check if we can convert between two legal vector types and extract. 2304 unsigned InWidenSize = InWidenVT.getSizeInBits(); 2305 unsigned Size = VT.getSizeInBits(); 2306 // x86mmx is not an acceptable vector element type, so don't try. 2307 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) { 2308 unsigned NewNumElts = InWidenSize / Size; 2309 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); 2310 if (TLI.isTypeLegal(NewVT)) { 2311 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp); 2312 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, 2313 DAG.getIntPtrConstant(0)); 2314 } 2315 } 2316 2317 return CreateStackStoreLoad(InOp, VT); 2318} 2319 2320SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) { 2321 // If the input vector is not legal, it is likely that we will not find a 2322 // legal vector of the same size. Replace the concatenate vector with a 2323 // nasty build vector. 2324 EVT VT = N->getValueType(0); 2325 EVT EltVT = VT.getVectorElementType(); 2326 SDLoc dl(N); 2327 unsigned NumElts = VT.getVectorNumElements(); 2328 SmallVector<SDValue, 16> Ops(NumElts); 2329 2330 EVT InVT = N->getOperand(0).getValueType(); 2331 unsigned NumInElts = InVT.getVectorNumElements(); 2332 2333 unsigned Idx = 0; 2334 unsigned NumOperands = N->getNumOperands(); 2335 for (unsigned i=0; i < NumOperands; ++i) { 2336 SDValue InOp = N->getOperand(i); 2337 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2338 InOp = GetWidenedVector(InOp); 2339 for (unsigned j=0; j < NumInElts; ++j) 2340 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2341 DAG.getIntPtrConstant(j)); 2342 } 2343 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2344} 2345 2346SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 2347 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2348 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), 2349 N->getValueType(0), InOp, N->getOperand(1)); 2350} 2351 2352SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 2353 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2354 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), 2355 N->getValueType(0), InOp, N->getOperand(1)); 2356} 2357 2358SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) { 2359 // We have to widen the value but we want only to store the original 2360 // vector type. 2361 StoreSDNode *ST = cast<StoreSDNode>(N); 2362 2363 SmallVector<SDValue, 16> StChain; 2364 if (ST->isTruncatingStore()) 2365 GenWidenVectorTruncStores(StChain, ST); 2366 else 2367 GenWidenVectorStores(StChain, ST); 2368 2369 if (StChain.size() == 1) 2370 return StChain[0]; 2371 else 2372 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), 2373 MVT::Other,&StChain[0],StChain.size()); 2374} 2375 2376SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) { 2377 SDValue InOp0 = GetWidenedVector(N->getOperand(0)); 2378 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 2379 SDLoc dl(N); 2380 2381 // WARNING: In this code we widen the compare instruction with garbage. 2382 // This garbage may contain denormal floats which may be slow. Is this a real 2383 // concern ? Should we zero the unused lanes if this is a float compare ? 2384 2385 // Get a new SETCC node to compare the newly widened operands. 2386 // Only some of the compared elements are legal. 2387 EVT SVT = TLI.getSetCCResultType(*DAG.getContext(), InOp0.getValueType()); 2388 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N), 2389 SVT, InOp0, InOp1, N->getOperand(2)); 2390 2391 // Extract the needed results from the result vector. 2392 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), 2393 SVT.getVectorElementType(), 2394 N->getValueType(0).getVectorNumElements()); 2395 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, 2396 ResVT, WideSETCC, DAG.getIntPtrConstant(0)); 2397 2398 return PromoteTargetBoolean(CC, N->getValueType(0)); 2399} 2400 2401 2402//===----------------------------------------------------------------------===// 2403// Vector Widening Utilities 2404//===----------------------------------------------------------------------===// 2405 2406// Utility function to find the type to chop up a widen vector for load/store 2407// TLI: Target lowering used to determine legal types. 2408// Width: Width left need to load/store. 2409// WidenVT: The widen vector type to load to/store from 2410// Align: If 0, don't allow use of a wider type 2411// WidenEx: If Align is not 0, the amount additional we can load/store from. 2412 2413static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, 2414 unsigned Width, EVT WidenVT, 2415 unsigned Align = 0, unsigned WidenEx = 0) { 2416 EVT WidenEltVT = WidenVT.getVectorElementType(); 2417 unsigned WidenWidth = WidenVT.getSizeInBits(); 2418 unsigned WidenEltWidth = WidenEltVT.getSizeInBits(); 2419 unsigned AlignInBits = Align*8; 2420 2421 // If we have one element to load/store, return it. 2422 EVT RetVT = WidenEltVT; 2423 if (Width == WidenEltWidth) 2424 return RetVT; 2425 2426 // See if there is larger legal integer than the element type to load/store 2427 unsigned VT; 2428 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE; 2429 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) { 2430 EVT MemVT((MVT::SimpleValueType) VT); 2431 unsigned MemVTWidth = MemVT.getSizeInBits(); 2432 if (MemVT.getSizeInBits() <= WidenEltWidth) 2433 break; 2434 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 && 2435 isPowerOf2_32(WidenWidth / MemVTWidth) && 2436 (MemVTWidth <= Width || 2437 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2438 RetVT = MemVT; 2439 break; 2440 } 2441 } 2442 2443 // See if there is a larger vector type to load/store that has the same vector 2444 // element type and is evenly divisible with the WidenVT. 2445 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; 2446 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) { 2447 EVT MemVT = (MVT::SimpleValueType) VT; 2448 unsigned MemVTWidth = MemVT.getSizeInBits(); 2449 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() && 2450 (WidenWidth % MemVTWidth) == 0 && 2451 isPowerOf2_32(WidenWidth / MemVTWidth) && 2452 (MemVTWidth <= Width || 2453 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2454 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT) 2455 return MemVT; 2456 } 2457 } 2458 2459 return RetVT; 2460} 2461 2462// Builds a vector type from scalar loads 2463// VecTy: Resulting Vector type 2464// LDOps: Load operators to build a vector type 2465// [Start,End) the list of loads to use. 2466static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, 2467 SmallVector<SDValue, 16>& LdOps, 2468 unsigned Start, unsigned End) { 2469 SDLoc dl(LdOps[Start]); 2470 EVT LdTy = LdOps[Start].getValueType(); 2471 unsigned Width = VecTy.getSizeInBits(); 2472 unsigned NumElts = Width / LdTy.getSizeInBits(); 2473 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts); 2474 2475 unsigned Idx = 1; 2476 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]); 2477 2478 for (unsigned i = Start + 1; i != End; ++i) { 2479 EVT NewLdTy = LdOps[i].getValueType(); 2480 if (NewLdTy != LdTy) { 2481 NumElts = Width / NewLdTy.getSizeInBits(); 2482 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts); 2483 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp); 2484 // Readjust position and vector position based on new load type 2485 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits(); 2486 LdTy = NewLdTy; 2487 } 2488 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], 2489 DAG.getIntPtrConstant(Idx++)); 2490 } 2491 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp); 2492} 2493 2494SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain, 2495 LoadSDNode *LD) { 2496 // The strategy assumes that we can efficiently load powers of two widths. 2497 // The routines chops the vector into the largest vector loads with the same 2498 // element type or scalar loads and then recombines it to the widen vector 2499 // type. 2500 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2501 unsigned WidenWidth = WidenVT.getSizeInBits(); 2502 EVT LdVT = LD->getMemoryVT(); 2503 SDLoc dl(LD); 2504 assert(LdVT.isVector() && WidenVT.isVector()); 2505 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType()); 2506 2507 // Load information 2508 SDValue Chain = LD->getChain(); 2509 SDValue BasePtr = LD->getBasePtr(); 2510 unsigned Align = LD->getAlignment(); 2511 bool isVolatile = LD->isVolatile(); 2512 bool isNonTemporal = LD->isNonTemporal(); 2513 bool isInvariant = LD->isInvariant(); 2514 2515 int LdWidth = LdVT.getSizeInBits(); 2516 int WidthDiff = WidenWidth - LdWidth; // Difference 2517 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads 2518 2519 // Find the vector type that can load from. 2520 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2521 int NewVTWidth = NewVT.getSizeInBits(); 2522 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(), 2523 isVolatile, isNonTemporal, isInvariant, Align); 2524 LdChain.push_back(LdOp.getValue(1)); 2525 2526 // Check if we can load the element with one instruction 2527 if (LdWidth <= NewVTWidth) { 2528 if (!NewVT.isVector()) { 2529 unsigned NumElts = WidenWidth / NewVTWidth; 2530 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2531 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp); 2532 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp); 2533 } 2534 if (NewVT == WidenVT) 2535 return LdOp; 2536 2537 assert(WidenWidth % NewVTWidth == 0); 2538 unsigned NumConcat = WidenWidth / NewVTWidth; 2539 SmallVector<SDValue, 16> ConcatOps(NumConcat); 2540 SDValue UndefVal = DAG.getUNDEF(NewVT); 2541 ConcatOps[0] = LdOp; 2542 for (unsigned i = 1; i != NumConcat; ++i) 2543 ConcatOps[i] = UndefVal; 2544 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], 2545 NumConcat); 2546 } 2547 2548 // Load vector by using multiple loads from largest vector to scalar 2549 SmallVector<SDValue, 16> LdOps; 2550 LdOps.push_back(LdOp); 2551 2552 LdWidth -= NewVTWidth; 2553 unsigned Offset = 0; 2554 2555 while (LdWidth > 0) { 2556 unsigned Increment = NewVTWidth / 8; 2557 Offset += Increment; 2558 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2559 DAG.getIntPtrConstant(Increment)); 2560 2561 SDValue L; 2562 if (LdWidth < NewVTWidth) { 2563 // Our current type we are using is too large, find a better size 2564 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2565 NewVTWidth = NewVT.getSizeInBits(); 2566 L = DAG.getLoad(NewVT, dl, Chain, BasePtr, 2567 LD->getPointerInfo().getWithOffset(Offset), isVolatile, 2568 isNonTemporal, isInvariant, MinAlign(Align, Increment)); 2569 LdChain.push_back(L.getValue(1)); 2570 if (L->getValueType(0).isVector()) { 2571 SmallVector<SDValue, 16> Loads; 2572 Loads.push_back(L); 2573 unsigned size = L->getValueSizeInBits(0); 2574 while (size < LdOp->getValueSizeInBits(0)) { 2575 Loads.push_back(DAG.getUNDEF(L->getValueType(0))); 2576 size += L->getValueSizeInBits(0); 2577 } 2578 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), 2579 &Loads[0], Loads.size()); 2580 } 2581 } else { 2582 L = DAG.getLoad(NewVT, dl, Chain, BasePtr, 2583 LD->getPointerInfo().getWithOffset(Offset), isVolatile, 2584 isNonTemporal, isInvariant, MinAlign(Align, Increment)); 2585 LdChain.push_back(L.getValue(1)); 2586 } 2587 2588 LdOps.push_back(L); 2589 2590 2591 LdWidth -= NewVTWidth; 2592 } 2593 2594 // Build the vector from the loads operations 2595 unsigned End = LdOps.size(); 2596 if (!LdOps[0].getValueType().isVector()) 2597 // All the loads are scalar loads. 2598 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End); 2599 2600 // If the load contains vectors, build the vector using concat vector. 2601 // All of the vectors used to loads are power of 2 and the scalars load 2602 // can be combined to make a power of 2 vector. 2603 SmallVector<SDValue, 16> ConcatOps(End); 2604 int i = End - 1; 2605 int Idx = End; 2606 EVT LdTy = LdOps[i].getValueType(); 2607 // First combine the scalar loads to a vector 2608 if (!LdTy.isVector()) { 2609 for (--i; i >= 0; --i) { 2610 LdTy = LdOps[i].getValueType(); 2611 if (LdTy.isVector()) 2612 break; 2613 } 2614 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End); 2615 } 2616 ConcatOps[--Idx] = LdOps[i]; 2617 for (--i; i >= 0; --i) { 2618 EVT NewLdTy = LdOps[i].getValueType(); 2619 if (NewLdTy != LdTy) { 2620 // Create a larger vector 2621 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy, 2622 &ConcatOps[Idx], End - Idx); 2623 Idx = End - 1; 2624 LdTy = NewLdTy; 2625 } 2626 ConcatOps[--Idx] = LdOps[i]; 2627 } 2628 2629 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx)) 2630 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, 2631 &ConcatOps[Idx], End - Idx); 2632 2633 // We need to fill the rest with undefs to build the vector 2634 unsigned NumOps = WidenWidth / LdTy.getSizeInBits(); 2635 SmallVector<SDValue, 16> WidenOps(NumOps); 2636 SDValue UndefVal = DAG.getUNDEF(LdTy); 2637 { 2638 unsigned i = 0; 2639 for (; i != End-Idx; ++i) 2640 WidenOps[i] = ConcatOps[Idx+i]; 2641 for (; i != NumOps; ++i) 2642 WidenOps[i] = UndefVal; 2643 } 2644 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps); 2645} 2646 2647SDValue 2648DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain, 2649 LoadSDNode * LD, 2650 ISD::LoadExtType ExtType) { 2651 // For extension loads, it may not be more efficient to chop up the vector 2652 // and then extended it. Instead, we unroll the load and build a new vector. 2653 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2654 EVT LdVT = LD->getMemoryVT(); 2655 SDLoc dl(LD); 2656 assert(LdVT.isVector() && WidenVT.isVector()); 2657 2658 // Load information 2659 SDValue Chain = LD->getChain(); 2660 SDValue BasePtr = LD->getBasePtr(); 2661 unsigned Align = LD->getAlignment(); 2662 bool isVolatile = LD->isVolatile(); 2663 bool isNonTemporal = LD->isNonTemporal(); 2664 2665 EVT EltVT = WidenVT.getVectorElementType(); 2666 EVT LdEltVT = LdVT.getVectorElementType(); 2667 unsigned NumElts = LdVT.getVectorNumElements(); 2668 2669 // Load each element and widen 2670 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2671 SmallVector<SDValue, 16> Ops(WidenNumElts); 2672 unsigned Increment = LdEltVT.getSizeInBits() / 8; 2673 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, 2674 LD->getPointerInfo(), 2675 LdEltVT, isVolatile, isNonTemporal, Align); 2676 LdChain.push_back(Ops[0].getValue(1)); 2677 unsigned i = 0, Offset = Increment; 2678 for (i=1; i < NumElts; ++i, Offset += Increment) { 2679 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2680 BasePtr, DAG.getIntPtrConstant(Offset)); 2681 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, 2682 LD->getPointerInfo().getWithOffset(Offset), LdEltVT, 2683 isVolatile, isNonTemporal, Align); 2684 LdChain.push_back(Ops[i].getValue(1)); 2685 } 2686 2687 // Fill the rest with undefs 2688 SDValue UndefVal = DAG.getUNDEF(EltVT); 2689 for (; i != WidenNumElts; ++i) 2690 Ops[i] = UndefVal; 2691 2692 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size()); 2693} 2694 2695 2696void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, 2697 StoreSDNode *ST) { 2698 // The strategy assumes that we can efficiently store powers of two widths. 2699 // The routines chops the vector into the largest vector stores with the same 2700 // element type or scalar stores. 2701 SDValue Chain = ST->getChain(); 2702 SDValue BasePtr = ST->getBasePtr(); 2703 unsigned Align = ST->getAlignment(); 2704 bool isVolatile = ST->isVolatile(); 2705 bool isNonTemporal = ST->isNonTemporal(); 2706 SDValue ValOp = GetWidenedVector(ST->getValue()); 2707 SDLoc dl(ST); 2708 2709 EVT StVT = ST->getMemoryVT(); 2710 unsigned StWidth = StVT.getSizeInBits(); 2711 EVT ValVT = ValOp.getValueType(); 2712 unsigned ValWidth = ValVT.getSizeInBits(); 2713 EVT ValEltVT = ValVT.getVectorElementType(); 2714 unsigned ValEltWidth = ValEltVT.getSizeInBits(); 2715 assert(StVT.getVectorElementType() == ValEltVT); 2716 2717 int Idx = 0; // current index to store 2718 unsigned Offset = 0; // offset from base to store 2719 while (StWidth != 0) { 2720 // Find the largest vector type we can store with 2721 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT); 2722 unsigned NewVTWidth = NewVT.getSizeInBits(); 2723 unsigned Increment = NewVTWidth / 8; 2724 if (NewVT.isVector()) { 2725 unsigned NumVTElts = NewVT.getVectorNumElements(); 2726 do { 2727 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, 2728 DAG.getIntPtrConstant(Idx)); 2729 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2730 ST->getPointerInfo().getWithOffset(Offset), 2731 isVolatile, isNonTemporal, 2732 MinAlign(Align, Offset))); 2733 StWidth -= NewVTWidth; 2734 Offset += Increment; 2735 Idx += NumVTElts; 2736 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2737 DAG.getIntPtrConstant(Increment)); 2738 } while (StWidth != 0 && StWidth >= NewVTWidth); 2739 } else { 2740 // Cast the vector to the scalar type we can store 2741 unsigned NumElts = ValWidth / NewVTWidth; 2742 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2743 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); 2744 // Readjust index position based on new vector type 2745 Idx = Idx * ValEltWidth / NewVTWidth; 2746 do { 2747 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp, 2748 DAG.getIntPtrConstant(Idx++)); 2749 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2750 ST->getPointerInfo().getWithOffset(Offset), 2751 isVolatile, isNonTemporal, 2752 MinAlign(Align, Offset))); 2753 StWidth -= NewVTWidth; 2754 Offset += Increment; 2755 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2756 DAG.getIntPtrConstant(Increment)); 2757 } while (StWidth != 0 && StWidth >= NewVTWidth); 2758 // Restore index back to be relative to the original widen element type 2759 Idx = Idx * NewVTWidth / ValEltWidth; 2760 } 2761 } 2762} 2763 2764void 2765DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain, 2766 StoreSDNode *ST) { 2767 // For extension loads, it may not be more efficient to truncate the vector 2768 // and then store it. Instead, we extract each element and then store it. 2769 SDValue Chain = ST->getChain(); 2770 SDValue BasePtr = ST->getBasePtr(); 2771 unsigned Align = ST->getAlignment(); 2772 bool isVolatile = ST->isVolatile(); 2773 bool isNonTemporal = ST->isNonTemporal(); 2774 SDValue ValOp = GetWidenedVector(ST->getValue()); 2775 SDLoc dl(ST); 2776 2777 EVT StVT = ST->getMemoryVT(); 2778 EVT ValVT = ValOp.getValueType(); 2779 2780 // It must be true that we the widen vector type is bigger than where 2781 // we need to store. 2782 assert(StVT.isVector() && ValOp.getValueType().isVector()); 2783 assert(StVT.bitsLT(ValOp.getValueType())); 2784 2785 // For truncating stores, we can not play the tricks of chopping legal 2786 // vector types and bit cast it to the right type. Instead, we unroll 2787 // the store. 2788 EVT StEltVT = StVT.getVectorElementType(); 2789 EVT ValEltVT = ValVT.getVectorElementType(); 2790 unsigned Increment = ValEltVT.getSizeInBits() / 8; 2791 unsigned NumElts = StVT.getVectorNumElements(); 2792 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2793 DAG.getIntPtrConstant(0)); 2794 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, 2795 ST->getPointerInfo(), StEltVT, 2796 isVolatile, isNonTemporal, Align)); 2797 unsigned Offset = Increment; 2798 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) { 2799 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2800 BasePtr, DAG.getIntPtrConstant(Offset)); 2801 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2802 DAG.getIntPtrConstant(0)); 2803 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, 2804 ST->getPointerInfo().getWithOffset(Offset), 2805 StEltVT, isVolatile, isNonTemporal, 2806 MinAlign(Align, Offset))); 2807 } 2808} 2809 2810/// Modifies a vector input (widen or narrows) to a vector of NVT. The 2811/// input vector must have the same element type as NVT. 2812SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) { 2813 // Note that InOp might have been widened so it might already have 2814 // the right width or it might need be narrowed. 2815 EVT InVT = InOp.getValueType(); 2816 assert(InVT.getVectorElementType() == NVT.getVectorElementType() && 2817 "input and widen element type must match"); 2818 SDLoc dl(InOp); 2819 2820 // Check if InOp already has the right width. 2821 if (InVT == NVT) 2822 return InOp; 2823 2824 unsigned InNumElts = InVT.getVectorNumElements(); 2825 unsigned WidenNumElts = NVT.getVectorNumElements(); 2826 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) { 2827 unsigned NumConcat = WidenNumElts / InNumElts; 2828 SmallVector<SDValue, 16> Ops(NumConcat); 2829 SDValue UndefVal = DAG.getUNDEF(InVT); 2830 Ops[0] = InOp; 2831 for (unsigned i = 1; i != NumConcat; ++i) 2832 Ops[i] = UndefVal; 2833 2834 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat); 2835 } 2836 2837 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts) 2838 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp, 2839 DAG.getIntPtrConstant(0)); 2840 2841 // Fall back to extract and build. 2842 SmallVector<SDValue, 16> Ops(WidenNumElts); 2843 EVT EltVT = NVT.getVectorElementType(); 2844 unsigned MinNumElts = std::min(WidenNumElts, InNumElts); 2845 unsigned Idx; 2846 for (Idx = 0; Idx < MinNumElts; ++Idx) 2847 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2848 DAG.getIntPtrConstant(Idx)); 2849 2850 SDValue UndefVal = DAG.getUNDEF(EltVT); 2851 for ( ; Idx < WidenNumElts; ++Idx) 2852 Ops[Idx] = UndefVal; 2853 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts); 2854} 2855