LegalizeVectorTypes.cpp revision 704e72b7b766bd03aec122657a18cdfa063c8cba
1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file performs vector type splitting and scalarization for LegalizeTypes. 11// Scalarization is the act of changing a computation in an illegal one-element 12// vector type to be a computation in its scalar element type. For example, 13// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed 14// as a base case when scalarizing vector arithmetic like <4 x f32>, which 15// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32 16// types. 17// Splitting is the act of changing a computation in an invalid vector type to 18// be a computation in multiple vectors of a smaller type. For example, 19// implementing <128 x f32> operations in terms of two <64 x f32> operations. 20// 21//===----------------------------------------------------------------------===// 22 23#include "LegalizeTypes.h" 24using namespace llvm; 25 26//===----------------------------------------------------------------------===// 27// Result Vector Scalarization: <1 x ty> -> ty. 28//===----------------------------------------------------------------------===// 29 30void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { 31 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG); 32 cerr << "\n"); 33 SDValue R = SDValue(); 34 35 switch (N->getOpcode()) { 36 default: 37#ifndef NDEBUG 38 cerr << "ScalarizeVectorResult #" << ResNo << ": "; 39 N->dump(&DAG); cerr << "\n"; 40#endif 41 assert(0 && "Do not know how to scalarize the result of this operator!"); 42 abort(); 43 44 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break; 45 case ISD::BUILD_VECTOR: R = N->getOperand(0); break; 46 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 47 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 48 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; 49 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break; 50 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; 51 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; 52 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break; 53 54 case ISD::CTLZ: 55 case ISD::CTPOP: 56 case ISD::CTTZ: 57 case ISD::FABS: 58 case ISD::FCOS: 59 case ISD::FNEG: 60 case ISD::FP_TO_SINT: 61 case ISD::FP_TO_UINT: 62 case ISD::FSIN: 63 case ISD::FSQRT: 64 case ISD::FTRUNC: 65 case ISD::FFLOOR: 66 case ISD::FCEIL: 67 case ISD::FRINT: 68 case ISD::FNEARBYINT: 69 case ISD::SINT_TO_FP: 70 case ISD::UINT_TO_FP: R = ScalarizeVecRes_UnaryOp(N); break; 71 72 case ISD::ADD: 73 case ISD::AND: 74 case ISD::FADD: 75 case ISD::FDIV: 76 case ISD::FMUL: 77 case ISD::FPOW: 78 case ISD::FREM: 79 case ISD::FSUB: 80 case ISD::MUL: 81 case ISD::OR: 82 case ISD::SDIV: 83 case ISD::SREM: 84 case ISD::SUB: 85 case ISD::UDIV: 86 case ISD::UREM: 87 case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break; 88 } 89 90 // If R is null, the sub-method took care of registering the result. 91 if (R.getNode()) 92 SetScalarizedVector(SDValue(N, ResNo), R); 93} 94 95SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { 96 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 97 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 98 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 99} 100 101SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) { 102 MVT NewVT = N->getValueType(0).getVectorElementType(); 103 return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0)); 104} 105 106SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) { 107 SDValue Op = GetScalarizedVector(N->getOperand(0)); 108 return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1)); 109} 110 111SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { 112 // The value to insert may have a wider type than the vector element type, 113 // so be sure to truncate it to the element type if necessary. 114 SDValue Op = N->getOperand(1); 115 MVT EltVT = N->getValueType(0).getVectorElementType(); 116 if (Op.getValueType() != EltVT) 117 // FIXME: Can this happen for floating point types? 118 Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op); 119 return Op; 120} 121 122SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { 123 assert(N->isUnindexed() && "Indexed vector load?"); 124 125 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getExtensionType(), 126 N->getValueType(0).getVectorElementType(), 127 N->getChain(), N->getBasePtr(), 128 DAG.getNode(ISD::UNDEF, 129 N->getBasePtr().getValueType()), 130 N->getSrcValue(), N->getSrcValueOffset(), 131 N->getMemoryVT().getVectorElementType(), 132 N->isVolatile(), N->getAlignment()); 133 134 // Legalized the chain result - switch anything that used the old chain to 135 // use the new one. 136 ReplaceValueWith(SDValue(N, 1), Result.getValue(1)); 137 return Result; 138} 139 140SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { 141 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp. 142 MVT DestVT = TLI.getTypeToTransformTo(N->getValueType(0)); 143 SDValue Op = GetScalarizedVector(N->getOperand(0)); 144 return DAG.getNode(N->getOpcode(), DestVT, Op); 145} 146 147SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { 148 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType()); 149} 150 151SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) { 152 SDValue LHS = GetScalarizedVector(N->getOperand(1)); 153 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS, 154 GetScalarizedVector(N->getOperand(2))); 155} 156 157SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { 158 // Figure out if the scalar is the LHS or RHS and return it. 159 SDValue Arg = N->getOperand(2).getOperand(0); 160 if (Arg.getOpcode() == ISD::UNDEF) 161 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType()); 162 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue(); 163 return GetScalarizedVector(N->getOperand(Op)); 164} 165 166SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) { 167 MVT NewVT = N->getValueType(0).getVectorElementType(); 168 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 169 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 170 LHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, RHS, 171 N->getOperand(2)); 172 return 173 DAG.getNode(ISD::SELECT, NewVT, LHS, 174 DAG.getConstant(APInt::getAllOnesValue(NewVT.getSizeInBits()), 175 NewVT), 176 DAG.getConstant(0ULL, NewVT)); 177} 178 179 180//===----------------------------------------------------------------------===// 181// Operand Vector Scalarization <1 x ty> -> ty. 182//===----------------------------------------------------------------------===// 183 184bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { 185 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG); 186 cerr << "\n"); 187 SDValue Res = SDValue(); 188 189 if (Res.getNode() == 0) { 190 switch (N->getOpcode()) { 191 default: 192#ifndef NDEBUG 193 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": "; 194 N->dump(&DAG); cerr << "\n"; 195#endif 196 assert(0 && "Do not know how to scalarize this operator's operand!"); 197 abort(); 198 199 case ISD::BIT_CONVERT: 200 Res = ScalarizeVecOp_BIT_CONVERT(N); break; 201 202 case ISD::EXTRACT_VECTOR_ELT: 203 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break; 204 205 case ISD::STORE: 206 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break; 207 } 208 } 209 210 // If the result is null, the sub-method took care of registering results etc. 211 if (!Res.getNode()) return false; 212 213 // If the result is N, the sub-method updated N in place. Check to see if any 214 // operands are new, and if so, mark them. 215 if (Res.getNode() == N) { 216 // Mark N as new and remark N and its operands. This allows us to correctly 217 // revisit N if it needs another step of promotion and allows us to visit 218 // any new operands to N. 219 ReanalyzeNode(N); 220 return true; 221 } 222 223 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 224 "Invalid operand expansion"); 225 226 ReplaceValueWith(SDValue(N, 0), Res); 227 return false; 228} 229 230/// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs 231/// to be scalarized, it must be <1 x ty>. Convert the element instead. 232SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) { 233 SDValue Elt = GetScalarizedVector(N->getOperand(0)); 234 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt); 235} 236 237/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to 238/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the 239/// index. 240SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 241 return GetScalarizedVector(N->getOperand(0)); 242} 243 244/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be 245/// scalarized, it must be <1 x ty>. Just store the element. 246SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ 247 assert(N->isUnindexed() && "Indexed store of one-element vector?"); 248 assert(OpNo == 1 && "Do not know how to scalarize this operand!"); 249 250 if (N->isTruncatingStore()) 251 return DAG.getTruncStore(N->getChain(), 252 GetScalarizedVector(N->getOperand(1)), 253 N->getBasePtr(), 254 N->getSrcValue(), N->getSrcValueOffset(), 255 N->getMemoryVT().getVectorElementType(), 256 N->isVolatile(), N->getAlignment()); 257 258 return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)), 259 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(), 260 N->isVolatile(), N->getAlignment()); 261} 262 263 264//===----------------------------------------------------------------------===// 265// Result Vector Splitting 266//===----------------------------------------------------------------------===// 267 268/// SplitVectorResult - This method is called when the specified result of the 269/// specified node is found to need vector splitting. At this point, the node 270/// may also have invalid operands or may have other results that need 271/// legalization, we just know that (at least) one result needs vector 272/// splitting. 273void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { 274 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n"); 275 SDValue Lo, Hi; 276 277 switch (N->getOpcode()) { 278 default: 279#ifndef NDEBUG 280 cerr << "SplitVectorResult #" << ResNo << ": "; 281 N->dump(&DAG); cerr << "\n"; 282#endif 283 assert(0 && "Do not know how to split the result of this operator!"); 284 abort(); 285 286 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 287 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 288 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 289 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 290 291 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break; 292 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 293 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 294 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; 295 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 296 case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break; 297 case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break; 298 case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break; 299 300 case ISD::CTTZ: 301 case ISD::CTLZ: 302 case ISD::CTPOP: 303 case ISD::FNEG: 304 case ISD::FABS: 305 case ISD::FSQRT: 306 case ISD::FSIN: 307 case ISD::FCOS: 308 case ISD::FTRUNC: 309 case ISD::FFLOOR: 310 case ISD::FCEIL: 311 case ISD::FRINT: 312 case ISD::FNEARBYINT: 313 case ISD::FP_TO_SINT: 314 case ISD::FP_TO_UINT: 315 case ISD::SINT_TO_FP: 316 case ISD::UINT_TO_FP: SplitVecRes_UnaryOp(N, Lo, Hi); break; 317 318 case ISD::ADD: 319 case ISD::SUB: 320 case ISD::MUL: 321 case ISD::FADD: 322 case ISD::FSUB: 323 case ISD::FMUL: 324 case ISD::SDIV: 325 case ISD::UDIV: 326 case ISD::FDIV: 327 case ISD::FPOW: 328 case ISD::AND: 329 case ISD::OR: 330 case ISD::XOR: 331 case ISD::UREM: 332 case ISD::SREM: 333 case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break; 334 } 335 336 // If Lo/Hi is null, the sub-method took care of registering results etc. 337 if (Lo.getNode()) 338 SetSplitVector(SDValue(N, ResNo), Lo, Hi); 339} 340 341void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo, 342 SDValue &Hi) { 343 SDValue LHSLo, LHSHi; 344 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 345 SDValue RHSLo, RHSHi; 346 GetSplitVector(N->getOperand(1), RHSLo, RHSHi); 347 348 Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo); 349 Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi); 350} 351 352void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo, 353 SDValue &Hi) { 354 // We know the result is a vector. The input may be either a vector or a 355 // scalar value. 356 MVT LoVT, HiVT; 357 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 358 359 SDValue InOp = N->getOperand(0); 360 MVT InVT = InOp.getValueType(); 361 362 // Handle some special cases efficiently. 363 switch (getTypeAction(InVT)) { 364 default: 365 assert(false && "Unknown type action!"); 366 case Legal: 367 case PromoteInteger: 368 case SoftenFloat: 369 case ScalarizeVector: 370 break; 371 case ExpandInteger: 372 case ExpandFloat: 373 // A scalar to vector conversion, where the scalar needs expansion. 374 // If the vector is being split in two then we can just convert the 375 // expanded pieces. 376 if (LoVT == HiVT) { 377 GetExpandedOp(InOp, Lo, Hi); 378 if (TLI.isBigEndian()) 379 std::swap(Lo, Hi); 380 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo); 381 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi); 382 return; 383 } 384 break; 385 case SplitVector: 386 // If the input is a vector that needs to be split, convert each split 387 // piece of the input now. 388 GetSplitVector(InOp, Lo, Hi); 389 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo); 390 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi); 391 return; 392 } 393 394 // In the general case, convert the input to an integer and split it by hand. 395 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits()); 396 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits()); 397 if (TLI.isBigEndian()) 398 std::swap(LoIntVT, HiIntVT); 399 400 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); 401 402 if (TLI.isBigEndian()) 403 std::swap(Lo, Hi); 404 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo); 405 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi); 406} 407 408void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, 409 SDValue &Hi) { 410 MVT LoVT, HiVT; 411 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 412 unsigned LoNumElts = LoVT.getVectorNumElements(); 413 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts); 414 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size()); 415 416 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end()); 417 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size()); 418} 419 420void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, 421 SDValue &Hi) { 422 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"); 423 unsigned NumSubvectors = N->getNumOperands() / 2; 424 if (NumSubvectors == 1) { 425 Lo = N->getOperand(0); 426 Hi = N->getOperand(1); 427 return; 428 } 429 430 MVT LoVT, HiVT; 431 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 432 433 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); 434 Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size()); 435 436 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end()); 437 Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size()); 438} 439 440void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, 441 SDValue &Hi) { 442 GetSplitVector(N->getOperand(0), Lo, Hi); 443 Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1)); 444 Hi = DAG.getNode(ISD::FPOWI, Hi.getValueType(), Hi, N->getOperand(1)); 445} 446 447void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, 448 SDValue &Hi) { 449 SDValue Vec = N->getOperand(0); 450 SDValue Elt = N->getOperand(1); 451 SDValue Idx = N->getOperand(2); 452 GetSplitVector(Vec, Lo, Hi); 453 454 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 455 unsigned IdxVal = CIdx->getZExtValue(); 456 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 457 if (IdxVal < LoNumElts) 458 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx); 459 else 460 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, Elt, 461 DAG.getIntPtrConstant(IdxVal - LoNumElts)); 462 return; 463 } 464 465 // Spill the vector to the stack. 466 MVT VecVT = Vec.getValueType(); 467 MVT EltVT = VecVT.getVectorElementType(); 468 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 469 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 470 471 // Store the new element. This may be larger than the vector element type, 472 // so use a truncating store. 473 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 474 Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT); 475 476 // Reload the vector from the stack. 477 SDValue Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0); 478 479 // Split it. 480 SplitVecRes_LOAD(cast<LoadSDNode>(Load.getNode()), Lo, Hi); 481} 482 483void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, 484 SDValue &Hi) { 485 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"); 486 MVT LoVT, HiVT; 487 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); 488 489 ISD::LoadExtType ExtType = LD->getExtensionType(); 490 SDValue Ch = LD->getChain(); 491 SDValue Ptr = LD->getBasePtr(); 492 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); 493 const Value *SV = LD->getSrcValue(); 494 int SVOffset = LD->getSrcValueOffset(); 495 MVT MemoryVT = LD->getMemoryVT(); 496 unsigned Alignment = LD->getAlignment(); 497 bool isVolatile = LD->isVolatile(); 498 499 MVT LoMemVT, HiMemVT; 500 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 501 502 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, Ch, Ptr, Offset, 503 SV, SVOffset, LoMemVT, isVolatile, Alignment); 504 505 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 506 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 507 DAG.getIntPtrConstant(IncrementSize)); 508 SVOffset += IncrementSize; 509 Alignment = MinAlign(Alignment, IncrementSize); 510 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, Ch, Ptr, Offset, 511 SV, SVOffset, HiMemVT, isVolatile, Alignment); 512 513 // Build a factor node to remember that this load is independent of the 514 // other one. 515 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 516 Hi.getValue(1)); 517 518 // Legalized the chain result - switch anything that used the old chain to 519 // use the new one. 520 ReplaceValueWith(SDValue(LD, 1), Ch); 521} 522 523void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, 524 SDValue &Hi) { 525 // Get the dest types - they may not match the input types, e.g. int_to_fp. 526 MVT LoVT, HiVT; 527 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 528 529 // Split the input. 530 MVT InVT = N->getOperand(0).getValueType(); 531 switch (getTypeAction(InVT)) { 532 default: assert(0 && "Unexpected type action!"); 533 case Legal: { 534 assert(LoVT == HiVT && "Legal non-power-of-two vector type?"); 535 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(), 536 LoVT.getVectorNumElements()); 537 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0), 538 DAG.getIntPtrConstant(0)); 539 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0), 540 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 541 break; 542 } 543 case SplitVector: 544 GetSplitVector(N->getOperand(0), Lo, Hi); 545 break; 546 } 547 548 Lo = DAG.getNode(N->getOpcode(), LoVT, Lo); 549 Hi = DAG.getNode(N->getOpcode(), HiVT, Hi); 550} 551 552void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo, 553 SDValue &Hi) { 554 // Build the low part. 555 SDValue Mask = N->getOperand(2); 556 SmallVector<SDValue, 16> Ops; 557 MVT LoVT, HiVT; 558 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 559 MVT EltVT = LoVT.getVectorElementType(); 560 unsigned LoNumElts = LoVT.getVectorNumElements(); 561 unsigned NumElements = Mask.getNumOperands(); 562 563 // Insert all of the elements from the input that are needed. We use 564 // buildvector of extractelement here because the input vectors will have 565 // to be legalized, so this makes the code simpler. 566 for (unsigned i = 0; i != LoNumElts; ++i) { 567 SDValue Arg = Mask.getOperand(i); 568 if (Arg.getOpcode() == ISD::UNDEF) { 569 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 570 } else { 571 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue(); 572 SDValue InVec = N->getOperand(0); 573 if (Idx >= NumElements) { 574 InVec = N->getOperand(1); 575 Idx -= NumElements; 576 } 577 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec, 578 DAG.getIntPtrConstant(Idx))); 579 } 580 } 581 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &Ops[0], Ops.size()); 582 Ops.clear(); 583 584 for (unsigned i = LoNumElts; i != NumElements; ++i) { 585 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue(); 586 SDValue InVec = N->getOperand(0); 587 if (Idx >= NumElements) { 588 InVec = N->getOperand(1); 589 Idx -= NumElements; 590 } 591 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec, 592 DAG.getIntPtrConstant(Idx))); 593 } 594 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size()); 595} 596 597void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo, 598 SDValue &Hi) { 599 MVT LoVT, HiVT; 600 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 601 602 SDValue LL, LH, RL, RH; 603 GetSplitVector(N->getOperand(0), LL, LH); 604 GetSplitVector(N->getOperand(1), RL, RH); 605 606 Lo = DAG.getNode(ISD::VSETCC, LoVT, LL, RL, N->getOperand(2)); 607 Hi = DAG.getNode(ISD::VSETCC, HiVT, LH, RH, N->getOperand(2)); 608} 609 610 611//===----------------------------------------------------------------------===// 612// Operand Vector Splitting 613//===----------------------------------------------------------------------===// 614 615/// SplitVectorOperand - This method is called when the specified operand of the 616/// specified node is found to need vector splitting. At this point, all of the 617/// result types of the node are known to be legal, but other operands of the 618/// node may need legalization as well as the specified one. 619bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { 620 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n"); 621 SDValue Res = SDValue(); 622 623 if (Res.getNode() == 0) { 624 switch (N->getOpcode()) { 625 default: 626#ifndef NDEBUG 627 cerr << "SplitVectorOperand Op #" << OpNo << ": "; 628 N->dump(&DAG); cerr << "\n"; 629#endif 630 assert(0 && "Do not know how to split this operator's operand!"); 631 abort(); 632 633 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break; 634 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; 635 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; 636 case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N), 637 OpNo); break; 638 case ISD::VECTOR_SHUFFLE: Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);break; 639 } 640 } 641 642 // If the result is null, the sub-method took care of registering results etc. 643 if (!Res.getNode()) return false; 644 645 // If the result is N, the sub-method updated N in place. Check to see if any 646 // operands are new, and if so, mark them. 647 if (Res.getNode() == N) { 648 // Mark N as new and remark N and its operands. This allows us to correctly 649 // revisit N if it needs another step of promotion and allows us to visit 650 // any new operands to N. 651 ReanalyzeNode(N); 652 return true; 653 } 654 655 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 656 "Invalid operand expansion"); 657 658 ReplaceValueWith(SDValue(N, 0), Res); 659 return false; 660} 661 662SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) { 663 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will 664 // end up being split all the way down to individual components. Convert the 665 // split pieces into integers and reassemble. 666 SDValue Lo, Hi; 667 GetSplitVector(N->getOperand(0), Lo, Hi); 668 Lo = BitConvertToInteger(Lo); 669 Hi = BitConvertToInteger(Hi); 670 671 if (TLI.isBigEndian()) 672 std::swap(Lo, Hi); 673 674 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), 675 JoinIntegers(Lo, Hi)); 676} 677 678SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 679 // We know that the extracted result type is legal. For now, assume the index 680 // is a constant. 681 MVT SubVT = N->getValueType(0); 682 SDValue Idx = N->getOperand(1); 683 SDValue Lo, Hi; 684 GetSplitVector(N->getOperand(0), Lo, Hi); 685 686 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 687 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 688 689 if (IdxVal < LoElts) { 690 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && 691 "Extracted subvector crosses vector split!"); 692 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx); 693 } else { 694 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi, 695 DAG.getConstant(IdxVal - LoElts, Idx.getValueType())); 696 } 697} 698 699SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 700 SDValue Vec = N->getOperand(0); 701 SDValue Idx = N->getOperand(1); 702 MVT VecVT = Vec.getValueType(); 703 704 if (isa<ConstantSDNode>(Idx)) { 705 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 706 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); 707 708 SDValue Lo, Hi; 709 GetSplitVector(Vec, Lo, Hi); 710 711 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 712 713 if (IdxVal < LoElts) 714 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx); 715 else 716 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi, 717 DAG.getConstant(IdxVal - LoElts, 718 Idx.getValueType())); 719 } 720 721 // Store the vector to the stack. 722 MVT EltVT = VecVT.getVectorElementType(); 723 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 724 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 725 726 // Load back the required element. 727 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 728 return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0); 729} 730 731SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { 732 assert(N->isUnindexed() && "Indexed store of vector?"); 733 assert(OpNo == 1 && "Can only split the stored value"); 734 735 bool isTruncating = N->isTruncatingStore(); 736 SDValue Ch = N->getChain(); 737 SDValue Ptr = N->getBasePtr(); 738 int SVOffset = N->getSrcValueOffset(); 739 MVT MemoryVT = N->getMemoryVT(); 740 unsigned Alignment = N->getAlignment(); 741 bool isVol = N->isVolatile(); 742 SDValue Lo, Hi; 743 GetSplitVector(N->getOperand(1), Lo, Hi); 744 745 MVT LoMemVT, HiMemVT; 746 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 747 748 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 749 750 if (isTruncating) 751 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 752 LoMemVT, isVol, Alignment); 753 else 754 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 755 isVol, Alignment); 756 757 // Increment the pointer to the other half. 758 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 759 DAG.getIntPtrConstant(IncrementSize)); 760 761 if (isTruncating) 762 Hi = DAG.getTruncStore(Ch, Hi, Ptr, 763 N->getSrcValue(), SVOffset+IncrementSize, 764 HiMemVT, 765 isVol, MinAlign(Alignment, IncrementSize)); 766 else 767 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize, 768 isVol, MinAlign(Alignment, IncrementSize)); 769 770 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 771} 772 773SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) { 774 assert(OpNo == 2 && "Shuffle source type differs from result type?"); 775 SDValue Mask = N->getOperand(2); 776 unsigned MaskLength = Mask.getValueType().getVectorNumElements(); 777 unsigned LargestMaskEntryPlusOne = 2 * MaskLength; 778 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne); 779 780 // Look for a legal vector type to place the mask values in. 781 // Note that there may not be *any* legal vector-of-integer 782 // type for which the element type is legal! 783 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE; 784 EltVT <= MVT::LAST_INTEGER_VALUETYPE; 785 // Integer values types are consecutively numbered. Exploit this. 786 EltVT = MVT::SimpleValueType(EltVT + 1)) { 787 788 // Is the element type big enough to hold the values? 789 if (MVT(EltVT).getSizeInBits() < MinimumBitWidth) 790 // Nope. 791 continue; 792 793 // Is the vector type legal? 794 MVT VecVT = MVT::getVectorVT(EltVT, MaskLength); 795 if (!isTypeLegal(VecVT)) 796 // Nope. 797 continue; 798 799 // If the element type is not legal, find a larger legal type to use for 800 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work! 801 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic 802 // node where the shuffle mask is a list of integer operands, #2 .. #2+n. 803 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE; 804 // Integer values types are consecutively numbered. Exploit this. 805 OpVT = MVT::SimpleValueType(OpVT + 1)) { 806 if (!isTypeLegal(OpVT)) 807 continue; 808 809 // Success! Rebuild the vector using the legal types. 810 SmallVector<SDValue, 16> Ops(MaskLength); 811 for (unsigned i = 0; i < MaskLength; ++i) { 812 SDValue Arg = Mask.getOperand(i); 813 if (Arg.getOpcode() == ISD::UNDEF) { 814 Ops[i] = DAG.getNode(ISD::UNDEF, OpVT); 815 } else { 816 uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue(); 817 Ops[i] = DAG.getConstant(Idx, OpVT); 818 } 819 } 820 return DAG.UpdateNodeOperands(SDValue(N,0), 821 N->getOperand(0), N->getOperand(1), 822 DAG.getNode(ISD::BUILD_VECTOR, 823 VecVT, &Ops[0], Ops.size())); 824 } 825 826 // Continuing is pointless - failure is certain. 827 break; 828 } 829 assert(false && "Failed to find an appropriate mask type!"); 830 return SDValue(N, 0); 831} 832