LegalizeVectorTypes.cpp revision 9008ca6b6b4f638cfafccb593cbc5b1d3f5ab877
1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file performs vector type splitting and scalarization for LegalizeTypes. 11// Scalarization is the act of changing a computation in an illegal one-element 12// vector type to be a computation in its scalar element type. For example, 13// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed 14// as a base case when scalarizing vector arithmetic like <4 x f32>, which 15// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32 16// types. 17// Splitting is the act of changing a computation in an invalid vector type to 18// be a computation in multiple vectors of a smaller type. For example, 19// implementing <128 x f32> operations in terms of two <64 x f32> operations. 20// 21//===----------------------------------------------------------------------===// 22 23#include "LegalizeTypes.h" 24#include "llvm/CodeGen/PseudoSourceValue.h" 25#include "llvm/Target/TargetData.h" 26using namespace llvm; 27 28//===----------------------------------------------------------------------===// 29// Result Vector Scalarization: <1 x ty> -> ty. 30//===----------------------------------------------------------------------===// 31 32void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { 33 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG); 34 cerr << "\n"); 35 SDValue R = SDValue(); 36 37 switch (N->getOpcode()) { 38 default: 39#ifndef NDEBUG 40 cerr << "ScalarizeVectorResult #" << ResNo << ": "; 41 N->dump(&DAG); cerr << "\n"; 42#endif 43 assert(0 && "Do not know how to scalarize the result of this operator!"); 44 abort(); 45 46 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break; 47 case ISD::BUILD_VECTOR: R = N->getOperand(0); break; 48 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; 49 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 50 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 51 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 52 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; 53 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; 54 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break; 55 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; 56 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; 57 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; 58 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break; 59 60 case ISD::CTLZ: 61 case ISD::CTPOP: 62 case ISD::CTTZ: 63 case ISD::FABS: 64 case ISD::FCOS: 65 case ISD::FNEG: 66 case ISD::FP_TO_SINT: 67 case ISD::FP_TO_UINT: 68 case ISD::FSIN: 69 case ISD::FSQRT: 70 case ISD::FTRUNC: 71 case ISD::FFLOOR: 72 case ISD::FCEIL: 73 case ISD::FRINT: 74 case ISD::FNEARBYINT: 75 case ISD::SINT_TO_FP: 76 case ISD::TRUNCATE: 77 case ISD::UINT_TO_FP: R = ScalarizeVecRes_UnaryOp(N); break; 78 79 case ISD::ADD: 80 case ISD::AND: 81 case ISD::FADD: 82 case ISD::FDIV: 83 case ISD::FMUL: 84 case ISD::FPOW: 85 case ISD::FREM: 86 case ISD::FSUB: 87 case ISD::MUL: 88 case ISD::OR: 89 case ISD::SDIV: 90 case ISD::SREM: 91 case ISD::SUB: 92 case ISD::UDIV: 93 case ISD::UREM: 94 case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break; 95 96 case ISD::SHL: 97 case ISD::SRA: 98 case ISD::SRL: R = ScalarizeVecRes_ShiftOp(N); break; 99 } 100 101 // If R is null, the sub-method took care of registering the result. 102 if (R.getNode()) 103 SetScalarizedVector(SDValue(N, ResNo), R); 104} 105 106SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { 107 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 108 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 109 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 110 LHS.getValueType(), LHS, RHS); 111} 112 113SDValue DAGTypeLegalizer::ScalarizeVecRes_ShiftOp(SDNode *N) { 114 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 115 SDValue ShiftAmt = GetScalarizedVector(N->getOperand(1)); 116 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 117 LHS.getValueType(), LHS, ShiftAmt); 118} 119 120SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) { 121 MVT NewVT = N->getValueType(0).getVectorElementType(); 122 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 123 NewVT, N->getOperand(0)); 124} 125 126SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) { 127 MVT NewVT = N->getValueType(0).getVectorElementType(); 128 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); 129 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(), 130 Op0, DAG.getValueType(NewVT), 131 DAG.getValueType(Op0.getValueType()), 132 N->getOperand(3), 133 N->getOperand(4), 134 cast<CvtRndSatSDNode>(N)->getCvtCode()); 135} 136 137SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 138 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 139 N->getValueType(0).getVectorElementType(), 140 N->getOperand(0), N->getOperand(1)); 141} 142 143SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) { 144 SDValue Op = GetScalarizedVector(N->getOperand(0)); 145 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(), 146 Op.getValueType(), Op, N->getOperand(1)); 147} 148 149SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { 150 // The value to insert may have a wider type than the vector element type, 151 // so be sure to truncate it to the element type if necessary. 152 SDValue Op = N->getOperand(1); 153 MVT EltVT = N->getValueType(0).getVectorElementType(); 154 if (Op.getValueType() != EltVT) 155 // FIXME: Can this happen for floating point types? 156 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op); 157 return Op; 158} 159 160SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { 161 assert(N->isUnindexed() && "Indexed vector load?"); 162 163 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getDebugLoc(), 164 N->getExtensionType(), 165 N->getValueType(0).getVectorElementType(), 166 N->getChain(), N->getBasePtr(), 167 DAG.getUNDEF(N->getBasePtr().getValueType()), 168 N->getSrcValue(), N->getSrcValueOffset(), 169 N->getMemoryVT().getVectorElementType(), 170 N->isVolatile(), N->getAlignment()); 171 172 // Legalized the chain result - switch anything that used the old chain to 173 // use the new one. 174 ReplaceValueWith(SDValue(N, 1), Result.getValue(1)); 175 return Result; 176} 177 178SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { 179 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp. 180 MVT DestVT = N->getValueType(0).getVectorElementType(); 181 SDValue Op = GetScalarizedVector(N->getOperand(0)); 182 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op); 183} 184 185SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) { 186 // If the operand is wider than the vector element type then it is implicitly 187 // truncated. Make that explicit here. 188 MVT EltVT = N->getValueType(0).getVectorElementType(); 189 SDValue InOp = N->getOperand(0); 190 if (InOp.getValueType() != EltVT) 191 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp); 192 return InOp; 193} 194 195SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) { 196 SDValue LHS = GetScalarizedVector(N->getOperand(1)); 197 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 198 LHS.getValueType(), N->getOperand(0), LHS, 199 GetScalarizedVector(N->getOperand(2))); 200} 201 202SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) { 203 SDValue LHS = GetScalarizedVector(N->getOperand(2)); 204 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(), 205 N->getOperand(0), N->getOperand(1), 206 LHS, GetScalarizedVector(N->getOperand(3)), 207 N->getOperand(4)); 208} 209 210SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { 211 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 212} 213 214SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { 215 // Figure out if the scalar is the LHS or RHS and return it. 216 SDValue Arg = N->getOperand(2).getOperand(0); 217 if (Arg.getOpcode() == ISD::UNDEF) 218 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 219 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue(); 220 return GetScalarizedVector(N->getOperand(Op)); 221} 222 223SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) { 224 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 225 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 226 MVT NVT = N->getValueType(0).getVectorElementType(); 227 MVT SVT = TLI.getSetCCResultType(LHS.getValueType()); 228 DebugLoc dl = N->getDebugLoc(); 229 230 // Turn it into a scalar SETCC. 231 SDValue Res = DAG.getNode(ISD::SETCC, dl, SVT, LHS, RHS, N->getOperand(2)); 232 233 // VSETCC always returns a sign-extended value, while SETCC may not. The 234 // SETCC result type may not match the vector element type. Correct these. 235 if (NVT.bitsLE(SVT)) { 236 // The SETCC result type is bigger than the vector element type. 237 // Ensure the SETCC result is sign-extended. 238 if (TLI.getBooleanContents() != 239 TargetLowering::ZeroOrNegativeOneBooleanContent) 240 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, SVT, Res, 241 DAG.getValueType(MVT::i1)); 242 // Truncate to the final type. 243 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res); 244 } else { 245 // The SETCC result type is smaller than the vector element type. 246 // If the SetCC result is not sign-extended, chop it down to MVT::i1. 247 if (TLI.getBooleanContents() != 248 TargetLowering::ZeroOrNegativeOneBooleanContent) 249 Res = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Res); 250 // Sign extend to the final type. 251 return DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Res); 252 } 253} 254 255 256//===----------------------------------------------------------------------===// 257// Operand Vector Scalarization <1 x ty> -> ty. 258//===----------------------------------------------------------------------===// 259 260bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { 261 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG); 262 cerr << "\n"); 263 SDValue Res = SDValue(); 264 265 if (Res.getNode() == 0) { 266 switch (N->getOpcode()) { 267 default: 268#ifndef NDEBUG 269 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": "; 270 N->dump(&DAG); cerr << "\n"; 271#endif 272 assert(0 && "Do not know how to scalarize this operator's operand!"); 273 abort(); 274 275 case ISD::BIT_CONVERT: 276 Res = ScalarizeVecOp_BIT_CONVERT(N); break; 277 278 case ISD::CONCAT_VECTORS: 279 Res = ScalarizeVecOp_CONCAT_VECTORS(N); break; 280 281 case ISD::EXTRACT_VECTOR_ELT: 282 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break; 283 284 case ISD::STORE: 285 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break; 286 } 287 } 288 289 // If the result is null, the sub-method took care of registering results etc. 290 if (!Res.getNode()) return false; 291 292 // If the result is N, the sub-method updated N in place. Tell the legalizer 293 // core about this. 294 if (Res.getNode() == N) 295 return true; 296 297 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 298 "Invalid operand expansion"); 299 300 ReplaceValueWith(SDValue(N, 0), Res); 301 return false; 302} 303 304/// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs 305/// to be scalarized, it must be <1 x ty>. Convert the element instead. 306SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) { 307 SDValue Elt = GetScalarizedVector(N->getOperand(0)); 308 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 309 N->getValueType(0), Elt); 310} 311 312/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one - 313/// use a BUILD_VECTOR instead. 314SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) { 315 SmallVector<SDValue, 8> Ops(N->getNumOperands()); 316 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 317 Ops[i] = GetScalarizedVector(N->getOperand(i)); 318 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0), 319 &Ops[0], Ops.size()); 320} 321 322/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to 323/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the 324/// index. 325SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 326 return GetScalarizedVector(N->getOperand(0)); 327} 328 329/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be 330/// scalarized, it must be <1 x ty>. Just store the element. 331SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ 332 assert(N->isUnindexed() && "Indexed store of one-element vector?"); 333 assert(OpNo == 1 && "Do not know how to scalarize this operand!"); 334 DebugLoc dl = N->getDebugLoc(); 335 336 if (N->isTruncatingStore()) 337 return DAG.getTruncStore(N->getChain(), dl, 338 GetScalarizedVector(N->getOperand(1)), 339 N->getBasePtr(), 340 N->getSrcValue(), N->getSrcValueOffset(), 341 N->getMemoryVT().getVectorElementType(), 342 N->isVolatile(), N->getAlignment()); 343 344 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)), 345 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(), 346 N->isVolatile(), N->getAlignment()); 347} 348 349 350//===----------------------------------------------------------------------===// 351// Result Vector Splitting 352//===----------------------------------------------------------------------===// 353 354/// SplitVectorResult - This method is called when the specified result of the 355/// specified node is found to need vector splitting. At this point, the node 356/// may also have invalid operands or may have other results that need 357/// legalization, we just know that (at least) one result needs vector 358/// splitting. 359void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { 360 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n"); 361 SDValue Lo, Hi; 362 363 switch (N->getOpcode()) { 364 default: 365#ifndef NDEBUG 366 cerr << "SplitVectorResult #" << ResNo << ": "; 367 N->dump(&DAG); cerr << "\n"; 368#endif 369 assert(0 && "Do not know how to split the result of this operator!"); 370 abort(); 371 372 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 373 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 374 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 375 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 376 377 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break; 378 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 379 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 380 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break; 381 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; 382 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; 383 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 384 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break; 385 case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break; 386 case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break; 387 case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break; 388 389 case ISD::CTTZ: 390 case ISD::CTLZ: 391 case ISD::CTPOP: 392 case ISD::FNEG: 393 case ISD::FABS: 394 case ISD::FSQRT: 395 case ISD::FSIN: 396 case ISD::FCOS: 397 case ISD::FTRUNC: 398 case ISD::FFLOOR: 399 case ISD::FCEIL: 400 case ISD::FRINT: 401 case ISD::FNEARBYINT: 402 case ISD::FP_TO_SINT: 403 case ISD::FP_TO_UINT: 404 case ISD::SINT_TO_FP: 405 case ISD::TRUNCATE: 406 case ISD::UINT_TO_FP: SplitVecRes_UnaryOp(N, Lo, Hi); break; 407 408 case ISD::ADD: 409 case ISD::SUB: 410 case ISD::MUL: 411 case ISD::FADD: 412 case ISD::FSUB: 413 case ISD::FMUL: 414 case ISD::SDIV: 415 case ISD::UDIV: 416 case ISD::FDIV: 417 case ISD::FPOW: 418 case ISD::AND: 419 case ISD::OR: 420 case ISD::XOR: 421 case ISD::SHL: 422 case ISD::SRA: 423 case ISD::SRL: 424 case ISD::UREM: 425 case ISD::SREM: 426 case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break; 427 } 428 429 // If Lo/Hi is null, the sub-method took care of registering results etc. 430 if (Lo.getNode()) 431 SetSplitVector(SDValue(N, ResNo), Lo, Hi); 432} 433 434void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo, 435 SDValue &Hi) { 436 SDValue LHSLo, LHSHi; 437 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 438 SDValue RHSLo, RHSHi; 439 GetSplitVector(N->getOperand(1), RHSLo, RHSHi); 440 DebugLoc dl = N->getDebugLoc(); 441 442 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo); 443 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi); 444} 445 446void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo, 447 SDValue &Hi) { 448 // We know the result is a vector. The input may be either a vector or a 449 // scalar value. 450 MVT LoVT, HiVT; 451 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 452 DebugLoc dl = N->getDebugLoc(); 453 454 SDValue InOp = N->getOperand(0); 455 MVT InVT = InOp.getValueType(); 456 457 // Handle some special cases efficiently. 458 switch (getTypeAction(InVT)) { 459 default: 460 assert(false && "Unknown type action!"); 461 case Legal: 462 case PromoteInteger: 463 case SoftenFloat: 464 case ScalarizeVector: 465 break; 466 case ExpandInteger: 467 case ExpandFloat: 468 // A scalar to vector conversion, where the scalar needs expansion. 469 // If the vector is being split in two then we can just convert the 470 // expanded pieces. 471 if (LoVT == HiVT) { 472 GetExpandedOp(InOp, Lo, Hi); 473 if (TLI.isBigEndian()) 474 std::swap(Lo, Hi); 475 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo); 476 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi); 477 return; 478 } 479 break; 480 case SplitVector: 481 // If the input is a vector that needs to be split, convert each split 482 // piece of the input now. 483 GetSplitVector(InOp, Lo, Hi); 484 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo); 485 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi); 486 return; 487 } 488 489 // In the general case, convert the input to an integer and split it by hand. 490 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits()); 491 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits()); 492 if (TLI.isBigEndian()) 493 std::swap(LoIntVT, HiIntVT); 494 495 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); 496 497 if (TLI.isBigEndian()) 498 std::swap(Lo, Hi); 499 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo); 500 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi); 501} 502 503void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, 504 SDValue &Hi) { 505 MVT LoVT, HiVT; 506 DebugLoc dl = N->getDebugLoc(); 507 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 508 unsigned LoNumElts = LoVT.getVectorNumElements(); 509 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts); 510 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size()); 511 512 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end()); 513 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size()); 514} 515 516void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, 517 SDValue &Hi) { 518 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"); 519 DebugLoc dl = N->getDebugLoc(); 520 unsigned NumSubvectors = N->getNumOperands() / 2; 521 if (NumSubvectors == 1) { 522 Lo = N->getOperand(0); 523 Hi = N->getOperand(1); 524 return; 525 } 526 527 MVT LoVT, HiVT; 528 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 529 530 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); 531 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size()); 532 533 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end()); 534 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size()); 535} 536 537void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo, 538 SDValue &Hi) { 539 MVT LoVT, HiVT; 540 DebugLoc dl = N->getDebugLoc(); 541 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 542 543 SDValue DTyOpLo = DAG.getValueType(LoVT); 544 SDValue DTyOpHi = DAG.getValueType(HiVT); 545 546 SDValue RndOp = N->getOperand(3); 547 SDValue SatOp = N->getOperand(4); 548 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 549 550 // Split the input. 551 SDValue VLo, VHi; 552 MVT InVT = N->getOperand(0).getValueType(); 553 switch (getTypeAction(InVT)) { 554 default: assert(0 && "Unexpected type action!"); 555 case Legal: { 556 assert(LoVT == HiVT && "Legal non-power-of-two vector type?"); 557 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(), 558 LoVT.getVectorNumElements()); 559 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 560 DAG.getIntPtrConstant(0)); 561 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 562 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 563 break; 564 } 565 case SplitVector: 566 GetSplitVector(N->getOperand(0), VLo, VHi); 567 break; 568 case WidenVector: { 569 // If the result needs to be split and the input needs to be widened, 570 // the two types must have different lengths. Use the widened result 571 // and extract from it to do the split. 572 assert(LoVT == HiVT && "Legal non-power-of-two vector type?"); 573 SDValue InOp = GetWidenedVector(N->getOperand(0)); 574 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(), 575 LoVT.getVectorNumElements()); 576 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 577 DAG.getIntPtrConstant(0)); 578 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 579 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 580 break; 581 } 582 } 583 584 SDValue STyOpLo = DAG.getValueType(VLo.getValueType()); 585 SDValue STyOpHi = DAG.getValueType(VHi.getValueType()); 586 587 Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, 588 CvtCode); 589 Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp, 590 CvtCode); 591} 592 593void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, 594 SDValue &Hi) { 595 SDValue Vec = N->getOperand(0); 596 SDValue Idx = N->getOperand(1); 597 MVT IdxVT = Idx.getValueType(); 598 DebugLoc dl = N->getDebugLoc(); 599 600 MVT LoVT, HiVT; 601 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 602 // The indices are not guaranteed to be a multiple of the new vector 603 // size unless the original vector type was split in two. 604 assert(LoVT == HiVT && "Non power-of-two vectors not supported!"); 605 606 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); 607 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx, 608 DAG.getConstant(LoVT.getVectorNumElements(), IdxVT)); 609 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, Idx); 610} 611 612void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, 613 SDValue &Hi) { 614 DebugLoc dl = N->getDebugLoc(); 615 GetSplitVector(N->getOperand(0), Lo, Hi); 616 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1)); 617 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1)); 618} 619 620void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, 621 SDValue &Hi) { 622 SDValue Vec = N->getOperand(0); 623 SDValue Elt = N->getOperand(1); 624 SDValue Idx = N->getOperand(2); 625 DebugLoc dl = N->getDebugLoc(); 626 GetSplitVector(Vec, Lo, Hi); 627 628 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 629 unsigned IdxVal = CIdx->getZExtValue(); 630 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 631 if (IdxVal < LoNumElts) 632 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 633 Lo.getValueType(), Lo, Elt, Idx); 634 else 635 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, 636 DAG.getIntPtrConstant(IdxVal - LoNumElts)); 637 return; 638 } 639 640 // Spill the vector to the stack. 641 MVT VecVT = Vec.getValueType(); 642 MVT EltVT = VecVT.getVectorElementType(); 643 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 644 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0); 645 646 // Store the new element. This may be larger than the vector element type, 647 // so use a truncating store. 648 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 649 unsigned Alignment = 650 TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForMVT()); 651 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, NULL, 0, EltVT); 652 653 // Load the Lo part from the stack slot. 654 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, NULL, 0); 655 656 // Increment the pointer to the other part. 657 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; 658 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 659 DAG.getIntPtrConstant(IncrementSize)); 660 661 // Load the Hi part from the stack slot. 662 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, NULL, 0, false, 663 MinAlign(Alignment, IncrementSize)); 664} 665 666void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, 667 SDValue &Hi) { 668 MVT LoVT, HiVT; 669 DebugLoc dl = N->getDebugLoc(); 670 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 671 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0)); 672 Hi = DAG.getUNDEF(HiVT); 673} 674 675void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, 676 SDValue &Hi) { 677 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"); 678 MVT LoVT, HiVT; 679 DebugLoc dl = LD->getDebugLoc(); 680 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); 681 682 ISD::LoadExtType ExtType = LD->getExtensionType(); 683 SDValue Ch = LD->getChain(); 684 SDValue Ptr = LD->getBasePtr(); 685 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 686 const Value *SV = LD->getSrcValue(); 687 int SVOffset = LD->getSrcValueOffset(); 688 MVT MemoryVT = LD->getMemoryVT(); 689 unsigned Alignment = LD->getAlignment(); 690 bool isVolatile = LD->isVolatile(); 691 692 MVT LoMemVT, HiMemVT; 693 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 694 695 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, LoVT, Ch, Ptr, Offset, 696 SV, SVOffset, LoMemVT, isVolatile, Alignment); 697 698 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 699 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 700 DAG.getIntPtrConstant(IncrementSize)); 701 SVOffset += IncrementSize; 702 Alignment = MinAlign(Alignment, IncrementSize); 703 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, HiVT, Ch, Ptr, Offset, 704 SV, SVOffset, HiMemVT, isVolatile, Alignment); 705 706 // Build a factor node to remember that this load is independent of the 707 // other one. 708 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 709 Hi.getValue(1)); 710 711 // Legalized the chain result - switch anything that used the old chain to 712 // use the new one. 713 ReplaceValueWith(SDValue(LD, 1), Ch); 714} 715 716void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, 717 SDValue &Hi) { 718 // Get the dest types - they may not match the input types, e.g. int_to_fp. 719 MVT LoVT, HiVT; 720 DebugLoc dl = N->getDebugLoc(); 721 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 722 723 // Split the input. 724 MVT InVT = N->getOperand(0).getValueType(); 725 switch (getTypeAction(InVT)) { 726 default: assert(0 && "Unexpected type action!"); 727 case Legal: { 728 assert(LoVT == HiVT && "Legal non-power-of-two vector type?"); 729 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(), 730 LoVT.getVectorNumElements()); 731 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 732 DAG.getIntPtrConstant(0)); 733 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 734 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 735 break; 736 } 737 case SplitVector: 738 GetSplitVector(N->getOperand(0), Lo, Hi); 739 break; 740 case WidenVector: { 741 // If the result needs to be split and the input needs to be widened, 742 // the two types must have different lengths. Use the widened result 743 // and extract from it to do the split. 744 assert(LoVT == HiVT && "Legal non-power-of-two vector type?"); 745 SDValue InOp = GetWidenedVector(N->getOperand(0)); 746 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(), 747 LoVT.getVectorNumElements()); 748 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 749 DAG.getIntPtrConstant(0)); 750 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 751 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 752 break; 753 } 754 } 755 756 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo); 757 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi); 758} 759 760void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo, 761 SDValue &Hi) { 762 // The low and high parts of the original input give four input vectors. 763 SDValue Inputs[4]; 764 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 765 DebugLoc dl = N->getDebugLoc(); 766 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]); 767 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]); 768 MVT NewVT = Inputs[0].getValueType(); 769 unsigned NewElts = NewVT.getVectorNumElements(); 770 assert(NewVT == Inputs[1].getValueType() && 771 "Non power-of-two vectors not supported!"); 772 773 // If Lo or Hi uses elements from at most two of the four input vectors, then 774 // express it as a vector shuffle of those two inputs. Otherwise extract the 775 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. 776 SmallVector<int, 16> Ops; 777 for (unsigned High = 0; High < 2; ++High) { 778 SDValue &Output = High ? Hi : Lo; 779 780 // Build a shuffle mask for the output, discovering on the fly which 781 // input vectors to use as shuffle operands (recorded in InputUsed). 782 // If building a suitable shuffle vector proves too hard, then bail 783 // out with useBuildVector set. 784 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered. 785 unsigned FirstMaskIdx = High * NewElts; 786 bool useBuildVector = false; 787 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 788 // The mask element. This indexes into the input. 789 int Idx = SVN->getMaskElt(FirstMaskIdx + MaskOffset); 790 791 // The input vector this mask element indexes into. 792 unsigned Input = (unsigned)Idx / NewElts; 793 794 if (Input >= array_lengthof(Inputs)) { 795 // The mask element does not index into any input vector. 796 Ops.push_back(-1); 797 continue; 798 } 799 800 // Turn the index into an offset from the start of the input vector. 801 Idx -= Input * NewElts; 802 803 // Find or create a shuffle vector operand to hold this input. 804 unsigned OpNo; 805 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 806 if (InputUsed[OpNo] == Input) { 807 // This input vector is already an operand. 808 break; 809 } else if (InputUsed[OpNo] == -1U) { 810 // Create a new operand for this input vector. 811 InputUsed[OpNo] = Input; 812 break; 813 } 814 } 815 816 if (OpNo >= array_lengthof(InputUsed)) { 817 // More than two input vectors used! Give up on trying to create a 818 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 819 useBuildVector = true; 820 break; 821 } 822 823 // Add the mask index for the new shuffle vector. 824 Ops.push_back(Idx + OpNo * NewElts); 825 } 826 827 if (useBuildVector) { 828 MVT EltVT = NewVT.getVectorElementType(); 829 SmallVector<SDValue, 16> SVOps; 830 831 // Extract the input elements by hand. 832 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 833 // The mask element. This indexes into the input. 834 int Idx = SVN->getMaskElt(FirstMaskIdx + MaskOffset); 835 836 // The input vector this mask element indexes into. 837 unsigned Input = (unsigned)Idx / NewElts; 838 839 if (Input >= array_lengthof(Inputs)) { 840 // The mask element is "undef" or indexes off the end of the input. 841 SVOps.push_back(DAG.getUNDEF(EltVT)); 842 continue; 843 } 844 845 // Turn the index into an offset from the start of the input vector. 846 Idx -= Input * NewElts; 847 848 // Extract the vector element by hand. 849 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 850 Inputs[Input], DAG.getIntPtrConstant(Idx))); 851 } 852 853 // Construct the Lo/Hi output using a BUILD_VECTOR. 854 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size()); 855 } else if (InputUsed[0] == -1U) { 856 // No input vectors were used! The result is undefined. 857 Output = DAG.getUNDEF(NewVT); 858 } else { 859 SDValue Op0 = Inputs[InputUsed[0]]; 860 // If only one input was used, use an undefined vector for the other. 861 SDValue Op1 = InputUsed[1] == -1U ? 862 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]]; 863 // At least one input vector was used. Create a new shuffle vector. 864 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]); 865 } 866 867 Ops.clear(); 868 } 869} 870 871void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo, 872 SDValue &Hi) { 873 MVT LoVT, HiVT; 874 DebugLoc dl = N->getDebugLoc(); 875 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 876 877 SDValue LL, LH, RL, RH; 878 GetSplitVector(N->getOperand(0), LL, LH); 879 GetSplitVector(N->getOperand(1), RL, RH); 880 881 Lo = DAG.getNode(ISD::VSETCC, dl, LoVT, LL, RL, N->getOperand(2)); 882 Hi = DAG.getNode(ISD::VSETCC, dl, HiVT, LH, RH, N->getOperand(2)); 883} 884 885 886//===----------------------------------------------------------------------===// 887// Operand Vector Splitting 888//===----------------------------------------------------------------------===// 889 890/// SplitVectorOperand - This method is called when the specified operand of the 891/// specified node is found to need vector splitting. At this point, all of the 892/// result types of the node are known to be legal, but other operands of the 893/// node may need legalization as well as the specified one. 894bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { 895 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n"); 896 SDValue Res = SDValue(); 897 898 if (Res.getNode() == 0) { 899 switch (N->getOpcode()) { 900 default: 901#ifndef NDEBUG 902 cerr << "SplitVectorOperand Op #" << OpNo << ": "; 903 N->dump(&DAG); cerr << "\n"; 904#endif 905 assert(0 && "Do not know how to split this operator's operand!"); 906 abort(); 907 908 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break; 909 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; 910 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; 911 case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N), 912 OpNo); break; 913 case ISD::VECTOR_SHUFFLE: Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);break; 914 915 case ISD::CTTZ: 916 case ISD::CTLZ: 917 case ISD::CTPOP: 918 case ISD::FP_TO_SINT: 919 case ISD::FP_TO_UINT: 920 case ISD::SINT_TO_FP: 921 case ISD::TRUNCATE: 922 case ISD::UINT_TO_FP: Res = SplitVecOp_UnaryOp(N); break; 923 } 924 } 925 926 // If the result is null, the sub-method took care of registering results etc. 927 if (!Res.getNode()) return false; 928 929 // If the result is N, the sub-method updated N in place. Tell the legalizer 930 // core about this. 931 if (Res.getNode() == N) 932 return true; 933 934 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 935 "Invalid operand expansion"); 936 937 ReplaceValueWith(SDValue(N, 0), Res); 938 return false; 939} 940 941SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) { 942 // The result has a legal vector type, but the input needs splitting. 943 MVT ResVT = N->getValueType(0); 944 SDValue Lo, Hi; 945 DebugLoc dl = N->getDebugLoc(); 946 GetSplitVector(N->getOperand(0), Lo, Hi); 947 assert(Lo.getValueType() == Hi.getValueType() && 948 "Returns legal non-power-of-two vector type?"); 949 MVT InVT = Lo.getValueType(); 950 951 MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(), 952 InVT.getVectorNumElements()); 953 954 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); 955 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); 956 957 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); 958} 959 960SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) { 961 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will 962 // end up being split all the way down to individual components. Convert the 963 // split pieces into integers and reassemble. 964 SDValue Lo, Hi; 965 GetSplitVector(N->getOperand(0), Lo, Hi); 966 Lo = BitConvertToInteger(Lo); 967 Hi = BitConvertToInteger(Hi); 968 969 if (TLI.isBigEndian()) 970 std::swap(Lo, Hi); 971 972 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), N->getValueType(0), 973 JoinIntegers(Lo, Hi)); 974} 975 976SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 977 // We know that the extracted result type is legal. For now, assume the index 978 // is a constant. 979 MVT SubVT = N->getValueType(0); 980 SDValue Idx = N->getOperand(1); 981 DebugLoc dl = N->getDebugLoc(); 982 SDValue Lo, Hi; 983 GetSplitVector(N->getOperand(0), Lo, Hi); 984 985 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 986 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 987 988 if (IdxVal < LoElts) { 989 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && 990 "Extracted subvector crosses vector split!"); 991 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); 992 } else { 993 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, 994 DAG.getConstant(IdxVal - LoElts, Idx.getValueType())); 995 } 996} 997 998SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 999 SDValue Vec = N->getOperand(0); 1000 SDValue Idx = N->getOperand(1); 1001 MVT VecVT = Vec.getValueType(); 1002 1003 if (isa<ConstantSDNode>(Idx)) { 1004 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1005 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); 1006 1007 SDValue Lo, Hi; 1008 GetSplitVector(Vec, Lo, Hi); 1009 1010 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1011 1012 if (IdxVal < LoElts) 1013 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx); 1014 else 1015 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi, 1016 DAG.getConstant(IdxVal - LoElts, 1017 Idx.getValueType())); 1018 } 1019 1020 // Store the vector to the stack. 1021 MVT EltVT = VecVT.getVectorElementType(); 1022 DebugLoc dl = N->getDebugLoc(); 1023 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 1024 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 1025 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1026 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, SV, 0); 1027 1028 // Load back the required element. 1029 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 1030 return DAG.getLoad(EltVT, dl, Store, StackPtr, SV, 0); 1031} 1032 1033SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { 1034 assert(N->isUnindexed() && "Indexed store of vector?"); 1035 assert(OpNo == 1 && "Can only split the stored value"); 1036 DebugLoc dl = N->getDebugLoc(); 1037 1038 bool isTruncating = N->isTruncatingStore(); 1039 SDValue Ch = N->getChain(); 1040 SDValue Ptr = N->getBasePtr(); 1041 int SVOffset = N->getSrcValueOffset(); 1042 MVT MemoryVT = N->getMemoryVT(); 1043 unsigned Alignment = N->getAlignment(); 1044 bool isVol = N->isVolatile(); 1045 SDValue Lo, Hi; 1046 GetSplitVector(N->getOperand(1), Lo, Hi); 1047 1048 MVT LoMemVT, HiMemVT; 1049 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 1050 1051 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 1052 1053 if (isTruncating) 1054 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, 1055 LoMemVT, isVol, Alignment); 1056 else 1057 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, 1058 isVol, Alignment); 1059 1060 // Increment the pointer to the other half. 1061 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1062 DAG.getIntPtrConstant(IncrementSize)); 1063 1064 if (isTruncating) 1065 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, 1066 N->getSrcValue(), SVOffset+IncrementSize, 1067 HiMemVT, 1068 isVol, MinAlign(Alignment, IncrementSize)); 1069 else 1070 Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize, 1071 isVol, MinAlign(Alignment, IncrementSize)); 1072 1073 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1074} 1075 1076SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) { 1077 assert(OpNo == 2 && "Shuffle source type differs from result type?"); 1078 SDValue Mask = N->getOperand(2); 1079 DebugLoc dl = N->getDebugLoc(); 1080 unsigned MaskLength = Mask.getValueType().getVectorNumElements(); 1081 unsigned LargestMaskEntryPlusOne = 2 * MaskLength; 1082 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne); 1083 1084 // Look for a legal vector type to place the mask values in. 1085 // Note that there may not be *any* legal vector-of-integer 1086 // type for which the element type is legal! 1087 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE; 1088 EltVT <= MVT::LAST_INTEGER_VALUETYPE; 1089 // Integer values types are consecutively numbered. Exploit this. 1090 EltVT = MVT::SimpleValueType(EltVT + 1)) { 1091 1092 // Is the element type big enough to hold the values? 1093 if (MVT(EltVT).getSizeInBits() < MinimumBitWidth) 1094 // Nope. 1095 continue; 1096 1097 // Is the vector type legal? 1098 MVT VecVT = MVT::getVectorVT(EltVT, MaskLength); 1099 if (!isTypeLegal(VecVT)) 1100 // Nope. 1101 continue; 1102 1103 // If the element type is not legal, find a larger legal type to use for 1104 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work! 1105 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic 1106 // node where the shuffle mask is a list of integer operands, #2 .. #2+n. 1107 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE; 1108 // Integer values types are consecutively numbered. Exploit this. 1109 OpVT = MVT::SimpleValueType(OpVT + 1)) { 1110 if (!isTypeLegal(OpVT)) 1111 continue; 1112 1113 // Success! Rebuild the vector using the legal types. 1114 SmallVector<SDValue, 16> Ops(MaskLength); 1115 for (unsigned i = 0; i < MaskLength; ++i) { 1116 SDValue Arg = Mask.getOperand(i); 1117 if (Arg.getOpcode() == ISD::UNDEF) { 1118 Ops[i] = DAG.getUNDEF(OpVT); 1119 } else { 1120 uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue(); 1121 Ops[i] = DAG.getConstant(Idx, OpVT); 1122 } 1123 } 1124 return DAG.UpdateNodeOperands(SDValue(N,0), 1125 N->getOperand(0), N->getOperand(1), 1126 DAG.getNode(ISD::BUILD_VECTOR, dl, 1127 VecVT, &Ops[0], Ops.size())); 1128 } 1129 1130 // Continuing is pointless - failure is certain. 1131 break; 1132 } 1133 assert(false && "Failed to find an appropriate mask type!"); 1134 return SDValue(N, 0); 1135} 1136 1137 1138//===----------------------------------------------------------------------===// 1139// Result Vector Widening 1140//===----------------------------------------------------------------------===// 1141 1142void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { 1143 DEBUG(cerr << "Widen node result " << ResNo << ": "; N->dump(&DAG); 1144 cerr << "\n"); 1145 SDValue Res = SDValue(); 1146 1147 switch (N->getOpcode()) { 1148 default: 1149#ifndef NDEBUG 1150 cerr << "WidenVectorResult #" << ResNo << ": "; 1151 N->dump(&DAG); cerr << "\n"; 1152#endif 1153 assert(0 && "Do not know how to widen the result of this operator!"); 1154 abort(); 1155 1156 case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break; 1157 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; 1158 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break; 1159 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break; 1160 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; 1161 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; 1162 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break; 1163 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break; 1164 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break; 1165 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; 1166 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break; 1167 case ISD::VECTOR_SHUFFLE: Res = WidenVecRes_VECTOR_SHUFFLE(N); break; 1168 case ISD::VSETCC: Res = WidenVecRes_VSETCC(N); break; 1169 1170 case ISD::ADD: 1171 case ISD::AND: 1172 case ISD::BSWAP: 1173 case ISD::FADD: 1174 case ISD::FCOPYSIGN: 1175 case ISD::FDIV: 1176 case ISD::FMUL: 1177 case ISD::FPOW: 1178 case ISD::FPOWI: 1179 case ISD::FREM: 1180 case ISD::FSUB: 1181 case ISD::MUL: 1182 case ISD::MULHS: 1183 case ISD::MULHU: 1184 case ISD::OR: 1185 case ISD::SDIV: 1186 case ISD::SREM: 1187 case ISD::UDIV: 1188 case ISD::UREM: 1189 case ISD::SUB: 1190 case ISD::XOR: Res = WidenVecRes_Binary(N); break; 1191 1192 case ISD::SHL: 1193 case ISD::SRA: 1194 case ISD::SRL: Res = WidenVecRes_Shift(N); break; 1195 1196 case ISD::ANY_EXTEND: 1197 case ISD::FP_ROUND: 1198 case ISD::FP_TO_SINT: 1199 case ISD::FP_TO_UINT: 1200 case ISD::SIGN_EXTEND: 1201 case ISD::SINT_TO_FP: 1202 case ISD::TRUNCATE: 1203 case ISD::ZERO_EXTEND: 1204 case ISD::UINT_TO_FP: Res = WidenVecRes_Convert(N); break; 1205 1206 case ISD::CTLZ: 1207 case ISD::CTPOP: 1208 case ISD::CTTZ: 1209 case ISD::FABS: 1210 case ISD::FCOS: 1211 case ISD::FNEG: 1212 case ISD::FSIN: 1213 case ISD::FSQRT: Res = WidenVecRes_Unary(N); break; 1214 } 1215 1216 // If Res is null, the sub-method took care of registering the result. 1217 if (Res.getNode()) 1218 SetWidenedVector(SDValue(N, ResNo), Res); 1219} 1220 1221SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) { 1222 // Binary op widening. 1223 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1224 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1225 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1226 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp1, InOp2); 1227} 1228 1229SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { 1230 SDValue InOp = N->getOperand(0); 1231 DebugLoc dl = N->getDebugLoc(); 1232 1233 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1234 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1235 1236 MVT InVT = InOp.getValueType(); 1237 MVT InEltVT = InVT.getVectorElementType(); 1238 MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts); 1239 1240 unsigned Opcode = N->getOpcode(); 1241 unsigned InVTNumElts = InVT.getVectorNumElements(); 1242 1243 if (getTypeAction(InVT) == WidenVector) { 1244 InOp = GetWidenedVector(N->getOperand(0)); 1245 InVT = InOp.getValueType(); 1246 InVTNumElts = InVT.getVectorNumElements(); 1247 if (InVTNumElts == WidenNumElts) 1248 return DAG.getNode(Opcode, dl, WidenVT, InOp); 1249 } 1250 1251 if (TLI.isTypeLegal(InWidenVT)) { 1252 // Because the result and the input are different vector types, widening 1253 // the result could create a legal type but widening the input might make 1254 // it an illegal type that might lead to repeatedly splitting the input 1255 // and then widening it. To avoid this, we widen the input only if 1256 // it results in a legal type. 1257 if (WidenNumElts % InVTNumElts == 0) { 1258 // Widen the input and call convert on the widened input vector. 1259 unsigned NumConcat = WidenNumElts/InVTNumElts; 1260 SmallVector<SDValue, 16> Ops(NumConcat); 1261 Ops[0] = InOp; 1262 SDValue UndefVal = DAG.getUNDEF(InVT); 1263 for (unsigned i = 1; i != NumConcat; ++i) 1264 Ops[i] = UndefVal; 1265 return DAG.getNode(Opcode, dl, WidenVT, 1266 DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, 1267 &Ops[0], NumConcat)); 1268 } 1269 1270 if (InVTNumElts % WidenNumElts == 0) { 1271 // Extract the input and convert the shorten input vector. 1272 return DAG.getNode(Opcode, dl, WidenVT, 1273 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, 1274 InOp, DAG.getIntPtrConstant(0))); 1275 } 1276 } 1277 1278 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1279 SmallVector<SDValue, 16> Ops(WidenNumElts); 1280 MVT EltVT = WidenVT.getVectorElementType(); 1281 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1282 unsigned i; 1283 for (i=0; i < MinElts; ++i) 1284 Ops[i] = DAG.getNode(Opcode, dl, EltVT, 1285 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 1286 DAG.getIntPtrConstant(i))); 1287 1288 SDValue UndefVal = DAG.getUNDEF(EltVT); 1289 for (; i < WidenNumElts; ++i) 1290 Ops[i] = UndefVal; 1291 1292 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1293} 1294 1295SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) { 1296 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1297 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1298 SDValue ShOp = N->getOperand(1); 1299 1300 MVT ShVT = ShOp.getValueType(); 1301 if (getTypeAction(ShVT) == WidenVector) { 1302 ShOp = GetWidenedVector(ShOp); 1303 ShVT = ShOp.getValueType(); 1304 } 1305 MVT ShWidenVT = MVT::getVectorVT(ShVT.getVectorElementType(), 1306 WidenVT.getVectorNumElements()); 1307 if (ShVT != ShWidenVT) 1308 ShOp = ModifyToType(ShOp, ShWidenVT); 1309 1310 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1311} 1312 1313SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) { 1314 // Unary op widening. 1315 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1316 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1317 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp); 1318} 1319 1320SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) { 1321 SDValue InOp = N->getOperand(0); 1322 MVT InVT = InOp.getValueType(); 1323 MVT VT = N->getValueType(0); 1324 MVT WidenVT = TLI.getTypeToTransformTo(VT); 1325 DebugLoc dl = N->getDebugLoc(); 1326 1327 switch (getTypeAction(InVT)) { 1328 default: 1329 assert(false && "Unknown type action!"); 1330 break; 1331 case Legal: 1332 break; 1333 case PromoteInteger: 1334 // If the InOp is promoted to the same size, convert it. Otherwise, 1335 // fall out of the switch and widen the promoted input. 1336 InOp = GetPromotedInteger(InOp); 1337 InVT = InOp.getValueType(); 1338 if (WidenVT.bitsEq(InVT)) 1339 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp); 1340 break; 1341 case SoftenFloat: 1342 case ExpandInteger: 1343 case ExpandFloat: 1344 case ScalarizeVector: 1345 case SplitVector: 1346 break; 1347 case WidenVector: 1348 // If the InOp is widened to the same size, convert it. Otherwise, fall 1349 // out of the switch and widen the widened input. 1350 InOp = GetWidenedVector(InOp); 1351 InVT = InOp.getValueType(); 1352 if (WidenVT.bitsEq(InVT)) 1353 // The input widens to the same size. Convert to the widen value. 1354 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp); 1355 break; 1356 } 1357 1358 unsigned WidenSize = WidenVT.getSizeInBits(); 1359 unsigned InSize = InVT.getSizeInBits(); 1360 if (WidenSize % InSize == 0) { 1361 // Determine new input vector type. The new input vector type will use 1362 // the same element type (if its a vector) or use the input type as a 1363 // vector. It is the same size as the type to widen to. 1364 MVT NewInVT; 1365 unsigned NewNumElts = WidenSize / InSize; 1366 if (InVT.isVector()) { 1367 MVT InEltVT = InVT.getVectorElementType(); 1368 NewInVT= MVT::getVectorVT(InEltVT, WidenSize / InEltVT.getSizeInBits()); 1369 } else { 1370 NewInVT = MVT::getVectorVT(InVT, NewNumElts); 1371 } 1372 1373 if (TLI.isTypeLegal(NewInVT)) { 1374 // Because the result and the input are different vector types, widening 1375 // the result could create a legal type but widening the input might make 1376 // it an illegal type that might lead to repeatedly splitting the input 1377 // and then widening it. To avoid this, we widen the input only if 1378 // it results in a legal type. 1379 SmallVector<SDValue, 16> Ops(NewNumElts); 1380 SDValue UndefVal = DAG.getUNDEF(InVT); 1381 Ops[0] = InOp; 1382 for (unsigned i = 1; i < NewNumElts; ++i) 1383 Ops[i] = UndefVal; 1384 1385 SDValue NewVec; 1386 if (InVT.isVector()) 1387 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1388 NewInVT, &Ops[0], NewNumElts); 1389 else 1390 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, 1391 NewInVT, &Ops[0], NewNumElts); 1392 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, NewVec); 1393 } 1394 } 1395 1396 // This should occur rarely. Lower the bit-convert to a store/load 1397 // from the stack. Create the stack frame object. Make sure it is aligned 1398 // for both the source and destination types. 1399 SDValue FIPtr = DAG.CreateStackTemporary(InVT, WidenVT); 1400 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1401 const Value *SV = PseudoSourceValue::getFixedStack(FI); 1402 1403 // Emit a store to the stack slot. 1404 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0); 1405 1406 // Result is a load from the stack slot. 1407 return DAG.getLoad(WidenVT, dl, Store, FIPtr, SV, 0); 1408} 1409 1410SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) { 1411 DebugLoc dl = N->getDebugLoc(); 1412 // Build a vector with undefined for the new nodes. 1413 MVT VT = N->getValueType(0); 1414 MVT EltVT = VT.getVectorElementType(); 1415 unsigned NumElts = VT.getVectorNumElements(); 1416 1417 MVT WidenVT = TLI.getTypeToTransformTo(VT); 1418 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1419 1420 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end()); 1421 NewOps.reserve(WidenNumElts); 1422 for (unsigned i = NumElts; i < WidenNumElts; ++i) 1423 NewOps.push_back(DAG.getUNDEF(EltVT)); 1424 1425 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size()); 1426} 1427 1428SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) { 1429 MVT InVT = N->getOperand(0).getValueType(); 1430 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1431 DebugLoc dl = N->getDebugLoc(); 1432 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1433 unsigned NumOperands = N->getNumOperands(); 1434 1435 bool InputWidened = false; // Indicates we need to widen the input. 1436 if (getTypeAction(InVT) != WidenVector) { 1437 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) { 1438 // Add undef vectors to widen to correct length. 1439 unsigned NumConcat = WidenVT.getVectorNumElements() / 1440 InVT.getVectorNumElements(); 1441 SDValue UndefVal = DAG.getUNDEF(InVT); 1442 SmallVector<SDValue, 16> Ops(NumConcat); 1443 for (unsigned i=0; i < NumOperands; ++i) 1444 Ops[i] = N->getOperand(i); 1445 for (unsigned i = NumOperands; i != NumConcat; ++i) 1446 Ops[i] = UndefVal; 1447 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat); 1448 } 1449 } else { 1450 InputWidened = true; 1451 if (WidenVT == TLI.getTypeToTransformTo(InVT)) { 1452 // The inputs and the result are widen to the same value. 1453 unsigned i; 1454 for (i=1; i < NumOperands; ++i) 1455 if (N->getOperand(i).getOpcode() != ISD::UNDEF) 1456 break; 1457 1458 if (i > NumOperands) 1459 // Everything but the first operand is an UNDEF so just return the 1460 // widened first operand. 1461 return GetWidenedVector(N->getOperand(0)); 1462 1463 if (NumOperands == 2) { 1464 // Replace concat of two operands with a shuffle. 1465 SmallVector<int, 16> MaskOps(WidenNumElts); 1466 for (unsigned i=0; i < WidenNumElts/2; ++i) { 1467 MaskOps[i] = i; 1468 MaskOps[i+WidenNumElts/2] = i+WidenNumElts; 1469 } 1470 return DAG.getVectorShuffle(WidenVT, dl, 1471 GetWidenedVector(N->getOperand(0)), 1472 GetWidenedVector(N->getOperand(1)), 1473 &MaskOps[0]); 1474 } 1475 } 1476 } 1477 1478 // Fall back to use extracts and build vector. 1479 MVT EltVT = WidenVT.getVectorElementType(); 1480 unsigned NumInElts = InVT.getVectorNumElements(); 1481 SmallVector<SDValue, 16> Ops(WidenNumElts); 1482 unsigned Idx = 0; 1483 for (unsigned i=0; i < NumOperands; ++i) { 1484 SDValue InOp = N->getOperand(i); 1485 if (InputWidened) 1486 InOp = GetWidenedVector(InOp); 1487 for (unsigned j=0; j < NumInElts; ++j) 1488 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1489 DAG.getIntPtrConstant(j)); 1490 } 1491 SDValue UndefVal = DAG.getUNDEF(EltVT); 1492 for (; Idx < WidenNumElts; ++Idx) 1493 Ops[Idx] = UndefVal; 1494 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1495} 1496 1497SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { 1498 DebugLoc dl = N->getDebugLoc(); 1499 SDValue InOp = N->getOperand(0); 1500 SDValue RndOp = N->getOperand(3); 1501 SDValue SatOp = N->getOperand(4); 1502 1503 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1504 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1505 1506 MVT InVT = InOp.getValueType(); 1507 MVT InEltVT = InVT.getVectorElementType(); 1508 MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts); 1509 1510 SDValue DTyOp = DAG.getValueType(WidenVT); 1511 SDValue STyOp = DAG.getValueType(InWidenVT); 1512 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 1513 1514 unsigned InVTNumElts = InVT.getVectorNumElements(); 1515 if (getTypeAction(InVT) == WidenVector) { 1516 InOp = GetWidenedVector(InOp); 1517 InVT = InOp.getValueType(); 1518 InVTNumElts = InVT.getVectorNumElements(); 1519 if (InVTNumElts == WidenNumElts) 1520 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1521 SatOp, CvtCode); 1522 } 1523 1524 if (TLI.isTypeLegal(InWidenVT)) { 1525 // Because the result and the input are different vector types, widening 1526 // the result could create a legal type but widening the input might make 1527 // it an illegal type that might lead to repeatedly splitting the input 1528 // and then widening it. To avoid this, we widen the input only if 1529 // it results in a legal type. 1530 if (WidenNumElts % InVTNumElts == 0) { 1531 // Widen the input and call convert on the widened input vector. 1532 unsigned NumConcat = WidenNumElts/InVTNumElts; 1533 SmallVector<SDValue, 16> Ops(NumConcat); 1534 Ops[0] = InOp; 1535 SDValue UndefVal = DAG.getUNDEF(InVT); 1536 for (unsigned i = 1; i != NumConcat; ++i) { 1537 Ops[i] = UndefVal; 1538 } 1539 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat); 1540 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1541 SatOp, CvtCode); 1542 } 1543 1544 if (InVTNumElts % WidenNumElts == 0) { 1545 // Extract the input and convert the shorten input vector. 1546 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp, 1547 DAG.getIntPtrConstant(0)); 1548 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1549 SatOp, CvtCode); 1550 } 1551 } 1552 1553 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1554 SmallVector<SDValue, 16> Ops(WidenNumElts); 1555 MVT EltVT = WidenVT.getVectorElementType(); 1556 DTyOp = DAG.getValueType(EltVT); 1557 STyOp = DAG.getValueType(InEltVT); 1558 1559 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1560 unsigned i; 1561 for (i=0; i < MinElts; ++i) { 1562 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 1563 DAG.getIntPtrConstant(i)); 1564 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp, 1565 SatOp, CvtCode); 1566 } 1567 1568 SDValue UndefVal = DAG.getUNDEF(EltVT); 1569 for (; i < WidenNumElts; ++i) 1570 Ops[i] = UndefVal; 1571 1572 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1573} 1574 1575SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 1576 MVT VT = N->getValueType(0); 1577 MVT WidenVT = TLI.getTypeToTransformTo(VT); 1578 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1579 SDValue InOp = N->getOperand(0); 1580 SDValue Idx = N->getOperand(1); 1581 DebugLoc dl = N->getDebugLoc(); 1582 1583 if (getTypeAction(InOp.getValueType()) == WidenVector) 1584 InOp = GetWidenedVector(InOp); 1585 1586 MVT InVT = InOp.getValueType(); 1587 1588 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx); 1589 if (CIdx) { 1590 unsigned IdxVal = CIdx->getZExtValue(); 1591 // Check if we can just return the input vector after widening. 1592 if (IdxVal == 0 && InVT == WidenVT) 1593 return InOp; 1594 1595 // Check if we can extract from the vector. 1596 unsigned InNumElts = InVT.getVectorNumElements(); 1597 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts) 1598 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx); 1599 } 1600 1601 // We could try widening the input to the right length but for now, extract 1602 // the original elements, fill the rest with undefs and build a vector. 1603 SmallVector<SDValue, 16> Ops(WidenNumElts); 1604 MVT EltVT = VT.getVectorElementType(); 1605 MVT IdxVT = Idx.getValueType(); 1606 unsigned NumElts = VT.getVectorNumElements(); 1607 unsigned i; 1608 if (CIdx) { 1609 unsigned IdxVal = CIdx->getZExtValue(); 1610 for (i=0; i < NumElts; ++i) 1611 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1612 DAG.getConstant(IdxVal+i, IdxVT)); 1613 } else { 1614 Ops[0] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, Idx); 1615 for (i=1; i < NumElts; ++i) { 1616 SDValue NewIdx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, 1617 DAG.getConstant(i, IdxVT)); 1618 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, NewIdx); 1619 } 1620 } 1621 1622 SDValue UndefVal = DAG.getUNDEF(EltVT); 1623 for (; i < WidenNumElts; ++i) 1624 Ops[i] = UndefVal; 1625 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1626} 1627 1628SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) { 1629 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1630 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(), 1631 InOp.getValueType(), InOp, 1632 N->getOperand(1), N->getOperand(2)); 1633} 1634 1635SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) { 1636 LoadSDNode *LD = cast<LoadSDNode>(N); 1637 MVT WidenVT = TLI.getTypeToTransformTo(LD->getValueType(0)); 1638 MVT LdVT = LD->getMemoryVT(); 1639 DebugLoc dl = N->getDebugLoc(); 1640 assert(LdVT.isVector() && WidenVT.isVector()); 1641 1642 // Load information 1643 SDValue Chain = LD->getChain(); 1644 SDValue BasePtr = LD->getBasePtr(); 1645 int SVOffset = LD->getSrcValueOffset(); 1646 unsigned Align = LD->getAlignment(); 1647 bool isVolatile = LD->isVolatile(); 1648 const Value *SV = LD->getSrcValue(); 1649 ISD::LoadExtType ExtType = LD->getExtensionType(); 1650 1651 SDValue Result; 1652 SmallVector<SDValue, 16> LdChain; // Chain for the series of load 1653 if (ExtType != ISD::NON_EXTLOAD) { 1654 // For extension loads, we can not play the tricks of chopping legal 1655 // vector types and bit cast it to the right type. Instead, we unroll 1656 // the load and build a vector. 1657 MVT EltVT = WidenVT.getVectorElementType(); 1658 MVT LdEltVT = LdVT.getVectorElementType(); 1659 unsigned NumElts = LdVT.getVectorNumElements(); 1660 1661 // Load each element and widen 1662 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1663 SmallVector<SDValue, 16> Ops(WidenNumElts); 1664 unsigned Increment = LdEltVT.getSizeInBits() / 8; 1665 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, SV, SVOffset, 1666 LdEltVT, isVolatile, Align); 1667 LdChain.push_back(Ops[0].getValue(1)); 1668 unsigned i = 0, Offset = Increment; 1669 for (i=1; i < NumElts; ++i, Offset += Increment) { 1670 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 1671 BasePtr, DAG.getIntPtrConstant(Offset)); 1672 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, SV, 1673 SVOffset + Offset, LdEltVT, isVolatile, Align); 1674 LdChain.push_back(Ops[i].getValue(1)); 1675 } 1676 1677 // Fill the rest with undefs 1678 SDValue UndefVal = DAG.getUNDEF(EltVT); 1679 for (; i != WidenNumElts; ++i) 1680 Ops[i] = UndefVal; 1681 1682 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size()); 1683 } else { 1684 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType()); 1685 unsigned int LdWidth = LdVT.getSizeInBits(); 1686 Result = GenWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset, 1687 Align, isVolatile, LdWidth, WidenVT, dl); 1688 } 1689 1690 // If we generate a single load, we can use that for the chain. Otherwise, 1691 // build a factor node to remember the multiple loads are independent and 1692 // chain to that. 1693 SDValue NewChain; 1694 if (LdChain.size() == 1) 1695 NewChain = LdChain[0]; 1696 else 1697 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LdChain[0], 1698 LdChain.size()); 1699 1700 // Modified the chain - switch anything that used the old chain to use 1701 // the new one. 1702 ReplaceValueWith(SDValue(N, 1), Chain); 1703 1704 return Result; 1705} 1706 1707SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) { 1708 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1709 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(), 1710 WidenVT, N->getOperand(0)); 1711} 1712 1713SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) { 1714 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1715 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1716 1717 SDValue Cond1 = N->getOperand(0); 1718 MVT CondVT = Cond1.getValueType(); 1719 if (CondVT.isVector()) { 1720 MVT CondEltVT = CondVT.getVectorElementType(); 1721 MVT CondWidenVT = MVT::getVectorVT(CondEltVT, WidenNumElts); 1722 if (getTypeAction(CondVT) == WidenVector) 1723 Cond1 = GetWidenedVector(Cond1); 1724 1725 if (Cond1.getValueType() != CondWidenVT) 1726 Cond1 = ModifyToType(Cond1, CondWidenVT); 1727 } 1728 1729 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 1730 SDValue InOp2 = GetWidenedVector(N->getOperand(2)); 1731 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT); 1732 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 1733 WidenVT, Cond1, InOp1, InOp2); 1734} 1735 1736SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) { 1737 SDValue InOp1 = GetWidenedVector(N->getOperand(2)); 1738 SDValue InOp2 = GetWidenedVector(N->getOperand(3)); 1739 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 1740 InOp1.getValueType(), N->getOperand(0), 1741 N->getOperand(1), InOp1, InOp2, N->getOperand(4)); 1742} 1743 1744SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) { 1745 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1746 return DAG.getUNDEF(WidenVT); 1747} 1748 1749SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(SDNode *N) { 1750 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 1751 MVT VT = N->getValueType(0); 1752 int NumElts = VT.getVectorNumElements(); 1753 DebugLoc dl = N->getDebugLoc(); 1754 1755 MVT WidenVT = TLI.getTypeToTransformTo(VT); 1756 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1757 1758 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1759 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1760 1761 // Adjust mask based on new input vector length. 1762 SmallVector<int, 16> NewMask; 1763 for (int i = 0; i < NumElts; ++i) { 1764 int Idx = SVN->getMaskElt(i); 1765 if (Idx < NumElts) 1766 NewMask.push_back(Idx); 1767 else 1768 NewMask.push_back(Idx - NumElts + WidenNumElts); 1769 } 1770 for (unsigned i = NumElts; i < WidenNumElts; ++i) 1771 NewMask.push_back(-1); 1772 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]); 1773} 1774 1775SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) { 1776 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1777 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1778 1779 SDValue InOp1 = N->getOperand(0); 1780 MVT InVT = InOp1.getValueType(); 1781 assert(InVT.isVector() && "can not widen non vector type"); 1782 MVT WidenInVT = MVT::getVectorVT(InVT.getVectorElementType(), WidenNumElts); 1783 InOp1 = GetWidenedVector(InOp1); 1784 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1785 1786 // Assume that the input and output will be widen appropriately. If not, 1787 // we will have to unroll it at some point. 1788 assert(InOp1.getValueType() == WidenInVT && 1789 InOp2.getValueType() == WidenInVT && 1790 "Input not widened to expected type!"); 1791 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(), 1792 WidenVT, InOp1, InOp2, N->getOperand(2)); 1793} 1794 1795 1796//===----------------------------------------------------------------------===// 1797// Widen Vector Operand 1798//===----------------------------------------------------------------------===// 1799bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) { 1800 DEBUG(cerr << "Widen node operand " << ResNo << ": "; N->dump(&DAG); 1801 cerr << "\n"); 1802 SDValue Res = SDValue(); 1803 1804 switch (N->getOpcode()) { 1805 default: 1806#ifndef NDEBUG 1807 cerr << "WidenVectorOperand op #" << ResNo << ": "; 1808 N->dump(&DAG); cerr << "\n"; 1809#endif 1810 assert(0 && "Do not know how to widen this operator's operand!"); 1811 abort(); 1812 1813 case ISD::BIT_CONVERT: Res = WidenVecOp_BIT_CONVERT(N); break; 1814 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break; 1815 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break; 1816 case ISD::STORE: Res = WidenVecOp_STORE(N); break; 1817 1818 case ISD::FP_ROUND: 1819 case ISD::FP_TO_SINT: 1820 case ISD::FP_TO_UINT: 1821 case ISD::SINT_TO_FP: 1822 case ISD::TRUNCATE: 1823 case ISD::UINT_TO_FP: Res = WidenVecOp_Convert(N); break; 1824 } 1825 1826 // If Res is null, the sub-method took care of registering the result. 1827 if (!Res.getNode()) return false; 1828 1829 // If the result is N, the sub-method updated N in place. Tell the legalizer 1830 // core about this. 1831 if (Res.getNode() == N) 1832 return true; 1833 1834 1835 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1836 "Invalid operand expansion"); 1837 1838 ReplaceValueWith(SDValue(N, 0), Res); 1839 return false; 1840} 1841 1842SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) { 1843 // Since the result is legal and the input is illegal, it is unlikely 1844 // that we can fix the input to a legal type so unroll the convert 1845 // into some scalar code and create a nasty build vector. 1846 MVT VT = N->getValueType(0); 1847 MVT EltVT = VT.getVectorElementType(); 1848 DebugLoc dl = N->getDebugLoc(); 1849 unsigned NumElts = VT.getVectorNumElements(); 1850 SDValue InOp = N->getOperand(0); 1851 if (getTypeAction(InOp.getValueType()) == WidenVector) 1852 InOp = GetWidenedVector(InOp); 1853 MVT InVT = InOp.getValueType(); 1854 MVT InEltVT = InVT.getVectorElementType(); 1855 1856 unsigned Opcode = N->getOpcode(); 1857 SmallVector<SDValue, 16> Ops(NumElts); 1858 for (unsigned i=0; i < NumElts; ++i) 1859 Ops[i] = DAG.getNode(Opcode, dl, EltVT, 1860 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 1861 DAG.getIntPtrConstant(i))); 1862 1863 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 1864} 1865 1866SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) { 1867 MVT VT = N->getValueType(0); 1868 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1869 MVT InWidenVT = InOp.getValueType(); 1870 DebugLoc dl = N->getDebugLoc(); 1871 1872 // Check if we can convert between two legal vector types and extract. 1873 unsigned InWidenSize = InWidenVT.getSizeInBits(); 1874 unsigned Size = VT.getSizeInBits(); 1875 if (InWidenSize % Size == 0 && !VT.isVector()) { 1876 unsigned NewNumElts = InWidenSize / Size; 1877 MVT NewVT = MVT::getVectorVT(VT, NewNumElts); 1878 if (TLI.isTypeLegal(NewVT)) { 1879 SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp); 1880 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, 1881 DAG.getIntPtrConstant(0)); 1882 } 1883 } 1884 1885 // Lower the bit-convert to a store/load from the stack. Create the stack 1886 // frame object. Make sure it is aligned for both the source and destination 1887 // types. 1888 SDValue FIPtr = DAG.CreateStackTemporary(InWidenVT, VT); 1889 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1890 const Value *SV = PseudoSourceValue::getFixedStack(FI); 1891 1892 // Emit a store to the stack slot. 1893 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0); 1894 1895 // Result is a load from the stack slot. 1896 return DAG.getLoad(VT, dl, Store, FIPtr, SV, 0); 1897} 1898 1899SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) { 1900 // If the input vector is not legal, it is likely that we will not find a 1901 // legal vector of the same size. Replace the concatenate vector with a 1902 // nasty build vector. 1903 MVT VT = N->getValueType(0); 1904 MVT EltVT = VT.getVectorElementType(); 1905 DebugLoc dl = N->getDebugLoc(); 1906 unsigned NumElts = VT.getVectorNumElements(); 1907 SmallVector<SDValue, 16> Ops(NumElts); 1908 1909 MVT InVT = N->getOperand(0).getValueType(); 1910 unsigned NumInElts = InVT.getVectorNumElements(); 1911 1912 unsigned Idx = 0; 1913 unsigned NumOperands = N->getNumOperands(); 1914 for (unsigned i=0; i < NumOperands; ++i) { 1915 SDValue InOp = N->getOperand(i); 1916 if (getTypeAction(InOp.getValueType()) == WidenVector) 1917 InOp = GetWidenedVector(InOp); 1918 for (unsigned j=0; j < NumInElts; ++j) 1919 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1920 DAG.getIntPtrConstant(j)); 1921 } 1922 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 1923} 1924 1925SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 1926 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1927 MVT EltVT = InOp.getValueType().getVectorElementType(); 1928 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 1929 EltVT, InOp, N->getOperand(1)); 1930} 1931 1932SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) { 1933 // We have to widen the value but we want only to store the original 1934 // vector type. 1935 StoreSDNode *ST = cast<StoreSDNode>(N); 1936 SDValue Chain = ST->getChain(); 1937 SDValue BasePtr = ST->getBasePtr(); 1938 const Value *SV = ST->getSrcValue(); 1939 int SVOffset = ST->getSrcValueOffset(); 1940 unsigned Align = ST->getAlignment(); 1941 bool isVolatile = ST->isVolatile(); 1942 SDValue ValOp = GetWidenedVector(ST->getValue()); 1943 DebugLoc dl = N->getDebugLoc(); 1944 1945 MVT StVT = ST->getMemoryVT(); 1946 MVT ValVT = ValOp.getValueType(); 1947 // It must be true that we the widen vector type is bigger than where 1948 // we need to store. 1949 assert(StVT.isVector() && ValOp.getValueType().isVector()); 1950 assert(StVT.bitsLT(ValOp.getValueType())); 1951 1952 SmallVector<SDValue, 16> StChain; 1953 if (ST->isTruncatingStore()) { 1954 // For truncating stores, we can not play the tricks of chopping legal 1955 // vector types and bit cast it to the right type. Instead, we unroll 1956 // the store. 1957 MVT StEltVT = StVT.getVectorElementType(); 1958 MVT ValEltVT = ValVT.getVectorElementType(); 1959 unsigned Increment = ValEltVT.getSizeInBits() / 8; 1960 unsigned NumElts = StVT.getVectorNumElements(); 1961 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 1962 DAG.getIntPtrConstant(0)); 1963 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, SV, 1964 SVOffset, StEltVT, 1965 isVolatile, Align)); 1966 unsigned Offset = Increment; 1967 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) { 1968 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 1969 BasePtr, DAG.getIntPtrConstant(Offset)); 1970 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 1971 DAG.getIntPtrConstant(0)); 1972 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, SV, 1973 SVOffset + Offset, StEltVT, 1974 isVolatile, MinAlign(Align, Offset))); 1975 } 1976 } 1977 else { 1978 assert(StVT.getVectorElementType() == ValVT.getVectorElementType()); 1979 // Store value 1980 GenWidenVectorStores(StChain, Chain, BasePtr, SV, SVOffset, 1981 Align, isVolatile, ValOp, StVT.getSizeInBits(), dl); 1982 } 1983 if (StChain.size() == 1) 1984 return StChain[0]; 1985 else 1986 return DAG.getNode(ISD::TokenFactor, dl, 1987 MVT::Other,&StChain[0],StChain.size()); 1988} 1989 1990//===----------------------------------------------------------------------===// 1991// Vector Widening Utilities 1992//===----------------------------------------------------------------------===// 1993 1994 1995// Utility function to find a vector type and its associated element 1996// type from a preferred width and whose vector type must be the same size 1997// as the VecVT. 1998// TLI: Target lowering used to determine legal types. 1999// Width: Preferred width to store. 2000// VecVT: Vector value type whose size we must match. 2001// Returns NewVecVT and NewEltVT - the vector type and its associated 2002// element type. 2003static void FindAssocWidenVecType(const TargetLowering &TLI, unsigned Width, 2004 MVT VecVT, 2005 MVT& NewEltVT, MVT& NewVecVT) { 2006 unsigned EltWidth = Width + 1; 2007 if (TLI.isTypeLegal(VecVT)) { 2008 // We start with the preferred with, making it a power of 2 and find a 2009 // legal vector type of that width. If not, we reduce it by another of 2. 2010 // For incoming type is legal, this process will end as a vector of the 2011 // smallest loadable type should always be legal. 2012 do { 2013 assert(EltWidth > 0); 2014 EltWidth = 1 << Log2_32(EltWidth - 1); 2015 NewEltVT = MVT::getIntegerVT(EltWidth); 2016 unsigned NumElts = VecVT.getSizeInBits() / EltWidth; 2017 NewVecVT = MVT::getVectorVT(NewEltVT, NumElts); 2018 } while (!TLI.isTypeLegal(NewVecVT) || 2019 VecVT.getSizeInBits() != NewVecVT.getSizeInBits()); 2020 } else { 2021 // The incoming vector type is illegal and is the result of widening 2022 // a vector to a power of 2. In this case, we will use the preferred 2023 // with as long as it is a multiple of the incoming vector length. 2024 // The legalization process will eventually make this into a legal type 2025 // and remove the illegal bit converts (which would turn to stack converts 2026 // if they are allow to exist). 2027 do { 2028 assert(EltWidth > 0); 2029 EltWidth = 1 << Log2_32(EltWidth - 1); 2030 NewEltVT = MVT::getIntegerVT(EltWidth); 2031 unsigned NumElts = VecVT.getSizeInBits() / EltWidth; 2032 NewVecVT = MVT::getVectorVT(NewEltVT, NumElts); 2033 } while (!TLI.isTypeLegal(NewEltVT) || 2034 VecVT.getSizeInBits() != NewVecVT.getSizeInBits()); 2035 } 2036} 2037 2038SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain, 2039 SDValue Chain, 2040 SDValue BasePtr, 2041 const Value *SV, 2042 int SVOffset, 2043 unsigned Alignment, 2044 bool isVolatile, 2045 unsigned LdWidth, 2046 MVT ResType, 2047 DebugLoc dl) { 2048 // The strategy assumes that we can efficiently load powers of two widths. 2049 // The routines chops the vector into the largest power of 2 load and 2050 // can be inserted into a legal vector and then cast the result into the 2051 // vector type we want. This avoids unnecessary stack converts. 2052 2053 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and 2054 // the load is nonvolatile, we an use a wider load for the value. 2055 2056 // Find the vector type that can load from. 2057 MVT NewEltVT, NewVecVT; 2058 unsigned NewEltVTWidth; 2059 FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT); 2060 NewEltVTWidth = NewEltVT.getSizeInBits(); 2061 2062 SDValue LdOp = DAG.getLoad(NewEltVT, dl, Chain, BasePtr, SV, SVOffset, 2063 isVolatile, Alignment); 2064 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp); 2065 LdChain.push_back(LdOp.getValue(1)); 2066 2067 // Check if we can load the element with one instruction 2068 if (LdWidth == NewEltVTWidth) { 2069 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp); 2070 } 2071 2072 unsigned Idx = 1; 2073 LdWidth -= NewEltVTWidth; 2074 unsigned Offset = 0; 2075 2076 while (LdWidth > 0) { 2077 unsigned Increment = NewEltVTWidth / 8; 2078 Offset += Increment; 2079 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2080 DAG.getIntPtrConstant(Increment)); 2081 2082 if (LdWidth < NewEltVTWidth) { 2083 // Our current type we are using is too large, use a smaller size by 2084 // using a smaller power of 2 2085 unsigned oNewEltVTWidth = NewEltVTWidth; 2086 FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT); 2087 NewEltVTWidth = NewEltVT.getSizeInBits(); 2088 // Readjust position and vector position based on new load type 2089 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth); 2090 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp); 2091 } 2092 2093 SDValue LdOp = DAG.getLoad(NewEltVT, dl, Chain, BasePtr, SV, 2094 SVOffset+Offset, isVolatile, 2095 MinAlign(Alignment, Offset)); 2096 LdChain.push_back(LdOp.getValue(1)); 2097 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOp, 2098 DAG.getIntPtrConstant(Idx++)); 2099 2100 LdWidth -= NewEltVTWidth; 2101 } 2102 2103 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp); 2104} 2105 2106void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, 2107 SDValue Chain, 2108 SDValue BasePtr, 2109 const Value *SV, 2110 int SVOffset, 2111 unsigned Alignment, 2112 bool isVolatile, 2113 SDValue ValOp, 2114 unsigned StWidth, 2115 DebugLoc dl) { 2116 // Breaks the stores into a series of power of 2 width stores. For any 2117 // width, we convert the vector to the vector of element size that we 2118 // want to store. This avoids requiring a stack convert. 2119 2120 // Find a width of the element type we can store with 2121 MVT WidenVT = ValOp.getValueType(); 2122 MVT NewEltVT, NewVecVT; 2123 2124 FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT); 2125 unsigned NewEltVTWidth = NewEltVT.getSizeInBits(); 2126 2127 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, ValOp); 2128 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, VecOp, 2129 DAG.getIntPtrConstant(0)); 2130 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset, 2131 isVolatile, Alignment); 2132 StChain.push_back(StOp); 2133 2134 // Check if we are done 2135 if (StWidth == NewEltVTWidth) { 2136 return; 2137 } 2138 2139 unsigned Idx = 1; 2140 StWidth -= NewEltVTWidth; 2141 unsigned Offset = 0; 2142 2143 while (StWidth > 0) { 2144 unsigned Increment = NewEltVTWidth / 8; 2145 Offset += Increment; 2146 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2147 DAG.getIntPtrConstant(Increment)); 2148 2149 if (StWidth < NewEltVTWidth) { 2150 // Our current type we are using is too large, use a smaller size by 2151 // using a smaller power of 2 2152 unsigned oNewEltVTWidth = NewEltVTWidth; 2153 FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT); 2154 NewEltVTWidth = NewEltVT.getSizeInBits(); 2155 // Readjust position and vector position based on new load type 2156 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth); 2157 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp); 2158 } 2159 2160 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, VecOp, 2161 DAG.getIntPtrConstant(Idx++)); 2162 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV, 2163 SVOffset + Offset, isVolatile, 2164 MinAlign(Alignment, Offset))); 2165 StWidth -= NewEltVTWidth; 2166 } 2167} 2168 2169/// Modifies a vector input (widen or narrows) to a vector of NVT. The 2170/// input vector must have the same element type as NVT. 2171SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, MVT NVT) { 2172 // Note that InOp might have been widened so it might already have 2173 // the right width or it might need be narrowed. 2174 MVT InVT = InOp.getValueType(); 2175 assert(InVT.getVectorElementType() == NVT.getVectorElementType() && 2176 "input and widen element type must match"); 2177 DebugLoc dl = InOp.getDebugLoc(); 2178 2179 // Check if InOp already has the right width. 2180 if (InVT == NVT) 2181 return InOp; 2182 2183 unsigned InNumElts = InVT.getVectorNumElements(); 2184 unsigned WidenNumElts = NVT.getVectorNumElements(); 2185 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) { 2186 unsigned NumConcat = WidenNumElts / InNumElts; 2187 SmallVector<SDValue, 16> Ops(NumConcat); 2188 SDValue UndefVal = DAG.getUNDEF(InVT); 2189 Ops[0] = InOp; 2190 for (unsigned i = 1; i != NumConcat; ++i) 2191 Ops[i] = UndefVal; 2192 2193 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat); 2194 } 2195 2196 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts) 2197 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp, 2198 DAG.getIntPtrConstant(0)); 2199 2200 // Fall back to extract and build. 2201 SmallVector<SDValue, 16> Ops(WidenNumElts); 2202 MVT EltVT = NVT.getVectorElementType(); 2203 unsigned MinNumElts = std::min(WidenNumElts, InNumElts); 2204 unsigned Idx; 2205 for (Idx = 0; Idx < MinNumElts; ++Idx) 2206 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2207 DAG.getIntPtrConstant(Idx)); 2208 2209 SDValue UndefVal = DAG.getUNDEF(EltVT); 2210 for ( ; Idx < WidenNumElts; ++Idx) 2211 Ops[Idx] = UndefVal; 2212 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts); 2213} 2214