LegalizeVectorTypes.cpp revision 953a83d09f658d621cd27ce874567f221b88e8db
1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file performs vector type splitting and scalarization for LegalizeTypes. 11// Scalarization is the act of changing a computation in an illegal one-element 12// vector type to be a computation in its scalar element type. For example, 13// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed 14// as a base case when scalarizing vector arithmetic like <4 x f32>, which 15// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32 16// types. 17// Splitting is the act of changing a computation in an invalid vector type to 18// be a computation in multiple vectors of a smaller type. For example, 19// implementing <128 x f32> operations in terms of two <64 x f32> operations. 20// 21//===----------------------------------------------------------------------===// 22 23#include "LegalizeTypes.h" 24using namespace llvm; 25 26//===----------------------------------------------------------------------===// 27// Result Vector Scalarization: <1 x ty> -> ty. 28//===----------------------------------------------------------------------===// 29 30void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { 31 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG); 32 cerr << "\n"); 33 SDOperand R = SDOperand(); 34 35 switch (N->getOpcode()) { 36 default: 37#ifndef NDEBUG 38 cerr << "ScalarizeVectorResult #" << ResNo << ": "; 39 N->dump(&DAG); cerr << "\n"; 40#endif 41 assert(0 && "Do not know how to scalarize the result of this operator!"); 42 abort(); 43 44 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; 45 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N)); break; 46 47 case ISD::ADD: 48 case ISD::FADD: 49 case ISD::SUB: 50 case ISD::FSUB: 51 case ISD::MUL: 52 case ISD::FMUL: 53 case ISD::SDIV: 54 case ISD::UDIV: 55 case ISD::FDIV: 56 case ISD::SREM: 57 case ISD::UREM: 58 case ISD::FREM: 59 case ISD::FPOW: 60 case ISD::AND: 61 case ISD::OR: 62 case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break; 63 64 case ISD::FNEG: 65 case ISD::FABS: 66 case ISD::FSQRT: 67 case ISD::FSIN: 68 case ISD::FCOS: R = ScalarizeVecRes_UnaryOp(N); break; 69 70 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 71 case ISD::BUILD_VECTOR: R = N->getOperand(0); break; 72 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 73 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; 74 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break; 75 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break; 76 } 77 78 // If R is null, the sub-method took care of registering the result. 79 if (R.Val) 80 SetScalarizedVector(SDOperand(N, ResNo), R); 81} 82 83SDOperand DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { 84 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType()); 85} 86 87SDOperand DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { 88 assert(ISD::isNormalLoad(N) && "Extending load of one-element vector?"); 89 SDOperand Result = DAG.getLoad(N->getValueType(0).getVectorElementType(), 90 N->getChain(), N->getBasePtr(), 91 N->getSrcValue(), N->getSrcValueOffset(), 92 N->isVolatile(), N->getAlignment()); 93 94 // Legalized the chain result - switch anything that used the old chain to 95 // use the new one. 96 ReplaceValueWith(SDOperand(N, 1), Result.getValue(1)); 97 return Result; 98} 99 100SDOperand DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { 101 SDOperand LHS = GetScalarizedVector(N->getOperand(0)); 102 SDOperand RHS = GetScalarizedVector(N->getOperand(1)); 103 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 104} 105 106SDOperand DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { 107 SDOperand Op = GetScalarizedVector(N->getOperand(0)); 108 return DAG.getNode(N->getOpcode(), Op.getValueType(), Op); 109} 110 111SDOperand DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) { 112 SDOperand Op = GetScalarizedVector(N->getOperand(0)); 113 return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1)); 114} 115 116SDOperand DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { 117 // The value to insert may have a wider type than the vector element type, 118 // so be sure to truncate it to the element type if necessary. 119 SDOperand Op = N->getOperand(1); 120 MVT EltVT = N->getValueType(0).getVectorElementType(); 121 if (Op.getValueType() != EltVT) 122 // FIXME: Can this happen for floating point types? 123 Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op); 124 return Op; 125} 126 127SDOperand DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { 128 // Figure out if the scalar is the LHS or RHS and return it. 129 SDOperand EltNum = N->getOperand(2).getOperand(0); 130 unsigned Op = cast<ConstantSDNode>(EltNum)->getValue() != 0; 131 return GetScalarizedVector(N->getOperand(Op)); 132} 133 134SDOperand DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) { 135 MVT NewVT = N->getValueType(0).getVectorElementType(); 136 return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0)); 137} 138 139SDOperand DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) { 140 SDOperand LHS = GetScalarizedVector(N->getOperand(1)); 141 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS, 142 GetScalarizedVector(N->getOperand(2))); 143} 144 145 146//===----------------------------------------------------------------------===// 147// Operand Vector Scalarization <1 x ty> -> ty. 148//===----------------------------------------------------------------------===// 149 150bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { 151 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG); 152 cerr << "\n"); 153 SDOperand Res = SDOperand(); 154 155 if (Res.Val == 0) { 156 switch (N->getOpcode()) { 157 default: 158#ifndef NDEBUG 159 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": "; 160 N->dump(&DAG); cerr << "\n"; 161#endif 162 assert(0 && "Do not know how to scalarize this operator's operand!"); 163 abort(); 164 165 case ISD::BIT_CONVERT: 166 Res = ScalarizeVecOp_BIT_CONVERT(N); break; 167 168 case ISD::EXTRACT_VECTOR_ELT: 169 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break; 170 171 case ISD::STORE: 172 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break; 173 } 174 } 175 176 // If the result is null, the sub-method took care of registering results etc. 177 if (!Res.Val) return false; 178 179 // If the result is N, the sub-method updated N in place. Check to see if any 180 // operands are new, and if so, mark them. 181 if (Res.Val == N) { 182 // Mark N as new and remark N and its operands. This allows us to correctly 183 // revisit N if it needs another step of promotion and allows us to visit 184 // any new operands to N. 185 ReanalyzeNode(N); 186 return true; 187 } 188 189 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 190 "Invalid operand expansion"); 191 192 ReplaceValueWith(SDOperand(N, 0), Res); 193 return false; 194} 195 196/// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs 197/// to be scalarized, it must be <1 x ty>. Convert the element instead. 198SDOperand DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) { 199 SDOperand Elt = GetScalarizedVector(N->getOperand(0)); 200 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt); 201} 202 203/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to 204/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the 205/// index. 206SDOperand DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 207 return GetScalarizedVector(N->getOperand(0)); 208} 209 210/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be 211/// scalarized, it must be <1 x ty>. Just store the element. 212SDOperand DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ 213 assert(ISD::isNormalStore(N) && "Truncating store of one-element vector?"); 214 assert(OpNo == 1 && "Do not know how to scalarize this operand!"); 215 return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)), 216 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(), 217 N->isVolatile(), N->getAlignment()); 218} 219 220 221//===----------------------------------------------------------------------===// 222// Result Vector Splitting 223//===----------------------------------------------------------------------===// 224 225/// SplitVectorResult - This method is called when the specified result of the 226/// specified node is found to need vector splitting. At this point, the node 227/// may also have invalid operands or may have other results that need 228/// legalization, we just know that (at least) one result needs vector 229/// splitting. 230void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { 231 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n"); 232 SDOperand Lo, Hi; 233 234 switch (N->getOpcode()) { 235 default: 236#ifndef NDEBUG 237 cerr << "SplitVectorResult #" << ResNo << ": "; 238 N->dump(&DAG); cerr << "\n"; 239#endif 240 assert(0 && "Do not know how to split the result of this operator!"); 241 abort(); 242 243 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 244 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 245 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 246 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 247 248 case ISD::LOAD: 249 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); 250 break; 251 case ISD::BUILD_PAIR: SplitVecRes_BUILD_PAIR(N, Lo, Hi); break; 252 case ISD::INSERT_VECTOR_ELT:SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 253 case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break; 254 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 255 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 256 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break; 257 case ISD::CTTZ: 258 case ISD::CTLZ: 259 case ISD::CTPOP: 260 case ISD::FNEG: 261 case ISD::FABS: 262 case ISD::FSQRT: 263 case ISD::FSIN: 264 case ISD::FCOS: 265 case ISD::FP_TO_SINT: 266 case ISD::FP_TO_UINT: 267 case ISD::SINT_TO_FP: 268 case ISD::UINT_TO_FP: SplitVecRes_UnOp(N, Lo, Hi); break; 269 case ISD::ADD: 270 case ISD::SUB: 271 case ISD::MUL: 272 case ISD::FADD: 273 case ISD::FSUB: 274 case ISD::FMUL: 275 case ISD::SDIV: 276 case ISD::UDIV: 277 case ISD::FDIV: 278 case ISD::FPOW: 279 case ISD::AND: 280 case ISD::OR: 281 case ISD::XOR: 282 case ISD::UREM: 283 case ISD::SREM: 284 case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break; 285 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; 286 } 287 288 // If Lo/Hi is null, the sub-method took care of registering results etc. 289 if (Lo.Val) 290 SetSplitVector(SDOperand(N, ResNo), Lo, Hi); 291} 292 293void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDOperand &Lo, 294 SDOperand &Hi) { 295 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"); 296 MVT LoVT, HiVT; 297 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); 298 299 SDOperand Ch = LD->getChain(); 300 SDOperand Ptr = LD->getBasePtr(); 301 const Value *SV = LD->getSrcValue(); 302 int SVOffset = LD->getSrcValueOffset(); 303 unsigned Alignment = LD->getAlignment(); 304 bool isVolatile = LD->isVolatile(); 305 306 Lo = DAG.getLoad(LoVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 307 308 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 309 unsigned IncrementSize = LoVT.getSizeInBits()/8; 310 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 311 DAG.getIntPtrConstant(IncrementSize)); 312 SVOffset += IncrementSize; 313 Alignment = MinAlign(Alignment, IncrementSize); 314 Hi = DAG.getLoad(HiVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 315 316 // Build a factor node to remember that this load is independent of the 317 // other one. 318 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 319 Hi.getValue(1)); 320 } else { 321 assert(LD->getExtensionType() == ISD::EXTLOAD && 322 "Unsupported vector extending load!"); 323 Hi = DAG.getNode(ISD::UNDEF, HiVT); 324 Ch = Lo.getValue(1); 325 } 326 327 // Legalized the chain result - switch anything that used the old chain to 328 // use the new one. 329 ReplaceValueWith(SDOperand(LD, 1), Ch); 330} 331 332void DAGTypeLegalizer::SplitVecRes_BUILD_PAIR(SDNode *N, SDOperand &Lo, 333 SDOperand &Hi) { 334#ifndef NDEBUG 335 MVT LoVT, HiVT; 336 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 337 assert(LoVT == HiVT && "Non-power-of-two vectors not supported!"); 338#endif 339 Lo = N->getOperand(0); 340 Hi = N->getOperand(1); 341} 342 343void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo, 344 SDOperand &Hi) { 345 SDOperand Vec = N->getOperand(0); 346 SDOperand Elt = N->getOperand(1); 347 SDOperand Idx = N->getOperand(2); 348 GetSplitVector(Vec, Lo, Hi); 349 350 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 351 unsigned IdxVal = CIdx->getValue(); 352 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 353 if (IdxVal < LoNumElts) 354 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx); 355 else 356 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, Elt, 357 DAG.getIntPtrConstant(IdxVal - LoNumElts)); 358 return; 359 } 360 361 // Spill the vector to the stack. 362 MVT VecVT = Vec.getValueType(); 363 SDOperand StackPtr = DAG.CreateStackTemporary(VecVT); 364 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 365 366 // Store the new element. 367 SDOperand EltPtr = GetVectorElementPointer(StackPtr, 368 VecVT.getVectorElementType(), Idx); 369 Store = DAG.getStore(Store, Elt, EltPtr, NULL, 0); 370 371 // Reload the vector from the stack. 372 SDOperand Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0); 373 374 // Split it. 375 SplitVecRes_LOAD(cast<LoadSDNode>(Load.Val), Lo, Hi); 376} 377 378void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo, 379 SDOperand &Hi) { 380 // Build the low part. 381 SDOperand Mask = N->getOperand(2); 382 SmallVector<SDOperand, 16> Ops; 383 MVT LoVT, HiVT; 384 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 385 MVT EltVT = LoVT.getVectorElementType(); 386 unsigned LoNumElts = LoVT.getVectorNumElements(); 387 unsigned NumElements = Mask.getNumOperands(); 388 389 // Insert all of the elements from the input that are needed. We use 390 // buildvector of extractelement here because the input vectors will have 391 // to be legalized, so this makes the code simpler. 392 for (unsigned i = 0; i != LoNumElts; ++i) { 393 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 394 SDOperand InVec = N->getOperand(0); 395 if (Idx >= NumElements) { 396 InVec = N->getOperand(1); 397 Idx -= NumElements; 398 } 399 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec, 400 DAG.getIntPtrConstant(Idx))); 401 } 402 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &Ops[0], Ops.size()); 403 Ops.clear(); 404 405 for (unsigned i = LoNumElts; i != NumElements; ++i) { 406 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 407 SDOperand InVec = N->getOperand(0); 408 if (Idx >= NumElements) { 409 InVec = N->getOperand(1); 410 Idx -= NumElements; 411 } 412 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec, 413 DAG.getIntPtrConstant(Idx))); 414 } 415 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size()); 416} 417 418void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo, 419 SDOperand &Hi) { 420 MVT LoVT, HiVT; 421 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 422 unsigned LoNumElts = LoVT.getVectorNumElements(); 423 SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts); 424 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size()); 425 426 SmallVector<SDOperand, 8> HiOps(N->op_begin()+LoNumElts, N->op_end()); 427 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size()); 428} 429 430void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDOperand &Lo, 431 SDOperand &Hi) { 432 // FIXME: Handle non-power-of-two vectors? 433 unsigned NumSubvectors = N->getNumOperands() / 2; 434 if (NumSubvectors == 1) { 435 Lo = N->getOperand(0); 436 Hi = N->getOperand(1); 437 return; 438 } 439 440 MVT LoVT, HiVT; 441 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 442 443 SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); 444 Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size()); 445 446 SmallVector<SDOperand, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end()); 447 Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size()); 448} 449 450void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDOperand &Lo, 451 SDOperand &Hi) { 452 // We know the result is a vector. The input may be either a vector or a 453 // scalar value. 454 MVT LoVT, HiVT; 455 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 456 457 SDOperand InOp = N->getOperand(0); 458 MVT InVT = InOp.getValueType(); 459 460 // Handle some special cases efficiently. 461 switch (getTypeAction(InVT)) { 462 default: 463 assert(false && "Unknown type action!"); 464 case Legal: 465 case PromoteInteger: 466 case SoftenFloat: 467 case ScalarizeVector: 468 break; 469 case ExpandInteger: 470 case ExpandFloat: 471 // A scalar to vector conversion, where the scalar needs expansion. 472 // If the vector is being split in two then we can just convert the 473 // expanded pieces. 474 if (LoVT == HiVT) { 475 GetExpandedOp(InOp, Lo, Hi); 476 if (TLI.isBigEndian()) 477 std::swap(Lo, Hi); 478 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo); 479 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi); 480 return; 481 } 482 break; 483 case SplitVector: 484 // If the input is a vector that needs to be split, convert each split 485 // piece of the input now. 486 GetSplitVector(InOp, Lo, Hi); 487 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo); 488 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi); 489 return; 490 } 491 492 // In the general case, convert the input to an integer and split it by hand. 493 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits()); 494 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits()); 495 if (TLI.isBigEndian()) 496 std::swap(LoIntVT, HiIntVT); 497 498 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); 499 500 if (TLI.isBigEndian()) 501 std::swap(Lo, Hi); 502 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo); 503 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi); 504} 505 506void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDOperand &Lo, 507 SDOperand &Hi) { 508 SDOperand LHSLo, LHSHi; 509 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 510 SDOperand RHSLo, RHSHi; 511 GetSplitVector(N->getOperand(1), RHSLo, RHSHi); 512 513 Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo); 514 Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi); 515} 516 517void DAGTypeLegalizer::SplitVecRes_UnOp(SDNode *N, SDOperand &Lo, 518 SDOperand &Hi) { 519 // Get the dest types. This doesn't always match input types, e.g. int_to_fp. 520 MVT LoVT, HiVT; 521 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 522 523 GetSplitVector(N->getOperand(0), Lo, Hi); 524 Lo = DAG.getNode(N->getOpcode(), LoVT, Lo); 525 Hi = DAG.getNode(N->getOpcode(), HiVT, Hi); 526} 527 528void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDOperand &Lo, 529 SDOperand &Hi) { 530 GetSplitVector(N->getOperand(0), Lo, Hi); 531 Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1)); 532 Hi = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Hi, N->getOperand(1)); 533} 534 535 536//===----------------------------------------------------------------------===// 537// Operand Vector Splitting 538//===----------------------------------------------------------------------===// 539 540/// SplitVectorOperand - This method is called when the specified operand of the 541/// specified node is found to need vector splitting. At this point, all of the 542/// result types of the node are known to be legal, but other operands of the 543/// node may need legalization as well as the specified one. 544bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { 545 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n"); 546 SDOperand Res = SDOperand(); 547 548 if (Res.Val == 0) { 549 switch (N->getOpcode()) { 550 default: 551#ifndef NDEBUG 552 cerr << "SplitVectorOperand Op #" << OpNo << ": "; 553 N->dump(&DAG); cerr << "\n"; 554#endif 555 assert(0 && "Do not know how to split this operator's operand!"); 556 abort(); 557 case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo); break; 558 559 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break; 560 561 case ISD::EXTRACT_VECTOR_ELT: Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; 562 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; 563 case ISD::VECTOR_SHUFFLE: 564 Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo); 565 break; 566 } 567 } 568 569 // If the result is null, the sub-method took care of registering results etc. 570 if (!Res.Val) return false; 571 572 // If the result is N, the sub-method updated N in place. Check to see if any 573 // operands are new, and if so, mark them. 574 if (Res.Val == N) { 575 // Mark N as new and remark N and its operands. This allows us to correctly 576 // revisit N if it needs another step of promotion and allows us to visit 577 // any new operands to N. 578 ReanalyzeNode(N); 579 return true; 580 } 581 582 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 583 "Invalid operand expansion"); 584 585 ReplaceValueWith(SDOperand(N, 0), Res); 586 return false; 587} 588 589SDOperand DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { 590 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 591 assert(OpNo == 1 && "Can only split the stored value"); 592 593 SDOperand Ch = N->getChain(); 594 SDOperand Ptr = N->getBasePtr(); 595 int SVOffset = N->getSrcValueOffset(); 596 unsigned Alignment = N->getAlignment(); 597 bool isVol = N->isVolatile(); 598 SDOperand Lo, Hi; 599 GetSplitVector(N->getOperand(1), Lo, Hi); 600 601 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; 602 603 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, isVol, Alignment); 604 605 // Increment the pointer to the other half. 606 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 607 DAG.getIntPtrConstant(IncrementSize)); 608 609 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize, 610 isVol, MinAlign(Alignment, IncrementSize)); 611 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 612} 613 614SDOperand DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) { 615 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will 616 // end up being split all the way down to individual components. Convert the 617 // split pieces into integers and reassemble. 618 SDOperand Lo, Hi; 619 GetSplitVector(N->getOperand(0), Lo, Hi); 620 Lo = BitConvertToInteger(Lo); 621 Hi = BitConvertToInteger(Hi); 622 623 if (TLI.isBigEndian()) 624 std::swap(Lo, Hi); 625 626 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), 627 JoinIntegers(Lo, Hi)); 628} 629 630SDOperand DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 631 SDOperand Vec = N->getOperand(0); 632 SDOperand Idx = N->getOperand(1); 633 MVT VecVT = Vec.getValueType(); 634 635 if (isa<ConstantSDNode>(Idx)) { 636 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue(); 637 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); 638 639 SDOperand Lo, Hi; 640 GetSplitVector(Vec, Lo, Hi); 641 642 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 643 644 if (IdxVal < LoElts) 645 return DAG.UpdateNodeOperands(SDOperand(N, 0), Lo, Idx); 646 else 647 return DAG.UpdateNodeOperands(SDOperand(N, 0), Hi, 648 DAG.getConstant(IdxVal - LoElts, 649 Idx.getValueType())); 650 } 651 652 // Store the vector to the stack. 653 MVT EltVT = VecVT.getVectorElementType(); 654 SDOperand StackPtr = DAG.CreateStackTemporary(VecVT); 655 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 656 657 // Load back the required element. 658 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 659 return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0); 660} 661 662SDOperand DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 663 // We know that the extracted result type is legal. For now, assume the index 664 // is a constant. 665 MVT SubVT = N->getValueType(0); 666 SDOperand Idx = N->getOperand(1); 667 SDOperand Lo, Hi; 668 GetSplitVector(N->getOperand(0), Lo, Hi); 669 670 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 671 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue(); 672 673 if (IdxVal < LoElts) { 674 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && 675 "Extracted subvector crosses vector split!"); 676 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx); 677 } else { 678 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi, 679 DAG.getConstant(IdxVal - LoElts, Idx.getValueType())); 680 } 681} 682 683SDOperand DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo){ 684 assert(OpNo == 2 && "Shuffle source type differs from result type?"); 685 SDOperand Mask = N->getOperand(2); 686 unsigned MaskLength = Mask.getValueType().getVectorNumElements(); 687 unsigned LargestMaskEntryPlusOne = 2 * MaskLength; 688 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne); 689 690 // Look for a legal vector type to place the mask values in. 691 // Note that there may not be *any* legal vector-of-integer 692 // type for which the element type is legal! 693 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE; 694 EltVT <= MVT::LAST_INTEGER_VALUETYPE; 695 // Integer values types are consecutively numbered. Exploit this. 696 EltVT = MVT::SimpleValueType(EltVT + 1)) { 697 698 // Is the element type big enough to hold the values? 699 if (MVT(EltVT).getSizeInBits() < MinimumBitWidth) 700 // Nope. 701 continue; 702 703 // Is the vector type legal? 704 MVT VecVT = MVT::getVectorVT(EltVT, MaskLength); 705 if (!isTypeLegal(VecVT)) 706 // Nope. 707 continue; 708 709 // If the element type is not legal, find a larger legal type to use for 710 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work! 711 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic 712 // node where the shuffle mask is a list of integer operands, #2 .. #2+n. 713 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE; 714 // Integer values types are consecutively numbered. Exploit this. 715 OpVT = MVT::SimpleValueType(OpVT + 1)) { 716 if (!isTypeLegal(OpVT)) 717 continue; 718 719 // Success! Rebuild the vector using the legal types. 720 SmallVector<SDOperand, 16> Ops(MaskLength); 721 for (unsigned i = 0; i < MaskLength; ++i) { 722 uint64_t Idx = 723 cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 724 Ops[i] = DAG.getConstant(Idx, OpVT); 725 } 726 return DAG.UpdateNodeOperands(SDOperand(N,0), 727 N->getOperand(0), N->getOperand(1), 728 DAG.getNode(ISD::BUILD_VECTOR, 729 VecVT, &Ops[0], Ops.size())); 730 } 731 732 // Continuing is pointless - failure is certain. 733 break; 734 } 735 assert(false && "Failed to find an appropriate mask type!"); 736 return SDOperand(N, 0); 737} 738