LegalizeVectorTypes.cpp revision 96e0c5477c41b316263e894bbb5821c7cdeb25ef
1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file performs vector type splitting and scalarization for LegalizeTypes. 11// Scalarization is the act of changing a computation in an illegal one-element 12// vector type to be a computation in its scalar element type. For example, 13// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed 14// as a base case when scalarizing vector arithmetic like <4 x f32>, which 15// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32 16// types. 17// Splitting is the act of changing a computation in an invalid vector type to 18// be a computation in two vectors of half the size. For example, implementing 19// <128 x f32> operations in terms of two <64 x f32> operations. 20// 21//===----------------------------------------------------------------------===// 22 23#include "LegalizeTypes.h" 24#include "llvm/CodeGen/PseudoSourceValue.h" 25#include "llvm/Target/TargetData.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Support/raw_ostream.h" 28using namespace llvm; 29 30//===----------------------------------------------------------------------===// 31// Result Vector Scalarization: <1 x ty> -> ty. 32//===----------------------------------------------------------------------===// 33 34void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { 35 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; 36 N->dump(&DAG); 37 dbgs() << "\n"); 38 SDValue R = SDValue(); 39 40 switch (N->getOpcode()) { 41 default: 42#ifndef NDEBUG 43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": "; 44 N->dump(&DAG); 45 dbgs() << "\n"; 46#endif 47 llvm_unreachable("Do not know how to scalarize the result of this operator!"); 48 49 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 50 case ISD::BUILD_VECTOR: R = N->getOperand(0); break; 51 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; 52 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 53 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; 54 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; 55 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 56 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 57 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; 58 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; 59 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; 60 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break; 61 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; 62 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; 63 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; 64 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; 65 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break; 66 67 case ISD::ANY_EXTEND: 68 case ISD::CTLZ: 69 case ISD::CTPOP: 70 case ISD::CTTZ: 71 case ISD::FABS: 72 case ISD::FCEIL: 73 case ISD::FCOS: 74 case ISD::FEXP: 75 case ISD::FEXP2: 76 case ISD::FFLOOR: 77 case ISD::FLOG: 78 case ISD::FLOG10: 79 case ISD::FLOG2: 80 case ISD::FNEARBYINT: 81 case ISD::FNEG: 82 case ISD::FP_EXTEND: 83 case ISD::FP_TO_SINT: 84 case ISD::FP_TO_UINT: 85 case ISD::FRINT: 86 case ISD::FSIN: 87 case ISD::FSQRT: 88 case ISD::FTRUNC: 89 case ISD::SIGN_EXTEND: 90 case ISD::SINT_TO_FP: 91 case ISD::TRUNCATE: 92 case ISD::UINT_TO_FP: 93 case ISD::ZERO_EXTEND: 94 R = ScalarizeVecRes_UnaryOp(N); 95 break; 96 97 case ISD::ADD: 98 case ISD::AND: 99 case ISD::FADD: 100 case ISD::FDIV: 101 case ISD::FMUL: 102 case ISD::FPOW: 103 case ISD::FREM: 104 case ISD::FSUB: 105 case ISD::MUL: 106 case ISD::OR: 107 case ISD::SDIV: 108 case ISD::SREM: 109 case ISD::SUB: 110 case ISD::UDIV: 111 case ISD::UREM: 112 case ISD::XOR: 113 case ISD::SHL: 114 case ISD::SRA: 115 case ISD::SRL: 116 R = ScalarizeVecRes_BinOp(N); 117 break; 118 } 119 120 // If R is null, the sub-method took care of registering the result. 121 if (R.getNode()) 122 SetScalarizedVector(SDValue(N, ResNo), R); 123} 124 125SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { 126 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 127 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 128 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 129 LHS.getValueType(), LHS, RHS); 130} 131 132SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) { 133 EVT NewVT = N->getValueType(0).getVectorElementType(); 134 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 135 NewVT, N->getOperand(0)); 136} 137 138SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) { 139 EVT NewVT = N->getValueType(0).getVectorElementType(); 140 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); 141 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(), 142 Op0, DAG.getValueType(NewVT), 143 DAG.getValueType(Op0.getValueType()), 144 N->getOperand(3), 145 N->getOperand(4), 146 cast<CvtRndSatSDNode>(N)->getCvtCode()); 147} 148 149SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 150 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 151 N->getValueType(0).getVectorElementType(), 152 N->getOperand(0), N->getOperand(1)); 153} 154 155SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) { 156 EVT NewVT = N->getValueType(0).getVectorElementType(); 157 SDValue Op = GetScalarizedVector(N->getOperand(0)); 158 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), 159 NewVT, Op, N->getOperand(1)); 160} 161 162SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) { 163 SDValue Op = GetScalarizedVector(N->getOperand(0)); 164 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(), 165 Op.getValueType(), Op, N->getOperand(1)); 166} 167 168SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { 169 // The value to insert may have a wider type than the vector element type, 170 // so be sure to truncate it to the element type if necessary. 171 SDValue Op = N->getOperand(1); 172 EVT EltVT = N->getValueType(0).getVectorElementType(); 173 if (Op.getValueType() != EltVT) 174 // FIXME: Can this happen for floating point types? 175 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op); 176 return Op; 177} 178 179SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { 180 assert(N->isUnindexed() && "Indexed vector load?"); 181 182 SDValue Result = DAG.getLoad(ISD::UNINDEXED, 183 N->getExtensionType(), 184 N->getValueType(0).getVectorElementType(), 185 N->getDebugLoc(), 186 N->getChain(), N->getBasePtr(), 187 DAG.getUNDEF(N->getBasePtr().getValueType()), 188 N->getPointerInfo(), 189 N->getMemoryVT().getVectorElementType(), 190 N->isVolatile(), N->isNonTemporal(), 191 N->getOriginalAlignment()); 192 193 // Legalized the chain result - switch anything that used the old chain to 194 // use the new one. 195 ReplaceValueWith(SDValue(N, 1), Result.getValue(1)); 196 return Result; 197} 198 199SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { 200 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp. 201 EVT DestVT = N->getValueType(0).getVectorElementType(); 202 SDValue Op = GetScalarizedVector(N->getOperand(0)); 203 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op); 204} 205 206SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) { 207 EVT EltVT = N->getValueType(0).getVectorElementType(); 208 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType(); 209 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 210 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT, 211 LHS, DAG.getValueType(ExtVT)); 212} 213 214SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) { 215 // If the operand is wider than the vector element type then it is implicitly 216 // truncated. Make that explicit here. 217 EVT EltVT = N->getValueType(0).getVectorElementType(); 218 SDValue InOp = N->getOperand(0); 219 if (InOp.getValueType() != EltVT) 220 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp); 221 return InOp; 222} 223 224SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) { 225 SDValue LHS = GetScalarizedVector(N->getOperand(1)); 226 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 227 LHS.getValueType(), N->getOperand(0), LHS, 228 GetScalarizedVector(N->getOperand(2))); 229} 230 231SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) { 232 SDValue LHS = GetScalarizedVector(N->getOperand(2)); 233 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(), 234 N->getOperand(0), N->getOperand(1), 235 LHS, GetScalarizedVector(N->getOperand(3)), 236 N->getOperand(4)); 237} 238 239SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) { 240 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 241 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 242 DebugLoc DL = N->getDebugLoc(); 243 244 // Turn it into a scalar SETCC. 245 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); 246} 247 248SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { 249 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 250} 251 252SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { 253 // Figure out if the scalar is the LHS or RHS and return it. 254 SDValue Arg = N->getOperand(2).getOperand(0); 255 if (Arg.getOpcode() == ISD::UNDEF) 256 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 257 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue(); 258 return GetScalarizedVector(N->getOperand(Op)); 259} 260 261SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) { 262 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 263 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 264 EVT NVT = N->getValueType(0).getVectorElementType(); 265 EVT SVT = TLI.getSetCCResultType(LHS.getValueType()); 266 DebugLoc DL = N->getDebugLoc(); 267 268 // Turn it into a scalar SETCC. 269 SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2)); 270 271 // VSETCC always returns a sign-extended value, while SETCC may not. The 272 // SETCC result type may not match the vector element type. Correct these. 273 if (NVT.bitsLE(SVT)) { 274 // The SETCC result type is bigger than the vector element type. 275 // Ensure the SETCC result is sign-extended. 276 if (TLI.getBooleanContents() != 277 TargetLowering::ZeroOrNegativeOneBooleanContent) 278 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res, 279 DAG.getValueType(MVT::i1)); 280 // Truncate to the final type. 281 return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res); 282 } 283 284 // The SETCC result type is smaller than the vector element type. 285 // If the SetCC result is not sign-extended, chop it down to MVT::i1. 286 if (TLI.getBooleanContents() != 287 TargetLowering::ZeroOrNegativeOneBooleanContent) 288 Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res); 289 // Sign extend to the final type. 290 return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res); 291} 292 293 294//===----------------------------------------------------------------------===// 295// Operand Vector Scalarization <1 x ty> -> ty. 296//===----------------------------------------------------------------------===// 297 298bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { 299 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; 300 N->dump(&DAG); 301 dbgs() << "\n"); 302 SDValue Res = SDValue(); 303 304 if (Res.getNode() == 0) { 305 switch (N->getOpcode()) { 306 default: 307#ifndef NDEBUG 308 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": "; 309 N->dump(&DAG); 310 dbgs() << "\n"; 311#endif 312 llvm_unreachable("Do not know how to scalarize this operator's operand!"); 313 case ISD::BITCAST: 314 Res = ScalarizeVecOp_BITCAST(N); 315 break; 316 case ISD::CONCAT_VECTORS: 317 Res = ScalarizeVecOp_CONCAT_VECTORS(N); 318 break; 319 case ISD::EXTRACT_VECTOR_ELT: 320 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); 321 break; 322 case ISD::STORE: 323 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); 324 break; 325 } 326 } 327 328 // If the result is null, the sub-method took care of registering results etc. 329 if (!Res.getNode()) return false; 330 331 // If the result is N, the sub-method updated N in place. Tell the legalizer 332 // core about this. 333 if (Res.getNode() == N) 334 return true; 335 336 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 337 "Invalid operand expansion"); 338 339 ReplaceValueWith(SDValue(N, 0), Res); 340 return false; 341} 342 343/// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs 344/// to be scalarized, it must be <1 x ty>. Convert the element instead. 345SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) { 346 SDValue Elt = GetScalarizedVector(N->getOperand(0)); 347 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 348 N->getValueType(0), Elt); 349} 350 351/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one - 352/// use a BUILD_VECTOR instead. 353SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) { 354 SmallVector<SDValue, 8> Ops(N->getNumOperands()); 355 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 356 Ops[i] = GetScalarizedVector(N->getOperand(i)); 357 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0), 358 &Ops[0], Ops.size()); 359} 360 361/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to 362/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the 363/// index. 364SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 365 SDValue Res = GetScalarizedVector(N->getOperand(0)); 366 if (Res.getValueType() != N->getValueType(0)) 367 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), 368 Res); 369 return Res; 370} 371 372/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be 373/// scalarized, it must be <1 x ty>. Just store the element. 374SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ 375 assert(N->isUnindexed() && "Indexed store of one-element vector?"); 376 assert(OpNo == 1 && "Do not know how to scalarize this operand!"); 377 DebugLoc dl = N->getDebugLoc(); 378 379 if (N->isTruncatingStore()) 380 return DAG.getTruncStore(N->getChain(), dl, 381 GetScalarizedVector(N->getOperand(1)), 382 N->getBasePtr(), N->getPointerInfo(), 383 N->getMemoryVT().getVectorElementType(), 384 N->isVolatile(), N->isNonTemporal(), 385 N->getAlignment()); 386 387 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)), 388 N->getBasePtr(), N->getPointerInfo(), 389 N->isVolatile(), N->isNonTemporal(), 390 N->getOriginalAlignment()); 391} 392 393 394//===----------------------------------------------------------------------===// 395// Result Vector Splitting 396//===----------------------------------------------------------------------===// 397 398/// SplitVectorResult - This method is called when the specified result of the 399/// specified node is found to need vector splitting. At this point, the node 400/// may also have invalid operands or may have other results that need 401/// legalization, we just know that (at least) one result needs vector 402/// splitting. 403void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { 404 DEBUG(dbgs() << "Split node result: "; 405 N->dump(&DAG); 406 dbgs() << "\n"); 407 SDValue Lo, Hi; 408 409 switch (N->getOpcode()) { 410 default: 411#ifndef NDEBUG 412 dbgs() << "SplitVectorResult #" << ResNo << ": "; 413 N->dump(&DAG); 414 dbgs() << "\n"; 415#endif 416 llvm_unreachable("Do not know how to split the result of this operator!"); 417 418 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 419 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 420 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 421 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 422 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; 423 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 424 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 425 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; 426 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 427 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; 428 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 429 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break; 430 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 431 case ISD::LOAD: 432 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); 433 break; 434 case ISD::SETCC: 435 case ISD::VSETCC: 436 SplitVecRes_SETCC(N, Lo, Hi); 437 break; 438 case ISD::VECTOR_SHUFFLE: 439 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); 440 break; 441 442 case ISD::ANY_EXTEND: 443 case ISD::CONVERT_RNDSAT: 444 case ISD::CTLZ: 445 case ISD::CTPOP: 446 case ISD::CTTZ: 447 case ISD::FABS: 448 case ISD::FCEIL: 449 case ISD::FCOS: 450 case ISD::FEXP: 451 case ISD::FEXP2: 452 case ISD::FFLOOR: 453 case ISD::FLOG: 454 case ISD::FLOG10: 455 case ISD::FLOG2: 456 case ISD::FNEARBYINT: 457 case ISD::FNEG: 458 case ISD::FP_EXTEND: 459 case ISD::FP_ROUND: 460 case ISD::FP_TO_SINT: 461 case ISD::FP_TO_UINT: 462 case ISD::FRINT: 463 case ISD::FSIN: 464 case ISD::FSQRT: 465 case ISD::FTRUNC: 466 case ISD::SIGN_EXTEND: 467 case ISD::SINT_TO_FP: 468 case ISD::TRUNCATE: 469 case ISD::UINT_TO_FP: 470 case ISD::ZERO_EXTEND: 471 SplitVecRes_UnaryOp(N, Lo, Hi); 472 break; 473 474 case ISD::ADD: 475 case ISD::SUB: 476 case ISD::MUL: 477 case ISD::FADD: 478 case ISD::FSUB: 479 case ISD::FMUL: 480 case ISD::SDIV: 481 case ISD::UDIV: 482 case ISD::FDIV: 483 case ISD::FPOW: 484 case ISD::AND: 485 case ISD::OR: 486 case ISD::XOR: 487 case ISD::SHL: 488 case ISD::SRA: 489 case ISD::SRL: 490 case ISD::UREM: 491 case ISD::SREM: 492 case ISD::FREM: 493 SplitVecRes_BinOp(N, Lo, Hi); 494 break; 495 } 496 497 // If Lo/Hi is null, the sub-method took care of registering results etc. 498 if (Lo.getNode()) 499 SetSplitVector(SDValue(N, ResNo), Lo, Hi); 500} 501 502void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo, 503 SDValue &Hi) { 504 SDValue LHSLo, LHSHi; 505 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 506 SDValue RHSLo, RHSHi; 507 GetSplitVector(N->getOperand(1), RHSLo, RHSHi); 508 DebugLoc dl = N->getDebugLoc(); 509 510 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo); 511 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi); 512} 513 514void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, 515 SDValue &Hi) { 516 // We know the result is a vector. The input may be either a vector or a 517 // scalar value. 518 EVT LoVT, HiVT; 519 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 520 DebugLoc dl = N->getDebugLoc(); 521 522 SDValue InOp = N->getOperand(0); 523 EVT InVT = InOp.getValueType(); 524 525 // Handle some special cases efficiently. 526 switch (getTypeAction(InVT)) { 527 default: 528 assert(false && "Unknown type action!"); 529 case TargetLowering::TypeLegal: 530 case TargetLowering::TypePromoteInteger: 531 case TargetLowering::TypeSoftenFloat: 532 case TargetLowering::TypeScalarizeVector: 533 break; 534 case TargetLowering::TypeExpandInteger: 535 case TargetLowering::TypeExpandFloat: 536 // A scalar to vector conversion, where the scalar needs expansion. 537 // If the vector is being split in two then we can just convert the 538 // expanded pieces. 539 if (LoVT == HiVT) { 540 GetExpandedOp(InOp, Lo, Hi); 541 if (TLI.isBigEndian()) 542 std::swap(Lo, Hi); 543 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 544 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 545 return; 546 } 547 break; 548 case TargetLowering::TypeSplitVector: 549 // If the input is a vector that needs to be split, convert each split 550 // piece of the input now. 551 GetSplitVector(InOp, Lo, Hi); 552 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 553 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 554 return; 555 } 556 557 // In the general case, convert the input to an integer and split it by hand. 558 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits()); 559 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits()); 560 if (TLI.isBigEndian()) 561 std::swap(LoIntVT, HiIntVT); 562 563 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); 564 565 if (TLI.isBigEndian()) 566 std::swap(Lo, Hi); 567 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 568 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 569} 570 571void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, 572 SDValue &Hi) { 573 EVT LoVT, HiVT; 574 DebugLoc dl = N->getDebugLoc(); 575 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 576 unsigned LoNumElts = LoVT.getVectorNumElements(); 577 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts); 578 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size()); 579 580 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end()); 581 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size()); 582} 583 584void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, 585 SDValue &Hi) { 586 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"); 587 DebugLoc dl = N->getDebugLoc(); 588 unsigned NumSubvectors = N->getNumOperands() / 2; 589 if (NumSubvectors == 1) { 590 Lo = N->getOperand(0); 591 Hi = N->getOperand(1); 592 return; 593 } 594 595 EVT LoVT, HiVT; 596 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 597 598 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); 599 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size()); 600 601 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end()); 602 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size()); 603} 604 605void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, 606 SDValue &Hi) { 607 SDValue Vec = N->getOperand(0); 608 SDValue Idx = N->getOperand(1); 609 DebugLoc dl = N->getDebugLoc(); 610 611 EVT LoVT, HiVT; 612 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 613 614 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); 615 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 616 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, 617 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements())); 618} 619 620void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, 621 SDValue &Hi) { 622 DebugLoc dl = N->getDebugLoc(); 623 GetSplitVector(N->getOperand(0), Lo, Hi); 624 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1)); 625 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1)); 626} 627 628void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo, 629 SDValue &Hi) { 630 SDValue LHSLo, LHSHi; 631 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 632 DebugLoc dl = N->getDebugLoc(); 633 634 EVT LoVT, HiVT; 635 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT); 636 637 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, 638 DAG.getValueType(LoVT)); 639 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, 640 DAG.getValueType(HiVT)); 641} 642 643void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, 644 SDValue &Hi) { 645 SDValue Vec = N->getOperand(0); 646 SDValue Elt = N->getOperand(1); 647 SDValue Idx = N->getOperand(2); 648 DebugLoc dl = N->getDebugLoc(); 649 GetSplitVector(Vec, Lo, Hi); 650 651 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 652 unsigned IdxVal = CIdx->getZExtValue(); 653 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 654 if (IdxVal < LoNumElts) 655 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 656 Lo.getValueType(), Lo, Elt, Idx); 657 else 658 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, 659 DAG.getIntPtrConstant(IdxVal - LoNumElts)); 660 return; 661 } 662 663 // Spill the vector to the stack. 664 EVT VecVT = Vec.getValueType(); 665 EVT EltVT = VecVT.getVectorElementType(); 666 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 667 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 668 MachinePointerInfo(), false, false, 0); 669 670 // Store the new element. This may be larger than the vector element type, 671 // so use a truncating store. 672 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 673 const Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); 674 unsigned Alignment = 675 TLI.getTargetData()->getPrefTypeAlignment(VecType); 676 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT, 677 false, false, 0); 678 679 // Load the Lo part from the stack slot. 680 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 681 false, false, 0); 682 683 // Increment the pointer to the other part. 684 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; 685 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 686 DAG.getIntPtrConstant(IncrementSize)); 687 688 // Load the Hi part from the stack slot. 689 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 690 false, false, MinAlign(Alignment, IncrementSize)); 691} 692 693void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, 694 SDValue &Hi) { 695 EVT LoVT, HiVT; 696 DebugLoc dl = N->getDebugLoc(); 697 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 698 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0)); 699 Hi = DAG.getUNDEF(HiVT); 700} 701 702void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, 703 SDValue &Hi) { 704 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"); 705 EVT LoVT, HiVT; 706 DebugLoc dl = LD->getDebugLoc(); 707 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); 708 709 ISD::LoadExtType ExtType = LD->getExtensionType(); 710 SDValue Ch = LD->getChain(); 711 SDValue Ptr = LD->getBasePtr(); 712 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 713 EVT MemoryVT = LD->getMemoryVT(); 714 unsigned Alignment = LD->getOriginalAlignment(); 715 bool isVolatile = LD->isVolatile(); 716 bool isNonTemporal = LD->isNonTemporal(); 717 718 EVT LoMemVT, HiMemVT; 719 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 720 721 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, 722 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal, 723 Alignment); 724 725 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 726 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 727 DAG.getIntPtrConstant(IncrementSize)); 728 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, 729 LD->getPointerInfo().getWithOffset(IncrementSize), 730 HiMemVT, isVolatile, isNonTemporal, Alignment); 731 732 // Build a factor node to remember that this load is independent of the 733 // other one. 734 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 735 Hi.getValue(1)); 736 737 // Legalized the chain result - switch anything that used the old chain to 738 // use the new one. 739 ReplaceValueWith(SDValue(LD, 1), Ch); 740} 741 742void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) { 743 EVT LoVT, HiVT; 744 DebugLoc DL = N->getDebugLoc(); 745 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 746 747 // Split the input. 748 EVT InVT = N->getOperand(0).getValueType(); 749 SDValue LL, LH, RL, RH; 750 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 751 LoVT.getVectorNumElements()); 752 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 753 DAG.getIntPtrConstant(0)); 754 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 755 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 756 757 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 758 DAG.getIntPtrConstant(0)); 759 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 760 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 761 762 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2)); 763 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2)); 764} 765 766void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, 767 SDValue &Hi) { 768 // Get the dest types - they may not match the input types, e.g. int_to_fp. 769 EVT LoVT, HiVT; 770 DebugLoc dl = N->getDebugLoc(); 771 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 772 773 // Split the input. 774 EVT InVT = N->getOperand(0).getValueType(); 775 switch (getTypeAction(InVT)) { 776 default: llvm_unreachable("Unexpected type action!"); 777 case TargetLowering::TypeLegal: { 778 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 779 LoVT.getVectorNumElements()); 780 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 781 DAG.getIntPtrConstant(0)); 782 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 783 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 784 break; 785 } 786 case TargetLowering::TypeSplitVector: 787 GetSplitVector(N->getOperand(0), Lo, Hi); 788 break; 789 case TargetLowering::TypeWidenVector: { 790 // If the result needs to be split and the input needs to be widened, 791 // the two types must have different lengths. Use the widened result 792 // and extract from it to do the split. 793 SDValue InOp = GetWidenedVector(N->getOperand(0)); 794 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 795 LoVT.getVectorNumElements()); 796 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 797 DAG.getIntPtrConstant(0)); 798 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 799 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 800 break; 801 } 802 } 803 804 if (N->getOpcode() == ISD::FP_ROUND) { 805 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1)); 806 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1)); 807 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) { 808 SDValue DTyOpLo = DAG.getValueType(LoVT); 809 SDValue DTyOpHi = DAG.getValueType(HiVT); 810 SDValue STyOpLo = DAG.getValueType(Lo.getValueType()); 811 SDValue STyOpHi = DAG.getValueType(Hi.getValueType()); 812 SDValue RndOp = N->getOperand(3); 813 SDValue SatOp = N->getOperand(4); 814 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 815 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp, 816 CvtCode); 817 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp, 818 CvtCode); 819 } else { 820 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo); 821 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi); 822 } 823} 824 825void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, 826 SDValue &Lo, SDValue &Hi) { 827 // The low and high parts of the original input give four input vectors. 828 SDValue Inputs[4]; 829 DebugLoc dl = N->getDebugLoc(); 830 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]); 831 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]); 832 EVT NewVT = Inputs[0].getValueType(); 833 unsigned NewElts = NewVT.getVectorNumElements(); 834 835 // If Lo or Hi uses elements from at most two of the four input vectors, then 836 // express it as a vector shuffle of those two inputs. Otherwise extract the 837 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. 838 SmallVector<int, 16> Ops; 839 for (unsigned High = 0; High < 2; ++High) { 840 SDValue &Output = High ? Hi : Lo; 841 842 // Build a shuffle mask for the output, discovering on the fly which 843 // input vectors to use as shuffle operands (recorded in InputUsed). 844 // If building a suitable shuffle vector proves too hard, then bail 845 // out with useBuildVector set. 846 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered. 847 unsigned FirstMaskIdx = High * NewElts; 848 bool useBuildVector = false; 849 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 850 // The mask element. This indexes into the input. 851 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 852 853 // The input vector this mask element indexes into. 854 unsigned Input = (unsigned)Idx / NewElts; 855 856 if (Input >= array_lengthof(Inputs)) { 857 // The mask element does not index into any input vector. 858 Ops.push_back(-1); 859 continue; 860 } 861 862 // Turn the index into an offset from the start of the input vector. 863 Idx -= Input * NewElts; 864 865 // Find or create a shuffle vector operand to hold this input. 866 unsigned OpNo; 867 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 868 if (InputUsed[OpNo] == Input) { 869 // This input vector is already an operand. 870 break; 871 } else if (InputUsed[OpNo] == -1U) { 872 // Create a new operand for this input vector. 873 InputUsed[OpNo] = Input; 874 break; 875 } 876 } 877 878 if (OpNo >= array_lengthof(InputUsed)) { 879 // More than two input vectors used! Give up on trying to create a 880 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 881 useBuildVector = true; 882 break; 883 } 884 885 // Add the mask index for the new shuffle vector. 886 Ops.push_back(Idx + OpNo * NewElts); 887 } 888 889 if (useBuildVector) { 890 EVT EltVT = NewVT.getVectorElementType(); 891 SmallVector<SDValue, 16> SVOps; 892 893 // Extract the input elements by hand. 894 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 895 // The mask element. This indexes into the input. 896 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 897 898 // The input vector this mask element indexes into. 899 unsigned Input = (unsigned)Idx / NewElts; 900 901 if (Input >= array_lengthof(Inputs)) { 902 // The mask element is "undef" or indexes off the end of the input. 903 SVOps.push_back(DAG.getUNDEF(EltVT)); 904 continue; 905 } 906 907 // Turn the index into an offset from the start of the input vector. 908 Idx -= Input * NewElts; 909 910 // Extract the vector element by hand. 911 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 912 Inputs[Input], DAG.getIntPtrConstant(Idx))); 913 } 914 915 // Construct the Lo/Hi output using a BUILD_VECTOR. 916 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size()); 917 } else if (InputUsed[0] == -1U) { 918 // No input vectors were used! The result is undefined. 919 Output = DAG.getUNDEF(NewVT); 920 } else { 921 SDValue Op0 = Inputs[InputUsed[0]]; 922 // If only one input was used, use an undefined vector for the other. 923 SDValue Op1 = InputUsed[1] == -1U ? 924 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]]; 925 // At least one input vector was used. Create a new shuffle vector. 926 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]); 927 } 928 929 Ops.clear(); 930 } 931} 932 933 934//===----------------------------------------------------------------------===// 935// Operand Vector Splitting 936//===----------------------------------------------------------------------===// 937 938/// SplitVectorOperand - This method is called when the specified operand of the 939/// specified node is found to need vector splitting. At this point, all of the 940/// result types of the node are known to be legal, but other operands of the 941/// node may need legalization as well as the specified one. 942bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { 943 DEBUG(dbgs() << "Split node operand: "; 944 N->dump(&DAG); 945 dbgs() << "\n"); 946 SDValue Res = SDValue(); 947 948 if (Res.getNode() == 0) { 949 switch (N->getOpcode()) { 950 default: 951#ifndef NDEBUG 952 dbgs() << "SplitVectorOperand Op #" << OpNo << ": "; 953 N->dump(&DAG); 954 dbgs() << "\n"; 955#endif 956 llvm_unreachable("Do not know how to split this operator's operand!"); 957 958 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break; 959 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; 960 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; 961 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; 962 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; 963 case ISD::STORE: 964 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo); 965 break; 966 967 case ISD::CTTZ: 968 case ISD::CTLZ: 969 case ISD::CTPOP: 970 case ISD::FP_EXTEND: 971 case ISD::FP_TO_SINT: 972 case ISD::FP_TO_UINT: 973 case ISD::SINT_TO_FP: 974 case ISD::UINT_TO_FP: 975 case ISD::FTRUNC: 976 case ISD::TRUNCATE: 977 case ISD::SIGN_EXTEND: 978 case ISD::ZERO_EXTEND: 979 case ISD::ANY_EXTEND: 980 Res = SplitVecOp_UnaryOp(N); 981 break; 982 } 983 } 984 985 // If the result is null, the sub-method took care of registering results etc. 986 if (!Res.getNode()) return false; 987 988 // If the result is N, the sub-method updated N in place. Tell the legalizer 989 // core about this. 990 if (Res.getNode() == N) 991 return true; 992 993 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 994 "Invalid operand expansion"); 995 996 ReplaceValueWith(SDValue(N, 0), Res); 997 return false; 998} 999 1000SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) { 1001 // The result has a legal vector type, but the input needs splitting. 1002 EVT ResVT = N->getValueType(0); 1003 SDValue Lo, Hi; 1004 DebugLoc dl = N->getDebugLoc(); 1005 GetSplitVector(N->getOperand(0), Lo, Hi); 1006 EVT InVT = Lo.getValueType(); 1007 1008 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1009 InVT.getVectorNumElements()); 1010 1011 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); 1012 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); 1013 1014 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); 1015} 1016 1017SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) { 1018 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will 1019 // end up being split all the way down to individual components. Convert the 1020 // split pieces into integers and reassemble. 1021 SDValue Lo, Hi; 1022 GetSplitVector(N->getOperand(0), Lo, Hi); 1023 Lo = BitConvertToInteger(Lo); 1024 Hi = BitConvertToInteger(Hi); 1025 1026 if (TLI.isBigEndian()) 1027 std::swap(Lo, Hi); 1028 1029 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0), 1030 JoinIntegers(Lo, Hi)); 1031} 1032 1033SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 1034 // We know that the extracted result type is legal. 1035 EVT SubVT = N->getValueType(0); 1036 SDValue Idx = N->getOperand(1); 1037 DebugLoc dl = N->getDebugLoc(); 1038 SDValue Lo, Hi; 1039 GetSplitVector(N->getOperand(0), Lo, Hi); 1040 1041 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1042 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1043 1044 if (IdxVal < LoElts) { 1045 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && 1046 "Extracted subvector crosses vector split!"); 1047 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); 1048 } else { 1049 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, 1050 DAG.getConstant(IdxVal - LoElts, Idx.getValueType())); 1051 } 1052} 1053 1054SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 1055 SDValue Vec = N->getOperand(0); 1056 SDValue Idx = N->getOperand(1); 1057 EVT VecVT = Vec.getValueType(); 1058 1059 if (isa<ConstantSDNode>(Idx)) { 1060 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1061 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); 1062 1063 SDValue Lo, Hi; 1064 GetSplitVector(Vec, Lo, Hi); 1065 1066 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1067 1068 if (IdxVal < LoElts) 1069 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0); 1070 return SDValue(DAG.UpdateNodeOperands(N, Hi, 1071 DAG.getConstant(IdxVal - LoElts, 1072 Idx.getValueType())), 0); 1073 } 1074 1075 // Store the vector to the stack. 1076 EVT EltVT = VecVT.getVectorElementType(); 1077 DebugLoc dl = N->getDebugLoc(); 1078 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 1079 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 1080 MachinePointerInfo(), false, false, 0); 1081 1082 // Load back the required element. 1083 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 1084 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, 1085 MachinePointerInfo(), EltVT, false, false, 0); 1086} 1087 1088SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { 1089 assert(N->isUnindexed() && "Indexed store of vector?"); 1090 assert(OpNo == 1 && "Can only split the stored value"); 1091 DebugLoc DL = N->getDebugLoc(); 1092 1093 bool isTruncating = N->isTruncatingStore(); 1094 SDValue Ch = N->getChain(); 1095 SDValue Ptr = N->getBasePtr(); 1096 EVT MemoryVT = N->getMemoryVT(); 1097 unsigned Alignment = N->getOriginalAlignment(); 1098 bool isVol = N->isVolatile(); 1099 bool isNT = N->isNonTemporal(); 1100 SDValue Lo, Hi; 1101 GetSplitVector(N->getOperand(1), Lo, Hi); 1102 1103 EVT LoMemVT, HiMemVT; 1104 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 1105 1106 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 1107 1108 if (isTruncating) 1109 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1110 LoMemVT, isVol, isNT, Alignment); 1111 else 1112 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1113 isVol, isNT, Alignment); 1114 1115 // Increment the pointer to the other half. 1116 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, 1117 DAG.getIntPtrConstant(IncrementSize)); 1118 1119 if (isTruncating) 1120 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr, 1121 N->getPointerInfo().getWithOffset(IncrementSize), 1122 HiMemVT, isVol, isNT, Alignment); 1123 else 1124 Hi = DAG.getStore(Ch, DL, Hi, Ptr, 1125 N->getPointerInfo().getWithOffset(IncrementSize), 1126 isVol, isNT, Alignment); 1127 1128 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi); 1129} 1130 1131SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) { 1132 DebugLoc DL = N->getDebugLoc(); 1133 1134 // The input operands all must have the same type, and we know the result the 1135 // result type is valid. Convert this to a buildvector which extracts all the 1136 // input elements. 1137 // TODO: If the input elements are power-two vectors, we could convert this to 1138 // a new CONCAT_VECTORS node with elements that are half-wide. 1139 SmallVector<SDValue, 32> Elts; 1140 EVT EltVT = N->getValueType(0).getVectorElementType(); 1141 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1142 SDValue Op = N->getOperand(op); 1143 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements(); 1144 i != e; ++i) { 1145 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, 1146 Op, DAG.getIntPtrConstant(i))); 1147 1148 } 1149 } 1150 1151 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), 1152 &Elts[0], Elts.size()); 1153} 1154 1155SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) { 1156 // The result has a legal vector type, but the input needs splitting. 1157 EVT ResVT = N->getValueType(0); 1158 SDValue Lo, Hi; 1159 DebugLoc DL = N->getDebugLoc(); 1160 GetSplitVector(N->getOperand(0), Lo, Hi); 1161 EVT InVT = Lo.getValueType(); 1162 1163 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1164 InVT.getVectorNumElements()); 1165 1166 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); 1167 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); 1168 1169 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); 1170} 1171 1172 1173 1174//===----------------------------------------------------------------------===// 1175// Result Vector Widening 1176//===----------------------------------------------------------------------===// 1177 1178void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { 1179 DEBUG(dbgs() << "Widen node result " << ResNo << ": "; 1180 N->dump(&DAG); 1181 dbgs() << "\n"); 1182 1183 // See if the target wants to custom widen this node. 1184 if (CustomWidenLowerNode(N, N->getValueType(ResNo))) 1185 return; 1186 1187 SDValue Res = SDValue(); 1188 switch (N->getOpcode()) { 1189 default: 1190#ifndef NDEBUG 1191 dbgs() << "WidenVectorResult #" << ResNo << ": "; 1192 N->dump(&DAG); 1193 dbgs() << "\n"; 1194#endif 1195 llvm_unreachable("Do not know how to widen the result of this operator!"); 1196 1197 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break; 1198 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; 1199 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break; 1200 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break; 1201 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; 1202 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break; 1203 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; 1204 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break; 1205 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break; 1206 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break; 1207 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break; 1208 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; 1209 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; 1210 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break; 1211 case ISD::VECTOR_SHUFFLE: 1212 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N)); 1213 break; 1214 case ISD::VSETCC: 1215 Res = WidenVecRes_VSETCC(N); 1216 break; 1217 1218 case ISD::ADD: 1219 case ISD::AND: 1220 case ISD::BSWAP: 1221 case ISD::FADD: 1222 case ISD::FCOPYSIGN: 1223 case ISD::FDIV: 1224 case ISD::FMUL: 1225 case ISD::FPOW: 1226 case ISD::FREM: 1227 case ISD::FSUB: 1228 case ISD::MUL: 1229 case ISD::MULHS: 1230 case ISD::MULHU: 1231 case ISD::OR: 1232 case ISD::SDIV: 1233 case ISD::SREM: 1234 case ISD::UDIV: 1235 case ISD::UREM: 1236 case ISD::SUB: 1237 case ISD::XOR: 1238 Res = WidenVecRes_Binary(N); 1239 break; 1240 1241 case ISD::FPOWI: 1242 Res = WidenVecRes_POWI(N); 1243 break; 1244 1245 case ISD::SHL: 1246 case ISD::SRA: 1247 case ISD::SRL: 1248 Res = WidenVecRes_Shift(N); 1249 break; 1250 1251 case ISD::ANY_EXTEND: 1252 case ISD::FP_EXTEND: 1253 case ISD::FP_ROUND: 1254 case ISD::FP_TO_SINT: 1255 case ISD::FP_TO_UINT: 1256 case ISD::SIGN_EXTEND: 1257 case ISD::SINT_TO_FP: 1258 case ISD::TRUNCATE: 1259 case ISD::UINT_TO_FP: 1260 case ISD::ZERO_EXTEND: 1261 Res = WidenVecRes_Convert(N); 1262 break; 1263 1264 case ISD::CTLZ: 1265 case ISD::CTPOP: 1266 case ISD::CTTZ: 1267 case ISD::FABS: 1268 case ISD::FCEIL: 1269 case ISD::FCOS: 1270 case ISD::FEXP: 1271 case ISD::FEXP2: 1272 case ISD::FFLOOR: 1273 case ISD::FLOG: 1274 case ISD::FLOG10: 1275 case ISD::FLOG2: 1276 case ISD::FNEARBYINT: 1277 case ISD::FNEG: 1278 case ISD::FRINT: 1279 case ISD::FSIN: 1280 case ISD::FSQRT: 1281 case ISD::FTRUNC: 1282 Res = WidenVecRes_Unary(N); 1283 break; 1284 } 1285 1286 // If Res is null, the sub-method took care of registering the result. 1287 if (Res.getNode()) 1288 SetWidenedVector(SDValue(N, ResNo), Res); 1289} 1290 1291SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) { 1292 // Binary op widening. 1293 unsigned Opcode = N->getOpcode(); 1294 DebugLoc dl = N->getDebugLoc(); 1295 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1296 EVT WidenEltVT = WidenVT.getVectorElementType(); 1297 EVT VT = WidenVT; 1298 unsigned NumElts = VT.getVectorNumElements(); 1299 while (!TLI.isTypeLegal(VT) && NumElts != 1) { 1300 NumElts = NumElts / 2; 1301 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1302 } 1303 1304 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) { 1305 // Operation doesn't trap so just widen as normal. 1306 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1307 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1308 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2); 1309 } 1310 1311 // No legal vector version so unroll the vector operation and then widen. 1312 if (NumElts == 1) 1313 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()); 1314 1315 // Since the operation can trap, apply operation on the original vector. 1316 EVT MaxVT = VT; 1317 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1318 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1319 unsigned CurNumElts = N->getValueType(0).getVectorNumElements(); 1320 1321 SmallVector<SDValue, 16> ConcatOps(CurNumElts); 1322 unsigned ConcatEnd = 0; // Current ConcatOps index. 1323 int Idx = 0; // Current Idx into input vectors. 1324 1325 // NumElts := greatest legal vector size (at most WidenVT) 1326 // while (orig. vector has unhandled elements) { 1327 // take munches of size NumElts from the beginning and add to ConcatOps 1328 // NumElts := next smaller supported vector size or 1 1329 // } 1330 while (CurNumElts != 0) { 1331 while (CurNumElts >= NumElts) { 1332 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, 1333 DAG.getIntPtrConstant(Idx)); 1334 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, 1335 DAG.getIntPtrConstant(Idx)); 1336 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2); 1337 Idx += NumElts; 1338 CurNumElts -= NumElts; 1339 } 1340 do { 1341 NumElts = NumElts / 2; 1342 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1343 } while (!TLI.isTypeLegal(VT) && NumElts != 1); 1344 1345 if (NumElts == 1) { 1346 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) { 1347 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1348 InOp1, DAG.getIntPtrConstant(Idx)); 1349 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1350 InOp2, DAG.getIntPtrConstant(Idx)); 1351 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT, 1352 EOp1, EOp2); 1353 } 1354 CurNumElts = 0; 1355 } 1356 } 1357 1358 // Check to see if we have a single operation with the widen type. 1359 if (ConcatEnd == 1) { 1360 VT = ConcatOps[0].getValueType(); 1361 if (VT == WidenVT) 1362 return ConcatOps[0]; 1363 } 1364 1365 // while (Some element of ConcatOps is not of type MaxVT) { 1366 // From the end of ConcatOps, collect elements of the same type and put 1367 // them into an op of the next larger supported type 1368 // } 1369 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) { 1370 Idx = ConcatEnd - 1; 1371 VT = ConcatOps[Idx--].getValueType(); 1372 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT) 1373 Idx--; 1374 1375 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1; 1376 EVT NextVT; 1377 do { 1378 NextSize *= 2; 1379 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize); 1380 } while (!TLI.isTypeLegal(NextVT)); 1381 1382 if (!VT.isVector()) { 1383 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT 1384 SDValue VecOp = DAG.getUNDEF(NextVT); 1385 unsigned NumToInsert = ConcatEnd - Idx - 1; 1386 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) { 1387 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, 1388 ConcatOps[OpIdx], DAG.getIntPtrConstant(i)); 1389 } 1390 ConcatOps[Idx+1] = VecOp; 1391 ConcatEnd = Idx + 2; 1392 } else { 1393 // Vector type, create a CONCAT_VECTORS of type NextVT 1394 SDValue undefVec = DAG.getUNDEF(VT); 1395 unsigned OpsToConcat = NextSize/VT.getVectorNumElements(); 1396 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat); 1397 unsigned RealVals = ConcatEnd - Idx - 1; 1398 unsigned SubConcatEnd = 0; 1399 unsigned SubConcatIdx = Idx + 1; 1400 while (SubConcatEnd < RealVals) 1401 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx]; 1402 while (SubConcatEnd < OpsToConcat) 1403 SubConcatOps[SubConcatEnd++] = undefVec; 1404 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1405 NextVT, &SubConcatOps[0], 1406 OpsToConcat); 1407 ConcatEnd = SubConcatIdx + 1; 1408 } 1409 } 1410 1411 // Check to see if we have a single operation with the widen type. 1412 if (ConcatEnd == 1) { 1413 VT = ConcatOps[0].getValueType(); 1414 if (VT == WidenVT) 1415 return ConcatOps[0]; 1416 } 1417 1418 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT 1419 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements(); 1420 if (NumOps != ConcatEnd ) { 1421 SDValue UndefVal = DAG.getUNDEF(MaxVT); 1422 for (unsigned j = ConcatEnd; j < NumOps; ++j) 1423 ConcatOps[j] = UndefVal; 1424 } 1425 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps); 1426} 1427 1428SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { 1429 SDValue InOp = N->getOperand(0); 1430 DebugLoc DL = N->getDebugLoc(); 1431 1432 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1433 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1434 1435 EVT InVT = InOp.getValueType(); 1436 EVT InEltVT = InVT.getVectorElementType(); 1437 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1438 1439 unsigned Opcode = N->getOpcode(); 1440 unsigned InVTNumElts = InVT.getVectorNumElements(); 1441 1442 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1443 InOp = GetWidenedVector(N->getOperand(0)); 1444 InVT = InOp.getValueType(); 1445 InVTNumElts = InVT.getVectorNumElements(); 1446 if (InVTNumElts == WidenNumElts) { 1447 if (N->getNumOperands() == 1) 1448 return DAG.getNode(Opcode, DL, WidenVT, InOp); 1449 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1)); 1450 } 1451 } 1452 1453 if (TLI.isTypeLegal(InWidenVT)) { 1454 // Because the result and the input are different vector types, widening 1455 // the result could create a legal type but widening the input might make 1456 // it an illegal type that might lead to repeatedly splitting the input 1457 // and then widening it. To avoid this, we widen the input only if 1458 // it results in a legal type. 1459 if (WidenNumElts % InVTNumElts == 0) { 1460 // Widen the input and call convert on the widened input vector. 1461 unsigned NumConcat = WidenNumElts/InVTNumElts; 1462 SmallVector<SDValue, 16> Ops(NumConcat); 1463 Ops[0] = InOp; 1464 SDValue UndefVal = DAG.getUNDEF(InVT); 1465 for (unsigned i = 1; i != NumConcat; ++i) 1466 Ops[i] = UndefVal; 1467 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, 1468 &Ops[0], NumConcat); 1469 if (N->getNumOperands() == 1) 1470 return DAG.getNode(Opcode, DL, WidenVT, InVec); 1471 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1)); 1472 } 1473 1474 if (InVTNumElts % WidenNumElts == 0) { 1475 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, 1476 InOp, DAG.getIntPtrConstant(0)); 1477 // Extract the input and convert the shorten input vector. 1478 if (N->getNumOperands() == 1) 1479 return DAG.getNode(Opcode, DL, WidenVT, InVal); 1480 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1)); 1481 } 1482 } 1483 1484 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1485 SmallVector<SDValue, 16> Ops(WidenNumElts); 1486 EVT EltVT = WidenVT.getVectorElementType(); 1487 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1488 unsigned i; 1489 for (i=0; i < MinElts; ++i) { 1490 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp, 1491 DAG.getIntPtrConstant(i)); 1492 if (N->getNumOperands() == 1) 1493 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val); 1494 else 1495 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1)); 1496 } 1497 1498 SDValue UndefVal = DAG.getUNDEF(EltVT); 1499 for (; i < WidenNumElts; ++i) 1500 Ops[i] = UndefVal; 1501 1502 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts); 1503} 1504 1505SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) { 1506 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1507 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1508 SDValue ShOp = N->getOperand(1); 1509 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1510} 1511 1512SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) { 1513 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1514 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1515 SDValue ShOp = N->getOperand(1); 1516 1517 EVT ShVT = ShOp.getValueType(); 1518 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) { 1519 ShOp = GetWidenedVector(ShOp); 1520 ShVT = ShOp.getValueType(); 1521 } 1522 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(), 1523 ShVT.getVectorElementType(), 1524 WidenVT.getVectorNumElements()); 1525 if (ShVT != ShWidenVT) 1526 ShOp = ModifyToType(ShOp, ShWidenVT); 1527 1528 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1529} 1530 1531SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) { 1532 // Unary op widening. 1533 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1534 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1535 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp); 1536} 1537 1538SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) { 1539 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1540 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), 1541 cast<VTSDNode>(N->getOperand(1))->getVT() 1542 .getVectorElementType(), 1543 WidenVT.getVectorNumElements()); 1544 SDValue WidenLHS = GetWidenedVector(N->getOperand(0)); 1545 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 1546 WidenVT, WidenLHS, DAG.getValueType(ExtVT)); 1547} 1548 1549SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) { 1550 SDValue InOp = N->getOperand(0); 1551 EVT InVT = InOp.getValueType(); 1552 EVT VT = N->getValueType(0); 1553 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1554 DebugLoc dl = N->getDebugLoc(); 1555 1556 switch (getTypeAction(InVT)) { 1557 default: 1558 assert(false && "Unknown type action!"); 1559 break; 1560 case TargetLowering::TypeLegal: 1561 break; 1562 case TargetLowering::TypePromoteInteger: 1563 // If the InOp is promoted to the same size, convert it. Otherwise, 1564 // fall out of the switch and widen the promoted input. 1565 InOp = GetPromotedInteger(InOp); 1566 InVT = InOp.getValueType(); 1567 if (WidenVT.bitsEq(InVT)) 1568 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1569 break; 1570 case TargetLowering::TypeSoftenFloat: 1571 case TargetLowering::TypeExpandInteger: 1572 case TargetLowering::TypeExpandFloat: 1573 case TargetLowering::TypeScalarizeVector: 1574 case TargetLowering::TypeSplitVector: 1575 break; 1576 case TargetLowering::TypeWidenVector: 1577 // If the InOp is widened to the same size, convert it. Otherwise, fall 1578 // out of the switch and widen the widened input. 1579 InOp = GetWidenedVector(InOp); 1580 InVT = InOp.getValueType(); 1581 if (WidenVT.bitsEq(InVT)) 1582 // The input widens to the same size. Convert to the widen value. 1583 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1584 break; 1585 } 1586 1587 unsigned WidenSize = WidenVT.getSizeInBits(); 1588 unsigned InSize = InVT.getSizeInBits(); 1589 // x86mmx is not an acceptable vector element type, so don't try. 1590 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) { 1591 // Determine new input vector type. The new input vector type will use 1592 // the same element type (if its a vector) or use the input type as a 1593 // vector. It is the same size as the type to widen to. 1594 EVT NewInVT; 1595 unsigned NewNumElts = WidenSize / InSize; 1596 if (InVT.isVector()) { 1597 EVT InEltVT = InVT.getVectorElementType(); 1598 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, 1599 WidenSize / InEltVT.getSizeInBits()); 1600 } else { 1601 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts); 1602 } 1603 1604 if (TLI.isTypeLegal(NewInVT)) { 1605 // Because the result and the input are different vector types, widening 1606 // the result could create a legal type but widening the input might make 1607 // it an illegal type that might lead to repeatedly splitting the input 1608 // and then widening it. To avoid this, we widen the input only if 1609 // it results in a legal type. 1610 SmallVector<SDValue, 16> Ops(NewNumElts); 1611 SDValue UndefVal = DAG.getUNDEF(InVT); 1612 Ops[0] = InOp; 1613 for (unsigned i = 1; i < NewNumElts; ++i) 1614 Ops[i] = UndefVal; 1615 1616 SDValue NewVec; 1617 if (InVT.isVector()) 1618 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1619 NewInVT, &Ops[0], NewNumElts); 1620 else 1621 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, 1622 NewInVT, &Ops[0], NewNumElts); 1623 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec); 1624 } 1625 } 1626 1627 return CreateStackStoreLoad(InOp, WidenVT); 1628} 1629 1630SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) { 1631 DebugLoc dl = N->getDebugLoc(); 1632 // Build a vector with undefined for the new nodes. 1633 EVT VT = N->getValueType(0); 1634 EVT EltVT = VT.getVectorElementType(); 1635 unsigned NumElts = VT.getVectorNumElements(); 1636 1637 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1638 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1639 1640 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end()); 1641 NewOps.reserve(WidenNumElts); 1642 for (unsigned i = NumElts; i < WidenNumElts; ++i) 1643 NewOps.push_back(DAG.getUNDEF(EltVT)); 1644 1645 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size()); 1646} 1647 1648SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) { 1649 EVT InVT = N->getOperand(0).getValueType(); 1650 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1651 DebugLoc dl = N->getDebugLoc(); 1652 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1653 unsigned NumOperands = N->getNumOperands(); 1654 1655 bool InputWidened = false; // Indicates we need to widen the input. 1656 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) { 1657 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) { 1658 // Add undef vectors to widen to correct length. 1659 unsigned NumConcat = WidenVT.getVectorNumElements() / 1660 InVT.getVectorNumElements(); 1661 SDValue UndefVal = DAG.getUNDEF(InVT); 1662 SmallVector<SDValue, 16> Ops(NumConcat); 1663 for (unsigned i=0; i < NumOperands; ++i) 1664 Ops[i] = N->getOperand(i); 1665 for (unsigned i = NumOperands; i != NumConcat; ++i) 1666 Ops[i] = UndefVal; 1667 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat); 1668 } 1669 } else { 1670 InputWidened = true; 1671 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) { 1672 // The inputs and the result are widen to the same value. 1673 unsigned i; 1674 for (i=1; i < NumOperands; ++i) 1675 if (N->getOperand(i).getOpcode() != ISD::UNDEF) 1676 break; 1677 1678 if (i > NumOperands) 1679 // Everything but the first operand is an UNDEF so just return the 1680 // widened first operand. 1681 return GetWidenedVector(N->getOperand(0)); 1682 1683 if (NumOperands == 2) { 1684 // Replace concat of two operands with a shuffle. 1685 SmallVector<int, 16> MaskOps(WidenNumElts); 1686 for (unsigned i=0; i < WidenNumElts/2; ++i) { 1687 MaskOps[i] = i; 1688 MaskOps[i+WidenNumElts/2] = i+WidenNumElts; 1689 } 1690 return DAG.getVectorShuffle(WidenVT, dl, 1691 GetWidenedVector(N->getOperand(0)), 1692 GetWidenedVector(N->getOperand(1)), 1693 &MaskOps[0]); 1694 } 1695 } 1696 } 1697 1698 // Fall back to use extracts and build vector. 1699 EVT EltVT = WidenVT.getVectorElementType(); 1700 unsigned NumInElts = InVT.getVectorNumElements(); 1701 SmallVector<SDValue, 16> Ops(WidenNumElts); 1702 unsigned Idx = 0; 1703 for (unsigned i=0; i < NumOperands; ++i) { 1704 SDValue InOp = N->getOperand(i); 1705 if (InputWidened) 1706 InOp = GetWidenedVector(InOp); 1707 for (unsigned j=0; j < NumInElts; ++j) 1708 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1709 DAG.getIntPtrConstant(j)); 1710 } 1711 SDValue UndefVal = DAG.getUNDEF(EltVT); 1712 for (; Idx < WidenNumElts; ++Idx) 1713 Ops[Idx] = UndefVal; 1714 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1715} 1716 1717SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { 1718 DebugLoc dl = N->getDebugLoc(); 1719 SDValue InOp = N->getOperand(0); 1720 SDValue RndOp = N->getOperand(3); 1721 SDValue SatOp = N->getOperand(4); 1722 1723 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1724 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1725 1726 EVT InVT = InOp.getValueType(); 1727 EVT InEltVT = InVT.getVectorElementType(); 1728 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1729 1730 SDValue DTyOp = DAG.getValueType(WidenVT); 1731 SDValue STyOp = DAG.getValueType(InWidenVT); 1732 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 1733 1734 unsigned InVTNumElts = InVT.getVectorNumElements(); 1735 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1736 InOp = GetWidenedVector(InOp); 1737 InVT = InOp.getValueType(); 1738 InVTNumElts = InVT.getVectorNumElements(); 1739 if (InVTNumElts == WidenNumElts) 1740 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1741 SatOp, CvtCode); 1742 } 1743 1744 if (TLI.isTypeLegal(InWidenVT)) { 1745 // Because the result and the input are different vector types, widening 1746 // the result could create a legal type but widening the input might make 1747 // it an illegal type that might lead to repeatedly splitting the input 1748 // and then widening it. To avoid this, we widen the input only if 1749 // it results in a legal type. 1750 if (WidenNumElts % InVTNumElts == 0) { 1751 // Widen the input and call convert on the widened input vector. 1752 unsigned NumConcat = WidenNumElts/InVTNumElts; 1753 SmallVector<SDValue, 16> Ops(NumConcat); 1754 Ops[0] = InOp; 1755 SDValue UndefVal = DAG.getUNDEF(InVT); 1756 for (unsigned i = 1; i != NumConcat; ++i) 1757 Ops[i] = UndefVal; 1758 1759 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat); 1760 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1761 SatOp, CvtCode); 1762 } 1763 1764 if (InVTNumElts % WidenNumElts == 0) { 1765 // Extract the input and convert the shorten input vector. 1766 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp, 1767 DAG.getIntPtrConstant(0)); 1768 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1769 SatOp, CvtCode); 1770 } 1771 } 1772 1773 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1774 SmallVector<SDValue, 16> Ops(WidenNumElts); 1775 EVT EltVT = WidenVT.getVectorElementType(); 1776 DTyOp = DAG.getValueType(EltVT); 1777 STyOp = DAG.getValueType(InEltVT); 1778 1779 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1780 unsigned i; 1781 for (i=0; i < MinElts; ++i) { 1782 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 1783 DAG.getIntPtrConstant(i)); 1784 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp, 1785 SatOp, CvtCode); 1786 } 1787 1788 SDValue UndefVal = DAG.getUNDEF(EltVT); 1789 for (; i < WidenNumElts; ++i) 1790 Ops[i] = UndefVal; 1791 1792 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1793} 1794 1795SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 1796 EVT VT = N->getValueType(0); 1797 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1798 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1799 SDValue InOp = N->getOperand(0); 1800 SDValue Idx = N->getOperand(1); 1801 DebugLoc dl = N->getDebugLoc(); 1802 1803 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 1804 InOp = GetWidenedVector(InOp); 1805 1806 EVT InVT = InOp.getValueType(); 1807 1808 // Check if we can just return the input vector after widening. 1809 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1810 if (IdxVal == 0 && InVT == WidenVT) 1811 return InOp; 1812 1813 // Check if we can extract from the vector. 1814 unsigned InNumElts = InVT.getVectorNumElements(); 1815 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts) 1816 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx); 1817 1818 // We could try widening the input to the right length but for now, extract 1819 // the original elements, fill the rest with undefs and build a vector. 1820 SmallVector<SDValue, 16> Ops(WidenNumElts); 1821 EVT EltVT = VT.getVectorElementType(); 1822 unsigned NumElts = VT.getVectorNumElements(); 1823 unsigned i; 1824 for (i=0; i < NumElts; ++i) 1825 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1826 DAG.getIntPtrConstant(IdxVal+i)); 1827 1828 SDValue UndefVal = DAG.getUNDEF(EltVT); 1829 for (; i < WidenNumElts; ++i) 1830 Ops[i] = UndefVal; 1831 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1832} 1833 1834SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) { 1835 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1836 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(), 1837 InOp.getValueType(), InOp, 1838 N->getOperand(1), N->getOperand(2)); 1839} 1840 1841SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) { 1842 LoadSDNode *LD = cast<LoadSDNode>(N); 1843 ISD::LoadExtType ExtType = LD->getExtensionType(); 1844 1845 SDValue Result; 1846 SmallVector<SDValue, 16> LdChain; // Chain for the series of load 1847 if (ExtType != ISD::NON_EXTLOAD) 1848 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); 1849 else 1850 Result = GenWidenVectorLoads(LdChain, LD); 1851 1852 // If we generate a single load, we can use that for the chain. Otherwise, 1853 // build a factor node to remember the multiple loads are independent and 1854 // chain to that. 1855 SDValue NewChain; 1856 if (LdChain.size() == 1) 1857 NewChain = LdChain[0]; 1858 else 1859 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other, 1860 &LdChain[0], LdChain.size()); 1861 1862 // Modified the chain - switch anything that used the old chain to use 1863 // the new one. 1864 ReplaceValueWith(SDValue(N, 1), NewChain); 1865 1866 return Result; 1867} 1868 1869SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) { 1870 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1871 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(), 1872 WidenVT, N->getOperand(0)); 1873} 1874 1875SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) { 1876 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1877 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1878 1879 SDValue Cond1 = N->getOperand(0); 1880 EVT CondVT = Cond1.getValueType(); 1881 if (CondVT.isVector()) { 1882 EVT CondEltVT = CondVT.getVectorElementType(); 1883 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), 1884 CondEltVT, WidenNumElts); 1885 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector) 1886 Cond1 = GetWidenedVector(Cond1); 1887 1888 if (Cond1.getValueType() != CondWidenVT) 1889 Cond1 = ModifyToType(Cond1, CondWidenVT); 1890 } 1891 1892 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 1893 SDValue InOp2 = GetWidenedVector(N->getOperand(2)); 1894 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT); 1895 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 1896 WidenVT, Cond1, InOp1, InOp2); 1897} 1898 1899SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) { 1900 SDValue InOp1 = GetWidenedVector(N->getOperand(2)); 1901 SDValue InOp2 = GetWidenedVector(N->getOperand(3)); 1902 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 1903 InOp1.getValueType(), N->getOperand(0), 1904 N->getOperand(1), InOp1, InOp2, N->getOperand(4)); 1905} 1906 1907SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) { 1908 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1909 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1910 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1911 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT, 1912 InOp1, InOp2, N->getOperand(2)); 1913} 1914 1915SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) { 1916 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1917 return DAG.getUNDEF(WidenVT); 1918} 1919 1920SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) { 1921 EVT VT = N->getValueType(0); 1922 DebugLoc dl = N->getDebugLoc(); 1923 1924 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1925 unsigned NumElts = VT.getVectorNumElements(); 1926 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1927 1928 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1929 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1930 1931 // Adjust mask based on new input vector length. 1932 SmallVector<int, 16> NewMask; 1933 for (unsigned i = 0; i != NumElts; ++i) { 1934 int Idx = N->getMaskElt(i); 1935 if (Idx < (int)NumElts) 1936 NewMask.push_back(Idx); 1937 else 1938 NewMask.push_back(Idx - NumElts + WidenNumElts); 1939 } 1940 for (unsigned i = NumElts; i != WidenNumElts; ++i) 1941 NewMask.push_back(-1); 1942 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]); 1943} 1944 1945SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) { 1946 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1947 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1948 1949 SDValue InOp1 = N->getOperand(0); 1950 EVT InVT = InOp1.getValueType(); 1951 assert(InVT.isVector() && "can not widen non vector type"); 1952 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(), 1953 InVT.getVectorElementType(), WidenNumElts); 1954 InOp1 = GetWidenedVector(InOp1); 1955 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1956 1957 // Assume that the input and output will be widen appropriately. If not, 1958 // we will have to unroll it at some point. 1959 assert(InOp1.getValueType() == WidenInVT && 1960 InOp2.getValueType() == WidenInVT && 1961 "Input not widened to expected type!"); 1962 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(), 1963 WidenVT, InOp1, InOp2, N->getOperand(2)); 1964} 1965 1966 1967//===----------------------------------------------------------------------===// 1968// Widen Vector Operand 1969//===----------------------------------------------------------------------===// 1970bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) { 1971 DEBUG(dbgs() << "Widen node operand " << ResNo << ": "; 1972 N->dump(&DAG); 1973 dbgs() << "\n"); 1974 SDValue Res = SDValue(); 1975 1976 switch (N->getOpcode()) { 1977 default: 1978#ifndef NDEBUG 1979 dbgs() << "WidenVectorOperand op #" << ResNo << ": "; 1980 N->dump(&DAG); 1981 dbgs() << "\n"; 1982#endif 1983 llvm_unreachable("Do not know how to widen this operator's operand!"); 1984 1985 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break; 1986 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break; 1987 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break; 1988 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break; 1989 case ISD::STORE: Res = WidenVecOp_STORE(N); break; 1990 1991 case ISD::FP_EXTEND: 1992 case ISD::FP_TO_SINT: 1993 case ISD::FP_TO_UINT: 1994 case ISD::SINT_TO_FP: 1995 case ISD::UINT_TO_FP: 1996 case ISD::TRUNCATE: 1997 case ISD::SIGN_EXTEND: 1998 case ISD::ZERO_EXTEND: 1999 case ISD::ANY_EXTEND: 2000 Res = WidenVecOp_Convert(N); 2001 break; 2002 } 2003 2004 // If Res is null, the sub-method took care of registering the result. 2005 if (!Res.getNode()) return false; 2006 2007 // If the result is N, the sub-method updated N in place. Tell the legalizer 2008 // core about this. 2009 if (Res.getNode() == N) 2010 return true; 2011 2012 2013 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2014 "Invalid operand expansion"); 2015 2016 ReplaceValueWith(SDValue(N, 0), Res); 2017 return false; 2018} 2019 2020SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) { 2021 // Since the result is legal and the input is illegal, it is unlikely 2022 // that we can fix the input to a legal type so unroll the convert 2023 // into some scalar code and create a nasty build vector. 2024 EVT VT = N->getValueType(0); 2025 EVT EltVT = VT.getVectorElementType(); 2026 DebugLoc dl = N->getDebugLoc(); 2027 unsigned NumElts = VT.getVectorNumElements(); 2028 SDValue InOp = N->getOperand(0); 2029 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2030 InOp = GetWidenedVector(InOp); 2031 EVT InVT = InOp.getValueType(); 2032 EVT InEltVT = InVT.getVectorElementType(); 2033 2034 unsigned Opcode = N->getOpcode(); 2035 SmallVector<SDValue, 16> Ops(NumElts); 2036 for (unsigned i=0; i < NumElts; ++i) 2037 Ops[i] = DAG.getNode(Opcode, dl, EltVT, 2038 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 2039 DAG.getIntPtrConstant(i))); 2040 2041 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2042} 2043 2044SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) { 2045 EVT VT = N->getValueType(0); 2046 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2047 EVT InWidenVT = InOp.getValueType(); 2048 DebugLoc dl = N->getDebugLoc(); 2049 2050 // Check if we can convert between two legal vector types and extract. 2051 unsigned InWidenSize = InWidenVT.getSizeInBits(); 2052 unsigned Size = VT.getSizeInBits(); 2053 // x86mmx is not an acceptable vector element type, so don't try. 2054 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) { 2055 unsigned NewNumElts = InWidenSize / Size; 2056 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); 2057 if (TLI.isTypeLegal(NewVT)) { 2058 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp); 2059 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, 2060 DAG.getIntPtrConstant(0)); 2061 } 2062 } 2063 2064 return CreateStackStoreLoad(InOp, VT); 2065} 2066 2067SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) { 2068 // If the input vector is not legal, it is likely that we will not find a 2069 // legal vector of the same size. Replace the concatenate vector with a 2070 // nasty build vector. 2071 EVT VT = N->getValueType(0); 2072 EVT EltVT = VT.getVectorElementType(); 2073 DebugLoc dl = N->getDebugLoc(); 2074 unsigned NumElts = VT.getVectorNumElements(); 2075 SmallVector<SDValue, 16> Ops(NumElts); 2076 2077 EVT InVT = N->getOperand(0).getValueType(); 2078 unsigned NumInElts = InVT.getVectorNumElements(); 2079 2080 unsigned Idx = 0; 2081 unsigned NumOperands = N->getNumOperands(); 2082 for (unsigned i=0; i < NumOperands; ++i) { 2083 SDValue InOp = N->getOperand(i); 2084 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2085 InOp = GetWidenedVector(InOp); 2086 for (unsigned j=0; j < NumInElts; ++j) 2087 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2088 DAG.getIntPtrConstant(j)); 2089 } 2090 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2091} 2092 2093SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 2094 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2095 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), 2096 N->getValueType(0), InOp, N->getOperand(1)); 2097} 2098 2099SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 2100 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2101 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 2102 N->getValueType(0), InOp, N->getOperand(1)); 2103} 2104 2105SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) { 2106 // We have to widen the value but we want only to store the original 2107 // vector type. 2108 StoreSDNode *ST = cast<StoreSDNode>(N); 2109 2110 SmallVector<SDValue, 16> StChain; 2111 if (ST->isTruncatingStore()) 2112 GenWidenVectorTruncStores(StChain, ST); 2113 else 2114 GenWidenVectorStores(StChain, ST); 2115 2116 if (StChain.size() == 1) 2117 return StChain[0]; 2118 else 2119 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(), 2120 MVT::Other,&StChain[0],StChain.size()); 2121} 2122 2123//===----------------------------------------------------------------------===// 2124// Vector Widening Utilities 2125//===----------------------------------------------------------------------===// 2126 2127// Utility function to find the type to chop up a widen vector for load/store 2128// TLI: Target lowering used to determine legal types. 2129// Width: Width left need to load/store. 2130// WidenVT: The widen vector type to load to/store from 2131// Align: If 0, don't allow use of a wider type 2132// WidenEx: If Align is not 0, the amount additional we can load/store from. 2133 2134static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, 2135 unsigned Width, EVT WidenVT, 2136 unsigned Align = 0, unsigned WidenEx = 0) { 2137 EVT WidenEltVT = WidenVT.getVectorElementType(); 2138 unsigned WidenWidth = WidenVT.getSizeInBits(); 2139 unsigned WidenEltWidth = WidenEltVT.getSizeInBits(); 2140 unsigned AlignInBits = Align*8; 2141 2142 // If we have one element to load/store, return it. 2143 EVT RetVT = WidenEltVT; 2144 if (Width == WidenEltWidth) 2145 return RetVT; 2146 2147 // See if there is larger legal integer than the element type to load/store 2148 unsigned VT; 2149 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE; 2150 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) { 2151 EVT MemVT((MVT::SimpleValueType) VT); 2152 unsigned MemVTWidth = MemVT.getSizeInBits(); 2153 if (MemVT.getSizeInBits() <= WidenEltWidth) 2154 break; 2155 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 && 2156 (MemVTWidth <= Width || 2157 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2158 RetVT = MemVT; 2159 break; 2160 } 2161 } 2162 2163 // See if there is a larger vector type to load/store that has the same vector 2164 // element type and is evenly divisible with the WidenVT. 2165 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; 2166 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) { 2167 EVT MemVT = (MVT::SimpleValueType) VT; 2168 unsigned MemVTWidth = MemVT.getSizeInBits(); 2169 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() && 2170 (WidenWidth % MemVTWidth) == 0 && 2171 (MemVTWidth <= Width || 2172 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2173 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT) 2174 return MemVT; 2175 } 2176 } 2177 2178 return RetVT; 2179} 2180 2181// Builds a vector type from scalar loads 2182// VecTy: Resulting Vector type 2183// LDOps: Load operators to build a vector type 2184// [Start,End) the list of loads to use. 2185static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, 2186 SmallVector<SDValue, 16>& LdOps, 2187 unsigned Start, unsigned End) { 2188 DebugLoc dl = LdOps[Start].getDebugLoc(); 2189 EVT LdTy = LdOps[Start].getValueType(); 2190 unsigned Width = VecTy.getSizeInBits(); 2191 unsigned NumElts = Width / LdTy.getSizeInBits(); 2192 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts); 2193 2194 unsigned Idx = 1; 2195 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]); 2196 2197 for (unsigned i = Start + 1; i != End; ++i) { 2198 EVT NewLdTy = LdOps[i].getValueType(); 2199 if (NewLdTy != LdTy) { 2200 NumElts = Width / NewLdTy.getSizeInBits(); 2201 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts); 2202 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp); 2203 // Readjust position and vector position based on new load type 2204 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits(); 2205 LdTy = NewLdTy; 2206 } 2207 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], 2208 DAG.getIntPtrConstant(Idx++)); 2209 } 2210 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp); 2211} 2212 2213SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain, 2214 LoadSDNode *LD) { 2215 // The strategy assumes that we can efficiently load powers of two widths. 2216 // The routines chops the vector into the largest vector loads with the same 2217 // element type or scalar loads and then recombines it to the widen vector 2218 // type. 2219 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2220 unsigned WidenWidth = WidenVT.getSizeInBits(); 2221 EVT LdVT = LD->getMemoryVT(); 2222 DebugLoc dl = LD->getDebugLoc(); 2223 assert(LdVT.isVector() && WidenVT.isVector()); 2224 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType()); 2225 2226 // Load information 2227 SDValue Chain = LD->getChain(); 2228 SDValue BasePtr = LD->getBasePtr(); 2229 unsigned Align = LD->getAlignment(); 2230 bool isVolatile = LD->isVolatile(); 2231 bool isNonTemporal = LD->isNonTemporal(); 2232 2233 int LdWidth = LdVT.getSizeInBits(); 2234 int WidthDiff = WidenWidth - LdWidth; // Difference 2235 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads 2236 2237 // Find the vector type that can load from. 2238 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2239 int NewVTWidth = NewVT.getSizeInBits(); 2240 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(), 2241 isVolatile, isNonTemporal, Align); 2242 LdChain.push_back(LdOp.getValue(1)); 2243 2244 // Check if we can load the element with one instruction 2245 if (LdWidth <= NewVTWidth) { 2246 if (!NewVT.isVector()) { 2247 unsigned NumElts = WidenWidth / NewVTWidth; 2248 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2249 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp); 2250 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp); 2251 } 2252 if (NewVT == WidenVT) 2253 return LdOp; 2254 2255 assert(WidenWidth % NewVTWidth == 0); 2256 unsigned NumConcat = WidenWidth / NewVTWidth; 2257 SmallVector<SDValue, 16> ConcatOps(NumConcat); 2258 SDValue UndefVal = DAG.getUNDEF(NewVT); 2259 ConcatOps[0] = LdOp; 2260 for (unsigned i = 1; i != NumConcat; ++i) 2261 ConcatOps[i] = UndefVal; 2262 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], 2263 NumConcat); 2264 } 2265 2266 // Load vector by using multiple loads from largest vector to scalar 2267 SmallVector<SDValue, 16> LdOps; 2268 LdOps.push_back(LdOp); 2269 2270 LdWidth -= NewVTWidth; 2271 unsigned Offset = 0; 2272 2273 while (LdWidth > 0) { 2274 unsigned Increment = NewVTWidth / 8; 2275 Offset += Increment; 2276 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2277 DAG.getIntPtrConstant(Increment)); 2278 2279 if (LdWidth < NewVTWidth) { 2280 // Our current type we are using is too large, find a better size 2281 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2282 NewVTWidth = NewVT.getSizeInBits(); 2283 } 2284 2285 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, 2286 LD->getPointerInfo().getWithOffset(Offset), 2287 isVolatile, 2288 isNonTemporal, MinAlign(Align, Increment)); 2289 LdChain.push_back(LdOp.getValue(1)); 2290 LdOps.push_back(LdOp); 2291 2292 LdWidth -= NewVTWidth; 2293 } 2294 2295 // Build the vector from the loads operations 2296 unsigned End = LdOps.size(); 2297 if (!LdOps[0].getValueType().isVector()) 2298 // All the loads are scalar loads. 2299 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End); 2300 2301 // If the load contains vectors, build the vector using concat vector. 2302 // All of the vectors used to loads are power of 2 and the scalars load 2303 // can be combined to make a power of 2 vector. 2304 SmallVector<SDValue, 16> ConcatOps(End); 2305 int i = End - 1; 2306 int Idx = End; 2307 EVT LdTy = LdOps[i].getValueType(); 2308 // First combine the scalar loads to a vector 2309 if (!LdTy.isVector()) { 2310 for (--i; i >= 0; --i) { 2311 LdTy = LdOps[i].getValueType(); 2312 if (LdTy.isVector()) 2313 break; 2314 } 2315 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End); 2316 } 2317 ConcatOps[--Idx] = LdOps[i]; 2318 for (--i; i >= 0; --i) { 2319 EVT NewLdTy = LdOps[i].getValueType(); 2320 if (NewLdTy != LdTy) { 2321 // Create a larger vector 2322 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy, 2323 &ConcatOps[Idx], End - Idx); 2324 Idx = End - 1; 2325 LdTy = NewLdTy; 2326 } 2327 ConcatOps[--Idx] = LdOps[i]; 2328 } 2329 2330 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx)) 2331 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, 2332 &ConcatOps[Idx], End - Idx); 2333 2334 // We need to fill the rest with undefs to build the vector 2335 unsigned NumOps = WidenWidth / LdTy.getSizeInBits(); 2336 SmallVector<SDValue, 16> WidenOps(NumOps); 2337 SDValue UndefVal = DAG.getUNDEF(LdTy); 2338 { 2339 unsigned i = 0; 2340 for (; i != End-Idx; ++i) 2341 WidenOps[i] = ConcatOps[Idx+i]; 2342 for (; i != NumOps; ++i) 2343 WidenOps[i] = UndefVal; 2344 } 2345 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps); 2346} 2347 2348SDValue 2349DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain, 2350 LoadSDNode * LD, 2351 ISD::LoadExtType ExtType) { 2352 // For extension loads, it may not be more efficient to chop up the vector 2353 // and then extended it. Instead, we unroll the load and build a new vector. 2354 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2355 EVT LdVT = LD->getMemoryVT(); 2356 DebugLoc dl = LD->getDebugLoc(); 2357 assert(LdVT.isVector() && WidenVT.isVector()); 2358 2359 // Load information 2360 SDValue Chain = LD->getChain(); 2361 SDValue BasePtr = LD->getBasePtr(); 2362 unsigned Align = LD->getAlignment(); 2363 bool isVolatile = LD->isVolatile(); 2364 bool isNonTemporal = LD->isNonTemporal(); 2365 2366 EVT EltVT = WidenVT.getVectorElementType(); 2367 EVT LdEltVT = LdVT.getVectorElementType(); 2368 unsigned NumElts = LdVT.getVectorNumElements(); 2369 2370 // Load each element and widen 2371 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2372 SmallVector<SDValue, 16> Ops(WidenNumElts); 2373 unsigned Increment = LdEltVT.getSizeInBits() / 8; 2374 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, 2375 LD->getPointerInfo(), 2376 LdEltVT, isVolatile, isNonTemporal, Align); 2377 LdChain.push_back(Ops[0].getValue(1)); 2378 unsigned i = 0, Offset = Increment; 2379 for (i=1; i < NumElts; ++i, Offset += Increment) { 2380 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2381 BasePtr, DAG.getIntPtrConstant(Offset)); 2382 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, 2383 LD->getPointerInfo().getWithOffset(Offset), LdEltVT, 2384 isVolatile, isNonTemporal, Align); 2385 LdChain.push_back(Ops[i].getValue(1)); 2386 } 2387 2388 // Fill the rest with undefs 2389 SDValue UndefVal = DAG.getUNDEF(EltVT); 2390 for (; i != WidenNumElts; ++i) 2391 Ops[i] = UndefVal; 2392 2393 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size()); 2394} 2395 2396 2397void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, 2398 StoreSDNode *ST) { 2399 // The strategy assumes that we can efficiently store powers of two widths. 2400 // The routines chops the vector into the largest vector stores with the same 2401 // element type or scalar stores. 2402 SDValue Chain = ST->getChain(); 2403 SDValue BasePtr = ST->getBasePtr(); 2404 unsigned Align = ST->getAlignment(); 2405 bool isVolatile = ST->isVolatile(); 2406 bool isNonTemporal = ST->isNonTemporal(); 2407 SDValue ValOp = GetWidenedVector(ST->getValue()); 2408 DebugLoc dl = ST->getDebugLoc(); 2409 2410 EVT StVT = ST->getMemoryVT(); 2411 unsigned StWidth = StVT.getSizeInBits(); 2412 EVT ValVT = ValOp.getValueType(); 2413 unsigned ValWidth = ValVT.getSizeInBits(); 2414 EVT ValEltVT = ValVT.getVectorElementType(); 2415 unsigned ValEltWidth = ValEltVT.getSizeInBits(); 2416 assert(StVT.getVectorElementType() == ValEltVT); 2417 2418 int Idx = 0; // current index to store 2419 unsigned Offset = 0; // offset from base to store 2420 while (StWidth != 0) { 2421 // Find the largest vector type we can store with 2422 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT); 2423 unsigned NewVTWidth = NewVT.getSizeInBits(); 2424 unsigned Increment = NewVTWidth / 8; 2425 if (NewVT.isVector()) { 2426 unsigned NumVTElts = NewVT.getVectorNumElements(); 2427 do { 2428 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, 2429 DAG.getIntPtrConstant(Idx)); 2430 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2431 ST->getPointerInfo().getWithOffset(Offset), 2432 isVolatile, isNonTemporal, 2433 MinAlign(Align, Offset))); 2434 StWidth -= NewVTWidth; 2435 Offset += Increment; 2436 Idx += NumVTElts; 2437 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2438 DAG.getIntPtrConstant(Increment)); 2439 } while (StWidth != 0 && StWidth >= NewVTWidth); 2440 } else { 2441 // Cast the vector to the scalar type we can store 2442 unsigned NumElts = ValWidth / NewVTWidth; 2443 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2444 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); 2445 // Readjust index position based on new vector type 2446 Idx = Idx * ValEltWidth / NewVTWidth; 2447 do { 2448 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp, 2449 DAG.getIntPtrConstant(Idx++)); 2450 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2451 ST->getPointerInfo().getWithOffset(Offset), 2452 isVolatile, isNonTemporal, 2453 MinAlign(Align, Offset))); 2454 StWidth -= NewVTWidth; 2455 Offset += Increment; 2456 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2457 DAG.getIntPtrConstant(Increment)); 2458 } while (StWidth != 0 && StWidth >= NewVTWidth); 2459 // Restore index back to be relative to the original widen element type 2460 Idx = Idx * NewVTWidth / ValEltWidth; 2461 } 2462 } 2463} 2464 2465void 2466DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain, 2467 StoreSDNode *ST) { 2468 // For extension loads, it may not be more efficient to truncate the vector 2469 // and then store it. Instead, we extract each element and then store it. 2470 SDValue Chain = ST->getChain(); 2471 SDValue BasePtr = ST->getBasePtr(); 2472 unsigned Align = ST->getAlignment(); 2473 bool isVolatile = ST->isVolatile(); 2474 bool isNonTemporal = ST->isNonTemporal(); 2475 SDValue ValOp = GetWidenedVector(ST->getValue()); 2476 DebugLoc dl = ST->getDebugLoc(); 2477 2478 EVT StVT = ST->getMemoryVT(); 2479 EVT ValVT = ValOp.getValueType(); 2480 2481 // It must be true that we the widen vector type is bigger than where 2482 // we need to store. 2483 assert(StVT.isVector() && ValOp.getValueType().isVector()); 2484 assert(StVT.bitsLT(ValOp.getValueType())); 2485 2486 // For truncating stores, we can not play the tricks of chopping legal 2487 // vector types and bit cast it to the right type. Instead, we unroll 2488 // the store. 2489 EVT StEltVT = StVT.getVectorElementType(); 2490 EVT ValEltVT = ValVT.getVectorElementType(); 2491 unsigned Increment = ValEltVT.getSizeInBits() / 8; 2492 unsigned NumElts = StVT.getVectorNumElements(); 2493 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2494 DAG.getIntPtrConstant(0)); 2495 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, 2496 ST->getPointerInfo(), StEltVT, 2497 isVolatile, isNonTemporal, Align)); 2498 unsigned Offset = Increment; 2499 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) { 2500 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2501 BasePtr, DAG.getIntPtrConstant(Offset)); 2502 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2503 DAG.getIntPtrConstant(0)); 2504 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, 2505 ST->getPointerInfo().getWithOffset(Offset), 2506 StEltVT, isVolatile, isNonTemporal, 2507 MinAlign(Align, Offset))); 2508 } 2509} 2510 2511/// Modifies a vector input (widen or narrows) to a vector of NVT. The 2512/// input vector must have the same element type as NVT. 2513SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) { 2514 // Note that InOp might have been widened so it might already have 2515 // the right width or it might need be narrowed. 2516 EVT InVT = InOp.getValueType(); 2517 assert(InVT.getVectorElementType() == NVT.getVectorElementType() && 2518 "input and widen element type must match"); 2519 DebugLoc dl = InOp.getDebugLoc(); 2520 2521 // Check if InOp already has the right width. 2522 if (InVT == NVT) 2523 return InOp; 2524 2525 unsigned InNumElts = InVT.getVectorNumElements(); 2526 unsigned WidenNumElts = NVT.getVectorNumElements(); 2527 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) { 2528 unsigned NumConcat = WidenNumElts / InNumElts; 2529 SmallVector<SDValue, 16> Ops(NumConcat); 2530 SDValue UndefVal = DAG.getUNDEF(InVT); 2531 Ops[0] = InOp; 2532 for (unsigned i = 1; i != NumConcat; ++i) 2533 Ops[i] = UndefVal; 2534 2535 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat); 2536 } 2537 2538 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts) 2539 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp, 2540 DAG.getIntPtrConstant(0)); 2541 2542 // Fall back to extract and build. 2543 SmallVector<SDValue, 16> Ops(WidenNumElts); 2544 EVT EltVT = NVT.getVectorElementType(); 2545 unsigned MinNumElts = std::min(WidenNumElts, InNumElts); 2546 unsigned Idx; 2547 for (Idx = 0; Idx < MinNumElts; ++Idx) 2548 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2549 DAG.getIntPtrConstant(Idx)); 2550 2551 SDValue UndefVal = DAG.getUNDEF(EltVT); 2552 for ( ; Idx < WidenNumElts; ++Idx) 2553 Ops[Idx] = UndefVal; 2554 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts); 2555} 2556