LegalizeVectorTypes.cpp revision a054bcb4cf26f9710bf6b7b256ba7313260a7335
1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file performs vector type splitting and scalarization for LegalizeTypes. 11// Scalarization is the act of changing a computation in an illegal one-element 12// vector type to be a computation in its scalar element type. For example, 13// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed 14// as a base case when scalarizing vector arithmetic like <4 x f32>, which 15// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32 16// types. 17// Splitting is the act of changing a computation in an invalid vector type to 18// be a computation in two vectors of half the size. For example, implementing 19// <128 x f32> operations in terms of two <64 x f32> operations. 20// 21//===----------------------------------------------------------------------===// 22 23#include "LegalizeTypes.h" 24#include "llvm/CodeGen/PseudoSourceValue.h" 25#include "llvm/Target/TargetData.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Support/raw_ostream.h" 28using namespace llvm; 29 30//===----------------------------------------------------------------------===// 31// Result Vector Scalarization: <1 x ty> -> ty. 32//===----------------------------------------------------------------------===// 33 34void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { 35 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; 36 N->dump(&DAG); 37 dbgs() << "\n"); 38 SDValue R = SDValue(); 39 40 switch (N->getOpcode()) { 41 default: 42#ifndef NDEBUG 43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": "; 44 N->dump(&DAG); 45 dbgs() << "\n"; 46#endif 47 report_fatal_error("Do not know how to scalarize the result of this " 48 "operator!\n"); 49 50 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; 51 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 52 case ISD::BUILD_VECTOR: R = N->getOperand(0); break; 53 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; 54 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 55 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; 56 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; 57 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 58 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 59 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; 60 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; 61 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; 62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break; 63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; 65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; 66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; 67 case ISD::ANY_EXTEND: 68 case ISD::CTLZ: 69 case ISD::CTPOP: 70 case ISD::CTTZ: 71 case ISD::FABS: 72 case ISD::FCEIL: 73 case ISD::FCOS: 74 case ISD::FEXP: 75 case ISD::FEXP2: 76 case ISD::FFLOOR: 77 case ISD::FLOG: 78 case ISD::FLOG10: 79 case ISD::FLOG2: 80 case ISD::FNEARBYINT: 81 case ISD::FNEG: 82 case ISD::FP_EXTEND: 83 case ISD::FP_TO_SINT: 84 case ISD::FP_TO_UINT: 85 case ISD::FRINT: 86 case ISD::FSIN: 87 case ISD::FSQRT: 88 case ISD::FTRUNC: 89 case ISD::SIGN_EXTEND: 90 case ISD::SINT_TO_FP: 91 case ISD::TRUNCATE: 92 case ISD::UINT_TO_FP: 93 case ISD::ZERO_EXTEND: 94 R = ScalarizeVecRes_UnaryOp(N); 95 break; 96 97 case ISD::ADD: 98 case ISD::AND: 99 case ISD::FADD: 100 case ISD::FDIV: 101 case ISD::FMUL: 102 case ISD::FPOW: 103 case ISD::FREM: 104 case ISD::FSUB: 105 case ISD::MUL: 106 case ISD::OR: 107 case ISD::SDIV: 108 case ISD::SREM: 109 case ISD::SUB: 110 case ISD::UDIV: 111 case ISD::UREM: 112 case ISD::XOR: 113 case ISD::SHL: 114 case ISD::SRA: 115 case ISD::SRL: 116 R = ScalarizeVecRes_BinOp(N); 117 break; 118 } 119 120 // If R is null, the sub-method took care of registering the result. 121 if (R.getNode()) 122 SetScalarizedVector(SDValue(N, ResNo), R); 123} 124 125SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { 126 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 127 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 128 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 129 LHS.getValueType(), LHS, RHS); 130} 131 132SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N, 133 unsigned ResNo) { 134 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); 135 return GetScalarizedVector(Op); 136} 137 138SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) { 139 EVT NewVT = N->getValueType(0).getVectorElementType(); 140 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 141 NewVT, N->getOperand(0)); 142} 143 144SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) { 145 EVT NewVT = N->getValueType(0).getVectorElementType(); 146 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); 147 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(), 148 Op0, DAG.getValueType(NewVT), 149 DAG.getValueType(Op0.getValueType()), 150 N->getOperand(3), 151 N->getOperand(4), 152 cast<CvtRndSatSDNode>(N)->getCvtCode()); 153} 154 155SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 156 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 157 N->getValueType(0).getVectorElementType(), 158 N->getOperand(0), N->getOperand(1)); 159} 160 161SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) { 162 EVT NewVT = N->getValueType(0).getVectorElementType(); 163 SDValue Op = GetScalarizedVector(N->getOperand(0)); 164 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), 165 NewVT, Op, N->getOperand(1)); 166} 167 168SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) { 169 SDValue Op = GetScalarizedVector(N->getOperand(0)); 170 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(), 171 Op.getValueType(), Op, N->getOperand(1)); 172} 173 174SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { 175 // The value to insert may have a wider type than the vector element type, 176 // so be sure to truncate it to the element type if necessary. 177 SDValue Op = N->getOperand(1); 178 EVT EltVT = N->getValueType(0).getVectorElementType(); 179 if (Op.getValueType() != EltVT) 180 // FIXME: Can this happen for floating point types? 181 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op); 182 return Op; 183} 184 185SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { 186 assert(N->isUnindexed() && "Indexed vector load?"); 187 188 SDValue Result = DAG.getLoad(ISD::UNINDEXED, 189 N->getExtensionType(), 190 N->getValueType(0).getVectorElementType(), 191 N->getDebugLoc(), 192 N->getChain(), N->getBasePtr(), 193 DAG.getUNDEF(N->getBasePtr().getValueType()), 194 N->getPointerInfo(), 195 N->getMemoryVT().getVectorElementType(), 196 N->isVolatile(), N->isNonTemporal(), 197 N->getOriginalAlignment()); 198 199 // Legalized the chain result - switch anything that used the old chain to 200 // use the new one. 201 ReplaceValueWith(SDValue(N, 1), Result.getValue(1)); 202 return Result; 203} 204 205SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { 206 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp. 207 EVT DestVT = N->getValueType(0).getVectorElementType(); 208 SDValue Op = GetScalarizedVector(N->getOperand(0)); 209 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op); 210} 211 212SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) { 213 EVT EltVT = N->getValueType(0).getVectorElementType(); 214 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType(); 215 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 216 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT, 217 LHS, DAG.getValueType(ExtVT)); 218} 219 220SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) { 221 // If the operand is wider than the vector element type then it is implicitly 222 // truncated. Make that explicit here. 223 EVT EltVT = N->getValueType(0).getVectorElementType(); 224 SDValue InOp = N->getOperand(0); 225 if (InOp.getValueType() != EltVT) 226 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp); 227 return InOp; 228} 229 230SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) { 231 SDValue LHS = GetScalarizedVector(N->getOperand(1)); 232 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 233 LHS.getValueType(), N->getOperand(0), LHS, 234 GetScalarizedVector(N->getOperand(2))); 235} 236 237SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) { 238 SDValue LHS = GetScalarizedVector(N->getOperand(2)); 239 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(), 240 N->getOperand(0), N->getOperand(1), 241 LHS, GetScalarizedVector(N->getOperand(3)), 242 N->getOperand(4)); 243} 244 245SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) { 246 assert(N->getValueType(0).isVector() == 247 N->getOperand(0).getValueType().isVector() && 248 "Scalar/Vector type mismatch"); 249 250 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N); 251 252 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 253 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 254 DebugLoc DL = N->getDebugLoc(); 255 256 // Turn it into a scalar SETCC. 257 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); 258} 259 260SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { 261 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 262} 263 264SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { 265 // Figure out if the scalar is the LHS or RHS and return it. 266 SDValue Arg = N->getOperand(2).getOperand(0); 267 if (Arg.getOpcode() == ISD::UNDEF) 268 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 269 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue(); 270 return GetScalarizedVector(N->getOperand(Op)); 271} 272 273SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) { 274 assert(N->getValueType(0).isVector() && 275 N->getOperand(0).getValueType().isVector() && 276 "Operand types must be vectors"); 277 278 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 279 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 280 EVT NVT = N->getValueType(0).getVectorElementType(); 281 DebugLoc DL = N->getDebugLoc(); 282 283 // Turn it into a scalar SETCC. 284 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, 285 N->getOperand(2)); 286 // Vectors may have a different boolean contents to scalars. Promote the 287 // value appropriately. 288 ISD::NodeType ExtendCode = 289 TargetLowering::getExtendForContent(TLI.getBooleanContents(true)); 290 return DAG.getNode(ExtendCode, DL, NVT, Res); 291} 292 293 294//===----------------------------------------------------------------------===// 295// Operand Vector Scalarization <1 x ty> -> ty. 296//===----------------------------------------------------------------------===// 297 298bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { 299 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; 300 N->dump(&DAG); 301 dbgs() << "\n"); 302 SDValue Res = SDValue(); 303 304 if (Res.getNode() == 0) { 305 switch (N->getOpcode()) { 306 default: 307#ifndef NDEBUG 308 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": "; 309 N->dump(&DAG); 310 dbgs() << "\n"; 311#endif 312 llvm_unreachable("Do not know how to scalarize this operator's operand!"); 313 case ISD::BITCAST: 314 Res = ScalarizeVecOp_BITCAST(N); 315 break; 316 case ISD::CONCAT_VECTORS: 317 Res = ScalarizeVecOp_CONCAT_VECTORS(N); 318 break; 319 case ISD::EXTRACT_VECTOR_ELT: 320 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); 321 break; 322 case ISD::STORE: 323 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); 324 break; 325 } 326 } 327 328 // If the result is null, the sub-method took care of registering results etc. 329 if (!Res.getNode()) return false; 330 331 // If the result is N, the sub-method updated N in place. Tell the legalizer 332 // core about this. 333 if (Res.getNode() == N) 334 return true; 335 336 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 337 "Invalid operand expansion"); 338 339 ReplaceValueWith(SDValue(N, 0), Res); 340 return false; 341} 342 343/// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs 344/// to be scalarized, it must be <1 x ty>. Convert the element instead. 345SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) { 346 SDValue Elt = GetScalarizedVector(N->getOperand(0)); 347 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 348 N->getValueType(0), Elt); 349} 350 351/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one - 352/// use a BUILD_VECTOR instead. 353SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) { 354 SmallVector<SDValue, 8> Ops(N->getNumOperands()); 355 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 356 Ops[i] = GetScalarizedVector(N->getOperand(i)); 357 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0), 358 &Ops[0], Ops.size()); 359} 360 361/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to 362/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the 363/// index. 364SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 365 SDValue Res = GetScalarizedVector(N->getOperand(0)); 366 if (Res.getValueType() != N->getValueType(0)) 367 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), 368 Res); 369 return Res; 370} 371 372/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be 373/// scalarized, it must be <1 x ty>. Just store the element. 374SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ 375 assert(N->isUnindexed() && "Indexed store of one-element vector?"); 376 assert(OpNo == 1 && "Do not know how to scalarize this operand!"); 377 DebugLoc dl = N->getDebugLoc(); 378 379 if (N->isTruncatingStore()) 380 return DAG.getTruncStore(N->getChain(), dl, 381 GetScalarizedVector(N->getOperand(1)), 382 N->getBasePtr(), N->getPointerInfo(), 383 N->getMemoryVT().getVectorElementType(), 384 N->isVolatile(), N->isNonTemporal(), 385 N->getAlignment()); 386 387 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)), 388 N->getBasePtr(), N->getPointerInfo(), 389 N->isVolatile(), N->isNonTemporal(), 390 N->getOriginalAlignment()); 391} 392 393 394//===----------------------------------------------------------------------===// 395// Result Vector Splitting 396//===----------------------------------------------------------------------===// 397 398/// SplitVectorResult - This method is called when the specified result of the 399/// specified node is found to need vector splitting. At this point, the node 400/// may also have invalid operands or may have other results that need 401/// legalization, we just know that (at least) one result needs vector 402/// splitting. 403void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { 404 DEBUG(dbgs() << "Split node result: "; 405 N->dump(&DAG); 406 dbgs() << "\n"); 407 SDValue Lo, Hi; 408 409 switch (N->getOpcode()) { 410 default: 411#ifndef NDEBUG 412 dbgs() << "SplitVectorResult #" << ResNo << ": "; 413 N->dump(&DAG); 414 dbgs() << "\n"; 415#endif 416 llvm_unreachable("Do not know how to split the result of this operator!"); 417 418 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 419 case ISD::VSELECT: 420 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 421 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 422 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 423 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; 424 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 425 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 426 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; 427 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 428 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; 429 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 430 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break; 431 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 432 case ISD::LOAD: 433 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); 434 break; 435 case ISD::SETCC: 436 SplitVecRes_SETCC(N, Lo, Hi); 437 break; 438 case ISD::VECTOR_SHUFFLE: 439 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); 440 break; 441 442 case ISD::ANY_EXTEND: 443 case ISD::CONVERT_RNDSAT: 444 case ISD::CTLZ: 445 case ISD::CTPOP: 446 case ISD::CTTZ: 447 case ISD::FABS: 448 case ISD::FCEIL: 449 case ISD::FCOS: 450 case ISD::FEXP: 451 case ISD::FEXP2: 452 case ISD::FFLOOR: 453 case ISD::FLOG: 454 case ISD::FLOG10: 455 case ISD::FLOG2: 456 case ISD::FNEARBYINT: 457 case ISD::FNEG: 458 case ISD::FP_EXTEND: 459 case ISD::FP_ROUND: 460 case ISD::FP_TO_SINT: 461 case ISD::FP_TO_UINT: 462 case ISD::FRINT: 463 case ISD::FSIN: 464 case ISD::FSQRT: 465 case ISD::FTRUNC: 466 case ISD::SIGN_EXTEND: 467 case ISD::SINT_TO_FP: 468 case ISD::TRUNCATE: 469 case ISD::UINT_TO_FP: 470 case ISD::ZERO_EXTEND: 471 SplitVecRes_UnaryOp(N, Lo, Hi); 472 break; 473 474 case ISD::ADD: 475 case ISD::SUB: 476 case ISD::MUL: 477 case ISD::FADD: 478 case ISD::FSUB: 479 case ISD::FMUL: 480 case ISD::SDIV: 481 case ISD::UDIV: 482 case ISD::FDIV: 483 case ISD::FPOW: 484 case ISD::AND: 485 case ISD::OR: 486 case ISD::XOR: 487 case ISD::SHL: 488 case ISD::SRA: 489 case ISD::SRL: 490 case ISD::UREM: 491 case ISD::SREM: 492 case ISD::FREM: 493 SplitVecRes_BinOp(N, Lo, Hi); 494 break; 495 } 496 497 // If Lo/Hi is null, the sub-method took care of registering results etc. 498 if (Lo.getNode()) 499 SetSplitVector(SDValue(N, ResNo), Lo, Hi); 500} 501 502void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo, 503 SDValue &Hi) { 504 SDValue LHSLo, LHSHi; 505 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 506 SDValue RHSLo, RHSHi; 507 GetSplitVector(N->getOperand(1), RHSLo, RHSHi); 508 DebugLoc dl = N->getDebugLoc(); 509 510 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo); 511 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi); 512} 513 514void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, 515 SDValue &Hi) { 516 // We know the result is a vector. The input may be either a vector or a 517 // scalar value. 518 EVT LoVT, HiVT; 519 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 520 DebugLoc dl = N->getDebugLoc(); 521 522 SDValue InOp = N->getOperand(0); 523 EVT InVT = InOp.getValueType(); 524 525 // Handle some special cases efficiently. 526 switch (getTypeAction(InVT)) { 527 case TargetLowering::TypeLegal: 528 case TargetLowering::TypePromoteInteger: 529 case TargetLowering::TypeSoftenFloat: 530 case TargetLowering::TypeScalarizeVector: 531 case TargetLowering::TypeWidenVector: 532 break; 533 case TargetLowering::TypeExpandInteger: 534 case TargetLowering::TypeExpandFloat: 535 // A scalar to vector conversion, where the scalar needs expansion. 536 // If the vector is being split in two then we can just convert the 537 // expanded pieces. 538 if (LoVT == HiVT) { 539 GetExpandedOp(InOp, Lo, Hi); 540 if (TLI.isBigEndian()) 541 std::swap(Lo, Hi); 542 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 543 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 544 return; 545 } 546 break; 547 case TargetLowering::TypeSplitVector: 548 // If the input is a vector that needs to be split, convert each split 549 // piece of the input now. 550 GetSplitVector(InOp, Lo, Hi); 551 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 552 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 553 return; 554 } 555 556 // In the general case, convert the input to an integer and split it by hand. 557 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits()); 558 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits()); 559 if (TLI.isBigEndian()) 560 std::swap(LoIntVT, HiIntVT); 561 562 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); 563 564 if (TLI.isBigEndian()) 565 std::swap(Lo, Hi); 566 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 567 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 568} 569 570void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, 571 SDValue &Hi) { 572 EVT LoVT, HiVT; 573 DebugLoc dl = N->getDebugLoc(); 574 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 575 unsigned LoNumElts = LoVT.getVectorNumElements(); 576 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts); 577 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size()); 578 579 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end()); 580 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size()); 581} 582 583void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, 584 SDValue &Hi) { 585 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"); 586 DebugLoc dl = N->getDebugLoc(); 587 unsigned NumSubvectors = N->getNumOperands() / 2; 588 if (NumSubvectors == 1) { 589 Lo = N->getOperand(0); 590 Hi = N->getOperand(1); 591 return; 592 } 593 594 EVT LoVT, HiVT; 595 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 596 597 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); 598 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size()); 599 600 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end()); 601 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size()); 602} 603 604void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, 605 SDValue &Hi) { 606 SDValue Vec = N->getOperand(0); 607 SDValue Idx = N->getOperand(1); 608 DebugLoc dl = N->getDebugLoc(); 609 610 EVT LoVT, HiVT; 611 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 612 613 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); 614 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 615 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, 616 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements())); 617} 618 619void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, 620 SDValue &Hi) { 621 DebugLoc dl = N->getDebugLoc(); 622 GetSplitVector(N->getOperand(0), Lo, Hi); 623 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1)); 624 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1)); 625} 626 627void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo, 628 SDValue &Hi) { 629 SDValue LHSLo, LHSHi; 630 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 631 DebugLoc dl = N->getDebugLoc(); 632 633 EVT LoVT, HiVT; 634 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT); 635 636 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, 637 DAG.getValueType(LoVT)); 638 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, 639 DAG.getValueType(HiVT)); 640} 641 642void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, 643 SDValue &Hi) { 644 SDValue Vec = N->getOperand(0); 645 SDValue Elt = N->getOperand(1); 646 SDValue Idx = N->getOperand(2); 647 DebugLoc dl = N->getDebugLoc(); 648 GetSplitVector(Vec, Lo, Hi); 649 650 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 651 unsigned IdxVal = CIdx->getZExtValue(); 652 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 653 if (IdxVal < LoNumElts) 654 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 655 Lo.getValueType(), Lo, Elt, Idx); 656 else 657 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, 658 DAG.getIntPtrConstant(IdxVal - LoNumElts)); 659 return; 660 } 661 662 // Spill the vector to the stack. 663 EVT VecVT = Vec.getValueType(); 664 EVT EltVT = VecVT.getVectorElementType(); 665 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 666 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 667 MachinePointerInfo(), false, false, 0); 668 669 // Store the new element. This may be larger than the vector element type, 670 // so use a truncating store. 671 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 672 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); 673 unsigned Alignment = 674 TLI.getTargetData()->getPrefTypeAlignment(VecType); 675 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT, 676 false, false, 0); 677 678 // Load the Lo part from the stack slot. 679 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 680 false, false, 0); 681 682 // Increment the pointer to the other part. 683 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; 684 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 685 DAG.getIntPtrConstant(IncrementSize)); 686 687 // Load the Hi part from the stack slot. 688 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 689 false, false, MinAlign(Alignment, IncrementSize)); 690} 691 692void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, 693 SDValue &Hi) { 694 EVT LoVT, HiVT; 695 DebugLoc dl = N->getDebugLoc(); 696 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 697 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0)); 698 Hi = DAG.getUNDEF(HiVT); 699} 700 701void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, 702 SDValue &Hi) { 703 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"); 704 EVT LoVT, HiVT; 705 DebugLoc dl = LD->getDebugLoc(); 706 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); 707 708 ISD::LoadExtType ExtType = LD->getExtensionType(); 709 SDValue Ch = LD->getChain(); 710 SDValue Ptr = LD->getBasePtr(); 711 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 712 EVT MemoryVT = LD->getMemoryVT(); 713 unsigned Alignment = LD->getOriginalAlignment(); 714 bool isVolatile = LD->isVolatile(); 715 bool isNonTemporal = LD->isNonTemporal(); 716 717 EVT LoMemVT, HiMemVT; 718 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 719 720 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, 721 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal, 722 Alignment); 723 724 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 725 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 726 DAG.getIntPtrConstant(IncrementSize)); 727 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, 728 LD->getPointerInfo().getWithOffset(IncrementSize), 729 HiMemVT, isVolatile, isNonTemporal, Alignment); 730 731 // Build a factor node to remember that this load is independent of the 732 // other one. 733 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 734 Hi.getValue(1)); 735 736 // Legalized the chain result - switch anything that used the old chain to 737 // use the new one. 738 ReplaceValueWith(SDValue(LD, 1), Ch); 739} 740 741void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) { 742 assert(N->getValueType(0).isVector() && 743 N->getOperand(0).getValueType().isVector() && 744 "Operand types must be vectors"); 745 746 EVT LoVT, HiVT; 747 DebugLoc DL = N->getDebugLoc(); 748 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 749 750 // Split the input. 751 EVT InVT = N->getOperand(0).getValueType(); 752 SDValue LL, LH, RL, RH; 753 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 754 LoVT.getVectorNumElements()); 755 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 756 DAG.getIntPtrConstant(0)); 757 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 758 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 759 760 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 761 DAG.getIntPtrConstant(0)); 762 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 763 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 764 765 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2)); 766 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2)); 767} 768 769void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, 770 SDValue &Hi) { 771 // Get the dest types - they may not match the input types, e.g. int_to_fp. 772 EVT LoVT, HiVT; 773 DebugLoc dl = N->getDebugLoc(); 774 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 775 776 // Split the input. 777 EVT InVT = N->getOperand(0).getValueType(); 778 switch (getTypeAction(InVT)) { 779 default: llvm_unreachable("Unexpected type action!"); 780 case TargetLowering::TypeLegal: { 781 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 782 LoVT.getVectorNumElements()); 783 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 784 DAG.getIntPtrConstant(0)); 785 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 786 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 787 break; 788 } 789 case TargetLowering::TypePromoteInteger: { 790 SDValue InOp; 791 if (N->getOpcode() == ISD::SIGN_EXTEND || 792 N->getOpcode() == ISD::SINT_TO_FP) { 793 InOp = SExtPromotedInteger(N->getOperand(0)); 794 } else if ( 795 N->getOpcode() == ISD::ZERO_EXTEND || 796 N->getOpcode() == ISD::UINT_TO_FP) { 797 InOp = ZExtPromotedInteger(N->getOperand(0)); 798 } else { 799 InOp = GetPromotedInteger(N->getOperand(0)); 800 } 801 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), 802 InOp.getValueType().getVectorElementType(), 803 LoVT.getVectorNumElements()); 804 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 805 DAG.getIntPtrConstant(0)); 806 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 807 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 808 break; 809 } 810 case TargetLowering::TypeSplitVector: 811 GetSplitVector(N->getOperand(0), Lo, Hi); 812 break; 813 case TargetLowering::TypeWidenVector: { 814 // If the result needs to be split and the input needs to be widened, 815 // the two types must have different lengths. Use the widened result 816 // and extract from it to do the split. 817 SDValue InOp = GetWidenedVector(N->getOperand(0)); 818 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 819 LoVT.getVectorNumElements()); 820 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 821 DAG.getIntPtrConstant(0)); 822 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 823 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 824 break; 825 } 826 } 827 828 if (N->getOpcode() == ISD::FP_ROUND) { 829 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1)); 830 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1)); 831 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) { 832 SDValue DTyOpLo = DAG.getValueType(LoVT); 833 SDValue DTyOpHi = DAG.getValueType(HiVT); 834 SDValue STyOpLo = DAG.getValueType(Lo.getValueType()); 835 SDValue STyOpHi = DAG.getValueType(Hi.getValueType()); 836 SDValue RndOp = N->getOperand(3); 837 SDValue SatOp = N->getOperand(4); 838 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 839 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp, 840 CvtCode); 841 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp, 842 CvtCode); 843 } else { 844 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo); 845 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi); 846 } 847} 848 849void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, 850 SDValue &Lo, SDValue &Hi) { 851 // The low and high parts of the original input give four input vectors. 852 SDValue Inputs[4]; 853 DebugLoc dl = N->getDebugLoc(); 854 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]); 855 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]); 856 EVT NewVT = Inputs[0].getValueType(); 857 unsigned NewElts = NewVT.getVectorNumElements(); 858 859 // If Lo or Hi uses elements from at most two of the four input vectors, then 860 // express it as a vector shuffle of those two inputs. Otherwise extract the 861 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. 862 SmallVector<int, 16> Ops; 863 for (unsigned High = 0; High < 2; ++High) { 864 SDValue &Output = High ? Hi : Lo; 865 866 // Build a shuffle mask for the output, discovering on the fly which 867 // input vectors to use as shuffle operands (recorded in InputUsed). 868 // If building a suitable shuffle vector proves too hard, then bail 869 // out with useBuildVector set. 870 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered. 871 unsigned FirstMaskIdx = High * NewElts; 872 bool useBuildVector = false; 873 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 874 // The mask element. This indexes into the input. 875 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 876 877 // The input vector this mask element indexes into. 878 unsigned Input = (unsigned)Idx / NewElts; 879 880 if (Input >= array_lengthof(Inputs)) { 881 // The mask element does not index into any input vector. 882 Ops.push_back(-1); 883 continue; 884 } 885 886 // Turn the index into an offset from the start of the input vector. 887 Idx -= Input * NewElts; 888 889 // Find or create a shuffle vector operand to hold this input. 890 unsigned OpNo; 891 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 892 if (InputUsed[OpNo] == Input) { 893 // This input vector is already an operand. 894 break; 895 } else if (InputUsed[OpNo] == -1U) { 896 // Create a new operand for this input vector. 897 InputUsed[OpNo] = Input; 898 break; 899 } 900 } 901 902 if (OpNo >= array_lengthof(InputUsed)) { 903 // More than two input vectors used! Give up on trying to create a 904 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 905 useBuildVector = true; 906 break; 907 } 908 909 // Add the mask index for the new shuffle vector. 910 Ops.push_back(Idx + OpNo * NewElts); 911 } 912 913 if (useBuildVector) { 914 EVT EltVT = NewVT.getVectorElementType(); 915 SmallVector<SDValue, 16> SVOps; 916 917 // Extract the input elements by hand. 918 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 919 // The mask element. This indexes into the input. 920 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 921 922 // The input vector this mask element indexes into. 923 unsigned Input = (unsigned)Idx / NewElts; 924 925 if (Input >= array_lengthof(Inputs)) { 926 // The mask element is "undef" or indexes off the end of the input. 927 SVOps.push_back(DAG.getUNDEF(EltVT)); 928 continue; 929 } 930 931 // Turn the index into an offset from the start of the input vector. 932 Idx -= Input * NewElts; 933 934 // Extract the vector element by hand. 935 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 936 Inputs[Input], DAG.getIntPtrConstant(Idx))); 937 } 938 939 // Construct the Lo/Hi output using a BUILD_VECTOR. 940 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size()); 941 } else if (InputUsed[0] == -1U) { 942 // No input vectors were used! The result is undefined. 943 Output = DAG.getUNDEF(NewVT); 944 } else { 945 SDValue Op0 = Inputs[InputUsed[0]]; 946 // If only one input was used, use an undefined vector for the other. 947 SDValue Op1 = InputUsed[1] == -1U ? 948 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]]; 949 // At least one input vector was used. Create a new shuffle vector. 950 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]); 951 } 952 953 Ops.clear(); 954 } 955} 956 957 958//===----------------------------------------------------------------------===// 959// Operand Vector Splitting 960//===----------------------------------------------------------------------===// 961 962/// SplitVectorOperand - This method is called when the specified operand of the 963/// specified node is found to need vector splitting. At this point, all of the 964/// result types of the node are known to be legal, but other operands of the 965/// node may need legalization as well as the specified one. 966bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { 967 DEBUG(dbgs() << "Split node operand: "; 968 N->dump(&DAG); 969 dbgs() << "\n"); 970 SDValue Res = SDValue(); 971 972 if (Res.getNode() == 0) { 973 switch (N->getOpcode()) { 974 default: 975#ifndef NDEBUG 976 dbgs() << "SplitVectorOperand Op #" << OpNo << ": "; 977 N->dump(&DAG); 978 dbgs() << "\n"; 979#endif 980 llvm_unreachable("Do not know how to split this operator's operand!"); 981 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; 982 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break; 983 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; 984 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; 985 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; 986 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; 987 case ISD::STORE: 988 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo); 989 break; 990 991 case ISD::CTTZ: 992 case ISD::CTLZ: 993 case ISD::CTPOP: 994 case ISD::FP_EXTEND: 995 case ISD::FP_TO_SINT: 996 case ISD::FP_TO_UINT: 997 case ISD::SINT_TO_FP: 998 case ISD::UINT_TO_FP: 999 case ISD::FTRUNC: 1000 case ISD::TRUNCATE: 1001 case ISD::SIGN_EXTEND: 1002 case ISD::ZERO_EXTEND: 1003 case ISD::ANY_EXTEND: 1004 Res = SplitVecOp_UnaryOp(N); 1005 break; 1006 } 1007 } 1008 1009 // If the result is null, the sub-method took care of registering results etc. 1010 if (!Res.getNode()) return false; 1011 1012 // If the result is N, the sub-method updated N in place. Tell the legalizer 1013 // core about this. 1014 if (Res.getNode() == N) 1015 return true; 1016 1017 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1018 "Invalid operand expansion"); 1019 1020 ReplaceValueWith(SDValue(N, 0), Res); 1021 return false; 1022} 1023 1024SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) { 1025 // The result has a legal vector type, but the input needs splitting. 1026 EVT ResVT = N->getValueType(0); 1027 SDValue Lo, Hi; 1028 DebugLoc dl = N->getDebugLoc(); 1029 GetSplitVector(N->getOperand(0), Lo, Hi); 1030 EVT InVT = Lo.getValueType(); 1031 1032 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1033 InVT.getVectorNumElements()); 1034 1035 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); 1036 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); 1037 1038 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); 1039} 1040 1041SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) { 1042 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will 1043 // end up being split all the way down to individual components. Convert the 1044 // split pieces into integers and reassemble. 1045 SDValue Lo, Hi; 1046 GetSplitVector(N->getOperand(0), Lo, Hi); 1047 Lo = BitConvertToInteger(Lo); 1048 Hi = BitConvertToInteger(Hi); 1049 1050 if (TLI.isBigEndian()) 1051 std::swap(Lo, Hi); 1052 1053 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0), 1054 JoinIntegers(Lo, Hi)); 1055} 1056 1057SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 1058 // We know that the extracted result type is legal. 1059 EVT SubVT = N->getValueType(0); 1060 SDValue Idx = N->getOperand(1); 1061 DebugLoc dl = N->getDebugLoc(); 1062 SDValue Lo, Hi; 1063 GetSplitVector(N->getOperand(0), Lo, Hi); 1064 1065 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1066 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1067 1068 if (IdxVal < LoElts) { 1069 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && 1070 "Extracted subvector crosses vector split!"); 1071 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); 1072 } else { 1073 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, 1074 DAG.getConstant(IdxVal - LoElts, Idx.getValueType())); 1075 } 1076} 1077 1078SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 1079 SDValue Vec = N->getOperand(0); 1080 SDValue Idx = N->getOperand(1); 1081 EVT VecVT = Vec.getValueType(); 1082 1083 if (isa<ConstantSDNode>(Idx)) { 1084 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1085 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); 1086 1087 SDValue Lo, Hi; 1088 GetSplitVector(Vec, Lo, Hi); 1089 1090 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1091 1092 if (IdxVal < LoElts) 1093 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0); 1094 return SDValue(DAG.UpdateNodeOperands(N, Hi, 1095 DAG.getConstant(IdxVal - LoElts, 1096 Idx.getValueType())), 0); 1097 } 1098 1099 // Store the vector to the stack. 1100 EVT EltVT = VecVT.getVectorElementType(); 1101 DebugLoc dl = N->getDebugLoc(); 1102 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 1103 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 1104 MachinePointerInfo(), false, false, 0); 1105 1106 // Load back the required element. 1107 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 1108 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, 1109 MachinePointerInfo(), EltVT, false, false, 0); 1110} 1111 1112SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { 1113 assert(N->isUnindexed() && "Indexed store of vector?"); 1114 assert(OpNo == 1 && "Can only split the stored value"); 1115 DebugLoc DL = N->getDebugLoc(); 1116 1117 bool isTruncating = N->isTruncatingStore(); 1118 SDValue Ch = N->getChain(); 1119 SDValue Ptr = N->getBasePtr(); 1120 EVT MemoryVT = N->getMemoryVT(); 1121 unsigned Alignment = N->getOriginalAlignment(); 1122 bool isVol = N->isVolatile(); 1123 bool isNT = N->isNonTemporal(); 1124 SDValue Lo, Hi; 1125 GetSplitVector(N->getOperand(1), Lo, Hi); 1126 1127 EVT LoMemVT, HiMemVT; 1128 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 1129 1130 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 1131 1132 if (isTruncating) 1133 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1134 LoMemVT, isVol, isNT, Alignment); 1135 else 1136 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1137 isVol, isNT, Alignment); 1138 1139 // Increment the pointer to the other half. 1140 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, 1141 DAG.getIntPtrConstant(IncrementSize)); 1142 1143 if (isTruncating) 1144 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr, 1145 N->getPointerInfo().getWithOffset(IncrementSize), 1146 HiMemVT, isVol, isNT, Alignment); 1147 else 1148 Hi = DAG.getStore(Ch, DL, Hi, Ptr, 1149 N->getPointerInfo().getWithOffset(IncrementSize), 1150 isVol, isNT, Alignment); 1151 1152 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi); 1153} 1154 1155SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) { 1156 DebugLoc DL = N->getDebugLoc(); 1157 1158 // The input operands all must have the same type, and we know the result the 1159 // result type is valid. Convert this to a buildvector which extracts all the 1160 // input elements. 1161 // TODO: If the input elements are power-two vectors, we could convert this to 1162 // a new CONCAT_VECTORS node with elements that are half-wide. 1163 SmallVector<SDValue, 32> Elts; 1164 EVT EltVT = N->getValueType(0).getVectorElementType(); 1165 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1166 SDValue Op = N->getOperand(op); 1167 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements(); 1168 i != e; ++i) { 1169 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, 1170 Op, DAG.getIntPtrConstant(i))); 1171 1172 } 1173 } 1174 1175 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), 1176 &Elts[0], Elts.size()); 1177} 1178 1179SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { 1180 assert(N->getValueType(0).isVector() && 1181 N->getOperand(0).getValueType().isVector() && 1182 "Operand types must be vectors"); 1183 // The result has a legal vector type, but the input needs splitting. 1184 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes; 1185 DebugLoc DL = N->getDebugLoc(); 1186 GetSplitVector(N->getOperand(0), Lo0, Hi0); 1187 GetSplitVector(N->getOperand(1), Lo1, Hi1); 1188 unsigned PartElements = Lo0.getValueType().getVectorNumElements(); 1189 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements); 1190 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements); 1191 1192 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); 1193 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); 1194 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes); 1195 return PromoteTargetBoolean(Con, N->getValueType(0)); 1196} 1197 1198 1199SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) { 1200 // The result has a legal vector type, but the input needs splitting. 1201 EVT ResVT = N->getValueType(0); 1202 SDValue Lo, Hi; 1203 DebugLoc DL = N->getDebugLoc(); 1204 GetSplitVector(N->getOperand(0), Lo, Hi); 1205 EVT InVT = Lo.getValueType(); 1206 1207 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1208 InVT.getVectorNumElements()); 1209 1210 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); 1211 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); 1212 1213 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); 1214} 1215 1216 1217 1218//===----------------------------------------------------------------------===// 1219// Result Vector Widening 1220//===----------------------------------------------------------------------===// 1221 1222void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { 1223 DEBUG(dbgs() << "Widen node result " << ResNo << ": "; 1224 N->dump(&DAG); 1225 dbgs() << "\n"); 1226 1227 // See if the target wants to custom widen this node. 1228 if (CustomWidenLowerNode(N, N->getValueType(ResNo))) 1229 return; 1230 1231 SDValue Res = SDValue(); 1232 switch (N->getOpcode()) { 1233 default: 1234#ifndef NDEBUG 1235 dbgs() << "WidenVectorResult #" << ResNo << ": "; 1236 N->dump(&DAG); 1237 dbgs() << "\n"; 1238#endif 1239 llvm_unreachable("Do not know how to widen the result of this operator!"); 1240 1241 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break; 1242 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break; 1243 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; 1244 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break; 1245 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break; 1246 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; 1247 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break; 1248 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; 1249 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break; 1250 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break; 1251 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break; 1252 case ISD::VSELECT: 1253 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break; 1254 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; 1255 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; 1256 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break; 1257 case ISD::VECTOR_SHUFFLE: 1258 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N)); 1259 break; 1260 case ISD::ADD: 1261 case ISD::AND: 1262 case ISD::BSWAP: 1263 case ISD::FADD: 1264 case ISD::FCOPYSIGN: 1265 case ISD::FDIV: 1266 case ISD::FMUL: 1267 case ISD::FPOW: 1268 case ISD::FREM: 1269 case ISD::FSUB: 1270 case ISD::MUL: 1271 case ISD::MULHS: 1272 case ISD::MULHU: 1273 case ISD::OR: 1274 case ISD::SDIV: 1275 case ISD::SREM: 1276 case ISD::UDIV: 1277 case ISD::UREM: 1278 case ISD::SUB: 1279 case ISD::XOR: 1280 Res = WidenVecRes_Binary(N); 1281 break; 1282 1283 case ISD::FPOWI: 1284 Res = WidenVecRes_POWI(N); 1285 break; 1286 1287 case ISD::SHL: 1288 case ISD::SRA: 1289 case ISD::SRL: 1290 Res = WidenVecRes_Shift(N); 1291 break; 1292 1293 case ISD::ANY_EXTEND: 1294 case ISD::FP_EXTEND: 1295 case ISD::FP_ROUND: 1296 case ISD::FP_TO_SINT: 1297 case ISD::FP_TO_UINT: 1298 case ISD::SIGN_EXTEND: 1299 case ISD::SINT_TO_FP: 1300 case ISD::TRUNCATE: 1301 case ISD::UINT_TO_FP: 1302 case ISD::ZERO_EXTEND: 1303 Res = WidenVecRes_Convert(N); 1304 break; 1305 1306 case ISD::CTLZ: 1307 case ISD::CTPOP: 1308 case ISD::CTTZ: 1309 case ISD::FABS: 1310 case ISD::FCEIL: 1311 case ISD::FCOS: 1312 case ISD::FEXP: 1313 case ISD::FEXP2: 1314 case ISD::FFLOOR: 1315 case ISD::FLOG: 1316 case ISD::FLOG10: 1317 case ISD::FLOG2: 1318 case ISD::FNEARBYINT: 1319 case ISD::FNEG: 1320 case ISD::FRINT: 1321 case ISD::FSIN: 1322 case ISD::FSQRT: 1323 case ISD::FTRUNC: 1324 Res = WidenVecRes_Unary(N); 1325 break; 1326 } 1327 1328 // If Res is null, the sub-method took care of registering the result. 1329 if (Res.getNode()) 1330 SetWidenedVector(SDValue(N, ResNo), Res); 1331} 1332 1333SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) { 1334 // Binary op widening. 1335 unsigned Opcode = N->getOpcode(); 1336 DebugLoc dl = N->getDebugLoc(); 1337 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1338 EVT WidenEltVT = WidenVT.getVectorElementType(); 1339 EVT VT = WidenVT; 1340 unsigned NumElts = VT.getVectorNumElements(); 1341 while (!TLI.isTypeLegal(VT) && NumElts != 1) { 1342 NumElts = NumElts / 2; 1343 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1344 } 1345 1346 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) { 1347 // Operation doesn't trap so just widen as normal. 1348 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1349 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1350 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2); 1351 } 1352 1353 // No legal vector version so unroll the vector operation and then widen. 1354 if (NumElts == 1) 1355 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()); 1356 1357 // Since the operation can trap, apply operation on the original vector. 1358 EVT MaxVT = VT; 1359 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1360 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1361 unsigned CurNumElts = N->getValueType(0).getVectorNumElements(); 1362 1363 SmallVector<SDValue, 16> ConcatOps(CurNumElts); 1364 unsigned ConcatEnd = 0; // Current ConcatOps index. 1365 int Idx = 0; // Current Idx into input vectors. 1366 1367 // NumElts := greatest legal vector size (at most WidenVT) 1368 // while (orig. vector has unhandled elements) { 1369 // take munches of size NumElts from the beginning and add to ConcatOps 1370 // NumElts := next smaller supported vector size or 1 1371 // } 1372 while (CurNumElts != 0) { 1373 while (CurNumElts >= NumElts) { 1374 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, 1375 DAG.getIntPtrConstant(Idx)); 1376 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, 1377 DAG.getIntPtrConstant(Idx)); 1378 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2); 1379 Idx += NumElts; 1380 CurNumElts -= NumElts; 1381 } 1382 do { 1383 NumElts = NumElts / 2; 1384 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1385 } while (!TLI.isTypeLegal(VT) && NumElts != 1); 1386 1387 if (NumElts == 1) { 1388 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) { 1389 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1390 InOp1, DAG.getIntPtrConstant(Idx)); 1391 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1392 InOp2, DAG.getIntPtrConstant(Idx)); 1393 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT, 1394 EOp1, EOp2); 1395 } 1396 CurNumElts = 0; 1397 } 1398 } 1399 1400 // Check to see if we have a single operation with the widen type. 1401 if (ConcatEnd == 1) { 1402 VT = ConcatOps[0].getValueType(); 1403 if (VT == WidenVT) 1404 return ConcatOps[0]; 1405 } 1406 1407 // while (Some element of ConcatOps is not of type MaxVT) { 1408 // From the end of ConcatOps, collect elements of the same type and put 1409 // them into an op of the next larger supported type 1410 // } 1411 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) { 1412 Idx = ConcatEnd - 1; 1413 VT = ConcatOps[Idx--].getValueType(); 1414 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT) 1415 Idx--; 1416 1417 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1; 1418 EVT NextVT; 1419 do { 1420 NextSize *= 2; 1421 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize); 1422 } while (!TLI.isTypeLegal(NextVT)); 1423 1424 if (!VT.isVector()) { 1425 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT 1426 SDValue VecOp = DAG.getUNDEF(NextVT); 1427 unsigned NumToInsert = ConcatEnd - Idx - 1; 1428 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) { 1429 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, 1430 ConcatOps[OpIdx], DAG.getIntPtrConstant(i)); 1431 } 1432 ConcatOps[Idx+1] = VecOp; 1433 ConcatEnd = Idx + 2; 1434 } else { 1435 // Vector type, create a CONCAT_VECTORS of type NextVT 1436 SDValue undefVec = DAG.getUNDEF(VT); 1437 unsigned OpsToConcat = NextSize/VT.getVectorNumElements(); 1438 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat); 1439 unsigned RealVals = ConcatEnd - Idx - 1; 1440 unsigned SubConcatEnd = 0; 1441 unsigned SubConcatIdx = Idx + 1; 1442 while (SubConcatEnd < RealVals) 1443 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx]; 1444 while (SubConcatEnd < OpsToConcat) 1445 SubConcatOps[SubConcatEnd++] = undefVec; 1446 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1447 NextVT, &SubConcatOps[0], 1448 OpsToConcat); 1449 ConcatEnd = SubConcatIdx + 1; 1450 } 1451 } 1452 1453 // Check to see if we have a single operation with the widen type. 1454 if (ConcatEnd == 1) { 1455 VT = ConcatOps[0].getValueType(); 1456 if (VT == WidenVT) 1457 return ConcatOps[0]; 1458 } 1459 1460 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT 1461 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements(); 1462 if (NumOps != ConcatEnd ) { 1463 SDValue UndefVal = DAG.getUNDEF(MaxVT); 1464 for (unsigned j = ConcatEnd; j < NumOps; ++j) 1465 ConcatOps[j] = UndefVal; 1466 } 1467 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps); 1468} 1469 1470SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { 1471 SDValue InOp = N->getOperand(0); 1472 DebugLoc DL = N->getDebugLoc(); 1473 1474 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1475 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1476 1477 EVT InVT = InOp.getValueType(); 1478 EVT InEltVT = InVT.getVectorElementType(); 1479 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1480 1481 unsigned Opcode = N->getOpcode(); 1482 unsigned InVTNumElts = InVT.getVectorNumElements(); 1483 1484 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1485 InOp = GetWidenedVector(N->getOperand(0)); 1486 InVT = InOp.getValueType(); 1487 InVTNumElts = InVT.getVectorNumElements(); 1488 if (InVTNumElts == WidenNumElts) { 1489 if (N->getNumOperands() == 1) 1490 return DAG.getNode(Opcode, DL, WidenVT, InOp); 1491 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1)); 1492 } 1493 } 1494 1495 if (TLI.isTypeLegal(InWidenVT)) { 1496 // Because the result and the input are different vector types, widening 1497 // the result could create a legal type but widening the input might make 1498 // it an illegal type that might lead to repeatedly splitting the input 1499 // and then widening it. To avoid this, we widen the input only if 1500 // it results in a legal type. 1501 if (WidenNumElts % InVTNumElts == 0) { 1502 // Widen the input and call convert on the widened input vector. 1503 unsigned NumConcat = WidenNumElts/InVTNumElts; 1504 SmallVector<SDValue, 16> Ops(NumConcat); 1505 Ops[0] = InOp; 1506 SDValue UndefVal = DAG.getUNDEF(InVT); 1507 for (unsigned i = 1; i != NumConcat; ++i) 1508 Ops[i] = UndefVal; 1509 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, 1510 &Ops[0], NumConcat); 1511 if (N->getNumOperands() == 1) 1512 return DAG.getNode(Opcode, DL, WidenVT, InVec); 1513 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1)); 1514 } 1515 1516 if (InVTNumElts % WidenNumElts == 0) { 1517 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, 1518 InOp, DAG.getIntPtrConstant(0)); 1519 // Extract the input and convert the shorten input vector. 1520 if (N->getNumOperands() == 1) 1521 return DAG.getNode(Opcode, DL, WidenVT, InVal); 1522 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1)); 1523 } 1524 } 1525 1526 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1527 SmallVector<SDValue, 16> Ops(WidenNumElts); 1528 EVT EltVT = WidenVT.getVectorElementType(); 1529 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1530 unsigned i; 1531 for (i=0; i < MinElts; ++i) { 1532 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp, 1533 DAG.getIntPtrConstant(i)); 1534 if (N->getNumOperands() == 1) 1535 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val); 1536 else 1537 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1)); 1538 } 1539 1540 SDValue UndefVal = DAG.getUNDEF(EltVT); 1541 for (; i < WidenNumElts; ++i) 1542 Ops[i] = UndefVal; 1543 1544 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts); 1545} 1546 1547SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) { 1548 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1549 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1550 SDValue ShOp = N->getOperand(1); 1551 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1552} 1553 1554SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) { 1555 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1556 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1557 SDValue ShOp = N->getOperand(1); 1558 1559 EVT ShVT = ShOp.getValueType(); 1560 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) { 1561 ShOp = GetWidenedVector(ShOp); 1562 ShVT = ShOp.getValueType(); 1563 } 1564 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(), 1565 ShVT.getVectorElementType(), 1566 WidenVT.getVectorNumElements()); 1567 if (ShVT != ShWidenVT) 1568 ShOp = ModifyToType(ShOp, ShWidenVT); 1569 1570 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1571} 1572 1573SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) { 1574 // Unary op widening. 1575 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1576 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1577 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp); 1578} 1579 1580SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) { 1581 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1582 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), 1583 cast<VTSDNode>(N->getOperand(1))->getVT() 1584 .getVectorElementType(), 1585 WidenVT.getVectorNumElements()); 1586 SDValue WidenLHS = GetWidenedVector(N->getOperand(0)); 1587 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 1588 WidenVT, WidenLHS, DAG.getValueType(ExtVT)); 1589} 1590 1591SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) { 1592 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo); 1593 return GetWidenedVector(WidenVec); 1594} 1595 1596SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) { 1597 SDValue InOp = N->getOperand(0); 1598 EVT InVT = InOp.getValueType(); 1599 EVT VT = N->getValueType(0); 1600 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1601 DebugLoc dl = N->getDebugLoc(); 1602 1603 switch (getTypeAction(InVT)) { 1604 default: 1605 assert(false && "Unknown type action!"); 1606 break; 1607 case TargetLowering::TypeLegal: 1608 break; 1609 case TargetLowering::TypePromoteInteger: 1610 // If the InOp is promoted to the same size, convert it. Otherwise, 1611 // fall out of the switch and widen the promoted input. 1612 InOp = GetPromotedInteger(InOp); 1613 InVT = InOp.getValueType(); 1614 if (WidenVT.bitsEq(InVT)) 1615 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1616 break; 1617 case TargetLowering::TypeSoftenFloat: 1618 case TargetLowering::TypeExpandInteger: 1619 case TargetLowering::TypeExpandFloat: 1620 case TargetLowering::TypeScalarizeVector: 1621 case TargetLowering::TypeSplitVector: 1622 break; 1623 case TargetLowering::TypeWidenVector: 1624 // If the InOp is widened to the same size, convert it. Otherwise, fall 1625 // out of the switch and widen the widened input. 1626 InOp = GetWidenedVector(InOp); 1627 InVT = InOp.getValueType(); 1628 if (WidenVT.bitsEq(InVT)) 1629 // The input widens to the same size. Convert to the widen value. 1630 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1631 break; 1632 } 1633 1634 unsigned WidenSize = WidenVT.getSizeInBits(); 1635 unsigned InSize = InVT.getSizeInBits(); 1636 // x86mmx is not an acceptable vector element type, so don't try. 1637 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) { 1638 // Determine new input vector type. The new input vector type will use 1639 // the same element type (if its a vector) or use the input type as a 1640 // vector. It is the same size as the type to widen to. 1641 EVT NewInVT; 1642 unsigned NewNumElts = WidenSize / InSize; 1643 if (InVT.isVector()) { 1644 EVT InEltVT = InVT.getVectorElementType(); 1645 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, 1646 WidenSize / InEltVT.getSizeInBits()); 1647 } else { 1648 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts); 1649 } 1650 1651 if (TLI.isTypeLegal(NewInVT)) { 1652 // Because the result and the input are different vector types, widening 1653 // the result could create a legal type but widening the input might make 1654 // it an illegal type that might lead to repeatedly splitting the input 1655 // and then widening it. To avoid this, we widen the input only if 1656 // it results in a legal type. 1657 SmallVector<SDValue, 16> Ops(NewNumElts); 1658 SDValue UndefVal = DAG.getUNDEF(InVT); 1659 Ops[0] = InOp; 1660 for (unsigned i = 1; i < NewNumElts; ++i) 1661 Ops[i] = UndefVal; 1662 1663 SDValue NewVec; 1664 if (InVT.isVector()) 1665 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1666 NewInVT, &Ops[0], NewNumElts); 1667 else 1668 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, 1669 NewInVT, &Ops[0], NewNumElts); 1670 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec); 1671 } 1672 } 1673 1674 return CreateStackStoreLoad(InOp, WidenVT); 1675} 1676 1677SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) { 1678 DebugLoc dl = N->getDebugLoc(); 1679 // Build a vector with undefined for the new nodes. 1680 EVT VT = N->getValueType(0); 1681 EVT EltVT = VT.getVectorElementType(); 1682 unsigned NumElts = VT.getVectorNumElements(); 1683 1684 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1685 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1686 1687 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end()); 1688 NewOps.reserve(WidenNumElts); 1689 for (unsigned i = NumElts; i < WidenNumElts; ++i) 1690 NewOps.push_back(DAG.getUNDEF(EltVT)); 1691 1692 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size()); 1693} 1694 1695SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) { 1696 EVT InVT = N->getOperand(0).getValueType(); 1697 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1698 DebugLoc dl = N->getDebugLoc(); 1699 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1700 unsigned NumInElts = InVT.getVectorNumElements(); 1701 unsigned NumOperands = N->getNumOperands(); 1702 1703 bool InputWidened = false; // Indicates we need to widen the input. 1704 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) { 1705 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) { 1706 // Add undef vectors to widen to correct length. 1707 unsigned NumConcat = WidenVT.getVectorNumElements() / 1708 InVT.getVectorNumElements(); 1709 SDValue UndefVal = DAG.getUNDEF(InVT); 1710 SmallVector<SDValue, 16> Ops(NumConcat); 1711 for (unsigned i=0; i < NumOperands; ++i) 1712 Ops[i] = N->getOperand(i); 1713 for (unsigned i = NumOperands; i != NumConcat; ++i) 1714 Ops[i] = UndefVal; 1715 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat); 1716 } 1717 } else { 1718 InputWidened = true; 1719 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) { 1720 // The inputs and the result are widen to the same value. 1721 unsigned i; 1722 for (i=1; i < NumOperands; ++i) 1723 if (N->getOperand(i).getOpcode() != ISD::UNDEF) 1724 break; 1725 1726 if (i == NumOperands) 1727 // Everything but the first operand is an UNDEF so just return the 1728 // widened first operand. 1729 return GetWidenedVector(N->getOperand(0)); 1730 1731 if (NumOperands == 2) { 1732 // Replace concat of two operands with a shuffle. 1733 SmallVector<int, 16> MaskOps(WidenNumElts, -1); 1734 for (unsigned i = 0; i < NumInElts; ++i) { 1735 MaskOps[i] = i; 1736 MaskOps[i + NumInElts] = i + WidenNumElts; 1737 } 1738 return DAG.getVectorShuffle(WidenVT, dl, 1739 GetWidenedVector(N->getOperand(0)), 1740 GetWidenedVector(N->getOperand(1)), 1741 &MaskOps[0]); 1742 } 1743 } 1744 } 1745 1746 // Fall back to use extracts and build vector. 1747 EVT EltVT = WidenVT.getVectorElementType(); 1748 SmallVector<SDValue, 16> Ops(WidenNumElts); 1749 unsigned Idx = 0; 1750 for (unsigned i=0; i < NumOperands; ++i) { 1751 SDValue InOp = N->getOperand(i); 1752 if (InputWidened) 1753 InOp = GetWidenedVector(InOp); 1754 for (unsigned j=0; j < NumInElts; ++j) 1755 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1756 DAG.getIntPtrConstant(j)); 1757 } 1758 SDValue UndefVal = DAG.getUNDEF(EltVT); 1759 for (; Idx < WidenNumElts; ++Idx) 1760 Ops[Idx] = UndefVal; 1761 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1762} 1763 1764SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { 1765 DebugLoc dl = N->getDebugLoc(); 1766 SDValue InOp = N->getOperand(0); 1767 SDValue RndOp = N->getOperand(3); 1768 SDValue SatOp = N->getOperand(4); 1769 1770 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1771 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1772 1773 EVT InVT = InOp.getValueType(); 1774 EVT InEltVT = InVT.getVectorElementType(); 1775 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1776 1777 SDValue DTyOp = DAG.getValueType(WidenVT); 1778 SDValue STyOp = DAG.getValueType(InWidenVT); 1779 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 1780 1781 unsigned InVTNumElts = InVT.getVectorNumElements(); 1782 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1783 InOp = GetWidenedVector(InOp); 1784 InVT = InOp.getValueType(); 1785 InVTNumElts = InVT.getVectorNumElements(); 1786 if (InVTNumElts == WidenNumElts) 1787 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1788 SatOp, CvtCode); 1789 } 1790 1791 if (TLI.isTypeLegal(InWidenVT)) { 1792 // Because the result and the input are different vector types, widening 1793 // the result could create a legal type but widening the input might make 1794 // it an illegal type that might lead to repeatedly splitting the input 1795 // and then widening it. To avoid this, we widen the input only if 1796 // it results in a legal type. 1797 if (WidenNumElts % InVTNumElts == 0) { 1798 // Widen the input and call convert on the widened input vector. 1799 unsigned NumConcat = WidenNumElts/InVTNumElts; 1800 SmallVector<SDValue, 16> Ops(NumConcat); 1801 Ops[0] = InOp; 1802 SDValue UndefVal = DAG.getUNDEF(InVT); 1803 for (unsigned i = 1; i != NumConcat; ++i) 1804 Ops[i] = UndefVal; 1805 1806 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat); 1807 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1808 SatOp, CvtCode); 1809 } 1810 1811 if (InVTNumElts % WidenNumElts == 0) { 1812 // Extract the input and convert the shorten input vector. 1813 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp, 1814 DAG.getIntPtrConstant(0)); 1815 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1816 SatOp, CvtCode); 1817 } 1818 } 1819 1820 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1821 SmallVector<SDValue, 16> Ops(WidenNumElts); 1822 EVT EltVT = WidenVT.getVectorElementType(); 1823 DTyOp = DAG.getValueType(EltVT); 1824 STyOp = DAG.getValueType(InEltVT); 1825 1826 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1827 unsigned i; 1828 for (i=0; i < MinElts; ++i) { 1829 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 1830 DAG.getIntPtrConstant(i)); 1831 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp, 1832 SatOp, CvtCode); 1833 } 1834 1835 SDValue UndefVal = DAG.getUNDEF(EltVT); 1836 for (; i < WidenNumElts; ++i) 1837 Ops[i] = UndefVal; 1838 1839 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1840} 1841 1842SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 1843 EVT VT = N->getValueType(0); 1844 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1845 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1846 SDValue InOp = N->getOperand(0); 1847 SDValue Idx = N->getOperand(1); 1848 DebugLoc dl = N->getDebugLoc(); 1849 1850 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 1851 InOp = GetWidenedVector(InOp); 1852 1853 EVT InVT = InOp.getValueType(); 1854 1855 // Check if we can just return the input vector after widening. 1856 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1857 if (IdxVal == 0 && InVT == WidenVT) 1858 return InOp; 1859 1860 // Check if we can extract from the vector. 1861 unsigned InNumElts = InVT.getVectorNumElements(); 1862 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts) 1863 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx); 1864 1865 // We could try widening the input to the right length but for now, extract 1866 // the original elements, fill the rest with undefs and build a vector. 1867 SmallVector<SDValue, 16> Ops(WidenNumElts); 1868 EVT EltVT = VT.getVectorElementType(); 1869 unsigned NumElts = VT.getVectorNumElements(); 1870 unsigned i; 1871 for (i=0; i < NumElts; ++i) 1872 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1873 DAG.getIntPtrConstant(IdxVal+i)); 1874 1875 SDValue UndefVal = DAG.getUNDEF(EltVT); 1876 for (; i < WidenNumElts; ++i) 1877 Ops[i] = UndefVal; 1878 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1879} 1880 1881SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) { 1882 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1883 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(), 1884 InOp.getValueType(), InOp, 1885 N->getOperand(1), N->getOperand(2)); 1886} 1887 1888SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) { 1889 LoadSDNode *LD = cast<LoadSDNode>(N); 1890 ISD::LoadExtType ExtType = LD->getExtensionType(); 1891 1892 SDValue Result; 1893 SmallVector<SDValue, 16> LdChain; // Chain for the series of load 1894 if (ExtType != ISD::NON_EXTLOAD) 1895 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); 1896 else 1897 Result = GenWidenVectorLoads(LdChain, LD); 1898 1899 // If we generate a single load, we can use that for the chain. Otherwise, 1900 // build a factor node to remember the multiple loads are independent and 1901 // chain to that. 1902 SDValue NewChain; 1903 if (LdChain.size() == 1) 1904 NewChain = LdChain[0]; 1905 else 1906 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other, 1907 &LdChain[0], LdChain.size()); 1908 1909 // Modified the chain - switch anything that used the old chain to use 1910 // the new one. 1911 ReplaceValueWith(SDValue(N, 1), NewChain); 1912 1913 return Result; 1914} 1915 1916SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) { 1917 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1918 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(), 1919 WidenVT, N->getOperand(0)); 1920} 1921 1922SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) { 1923 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1924 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1925 1926 SDValue Cond1 = N->getOperand(0); 1927 EVT CondVT = Cond1.getValueType(); 1928 if (CondVT.isVector()) { 1929 EVT CondEltVT = CondVT.getVectorElementType(); 1930 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), 1931 CondEltVT, WidenNumElts); 1932 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector) 1933 Cond1 = GetWidenedVector(Cond1); 1934 1935 if (Cond1.getValueType() != CondWidenVT) 1936 Cond1 = ModifyToType(Cond1, CondWidenVT); 1937 } 1938 1939 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 1940 SDValue InOp2 = GetWidenedVector(N->getOperand(2)); 1941 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT); 1942 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 1943 WidenVT, Cond1, InOp1, InOp2); 1944} 1945 1946SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) { 1947 SDValue InOp1 = GetWidenedVector(N->getOperand(2)); 1948 SDValue InOp2 = GetWidenedVector(N->getOperand(3)); 1949 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 1950 InOp1.getValueType(), N->getOperand(0), 1951 N->getOperand(1), InOp1, InOp2, N->getOperand(4)); 1952} 1953 1954SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) { 1955 assert(N->getValueType(0).isVector() == 1956 N->getOperand(0).getValueType().isVector() && 1957 "Scalar/Vector type mismatch"); 1958 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N); 1959 1960 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1961 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1962 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1963 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT, 1964 InOp1, InOp2, N->getOperand(2)); 1965} 1966 1967SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) { 1968 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1969 return DAG.getUNDEF(WidenVT); 1970} 1971 1972SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) { 1973 EVT VT = N->getValueType(0); 1974 DebugLoc dl = N->getDebugLoc(); 1975 1976 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1977 unsigned NumElts = VT.getVectorNumElements(); 1978 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1979 1980 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1981 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1982 1983 // Adjust mask based on new input vector length. 1984 SmallVector<int, 16> NewMask; 1985 for (unsigned i = 0; i != NumElts; ++i) { 1986 int Idx = N->getMaskElt(i); 1987 if (Idx < (int)NumElts) 1988 NewMask.push_back(Idx); 1989 else 1990 NewMask.push_back(Idx - NumElts + WidenNumElts); 1991 } 1992 for (unsigned i = NumElts; i != WidenNumElts; ++i) 1993 NewMask.push_back(-1); 1994 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]); 1995} 1996 1997SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) { 1998 assert(N->getValueType(0).isVector() && 1999 N->getOperand(0).getValueType().isVector() && 2000 "Operands must be vectors"); 2001 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2002 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2003 2004 SDValue InOp1 = N->getOperand(0); 2005 EVT InVT = InOp1.getValueType(); 2006 assert(InVT.isVector() && "can not widen non vector type"); 2007 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(), 2008 InVT.getVectorElementType(), WidenNumElts); 2009 InOp1 = GetWidenedVector(InOp1); 2010 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 2011 2012 // Assume that the input and output will be widen appropriately. If not, 2013 // we will have to unroll it at some point. 2014 assert(InOp1.getValueType() == WidenInVT && 2015 InOp2.getValueType() == WidenInVT && 2016 "Input not widened to expected type!"); 2017 (void)WidenInVT; 2018 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), 2019 WidenVT, InOp1, InOp2, N->getOperand(2)); 2020} 2021 2022 2023//===----------------------------------------------------------------------===// 2024// Widen Vector Operand 2025//===----------------------------------------------------------------------===// 2026bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) { 2027 DEBUG(dbgs() << "Widen node operand " << ResNo << ": "; 2028 N->dump(&DAG); 2029 dbgs() << "\n"); 2030 SDValue Res = SDValue(); 2031 2032 switch (N->getOpcode()) { 2033 default: 2034#ifndef NDEBUG 2035 dbgs() << "WidenVectorOperand op #" << ResNo << ": "; 2036 N->dump(&DAG); 2037 dbgs() << "\n"; 2038#endif 2039 llvm_unreachable("Do not know how to widen this operator's operand!"); 2040 2041 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break; 2042 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break; 2043 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break; 2044 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break; 2045 case ISD::STORE: Res = WidenVecOp_STORE(N); break; 2046 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break; 2047 2048 case ISD::FP_EXTEND: 2049 case ISD::FP_TO_SINT: 2050 case ISD::FP_TO_UINT: 2051 case ISD::SINT_TO_FP: 2052 case ISD::UINT_TO_FP: 2053 case ISD::TRUNCATE: 2054 case ISD::SIGN_EXTEND: 2055 case ISD::ZERO_EXTEND: 2056 case ISD::ANY_EXTEND: 2057 Res = WidenVecOp_Convert(N); 2058 break; 2059 } 2060 2061 // If Res is null, the sub-method took care of registering the result. 2062 if (!Res.getNode()) return false; 2063 2064 // If the result is N, the sub-method updated N in place. Tell the legalizer 2065 // core about this. 2066 if (Res.getNode() == N) 2067 return true; 2068 2069 2070 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2071 "Invalid operand expansion"); 2072 2073 ReplaceValueWith(SDValue(N, 0), Res); 2074 return false; 2075} 2076 2077SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) { 2078 // Since the result is legal and the input is illegal, it is unlikely 2079 // that we can fix the input to a legal type so unroll the convert 2080 // into some scalar code and create a nasty build vector. 2081 EVT VT = N->getValueType(0); 2082 EVT EltVT = VT.getVectorElementType(); 2083 DebugLoc dl = N->getDebugLoc(); 2084 unsigned NumElts = VT.getVectorNumElements(); 2085 SDValue InOp = N->getOperand(0); 2086 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2087 InOp = GetWidenedVector(InOp); 2088 EVT InVT = InOp.getValueType(); 2089 EVT InEltVT = InVT.getVectorElementType(); 2090 2091 unsigned Opcode = N->getOpcode(); 2092 SmallVector<SDValue, 16> Ops(NumElts); 2093 for (unsigned i=0; i < NumElts; ++i) 2094 Ops[i] = DAG.getNode(Opcode, dl, EltVT, 2095 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 2096 DAG.getIntPtrConstant(i))); 2097 2098 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2099} 2100 2101SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) { 2102 EVT VT = N->getValueType(0); 2103 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2104 EVT InWidenVT = InOp.getValueType(); 2105 DebugLoc dl = N->getDebugLoc(); 2106 2107 // Check if we can convert between two legal vector types and extract. 2108 unsigned InWidenSize = InWidenVT.getSizeInBits(); 2109 unsigned Size = VT.getSizeInBits(); 2110 // x86mmx is not an acceptable vector element type, so don't try. 2111 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) { 2112 unsigned NewNumElts = InWidenSize / Size; 2113 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); 2114 if (TLI.isTypeLegal(NewVT)) { 2115 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp); 2116 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, 2117 DAG.getIntPtrConstant(0)); 2118 } 2119 } 2120 2121 return CreateStackStoreLoad(InOp, VT); 2122} 2123 2124SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) { 2125 // If the input vector is not legal, it is likely that we will not find a 2126 // legal vector of the same size. Replace the concatenate vector with a 2127 // nasty build vector. 2128 EVT VT = N->getValueType(0); 2129 EVT EltVT = VT.getVectorElementType(); 2130 DebugLoc dl = N->getDebugLoc(); 2131 unsigned NumElts = VT.getVectorNumElements(); 2132 SmallVector<SDValue, 16> Ops(NumElts); 2133 2134 EVT InVT = N->getOperand(0).getValueType(); 2135 unsigned NumInElts = InVT.getVectorNumElements(); 2136 2137 unsigned Idx = 0; 2138 unsigned NumOperands = N->getNumOperands(); 2139 for (unsigned i=0; i < NumOperands; ++i) { 2140 SDValue InOp = N->getOperand(i); 2141 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2142 InOp = GetWidenedVector(InOp); 2143 for (unsigned j=0; j < NumInElts; ++j) 2144 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2145 DAG.getIntPtrConstant(j)); 2146 } 2147 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2148} 2149 2150SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 2151 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2152 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), 2153 N->getValueType(0), InOp, N->getOperand(1)); 2154} 2155 2156SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 2157 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2158 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 2159 N->getValueType(0), InOp, N->getOperand(1)); 2160} 2161 2162SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) { 2163 // We have to widen the value but we want only to store the original 2164 // vector type. 2165 StoreSDNode *ST = cast<StoreSDNode>(N); 2166 2167 SmallVector<SDValue, 16> StChain; 2168 if (ST->isTruncatingStore()) 2169 GenWidenVectorTruncStores(StChain, ST); 2170 else 2171 GenWidenVectorStores(StChain, ST); 2172 2173 if (StChain.size() == 1) 2174 return StChain[0]; 2175 else 2176 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(), 2177 MVT::Other,&StChain[0],StChain.size()); 2178} 2179 2180SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) { 2181 SDValue InOp0 = GetWidenedVector(N->getOperand(0)); 2182 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 2183 DebugLoc dl = N->getDebugLoc(); 2184 2185 // WARNING: In this code we widen the compare instruction with garbage. 2186 // This garbage may contain denormal floats which may be slow. Is this a real 2187 // concern ? Should we zero the unused lanes if this is a float compare ? 2188 2189 // Get a new SETCC node to compare the newly widened operands. 2190 // Only some of the compared elements are legal. 2191 EVT SVT = TLI.getSetCCResultType(InOp0.getValueType()); 2192 SDValue WideSETCC = DAG.getNode(ISD::SETCC, N->getDebugLoc(), 2193 SVT, InOp0, InOp1, N->getOperand(2)); 2194 2195 // Extract the needed results from the result vector. 2196 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), 2197 SVT.getVectorElementType(), 2198 N->getValueType(0).getVectorNumElements()); 2199 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, 2200 ResVT, WideSETCC, DAG.getIntPtrConstant(0)); 2201 2202 return PromoteTargetBoolean(CC, N->getValueType(0)); 2203} 2204 2205 2206//===----------------------------------------------------------------------===// 2207// Vector Widening Utilities 2208//===----------------------------------------------------------------------===// 2209 2210// Utility function to find the type to chop up a widen vector for load/store 2211// TLI: Target lowering used to determine legal types. 2212// Width: Width left need to load/store. 2213// WidenVT: The widen vector type to load to/store from 2214// Align: If 0, don't allow use of a wider type 2215// WidenEx: If Align is not 0, the amount additional we can load/store from. 2216 2217static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, 2218 unsigned Width, EVT WidenVT, 2219 unsigned Align = 0, unsigned WidenEx = 0) { 2220 EVT WidenEltVT = WidenVT.getVectorElementType(); 2221 unsigned WidenWidth = WidenVT.getSizeInBits(); 2222 unsigned WidenEltWidth = WidenEltVT.getSizeInBits(); 2223 unsigned AlignInBits = Align*8; 2224 2225 // If we have one element to load/store, return it. 2226 EVT RetVT = WidenEltVT; 2227 if (Width == WidenEltWidth) 2228 return RetVT; 2229 2230 // See if there is larger legal integer than the element type to load/store 2231 unsigned VT; 2232 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE; 2233 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) { 2234 EVT MemVT((MVT::SimpleValueType) VT); 2235 unsigned MemVTWidth = MemVT.getSizeInBits(); 2236 if (MemVT.getSizeInBits() <= WidenEltWidth) 2237 break; 2238 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 && 2239 isPowerOf2_32(WidenWidth / MemVTWidth) && 2240 (MemVTWidth <= Width || 2241 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2242 RetVT = MemVT; 2243 break; 2244 } 2245 } 2246 2247 // See if there is a larger vector type to load/store that has the same vector 2248 // element type and is evenly divisible with the WidenVT. 2249 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; 2250 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) { 2251 EVT MemVT = (MVT::SimpleValueType) VT; 2252 unsigned MemVTWidth = MemVT.getSizeInBits(); 2253 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() && 2254 (WidenWidth % MemVTWidth) == 0 && 2255 isPowerOf2_32(WidenWidth / MemVTWidth) && 2256 (MemVTWidth <= Width || 2257 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2258 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT) 2259 return MemVT; 2260 } 2261 } 2262 2263 return RetVT; 2264} 2265 2266// Builds a vector type from scalar loads 2267// VecTy: Resulting Vector type 2268// LDOps: Load operators to build a vector type 2269// [Start,End) the list of loads to use. 2270static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, 2271 SmallVector<SDValue, 16>& LdOps, 2272 unsigned Start, unsigned End) { 2273 DebugLoc dl = LdOps[Start].getDebugLoc(); 2274 EVT LdTy = LdOps[Start].getValueType(); 2275 unsigned Width = VecTy.getSizeInBits(); 2276 unsigned NumElts = Width / LdTy.getSizeInBits(); 2277 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts); 2278 2279 unsigned Idx = 1; 2280 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]); 2281 2282 for (unsigned i = Start + 1; i != End; ++i) { 2283 EVT NewLdTy = LdOps[i].getValueType(); 2284 if (NewLdTy != LdTy) { 2285 NumElts = Width / NewLdTy.getSizeInBits(); 2286 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts); 2287 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp); 2288 // Readjust position and vector position based on new load type 2289 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits(); 2290 LdTy = NewLdTy; 2291 } 2292 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], 2293 DAG.getIntPtrConstant(Idx++)); 2294 } 2295 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp); 2296} 2297 2298SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain, 2299 LoadSDNode *LD) { 2300 // The strategy assumes that we can efficiently load powers of two widths. 2301 // The routines chops the vector into the largest vector loads with the same 2302 // element type or scalar loads and then recombines it to the widen vector 2303 // type. 2304 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2305 unsigned WidenWidth = WidenVT.getSizeInBits(); 2306 EVT LdVT = LD->getMemoryVT(); 2307 DebugLoc dl = LD->getDebugLoc(); 2308 assert(LdVT.isVector() && WidenVT.isVector()); 2309 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType()); 2310 2311 // Load information 2312 SDValue Chain = LD->getChain(); 2313 SDValue BasePtr = LD->getBasePtr(); 2314 unsigned Align = LD->getAlignment(); 2315 bool isVolatile = LD->isVolatile(); 2316 bool isNonTemporal = LD->isNonTemporal(); 2317 2318 int LdWidth = LdVT.getSizeInBits(); 2319 int WidthDiff = WidenWidth - LdWidth; // Difference 2320 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads 2321 2322 // Find the vector type that can load from. 2323 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2324 int NewVTWidth = NewVT.getSizeInBits(); 2325 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(), 2326 isVolatile, isNonTemporal, Align); 2327 LdChain.push_back(LdOp.getValue(1)); 2328 2329 // Check if we can load the element with one instruction 2330 if (LdWidth <= NewVTWidth) { 2331 if (!NewVT.isVector()) { 2332 unsigned NumElts = WidenWidth / NewVTWidth; 2333 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2334 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp); 2335 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp); 2336 } 2337 if (NewVT == WidenVT) 2338 return LdOp; 2339 2340 assert(WidenWidth % NewVTWidth == 0); 2341 unsigned NumConcat = WidenWidth / NewVTWidth; 2342 SmallVector<SDValue, 16> ConcatOps(NumConcat); 2343 SDValue UndefVal = DAG.getUNDEF(NewVT); 2344 ConcatOps[0] = LdOp; 2345 for (unsigned i = 1; i != NumConcat; ++i) 2346 ConcatOps[i] = UndefVal; 2347 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], 2348 NumConcat); 2349 } 2350 2351 // Load vector by using multiple loads from largest vector to scalar 2352 SmallVector<SDValue, 16> LdOps; 2353 LdOps.push_back(LdOp); 2354 2355 LdWidth -= NewVTWidth; 2356 unsigned Offset = 0; 2357 2358 while (LdWidth > 0) { 2359 unsigned Increment = NewVTWidth / 8; 2360 Offset += Increment; 2361 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2362 DAG.getIntPtrConstant(Increment)); 2363 2364 if (LdWidth < NewVTWidth) { 2365 // Our current type we are using is too large, find a better size 2366 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2367 NewVTWidth = NewVT.getSizeInBits(); 2368 } 2369 2370 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, 2371 LD->getPointerInfo().getWithOffset(Offset), 2372 isVolatile, 2373 isNonTemporal, MinAlign(Align, Increment)); 2374 LdChain.push_back(LdOp.getValue(1)); 2375 LdOps.push_back(LdOp); 2376 2377 LdWidth -= NewVTWidth; 2378 } 2379 2380 // Build the vector from the loads operations 2381 unsigned End = LdOps.size(); 2382 if (!LdOps[0].getValueType().isVector()) 2383 // All the loads are scalar loads. 2384 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End); 2385 2386 // If the load contains vectors, build the vector using concat vector. 2387 // All of the vectors used to loads are power of 2 and the scalars load 2388 // can be combined to make a power of 2 vector. 2389 SmallVector<SDValue, 16> ConcatOps(End); 2390 int i = End - 1; 2391 int Idx = End; 2392 EVT LdTy = LdOps[i].getValueType(); 2393 // First combine the scalar loads to a vector 2394 if (!LdTy.isVector()) { 2395 for (--i; i >= 0; --i) { 2396 LdTy = LdOps[i].getValueType(); 2397 if (LdTy.isVector()) 2398 break; 2399 } 2400 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End); 2401 } 2402 ConcatOps[--Idx] = LdOps[i]; 2403 for (--i; i >= 0; --i) { 2404 EVT NewLdTy = LdOps[i].getValueType(); 2405 if (NewLdTy != LdTy) { 2406 // Create a larger vector 2407 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy, 2408 &ConcatOps[Idx], End - Idx); 2409 Idx = End - 1; 2410 LdTy = NewLdTy; 2411 } 2412 ConcatOps[--Idx] = LdOps[i]; 2413 } 2414 2415 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx)) 2416 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, 2417 &ConcatOps[Idx], End - Idx); 2418 2419 // We need to fill the rest with undefs to build the vector 2420 unsigned NumOps = WidenWidth / LdTy.getSizeInBits(); 2421 SmallVector<SDValue, 16> WidenOps(NumOps); 2422 SDValue UndefVal = DAG.getUNDEF(LdTy); 2423 { 2424 unsigned i = 0; 2425 for (; i != End-Idx; ++i) 2426 WidenOps[i] = ConcatOps[Idx+i]; 2427 for (; i != NumOps; ++i) 2428 WidenOps[i] = UndefVal; 2429 } 2430 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps); 2431} 2432 2433SDValue 2434DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain, 2435 LoadSDNode * LD, 2436 ISD::LoadExtType ExtType) { 2437 // For extension loads, it may not be more efficient to chop up the vector 2438 // and then extended it. Instead, we unroll the load and build a new vector. 2439 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2440 EVT LdVT = LD->getMemoryVT(); 2441 DebugLoc dl = LD->getDebugLoc(); 2442 assert(LdVT.isVector() && WidenVT.isVector()); 2443 2444 // Load information 2445 SDValue Chain = LD->getChain(); 2446 SDValue BasePtr = LD->getBasePtr(); 2447 unsigned Align = LD->getAlignment(); 2448 bool isVolatile = LD->isVolatile(); 2449 bool isNonTemporal = LD->isNonTemporal(); 2450 2451 EVT EltVT = WidenVT.getVectorElementType(); 2452 EVT LdEltVT = LdVT.getVectorElementType(); 2453 unsigned NumElts = LdVT.getVectorNumElements(); 2454 2455 // Load each element and widen 2456 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2457 SmallVector<SDValue, 16> Ops(WidenNumElts); 2458 unsigned Increment = LdEltVT.getSizeInBits() / 8; 2459 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, 2460 LD->getPointerInfo(), 2461 LdEltVT, isVolatile, isNonTemporal, Align); 2462 LdChain.push_back(Ops[0].getValue(1)); 2463 unsigned i = 0, Offset = Increment; 2464 for (i=1; i < NumElts; ++i, Offset += Increment) { 2465 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2466 BasePtr, DAG.getIntPtrConstant(Offset)); 2467 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, 2468 LD->getPointerInfo().getWithOffset(Offset), LdEltVT, 2469 isVolatile, isNonTemporal, Align); 2470 LdChain.push_back(Ops[i].getValue(1)); 2471 } 2472 2473 // Fill the rest with undefs 2474 SDValue UndefVal = DAG.getUNDEF(EltVT); 2475 for (; i != WidenNumElts; ++i) 2476 Ops[i] = UndefVal; 2477 2478 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size()); 2479} 2480 2481 2482void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, 2483 StoreSDNode *ST) { 2484 // The strategy assumes that we can efficiently store powers of two widths. 2485 // The routines chops the vector into the largest vector stores with the same 2486 // element type or scalar stores. 2487 SDValue Chain = ST->getChain(); 2488 SDValue BasePtr = ST->getBasePtr(); 2489 unsigned Align = ST->getAlignment(); 2490 bool isVolatile = ST->isVolatile(); 2491 bool isNonTemporal = ST->isNonTemporal(); 2492 SDValue ValOp = GetWidenedVector(ST->getValue()); 2493 DebugLoc dl = ST->getDebugLoc(); 2494 2495 EVT StVT = ST->getMemoryVT(); 2496 unsigned StWidth = StVT.getSizeInBits(); 2497 EVT ValVT = ValOp.getValueType(); 2498 unsigned ValWidth = ValVT.getSizeInBits(); 2499 EVT ValEltVT = ValVT.getVectorElementType(); 2500 unsigned ValEltWidth = ValEltVT.getSizeInBits(); 2501 assert(StVT.getVectorElementType() == ValEltVT); 2502 2503 int Idx = 0; // current index to store 2504 unsigned Offset = 0; // offset from base to store 2505 while (StWidth != 0) { 2506 // Find the largest vector type we can store with 2507 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT); 2508 unsigned NewVTWidth = NewVT.getSizeInBits(); 2509 unsigned Increment = NewVTWidth / 8; 2510 if (NewVT.isVector()) { 2511 unsigned NumVTElts = NewVT.getVectorNumElements(); 2512 do { 2513 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, 2514 DAG.getIntPtrConstant(Idx)); 2515 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2516 ST->getPointerInfo().getWithOffset(Offset), 2517 isVolatile, isNonTemporal, 2518 MinAlign(Align, Offset))); 2519 StWidth -= NewVTWidth; 2520 Offset += Increment; 2521 Idx += NumVTElts; 2522 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2523 DAG.getIntPtrConstant(Increment)); 2524 } while (StWidth != 0 && StWidth >= NewVTWidth); 2525 } else { 2526 // Cast the vector to the scalar type we can store 2527 unsigned NumElts = ValWidth / NewVTWidth; 2528 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2529 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); 2530 // Readjust index position based on new vector type 2531 Idx = Idx * ValEltWidth / NewVTWidth; 2532 do { 2533 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp, 2534 DAG.getIntPtrConstant(Idx++)); 2535 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2536 ST->getPointerInfo().getWithOffset(Offset), 2537 isVolatile, isNonTemporal, 2538 MinAlign(Align, Offset))); 2539 StWidth -= NewVTWidth; 2540 Offset += Increment; 2541 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2542 DAG.getIntPtrConstant(Increment)); 2543 } while (StWidth != 0 && StWidth >= NewVTWidth); 2544 // Restore index back to be relative to the original widen element type 2545 Idx = Idx * NewVTWidth / ValEltWidth; 2546 } 2547 } 2548} 2549 2550void 2551DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain, 2552 StoreSDNode *ST) { 2553 // For extension loads, it may not be more efficient to truncate the vector 2554 // and then store it. Instead, we extract each element and then store it. 2555 SDValue Chain = ST->getChain(); 2556 SDValue BasePtr = ST->getBasePtr(); 2557 unsigned Align = ST->getAlignment(); 2558 bool isVolatile = ST->isVolatile(); 2559 bool isNonTemporal = ST->isNonTemporal(); 2560 SDValue ValOp = GetWidenedVector(ST->getValue()); 2561 DebugLoc dl = ST->getDebugLoc(); 2562 2563 EVT StVT = ST->getMemoryVT(); 2564 EVT ValVT = ValOp.getValueType(); 2565 2566 // It must be true that we the widen vector type is bigger than where 2567 // we need to store. 2568 assert(StVT.isVector() && ValOp.getValueType().isVector()); 2569 assert(StVT.bitsLT(ValOp.getValueType())); 2570 2571 // For truncating stores, we can not play the tricks of chopping legal 2572 // vector types and bit cast it to the right type. Instead, we unroll 2573 // the store. 2574 EVT StEltVT = StVT.getVectorElementType(); 2575 EVT ValEltVT = ValVT.getVectorElementType(); 2576 unsigned Increment = ValEltVT.getSizeInBits() / 8; 2577 unsigned NumElts = StVT.getVectorNumElements(); 2578 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2579 DAG.getIntPtrConstant(0)); 2580 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, 2581 ST->getPointerInfo(), StEltVT, 2582 isVolatile, isNonTemporal, Align)); 2583 unsigned Offset = Increment; 2584 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) { 2585 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2586 BasePtr, DAG.getIntPtrConstant(Offset)); 2587 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2588 DAG.getIntPtrConstant(0)); 2589 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, 2590 ST->getPointerInfo().getWithOffset(Offset), 2591 StEltVT, isVolatile, isNonTemporal, 2592 MinAlign(Align, Offset))); 2593 } 2594} 2595 2596/// Modifies a vector input (widen or narrows) to a vector of NVT. The 2597/// input vector must have the same element type as NVT. 2598SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) { 2599 // Note that InOp might have been widened so it might already have 2600 // the right width or it might need be narrowed. 2601 EVT InVT = InOp.getValueType(); 2602 assert(InVT.getVectorElementType() == NVT.getVectorElementType() && 2603 "input and widen element type must match"); 2604 DebugLoc dl = InOp.getDebugLoc(); 2605 2606 // Check if InOp already has the right width. 2607 if (InVT == NVT) 2608 return InOp; 2609 2610 unsigned InNumElts = InVT.getVectorNumElements(); 2611 unsigned WidenNumElts = NVT.getVectorNumElements(); 2612 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) { 2613 unsigned NumConcat = WidenNumElts / InNumElts; 2614 SmallVector<SDValue, 16> Ops(NumConcat); 2615 SDValue UndefVal = DAG.getUNDEF(InVT); 2616 Ops[0] = InOp; 2617 for (unsigned i = 1; i != NumConcat; ++i) 2618 Ops[i] = UndefVal; 2619 2620 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat); 2621 } 2622 2623 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts) 2624 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp, 2625 DAG.getIntPtrConstant(0)); 2626 2627 // Fall back to extract and build. 2628 SmallVector<SDValue, 16> Ops(WidenNumElts); 2629 EVT EltVT = NVT.getVectorElementType(); 2630 unsigned MinNumElts = std::min(WidenNumElts, InNumElts); 2631 unsigned Idx; 2632 for (Idx = 0; Idx < MinNumElts; ++Idx) 2633 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2634 DAG.getIntPtrConstant(Idx)); 2635 2636 SDValue UndefVal = DAG.getUNDEF(EltVT); 2637 for ( ; Idx < WidenNumElts; ++Idx) 2638 Ops[Idx] = UndefVal; 2639 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts); 2640} 2641