LegalizeVectorTypes.cpp revision a921a468542a804ccebb680935175798ac48868b
1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file performs vector type splitting and scalarization for LegalizeTypes. 11// Scalarization is the act of changing a computation in an illegal one-element 12// vector type to be a computation in its scalar element type. For example, 13// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed 14// as a base case when scalarizing vector arithmetic like <4 x f32>, which 15// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32 16// types. 17// Splitting is the act of changing a computation in an invalid vector type to 18// be a computation in two vectors of half the size. For example, implementing 19// <128 x f32> operations in terms of two <64 x f32> operations. 20// 21//===----------------------------------------------------------------------===// 22 23#include "LegalizeTypes.h" 24#include "llvm/CodeGen/PseudoSourceValue.h" 25#include "llvm/Target/TargetData.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Support/raw_ostream.h" 28using namespace llvm; 29 30//===----------------------------------------------------------------------===// 31// Result Vector Scalarization: <1 x ty> -> ty. 32//===----------------------------------------------------------------------===// 33 34void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { 35 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; 36 N->dump(&DAG); 37 dbgs() << "\n"); 38 SDValue R = SDValue(); 39 40 switch (N->getOpcode()) { 41 default: 42#ifndef NDEBUG 43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": "; 44 N->dump(&DAG); 45 dbgs() << "\n"; 46#endif 47 report_fatal_error("Do not know how to scalarize the result of this " 48 "operator!\n"); 49 50 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; 51 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 52 case ISD::BUILD_VECTOR: R = N->getOperand(0); break; 53 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; 54 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 55 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; 56 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; 57 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 58 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 59 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; 60 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; 61 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; 62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break; 63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; 65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; 66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; 67 case ISD::ANY_EXTEND: 68 case ISD::CTLZ: 69 case ISD::CTPOP: 70 case ISD::CTTZ: 71 case ISD::FABS: 72 case ISD::FCEIL: 73 case ISD::FCOS: 74 case ISD::FEXP: 75 case ISD::FEXP2: 76 case ISD::FFLOOR: 77 case ISD::FLOG: 78 case ISD::FLOG10: 79 case ISD::FLOG2: 80 case ISD::FNEARBYINT: 81 case ISD::FNEG: 82 case ISD::FP_EXTEND: 83 case ISD::FP_TO_SINT: 84 case ISD::FP_TO_UINT: 85 case ISD::FRINT: 86 case ISD::FSIN: 87 case ISD::FSQRT: 88 case ISD::FTRUNC: 89 case ISD::SIGN_EXTEND: 90 case ISD::SINT_TO_FP: 91 case ISD::TRUNCATE: 92 case ISD::UINT_TO_FP: 93 case ISD::ZERO_EXTEND: 94 R = ScalarizeVecRes_UnaryOp(N); 95 break; 96 97 case ISD::ADD: 98 case ISD::AND: 99 case ISD::FADD: 100 case ISD::FDIV: 101 case ISD::FMUL: 102 case ISD::FPOW: 103 case ISD::FREM: 104 case ISD::FSUB: 105 case ISD::MUL: 106 case ISD::OR: 107 case ISD::SDIV: 108 case ISD::SREM: 109 case ISD::SUB: 110 case ISD::UDIV: 111 case ISD::UREM: 112 case ISD::XOR: 113 case ISD::SHL: 114 case ISD::SRA: 115 case ISD::SRL: 116 R = ScalarizeVecRes_BinOp(N); 117 break; 118 } 119 120 // If R is null, the sub-method took care of registering the result. 121 if (R.getNode()) 122 SetScalarizedVector(SDValue(N, ResNo), R); 123} 124 125SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { 126 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 127 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 128 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 129 LHS.getValueType(), LHS, RHS); 130} 131 132SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N, 133 unsigned ResNo) { 134 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); 135 return GetScalarizedVector(Op); 136} 137 138SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) { 139 EVT NewVT = N->getValueType(0).getVectorElementType(); 140 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 141 NewVT, N->getOperand(0)); 142} 143 144SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) { 145 EVT NewVT = N->getValueType(0).getVectorElementType(); 146 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); 147 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(), 148 Op0, DAG.getValueType(NewVT), 149 DAG.getValueType(Op0.getValueType()), 150 N->getOperand(3), 151 N->getOperand(4), 152 cast<CvtRndSatSDNode>(N)->getCvtCode()); 153} 154 155SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 156 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 157 N->getValueType(0).getVectorElementType(), 158 N->getOperand(0), N->getOperand(1)); 159} 160 161SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) { 162 EVT NewVT = N->getValueType(0).getVectorElementType(); 163 SDValue Op = GetScalarizedVector(N->getOperand(0)); 164 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), 165 NewVT, Op, N->getOperand(1)); 166} 167 168SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) { 169 SDValue Op = GetScalarizedVector(N->getOperand(0)); 170 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(), 171 Op.getValueType(), Op, N->getOperand(1)); 172} 173 174SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { 175 // The value to insert may have a wider type than the vector element type, 176 // so be sure to truncate it to the element type if necessary. 177 SDValue Op = N->getOperand(1); 178 EVT EltVT = N->getValueType(0).getVectorElementType(); 179 if (Op.getValueType() != EltVT) 180 // FIXME: Can this happen for floating point types? 181 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op); 182 return Op; 183} 184 185SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { 186 assert(N->isUnindexed() && "Indexed vector load?"); 187 188 SDValue Result = DAG.getLoad(ISD::UNINDEXED, 189 N->getExtensionType(), 190 N->getValueType(0).getVectorElementType(), 191 N->getDebugLoc(), 192 N->getChain(), N->getBasePtr(), 193 DAG.getUNDEF(N->getBasePtr().getValueType()), 194 N->getPointerInfo(), 195 N->getMemoryVT().getVectorElementType(), 196 N->isVolatile(), N->isNonTemporal(), 197 N->getOriginalAlignment()); 198 199 // Legalized the chain result - switch anything that used the old chain to 200 // use the new one. 201 ReplaceValueWith(SDValue(N, 1), Result.getValue(1)); 202 return Result; 203} 204 205SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { 206 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp. 207 EVT DestVT = N->getValueType(0).getVectorElementType(); 208 SDValue Op = GetScalarizedVector(N->getOperand(0)); 209 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op); 210} 211 212SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) { 213 EVT EltVT = N->getValueType(0).getVectorElementType(); 214 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType(); 215 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 216 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT, 217 LHS, DAG.getValueType(ExtVT)); 218} 219 220SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) { 221 // If the operand is wider than the vector element type then it is implicitly 222 // truncated. Make that explicit here. 223 EVT EltVT = N->getValueType(0).getVectorElementType(); 224 SDValue InOp = N->getOperand(0); 225 if (InOp.getValueType() != EltVT) 226 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp); 227 return InOp; 228} 229 230SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) { 231 SDValue LHS = GetScalarizedVector(N->getOperand(1)); 232 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 233 LHS.getValueType(), N->getOperand(0), LHS, 234 GetScalarizedVector(N->getOperand(2))); 235} 236 237SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) { 238 SDValue LHS = GetScalarizedVector(N->getOperand(2)); 239 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(), 240 N->getOperand(0), N->getOperand(1), 241 LHS, GetScalarizedVector(N->getOperand(3)), 242 N->getOperand(4)); 243} 244 245SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) { 246 assert(N->getValueType(0).isVector() == 247 N->getOperand(0).getValueType().isVector() && 248 "Scalar/Vector type mismatch"); 249 250 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N); 251 252 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 253 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 254 DebugLoc DL = N->getDebugLoc(); 255 256 // Turn it into a scalar SETCC. 257 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); 258} 259 260SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { 261 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 262} 263 264SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { 265 // Figure out if the scalar is the LHS or RHS and return it. 266 SDValue Arg = N->getOperand(2).getOperand(0); 267 if (Arg.getOpcode() == ISD::UNDEF) 268 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 269 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue(); 270 return GetScalarizedVector(N->getOperand(Op)); 271} 272 273SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) { 274 assert(N->getValueType(0).isVector() && 275 N->getOperand(0).getValueType().isVector() && 276 "Operand types must be vectors"); 277 278 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 279 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 280 EVT NVT = N->getValueType(0).getVectorElementType(); 281 DebugLoc DL = N->getDebugLoc(); 282 283 // Turn it into a scalar SETCC. 284 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, 285 N->getOperand(2)); 286 // Vectors may have a different boolean contents to scalars. Promote the 287 // value appropriately. 288 ISD::NodeType ExtendCode = 289 TargetLowering::getExtendForContent(TLI.getBooleanContents(true)); 290 return DAG.getNode(ExtendCode, DL, NVT, Res); 291} 292 293 294//===----------------------------------------------------------------------===// 295// Operand Vector Scalarization <1 x ty> -> ty. 296//===----------------------------------------------------------------------===// 297 298bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { 299 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; 300 N->dump(&DAG); 301 dbgs() << "\n"); 302 SDValue Res = SDValue(); 303 304 if (Res.getNode() == 0) { 305 switch (N->getOpcode()) { 306 default: 307#ifndef NDEBUG 308 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": "; 309 N->dump(&DAG); 310 dbgs() << "\n"; 311#endif 312 llvm_unreachable("Do not know how to scalarize this operator's operand!"); 313 case ISD::BITCAST: 314 Res = ScalarizeVecOp_BITCAST(N); 315 break; 316 case ISD::CONCAT_VECTORS: 317 Res = ScalarizeVecOp_CONCAT_VECTORS(N); 318 break; 319 case ISD::EXTRACT_VECTOR_ELT: 320 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); 321 break; 322 case ISD::STORE: 323 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); 324 break; 325 } 326 } 327 328 // If the result is null, the sub-method took care of registering results etc. 329 if (!Res.getNode()) return false; 330 331 // If the result is N, the sub-method updated N in place. Tell the legalizer 332 // core about this. 333 if (Res.getNode() == N) 334 return true; 335 336 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 337 "Invalid operand expansion"); 338 339 ReplaceValueWith(SDValue(N, 0), Res); 340 return false; 341} 342 343/// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs 344/// to be scalarized, it must be <1 x ty>. Convert the element instead. 345SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) { 346 SDValue Elt = GetScalarizedVector(N->getOperand(0)); 347 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 348 N->getValueType(0), Elt); 349} 350 351/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one - 352/// use a BUILD_VECTOR instead. 353SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) { 354 SmallVector<SDValue, 8> Ops(N->getNumOperands()); 355 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 356 Ops[i] = GetScalarizedVector(N->getOperand(i)); 357 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0), 358 &Ops[0], Ops.size()); 359} 360 361/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to 362/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the 363/// index. 364SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 365 SDValue Res = GetScalarizedVector(N->getOperand(0)); 366 if (Res.getValueType() != N->getValueType(0)) 367 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), 368 Res); 369 return Res; 370} 371 372/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be 373/// scalarized, it must be <1 x ty>. Just store the element. 374SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ 375 assert(N->isUnindexed() && "Indexed store of one-element vector?"); 376 assert(OpNo == 1 && "Do not know how to scalarize this operand!"); 377 DebugLoc dl = N->getDebugLoc(); 378 379 if (N->isTruncatingStore()) 380 return DAG.getTruncStore(N->getChain(), dl, 381 GetScalarizedVector(N->getOperand(1)), 382 N->getBasePtr(), N->getPointerInfo(), 383 N->getMemoryVT().getVectorElementType(), 384 N->isVolatile(), N->isNonTemporal(), 385 N->getAlignment()); 386 387 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)), 388 N->getBasePtr(), N->getPointerInfo(), 389 N->isVolatile(), N->isNonTemporal(), 390 N->getOriginalAlignment()); 391} 392 393 394//===----------------------------------------------------------------------===// 395// Result Vector Splitting 396//===----------------------------------------------------------------------===// 397 398/// SplitVectorResult - This method is called when the specified result of the 399/// specified node is found to need vector splitting. At this point, the node 400/// may also have invalid operands or may have other results that need 401/// legalization, we just know that (at least) one result needs vector 402/// splitting. 403void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { 404 DEBUG(dbgs() << "Split node result: "; 405 N->dump(&DAG); 406 dbgs() << "\n"); 407 SDValue Lo, Hi; 408 409 switch (N->getOpcode()) { 410 default: 411#ifndef NDEBUG 412 dbgs() << "SplitVectorResult #" << ResNo << ": "; 413 N->dump(&DAG); 414 dbgs() << "\n"; 415#endif 416 llvm_unreachable("Do not know how to split the result of this operator!"); 417 418 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 419 case ISD::VSELECT: 420 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 421 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 422 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 423 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; 424 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 425 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 426 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; 427 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 428 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; 429 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 430 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break; 431 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 432 case ISD::LOAD: 433 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); 434 break; 435 case ISD::SETCC: 436 SplitVecRes_SETCC(N, Lo, Hi); 437 break; 438 case ISD::VECTOR_SHUFFLE: 439 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); 440 break; 441 442 case ISD::ANY_EXTEND: 443 case ISD::CONVERT_RNDSAT: 444 case ISD::CTLZ: 445 case ISD::CTPOP: 446 case ISD::CTTZ: 447 case ISD::FABS: 448 case ISD::FCEIL: 449 case ISD::FCOS: 450 case ISD::FEXP: 451 case ISD::FEXP2: 452 case ISD::FFLOOR: 453 case ISD::FLOG: 454 case ISD::FLOG10: 455 case ISD::FLOG2: 456 case ISD::FNEARBYINT: 457 case ISD::FNEG: 458 case ISD::FP_EXTEND: 459 case ISD::FP_ROUND: 460 case ISD::FP_TO_SINT: 461 case ISD::FP_TO_UINT: 462 case ISD::FRINT: 463 case ISD::FSIN: 464 case ISD::FSQRT: 465 case ISD::FTRUNC: 466 case ISD::SIGN_EXTEND: 467 case ISD::SINT_TO_FP: 468 case ISD::TRUNCATE: 469 case ISD::UINT_TO_FP: 470 case ISD::ZERO_EXTEND: 471 SplitVecRes_UnaryOp(N, Lo, Hi); 472 break; 473 474 case ISD::ADD: 475 case ISD::SUB: 476 case ISD::MUL: 477 case ISD::FADD: 478 case ISD::FSUB: 479 case ISD::FMUL: 480 case ISD::SDIV: 481 case ISD::UDIV: 482 case ISD::FDIV: 483 case ISD::FPOW: 484 case ISD::AND: 485 case ISD::OR: 486 case ISD::XOR: 487 case ISD::SHL: 488 case ISD::SRA: 489 case ISD::SRL: 490 case ISD::UREM: 491 case ISD::SREM: 492 case ISD::FREM: 493 SplitVecRes_BinOp(N, Lo, Hi); 494 break; 495 } 496 497 // If Lo/Hi is null, the sub-method took care of registering results etc. 498 if (Lo.getNode()) 499 SetSplitVector(SDValue(N, ResNo), Lo, Hi); 500} 501 502void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo, 503 SDValue &Hi) { 504 SDValue LHSLo, LHSHi; 505 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 506 SDValue RHSLo, RHSHi; 507 GetSplitVector(N->getOperand(1), RHSLo, RHSHi); 508 DebugLoc dl = N->getDebugLoc(); 509 510 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo); 511 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi); 512} 513 514void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, 515 SDValue &Hi) { 516 // We know the result is a vector. The input may be either a vector or a 517 // scalar value. 518 EVT LoVT, HiVT; 519 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 520 DebugLoc dl = N->getDebugLoc(); 521 522 SDValue InOp = N->getOperand(0); 523 EVT InVT = InOp.getValueType(); 524 525 // Handle some special cases efficiently. 526 switch (getTypeAction(InVT)) { 527 case TargetLowering::TypeLegal: 528 case TargetLowering::TypePromoteInteger: 529 case TargetLowering::TypeSoftenFloat: 530 case TargetLowering::TypeScalarizeVector: 531 case TargetLowering::TypeWidenVector: 532 break; 533 case TargetLowering::TypeExpandInteger: 534 case TargetLowering::TypeExpandFloat: 535 // A scalar to vector conversion, where the scalar needs expansion. 536 // If the vector is being split in two then we can just convert the 537 // expanded pieces. 538 if (LoVT == HiVT) { 539 GetExpandedOp(InOp, Lo, Hi); 540 if (TLI.isBigEndian()) 541 std::swap(Lo, Hi); 542 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 543 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 544 return; 545 } 546 break; 547 case TargetLowering::TypeSplitVector: 548 // If the input is a vector that needs to be split, convert each split 549 // piece of the input now. 550 GetSplitVector(InOp, Lo, Hi); 551 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 552 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 553 return; 554 } 555 556 // In the general case, convert the input to an integer and split it by hand. 557 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits()); 558 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits()); 559 if (TLI.isBigEndian()) 560 std::swap(LoIntVT, HiIntVT); 561 562 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); 563 564 if (TLI.isBigEndian()) 565 std::swap(Lo, Hi); 566 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 567 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 568} 569 570void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, 571 SDValue &Hi) { 572 EVT LoVT, HiVT; 573 DebugLoc dl = N->getDebugLoc(); 574 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 575 unsigned LoNumElts = LoVT.getVectorNumElements(); 576 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts); 577 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size()); 578 579 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end()); 580 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size()); 581} 582 583void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, 584 SDValue &Hi) { 585 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"); 586 DebugLoc dl = N->getDebugLoc(); 587 unsigned NumSubvectors = N->getNumOperands() / 2; 588 if (NumSubvectors == 1) { 589 Lo = N->getOperand(0); 590 Hi = N->getOperand(1); 591 return; 592 } 593 594 EVT LoVT, HiVT; 595 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 596 597 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); 598 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size()); 599 600 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end()); 601 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size()); 602} 603 604void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, 605 SDValue &Hi) { 606 SDValue Vec = N->getOperand(0); 607 SDValue Idx = N->getOperand(1); 608 DebugLoc dl = N->getDebugLoc(); 609 610 EVT LoVT, HiVT; 611 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 612 613 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); 614 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 615 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, 616 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements())); 617} 618 619void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, 620 SDValue &Hi) { 621 DebugLoc dl = N->getDebugLoc(); 622 GetSplitVector(N->getOperand(0), Lo, Hi); 623 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1)); 624 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1)); 625} 626 627void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo, 628 SDValue &Hi) { 629 SDValue LHSLo, LHSHi; 630 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 631 DebugLoc dl = N->getDebugLoc(); 632 633 EVT LoVT, HiVT; 634 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT); 635 636 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, 637 DAG.getValueType(LoVT)); 638 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, 639 DAG.getValueType(HiVT)); 640} 641 642void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, 643 SDValue &Hi) { 644 SDValue Vec = N->getOperand(0); 645 SDValue Elt = N->getOperand(1); 646 SDValue Idx = N->getOperand(2); 647 DebugLoc dl = N->getDebugLoc(); 648 GetSplitVector(Vec, Lo, Hi); 649 650 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 651 unsigned IdxVal = CIdx->getZExtValue(); 652 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 653 if (IdxVal < LoNumElts) 654 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 655 Lo.getValueType(), Lo, Elt, Idx); 656 else 657 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, 658 DAG.getIntPtrConstant(IdxVal - LoNumElts)); 659 return; 660 } 661 662 // Spill the vector to the stack. 663 EVT VecVT = Vec.getValueType(); 664 EVT EltVT = VecVT.getVectorElementType(); 665 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 666 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 667 MachinePointerInfo(), false, false, 0); 668 669 // Store the new element. This may be larger than the vector element type, 670 // so use a truncating store. 671 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 672 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); 673 unsigned Alignment = 674 TLI.getTargetData()->getPrefTypeAlignment(VecType); 675 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT, 676 false, false, 0); 677 678 // Load the Lo part from the stack slot. 679 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 680 false, false, 0); 681 682 // Increment the pointer to the other part. 683 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; 684 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 685 DAG.getIntPtrConstant(IncrementSize)); 686 687 // Load the Hi part from the stack slot. 688 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 689 false, false, MinAlign(Alignment, IncrementSize)); 690} 691 692void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, 693 SDValue &Hi) { 694 EVT LoVT, HiVT; 695 DebugLoc dl = N->getDebugLoc(); 696 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 697 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0)); 698 Hi = DAG.getUNDEF(HiVT); 699} 700 701void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, 702 SDValue &Hi) { 703 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"); 704 EVT LoVT, HiVT; 705 DebugLoc dl = LD->getDebugLoc(); 706 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); 707 708 ISD::LoadExtType ExtType = LD->getExtensionType(); 709 SDValue Ch = LD->getChain(); 710 SDValue Ptr = LD->getBasePtr(); 711 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 712 EVT MemoryVT = LD->getMemoryVT(); 713 unsigned Alignment = LD->getOriginalAlignment(); 714 bool isVolatile = LD->isVolatile(); 715 bool isNonTemporal = LD->isNonTemporal(); 716 717 EVT LoMemVT, HiMemVT; 718 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 719 720 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, 721 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal, 722 Alignment); 723 724 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 725 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 726 DAG.getIntPtrConstant(IncrementSize)); 727 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, 728 LD->getPointerInfo().getWithOffset(IncrementSize), 729 HiMemVT, isVolatile, isNonTemporal, Alignment); 730 731 // Build a factor node to remember that this load is independent of the 732 // other one. 733 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 734 Hi.getValue(1)); 735 736 // Legalized the chain result - switch anything that used the old chain to 737 // use the new one. 738 ReplaceValueWith(SDValue(LD, 1), Ch); 739} 740 741void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) { 742 assert(N->getValueType(0).isVector() && 743 N->getOperand(0).getValueType().isVector() && 744 "Operand types must be vectors"); 745 746 EVT LoVT, HiVT; 747 DebugLoc DL = N->getDebugLoc(); 748 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 749 750 // Split the input. 751 EVT InVT = N->getOperand(0).getValueType(); 752 SDValue LL, LH, RL, RH; 753 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 754 LoVT.getVectorNumElements()); 755 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 756 DAG.getIntPtrConstant(0)); 757 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 758 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 759 760 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 761 DAG.getIntPtrConstant(0)); 762 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 763 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 764 765 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2)); 766 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2)); 767} 768 769void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, 770 SDValue &Hi) { 771 // Get the dest types - they may not match the input types, e.g. int_to_fp. 772 EVT LoVT, HiVT; 773 DebugLoc dl = N->getDebugLoc(); 774 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 775 776 // If the input also splits, handle it directly for a compile time speedup. 777 // Otherwise split it by hand. 778 EVT InVT = N->getOperand(0).getValueType(); 779 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) { 780 GetSplitVector(N->getOperand(0), Lo, Hi); 781 } else { 782 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 783 LoVT.getVectorNumElements()); 784 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 785 DAG.getIntPtrConstant(0)); 786 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 787 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 788 } 789 790 if (N->getOpcode() == ISD::FP_ROUND) { 791 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1)); 792 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1)); 793 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) { 794 SDValue DTyOpLo = DAG.getValueType(LoVT); 795 SDValue DTyOpHi = DAG.getValueType(HiVT); 796 SDValue STyOpLo = DAG.getValueType(Lo.getValueType()); 797 SDValue STyOpHi = DAG.getValueType(Hi.getValueType()); 798 SDValue RndOp = N->getOperand(3); 799 SDValue SatOp = N->getOperand(4); 800 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 801 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp, 802 CvtCode); 803 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp, 804 CvtCode); 805 } else { 806 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo); 807 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi); 808 } 809} 810 811void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, 812 SDValue &Lo, SDValue &Hi) { 813 // The low and high parts of the original input give four input vectors. 814 SDValue Inputs[4]; 815 DebugLoc dl = N->getDebugLoc(); 816 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]); 817 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]); 818 EVT NewVT = Inputs[0].getValueType(); 819 unsigned NewElts = NewVT.getVectorNumElements(); 820 821 // If Lo or Hi uses elements from at most two of the four input vectors, then 822 // express it as a vector shuffle of those two inputs. Otherwise extract the 823 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. 824 SmallVector<int, 16> Ops; 825 for (unsigned High = 0; High < 2; ++High) { 826 SDValue &Output = High ? Hi : Lo; 827 828 // Build a shuffle mask for the output, discovering on the fly which 829 // input vectors to use as shuffle operands (recorded in InputUsed). 830 // If building a suitable shuffle vector proves too hard, then bail 831 // out with useBuildVector set. 832 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered. 833 unsigned FirstMaskIdx = High * NewElts; 834 bool useBuildVector = false; 835 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 836 // The mask element. This indexes into the input. 837 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 838 839 // The input vector this mask element indexes into. 840 unsigned Input = (unsigned)Idx / NewElts; 841 842 if (Input >= array_lengthof(Inputs)) { 843 // The mask element does not index into any input vector. 844 Ops.push_back(-1); 845 continue; 846 } 847 848 // Turn the index into an offset from the start of the input vector. 849 Idx -= Input * NewElts; 850 851 // Find or create a shuffle vector operand to hold this input. 852 unsigned OpNo; 853 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 854 if (InputUsed[OpNo] == Input) { 855 // This input vector is already an operand. 856 break; 857 } else if (InputUsed[OpNo] == -1U) { 858 // Create a new operand for this input vector. 859 InputUsed[OpNo] = Input; 860 break; 861 } 862 } 863 864 if (OpNo >= array_lengthof(InputUsed)) { 865 // More than two input vectors used! Give up on trying to create a 866 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 867 useBuildVector = true; 868 break; 869 } 870 871 // Add the mask index for the new shuffle vector. 872 Ops.push_back(Idx + OpNo * NewElts); 873 } 874 875 if (useBuildVector) { 876 EVT EltVT = NewVT.getVectorElementType(); 877 SmallVector<SDValue, 16> SVOps; 878 879 // Extract the input elements by hand. 880 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 881 // The mask element. This indexes into the input. 882 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 883 884 // The input vector this mask element indexes into. 885 unsigned Input = (unsigned)Idx / NewElts; 886 887 if (Input >= array_lengthof(Inputs)) { 888 // The mask element is "undef" or indexes off the end of the input. 889 SVOps.push_back(DAG.getUNDEF(EltVT)); 890 continue; 891 } 892 893 // Turn the index into an offset from the start of the input vector. 894 Idx -= Input * NewElts; 895 896 // Extract the vector element by hand. 897 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 898 Inputs[Input], DAG.getIntPtrConstant(Idx))); 899 } 900 901 // Construct the Lo/Hi output using a BUILD_VECTOR. 902 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size()); 903 } else if (InputUsed[0] == -1U) { 904 // No input vectors were used! The result is undefined. 905 Output = DAG.getUNDEF(NewVT); 906 } else { 907 SDValue Op0 = Inputs[InputUsed[0]]; 908 // If only one input was used, use an undefined vector for the other. 909 SDValue Op1 = InputUsed[1] == -1U ? 910 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]]; 911 // At least one input vector was used. Create a new shuffle vector. 912 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]); 913 } 914 915 Ops.clear(); 916 } 917} 918 919 920//===----------------------------------------------------------------------===// 921// Operand Vector Splitting 922//===----------------------------------------------------------------------===// 923 924/// SplitVectorOperand - This method is called when the specified operand of the 925/// specified node is found to need vector splitting. At this point, all of the 926/// result types of the node are known to be legal, but other operands of the 927/// node may need legalization as well as the specified one. 928bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { 929 DEBUG(dbgs() << "Split node operand: "; 930 N->dump(&DAG); 931 dbgs() << "\n"); 932 SDValue Res = SDValue(); 933 934 if (Res.getNode() == 0) { 935 switch (N->getOpcode()) { 936 default: 937#ifndef NDEBUG 938 dbgs() << "SplitVectorOperand Op #" << OpNo << ": "; 939 N->dump(&DAG); 940 dbgs() << "\n"; 941#endif 942 llvm_unreachable("Do not know how to split this operator's operand!"); 943 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; 944 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break; 945 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; 946 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; 947 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; 948 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; 949 case ISD::STORE: 950 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo); 951 break; 952 953 case ISD::CTTZ: 954 case ISD::CTLZ: 955 case ISD::CTPOP: 956 case ISD::FP_EXTEND: 957 case ISD::FP_TO_SINT: 958 case ISD::FP_TO_UINT: 959 case ISD::SINT_TO_FP: 960 case ISD::UINT_TO_FP: 961 case ISD::FTRUNC: 962 case ISD::TRUNCATE: 963 case ISD::SIGN_EXTEND: 964 case ISD::ZERO_EXTEND: 965 case ISD::ANY_EXTEND: 966 Res = SplitVecOp_UnaryOp(N); 967 break; 968 } 969 } 970 971 // If the result is null, the sub-method took care of registering results etc. 972 if (!Res.getNode()) return false; 973 974 // If the result is N, the sub-method updated N in place. Tell the legalizer 975 // core about this. 976 if (Res.getNode() == N) 977 return true; 978 979 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 980 "Invalid operand expansion"); 981 982 ReplaceValueWith(SDValue(N, 0), Res); 983 return false; 984} 985 986SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) { 987 // The result has a legal vector type, but the input needs splitting. 988 EVT ResVT = N->getValueType(0); 989 SDValue Lo, Hi; 990 DebugLoc dl = N->getDebugLoc(); 991 GetSplitVector(N->getOperand(0), Lo, Hi); 992 EVT InVT = Lo.getValueType(); 993 994 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 995 InVT.getVectorNumElements()); 996 997 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); 998 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); 999 1000 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); 1001} 1002 1003SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) { 1004 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will 1005 // end up being split all the way down to individual components. Convert the 1006 // split pieces into integers and reassemble. 1007 SDValue Lo, Hi; 1008 GetSplitVector(N->getOperand(0), Lo, Hi); 1009 Lo = BitConvertToInteger(Lo); 1010 Hi = BitConvertToInteger(Hi); 1011 1012 if (TLI.isBigEndian()) 1013 std::swap(Lo, Hi); 1014 1015 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0), 1016 JoinIntegers(Lo, Hi)); 1017} 1018 1019SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 1020 // We know that the extracted result type is legal. 1021 EVT SubVT = N->getValueType(0); 1022 SDValue Idx = N->getOperand(1); 1023 DebugLoc dl = N->getDebugLoc(); 1024 SDValue Lo, Hi; 1025 GetSplitVector(N->getOperand(0), Lo, Hi); 1026 1027 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1028 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1029 1030 if (IdxVal < LoElts) { 1031 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && 1032 "Extracted subvector crosses vector split!"); 1033 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); 1034 } else { 1035 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, 1036 DAG.getConstant(IdxVal - LoElts, Idx.getValueType())); 1037 } 1038} 1039 1040SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 1041 SDValue Vec = N->getOperand(0); 1042 SDValue Idx = N->getOperand(1); 1043 EVT VecVT = Vec.getValueType(); 1044 1045 if (isa<ConstantSDNode>(Idx)) { 1046 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1047 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); 1048 1049 SDValue Lo, Hi; 1050 GetSplitVector(Vec, Lo, Hi); 1051 1052 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1053 1054 if (IdxVal < LoElts) 1055 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0); 1056 return SDValue(DAG.UpdateNodeOperands(N, Hi, 1057 DAG.getConstant(IdxVal - LoElts, 1058 Idx.getValueType())), 0); 1059 } 1060 1061 // Store the vector to the stack. 1062 EVT EltVT = VecVT.getVectorElementType(); 1063 DebugLoc dl = N->getDebugLoc(); 1064 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 1065 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 1066 MachinePointerInfo(), false, false, 0); 1067 1068 // Load back the required element. 1069 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 1070 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, 1071 MachinePointerInfo(), EltVT, false, false, 0); 1072} 1073 1074SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { 1075 assert(N->isUnindexed() && "Indexed store of vector?"); 1076 assert(OpNo == 1 && "Can only split the stored value"); 1077 DebugLoc DL = N->getDebugLoc(); 1078 1079 bool isTruncating = N->isTruncatingStore(); 1080 SDValue Ch = N->getChain(); 1081 SDValue Ptr = N->getBasePtr(); 1082 EVT MemoryVT = N->getMemoryVT(); 1083 unsigned Alignment = N->getOriginalAlignment(); 1084 bool isVol = N->isVolatile(); 1085 bool isNT = N->isNonTemporal(); 1086 SDValue Lo, Hi; 1087 GetSplitVector(N->getOperand(1), Lo, Hi); 1088 1089 EVT LoMemVT, HiMemVT; 1090 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 1091 1092 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 1093 1094 if (isTruncating) 1095 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1096 LoMemVT, isVol, isNT, Alignment); 1097 else 1098 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1099 isVol, isNT, Alignment); 1100 1101 // Increment the pointer to the other half. 1102 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, 1103 DAG.getIntPtrConstant(IncrementSize)); 1104 1105 if (isTruncating) 1106 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr, 1107 N->getPointerInfo().getWithOffset(IncrementSize), 1108 HiMemVT, isVol, isNT, Alignment); 1109 else 1110 Hi = DAG.getStore(Ch, DL, Hi, Ptr, 1111 N->getPointerInfo().getWithOffset(IncrementSize), 1112 isVol, isNT, Alignment); 1113 1114 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi); 1115} 1116 1117SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) { 1118 DebugLoc DL = N->getDebugLoc(); 1119 1120 // The input operands all must have the same type, and we know the result the 1121 // result type is valid. Convert this to a buildvector which extracts all the 1122 // input elements. 1123 // TODO: If the input elements are power-two vectors, we could convert this to 1124 // a new CONCAT_VECTORS node with elements that are half-wide. 1125 SmallVector<SDValue, 32> Elts; 1126 EVT EltVT = N->getValueType(0).getVectorElementType(); 1127 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1128 SDValue Op = N->getOperand(op); 1129 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements(); 1130 i != e; ++i) { 1131 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, 1132 Op, DAG.getIntPtrConstant(i))); 1133 1134 } 1135 } 1136 1137 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), 1138 &Elts[0], Elts.size()); 1139} 1140 1141SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { 1142 assert(N->getValueType(0).isVector() && 1143 N->getOperand(0).getValueType().isVector() && 1144 "Operand types must be vectors"); 1145 // The result has a legal vector type, but the input needs splitting. 1146 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes; 1147 DebugLoc DL = N->getDebugLoc(); 1148 GetSplitVector(N->getOperand(0), Lo0, Hi0); 1149 GetSplitVector(N->getOperand(1), Lo1, Hi1); 1150 unsigned PartElements = Lo0.getValueType().getVectorNumElements(); 1151 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements); 1152 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements); 1153 1154 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); 1155 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); 1156 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes); 1157 return PromoteTargetBoolean(Con, N->getValueType(0)); 1158} 1159 1160 1161SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) { 1162 // The result has a legal vector type, but the input needs splitting. 1163 EVT ResVT = N->getValueType(0); 1164 SDValue Lo, Hi; 1165 DebugLoc DL = N->getDebugLoc(); 1166 GetSplitVector(N->getOperand(0), Lo, Hi); 1167 EVT InVT = Lo.getValueType(); 1168 1169 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1170 InVT.getVectorNumElements()); 1171 1172 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); 1173 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); 1174 1175 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); 1176} 1177 1178 1179 1180//===----------------------------------------------------------------------===// 1181// Result Vector Widening 1182//===----------------------------------------------------------------------===// 1183 1184void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { 1185 DEBUG(dbgs() << "Widen node result " << ResNo << ": "; 1186 N->dump(&DAG); 1187 dbgs() << "\n"); 1188 1189 // See if the target wants to custom widen this node. 1190 if (CustomWidenLowerNode(N, N->getValueType(ResNo))) 1191 return; 1192 1193 SDValue Res = SDValue(); 1194 switch (N->getOpcode()) { 1195 default: 1196#ifndef NDEBUG 1197 dbgs() << "WidenVectorResult #" << ResNo << ": "; 1198 N->dump(&DAG); 1199 dbgs() << "\n"; 1200#endif 1201 llvm_unreachable("Do not know how to widen the result of this operator!"); 1202 1203 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break; 1204 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break; 1205 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; 1206 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break; 1207 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break; 1208 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; 1209 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break; 1210 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; 1211 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break; 1212 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break; 1213 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break; 1214 case ISD::VSELECT: 1215 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break; 1216 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; 1217 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; 1218 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break; 1219 case ISD::VECTOR_SHUFFLE: 1220 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N)); 1221 break; 1222 case ISD::ADD: 1223 case ISD::AND: 1224 case ISD::BSWAP: 1225 case ISD::FADD: 1226 case ISD::FCOPYSIGN: 1227 case ISD::FDIV: 1228 case ISD::FMUL: 1229 case ISD::FPOW: 1230 case ISD::FREM: 1231 case ISD::FSUB: 1232 case ISD::MUL: 1233 case ISD::MULHS: 1234 case ISD::MULHU: 1235 case ISD::OR: 1236 case ISD::SDIV: 1237 case ISD::SREM: 1238 case ISD::UDIV: 1239 case ISD::UREM: 1240 case ISD::SUB: 1241 case ISD::XOR: 1242 Res = WidenVecRes_Binary(N); 1243 break; 1244 1245 case ISD::FPOWI: 1246 Res = WidenVecRes_POWI(N); 1247 break; 1248 1249 case ISD::SHL: 1250 case ISD::SRA: 1251 case ISD::SRL: 1252 Res = WidenVecRes_Shift(N); 1253 break; 1254 1255 case ISD::ANY_EXTEND: 1256 case ISD::FP_EXTEND: 1257 case ISD::FP_ROUND: 1258 case ISD::FP_TO_SINT: 1259 case ISD::FP_TO_UINT: 1260 case ISD::SIGN_EXTEND: 1261 case ISD::SINT_TO_FP: 1262 case ISD::TRUNCATE: 1263 case ISD::UINT_TO_FP: 1264 case ISD::ZERO_EXTEND: 1265 Res = WidenVecRes_Convert(N); 1266 break; 1267 1268 case ISD::CTLZ: 1269 case ISD::CTPOP: 1270 case ISD::CTTZ: 1271 case ISD::FABS: 1272 case ISD::FCEIL: 1273 case ISD::FCOS: 1274 case ISD::FEXP: 1275 case ISD::FEXP2: 1276 case ISD::FFLOOR: 1277 case ISD::FLOG: 1278 case ISD::FLOG10: 1279 case ISD::FLOG2: 1280 case ISD::FNEARBYINT: 1281 case ISD::FNEG: 1282 case ISD::FRINT: 1283 case ISD::FSIN: 1284 case ISD::FSQRT: 1285 case ISD::FTRUNC: 1286 Res = WidenVecRes_Unary(N); 1287 break; 1288 } 1289 1290 // If Res is null, the sub-method took care of registering the result. 1291 if (Res.getNode()) 1292 SetWidenedVector(SDValue(N, ResNo), Res); 1293} 1294 1295SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) { 1296 // Binary op widening. 1297 unsigned Opcode = N->getOpcode(); 1298 DebugLoc dl = N->getDebugLoc(); 1299 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1300 EVT WidenEltVT = WidenVT.getVectorElementType(); 1301 EVT VT = WidenVT; 1302 unsigned NumElts = VT.getVectorNumElements(); 1303 while (!TLI.isTypeLegal(VT) && NumElts != 1) { 1304 NumElts = NumElts / 2; 1305 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1306 } 1307 1308 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) { 1309 // Operation doesn't trap so just widen as normal. 1310 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1311 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1312 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2); 1313 } 1314 1315 // No legal vector version so unroll the vector operation and then widen. 1316 if (NumElts == 1) 1317 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()); 1318 1319 // Since the operation can trap, apply operation on the original vector. 1320 EVT MaxVT = VT; 1321 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1322 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1323 unsigned CurNumElts = N->getValueType(0).getVectorNumElements(); 1324 1325 SmallVector<SDValue, 16> ConcatOps(CurNumElts); 1326 unsigned ConcatEnd = 0; // Current ConcatOps index. 1327 int Idx = 0; // Current Idx into input vectors. 1328 1329 // NumElts := greatest legal vector size (at most WidenVT) 1330 // while (orig. vector has unhandled elements) { 1331 // take munches of size NumElts from the beginning and add to ConcatOps 1332 // NumElts := next smaller supported vector size or 1 1333 // } 1334 while (CurNumElts != 0) { 1335 while (CurNumElts >= NumElts) { 1336 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, 1337 DAG.getIntPtrConstant(Idx)); 1338 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, 1339 DAG.getIntPtrConstant(Idx)); 1340 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2); 1341 Idx += NumElts; 1342 CurNumElts -= NumElts; 1343 } 1344 do { 1345 NumElts = NumElts / 2; 1346 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1347 } while (!TLI.isTypeLegal(VT) && NumElts != 1); 1348 1349 if (NumElts == 1) { 1350 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) { 1351 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1352 InOp1, DAG.getIntPtrConstant(Idx)); 1353 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1354 InOp2, DAG.getIntPtrConstant(Idx)); 1355 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT, 1356 EOp1, EOp2); 1357 } 1358 CurNumElts = 0; 1359 } 1360 } 1361 1362 // Check to see if we have a single operation with the widen type. 1363 if (ConcatEnd == 1) { 1364 VT = ConcatOps[0].getValueType(); 1365 if (VT == WidenVT) 1366 return ConcatOps[0]; 1367 } 1368 1369 // while (Some element of ConcatOps is not of type MaxVT) { 1370 // From the end of ConcatOps, collect elements of the same type and put 1371 // them into an op of the next larger supported type 1372 // } 1373 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) { 1374 Idx = ConcatEnd - 1; 1375 VT = ConcatOps[Idx--].getValueType(); 1376 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT) 1377 Idx--; 1378 1379 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1; 1380 EVT NextVT; 1381 do { 1382 NextSize *= 2; 1383 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize); 1384 } while (!TLI.isTypeLegal(NextVT)); 1385 1386 if (!VT.isVector()) { 1387 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT 1388 SDValue VecOp = DAG.getUNDEF(NextVT); 1389 unsigned NumToInsert = ConcatEnd - Idx - 1; 1390 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) { 1391 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, 1392 ConcatOps[OpIdx], DAG.getIntPtrConstant(i)); 1393 } 1394 ConcatOps[Idx+1] = VecOp; 1395 ConcatEnd = Idx + 2; 1396 } else { 1397 // Vector type, create a CONCAT_VECTORS of type NextVT 1398 SDValue undefVec = DAG.getUNDEF(VT); 1399 unsigned OpsToConcat = NextSize/VT.getVectorNumElements(); 1400 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat); 1401 unsigned RealVals = ConcatEnd - Idx - 1; 1402 unsigned SubConcatEnd = 0; 1403 unsigned SubConcatIdx = Idx + 1; 1404 while (SubConcatEnd < RealVals) 1405 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx]; 1406 while (SubConcatEnd < OpsToConcat) 1407 SubConcatOps[SubConcatEnd++] = undefVec; 1408 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1409 NextVT, &SubConcatOps[0], 1410 OpsToConcat); 1411 ConcatEnd = SubConcatIdx + 1; 1412 } 1413 } 1414 1415 // Check to see if we have a single operation with the widen type. 1416 if (ConcatEnd == 1) { 1417 VT = ConcatOps[0].getValueType(); 1418 if (VT == WidenVT) 1419 return ConcatOps[0]; 1420 } 1421 1422 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT 1423 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements(); 1424 if (NumOps != ConcatEnd ) { 1425 SDValue UndefVal = DAG.getUNDEF(MaxVT); 1426 for (unsigned j = ConcatEnd; j < NumOps; ++j) 1427 ConcatOps[j] = UndefVal; 1428 } 1429 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps); 1430} 1431 1432SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { 1433 SDValue InOp = N->getOperand(0); 1434 DebugLoc DL = N->getDebugLoc(); 1435 1436 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1437 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1438 1439 EVT InVT = InOp.getValueType(); 1440 EVT InEltVT = InVT.getVectorElementType(); 1441 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1442 1443 unsigned Opcode = N->getOpcode(); 1444 unsigned InVTNumElts = InVT.getVectorNumElements(); 1445 1446 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1447 InOp = GetWidenedVector(N->getOperand(0)); 1448 InVT = InOp.getValueType(); 1449 InVTNumElts = InVT.getVectorNumElements(); 1450 if (InVTNumElts == WidenNumElts) { 1451 if (N->getNumOperands() == 1) 1452 return DAG.getNode(Opcode, DL, WidenVT, InOp); 1453 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1)); 1454 } 1455 } 1456 1457 if (TLI.isTypeLegal(InWidenVT)) { 1458 // Because the result and the input are different vector types, widening 1459 // the result could create a legal type but widening the input might make 1460 // it an illegal type that might lead to repeatedly splitting the input 1461 // and then widening it. To avoid this, we widen the input only if 1462 // it results in a legal type. 1463 if (WidenNumElts % InVTNumElts == 0) { 1464 // Widen the input and call convert on the widened input vector. 1465 unsigned NumConcat = WidenNumElts/InVTNumElts; 1466 SmallVector<SDValue, 16> Ops(NumConcat); 1467 Ops[0] = InOp; 1468 SDValue UndefVal = DAG.getUNDEF(InVT); 1469 for (unsigned i = 1; i != NumConcat; ++i) 1470 Ops[i] = UndefVal; 1471 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, 1472 &Ops[0], NumConcat); 1473 if (N->getNumOperands() == 1) 1474 return DAG.getNode(Opcode, DL, WidenVT, InVec); 1475 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1)); 1476 } 1477 1478 if (InVTNumElts % WidenNumElts == 0) { 1479 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, 1480 InOp, DAG.getIntPtrConstant(0)); 1481 // Extract the input and convert the shorten input vector. 1482 if (N->getNumOperands() == 1) 1483 return DAG.getNode(Opcode, DL, WidenVT, InVal); 1484 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1)); 1485 } 1486 } 1487 1488 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1489 SmallVector<SDValue, 16> Ops(WidenNumElts); 1490 EVT EltVT = WidenVT.getVectorElementType(); 1491 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1492 unsigned i; 1493 for (i=0; i < MinElts; ++i) { 1494 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp, 1495 DAG.getIntPtrConstant(i)); 1496 if (N->getNumOperands() == 1) 1497 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val); 1498 else 1499 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1)); 1500 } 1501 1502 SDValue UndefVal = DAG.getUNDEF(EltVT); 1503 for (; i < WidenNumElts; ++i) 1504 Ops[i] = UndefVal; 1505 1506 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts); 1507} 1508 1509SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) { 1510 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1511 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1512 SDValue ShOp = N->getOperand(1); 1513 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1514} 1515 1516SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) { 1517 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1518 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1519 SDValue ShOp = N->getOperand(1); 1520 1521 EVT ShVT = ShOp.getValueType(); 1522 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) { 1523 ShOp = GetWidenedVector(ShOp); 1524 ShVT = ShOp.getValueType(); 1525 } 1526 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(), 1527 ShVT.getVectorElementType(), 1528 WidenVT.getVectorNumElements()); 1529 if (ShVT != ShWidenVT) 1530 ShOp = ModifyToType(ShOp, ShWidenVT); 1531 1532 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1533} 1534 1535SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) { 1536 // Unary op widening. 1537 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1538 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1539 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp); 1540} 1541 1542SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) { 1543 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1544 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), 1545 cast<VTSDNode>(N->getOperand(1))->getVT() 1546 .getVectorElementType(), 1547 WidenVT.getVectorNumElements()); 1548 SDValue WidenLHS = GetWidenedVector(N->getOperand(0)); 1549 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 1550 WidenVT, WidenLHS, DAG.getValueType(ExtVT)); 1551} 1552 1553SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) { 1554 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo); 1555 return GetWidenedVector(WidenVec); 1556} 1557 1558SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) { 1559 SDValue InOp = N->getOperand(0); 1560 EVT InVT = InOp.getValueType(); 1561 EVT VT = N->getValueType(0); 1562 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1563 DebugLoc dl = N->getDebugLoc(); 1564 1565 switch (getTypeAction(InVT)) { 1566 default: 1567 assert(false && "Unknown type action!"); 1568 break; 1569 case TargetLowering::TypeLegal: 1570 break; 1571 case TargetLowering::TypePromoteInteger: 1572 // If the InOp is promoted to the same size, convert it. Otherwise, 1573 // fall out of the switch and widen the promoted input. 1574 InOp = GetPromotedInteger(InOp); 1575 InVT = InOp.getValueType(); 1576 if (WidenVT.bitsEq(InVT)) 1577 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1578 break; 1579 case TargetLowering::TypeSoftenFloat: 1580 case TargetLowering::TypeExpandInteger: 1581 case TargetLowering::TypeExpandFloat: 1582 case TargetLowering::TypeScalarizeVector: 1583 case TargetLowering::TypeSplitVector: 1584 break; 1585 case TargetLowering::TypeWidenVector: 1586 // If the InOp is widened to the same size, convert it. Otherwise, fall 1587 // out of the switch and widen the widened input. 1588 InOp = GetWidenedVector(InOp); 1589 InVT = InOp.getValueType(); 1590 if (WidenVT.bitsEq(InVT)) 1591 // The input widens to the same size. Convert to the widen value. 1592 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1593 break; 1594 } 1595 1596 unsigned WidenSize = WidenVT.getSizeInBits(); 1597 unsigned InSize = InVT.getSizeInBits(); 1598 // x86mmx is not an acceptable vector element type, so don't try. 1599 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) { 1600 // Determine new input vector type. The new input vector type will use 1601 // the same element type (if its a vector) or use the input type as a 1602 // vector. It is the same size as the type to widen to. 1603 EVT NewInVT; 1604 unsigned NewNumElts = WidenSize / InSize; 1605 if (InVT.isVector()) { 1606 EVT InEltVT = InVT.getVectorElementType(); 1607 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, 1608 WidenSize / InEltVT.getSizeInBits()); 1609 } else { 1610 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts); 1611 } 1612 1613 if (TLI.isTypeLegal(NewInVT)) { 1614 // Because the result and the input are different vector types, widening 1615 // the result could create a legal type but widening the input might make 1616 // it an illegal type that might lead to repeatedly splitting the input 1617 // and then widening it. To avoid this, we widen the input only if 1618 // it results in a legal type. 1619 SmallVector<SDValue, 16> Ops(NewNumElts); 1620 SDValue UndefVal = DAG.getUNDEF(InVT); 1621 Ops[0] = InOp; 1622 for (unsigned i = 1; i < NewNumElts; ++i) 1623 Ops[i] = UndefVal; 1624 1625 SDValue NewVec; 1626 if (InVT.isVector()) 1627 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1628 NewInVT, &Ops[0], NewNumElts); 1629 else 1630 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, 1631 NewInVT, &Ops[0], NewNumElts); 1632 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec); 1633 } 1634 } 1635 1636 return CreateStackStoreLoad(InOp, WidenVT); 1637} 1638 1639SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) { 1640 DebugLoc dl = N->getDebugLoc(); 1641 // Build a vector with undefined for the new nodes. 1642 EVT VT = N->getValueType(0); 1643 EVT EltVT = VT.getVectorElementType(); 1644 unsigned NumElts = VT.getVectorNumElements(); 1645 1646 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1647 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1648 1649 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end()); 1650 NewOps.reserve(WidenNumElts); 1651 for (unsigned i = NumElts; i < WidenNumElts; ++i) 1652 NewOps.push_back(DAG.getUNDEF(EltVT)); 1653 1654 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size()); 1655} 1656 1657SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) { 1658 EVT InVT = N->getOperand(0).getValueType(); 1659 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1660 DebugLoc dl = N->getDebugLoc(); 1661 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1662 unsigned NumInElts = InVT.getVectorNumElements(); 1663 unsigned NumOperands = N->getNumOperands(); 1664 1665 bool InputWidened = false; // Indicates we need to widen the input. 1666 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) { 1667 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) { 1668 // Add undef vectors to widen to correct length. 1669 unsigned NumConcat = WidenVT.getVectorNumElements() / 1670 InVT.getVectorNumElements(); 1671 SDValue UndefVal = DAG.getUNDEF(InVT); 1672 SmallVector<SDValue, 16> Ops(NumConcat); 1673 for (unsigned i=0; i < NumOperands; ++i) 1674 Ops[i] = N->getOperand(i); 1675 for (unsigned i = NumOperands; i != NumConcat; ++i) 1676 Ops[i] = UndefVal; 1677 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat); 1678 } 1679 } else { 1680 InputWidened = true; 1681 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) { 1682 // The inputs and the result are widen to the same value. 1683 unsigned i; 1684 for (i=1; i < NumOperands; ++i) 1685 if (N->getOperand(i).getOpcode() != ISD::UNDEF) 1686 break; 1687 1688 if (i == NumOperands) 1689 // Everything but the first operand is an UNDEF so just return the 1690 // widened first operand. 1691 return GetWidenedVector(N->getOperand(0)); 1692 1693 if (NumOperands == 2) { 1694 // Replace concat of two operands with a shuffle. 1695 SmallVector<int, 16> MaskOps(WidenNumElts, -1); 1696 for (unsigned i = 0; i < NumInElts; ++i) { 1697 MaskOps[i] = i; 1698 MaskOps[i + NumInElts] = i + WidenNumElts; 1699 } 1700 return DAG.getVectorShuffle(WidenVT, dl, 1701 GetWidenedVector(N->getOperand(0)), 1702 GetWidenedVector(N->getOperand(1)), 1703 &MaskOps[0]); 1704 } 1705 } 1706 } 1707 1708 // Fall back to use extracts and build vector. 1709 EVT EltVT = WidenVT.getVectorElementType(); 1710 SmallVector<SDValue, 16> Ops(WidenNumElts); 1711 unsigned Idx = 0; 1712 for (unsigned i=0; i < NumOperands; ++i) { 1713 SDValue InOp = N->getOperand(i); 1714 if (InputWidened) 1715 InOp = GetWidenedVector(InOp); 1716 for (unsigned j=0; j < NumInElts; ++j) 1717 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1718 DAG.getIntPtrConstant(j)); 1719 } 1720 SDValue UndefVal = DAG.getUNDEF(EltVT); 1721 for (; Idx < WidenNumElts; ++Idx) 1722 Ops[Idx] = UndefVal; 1723 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1724} 1725 1726SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { 1727 DebugLoc dl = N->getDebugLoc(); 1728 SDValue InOp = N->getOperand(0); 1729 SDValue RndOp = N->getOperand(3); 1730 SDValue SatOp = N->getOperand(4); 1731 1732 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1733 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1734 1735 EVT InVT = InOp.getValueType(); 1736 EVT InEltVT = InVT.getVectorElementType(); 1737 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1738 1739 SDValue DTyOp = DAG.getValueType(WidenVT); 1740 SDValue STyOp = DAG.getValueType(InWidenVT); 1741 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 1742 1743 unsigned InVTNumElts = InVT.getVectorNumElements(); 1744 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1745 InOp = GetWidenedVector(InOp); 1746 InVT = InOp.getValueType(); 1747 InVTNumElts = InVT.getVectorNumElements(); 1748 if (InVTNumElts == WidenNumElts) 1749 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1750 SatOp, CvtCode); 1751 } 1752 1753 if (TLI.isTypeLegal(InWidenVT)) { 1754 // Because the result and the input are different vector types, widening 1755 // the result could create a legal type but widening the input might make 1756 // it an illegal type that might lead to repeatedly splitting the input 1757 // and then widening it. To avoid this, we widen the input only if 1758 // it results in a legal type. 1759 if (WidenNumElts % InVTNumElts == 0) { 1760 // Widen the input and call convert on the widened input vector. 1761 unsigned NumConcat = WidenNumElts/InVTNumElts; 1762 SmallVector<SDValue, 16> Ops(NumConcat); 1763 Ops[0] = InOp; 1764 SDValue UndefVal = DAG.getUNDEF(InVT); 1765 for (unsigned i = 1; i != NumConcat; ++i) 1766 Ops[i] = UndefVal; 1767 1768 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat); 1769 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1770 SatOp, CvtCode); 1771 } 1772 1773 if (InVTNumElts % WidenNumElts == 0) { 1774 // Extract the input and convert the shorten input vector. 1775 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp, 1776 DAG.getIntPtrConstant(0)); 1777 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1778 SatOp, CvtCode); 1779 } 1780 } 1781 1782 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1783 SmallVector<SDValue, 16> Ops(WidenNumElts); 1784 EVT EltVT = WidenVT.getVectorElementType(); 1785 DTyOp = DAG.getValueType(EltVT); 1786 STyOp = DAG.getValueType(InEltVT); 1787 1788 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1789 unsigned i; 1790 for (i=0; i < MinElts; ++i) { 1791 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 1792 DAG.getIntPtrConstant(i)); 1793 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp, 1794 SatOp, CvtCode); 1795 } 1796 1797 SDValue UndefVal = DAG.getUNDEF(EltVT); 1798 for (; i < WidenNumElts; ++i) 1799 Ops[i] = UndefVal; 1800 1801 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1802} 1803 1804SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 1805 EVT VT = N->getValueType(0); 1806 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1807 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1808 SDValue InOp = N->getOperand(0); 1809 SDValue Idx = N->getOperand(1); 1810 DebugLoc dl = N->getDebugLoc(); 1811 1812 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 1813 InOp = GetWidenedVector(InOp); 1814 1815 EVT InVT = InOp.getValueType(); 1816 1817 // Check if we can just return the input vector after widening. 1818 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1819 if (IdxVal == 0 && InVT == WidenVT) 1820 return InOp; 1821 1822 // Check if we can extract from the vector. 1823 unsigned InNumElts = InVT.getVectorNumElements(); 1824 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts) 1825 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx); 1826 1827 // We could try widening the input to the right length but for now, extract 1828 // the original elements, fill the rest with undefs and build a vector. 1829 SmallVector<SDValue, 16> Ops(WidenNumElts); 1830 EVT EltVT = VT.getVectorElementType(); 1831 unsigned NumElts = VT.getVectorNumElements(); 1832 unsigned i; 1833 for (i=0; i < NumElts; ++i) 1834 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1835 DAG.getIntPtrConstant(IdxVal+i)); 1836 1837 SDValue UndefVal = DAG.getUNDEF(EltVT); 1838 for (; i < WidenNumElts; ++i) 1839 Ops[i] = UndefVal; 1840 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1841} 1842 1843SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) { 1844 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1845 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(), 1846 InOp.getValueType(), InOp, 1847 N->getOperand(1), N->getOperand(2)); 1848} 1849 1850SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) { 1851 LoadSDNode *LD = cast<LoadSDNode>(N); 1852 ISD::LoadExtType ExtType = LD->getExtensionType(); 1853 1854 SDValue Result; 1855 SmallVector<SDValue, 16> LdChain; // Chain for the series of load 1856 if (ExtType != ISD::NON_EXTLOAD) 1857 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); 1858 else 1859 Result = GenWidenVectorLoads(LdChain, LD); 1860 1861 // If we generate a single load, we can use that for the chain. Otherwise, 1862 // build a factor node to remember the multiple loads are independent and 1863 // chain to that. 1864 SDValue NewChain; 1865 if (LdChain.size() == 1) 1866 NewChain = LdChain[0]; 1867 else 1868 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other, 1869 &LdChain[0], LdChain.size()); 1870 1871 // Modified the chain - switch anything that used the old chain to use 1872 // the new one. 1873 ReplaceValueWith(SDValue(N, 1), NewChain); 1874 1875 return Result; 1876} 1877 1878SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) { 1879 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1880 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(), 1881 WidenVT, N->getOperand(0)); 1882} 1883 1884SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) { 1885 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1886 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1887 1888 SDValue Cond1 = N->getOperand(0); 1889 EVT CondVT = Cond1.getValueType(); 1890 if (CondVT.isVector()) { 1891 EVT CondEltVT = CondVT.getVectorElementType(); 1892 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), 1893 CondEltVT, WidenNumElts); 1894 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector) 1895 Cond1 = GetWidenedVector(Cond1); 1896 1897 if (Cond1.getValueType() != CondWidenVT) 1898 Cond1 = ModifyToType(Cond1, CondWidenVT); 1899 } 1900 1901 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 1902 SDValue InOp2 = GetWidenedVector(N->getOperand(2)); 1903 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT); 1904 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 1905 WidenVT, Cond1, InOp1, InOp2); 1906} 1907 1908SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) { 1909 SDValue InOp1 = GetWidenedVector(N->getOperand(2)); 1910 SDValue InOp2 = GetWidenedVector(N->getOperand(3)); 1911 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 1912 InOp1.getValueType(), N->getOperand(0), 1913 N->getOperand(1), InOp1, InOp2, N->getOperand(4)); 1914} 1915 1916SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) { 1917 assert(N->getValueType(0).isVector() == 1918 N->getOperand(0).getValueType().isVector() && 1919 "Scalar/Vector type mismatch"); 1920 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N); 1921 1922 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1923 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1924 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1925 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT, 1926 InOp1, InOp2, N->getOperand(2)); 1927} 1928 1929SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) { 1930 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1931 return DAG.getUNDEF(WidenVT); 1932} 1933 1934SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) { 1935 EVT VT = N->getValueType(0); 1936 DebugLoc dl = N->getDebugLoc(); 1937 1938 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1939 unsigned NumElts = VT.getVectorNumElements(); 1940 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1941 1942 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1943 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1944 1945 // Adjust mask based on new input vector length. 1946 SmallVector<int, 16> NewMask; 1947 for (unsigned i = 0; i != NumElts; ++i) { 1948 int Idx = N->getMaskElt(i); 1949 if (Idx < (int)NumElts) 1950 NewMask.push_back(Idx); 1951 else 1952 NewMask.push_back(Idx - NumElts + WidenNumElts); 1953 } 1954 for (unsigned i = NumElts; i != WidenNumElts; ++i) 1955 NewMask.push_back(-1); 1956 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]); 1957} 1958 1959SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) { 1960 assert(N->getValueType(0).isVector() && 1961 N->getOperand(0).getValueType().isVector() && 1962 "Operands must be vectors"); 1963 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1964 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1965 1966 SDValue InOp1 = N->getOperand(0); 1967 EVT InVT = InOp1.getValueType(); 1968 assert(InVT.isVector() && "can not widen non vector type"); 1969 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(), 1970 InVT.getVectorElementType(), WidenNumElts); 1971 InOp1 = GetWidenedVector(InOp1); 1972 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1973 1974 // Assume that the input and output will be widen appropriately. If not, 1975 // we will have to unroll it at some point. 1976 assert(InOp1.getValueType() == WidenInVT && 1977 InOp2.getValueType() == WidenInVT && 1978 "Input not widened to expected type!"); 1979 (void)WidenInVT; 1980 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), 1981 WidenVT, InOp1, InOp2, N->getOperand(2)); 1982} 1983 1984 1985//===----------------------------------------------------------------------===// 1986// Widen Vector Operand 1987//===----------------------------------------------------------------------===// 1988bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) { 1989 DEBUG(dbgs() << "Widen node operand " << ResNo << ": "; 1990 N->dump(&DAG); 1991 dbgs() << "\n"); 1992 SDValue Res = SDValue(); 1993 1994 switch (N->getOpcode()) { 1995 default: 1996#ifndef NDEBUG 1997 dbgs() << "WidenVectorOperand op #" << ResNo << ": "; 1998 N->dump(&DAG); 1999 dbgs() << "\n"; 2000#endif 2001 llvm_unreachable("Do not know how to widen this operator's operand!"); 2002 2003 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break; 2004 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break; 2005 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break; 2006 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break; 2007 case ISD::STORE: Res = WidenVecOp_STORE(N); break; 2008 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break; 2009 2010 case ISD::FP_EXTEND: 2011 case ISD::FP_TO_SINT: 2012 case ISD::FP_TO_UINT: 2013 case ISD::SINT_TO_FP: 2014 case ISD::UINT_TO_FP: 2015 case ISD::TRUNCATE: 2016 case ISD::SIGN_EXTEND: 2017 case ISD::ZERO_EXTEND: 2018 case ISD::ANY_EXTEND: 2019 Res = WidenVecOp_Convert(N); 2020 break; 2021 } 2022 2023 // If Res is null, the sub-method took care of registering the result. 2024 if (!Res.getNode()) return false; 2025 2026 // If the result is N, the sub-method updated N in place. Tell the legalizer 2027 // core about this. 2028 if (Res.getNode() == N) 2029 return true; 2030 2031 2032 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2033 "Invalid operand expansion"); 2034 2035 ReplaceValueWith(SDValue(N, 0), Res); 2036 return false; 2037} 2038 2039SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) { 2040 // Since the result is legal and the input is illegal, it is unlikely 2041 // that we can fix the input to a legal type so unroll the convert 2042 // into some scalar code and create a nasty build vector. 2043 EVT VT = N->getValueType(0); 2044 EVT EltVT = VT.getVectorElementType(); 2045 DebugLoc dl = N->getDebugLoc(); 2046 unsigned NumElts = VT.getVectorNumElements(); 2047 SDValue InOp = N->getOperand(0); 2048 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2049 InOp = GetWidenedVector(InOp); 2050 EVT InVT = InOp.getValueType(); 2051 EVT InEltVT = InVT.getVectorElementType(); 2052 2053 unsigned Opcode = N->getOpcode(); 2054 SmallVector<SDValue, 16> Ops(NumElts); 2055 for (unsigned i=0; i < NumElts; ++i) 2056 Ops[i] = DAG.getNode(Opcode, dl, EltVT, 2057 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 2058 DAG.getIntPtrConstant(i))); 2059 2060 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2061} 2062 2063SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) { 2064 EVT VT = N->getValueType(0); 2065 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2066 EVT InWidenVT = InOp.getValueType(); 2067 DebugLoc dl = N->getDebugLoc(); 2068 2069 // Check if we can convert between two legal vector types and extract. 2070 unsigned InWidenSize = InWidenVT.getSizeInBits(); 2071 unsigned Size = VT.getSizeInBits(); 2072 // x86mmx is not an acceptable vector element type, so don't try. 2073 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) { 2074 unsigned NewNumElts = InWidenSize / Size; 2075 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); 2076 if (TLI.isTypeLegal(NewVT)) { 2077 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp); 2078 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, 2079 DAG.getIntPtrConstant(0)); 2080 } 2081 } 2082 2083 return CreateStackStoreLoad(InOp, VT); 2084} 2085 2086SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) { 2087 // If the input vector is not legal, it is likely that we will not find a 2088 // legal vector of the same size. Replace the concatenate vector with a 2089 // nasty build vector. 2090 EVT VT = N->getValueType(0); 2091 EVT EltVT = VT.getVectorElementType(); 2092 DebugLoc dl = N->getDebugLoc(); 2093 unsigned NumElts = VT.getVectorNumElements(); 2094 SmallVector<SDValue, 16> Ops(NumElts); 2095 2096 EVT InVT = N->getOperand(0).getValueType(); 2097 unsigned NumInElts = InVT.getVectorNumElements(); 2098 2099 unsigned Idx = 0; 2100 unsigned NumOperands = N->getNumOperands(); 2101 for (unsigned i=0; i < NumOperands; ++i) { 2102 SDValue InOp = N->getOperand(i); 2103 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2104 InOp = GetWidenedVector(InOp); 2105 for (unsigned j=0; j < NumInElts; ++j) 2106 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2107 DAG.getIntPtrConstant(j)); 2108 } 2109 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2110} 2111 2112SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 2113 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2114 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), 2115 N->getValueType(0), InOp, N->getOperand(1)); 2116} 2117 2118SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 2119 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2120 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 2121 N->getValueType(0), InOp, N->getOperand(1)); 2122} 2123 2124SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) { 2125 // We have to widen the value but we want only to store the original 2126 // vector type. 2127 StoreSDNode *ST = cast<StoreSDNode>(N); 2128 2129 SmallVector<SDValue, 16> StChain; 2130 if (ST->isTruncatingStore()) 2131 GenWidenVectorTruncStores(StChain, ST); 2132 else 2133 GenWidenVectorStores(StChain, ST); 2134 2135 if (StChain.size() == 1) 2136 return StChain[0]; 2137 else 2138 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(), 2139 MVT::Other,&StChain[0],StChain.size()); 2140} 2141 2142SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) { 2143 SDValue InOp0 = GetWidenedVector(N->getOperand(0)); 2144 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 2145 DebugLoc dl = N->getDebugLoc(); 2146 2147 // WARNING: In this code we widen the compare instruction with garbage. 2148 // This garbage may contain denormal floats which may be slow. Is this a real 2149 // concern ? Should we zero the unused lanes if this is a float compare ? 2150 2151 // Get a new SETCC node to compare the newly widened operands. 2152 // Only some of the compared elements are legal. 2153 EVT SVT = TLI.getSetCCResultType(InOp0.getValueType()); 2154 SDValue WideSETCC = DAG.getNode(ISD::SETCC, N->getDebugLoc(), 2155 SVT, InOp0, InOp1, N->getOperand(2)); 2156 2157 // Extract the needed results from the result vector. 2158 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), 2159 SVT.getVectorElementType(), 2160 N->getValueType(0).getVectorNumElements()); 2161 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, 2162 ResVT, WideSETCC, DAG.getIntPtrConstant(0)); 2163 2164 return PromoteTargetBoolean(CC, N->getValueType(0)); 2165} 2166 2167 2168//===----------------------------------------------------------------------===// 2169// Vector Widening Utilities 2170//===----------------------------------------------------------------------===// 2171 2172// Utility function to find the type to chop up a widen vector for load/store 2173// TLI: Target lowering used to determine legal types. 2174// Width: Width left need to load/store. 2175// WidenVT: The widen vector type to load to/store from 2176// Align: If 0, don't allow use of a wider type 2177// WidenEx: If Align is not 0, the amount additional we can load/store from. 2178 2179static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, 2180 unsigned Width, EVT WidenVT, 2181 unsigned Align = 0, unsigned WidenEx = 0) { 2182 EVT WidenEltVT = WidenVT.getVectorElementType(); 2183 unsigned WidenWidth = WidenVT.getSizeInBits(); 2184 unsigned WidenEltWidth = WidenEltVT.getSizeInBits(); 2185 unsigned AlignInBits = Align*8; 2186 2187 // If we have one element to load/store, return it. 2188 EVT RetVT = WidenEltVT; 2189 if (Width == WidenEltWidth) 2190 return RetVT; 2191 2192 // See if there is larger legal integer than the element type to load/store 2193 unsigned VT; 2194 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE; 2195 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) { 2196 EVT MemVT((MVT::SimpleValueType) VT); 2197 unsigned MemVTWidth = MemVT.getSizeInBits(); 2198 if (MemVT.getSizeInBits() <= WidenEltWidth) 2199 break; 2200 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 && 2201 isPowerOf2_32(WidenWidth / MemVTWidth) && 2202 (MemVTWidth <= Width || 2203 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2204 RetVT = MemVT; 2205 break; 2206 } 2207 } 2208 2209 // See if there is a larger vector type to load/store that has the same vector 2210 // element type and is evenly divisible with the WidenVT. 2211 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; 2212 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) { 2213 EVT MemVT = (MVT::SimpleValueType) VT; 2214 unsigned MemVTWidth = MemVT.getSizeInBits(); 2215 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() && 2216 (WidenWidth % MemVTWidth) == 0 && 2217 isPowerOf2_32(WidenWidth / MemVTWidth) && 2218 (MemVTWidth <= Width || 2219 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2220 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT) 2221 return MemVT; 2222 } 2223 } 2224 2225 return RetVT; 2226} 2227 2228// Builds a vector type from scalar loads 2229// VecTy: Resulting Vector type 2230// LDOps: Load operators to build a vector type 2231// [Start,End) the list of loads to use. 2232static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, 2233 SmallVector<SDValue, 16>& LdOps, 2234 unsigned Start, unsigned End) { 2235 DebugLoc dl = LdOps[Start].getDebugLoc(); 2236 EVT LdTy = LdOps[Start].getValueType(); 2237 unsigned Width = VecTy.getSizeInBits(); 2238 unsigned NumElts = Width / LdTy.getSizeInBits(); 2239 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts); 2240 2241 unsigned Idx = 1; 2242 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]); 2243 2244 for (unsigned i = Start + 1; i != End; ++i) { 2245 EVT NewLdTy = LdOps[i].getValueType(); 2246 if (NewLdTy != LdTy) { 2247 NumElts = Width / NewLdTy.getSizeInBits(); 2248 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts); 2249 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp); 2250 // Readjust position and vector position based on new load type 2251 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits(); 2252 LdTy = NewLdTy; 2253 } 2254 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], 2255 DAG.getIntPtrConstant(Idx++)); 2256 } 2257 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp); 2258} 2259 2260SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain, 2261 LoadSDNode *LD) { 2262 // The strategy assumes that we can efficiently load powers of two widths. 2263 // The routines chops the vector into the largest vector loads with the same 2264 // element type or scalar loads and then recombines it to the widen vector 2265 // type. 2266 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2267 unsigned WidenWidth = WidenVT.getSizeInBits(); 2268 EVT LdVT = LD->getMemoryVT(); 2269 DebugLoc dl = LD->getDebugLoc(); 2270 assert(LdVT.isVector() && WidenVT.isVector()); 2271 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType()); 2272 2273 // Load information 2274 SDValue Chain = LD->getChain(); 2275 SDValue BasePtr = LD->getBasePtr(); 2276 unsigned Align = LD->getAlignment(); 2277 bool isVolatile = LD->isVolatile(); 2278 bool isNonTemporal = LD->isNonTemporal(); 2279 2280 int LdWidth = LdVT.getSizeInBits(); 2281 int WidthDiff = WidenWidth - LdWidth; // Difference 2282 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads 2283 2284 // Find the vector type that can load from. 2285 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2286 int NewVTWidth = NewVT.getSizeInBits(); 2287 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(), 2288 isVolatile, isNonTemporal, Align); 2289 LdChain.push_back(LdOp.getValue(1)); 2290 2291 // Check if we can load the element with one instruction 2292 if (LdWidth <= NewVTWidth) { 2293 if (!NewVT.isVector()) { 2294 unsigned NumElts = WidenWidth / NewVTWidth; 2295 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2296 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp); 2297 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp); 2298 } 2299 if (NewVT == WidenVT) 2300 return LdOp; 2301 2302 assert(WidenWidth % NewVTWidth == 0); 2303 unsigned NumConcat = WidenWidth / NewVTWidth; 2304 SmallVector<SDValue, 16> ConcatOps(NumConcat); 2305 SDValue UndefVal = DAG.getUNDEF(NewVT); 2306 ConcatOps[0] = LdOp; 2307 for (unsigned i = 1; i != NumConcat; ++i) 2308 ConcatOps[i] = UndefVal; 2309 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], 2310 NumConcat); 2311 } 2312 2313 // Load vector by using multiple loads from largest vector to scalar 2314 SmallVector<SDValue, 16> LdOps; 2315 LdOps.push_back(LdOp); 2316 2317 LdWidth -= NewVTWidth; 2318 unsigned Offset = 0; 2319 2320 while (LdWidth > 0) { 2321 unsigned Increment = NewVTWidth / 8; 2322 Offset += Increment; 2323 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2324 DAG.getIntPtrConstant(Increment)); 2325 2326 if (LdWidth < NewVTWidth) { 2327 // Our current type we are using is too large, find a better size 2328 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2329 NewVTWidth = NewVT.getSizeInBits(); 2330 } 2331 2332 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, 2333 LD->getPointerInfo().getWithOffset(Offset), 2334 isVolatile, 2335 isNonTemporal, MinAlign(Align, Increment)); 2336 LdChain.push_back(LdOp.getValue(1)); 2337 LdOps.push_back(LdOp); 2338 2339 LdWidth -= NewVTWidth; 2340 } 2341 2342 // Build the vector from the loads operations 2343 unsigned End = LdOps.size(); 2344 if (!LdOps[0].getValueType().isVector()) 2345 // All the loads are scalar loads. 2346 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End); 2347 2348 // If the load contains vectors, build the vector using concat vector. 2349 // All of the vectors used to loads are power of 2 and the scalars load 2350 // can be combined to make a power of 2 vector. 2351 SmallVector<SDValue, 16> ConcatOps(End); 2352 int i = End - 1; 2353 int Idx = End; 2354 EVT LdTy = LdOps[i].getValueType(); 2355 // First combine the scalar loads to a vector 2356 if (!LdTy.isVector()) { 2357 for (--i; i >= 0; --i) { 2358 LdTy = LdOps[i].getValueType(); 2359 if (LdTy.isVector()) 2360 break; 2361 } 2362 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End); 2363 } 2364 ConcatOps[--Idx] = LdOps[i]; 2365 for (--i; i >= 0; --i) { 2366 EVT NewLdTy = LdOps[i].getValueType(); 2367 if (NewLdTy != LdTy) { 2368 // Create a larger vector 2369 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy, 2370 &ConcatOps[Idx], End - Idx); 2371 Idx = End - 1; 2372 LdTy = NewLdTy; 2373 } 2374 ConcatOps[--Idx] = LdOps[i]; 2375 } 2376 2377 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx)) 2378 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, 2379 &ConcatOps[Idx], End - Idx); 2380 2381 // We need to fill the rest with undefs to build the vector 2382 unsigned NumOps = WidenWidth / LdTy.getSizeInBits(); 2383 SmallVector<SDValue, 16> WidenOps(NumOps); 2384 SDValue UndefVal = DAG.getUNDEF(LdTy); 2385 { 2386 unsigned i = 0; 2387 for (; i != End-Idx; ++i) 2388 WidenOps[i] = ConcatOps[Idx+i]; 2389 for (; i != NumOps; ++i) 2390 WidenOps[i] = UndefVal; 2391 } 2392 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps); 2393} 2394 2395SDValue 2396DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain, 2397 LoadSDNode * LD, 2398 ISD::LoadExtType ExtType) { 2399 // For extension loads, it may not be more efficient to chop up the vector 2400 // and then extended it. Instead, we unroll the load and build a new vector. 2401 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2402 EVT LdVT = LD->getMemoryVT(); 2403 DebugLoc dl = LD->getDebugLoc(); 2404 assert(LdVT.isVector() && WidenVT.isVector()); 2405 2406 // Load information 2407 SDValue Chain = LD->getChain(); 2408 SDValue BasePtr = LD->getBasePtr(); 2409 unsigned Align = LD->getAlignment(); 2410 bool isVolatile = LD->isVolatile(); 2411 bool isNonTemporal = LD->isNonTemporal(); 2412 2413 EVT EltVT = WidenVT.getVectorElementType(); 2414 EVT LdEltVT = LdVT.getVectorElementType(); 2415 unsigned NumElts = LdVT.getVectorNumElements(); 2416 2417 // Load each element and widen 2418 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2419 SmallVector<SDValue, 16> Ops(WidenNumElts); 2420 unsigned Increment = LdEltVT.getSizeInBits() / 8; 2421 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, 2422 LD->getPointerInfo(), 2423 LdEltVT, isVolatile, isNonTemporal, Align); 2424 LdChain.push_back(Ops[0].getValue(1)); 2425 unsigned i = 0, Offset = Increment; 2426 for (i=1; i < NumElts; ++i, Offset += Increment) { 2427 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2428 BasePtr, DAG.getIntPtrConstant(Offset)); 2429 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, 2430 LD->getPointerInfo().getWithOffset(Offset), LdEltVT, 2431 isVolatile, isNonTemporal, Align); 2432 LdChain.push_back(Ops[i].getValue(1)); 2433 } 2434 2435 // Fill the rest with undefs 2436 SDValue UndefVal = DAG.getUNDEF(EltVT); 2437 for (; i != WidenNumElts; ++i) 2438 Ops[i] = UndefVal; 2439 2440 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size()); 2441} 2442 2443 2444void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, 2445 StoreSDNode *ST) { 2446 // The strategy assumes that we can efficiently store powers of two widths. 2447 // The routines chops the vector into the largest vector stores with the same 2448 // element type or scalar stores. 2449 SDValue Chain = ST->getChain(); 2450 SDValue BasePtr = ST->getBasePtr(); 2451 unsigned Align = ST->getAlignment(); 2452 bool isVolatile = ST->isVolatile(); 2453 bool isNonTemporal = ST->isNonTemporal(); 2454 SDValue ValOp = GetWidenedVector(ST->getValue()); 2455 DebugLoc dl = ST->getDebugLoc(); 2456 2457 EVT StVT = ST->getMemoryVT(); 2458 unsigned StWidth = StVT.getSizeInBits(); 2459 EVT ValVT = ValOp.getValueType(); 2460 unsigned ValWidth = ValVT.getSizeInBits(); 2461 EVT ValEltVT = ValVT.getVectorElementType(); 2462 unsigned ValEltWidth = ValEltVT.getSizeInBits(); 2463 assert(StVT.getVectorElementType() == ValEltVT); 2464 2465 int Idx = 0; // current index to store 2466 unsigned Offset = 0; // offset from base to store 2467 while (StWidth != 0) { 2468 // Find the largest vector type we can store with 2469 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT); 2470 unsigned NewVTWidth = NewVT.getSizeInBits(); 2471 unsigned Increment = NewVTWidth / 8; 2472 if (NewVT.isVector()) { 2473 unsigned NumVTElts = NewVT.getVectorNumElements(); 2474 do { 2475 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, 2476 DAG.getIntPtrConstant(Idx)); 2477 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2478 ST->getPointerInfo().getWithOffset(Offset), 2479 isVolatile, isNonTemporal, 2480 MinAlign(Align, Offset))); 2481 StWidth -= NewVTWidth; 2482 Offset += Increment; 2483 Idx += NumVTElts; 2484 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2485 DAG.getIntPtrConstant(Increment)); 2486 } while (StWidth != 0 && StWidth >= NewVTWidth); 2487 } else { 2488 // Cast the vector to the scalar type we can store 2489 unsigned NumElts = ValWidth / NewVTWidth; 2490 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2491 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); 2492 // Readjust index position based on new vector type 2493 Idx = Idx * ValEltWidth / NewVTWidth; 2494 do { 2495 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp, 2496 DAG.getIntPtrConstant(Idx++)); 2497 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2498 ST->getPointerInfo().getWithOffset(Offset), 2499 isVolatile, isNonTemporal, 2500 MinAlign(Align, Offset))); 2501 StWidth -= NewVTWidth; 2502 Offset += Increment; 2503 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2504 DAG.getIntPtrConstant(Increment)); 2505 } while (StWidth != 0 && StWidth >= NewVTWidth); 2506 // Restore index back to be relative to the original widen element type 2507 Idx = Idx * NewVTWidth / ValEltWidth; 2508 } 2509 } 2510} 2511 2512void 2513DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain, 2514 StoreSDNode *ST) { 2515 // For extension loads, it may not be more efficient to truncate the vector 2516 // and then store it. Instead, we extract each element and then store it. 2517 SDValue Chain = ST->getChain(); 2518 SDValue BasePtr = ST->getBasePtr(); 2519 unsigned Align = ST->getAlignment(); 2520 bool isVolatile = ST->isVolatile(); 2521 bool isNonTemporal = ST->isNonTemporal(); 2522 SDValue ValOp = GetWidenedVector(ST->getValue()); 2523 DebugLoc dl = ST->getDebugLoc(); 2524 2525 EVT StVT = ST->getMemoryVT(); 2526 EVT ValVT = ValOp.getValueType(); 2527 2528 // It must be true that we the widen vector type is bigger than where 2529 // we need to store. 2530 assert(StVT.isVector() && ValOp.getValueType().isVector()); 2531 assert(StVT.bitsLT(ValOp.getValueType())); 2532 2533 // For truncating stores, we can not play the tricks of chopping legal 2534 // vector types and bit cast it to the right type. Instead, we unroll 2535 // the store. 2536 EVT StEltVT = StVT.getVectorElementType(); 2537 EVT ValEltVT = ValVT.getVectorElementType(); 2538 unsigned Increment = ValEltVT.getSizeInBits() / 8; 2539 unsigned NumElts = StVT.getVectorNumElements(); 2540 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2541 DAG.getIntPtrConstant(0)); 2542 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, 2543 ST->getPointerInfo(), StEltVT, 2544 isVolatile, isNonTemporal, Align)); 2545 unsigned Offset = Increment; 2546 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) { 2547 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2548 BasePtr, DAG.getIntPtrConstant(Offset)); 2549 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2550 DAG.getIntPtrConstant(0)); 2551 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, 2552 ST->getPointerInfo().getWithOffset(Offset), 2553 StEltVT, isVolatile, isNonTemporal, 2554 MinAlign(Align, Offset))); 2555 } 2556} 2557 2558/// Modifies a vector input (widen or narrows) to a vector of NVT. The 2559/// input vector must have the same element type as NVT. 2560SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) { 2561 // Note that InOp might have been widened so it might already have 2562 // the right width or it might need be narrowed. 2563 EVT InVT = InOp.getValueType(); 2564 assert(InVT.getVectorElementType() == NVT.getVectorElementType() && 2565 "input and widen element type must match"); 2566 DebugLoc dl = InOp.getDebugLoc(); 2567 2568 // Check if InOp already has the right width. 2569 if (InVT == NVT) 2570 return InOp; 2571 2572 unsigned InNumElts = InVT.getVectorNumElements(); 2573 unsigned WidenNumElts = NVT.getVectorNumElements(); 2574 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) { 2575 unsigned NumConcat = WidenNumElts / InNumElts; 2576 SmallVector<SDValue, 16> Ops(NumConcat); 2577 SDValue UndefVal = DAG.getUNDEF(InVT); 2578 Ops[0] = InOp; 2579 for (unsigned i = 1; i != NumConcat; ++i) 2580 Ops[i] = UndefVal; 2581 2582 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat); 2583 } 2584 2585 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts) 2586 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp, 2587 DAG.getIntPtrConstant(0)); 2588 2589 // Fall back to extract and build. 2590 SmallVector<SDValue, 16> Ops(WidenNumElts); 2591 EVT EltVT = NVT.getVectorElementType(); 2592 unsigned MinNumElts = std::min(WidenNumElts, InNumElts); 2593 unsigned Idx; 2594 for (Idx = 0; Idx < MinNumElts; ++Idx) 2595 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2596 DAG.getIntPtrConstant(Idx)); 2597 2598 SDValue UndefVal = DAG.getUNDEF(EltVT); 2599 for ( ; Idx < WidenNumElts; ++Idx) 2600 Ops[Idx] = UndefVal; 2601 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts); 2602} 2603