LegalizeVectorTypes.cpp revision d133bf8f27af57c9ed807a033f2375d80bf644a2
1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file performs vector type splitting and scalarization for LegalizeTypes. 11// Scalarization is the act of changing a computation in an illegal one-element 12// vector type to be a computation in its scalar element type. For example, 13// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed 14// as a base case when scalarizing vector arithmetic like <4 x f32>, which 15// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32 16// types. 17// Splitting is the act of changing a computation in an invalid vector type to 18// be a computation in two vectors of half the size. For example, implementing 19// <128 x f32> operations in terms of two <64 x f32> operations. 20// 21//===----------------------------------------------------------------------===// 22 23#include "LegalizeTypes.h" 24#include "llvm/CodeGen/PseudoSourceValue.h" 25#include "llvm/Target/TargetData.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Support/raw_ostream.h" 28using namespace llvm; 29 30//===----------------------------------------------------------------------===// 31// Result Vector Scalarization: <1 x ty> -> ty. 32//===----------------------------------------------------------------------===// 33 34void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { 35 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; 36 N->dump(&DAG); 37 dbgs() << "\n"); 38 SDValue R = SDValue(); 39 40 switch (N->getOpcode()) { 41 default: 42#ifndef NDEBUG 43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": "; 44 N->dump(&DAG); 45 dbgs() << "\n"; 46 dbgs() << "Do not know how to scalarize the result of this operator!\n"; 47#endif 48 abort(); 49 50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 51 case ISD::BUILD_VECTOR: R = N->getOperand(0); break; 52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; 53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; 55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; 56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; 59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; 60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; 61 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break; 62 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; 63 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; 64 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; 65 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; 66 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break; 67 68 case ISD::ANY_EXTEND: 69 case ISD::CTLZ: 70 case ISD::CTPOP: 71 case ISD::CTTZ: 72 case ISD::FABS: 73 case ISD::FCEIL: 74 case ISD::FCOS: 75 case ISD::FEXP: 76 case ISD::FEXP2: 77 case ISD::FFLOOR: 78 case ISD::FLOG: 79 case ISD::FLOG10: 80 case ISD::FLOG2: 81 case ISD::FNEARBYINT: 82 case ISD::FNEG: 83 case ISD::FP_EXTEND: 84 case ISD::FP_TO_SINT: 85 case ISD::FP_TO_UINT: 86 case ISD::FRINT: 87 case ISD::FSIN: 88 case ISD::FSQRT: 89 case ISD::FTRUNC: 90 case ISD::SIGN_EXTEND: 91 case ISD::SINT_TO_FP: 92 case ISD::TRUNCATE: 93 case ISD::UINT_TO_FP: 94 case ISD::ZERO_EXTEND: 95 R = ScalarizeVecRes_UnaryOp(N); 96 break; 97 98 case ISD::ADD: 99 case ISD::AND: 100 case ISD::FADD: 101 case ISD::FDIV: 102 case ISD::FMUL: 103 case ISD::FPOW: 104 case ISD::FREM: 105 case ISD::FSUB: 106 case ISD::MUL: 107 case ISD::OR: 108 case ISD::SDIV: 109 case ISD::SREM: 110 case ISD::SUB: 111 case ISD::UDIV: 112 case ISD::UREM: 113 case ISD::XOR: 114 case ISD::SHL: 115 case ISD::SRA: 116 case ISD::SRL: 117 R = ScalarizeVecRes_BinOp(N); 118 break; 119 } 120 121 // If R is null, the sub-method took care of registering the result. 122 if (R.getNode()) 123 SetScalarizedVector(SDValue(N, ResNo), R); 124} 125 126SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { 127 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 128 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 129 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 130 LHS.getValueType(), LHS, RHS); 131} 132 133SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) { 134 EVT NewVT = N->getValueType(0).getVectorElementType(); 135 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 136 NewVT, N->getOperand(0)); 137} 138 139SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) { 140 EVT NewVT = N->getValueType(0).getVectorElementType(); 141 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); 142 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(), 143 Op0, DAG.getValueType(NewVT), 144 DAG.getValueType(Op0.getValueType()), 145 N->getOperand(3), 146 N->getOperand(4), 147 cast<CvtRndSatSDNode>(N)->getCvtCode()); 148} 149 150SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 151 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 152 N->getValueType(0).getVectorElementType(), 153 N->getOperand(0), N->getOperand(1)); 154} 155 156SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) { 157 EVT NewVT = N->getValueType(0).getVectorElementType(); 158 SDValue Op = GetScalarizedVector(N->getOperand(0)); 159 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), 160 NewVT, Op, N->getOperand(1)); 161} 162 163SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) { 164 SDValue Op = GetScalarizedVector(N->getOperand(0)); 165 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(), 166 Op.getValueType(), Op, N->getOperand(1)); 167} 168 169SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { 170 // The value to insert may have a wider type than the vector element type, 171 // so be sure to truncate it to the element type if necessary. 172 SDValue Op = N->getOperand(1); 173 EVT EltVT = N->getValueType(0).getVectorElementType(); 174 if (Op.getValueType() != EltVT) 175 // FIXME: Can this happen for floating point types? 176 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op); 177 return Op; 178} 179 180SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { 181 assert(N->isUnindexed() && "Indexed vector load?"); 182 183 SDValue Result = DAG.getLoad(ISD::UNINDEXED, 184 N->getExtensionType(), 185 N->getValueType(0).getVectorElementType(), 186 N->getDebugLoc(), 187 N->getChain(), N->getBasePtr(), 188 DAG.getUNDEF(N->getBasePtr().getValueType()), 189 N->getPointerInfo(), 190 N->getMemoryVT().getVectorElementType(), 191 N->isVolatile(), N->isNonTemporal(), 192 N->getOriginalAlignment()); 193 194 // Legalized the chain result - switch anything that used the old chain to 195 // use the new one. 196 ReplaceValueWith(SDValue(N, 1), Result.getValue(1)); 197 return Result; 198} 199 200SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { 201 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp. 202 EVT DestVT = N->getValueType(0).getVectorElementType(); 203 SDValue Op = GetScalarizedVector(N->getOperand(0)); 204 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op); 205} 206 207SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) { 208 EVT EltVT = N->getValueType(0).getVectorElementType(); 209 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType(); 210 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 211 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT, 212 LHS, DAG.getValueType(ExtVT)); 213} 214 215SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) { 216 // If the operand is wider than the vector element type then it is implicitly 217 // truncated. Make that explicit here. 218 EVT EltVT = N->getValueType(0).getVectorElementType(); 219 SDValue InOp = N->getOperand(0); 220 if (InOp.getValueType() != EltVT) 221 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp); 222 return InOp; 223} 224 225SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) { 226 SDValue LHS = GetScalarizedVector(N->getOperand(1)); 227 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 228 LHS.getValueType(), N->getOperand(0), LHS, 229 GetScalarizedVector(N->getOperand(2))); 230} 231 232SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) { 233 SDValue LHS = GetScalarizedVector(N->getOperand(2)); 234 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(), 235 N->getOperand(0), N->getOperand(1), 236 LHS, GetScalarizedVector(N->getOperand(3)), 237 N->getOperand(4)); 238} 239 240SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) { 241 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 242 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 243 DebugLoc DL = N->getDebugLoc(); 244 245 // Turn it into a scalar SETCC. 246 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); 247} 248 249SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { 250 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 251} 252 253SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { 254 // Figure out if the scalar is the LHS or RHS and return it. 255 SDValue Arg = N->getOperand(2).getOperand(0); 256 if (Arg.getOpcode() == ISD::UNDEF) 257 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 258 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue(); 259 return GetScalarizedVector(N->getOperand(Op)); 260} 261 262SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) { 263 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 264 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 265 EVT NVT = N->getValueType(0).getVectorElementType(); 266 EVT SVT = TLI.getSetCCResultType(LHS.getValueType()); 267 DebugLoc DL = N->getDebugLoc(); 268 269 // Turn it into a scalar SETCC. 270 SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2)); 271 272 // VSETCC always returns a sign-extended value, while SETCC may not. The 273 // SETCC result type may not match the vector element type. Correct these. 274 if (NVT.bitsLE(SVT)) { 275 // The SETCC result type is bigger than the vector element type. 276 // Ensure the SETCC result is sign-extended. 277 if (TLI.getBooleanContents() != 278 TargetLowering::ZeroOrNegativeOneBooleanContent) 279 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res, 280 DAG.getValueType(MVT::i1)); 281 // Truncate to the final type. 282 return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res); 283 } 284 285 // The SETCC result type is smaller than the vector element type. 286 // If the SetCC result is not sign-extended, chop it down to MVT::i1. 287 if (TLI.getBooleanContents() != 288 TargetLowering::ZeroOrNegativeOneBooleanContent) 289 Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res); 290 // Sign extend to the final type. 291 return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res); 292} 293 294 295//===----------------------------------------------------------------------===// 296// Operand Vector Scalarization <1 x ty> -> ty. 297//===----------------------------------------------------------------------===// 298 299bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { 300 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; 301 N->dump(&DAG); 302 dbgs() << "\n"); 303 SDValue Res = SDValue(); 304 305 if (Res.getNode() == 0) { 306 switch (N->getOpcode()) { 307 default: 308#ifndef NDEBUG 309 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": "; 310 N->dump(&DAG); 311 dbgs() << "\n"; 312#endif 313 llvm_unreachable("Do not know how to scalarize this operator's operand!"); 314 case ISD::BITCAST: 315 Res = ScalarizeVecOp_BITCAST(N); 316 break; 317 case ISD::CONCAT_VECTORS: 318 Res = ScalarizeVecOp_CONCAT_VECTORS(N); 319 break; 320 case ISD::EXTRACT_VECTOR_ELT: 321 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); 322 break; 323 case ISD::STORE: 324 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); 325 break; 326 } 327 } 328 329 // If the result is null, the sub-method took care of registering results etc. 330 if (!Res.getNode()) return false; 331 332 // If the result is N, the sub-method updated N in place. Tell the legalizer 333 // core about this. 334 if (Res.getNode() == N) 335 return true; 336 337 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 338 "Invalid operand expansion"); 339 340 ReplaceValueWith(SDValue(N, 0), Res); 341 return false; 342} 343 344/// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs 345/// to be scalarized, it must be <1 x ty>. Convert the element instead. 346SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) { 347 SDValue Elt = GetScalarizedVector(N->getOperand(0)); 348 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 349 N->getValueType(0), Elt); 350} 351 352/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one - 353/// use a BUILD_VECTOR instead. 354SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) { 355 SmallVector<SDValue, 8> Ops(N->getNumOperands()); 356 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 357 Ops[i] = GetScalarizedVector(N->getOperand(i)); 358 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0), 359 &Ops[0], Ops.size()); 360} 361 362/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to 363/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the 364/// index. 365SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 366 SDValue Res = GetScalarizedVector(N->getOperand(0)); 367 if (Res.getValueType() != N->getValueType(0)) 368 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), 369 Res); 370 return Res; 371} 372 373/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be 374/// scalarized, it must be <1 x ty>. Just store the element. 375SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ 376 assert(N->isUnindexed() && "Indexed store of one-element vector?"); 377 assert(OpNo == 1 && "Do not know how to scalarize this operand!"); 378 DebugLoc dl = N->getDebugLoc(); 379 380 if (N->isTruncatingStore()) 381 return DAG.getTruncStore(N->getChain(), dl, 382 GetScalarizedVector(N->getOperand(1)), 383 N->getBasePtr(), N->getPointerInfo(), 384 N->getMemoryVT().getVectorElementType(), 385 N->isVolatile(), N->isNonTemporal(), 386 N->getAlignment()); 387 388 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)), 389 N->getBasePtr(), N->getPointerInfo(), 390 N->isVolatile(), N->isNonTemporal(), 391 N->getOriginalAlignment()); 392} 393 394 395//===----------------------------------------------------------------------===// 396// Result Vector Splitting 397//===----------------------------------------------------------------------===// 398 399/// SplitVectorResult - This method is called when the specified result of the 400/// specified node is found to need vector splitting. At this point, the node 401/// may also have invalid operands or may have other results that need 402/// legalization, we just know that (at least) one result needs vector 403/// splitting. 404void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { 405 DEBUG(dbgs() << "Split node result: "; 406 N->dump(&DAG); 407 dbgs() << "\n"); 408 SDValue Lo, Hi; 409 410 switch (N->getOpcode()) { 411 default: 412#ifndef NDEBUG 413 dbgs() << "SplitVectorResult #" << ResNo << ": "; 414 N->dump(&DAG); 415 dbgs() << "\n"; 416#endif 417 llvm_unreachable("Do not know how to split the result of this operator!"); 418 419 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 420 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 421 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 422 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 423 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; 424 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 425 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 426 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; 427 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 428 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; 429 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 430 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break; 431 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 432 case ISD::LOAD: 433 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); 434 break; 435 case ISD::SETCC: 436 case ISD::VSETCC: 437 SplitVecRes_SETCC(N, Lo, Hi); 438 break; 439 case ISD::VECTOR_SHUFFLE: 440 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); 441 break; 442 443 case ISD::ANY_EXTEND: 444 case ISD::CONVERT_RNDSAT: 445 case ISD::CTLZ: 446 case ISD::CTPOP: 447 case ISD::CTTZ: 448 case ISD::FABS: 449 case ISD::FCEIL: 450 case ISD::FCOS: 451 case ISD::FEXP: 452 case ISD::FEXP2: 453 case ISD::FFLOOR: 454 case ISD::FLOG: 455 case ISD::FLOG10: 456 case ISD::FLOG2: 457 case ISD::FNEARBYINT: 458 case ISD::FNEG: 459 case ISD::FP_EXTEND: 460 case ISD::FP_ROUND: 461 case ISD::FP_TO_SINT: 462 case ISD::FP_TO_UINT: 463 case ISD::FRINT: 464 case ISD::FSIN: 465 case ISD::FSQRT: 466 case ISD::FTRUNC: 467 case ISD::SIGN_EXTEND: 468 case ISD::SINT_TO_FP: 469 case ISD::TRUNCATE: 470 case ISD::UINT_TO_FP: 471 case ISD::ZERO_EXTEND: 472 SplitVecRes_UnaryOp(N, Lo, Hi); 473 break; 474 475 case ISD::ADD: 476 case ISD::SUB: 477 case ISD::MUL: 478 case ISD::FADD: 479 case ISD::FSUB: 480 case ISD::FMUL: 481 case ISD::SDIV: 482 case ISD::UDIV: 483 case ISD::FDIV: 484 case ISD::FPOW: 485 case ISD::AND: 486 case ISD::OR: 487 case ISD::XOR: 488 case ISD::SHL: 489 case ISD::SRA: 490 case ISD::SRL: 491 case ISD::UREM: 492 case ISD::SREM: 493 case ISD::FREM: 494 SplitVecRes_BinOp(N, Lo, Hi); 495 break; 496 } 497 498 // If Lo/Hi is null, the sub-method took care of registering results etc. 499 if (Lo.getNode()) 500 SetSplitVector(SDValue(N, ResNo), Lo, Hi); 501} 502 503void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo, 504 SDValue &Hi) { 505 SDValue LHSLo, LHSHi; 506 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 507 SDValue RHSLo, RHSHi; 508 GetSplitVector(N->getOperand(1), RHSLo, RHSHi); 509 DebugLoc dl = N->getDebugLoc(); 510 511 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo); 512 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi); 513} 514 515void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, 516 SDValue &Hi) { 517 // We know the result is a vector. The input may be either a vector or a 518 // scalar value. 519 EVT LoVT, HiVT; 520 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 521 DebugLoc dl = N->getDebugLoc(); 522 523 SDValue InOp = N->getOperand(0); 524 EVT InVT = InOp.getValueType(); 525 526 // Handle some special cases efficiently. 527 switch (getTypeAction(InVT)) { 528 case TargetLowering::TypeLegal: 529 case TargetLowering::TypePromoteInteger: 530 case TargetLowering::TypeSoftenFloat: 531 case TargetLowering::TypeScalarizeVector: 532 case TargetLowering::TypeWidenVector: 533 break; 534 case TargetLowering::TypeExpandInteger: 535 case TargetLowering::TypeExpandFloat: 536 // A scalar to vector conversion, where the scalar needs expansion. 537 // If the vector is being split in two then we can just convert the 538 // expanded pieces. 539 if (LoVT == HiVT) { 540 GetExpandedOp(InOp, Lo, Hi); 541 if (TLI.isBigEndian()) 542 std::swap(Lo, Hi); 543 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 544 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 545 return; 546 } 547 break; 548 case TargetLowering::TypeSplitVector: 549 // If the input is a vector that needs to be split, convert each split 550 // piece of the input now. 551 GetSplitVector(InOp, Lo, Hi); 552 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 553 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 554 return; 555 } 556 557 // In the general case, convert the input to an integer and split it by hand. 558 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits()); 559 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits()); 560 if (TLI.isBigEndian()) 561 std::swap(LoIntVT, HiIntVT); 562 563 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); 564 565 if (TLI.isBigEndian()) 566 std::swap(Lo, Hi); 567 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 568 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 569} 570 571void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, 572 SDValue &Hi) { 573 EVT LoVT, HiVT; 574 DebugLoc dl = N->getDebugLoc(); 575 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 576 unsigned LoNumElts = LoVT.getVectorNumElements(); 577 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts); 578 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size()); 579 580 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end()); 581 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size()); 582} 583 584void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, 585 SDValue &Hi) { 586 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"); 587 DebugLoc dl = N->getDebugLoc(); 588 unsigned NumSubvectors = N->getNumOperands() / 2; 589 if (NumSubvectors == 1) { 590 Lo = N->getOperand(0); 591 Hi = N->getOperand(1); 592 return; 593 } 594 595 EVT LoVT, HiVT; 596 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 597 598 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); 599 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size()); 600 601 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end()); 602 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size()); 603} 604 605void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, 606 SDValue &Hi) { 607 SDValue Vec = N->getOperand(0); 608 SDValue Idx = N->getOperand(1); 609 DebugLoc dl = N->getDebugLoc(); 610 611 EVT LoVT, HiVT; 612 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 613 614 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); 615 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 616 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, 617 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements())); 618} 619 620void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, 621 SDValue &Hi) { 622 DebugLoc dl = N->getDebugLoc(); 623 GetSplitVector(N->getOperand(0), Lo, Hi); 624 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1)); 625 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1)); 626} 627 628void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo, 629 SDValue &Hi) { 630 SDValue LHSLo, LHSHi; 631 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 632 DebugLoc dl = N->getDebugLoc(); 633 634 EVT LoVT, HiVT; 635 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT); 636 637 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, 638 DAG.getValueType(LoVT)); 639 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, 640 DAG.getValueType(HiVT)); 641} 642 643void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, 644 SDValue &Hi) { 645 SDValue Vec = N->getOperand(0); 646 SDValue Elt = N->getOperand(1); 647 SDValue Idx = N->getOperand(2); 648 DebugLoc dl = N->getDebugLoc(); 649 GetSplitVector(Vec, Lo, Hi); 650 651 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 652 unsigned IdxVal = CIdx->getZExtValue(); 653 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 654 if (IdxVal < LoNumElts) 655 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 656 Lo.getValueType(), Lo, Elt, Idx); 657 else 658 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, 659 DAG.getIntPtrConstant(IdxVal - LoNumElts)); 660 return; 661 } 662 663 // Spill the vector to the stack. 664 EVT VecVT = Vec.getValueType(); 665 EVT EltVT = VecVT.getVectorElementType(); 666 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 667 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 668 MachinePointerInfo(), false, false, 0); 669 670 // Store the new element. This may be larger than the vector element type, 671 // so use a truncating store. 672 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 673 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); 674 unsigned Alignment = 675 TLI.getTargetData()->getPrefTypeAlignment(VecType); 676 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT, 677 false, false, 0); 678 679 // Load the Lo part from the stack slot. 680 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 681 false, false, 0); 682 683 // Increment the pointer to the other part. 684 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; 685 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 686 DAG.getIntPtrConstant(IncrementSize)); 687 688 // Load the Hi part from the stack slot. 689 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 690 false, false, MinAlign(Alignment, IncrementSize)); 691} 692 693void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, 694 SDValue &Hi) { 695 EVT LoVT, HiVT; 696 DebugLoc dl = N->getDebugLoc(); 697 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 698 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0)); 699 Hi = DAG.getUNDEF(HiVT); 700} 701 702void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, 703 SDValue &Hi) { 704 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"); 705 EVT LoVT, HiVT; 706 DebugLoc dl = LD->getDebugLoc(); 707 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); 708 709 ISD::LoadExtType ExtType = LD->getExtensionType(); 710 SDValue Ch = LD->getChain(); 711 SDValue Ptr = LD->getBasePtr(); 712 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 713 EVT MemoryVT = LD->getMemoryVT(); 714 unsigned Alignment = LD->getOriginalAlignment(); 715 bool isVolatile = LD->isVolatile(); 716 bool isNonTemporal = LD->isNonTemporal(); 717 718 EVT LoMemVT, HiMemVT; 719 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 720 721 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, 722 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal, 723 Alignment); 724 725 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 726 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 727 DAG.getIntPtrConstant(IncrementSize)); 728 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, 729 LD->getPointerInfo().getWithOffset(IncrementSize), 730 HiMemVT, isVolatile, isNonTemporal, Alignment); 731 732 // Build a factor node to remember that this load is independent of the 733 // other one. 734 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 735 Hi.getValue(1)); 736 737 // Legalized the chain result - switch anything that used the old chain to 738 // use the new one. 739 ReplaceValueWith(SDValue(LD, 1), Ch); 740} 741 742void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) { 743 EVT LoVT, HiVT; 744 DebugLoc DL = N->getDebugLoc(); 745 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 746 747 // Split the input. 748 EVT InVT = N->getOperand(0).getValueType(); 749 SDValue LL, LH, RL, RH; 750 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 751 LoVT.getVectorNumElements()); 752 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 753 DAG.getIntPtrConstant(0)); 754 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 755 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 756 757 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 758 DAG.getIntPtrConstant(0)); 759 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 760 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 761 762 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2)); 763 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2)); 764} 765 766void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, 767 SDValue &Hi) { 768 // Get the dest types - they may not match the input types, e.g. int_to_fp. 769 EVT LoVT, HiVT; 770 DebugLoc dl = N->getDebugLoc(); 771 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 772 773 // Split the input. 774 EVT InVT = N->getOperand(0).getValueType(); 775 switch (getTypeAction(InVT)) { 776 default: llvm_unreachable("Unexpected type action!"); 777 case TargetLowering::TypeLegal: { 778 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 779 LoVT.getVectorNumElements()); 780 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 781 DAG.getIntPtrConstant(0)); 782 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 783 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 784 break; 785 } 786 case TargetLowering::TypePromoteInteger: { 787 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 788 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), 789 InOp.getValueType().getVectorElementType(), 790 LoVT.getVectorNumElements()); 791 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 792 DAG.getIntPtrConstant(0)); 793 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 794 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 795 break; 796 } 797 case TargetLowering::TypeSplitVector: 798 GetSplitVector(N->getOperand(0), Lo, Hi); 799 break; 800 case TargetLowering::TypeWidenVector: { 801 // If the result needs to be split and the input needs to be widened, 802 // the two types must have different lengths. Use the widened result 803 // and extract from it to do the split. 804 SDValue InOp = GetWidenedVector(N->getOperand(0)); 805 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 806 LoVT.getVectorNumElements()); 807 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 808 DAG.getIntPtrConstant(0)); 809 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 810 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 811 break; 812 } 813 } 814 815 if (N->getOpcode() == ISD::FP_ROUND) { 816 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1)); 817 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1)); 818 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) { 819 SDValue DTyOpLo = DAG.getValueType(LoVT); 820 SDValue DTyOpHi = DAG.getValueType(HiVT); 821 SDValue STyOpLo = DAG.getValueType(Lo.getValueType()); 822 SDValue STyOpHi = DAG.getValueType(Hi.getValueType()); 823 SDValue RndOp = N->getOperand(3); 824 SDValue SatOp = N->getOperand(4); 825 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 826 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp, 827 CvtCode); 828 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp, 829 CvtCode); 830 } else { 831 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo); 832 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi); 833 } 834} 835 836void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, 837 SDValue &Lo, SDValue &Hi) { 838 // The low and high parts of the original input give four input vectors. 839 SDValue Inputs[4]; 840 DebugLoc dl = N->getDebugLoc(); 841 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]); 842 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]); 843 EVT NewVT = Inputs[0].getValueType(); 844 unsigned NewElts = NewVT.getVectorNumElements(); 845 846 // If Lo or Hi uses elements from at most two of the four input vectors, then 847 // express it as a vector shuffle of those two inputs. Otherwise extract the 848 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. 849 SmallVector<int, 16> Ops; 850 for (unsigned High = 0; High < 2; ++High) { 851 SDValue &Output = High ? Hi : Lo; 852 853 // Build a shuffle mask for the output, discovering on the fly which 854 // input vectors to use as shuffle operands (recorded in InputUsed). 855 // If building a suitable shuffle vector proves too hard, then bail 856 // out with useBuildVector set. 857 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered. 858 unsigned FirstMaskIdx = High * NewElts; 859 bool useBuildVector = false; 860 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 861 // The mask element. This indexes into the input. 862 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 863 864 // The input vector this mask element indexes into. 865 unsigned Input = (unsigned)Idx / NewElts; 866 867 if (Input >= array_lengthof(Inputs)) { 868 // The mask element does not index into any input vector. 869 Ops.push_back(-1); 870 continue; 871 } 872 873 // Turn the index into an offset from the start of the input vector. 874 Idx -= Input * NewElts; 875 876 // Find or create a shuffle vector operand to hold this input. 877 unsigned OpNo; 878 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 879 if (InputUsed[OpNo] == Input) { 880 // This input vector is already an operand. 881 break; 882 } else if (InputUsed[OpNo] == -1U) { 883 // Create a new operand for this input vector. 884 InputUsed[OpNo] = Input; 885 break; 886 } 887 } 888 889 if (OpNo >= array_lengthof(InputUsed)) { 890 // More than two input vectors used! Give up on trying to create a 891 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 892 useBuildVector = true; 893 break; 894 } 895 896 // Add the mask index for the new shuffle vector. 897 Ops.push_back(Idx + OpNo * NewElts); 898 } 899 900 if (useBuildVector) { 901 EVT EltVT = NewVT.getVectorElementType(); 902 SmallVector<SDValue, 16> SVOps; 903 904 // Extract the input elements by hand. 905 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 906 // The mask element. This indexes into the input. 907 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 908 909 // The input vector this mask element indexes into. 910 unsigned Input = (unsigned)Idx / NewElts; 911 912 if (Input >= array_lengthof(Inputs)) { 913 // The mask element is "undef" or indexes off the end of the input. 914 SVOps.push_back(DAG.getUNDEF(EltVT)); 915 continue; 916 } 917 918 // Turn the index into an offset from the start of the input vector. 919 Idx -= Input * NewElts; 920 921 // Extract the vector element by hand. 922 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 923 Inputs[Input], DAG.getIntPtrConstant(Idx))); 924 } 925 926 // Construct the Lo/Hi output using a BUILD_VECTOR. 927 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size()); 928 } else if (InputUsed[0] == -1U) { 929 // No input vectors were used! The result is undefined. 930 Output = DAG.getUNDEF(NewVT); 931 } else { 932 SDValue Op0 = Inputs[InputUsed[0]]; 933 // If only one input was used, use an undefined vector for the other. 934 SDValue Op1 = InputUsed[1] == -1U ? 935 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]]; 936 // At least one input vector was used. Create a new shuffle vector. 937 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]); 938 } 939 940 Ops.clear(); 941 } 942} 943 944 945//===----------------------------------------------------------------------===// 946// Operand Vector Splitting 947//===----------------------------------------------------------------------===// 948 949/// SplitVectorOperand - This method is called when the specified operand of the 950/// specified node is found to need vector splitting. At this point, all of the 951/// result types of the node are known to be legal, but other operands of the 952/// node may need legalization as well as the specified one. 953bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { 954 DEBUG(dbgs() << "Split node operand: "; 955 N->dump(&DAG); 956 dbgs() << "\n"); 957 SDValue Res = SDValue(); 958 959 if (Res.getNode() == 0) { 960 switch (N->getOpcode()) { 961 default: 962#ifndef NDEBUG 963 dbgs() << "SplitVectorOperand Op #" << OpNo << ": "; 964 N->dump(&DAG); 965 dbgs() << "\n"; 966#endif 967 llvm_unreachable("Do not know how to split this operator's operand!"); 968 969 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break; 970 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; 971 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; 972 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; 973 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; 974 case ISD::STORE: 975 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo); 976 break; 977 978 case ISD::CTTZ: 979 case ISD::CTLZ: 980 case ISD::CTPOP: 981 case ISD::FP_EXTEND: 982 case ISD::FP_TO_SINT: 983 case ISD::FP_TO_UINT: 984 case ISD::SINT_TO_FP: 985 case ISD::UINT_TO_FP: 986 case ISD::FTRUNC: 987 case ISD::TRUNCATE: 988 case ISD::SIGN_EXTEND: 989 case ISD::ZERO_EXTEND: 990 case ISD::ANY_EXTEND: 991 Res = SplitVecOp_UnaryOp(N); 992 break; 993 } 994 } 995 996 // If the result is null, the sub-method took care of registering results etc. 997 if (!Res.getNode()) return false; 998 999 // If the result is N, the sub-method updated N in place. Tell the legalizer 1000 // core about this. 1001 if (Res.getNode() == N) 1002 return true; 1003 1004 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1005 "Invalid operand expansion"); 1006 1007 ReplaceValueWith(SDValue(N, 0), Res); 1008 return false; 1009} 1010 1011SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) { 1012 // The result has a legal vector type, but the input needs splitting. 1013 EVT ResVT = N->getValueType(0); 1014 SDValue Lo, Hi; 1015 DebugLoc dl = N->getDebugLoc(); 1016 GetSplitVector(N->getOperand(0), Lo, Hi); 1017 EVT InVT = Lo.getValueType(); 1018 1019 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1020 InVT.getVectorNumElements()); 1021 1022 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); 1023 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); 1024 1025 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); 1026} 1027 1028SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) { 1029 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will 1030 // end up being split all the way down to individual components. Convert the 1031 // split pieces into integers and reassemble. 1032 SDValue Lo, Hi; 1033 GetSplitVector(N->getOperand(0), Lo, Hi); 1034 Lo = BitConvertToInteger(Lo); 1035 Hi = BitConvertToInteger(Hi); 1036 1037 if (TLI.isBigEndian()) 1038 std::swap(Lo, Hi); 1039 1040 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0), 1041 JoinIntegers(Lo, Hi)); 1042} 1043 1044SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 1045 // We know that the extracted result type is legal. 1046 EVT SubVT = N->getValueType(0); 1047 SDValue Idx = N->getOperand(1); 1048 DebugLoc dl = N->getDebugLoc(); 1049 SDValue Lo, Hi; 1050 GetSplitVector(N->getOperand(0), Lo, Hi); 1051 1052 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1053 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1054 1055 if (IdxVal < LoElts) { 1056 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && 1057 "Extracted subvector crosses vector split!"); 1058 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); 1059 } else { 1060 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, 1061 DAG.getConstant(IdxVal - LoElts, Idx.getValueType())); 1062 } 1063} 1064 1065SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 1066 SDValue Vec = N->getOperand(0); 1067 SDValue Idx = N->getOperand(1); 1068 EVT VecVT = Vec.getValueType(); 1069 1070 if (isa<ConstantSDNode>(Idx)) { 1071 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1072 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); 1073 1074 SDValue Lo, Hi; 1075 GetSplitVector(Vec, Lo, Hi); 1076 1077 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1078 1079 if (IdxVal < LoElts) 1080 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0); 1081 return SDValue(DAG.UpdateNodeOperands(N, Hi, 1082 DAG.getConstant(IdxVal - LoElts, 1083 Idx.getValueType())), 0); 1084 } 1085 1086 // Store the vector to the stack. 1087 EVT EltVT = VecVT.getVectorElementType(); 1088 DebugLoc dl = N->getDebugLoc(); 1089 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 1090 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 1091 MachinePointerInfo(), false, false, 0); 1092 1093 // Load back the required element. 1094 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 1095 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, 1096 MachinePointerInfo(), EltVT, false, false, 0); 1097} 1098 1099SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { 1100 assert(N->isUnindexed() && "Indexed store of vector?"); 1101 assert(OpNo == 1 && "Can only split the stored value"); 1102 DebugLoc DL = N->getDebugLoc(); 1103 1104 bool isTruncating = N->isTruncatingStore(); 1105 SDValue Ch = N->getChain(); 1106 SDValue Ptr = N->getBasePtr(); 1107 EVT MemoryVT = N->getMemoryVT(); 1108 unsigned Alignment = N->getOriginalAlignment(); 1109 bool isVol = N->isVolatile(); 1110 bool isNT = N->isNonTemporal(); 1111 SDValue Lo, Hi; 1112 GetSplitVector(N->getOperand(1), Lo, Hi); 1113 1114 EVT LoMemVT, HiMemVT; 1115 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 1116 1117 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 1118 1119 if (isTruncating) 1120 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1121 LoMemVT, isVol, isNT, Alignment); 1122 else 1123 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1124 isVol, isNT, Alignment); 1125 1126 // Increment the pointer to the other half. 1127 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, 1128 DAG.getIntPtrConstant(IncrementSize)); 1129 1130 if (isTruncating) 1131 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr, 1132 N->getPointerInfo().getWithOffset(IncrementSize), 1133 HiMemVT, isVol, isNT, Alignment); 1134 else 1135 Hi = DAG.getStore(Ch, DL, Hi, Ptr, 1136 N->getPointerInfo().getWithOffset(IncrementSize), 1137 isVol, isNT, Alignment); 1138 1139 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi); 1140} 1141 1142SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) { 1143 DebugLoc DL = N->getDebugLoc(); 1144 1145 // The input operands all must have the same type, and we know the result the 1146 // result type is valid. Convert this to a buildvector which extracts all the 1147 // input elements. 1148 // TODO: If the input elements are power-two vectors, we could convert this to 1149 // a new CONCAT_VECTORS node with elements that are half-wide. 1150 SmallVector<SDValue, 32> Elts; 1151 EVT EltVT = N->getValueType(0).getVectorElementType(); 1152 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1153 SDValue Op = N->getOperand(op); 1154 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements(); 1155 i != e; ++i) { 1156 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, 1157 Op, DAG.getIntPtrConstant(i))); 1158 1159 } 1160 } 1161 1162 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), 1163 &Elts[0], Elts.size()); 1164} 1165 1166SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) { 1167 // The result has a legal vector type, but the input needs splitting. 1168 EVT ResVT = N->getValueType(0); 1169 SDValue Lo, Hi; 1170 DebugLoc DL = N->getDebugLoc(); 1171 GetSplitVector(N->getOperand(0), Lo, Hi); 1172 EVT InVT = Lo.getValueType(); 1173 1174 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1175 InVT.getVectorNumElements()); 1176 1177 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); 1178 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); 1179 1180 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); 1181} 1182 1183 1184 1185//===----------------------------------------------------------------------===// 1186// Result Vector Widening 1187//===----------------------------------------------------------------------===// 1188 1189void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { 1190 DEBUG(dbgs() << "Widen node result " << ResNo << ": "; 1191 N->dump(&DAG); 1192 dbgs() << "\n"); 1193 1194 // See if the target wants to custom widen this node. 1195 if (CustomWidenLowerNode(N, N->getValueType(ResNo))) 1196 return; 1197 1198 SDValue Res = SDValue(); 1199 switch (N->getOpcode()) { 1200 default: 1201#ifndef NDEBUG 1202 dbgs() << "WidenVectorResult #" << ResNo << ": "; 1203 N->dump(&DAG); 1204 dbgs() << "\n"; 1205#endif 1206 llvm_unreachable("Do not know how to widen the result of this operator!"); 1207 1208 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break; 1209 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; 1210 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break; 1211 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break; 1212 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; 1213 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break; 1214 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; 1215 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break; 1216 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break; 1217 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break; 1218 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break; 1219 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; 1220 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; 1221 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break; 1222 case ISD::VECTOR_SHUFFLE: 1223 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N)); 1224 break; 1225 case ISD::VSETCC: 1226 Res = WidenVecRes_VSETCC(N); 1227 break; 1228 1229 case ISD::ADD: 1230 case ISD::AND: 1231 case ISD::BSWAP: 1232 case ISD::FADD: 1233 case ISD::FCOPYSIGN: 1234 case ISD::FDIV: 1235 case ISD::FMUL: 1236 case ISD::FPOW: 1237 case ISD::FREM: 1238 case ISD::FSUB: 1239 case ISD::MUL: 1240 case ISD::MULHS: 1241 case ISD::MULHU: 1242 case ISD::OR: 1243 case ISD::SDIV: 1244 case ISD::SREM: 1245 case ISD::UDIV: 1246 case ISD::UREM: 1247 case ISD::SUB: 1248 case ISD::XOR: 1249 Res = WidenVecRes_Binary(N); 1250 break; 1251 1252 case ISD::FPOWI: 1253 Res = WidenVecRes_POWI(N); 1254 break; 1255 1256 case ISD::SHL: 1257 case ISD::SRA: 1258 case ISD::SRL: 1259 Res = WidenVecRes_Shift(N); 1260 break; 1261 1262 case ISD::ANY_EXTEND: 1263 case ISD::FP_EXTEND: 1264 case ISD::FP_ROUND: 1265 case ISD::FP_TO_SINT: 1266 case ISD::FP_TO_UINT: 1267 case ISD::SIGN_EXTEND: 1268 case ISD::SINT_TO_FP: 1269 case ISD::TRUNCATE: 1270 case ISD::UINT_TO_FP: 1271 case ISD::ZERO_EXTEND: 1272 Res = WidenVecRes_Convert(N); 1273 break; 1274 1275 case ISD::CTLZ: 1276 case ISD::CTPOP: 1277 case ISD::CTTZ: 1278 case ISD::FABS: 1279 case ISD::FCEIL: 1280 case ISD::FCOS: 1281 case ISD::FEXP: 1282 case ISD::FEXP2: 1283 case ISD::FFLOOR: 1284 case ISD::FLOG: 1285 case ISD::FLOG10: 1286 case ISD::FLOG2: 1287 case ISD::FNEARBYINT: 1288 case ISD::FNEG: 1289 case ISD::FRINT: 1290 case ISD::FSIN: 1291 case ISD::FSQRT: 1292 case ISD::FTRUNC: 1293 Res = WidenVecRes_Unary(N); 1294 break; 1295 } 1296 1297 // If Res is null, the sub-method took care of registering the result. 1298 if (Res.getNode()) 1299 SetWidenedVector(SDValue(N, ResNo), Res); 1300} 1301 1302SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) { 1303 // Binary op widening. 1304 unsigned Opcode = N->getOpcode(); 1305 DebugLoc dl = N->getDebugLoc(); 1306 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1307 EVT WidenEltVT = WidenVT.getVectorElementType(); 1308 EVT VT = WidenVT; 1309 unsigned NumElts = VT.getVectorNumElements(); 1310 while (!TLI.isTypeLegal(VT) && NumElts != 1) { 1311 NumElts = NumElts / 2; 1312 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1313 } 1314 1315 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) { 1316 // Operation doesn't trap so just widen as normal. 1317 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1318 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1319 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2); 1320 } 1321 1322 // No legal vector version so unroll the vector operation and then widen. 1323 if (NumElts == 1) 1324 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()); 1325 1326 // Since the operation can trap, apply operation on the original vector. 1327 EVT MaxVT = VT; 1328 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1329 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1330 unsigned CurNumElts = N->getValueType(0).getVectorNumElements(); 1331 1332 SmallVector<SDValue, 16> ConcatOps(CurNumElts); 1333 unsigned ConcatEnd = 0; // Current ConcatOps index. 1334 int Idx = 0; // Current Idx into input vectors. 1335 1336 // NumElts := greatest legal vector size (at most WidenVT) 1337 // while (orig. vector has unhandled elements) { 1338 // take munches of size NumElts from the beginning and add to ConcatOps 1339 // NumElts := next smaller supported vector size or 1 1340 // } 1341 while (CurNumElts != 0) { 1342 while (CurNumElts >= NumElts) { 1343 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, 1344 DAG.getIntPtrConstant(Idx)); 1345 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, 1346 DAG.getIntPtrConstant(Idx)); 1347 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2); 1348 Idx += NumElts; 1349 CurNumElts -= NumElts; 1350 } 1351 do { 1352 NumElts = NumElts / 2; 1353 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1354 } while (!TLI.isTypeLegal(VT) && NumElts != 1); 1355 1356 if (NumElts == 1) { 1357 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) { 1358 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1359 InOp1, DAG.getIntPtrConstant(Idx)); 1360 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1361 InOp2, DAG.getIntPtrConstant(Idx)); 1362 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT, 1363 EOp1, EOp2); 1364 } 1365 CurNumElts = 0; 1366 } 1367 } 1368 1369 // Check to see if we have a single operation with the widen type. 1370 if (ConcatEnd == 1) { 1371 VT = ConcatOps[0].getValueType(); 1372 if (VT == WidenVT) 1373 return ConcatOps[0]; 1374 } 1375 1376 // while (Some element of ConcatOps is not of type MaxVT) { 1377 // From the end of ConcatOps, collect elements of the same type and put 1378 // them into an op of the next larger supported type 1379 // } 1380 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) { 1381 Idx = ConcatEnd - 1; 1382 VT = ConcatOps[Idx--].getValueType(); 1383 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT) 1384 Idx--; 1385 1386 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1; 1387 EVT NextVT; 1388 do { 1389 NextSize *= 2; 1390 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize); 1391 } while (!TLI.isTypeLegal(NextVT)); 1392 1393 if (!VT.isVector()) { 1394 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT 1395 SDValue VecOp = DAG.getUNDEF(NextVT); 1396 unsigned NumToInsert = ConcatEnd - Idx - 1; 1397 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) { 1398 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, 1399 ConcatOps[OpIdx], DAG.getIntPtrConstant(i)); 1400 } 1401 ConcatOps[Idx+1] = VecOp; 1402 ConcatEnd = Idx + 2; 1403 } else { 1404 // Vector type, create a CONCAT_VECTORS of type NextVT 1405 SDValue undefVec = DAG.getUNDEF(VT); 1406 unsigned OpsToConcat = NextSize/VT.getVectorNumElements(); 1407 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat); 1408 unsigned RealVals = ConcatEnd - Idx - 1; 1409 unsigned SubConcatEnd = 0; 1410 unsigned SubConcatIdx = Idx + 1; 1411 while (SubConcatEnd < RealVals) 1412 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx]; 1413 while (SubConcatEnd < OpsToConcat) 1414 SubConcatOps[SubConcatEnd++] = undefVec; 1415 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1416 NextVT, &SubConcatOps[0], 1417 OpsToConcat); 1418 ConcatEnd = SubConcatIdx + 1; 1419 } 1420 } 1421 1422 // Check to see if we have a single operation with the widen type. 1423 if (ConcatEnd == 1) { 1424 VT = ConcatOps[0].getValueType(); 1425 if (VT == WidenVT) 1426 return ConcatOps[0]; 1427 } 1428 1429 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT 1430 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements(); 1431 if (NumOps != ConcatEnd ) { 1432 SDValue UndefVal = DAG.getUNDEF(MaxVT); 1433 for (unsigned j = ConcatEnd; j < NumOps; ++j) 1434 ConcatOps[j] = UndefVal; 1435 } 1436 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps); 1437} 1438 1439SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { 1440 SDValue InOp = N->getOperand(0); 1441 DebugLoc DL = N->getDebugLoc(); 1442 1443 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1444 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1445 1446 EVT InVT = InOp.getValueType(); 1447 EVT InEltVT = InVT.getVectorElementType(); 1448 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1449 1450 unsigned Opcode = N->getOpcode(); 1451 unsigned InVTNumElts = InVT.getVectorNumElements(); 1452 1453 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1454 InOp = GetWidenedVector(N->getOperand(0)); 1455 InVT = InOp.getValueType(); 1456 InVTNumElts = InVT.getVectorNumElements(); 1457 if (InVTNumElts == WidenNumElts) { 1458 if (N->getNumOperands() == 1) 1459 return DAG.getNode(Opcode, DL, WidenVT, InOp); 1460 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1)); 1461 } 1462 } 1463 1464 if (TLI.isTypeLegal(InWidenVT)) { 1465 // Because the result and the input are different vector types, widening 1466 // the result could create a legal type but widening the input might make 1467 // it an illegal type that might lead to repeatedly splitting the input 1468 // and then widening it. To avoid this, we widen the input only if 1469 // it results in a legal type. 1470 if (WidenNumElts % InVTNumElts == 0) { 1471 // Widen the input and call convert on the widened input vector. 1472 unsigned NumConcat = WidenNumElts/InVTNumElts; 1473 SmallVector<SDValue, 16> Ops(NumConcat); 1474 Ops[0] = InOp; 1475 SDValue UndefVal = DAG.getUNDEF(InVT); 1476 for (unsigned i = 1; i != NumConcat; ++i) 1477 Ops[i] = UndefVal; 1478 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, 1479 &Ops[0], NumConcat); 1480 if (N->getNumOperands() == 1) 1481 return DAG.getNode(Opcode, DL, WidenVT, InVec); 1482 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1)); 1483 } 1484 1485 if (InVTNumElts % WidenNumElts == 0) { 1486 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, 1487 InOp, DAG.getIntPtrConstant(0)); 1488 // Extract the input and convert the shorten input vector. 1489 if (N->getNumOperands() == 1) 1490 return DAG.getNode(Opcode, DL, WidenVT, InVal); 1491 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1)); 1492 } 1493 } 1494 1495 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1496 SmallVector<SDValue, 16> Ops(WidenNumElts); 1497 EVT EltVT = WidenVT.getVectorElementType(); 1498 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1499 unsigned i; 1500 for (i=0; i < MinElts; ++i) { 1501 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp, 1502 DAG.getIntPtrConstant(i)); 1503 if (N->getNumOperands() == 1) 1504 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val); 1505 else 1506 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1)); 1507 } 1508 1509 SDValue UndefVal = DAG.getUNDEF(EltVT); 1510 for (; i < WidenNumElts; ++i) 1511 Ops[i] = UndefVal; 1512 1513 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts); 1514} 1515 1516SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) { 1517 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1518 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1519 SDValue ShOp = N->getOperand(1); 1520 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1521} 1522 1523SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) { 1524 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1525 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1526 SDValue ShOp = N->getOperand(1); 1527 1528 EVT ShVT = ShOp.getValueType(); 1529 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) { 1530 ShOp = GetWidenedVector(ShOp); 1531 ShVT = ShOp.getValueType(); 1532 } 1533 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(), 1534 ShVT.getVectorElementType(), 1535 WidenVT.getVectorNumElements()); 1536 if (ShVT != ShWidenVT) 1537 ShOp = ModifyToType(ShOp, ShWidenVT); 1538 1539 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1540} 1541 1542SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) { 1543 // Unary op widening. 1544 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1545 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1546 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp); 1547} 1548 1549SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) { 1550 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1551 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), 1552 cast<VTSDNode>(N->getOperand(1))->getVT() 1553 .getVectorElementType(), 1554 WidenVT.getVectorNumElements()); 1555 SDValue WidenLHS = GetWidenedVector(N->getOperand(0)); 1556 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 1557 WidenVT, WidenLHS, DAG.getValueType(ExtVT)); 1558} 1559 1560SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) { 1561 SDValue InOp = N->getOperand(0); 1562 EVT InVT = InOp.getValueType(); 1563 EVT VT = N->getValueType(0); 1564 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1565 DebugLoc dl = N->getDebugLoc(); 1566 1567 switch (getTypeAction(InVT)) { 1568 default: 1569 assert(false && "Unknown type action!"); 1570 break; 1571 case TargetLowering::TypeLegal: 1572 break; 1573 case TargetLowering::TypePromoteInteger: 1574 // If the InOp is promoted to the same size, convert it. Otherwise, 1575 // fall out of the switch and widen the promoted input. 1576 InOp = GetPromotedInteger(InOp); 1577 InVT = InOp.getValueType(); 1578 if (WidenVT.bitsEq(InVT)) 1579 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1580 break; 1581 case TargetLowering::TypeSoftenFloat: 1582 case TargetLowering::TypeExpandInteger: 1583 case TargetLowering::TypeExpandFloat: 1584 case TargetLowering::TypeScalarizeVector: 1585 case TargetLowering::TypeSplitVector: 1586 break; 1587 case TargetLowering::TypeWidenVector: 1588 // If the InOp is widened to the same size, convert it. Otherwise, fall 1589 // out of the switch and widen the widened input. 1590 InOp = GetWidenedVector(InOp); 1591 InVT = InOp.getValueType(); 1592 if (WidenVT.bitsEq(InVT)) 1593 // The input widens to the same size. Convert to the widen value. 1594 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1595 break; 1596 } 1597 1598 unsigned WidenSize = WidenVT.getSizeInBits(); 1599 unsigned InSize = InVT.getSizeInBits(); 1600 // x86mmx is not an acceptable vector element type, so don't try. 1601 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) { 1602 // Determine new input vector type. The new input vector type will use 1603 // the same element type (if its a vector) or use the input type as a 1604 // vector. It is the same size as the type to widen to. 1605 EVT NewInVT; 1606 unsigned NewNumElts = WidenSize / InSize; 1607 if (InVT.isVector()) { 1608 EVT InEltVT = InVT.getVectorElementType(); 1609 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, 1610 WidenSize / InEltVT.getSizeInBits()); 1611 } else { 1612 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts); 1613 } 1614 1615 if (TLI.isTypeLegal(NewInVT)) { 1616 // Because the result and the input are different vector types, widening 1617 // the result could create a legal type but widening the input might make 1618 // it an illegal type that might lead to repeatedly splitting the input 1619 // and then widening it. To avoid this, we widen the input only if 1620 // it results in a legal type. 1621 SmallVector<SDValue, 16> Ops(NewNumElts); 1622 SDValue UndefVal = DAG.getUNDEF(InVT); 1623 Ops[0] = InOp; 1624 for (unsigned i = 1; i < NewNumElts; ++i) 1625 Ops[i] = UndefVal; 1626 1627 SDValue NewVec; 1628 if (InVT.isVector()) 1629 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1630 NewInVT, &Ops[0], NewNumElts); 1631 else 1632 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, 1633 NewInVT, &Ops[0], NewNumElts); 1634 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec); 1635 } 1636 } 1637 1638 return CreateStackStoreLoad(InOp, WidenVT); 1639} 1640 1641SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) { 1642 DebugLoc dl = N->getDebugLoc(); 1643 // Build a vector with undefined for the new nodes. 1644 EVT VT = N->getValueType(0); 1645 EVT EltVT = VT.getVectorElementType(); 1646 unsigned NumElts = VT.getVectorNumElements(); 1647 1648 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1649 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1650 1651 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end()); 1652 NewOps.reserve(WidenNumElts); 1653 for (unsigned i = NumElts; i < WidenNumElts; ++i) 1654 NewOps.push_back(DAG.getUNDEF(EltVT)); 1655 1656 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size()); 1657} 1658 1659SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) { 1660 EVT InVT = N->getOperand(0).getValueType(); 1661 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1662 DebugLoc dl = N->getDebugLoc(); 1663 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1664 unsigned NumInElts = InVT.getVectorNumElements(); 1665 unsigned NumOperands = N->getNumOperands(); 1666 1667 bool InputWidened = false; // Indicates we need to widen the input. 1668 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) { 1669 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) { 1670 // Add undef vectors to widen to correct length. 1671 unsigned NumConcat = WidenVT.getVectorNumElements() / 1672 InVT.getVectorNumElements(); 1673 SDValue UndefVal = DAG.getUNDEF(InVT); 1674 SmallVector<SDValue, 16> Ops(NumConcat); 1675 for (unsigned i=0; i < NumOperands; ++i) 1676 Ops[i] = N->getOperand(i); 1677 for (unsigned i = NumOperands; i != NumConcat; ++i) 1678 Ops[i] = UndefVal; 1679 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat); 1680 } 1681 } else { 1682 InputWidened = true; 1683 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) { 1684 // The inputs and the result are widen to the same value. 1685 unsigned i; 1686 for (i=1; i < NumOperands; ++i) 1687 if (N->getOperand(i).getOpcode() != ISD::UNDEF) 1688 break; 1689 1690 if (i == NumOperands) 1691 // Everything but the first operand is an UNDEF so just return the 1692 // widened first operand. 1693 return GetWidenedVector(N->getOperand(0)); 1694 1695 if (NumOperands == 2) { 1696 // Replace concat of two operands with a shuffle. 1697 SmallVector<int, 16> MaskOps(WidenNumElts, -1); 1698 for (unsigned i = 0; i < NumInElts; ++i) { 1699 MaskOps[i] = i; 1700 MaskOps[i + NumInElts] = i + WidenNumElts; 1701 } 1702 return DAG.getVectorShuffle(WidenVT, dl, 1703 GetWidenedVector(N->getOperand(0)), 1704 GetWidenedVector(N->getOperand(1)), 1705 &MaskOps[0]); 1706 } 1707 } 1708 } 1709 1710 // Fall back to use extracts and build vector. 1711 EVT EltVT = WidenVT.getVectorElementType(); 1712 SmallVector<SDValue, 16> Ops(WidenNumElts); 1713 unsigned Idx = 0; 1714 for (unsigned i=0; i < NumOperands; ++i) { 1715 SDValue InOp = N->getOperand(i); 1716 if (InputWidened) 1717 InOp = GetWidenedVector(InOp); 1718 for (unsigned j=0; j < NumInElts; ++j) 1719 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1720 DAG.getIntPtrConstant(j)); 1721 } 1722 SDValue UndefVal = DAG.getUNDEF(EltVT); 1723 for (; Idx < WidenNumElts; ++Idx) 1724 Ops[Idx] = UndefVal; 1725 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1726} 1727 1728SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { 1729 DebugLoc dl = N->getDebugLoc(); 1730 SDValue InOp = N->getOperand(0); 1731 SDValue RndOp = N->getOperand(3); 1732 SDValue SatOp = N->getOperand(4); 1733 1734 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1735 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1736 1737 EVT InVT = InOp.getValueType(); 1738 EVT InEltVT = InVT.getVectorElementType(); 1739 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1740 1741 SDValue DTyOp = DAG.getValueType(WidenVT); 1742 SDValue STyOp = DAG.getValueType(InWidenVT); 1743 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 1744 1745 unsigned InVTNumElts = InVT.getVectorNumElements(); 1746 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1747 InOp = GetWidenedVector(InOp); 1748 InVT = InOp.getValueType(); 1749 InVTNumElts = InVT.getVectorNumElements(); 1750 if (InVTNumElts == WidenNumElts) 1751 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1752 SatOp, CvtCode); 1753 } 1754 1755 if (TLI.isTypeLegal(InWidenVT)) { 1756 // Because the result and the input are different vector types, widening 1757 // the result could create a legal type but widening the input might make 1758 // it an illegal type that might lead to repeatedly splitting the input 1759 // and then widening it. To avoid this, we widen the input only if 1760 // it results in a legal type. 1761 if (WidenNumElts % InVTNumElts == 0) { 1762 // Widen the input and call convert on the widened input vector. 1763 unsigned NumConcat = WidenNumElts/InVTNumElts; 1764 SmallVector<SDValue, 16> Ops(NumConcat); 1765 Ops[0] = InOp; 1766 SDValue UndefVal = DAG.getUNDEF(InVT); 1767 for (unsigned i = 1; i != NumConcat; ++i) 1768 Ops[i] = UndefVal; 1769 1770 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat); 1771 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1772 SatOp, CvtCode); 1773 } 1774 1775 if (InVTNumElts % WidenNumElts == 0) { 1776 // Extract the input and convert the shorten input vector. 1777 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp, 1778 DAG.getIntPtrConstant(0)); 1779 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1780 SatOp, CvtCode); 1781 } 1782 } 1783 1784 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1785 SmallVector<SDValue, 16> Ops(WidenNumElts); 1786 EVT EltVT = WidenVT.getVectorElementType(); 1787 DTyOp = DAG.getValueType(EltVT); 1788 STyOp = DAG.getValueType(InEltVT); 1789 1790 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1791 unsigned i; 1792 for (i=0; i < MinElts; ++i) { 1793 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 1794 DAG.getIntPtrConstant(i)); 1795 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp, 1796 SatOp, CvtCode); 1797 } 1798 1799 SDValue UndefVal = DAG.getUNDEF(EltVT); 1800 for (; i < WidenNumElts; ++i) 1801 Ops[i] = UndefVal; 1802 1803 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1804} 1805 1806SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 1807 EVT VT = N->getValueType(0); 1808 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1809 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1810 SDValue InOp = N->getOperand(0); 1811 SDValue Idx = N->getOperand(1); 1812 DebugLoc dl = N->getDebugLoc(); 1813 1814 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 1815 InOp = GetWidenedVector(InOp); 1816 1817 EVT InVT = InOp.getValueType(); 1818 1819 // Check if we can just return the input vector after widening. 1820 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1821 if (IdxVal == 0 && InVT == WidenVT) 1822 return InOp; 1823 1824 // Check if we can extract from the vector. 1825 unsigned InNumElts = InVT.getVectorNumElements(); 1826 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts) 1827 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx); 1828 1829 // We could try widening the input to the right length but for now, extract 1830 // the original elements, fill the rest with undefs and build a vector. 1831 SmallVector<SDValue, 16> Ops(WidenNumElts); 1832 EVT EltVT = VT.getVectorElementType(); 1833 unsigned NumElts = VT.getVectorNumElements(); 1834 unsigned i; 1835 for (i=0; i < NumElts; ++i) 1836 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1837 DAG.getIntPtrConstant(IdxVal+i)); 1838 1839 SDValue UndefVal = DAG.getUNDEF(EltVT); 1840 for (; i < WidenNumElts; ++i) 1841 Ops[i] = UndefVal; 1842 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1843} 1844 1845SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) { 1846 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1847 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(), 1848 InOp.getValueType(), InOp, 1849 N->getOperand(1), N->getOperand(2)); 1850} 1851 1852SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) { 1853 LoadSDNode *LD = cast<LoadSDNode>(N); 1854 ISD::LoadExtType ExtType = LD->getExtensionType(); 1855 1856 SDValue Result; 1857 SmallVector<SDValue, 16> LdChain; // Chain for the series of load 1858 if (ExtType != ISD::NON_EXTLOAD) 1859 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); 1860 else 1861 Result = GenWidenVectorLoads(LdChain, LD); 1862 1863 // If we generate a single load, we can use that for the chain. Otherwise, 1864 // build a factor node to remember the multiple loads are independent and 1865 // chain to that. 1866 SDValue NewChain; 1867 if (LdChain.size() == 1) 1868 NewChain = LdChain[0]; 1869 else 1870 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other, 1871 &LdChain[0], LdChain.size()); 1872 1873 // Modified the chain - switch anything that used the old chain to use 1874 // the new one. 1875 ReplaceValueWith(SDValue(N, 1), NewChain); 1876 1877 return Result; 1878} 1879 1880SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) { 1881 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1882 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(), 1883 WidenVT, N->getOperand(0)); 1884} 1885 1886SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) { 1887 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1888 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1889 1890 SDValue Cond1 = N->getOperand(0); 1891 EVT CondVT = Cond1.getValueType(); 1892 if (CondVT.isVector()) { 1893 EVT CondEltVT = CondVT.getVectorElementType(); 1894 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), 1895 CondEltVT, WidenNumElts); 1896 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector) 1897 Cond1 = GetWidenedVector(Cond1); 1898 1899 if (Cond1.getValueType() != CondWidenVT) 1900 Cond1 = ModifyToType(Cond1, CondWidenVT); 1901 } 1902 1903 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 1904 SDValue InOp2 = GetWidenedVector(N->getOperand(2)); 1905 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT); 1906 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 1907 WidenVT, Cond1, InOp1, InOp2); 1908} 1909 1910SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) { 1911 SDValue InOp1 = GetWidenedVector(N->getOperand(2)); 1912 SDValue InOp2 = GetWidenedVector(N->getOperand(3)); 1913 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 1914 InOp1.getValueType(), N->getOperand(0), 1915 N->getOperand(1), InOp1, InOp2, N->getOperand(4)); 1916} 1917 1918SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) { 1919 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1920 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1921 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1922 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT, 1923 InOp1, InOp2, N->getOperand(2)); 1924} 1925 1926SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) { 1927 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1928 return DAG.getUNDEF(WidenVT); 1929} 1930 1931SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) { 1932 EVT VT = N->getValueType(0); 1933 DebugLoc dl = N->getDebugLoc(); 1934 1935 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1936 unsigned NumElts = VT.getVectorNumElements(); 1937 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1938 1939 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1940 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1941 1942 // Adjust mask based on new input vector length. 1943 SmallVector<int, 16> NewMask; 1944 for (unsigned i = 0; i != NumElts; ++i) { 1945 int Idx = N->getMaskElt(i); 1946 if (Idx < (int)NumElts) 1947 NewMask.push_back(Idx); 1948 else 1949 NewMask.push_back(Idx - NumElts + WidenNumElts); 1950 } 1951 for (unsigned i = NumElts; i != WidenNumElts; ++i) 1952 NewMask.push_back(-1); 1953 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]); 1954} 1955 1956SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) { 1957 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1958 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1959 1960 SDValue InOp1 = N->getOperand(0); 1961 EVT InVT = InOp1.getValueType(); 1962 assert(InVT.isVector() && "can not widen non vector type"); 1963 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(), 1964 InVT.getVectorElementType(), WidenNumElts); 1965 InOp1 = GetWidenedVector(InOp1); 1966 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1967 1968 // Assume that the input and output will be widen appropriately. If not, 1969 // we will have to unroll it at some point. 1970 assert(InOp1.getValueType() == WidenInVT && 1971 InOp2.getValueType() == WidenInVT && 1972 "Input not widened to expected type!"); 1973 (void)WidenInVT; 1974 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(), 1975 WidenVT, InOp1, InOp2, N->getOperand(2)); 1976} 1977 1978 1979//===----------------------------------------------------------------------===// 1980// Widen Vector Operand 1981//===----------------------------------------------------------------------===// 1982bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) { 1983 DEBUG(dbgs() << "Widen node operand " << ResNo << ": "; 1984 N->dump(&DAG); 1985 dbgs() << "\n"); 1986 SDValue Res = SDValue(); 1987 1988 switch (N->getOpcode()) { 1989 default: 1990#ifndef NDEBUG 1991 dbgs() << "WidenVectorOperand op #" << ResNo << ": "; 1992 N->dump(&DAG); 1993 dbgs() << "\n"; 1994#endif 1995 llvm_unreachable("Do not know how to widen this operator's operand!"); 1996 1997 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break; 1998 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break; 1999 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break; 2000 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break; 2001 case ISD::STORE: Res = WidenVecOp_STORE(N); break; 2002 2003 case ISD::FP_EXTEND: 2004 case ISD::FP_TO_SINT: 2005 case ISD::FP_TO_UINT: 2006 case ISD::SINT_TO_FP: 2007 case ISD::UINT_TO_FP: 2008 case ISD::TRUNCATE: 2009 case ISD::SIGN_EXTEND: 2010 case ISD::ZERO_EXTEND: 2011 case ISD::ANY_EXTEND: 2012 Res = WidenVecOp_Convert(N); 2013 break; 2014 } 2015 2016 // If Res is null, the sub-method took care of registering the result. 2017 if (!Res.getNode()) return false; 2018 2019 // If the result is N, the sub-method updated N in place. Tell the legalizer 2020 // core about this. 2021 if (Res.getNode() == N) 2022 return true; 2023 2024 2025 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2026 "Invalid operand expansion"); 2027 2028 ReplaceValueWith(SDValue(N, 0), Res); 2029 return false; 2030} 2031 2032SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) { 2033 // Since the result is legal and the input is illegal, it is unlikely 2034 // that we can fix the input to a legal type so unroll the convert 2035 // into some scalar code and create a nasty build vector. 2036 EVT VT = N->getValueType(0); 2037 EVT EltVT = VT.getVectorElementType(); 2038 DebugLoc dl = N->getDebugLoc(); 2039 unsigned NumElts = VT.getVectorNumElements(); 2040 SDValue InOp = N->getOperand(0); 2041 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2042 InOp = GetWidenedVector(InOp); 2043 EVT InVT = InOp.getValueType(); 2044 EVT InEltVT = InVT.getVectorElementType(); 2045 2046 unsigned Opcode = N->getOpcode(); 2047 SmallVector<SDValue, 16> Ops(NumElts); 2048 for (unsigned i=0; i < NumElts; ++i) 2049 Ops[i] = DAG.getNode(Opcode, dl, EltVT, 2050 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 2051 DAG.getIntPtrConstant(i))); 2052 2053 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2054} 2055 2056SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) { 2057 EVT VT = N->getValueType(0); 2058 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2059 EVT InWidenVT = InOp.getValueType(); 2060 DebugLoc dl = N->getDebugLoc(); 2061 2062 // Check if we can convert between two legal vector types and extract. 2063 unsigned InWidenSize = InWidenVT.getSizeInBits(); 2064 unsigned Size = VT.getSizeInBits(); 2065 // x86mmx is not an acceptable vector element type, so don't try. 2066 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) { 2067 unsigned NewNumElts = InWidenSize / Size; 2068 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); 2069 if (TLI.isTypeLegal(NewVT)) { 2070 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp); 2071 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, 2072 DAG.getIntPtrConstant(0)); 2073 } 2074 } 2075 2076 return CreateStackStoreLoad(InOp, VT); 2077} 2078 2079SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) { 2080 // If the input vector is not legal, it is likely that we will not find a 2081 // legal vector of the same size. Replace the concatenate vector with a 2082 // nasty build vector. 2083 EVT VT = N->getValueType(0); 2084 EVT EltVT = VT.getVectorElementType(); 2085 DebugLoc dl = N->getDebugLoc(); 2086 unsigned NumElts = VT.getVectorNumElements(); 2087 SmallVector<SDValue, 16> Ops(NumElts); 2088 2089 EVT InVT = N->getOperand(0).getValueType(); 2090 unsigned NumInElts = InVT.getVectorNumElements(); 2091 2092 unsigned Idx = 0; 2093 unsigned NumOperands = N->getNumOperands(); 2094 for (unsigned i=0; i < NumOperands; ++i) { 2095 SDValue InOp = N->getOperand(i); 2096 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2097 InOp = GetWidenedVector(InOp); 2098 for (unsigned j=0; j < NumInElts; ++j) 2099 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2100 DAG.getIntPtrConstant(j)); 2101 } 2102 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2103} 2104 2105SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 2106 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2107 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), 2108 N->getValueType(0), InOp, N->getOperand(1)); 2109} 2110 2111SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 2112 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2113 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 2114 N->getValueType(0), InOp, N->getOperand(1)); 2115} 2116 2117SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) { 2118 // We have to widen the value but we want only to store the original 2119 // vector type. 2120 StoreSDNode *ST = cast<StoreSDNode>(N); 2121 2122 SmallVector<SDValue, 16> StChain; 2123 if (ST->isTruncatingStore()) 2124 GenWidenVectorTruncStores(StChain, ST); 2125 else 2126 GenWidenVectorStores(StChain, ST); 2127 2128 if (StChain.size() == 1) 2129 return StChain[0]; 2130 else 2131 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(), 2132 MVT::Other,&StChain[0],StChain.size()); 2133} 2134 2135//===----------------------------------------------------------------------===// 2136// Vector Widening Utilities 2137//===----------------------------------------------------------------------===// 2138 2139// Utility function to find the type to chop up a widen vector for load/store 2140// TLI: Target lowering used to determine legal types. 2141// Width: Width left need to load/store. 2142// WidenVT: The widen vector type to load to/store from 2143// Align: If 0, don't allow use of a wider type 2144// WidenEx: If Align is not 0, the amount additional we can load/store from. 2145 2146static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, 2147 unsigned Width, EVT WidenVT, 2148 unsigned Align = 0, unsigned WidenEx = 0) { 2149 EVT WidenEltVT = WidenVT.getVectorElementType(); 2150 unsigned WidenWidth = WidenVT.getSizeInBits(); 2151 unsigned WidenEltWidth = WidenEltVT.getSizeInBits(); 2152 unsigned AlignInBits = Align*8; 2153 2154 // If we have one element to load/store, return it. 2155 EVT RetVT = WidenEltVT; 2156 if (Width == WidenEltWidth) 2157 return RetVT; 2158 2159 // See if there is larger legal integer than the element type to load/store 2160 unsigned VT; 2161 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE; 2162 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) { 2163 EVT MemVT((MVT::SimpleValueType) VT); 2164 unsigned MemVTWidth = MemVT.getSizeInBits(); 2165 if (MemVT.getSizeInBits() <= WidenEltWidth) 2166 break; 2167 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 && 2168 isPowerOf2_32(WidenWidth / MemVTWidth) && 2169 (MemVTWidth <= Width || 2170 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2171 RetVT = MemVT; 2172 break; 2173 } 2174 } 2175 2176 // See if there is a larger vector type to load/store that has the same vector 2177 // element type and is evenly divisible with the WidenVT. 2178 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; 2179 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) { 2180 EVT MemVT = (MVT::SimpleValueType) VT; 2181 unsigned MemVTWidth = MemVT.getSizeInBits(); 2182 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() && 2183 (WidenWidth % MemVTWidth) == 0 && 2184 isPowerOf2_32(WidenWidth / MemVTWidth) && 2185 (MemVTWidth <= Width || 2186 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2187 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT) 2188 return MemVT; 2189 } 2190 } 2191 2192 return RetVT; 2193} 2194 2195// Builds a vector type from scalar loads 2196// VecTy: Resulting Vector type 2197// LDOps: Load operators to build a vector type 2198// [Start,End) the list of loads to use. 2199static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, 2200 SmallVector<SDValue, 16>& LdOps, 2201 unsigned Start, unsigned End) { 2202 DebugLoc dl = LdOps[Start].getDebugLoc(); 2203 EVT LdTy = LdOps[Start].getValueType(); 2204 unsigned Width = VecTy.getSizeInBits(); 2205 unsigned NumElts = Width / LdTy.getSizeInBits(); 2206 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts); 2207 2208 unsigned Idx = 1; 2209 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]); 2210 2211 for (unsigned i = Start + 1; i != End; ++i) { 2212 EVT NewLdTy = LdOps[i].getValueType(); 2213 if (NewLdTy != LdTy) { 2214 NumElts = Width / NewLdTy.getSizeInBits(); 2215 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts); 2216 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp); 2217 // Readjust position and vector position based on new load type 2218 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits(); 2219 LdTy = NewLdTy; 2220 } 2221 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], 2222 DAG.getIntPtrConstant(Idx++)); 2223 } 2224 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp); 2225} 2226 2227SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain, 2228 LoadSDNode *LD) { 2229 // The strategy assumes that we can efficiently load powers of two widths. 2230 // The routines chops the vector into the largest vector loads with the same 2231 // element type or scalar loads and then recombines it to the widen vector 2232 // type. 2233 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2234 unsigned WidenWidth = WidenVT.getSizeInBits(); 2235 EVT LdVT = LD->getMemoryVT(); 2236 DebugLoc dl = LD->getDebugLoc(); 2237 assert(LdVT.isVector() && WidenVT.isVector()); 2238 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType()); 2239 2240 // Load information 2241 SDValue Chain = LD->getChain(); 2242 SDValue BasePtr = LD->getBasePtr(); 2243 unsigned Align = LD->getAlignment(); 2244 bool isVolatile = LD->isVolatile(); 2245 bool isNonTemporal = LD->isNonTemporal(); 2246 2247 int LdWidth = LdVT.getSizeInBits(); 2248 int WidthDiff = WidenWidth - LdWidth; // Difference 2249 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads 2250 2251 // Find the vector type that can load from. 2252 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2253 int NewVTWidth = NewVT.getSizeInBits(); 2254 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(), 2255 isVolatile, isNonTemporal, Align); 2256 LdChain.push_back(LdOp.getValue(1)); 2257 2258 // Check if we can load the element with one instruction 2259 if (LdWidth <= NewVTWidth) { 2260 if (!NewVT.isVector()) { 2261 unsigned NumElts = WidenWidth / NewVTWidth; 2262 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2263 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp); 2264 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp); 2265 } 2266 if (NewVT == WidenVT) 2267 return LdOp; 2268 2269 assert(WidenWidth % NewVTWidth == 0); 2270 unsigned NumConcat = WidenWidth / NewVTWidth; 2271 SmallVector<SDValue, 16> ConcatOps(NumConcat); 2272 SDValue UndefVal = DAG.getUNDEF(NewVT); 2273 ConcatOps[0] = LdOp; 2274 for (unsigned i = 1; i != NumConcat; ++i) 2275 ConcatOps[i] = UndefVal; 2276 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], 2277 NumConcat); 2278 } 2279 2280 // Load vector by using multiple loads from largest vector to scalar 2281 SmallVector<SDValue, 16> LdOps; 2282 LdOps.push_back(LdOp); 2283 2284 LdWidth -= NewVTWidth; 2285 unsigned Offset = 0; 2286 2287 while (LdWidth > 0) { 2288 unsigned Increment = NewVTWidth / 8; 2289 Offset += Increment; 2290 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2291 DAG.getIntPtrConstant(Increment)); 2292 2293 if (LdWidth < NewVTWidth) { 2294 // Our current type we are using is too large, find a better size 2295 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2296 NewVTWidth = NewVT.getSizeInBits(); 2297 } 2298 2299 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, 2300 LD->getPointerInfo().getWithOffset(Offset), 2301 isVolatile, 2302 isNonTemporal, MinAlign(Align, Increment)); 2303 LdChain.push_back(LdOp.getValue(1)); 2304 LdOps.push_back(LdOp); 2305 2306 LdWidth -= NewVTWidth; 2307 } 2308 2309 // Build the vector from the loads operations 2310 unsigned End = LdOps.size(); 2311 if (!LdOps[0].getValueType().isVector()) 2312 // All the loads are scalar loads. 2313 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End); 2314 2315 // If the load contains vectors, build the vector using concat vector. 2316 // All of the vectors used to loads are power of 2 and the scalars load 2317 // can be combined to make a power of 2 vector. 2318 SmallVector<SDValue, 16> ConcatOps(End); 2319 int i = End - 1; 2320 int Idx = End; 2321 EVT LdTy = LdOps[i].getValueType(); 2322 // First combine the scalar loads to a vector 2323 if (!LdTy.isVector()) { 2324 for (--i; i >= 0; --i) { 2325 LdTy = LdOps[i].getValueType(); 2326 if (LdTy.isVector()) 2327 break; 2328 } 2329 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End); 2330 } 2331 ConcatOps[--Idx] = LdOps[i]; 2332 for (--i; i >= 0; --i) { 2333 EVT NewLdTy = LdOps[i].getValueType(); 2334 if (NewLdTy != LdTy) { 2335 // Create a larger vector 2336 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy, 2337 &ConcatOps[Idx], End - Idx); 2338 Idx = End - 1; 2339 LdTy = NewLdTy; 2340 } 2341 ConcatOps[--Idx] = LdOps[i]; 2342 } 2343 2344 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx)) 2345 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, 2346 &ConcatOps[Idx], End - Idx); 2347 2348 // We need to fill the rest with undefs to build the vector 2349 unsigned NumOps = WidenWidth / LdTy.getSizeInBits(); 2350 SmallVector<SDValue, 16> WidenOps(NumOps); 2351 SDValue UndefVal = DAG.getUNDEF(LdTy); 2352 { 2353 unsigned i = 0; 2354 for (; i != End-Idx; ++i) 2355 WidenOps[i] = ConcatOps[Idx+i]; 2356 for (; i != NumOps; ++i) 2357 WidenOps[i] = UndefVal; 2358 } 2359 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps); 2360} 2361 2362SDValue 2363DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain, 2364 LoadSDNode * LD, 2365 ISD::LoadExtType ExtType) { 2366 // For extension loads, it may not be more efficient to chop up the vector 2367 // and then extended it. Instead, we unroll the load and build a new vector. 2368 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2369 EVT LdVT = LD->getMemoryVT(); 2370 DebugLoc dl = LD->getDebugLoc(); 2371 assert(LdVT.isVector() && WidenVT.isVector()); 2372 2373 // Load information 2374 SDValue Chain = LD->getChain(); 2375 SDValue BasePtr = LD->getBasePtr(); 2376 unsigned Align = LD->getAlignment(); 2377 bool isVolatile = LD->isVolatile(); 2378 bool isNonTemporal = LD->isNonTemporal(); 2379 2380 EVT EltVT = WidenVT.getVectorElementType(); 2381 EVT LdEltVT = LdVT.getVectorElementType(); 2382 unsigned NumElts = LdVT.getVectorNumElements(); 2383 2384 // Load each element and widen 2385 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2386 SmallVector<SDValue, 16> Ops(WidenNumElts); 2387 unsigned Increment = LdEltVT.getSizeInBits() / 8; 2388 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, 2389 LD->getPointerInfo(), 2390 LdEltVT, isVolatile, isNonTemporal, Align); 2391 LdChain.push_back(Ops[0].getValue(1)); 2392 unsigned i = 0, Offset = Increment; 2393 for (i=1; i < NumElts; ++i, Offset += Increment) { 2394 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2395 BasePtr, DAG.getIntPtrConstant(Offset)); 2396 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, 2397 LD->getPointerInfo().getWithOffset(Offset), LdEltVT, 2398 isVolatile, isNonTemporal, Align); 2399 LdChain.push_back(Ops[i].getValue(1)); 2400 } 2401 2402 // Fill the rest with undefs 2403 SDValue UndefVal = DAG.getUNDEF(EltVT); 2404 for (; i != WidenNumElts; ++i) 2405 Ops[i] = UndefVal; 2406 2407 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size()); 2408} 2409 2410 2411void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, 2412 StoreSDNode *ST) { 2413 // The strategy assumes that we can efficiently store powers of two widths. 2414 // The routines chops the vector into the largest vector stores with the same 2415 // element type or scalar stores. 2416 SDValue Chain = ST->getChain(); 2417 SDValue BasePtr = ST->getBasePtr(); 2418 unsigned Align = ST->getAlignment(); 2419 bool isVolatile = ST->isVolatile(); 2420 bool isNonTemporal = ST->isNonTemporal(); 2421 SDValue ValOp = GetWidenedVector(ST->getValue()); 2422 DebugLoc dl = ST->getDebugLoc(); 2423 2424 EVT StVT = ST->getMemoryVT(); 2425 unsigned StWidth = StVT.getSizeInBits(); 2426 EVT ValVT = ValOp.getValueType(); 2427 unsigned ValWidth = ValVT.getSizeInBits(); 2428 EVT ValEltVT = ValVT.getVectorElementType(); 2429 unsigned ValEltWidth = ValEltVT.getSizeInBits(); 2430 assert(StVT.getVectorElementType() == ValEltVT); 2431 2432 int Idx = 0; // current index to store 2433 unsigned Offset = 0; // offset from base to store 2434 while (StWidth != 0) { 2435 // Find the largest vector type we can store with 2436 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT); 2437 unsigned NewVTWidth = NewVT.getSizeInBits(); 2438 unsigned Increment = NewVTWidth / 8; 2439 if (NewVT.isVector()) { 2440 unsigned NumVTElts = NewVT.getVectorNumElements(); 2441 do { 2442 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, 2443 DAG.getIntPtrConstant(Idx)); 2444 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2445 ST->getPointerInfo().getWithOffset(Offset), 2446 isVolatile, isNonTemporal, 2447 MinAlign(Align, Offset))); 2448 StWidth -= NewVTWidth; 2449 Offset += Increment; 2450 Idx += NumVTElts; 2451 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2452 DAG.getIntPtrConstant(Increment)); 2453 } while (StWidth != 0 && StWidth >= NewVTWidth); 2454 } else { 2455 // Cast the vector to the scalar type we can store 2456 unsigned NumElts = ValWidth / NewVTWidth; 2457 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2458 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); 2459 // Readjust index position based on new vector type 2460 Idx = Idx * ValEltWidth / NewVTWidth; 2461 do { 2462 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp, 2463 DAG.getIntPtrConstant(Idx++)); 2464 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2465 ST->getPointerInfo().getWithOffset(Offset), 2466 isVolatile, isNonTemporal, 2467 MinAlign(Align, Offset))); 2468 StWidth -= NewVTWidth; 2469 Offset += Increment; 2470 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2471 DAG.getIntPtrConstant(Increment)); 2472 } while (StWidth != 0 && StWidth >= NewVTWidth); 2473 // Restore index back to be relative to the original widen element type 2474 Idx = Idx * NewVTWidth / ValEltWidth; 2475 } 2476 } 2477} 2478 2479void 2480DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain, 2481 StoreSDNode *ST) { 2482 // For extension loads, it may not be more efficient to truncate the vector 2483 // and then store it. Instead, we extract each element and then store it. 2484 SDValue Chain = ST->getChain(); 2485 SDValue BasePtr = ST->getBasePtr(); 2486 unsigned Align = ST->getAlignment(); 2487 bool isVolatile = ST->isVolatile(); 2488 bool isNonTemporal = ST->isNonTemporal(); 2489 SDValue ValOp = GetWidenedVector(ST->getValue()); 2490 DebugLoc dl = ST->getDebugLoc(); 2491 2492 EVT StVT = ST->getMemoryVT(); 2493 EVT ValVT = ValOp.getValueType(); 2494 2495 // It must be true that we the widen vector type is bigger than where 2496 // we need to store. 2497 assert(StVT.isVector() && ValOp.getValueType().isVector()); 2498 assert(StVT.bitsLT(ValOp.getValueType())); 2499 2500 // For truncating stores, we can not play the tricks of chopping legal 2501 // vector types and bit cast it to the right type. Instead, we unroll 2502 // the store. 2503 EVT StEltVT = StVT.getVectorElementType(); 2504 EVT ValEltVT = ValVT.getVectorElementType(); 2505 unsigned Increment = ValEltVT.getSizeInBits() / 8; 2506 unsigned NumElts = StVT.getVectorNumElements(); 2507 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2508 DAG.getIntPtrConstant(0)); 2509 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, 2510 ST->getPointerInfo(), StEltVT, 2511 isVolatile, isNonTemporal, Align)); 2512 unsigned Offset = Increment; 2513 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) { 2514 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2515 BasePtr, DAG.getIntPtrConstant(Offset)); 2516 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2517 DAG.getIntPtrConstant(0)); 2518 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, 2519 ST->getPointerInfo().getWithOffset(Offset), 2520 StEltVT, isVolatile, isNonTemporal, 2521 MinAlign(Align, Offset))); 2522 } 2523} 2524 2525/// Modifies a vector input (widen or narrows) to a vector of NVT. The 2526/// input vector must have the same element type as NVT. 2527SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) { 2528 // Note that InOp might have been widened so it might already have 2529 // the right width or it might need be narrowed. 2530 EVT InVT = InOp.getValueType(); 2531 assert(InVT.getVectorElementType() == NVT.getVectorElementType() && 2532 "input and widen element type must match"); 2533 DebugLoc dl = InOp.getDebugLoc(); 2534 2535 // Check if InOp already has the right width. 2536 if (InVT == NVT) 2537 return InOp; 2538 2539 unsigned InNumElts = InVT.getVectorNumElements(); 2540 unsigned WidenNumElts = NVT.getVectorNumElements(); 2541 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) { 2542 unsigned NumConcat = WidenNumElts / InNumElts; 2543 SmallVector<SDValue, 16> Ops(NumConcat); 2544 SDValue UndefVal = DAG.getUNDEF(InVT); 2545 Ops[0] = InOp; 2546 for (unsigned i = 1; i != NumConcat; ++i) 2547 Ops[i] = UndefVal; 2548 2549 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat); 2550 } 2551 2552 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts) 2553 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp, 2554 DAG.getIntPtrConstant(0)); 2555 2556 // Fall back to extract and build. 2557 SmallVector<SDValue, 16> Ops(WidenNumElts); 2558 EVT EltVT = NVT.getVectorElementType(); 2559 unsigned MinNumElts = std::min(WidenNumElts, InNumElts); 2560 unsigned Idx; 2561 for (Idx = 0; Idx < MinNumElts; ++Idx) 2562 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2563 DAG.getIntPtrConstant(Idx)); 2564 2565 SDValue UndefVal = DAG.getUNDEF(EltVT); 2566 for ( ; Idx < WidenNumElts; ++Idx) 2567 Ops[Idx] = UndefVal; 2568 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts); 2569} 2570