LegalizeVectorTypes.cpp revision d752e0f7e64585839cb3a458ef52456eaebbea3c
1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file performs vector type splitting and scalarization for LegalizeTypes. 11// Scalarization is the act of changing a computation in an illegal one-element 12// vector type to be a computation in its scalar element type. For example, 13// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed 14// as a base case when scalarizing vector arithmetic like <4 x f32>, which 15// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32 16// types. 17// Splitting is the act of changing a computation in an invalid vector type to 18// be a computation in two vectors of half the size. For example, implementing 19// <128 x f32> operations in terms of two <64 x f32> operations. 20// 21//===----------------------------------------------------------------------===// 22 23#include "LegalizeTypes.h" 24#include "llvm/CodeGen/PseudoSourceValue.h" 25#include "llvm/Target/TargetData.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Support/raw_ostream.h" 28using namespace llvm; 29 30//===----------------------------------------------------------------------===// 31// Result Vector Scalarization: <1 x ty> -> ty. 32//===----------------------------------------------------------------------===// 33 34void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { 35 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; 36 N->dump(&DAG); 37 dbgs() << "\n"); 38 SDValue R = SDValue(); 39 40 switch (N->getOpcode()) { 41 default: 42#ifndef NDEBUG 43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": "; 44 N->dump(&DAG); 45 dbgs() << "\n"; 46#endif 47 report_fatal_error("Do not know how to scalarize the result of this " 48 "operator!\n"); 49 50 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; 51 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 52 case ISD::BUILD_VECTOR: R = N->getOperand(0); break; 53 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; 54 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 55 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; 56 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; 57 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 58 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 59 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; 60 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; 61 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; 62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break; 63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; 65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; 66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; 67 case ISD::ANY_EXTEND: 68 case ISD::CTLZ: 69 case ISD::CTPOP: 70 case ISD::CTTZ: 71 case ISD::FABS: 72 case ISD::FCEIL: 73 case ISD::FCOS: 74 case ISD::FEXP: 75 case ISD::FEXP2: 76 case ISD::FFLOOR: 77 case ISD::FLOG: 78 case ISD::FLOG10: 79 case ISD::FLOG2: 80 case ISD::FNEARBYINT: 81 case ISD::FNEG: 82 case ISD::FP_EXTEND: 83 case ISD::FP_TO_SINT: 84 case ISD::FP_TO_UINT: 85 case ISD::FRINT: 86 case ISD::FSIN: 87 case ISD::FSQRT: 88 case ISD::FTRUNC: 89 case ISD::SIGN_EXTEND: 90 case ISD::SINT_TO_FP: 91 case ISD::TRUNCATE: 92 case ISD::UINT_TO_FP: 93 case ISD::ZERO_EXTEND: 94 R = ScalarizeVecRes_UnaryOp(N); 95 break; 96 97 case ISD::ADD: 98 case ISD::AND: 99 case ISD::FADD: 100 case ISD::FDIV: 101 case ISD::FMUL: 102 case ISD::FPOW: 103 case ISD::FREM: 104 case ISD::FSUB: 105 case ISD::MUL: 106 case ISD::OR: 107 case ISD::SDIV: 108 case ISD::SREM: 109 case ISD::SUB: 110 case ISD::UDIV: 111 case ISD::UREM: 112 case ISD::XOR: 113 case ISD::SHL: 114 case ISD::SRA: 115 case ISD::SRL: 116 R = ScalarizeVecRes_BinOp(N); 117 break; 118 } 119 120 // If R is null, the sub-method took care of registering the result. 121 if (R.getNode()) 122 SetScalarizedVector(SDValue(N, ResNo), R); 123} 124 125SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { 126 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 127 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 128 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 129 LHS.getValueType(), LHS, RHS); 130} 131 132SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N, 133 unsigned ResNo) { 134 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); 135 return GetScalarizedVector(Op); 136} 137 138SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) { 139 EVT NewVT = N->getValueType(0).getVectorElementType(); 140 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 141 NewVT, N->getOperand(0)); 142} 143 144SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) { 145 EVT NewVT = N->getValueType(0).getVectorElementType(); 146 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); 147 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(), 148 Op0, DAG.getValueType(NewVT), 149 DAG.getValueType(Op0.getValueType()), 150 N->getOperand(3), 151 N->getOperand(4), 152 cast<CvtRndSatSDNode>(N)->getCvtCode()); 153} 154 155SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 156 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 157 N->getValueType(0).getVectorElementType(), 158 N->getOperand(0), N->getOperand(1)); 159} 160 161SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) { 162 EVT NewVT = N->getValueType(0).getVectorElementType(); 163 SDValue Op = GetScalarizedVector(N->getOperand(0)); 164 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), 165 NewVT, Op, N->getOperand(1)); 166} 167 168SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) { 169 SDValue Op = GetScalarizedVector(N->getOperand(0)); 170 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(), 171 Op.getValueType(), Op, N->getOperand(1)); 172} 173 174SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { 175 // The value to insert may have a wider type than the vector element type, 176 // so be sure to truncate it to the element type if necessary. 177 SDValue Op = N->getOperand(1); 178 EVT EltVT = N->getValueType(0).getVectorElementType(); 179 if (Op.getValueType() != EltVT) 180 // FIXME: Can this happen for floating point types? 181 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op); 182 return Op; 183} 184 185SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { 186 assert(N->isUnindexed() && "Indexed vector load?"); 187 188 SDValue Result = DAG.getLoad(ISD::UNINDEXED, 189 N->getExtensionType(), 190 N->getValueType(0).getVectorElementType(), 191 N->getDebugLoc(), 192 N->getChain(), N->getBasePtr(), 193 DAG.getUNDEF(N->getBasePtr().getValueType()), 194 N->getPointerInfo(), 195 N->getMemoryVT().getVectorElementType(), 196 N->isVolatile(), N->isNonTemporal(), 197 N->isInvariant(), N->getOriginalAlignment()); 198 199 // Legalized the chain result - switch anything that used the old chain to 200 // use the new one. 201 ReplaceValueWith(SDValue(N, 1), Result.getValue(1)); 202 return Result; 203} 204 205SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { 206 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp. 207 EVT DestVT = N->getValueType(0).getVectorElementType(); 208 SDValue Op = GetScalarizedVector(N->getOperand(0)); 209 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op); 210} 211 212SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) { 213 EVT EltVT = N->getValueType(0).getVectorElementType(); 214 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType(); 215 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 216 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT, 217 LHS, DAG.getValueType(ExtVT)); 218} 219 220SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) { 221 // If the operand is wider than the vector element type then it is implicitly 222 // truncated. Make that explicit here. 223 EVT EltVT = N->getValueType(0).getVectorElementType(); 224 SDValue InOp = N->getOperand(0); 225 if (InOp.getValueType() != EltVT) 226 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp); 227 return InOp; 228} 229 230SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) { 231 SDValue LHS = GetScalarizedVector(N->getOperand(1)); 232 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 233 LHS.getValueType(), N->getOperand(0), LHS, 234 GetScalarizedVector(N->getOperand(2))); 235} 236 237SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) { 238 SDValue LHS = GetScalarizedVector(N->getOperand(2)); 239 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(), 240 N->getOperand(0), N->getOperand(1), 241 LHS, GetScalarizedVector(N->getOperand(3)), 242 N->getOperand(4)); 243} 244 245SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) { 246 assert(N->getValueType(0).isVector() == 247 N->getOperand(0).getValueType().isVector() && 248 "Scalar/Vector type mismatch"); 249 250 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N); 251 252 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 253 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 254 DebugLoc DL = N->getDebugLoc(); 255 256 // Turn it into a scalar SETCC. 257 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); 258} 259 260SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { 261 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 262} 263 264SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { 265 // Figure out if the scalar is the LHS or RHS and return it. 266 SDValue Arg = N->getOperand(2).getOperand(0); 267 if (Arg.getOpcode() == ISD::UNDEF) 268 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 269 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue(); 270 return GetScalarizedVector(N->getOperand(Op)); 271} 272 273SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) { 274 assert(N->getValueType(0).isVector() && 275 N->getOperand(0).getValueType().isVector() && 276 "Operand types must be vectors"); 277 278 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 279 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 280 EVT NVT = N->getValueType(0).getVectorElementType(); 281 DebugLoc DL = N->getDebugLoc(); 282 283 // Turn it into a scalar SETCC. 284 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, 285 N->getOperand(2)); 286 // Vectors may have a different boolean contents to scalars. Promote the 287 // value appropriately. 288 ISD::NodeType ExtendCode = 289 TargetLowering::getExtendForContent(TLI.getBooleanContents(true)); 290 return DAG.getNode(ExtendCode, DL, NVT, Res); 291} 292 293 294//===----------------------------------------------------------------------===// 295// Operand Vector Scalarization <1 x ty> -> ty. 296//===----------------------------------------------------------------------===// 297 298bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { 299 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; 300 N->dump(&DAG); 301 dbgs() << "\n"); 302 SDValue Res = SDValue(); 303 304 if (Res.getNode() == 0) { 305 switch (N->getOpcode()) { 306 default: 307#ifndef NDEBUG 308 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": "; 309 N->dump(&DAG); 310 dbgs() << "\n"; 311#endif 312 llvm_unreachable("Do not know how to scalarize this operator's operand!"); 313 case ISD::BITCAST: 314 Res = ScalarizeVecOp_BITCAST(N); 315 break; 316 case ISD::CONCAT_VECTORS: 317 Res = ScalarizeVecOp_CONCAT_VECTORS(N); 318 break; 319 case ISD::EXTRACT_VECTOR_ELT: 320 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); 321 break; 322 case ISD::STORE: 323 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); 324 break; 325 } 326 } 327 328 // If the result is null, the sub-method took care of registering results etc. 329 if (!Res.getNode()) return false; 330 331 // If the result is N, the sub-method updated N in place. Tell the legalizer 332 // core about this. 333 if (Res.getNode() == N) 334 return true; 335 336 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 337 "Invalid operand expansion"); 338 339 ReplaceValueWith(SDValue(N, 0), Res); 340 return false; 341} 342 343/// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs 344/// to be scalarized, it must be <1 x ty>. Convert the element instead. 345SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) { 346 SDValue Elt = GetScalarizedVector(N->getOperand(0)); 347 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 348 N->getValueType(0), Elt); 349} 350 351/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one - 352/// use a BUILD_VECTOR instead. 353SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) { 354 SmallVector<SDValue, 8> Ops(N->getNumOperands()); 355 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 356 Ops[i] = GetScalarizedVector(N->getOperand(i)); 357 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0), 358 &Ops[0], Ops.size()); 359} 360 361/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to 362/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the 363/// index. 364SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 365 SDValue Res = GetScalarizedVector(N->getOperand(0)); 366 if (Res.getValueType() != N->getValueType(0)) 367 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), 368 Res); 369 return Res; 370} 371 372/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be 373/// scalarized, it must be <1 x ty>. Just store the element. 374SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ 375 assert(N->isUnindexed() && "Indexed store of one-element vector?"); 376 assert(OpNo == 1 && "Do not know how to scalarize this operand!"); 377 DebugLoc dl = N->getDebugLoc(); 378 379 if (N->isTruncatingStore()) 380 return DAG.getTruncStore(N->getChain(), dl, 381 GetScalarizedVector(N->getOperand(1)), 382 N->getBasePtr(), N->getPointerInfo(), 383 N->getMemoryVT().getVectorElementType(), 384 N->isVolatile(), N->isNonTemporal(), 385 N->getAlignment()); 386 387 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)), 388 N->getBasePtr(), N->getPointerInfo(), 389 N->isVolatile(), N->isNonTemporal(), 390 N->getOriginalAlignment()); 391} 392 393 394//===----------------------------------------------------------------------===// 395// Result Vector Splitting 396//===----------------------------------------------------------------------===// 397 398/// SplitVectorResult - This method is called when the specified result of the 399/// specified node is found to need vector splitting. At this point, the node 400/// may also have invalid operands or may have other results that need 401/// legalization, we just know that (at least) one result needs vector 402/// splitting. 403void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { 404 DEBUG(dbgs() << "Split node result: "; 405 N->dump(&DAG); 406 dbgs() << "\n"); 407 SDValue Lo, Hi; 408 409 switch (N->getOpcode()) { 410 default: 411#ifndef NDEBUG 412 dbgs() << "SplitVectorResult #" << ResNo << ": "; 413 N->dump(&DAG); 414 dbgs() << "\n"; 415#endif 416 llvm_unreachable("Do not know how to split the result of this operator!"); 417 418 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 419 case ISD::VSELECT: 420 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 421 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 422 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 423 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; 424 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 425 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 426 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; 427 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 428 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; 429 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 430 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break; 431 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 432 case ISD::LOAD: 433 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); 434 break; 435 case ISD::SETCC: 436 SplitVecRes_SETCC(N, Lo, Hi); 437 break; 438 case ISD::VECTOR_SHUFFLE: 439 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); 440 break; 441 442 case ISD::ANY_EXTEND: 443 case ISD::CONVERT_RNDSAT: 444 case ISD::CTLZ: 445 case ISD::CTPOP: 446 case ISD::CTTZ: 447 case ISD::FABS: 448 case ISD::FCEIL: 449 case ISD::FCOS: 450 case ISD::FEXP: 451 case ISD::FEXP2: 452 case ISD::FFLOOR: 453 case ISD::FLOG: 454 case ISD::FLOG10: 455 case ISD::FLOG2: 456 case ISD::FNEARBYINT: 457 case ISD::FNEG: 458 case ISD::FP_EXTEND: 459 case ISD::FP_ROUND: 460 case ISD::FP_TO_SINT: 461 case ISD::FP_TO_UINT: 462 case ISD::FRINT: 463 case ISD::FSIN: 464 case ISD::FSQRT: 465 case ISD::FTRUNC: 466 case ISD::SIGN_EXTEND: 467 case ISD::SINT_TO_FP: 468 case ISD::TRUNCATE: 469 case ISD::UINT_TO_FP: 470 case ISD::ZERO_EXTEND: 471 SplitVecRes_UnaryOp(N, Lo, Hi); 472 break; 473 474 case ISD::ADD: 475 case ISD::SUB: 476 case ISD::MUL: 477 case ISD::FADD: 478 case ISD::FSUB: 479 case ISD::FMUL: 480 case ISD::SDIV: 481 case ISD::UDIV: 482 case ISD::FDIV: 483 case ISD::FPOW: 484 case ISD::AND: 485 case ISD::OR: 486 case ISD::XOR: 487 case ISD::SHL: 488 case ISD::SRA: 489 case ISD::SRL: 490 case ISD::UREM: 491 case ISD::SREM: 492 case ISD::FREM: 493 SplitVecRes_BinOp(N, Lo, Hi); 494 break; 495 } 496 497 // If Lo/Hi is null, the sub-method took care of registering results etc. 498 if (Lo.getNode()) 499 SetSplitVector(SDValue(N, ResNo), Lo, Hi); 500} 501 502void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo, 503 SDValue &Hi) { 504 SDValue LHSLo, LHSHi; 505 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 506 SDValue RHSLo, RHSHi; 507 GetSplitVector(N->getOperand(1), RHSLo, RHSHi); 508 DebugLoc dl = N->getDebugLoc(); 509 510 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo); 511 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi); 512} 513 514void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, 515 SDValue &Hi) { 516 // We know the result is a vector. The input may be either a vector or a 517 // scalar value. 518 EVT LoVT, HiVT; 519 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 520 DebugLoc dl = N->getDebugLoc(); 521 522 SDValue InOp = N->getOperand(0); 523 EVT InVT = InOp.getValueType(); 524 525 // Handle some special cases efficiently. 526 switch (getTypeAction(InVT)) { 527 case TargetLowering::TypeLegal: 528 case TargetLowering::TypePromoteInteger: 529 case TargetLowering::TypeSoftenFloat: 530 case TargetLowering::TypeScalarizeVector: 531 case TargetLowering::TypeWidenVector: 532 break; 533 case TargetLowering::TypeExpandInteger: 534 case TargetLowering::TypeExpandFloat: 535 // A scalar to vector conversion, where the scalar needs expansion. 536 // If the vector is being split in two then we can just convert the 537 // expanded pieces. 538 if (LoVT == HiVT) { 539 GetExpandedOp(InOp, Lo, Hi); 540 if (TLI.isBigEndian()) 541 std::swap(Lo, Hi); 542 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 543 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 544 return; 545 } 546 break; 547 case TargetLowering::TypeSplitVector: 548 // If the input is a vector that needs to be split, convert each split 549 // piece of the input now. 550 GetSplitVector(InOp, Lo, Hi); 551 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 552 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 553 return; 554 } 555 556 // In the general case, convert the input to an integer and split it by hand. 557 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits()); 558 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits()); 559 if (TLI.isBigEndian()) 560 std::swap(LoIntVT, HiIntVT); 561 562 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); 563 564 if (TLI.isBigEndian()) 565 std::swap(Lo, Hi); 566 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 567 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 568} 569 570void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, 571 SDValue &Hi) { 572 EVT LoVT, HiVT; 573 DebugLoc dl = N->getDebugLoc(); 574 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 575 unsigned LoNumElts = LoVT.getVectorNumElements(); 576 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts); 577 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size()); 578 579 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end()); 580 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size()); 581} 582 583void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, 584 SDValue &Hi) { 585 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"); 586 DebugLoc dl = N->getDebugLoc(); 587 unsigned NumSubvectors = N->getNumOperands() / 2; 588 if (NumSubvectors == 1) { 589 Lo = N->getOperand(0); 590 Hi = N->getOperand(1); 591 return; 592 } 593 594 EVT LoVT, HiVT; 595 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 596 597 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); 598 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size()); 599 600 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end()); 601 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size()); 602} 603 604void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, 605 SDValue &Hi) { 606 SDValue Vec = N->getOperand(0); 607 SDValue Idx = N->getOperand(1); 608 DebugLoc dl = N->getDebugLoc(); 609 610 EVT LoVT, HiVT; 611 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 612 613 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); 614 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 615 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, 616 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements())); 617} 618 619void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, 620 SDValue &Hi) { 621 DebugLoc dl = N->getDebugLoc(); 622 GetSplitVector(N->getOperand(0), Lo, Hi); 623 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1)); 624 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1)); 625} 626 627void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo, 628 SDValue &Hi) { 629 SDValue LHSLo, LHSHi; 630 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 631 DebugLoc dl = N->getDebugLoc(); 632 633 EVT LoVT, HiVT; 634 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT); 635 636 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, 637 DAG.getValueType(LoVT)); 638 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, 639 DAG.getValueType(HiVT)); 640} 641 642void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, 643 SDValue &Hi) { 644 SDValue Vec = N->getOperand(0); 645 SDValue Elt = N->getOperand(1); 646 SDValue Idx = N->getOperand(2); 647 DebugLoc dl = N->getDebugLoc(); 648 GetSplitVector(Vec, Lo, Hi); 649 650 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 651 unsigned IdxVal = CIdx->getZExtValue(); 652 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 653 if (IdxVal < LoNumElts) 654 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 655 Lo.getValueType(), Lo, Elt, Idx); 656 else 657 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, 658 DAG.getIntPtrConstant(IdxVal - LoNumElts)); 659 return; 660 } 661 662 // Spill the vector to the stack. 663 EVT VecVT = Vec.getValueType(); 664 EVT EltVT = VecVT.getVectorElementType(); 665 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 666 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 667 MachinePointerInfo(), false, false, 0); 668 669 // Store the new element. This may be larger than the vector element type, 670 // so use a truncating store. 671 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 672 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); 673 unsigned Alignment = 674 TLI.getTargetData()->getPrefTypeAlignment(VecType); 675 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT, 676 false, false, 0); 677 678 // Load the Lo part from the stack slot. 679 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 680 false, false, false, 0); 681 682 // Increment the pointer to the other part. 683 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; 684 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 685 DAG.getIntPtrConstant(IncrementSize)); 686 687 // Load the Hi part from the stack slot. 688 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 689 false, false, false, MinAlign(Alignment, IncrementSize)); 690} 691 692void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, 693 SDValue &Hi) { 694 EVT LoVT, HiVT; 695 DebugLoc dl = N->getDebugLoc(); 696 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 697 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0)); 698 Hi = DAG.getUNDEF(HiVT); 699} 700 701void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, 702 SDValue &Hi) { 703 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"); 704 EVT LoVT, HiVT; 705 DebugLoc dl = LD->getDebugLoc(); 706 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); 707 708 ISD::LoadExtType ExtType = LD->getExtensionType(); 709 SDValue Ch = LD->getChain(); 710 SDValue Ptr = LD->getBasePtr(); 711 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 712 EVT MemoryVT = LD->getMemoryVT(); 713 unsigned Alignment = LD->getOriginalAlignment(); 714 bool isVolatile = LD->isVolatile(); 715 bool isNonTemporal = LD->isNonTemporal(); 716 bool isInvariant = LD->isInvariant(); 717 718 EVT LoMemVT, HiMemVT; 719 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 720 721 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, 722 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal, 723 isInvariant, Alignment); 724 725 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 726 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 727 DAG.getIntPtrConstant(IncrementSize)); 728 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, 729 LD->getPointerInfo().getWithOffset(IncrementSize), 730 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment); 731 732 // Build a factor node to remember that this load is independent of the 733 // other one. 734 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 735 Hi.getValue(1)); 736 737 // Legalized the chain result - switch anything that used the old chain to 738 // use the new one. 739 ReplaceValueWith(SDValue(LD, 1), Ch); 740} 741 742void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) { 743 assert(N->getValueType(0).isVector() && 744 N->getOperand(0).getValueType().isVector() && 745 "Operand types must be vectors"); 746 747 EVT LoVT, HiVT; 748 DebugLoc DL = N->getDebugLoc(); 749 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 750 751 // Split the input. 752 EVT InVT = N->getOperand(0).getValueType(); 753 SDValue LL, LH, RL, RH; 754 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 755 LoVT.getVectorNumElements()); 756 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 757 DAG.getIntPtrConstant(0)); 758 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 759 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 760 761 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 762 DAG.getIntPtrConstant(0)); 763 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 764 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 765 766 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2)); 767 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2)); 768} 769 770void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, 771 SDValue &Hi) { 772 // Get the dest types - they may not match the input types, e.g. int_to_fp. 773 EVT LoVT, HiVT; 774 DebugLoc dl = N->getDebugLoc(); 775 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 776 777 // If the input also splits, handle it directly for a compile time speedup. 778 // Otherwise split it by hand. 779 EVT InVT = N->getOperand(0).getValueType(); 780 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) { 781 GetSplitVector(N->getOperand(0), Lo, Hi); 782 } else { 783 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 784 LoVT.getVectorNumElements()); 785 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 786 DAG.getIntPtrConstant(0)); 787 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 788 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 789 } 790 791 if (N->getOpcode() == ISD::FP_ROUND) { 792 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1)); 793 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1)); 794 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) { 795 SDValue DTyOpLo = DAG.getValueType(LoVT); 796 SDValue DTyOpHi = DAG.getValueType(HiVT); 797 SDValue STyOpLo = DAG.getValueType(Lo.getValueType()); 798 SDValue STyOpHi = DAG.getValueType(Hi.getValueType()); 799 SDValue RndOp = N->getOperand(3); 800 SDValue SatOp = N->getOperand(4); 801 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 802 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp, 803 CvtCode); 804 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp, 805 CvtCode); 806 } else { 807 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo); 808 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi); 809 } 810} 811 812void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, 813 SDValue &Lo, SDValue &Hi) { 814 // The low and high parts of the original input give four input vectors. 815 SDValue Inputs[4]; 816 DebugLoc dl = N->getDebugLoc(); 817 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]); 818 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]); 819 EVT NewVT = Inputs[0].getValueType(); 820 unsigned NewElts = NewVT.getVectorNumElements(); 821 822 // If Lo or Hi uses elements from at most two of the four input vectors, then 823 // express it as a vector shuffle of those two inputs. Otherwise extract the 824 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. 825 SmallVector<int, 16> Ops; 826 for (unsigned High = 0; High < 2; ++High) { 827 SDValue &Output = High ? Hi : Lo; 828 829 // Build a shuffle mask for the output, discovering on the fly which 830 // input vectors to use as shuffle operands (recorded in InputUsed). 831 // If building a suitable shuffle vector proves too hard, then bail 832 // out with useBuildVector set. 833 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered. 834 unsigned FirstMaskIdx = High * NewElts; 835 bool useBuildVector = false; 836 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 837 // The mask element. This indexes into the input. 838 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 839 840 // The input vector this mask element indexes into. 841 unsigned Input = (unsigned)Idx / NewElts; 842 843 if (Input >= array_lengthof(Inputs)) { 844 // The mask element does not index into any input vector. 845 Ops.push_back(-1); 846 continue; 847 } 848 849 // Turn the index into an offset from the start of the input vector. 850 Idx -= Input * NewElts; 851 852 // Find or create a shuffle vector operand to hold this input. 853 unsigned OpNo; 854 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 855 if (InputUsed[OpNo] == Input) { 856 // This input vector is already an operand. 857 break; 858 } else if (InputUsed[OpNo] == -1U) { 859 // Create a new operand for this input vector. 860 InputUsed[OpNo] = Input; 861 break; 862 } 863 } 864 865 if (OpNo >= array_lengthof(InputUsed)) { 866 // More than two input vectors used! Give up on trying to create a 867 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 868 useBuildVector = true; 869 break; 870 } 871 872 // Add the mask index for the new shuffle vector. 873 Ops.push_back(Idx + OpNo * NewElts); 874 } 875 876 if (useBuildVector) { 877 EVT EltVT = NewVT.getVectorElementType(); 878 SmallVector<SDValue, 16> SVOps; 879 880 // Extract the input elements by hand. 881 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 882 // The mask element. This indexes into the input. 883 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 884 885 // The input vector this mask element indexes into. 886 unsigned Input = (unsigned)Idx / NewElts; 887 888 if (Input >= array_lengthof(Inputs)) { 889 // The mask element is "undef" or indexes off the end of the input. 890 SVOps.push_back(DAG.getUNDEF(EltVT)); 891 continue; 892 } 893 894 // Turn the index into an offset from the start of the input vector. 895 Idx -= Input * NewElts; 896 897 // Extract the vector element by hand. 898 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 899 Inputs[Input], DAG.getIntPtrConstant(Idx))); 900 } 901 902 // Construct the Lo/Hi output using a BUILD_VECTOR. 903 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size()); 904 } else if (InputUsed[0] == -1U) { 905 // No input vectors were used! The result is undefined. 906 Output = DAG.getUNDEF(NewVT); 907 } else { 908 SDValue Op0 = Inputs[InputUsed[0]]; 909 // If only one input was used, use an undefined vector for the other. 910 SDValue Op1 = InputUsed[1] == -1U ? 911 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]]; 912 // At least one input vector was used. Create a new shuffle vector. 913 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]); 914 } 915 916 Ops.clear(); 917 } 918} 919 920 921//===----------------------------------------------------------------------===// 922// Operand Vector Splitting 923//===----------------------------------------------------------------------===// 924 925/// SplitVectorOperand - This method is called when the specified operand of the 926/// specified node is found to need vector splitting. At this point, all of the 927/// result types of the node are known to be legal, but other operands of the 928/// node may need legalization as well as the specified one. 929bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { 930 DEBUG(dbgs() << "Split node operand: "; 931 N->dump(&DAG); 932 dbgs() << "\n"); 933 SDValue Res = SDValue(); 934 935 if (Res.getNode() == 0) { 936 switch (N->getOpcode()) { 937 default: 938#ifndef NDEBUG 939 dbgs() << "SplitVectorOperand Op #" << OpNo << ": "; 940 N->dump(&DAG); 941 dbgs() << "\n"; 942#endif 943 llvm_unreachable("Do not know how to split this operator's operand!"); 944 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; 945 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break; 946 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; 947 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; 948 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; 949 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; 950 case ISD::STORE: 951 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo); 952 break; 953 954 case ISD::CTTZ: 955 case ISD::CTLZ: 956 case ISD::CTPOP: 957 case ISD::FP_EXTEND: 958 case ISD::FP_TO_SINT: 959 case ISD::FP_TO_UINT: 960 case ISD::SINT_TO_FP: 961 case ISD::UINT_TO_FP: 962 case ISD::FTRUNC: 963 case ISD::TRUNCATE: 964 case ISD::SIGN_EXTEND: 965 case ISD::ZERO_EXTEND: 966 case ISD::ANY_EXTEND: 967 Res = SplitVecOp_UnaryOp(N); 968 break; 969 } 970 } 971 972 // If the result is null, the sub-method took care of registering results etc. 973 if (!Res.getNode()) return false; 974 975 // If the result is N, the sub-method updated N in place. Tell the legalizer 976 // core about this. 977 if (Res.getNode() == N) 978 return true; 979 980 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 981 "Invalid operand expansion"); 982 983 ReplaceValueWith(SDValue(N, 0), Res); 984 return false; 985} 986 987SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) { 988 // The result has a legal vector type, but the input needs splitting. 989 EVT ResVT = N->getValueType(0); 990 SDValue Lo, Hi; 991 DebugLoc dl = N->getDebugLoc(); 992 GetSplitVector(N->getOperand(0), Lo, Hi); 993 EVT InVT = Lo.getValueType(); 994 995 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 996 InVT.getVectorNumElements()); 997 998 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); 999 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); 1000 1001 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); 1002} 1003 1004SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) { 1005 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will 1006 // end up being split all the way down to individual components. Convert the 1007 // split pieces into integers and reassemble. 1008 SDValue Lo, Hi; 1009 GetSplitVector(N->getOperand(0), Lo, Hi); 1010 Lo = BitConvertToInteger(Lo); 1011 Hi = BitConvertToInteger(Hi); 1012 1013 if (TLI.isBigEndian()) 1014 std::swap(Lo, Hi); 1015 1016 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0), 1017 JoinIntegers(Lo, Hi)); 1018} 1019 1020SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 1021 // We know that the extracted result type is legal. 1022 EVT SubVT = N->getValueType(0); 1023 SDValue Idx = N->getOperand(1); 1024 DebugLoc dl = N->getDebugLoc(); 1025 SDValue Lo, Hi; 1026 GetSplitVector(N->getOperand(0), Lo, Hi); 1027 1028 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1029 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1030 1031 if (IdxVal < LoElts) { 1032 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && 1033 "Extracted subvector crosses vector split!"); 1034 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); 1035 } else { 1036 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, 1037 DAG.getConstant(IdxVal - LoElts, Idx.getValueType())); 1038 } 1039} 1040 1041SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 1042 SDValue Vec = N->getOperand(0); 1043 SDValue Idx = N->getOperand(1); 1044 EVT VecVT = Vec.getValueType(); 1045 1046 if (isa<ConstantSDNode>(Idx)) { 1047 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1048 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); 1049 1050 SDValue Lo, Hi; 1051 GetSplitVector(Vec, Lo, Hi); 1052 1053 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1054 1055 if (IdxVal < LoElts) 1056 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0); 1057 return SDValue(DAG.UpdateNodeOperands(N, Hi, 1058 DAG.getConstant(IdxVal - LoElts, 1059 Idx.getValueType())), 0); 1060 } 1061 1062 // Store the vector to the stack. 1063 EVT EltVT = VecVT.getVectorElementType(); 1064 DebugLoc dl = N->getDebugLoc(); 1065 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 1066 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 1067 MachinePointerInfo(), false, false, 0); 1068 1069 // Load back the required element. 1070 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 1071 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, 1072 MachinePointerInfo(), EltVT, false, false, 0); 1073} 1074 1075SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { 1076 assert(N->isUnindexed() && "Indexed store of vector?"); 1077 assert(OpNo == 1 && "Can only split the stored value"); 1078 DebugLoc DL = N->getDebugLoc(); 1079 1080 bool isTruncating = N->isTruncatingStore(); 1081 SDValue Ch = N->getChain(); 1082 SDValue Ptr = N->getBasePtr(); 1083 EVT MemoryVT = N->getMemoryVT(); 1084 unsigned Alignment = N->getOriginalAlignment(); 1085 bool isVol = N->isVolatile(); 1086 bool isNT = N->isNonTemporal(); 1087 SDValue Lo, Hi; 1088 GetSplitVector(N->getOperand(1), Lo, Hi); 1089 1090 EVT LoMemVT, HiMemVT; 1091 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 1092 1093 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 1094 1095 if (isTruncating) 1096 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1097 LoMemVT, isVol, isNT, Alignment); 1098 else 1099 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1100 isVol, isNT, Alignment); 1101 1102 // Increment the pointer to the other half. 1103 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, 1104 DAG.getIntPtrConstant(IncrementSize)); 1105 1106 if (isTruncating) 1107 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr, 1108 N->getPointerInfo().getWithOffset(IncrementSize), 1109 HiMemVT, isVol, isNT, Alignment); 1110 else 1111 Hi = DAG.getStore(Ch, DL, Hi, Ptr, 1112 N->getPointerInfo().getWithOffset(IncrementSize), 1113 isVol, isNT, Alignment); 1114 1115 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi); 1116} 1117 1118SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) { 1119 DebugLoc DL = N->getDebugLoc(); 1120 1121 // The input operands all must have the same type, and we know the result the 1122 // result type is valid. Convert this to a buildvector which extracts all the 1123 // input elements. 1124 // TODO: If the input elements are power-two vectors, we could convert this to 1125 // a new CONCAT_VECTORS node with elements that are half-wide. 1126 SmallVector<SDValue, 32> Elts; 1127 EVT EltVT = N->getValueType(0).getVectorElementType(); 1128 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1129 SDValue Op = N->getOperand(op); 1130 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements(); 1131 i != e; ++i) { 1132 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, 1133 Op, DAG.getIntPtrConstant(i))); 1134 1135 } 1136 } 1137 1138 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), 1139 &Elts[0], Elts.size()); 1140} 1141 1142SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { 1143 assert(N->getValueType(0).isVector() && 1144 N->getOperand(0).getValueType().isVector() && 1145 "Operand types must be vectors"); 1146 // The result has a legal vector type, but the input needs splitting. 1147 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes; 1148 DebugLoc DL = N->getDebugLoc(); 1149 GetSplitVector(N->getOperand(0), Lo0, Hi0); 1150 GetSplitVector(N->getOperand(1), Lo1, Hi1); 1151 unsigned PartElements = Lo0.getValueType().getVectorNumElements(); 1152 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements); 1153 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements); 1154 1155 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); 1156 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); 1157 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes); 1158 return PromoteTargetBoolean(Con, N->getValueType(0)); 1159} 1160 1161 1162SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) { 1163 // The result has a legal vector type, but the input needs splitting. 1164 EVT ResVT = N->getValueType(0); 1165 SDValue Lo, Hi; 1166 DebugLoc DL = N->getDebugLoc(); 1167 GetSplitVector(N->getOperand(0), Lo, Hi); 1168 EVT InVT = Lo.getValueType(); 1169 1170 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1171 InVT.getVectorNumElements()); 1172 1173 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); 1174 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); 1175 1176 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); 1177} 1178 1179 1180 1181//===----------------------------------------------------------------------===// 1182// Result Vector Widening 1183//===----------------------------------------------------------------------===// 1184 1185void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { 1186 DEBUG(dbgs() << "Widen node result " << ResNo << ": "; 1187 N->dump(&DAG); 1188 dbgs() << "\n"); 1189 1190 // See if the target wants to custom widen this node. 1191 if (CustomWidenLowerNode(N, N->getValueType(ResNo))) 1192 return; 1193 1194 SDValue Res = SDValue(); 1195 switch (N->getOpcode()) { 1196 default: 1197#ifndef NDEBUG 1198 dbgs() << "WidenVectorResult #" << ResNo << ": "; 1199 N->dump(&DAG); 1200 dbgs() << "\n"; 1201#endif 1202 llvm_unreachable("Do not know how to widen the result of this operator!"); 1203 1204 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break; 1205 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break; 1206 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; 1207 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break; 1208 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break; 1209 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; 1210 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break; 1211 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; 1212 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break; 1213 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break; 1214 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break; 1215 case ISD::VSELECT: 1216 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break; 1217 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; 1218 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; 1219 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break; 1220 case ISD::VECTOR_SHUFFLE: 1221 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N)); 1222 break; 1223 case ISD::ADD: 1224 case ISD::AND: 1225 case ISD::BSWAP: 1226 case ISD::FADD: 1227 case ISD::FCOPYSIGN: 1228 case ISD::FDIV: 1229 case ISD::FMUL: 1230 case ISD::FPOW: 1231 case ISD::FREM: 1232 case ISD::FSUB: 1233 case ISD::MUL: 1234 case ISD::MULHS: 1235 case ISD::MULHU: 1236 case ISD::OR: 1237 case ISD::SDIV: 1238 case ISD::SREM: 1239 case ISD::UDIV: 1240 case ISD::UREM: 1241 case ISD::SUB: 1242 case ISD::XOR: 1243 Res = WidenVecRes_Binary(N); 1244 break; 1245 1246 case ISD::FPOWI: 1247 Res = WidenVecRes_POWI(N); 1248 break; 1249 1250 case ISD::SHL: 1251 case ISD::SRA: 1252 case ISD::SRL: 1253 Res = WidenVecRes_Shift(N); 1254 break; 1255 1256 case ISD::ANY_EXTEND: 1257 case ISD::FP_EXTEND: 1258 case ISD::FP_ROUND: 1259 case ISD::FP_TO_SINT: 1260 case ISD::FP_TO_UINT: 1261 case ISD::SIGN_EXTEND: 1262 case ISD::SINT_TO_FP: 1263 case ISD::TRUNCATE: 1264 case ISD::UINT_TO_FP: 1265 case ISD::ZERO_EXTEND: 1266 Res = WidenVecRes_Convert(N); 1267 break; 1268 1269 case ISD::CTLZ: 1270 case ISD::CTPOP: 1271 case ISD::CTTZ: 1272 case ISD::FABS: 1273 case ISD::FCEIL: 1274 case ISD::FCOS: 1275 case ISD::FEXP: 1276 case ISD::FEXP2: 1277 case ISD::FFLOOR: 1278 case ISD::FLOG: 1279 case ISD::FLOG10: 1280 case ISD::FLOG2: 1281 case ISD::FNEARBYINT: 1282 case ISD::FNEG: 1283 case ISD::FRINT: 1284 case ISD::FSIN: 1285 case ISD::FSQRT: 1286 case ISD::FTRUNC: 1287 Res = WidenVecRes_Unary(N); 1288 break; 1289 } 1290 1291 // If Res is null, the sub-method took care of registering the result. 1292 if (Res.getNode()) 1293 SetWidenedVector(SDValue(N, ResNo), Res); 1294} 1295 1296SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) { 1297 // Binary op widening. 1298 unsigned Opcode = N->getOpcode(); 1299 DebugLoc dl = N->getDebugLoc(); 1300 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1301 EVT WidenEltVT = WidenVT.getVectorElementType(); 1302 EVT VT = WidenVT; 1303 unsigned NumElts = VT.getVectorNumElements(); 1304 while (!TLI.isTypeLegal(VT) && NumElts != 1) { 1305 NumElts = NumElts / 2; 1306 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1307 } 1308 1309 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) { 1310 // Operation doesn't trap so just widen as normal. 1311 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1312 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1313 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2); 1314 } 1315 1316 // No legal vector version so unroll the vector operation and then widen. 1317 if (NumElts == 1) 1318 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()); 1319 1320 // Since the operation can trap, apply operation on the original vector. 1321 EVT MaxVT = VT; 1322 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1323 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1324 unsigned CurNumElts = N->getValueType(0).getVectorNumElements(); 1325 1326 SmallVector<SDValue, 16> ConcatOps(CurNumElts); 1327 unsigned ConcatEnd = 0; // Current ConcatOps index. 1328 int Idx = 0; // Current Idx into input vectors. 1329 1330 // NumElts := greatest legal vector size (at most WidenVT) 1331 // while (orig. vector has unhandled elements) { 1332 // take munches of size NumElts from the beginning and add to ConcatOps 1333 // NumElts := next smaller supported vector size or 1 1334 // } 1335 while (CurNumElts != 0) { 1336 while (CurNumElts >= NumElts) { 1337 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, 1338 DAG.getIntPtrConstant(Idx)); 1339 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, 1340 DAG.getIntPtrConstant(Idx)); 1341 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2); 1342 Idx += NumElts; 1343 CurNumElts -= NumElts; 1344 } 1345 do { 1346 NumElts = NumElts / 2; 1347 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1348 } while (!TLI.isTypeLegal(VT) && NumElts != 1); 1349 1350 if (NumElts == 1) { 1351 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) { 1352 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1353 InOp1, DAG.getIntPtrConstant(Idx)); 1354 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1355 InOp2, DAG.getIntPtrConstant(Idx)); 1356 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT, 1357 EOp1, EOp2); 1358 } 1359 CurNumElts = 0; 1360 } 1361 } 1362 1363 // Check to see if we have a single operation with the widen type. 1364 if (ConcatEnd == 1) { 1365 VT = ConcatOps[0].getValueType(); 1366 if (VT == WidenVT) 1367 return ConcatOps[0]; 1368 } 1369 1370 // while (Some element of ConcatOps is not of type MaxVT) { 1371 // From the end of ConcatOps, collect elements of the same type and put 1372 // them into an op of the next larger supported type 1373 // } 1374 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) { 1375 Idx = ConcatEnd - 1; 1376 VT = ConcatOps[Idx--].getValueType(); 1377 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT) 1378 Idx--; 1379 1380 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1; 1381 EVT NextVT; 1382 do { 1383 NextSize *= 2; 1384 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize); 1385 } while (!TLI.isTypeLegal(NextVT)); 1386 1387 if (!VT.isVector()) { 1388 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT 1389 SDValue VecOp = DAG.getUNDEF(NextVT); 1390 unsigned NumToInsert = ConcatEnd - Idx - 1; 1391 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) { 1392 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, 1393 ConcatOps[OpIdx], DAG.getIntPtrConstant(i)); 1394 } 1395 ConcatOps[Idx+1] = VecOp; 1396 ConcatEnd = Idx + 2; 1397 } else { 1398 // Vector type, create a CONCAT_VECTORS of type NextVT 1399 SDValue undefVec = DAG.getUNDEF(VT); 1400 unsigned OpsToConcat = NextSize/VT.getVectorNumElements(); 1401 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat); 1402 unsigned RealVals = ConcatEnd - Idx - 1; 1403 unsigned SubConcatEnd = 0; 1404 unsigned SubConcatIdx = Idx + 1; 1405 while (SubConcatEnd < RealVals) 1406 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx]; 1407 while (SubConcatEnd < OpsToConcat) 1408 SubConcatOps[SubConcatEnd++] = undefVec; 1409 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1410 NextVT, &SubConcatOps[0], 1411 OpsToConcat); 1412 ConcatEnd = SubConcatIdx + 1; 1413 } 1414 } 1415 1416 // Check to see if we have a single operation with the widen type. 1417 if (ConcatEnd == 1) { 1418 VT = ConcatOps[0].getValueType(); 1419 if (VT == WidenVT) 1420 return ConcatOps[0]; 1421 } 1422 1423 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT 1424 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements(); 1425 if (NumOps != ConcatEnd ) { 1426 SDValue UndefVal = DAG.getUNDEF(MaxVT); 1427 for (unsigned j = ConcatEnd; j < NumOps; ++j) 1428 ConcatOps[j] = UndefVal; 1429 } 1430 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps); 1431} 1432 1433SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { 1434 SDValue InOp = N->getOperand(0); 1435 DebugLoc DL = N->getDebugLoc(); 1436 1437 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1438 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1439 1440 EVT InVT = InOp.getValueType(); 1441 EVT InEltVT = InVT.getVectorElementType(); 1442 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1443 1444 unsigned Opcode = N->getOpcode(); 1445 unsigned InVTNumElts = InVT.getVectorNumElements(); 1446 1447 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1448 InOp = GetWidenedVector(N->getOperand(0)); 1449 InVT = InOp.getValueType(); 1450 InVTNumElts = InVT.getVectorNumElements(); 1451 if (InVTNumElts == WidenNumElts) { 1452 if (N->getNumOperands() == 1) 1453 return DAG.getNode(Opcode, DL, WidenVT, InOp); 1454 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1)); 1455 } 1456 } 1457 1458 if (TLI.isTypeLegal(InWidenVT)) { 1459 // Because the result and the input are different vector types, widening 1460 // the result could create a legal type but widening the input might make 1461 // it an illegal type that might lead to repeatedly splitting the input 1462 // and then widening it. To avoid this, we widen the input only if 1463 // it results in a legal type. 1464 if (WidenNumElts % InVTNumElts == 0) { 1465 // Widen the input and call convert on the widened input vector. 1466 unsigned NumConcat = WidenNumElts/InVTNumElts; 1467 SmallVector<SDValue, 16> Ops(NumConcat); 1468 Ops[0] = InOp; 1469 SDValue UndefVal = DAG.getUNDEF(InVT); 1470 for (unsigned i = 1; i != NumConcat; ++i) 1471 Ops[i] = UndefVal; 1472 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, 1473 &Ops[0], NumConcat); 1474 if (N->getNumOperands() == 1) 1475 return DAG.getNode(Opcode, DL, WidenVT, InVec); 1476 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1)); 1477 } 1478 1479 if (InVTNumElts % WidenNumElts == 0) { 1480 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, 1481 InOp, DAG.getIntPtrConstant(0)); 1482 // Extract the input and convert the shorten input vector. 1483 if (N->getNumOperands() == 1) 1484 return DAG.getNode(Opcode, DL, WidenVT, InVal); 1485 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1)); 1486 } 1487 } 1488 1489 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1490 SmallVector<SDValue, 16> Ops(WidenNumElts); 1491 EVT EltVT = WidenVT.getVectorElementType(); 1492 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1493 unsigned i; 1494 for (i=0; i < MinElts; ++i) { 1495 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp, 1496 DAG.getIntPtrConstant(i)); 1497 if (N->getNumOperands() == 1) 1498 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val); 1499 else 1500 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1)); 1501 } 1502 1503 SDValue UndefVal = DAG.getUNDEF(EltVT); 1504 for (; i < WidenNumElts; ++i) 1505 Ops[i] = UndefVal; 1506 1507 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts); 1508} 1509 1510SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) { 1511 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1512 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1513 SDValue ShOp = N->getOperand(1); 1514 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1515} 1516 1517SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) { 1518 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1519 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1520 SDValue ShOp = N->getOperand(1); 1521 1522 EVT ShVT = ShOp.getValueType(); 1523 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) { 1524 ShOp = GetWidenedVector(ShOp); 1525 ShVT = ShOp.getValueType(); 1526 } 1527 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(), 1528 ShVT.getVectorElementType(), 1529 WidenVT.getVectorNumElements()); 1530 if (ShVT != ShWidenVT) 1531 ShOp = ModifyToType(ShOp, ShWidenVT); 1532 1533 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1534} 1535 1536SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) { 1537 // Unary op widening. 1538 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1539 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1540 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp); 1541} 1542 1543SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) { 1544 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1545 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), 1546 cast<VTSDNode>(N->getOperand(1))->getVT() 1547 .getVectorElementType(), 1548 WidenVT.getVectorNumElements()); 1549 SDValue WidenLHS = GetWidenedVector(N->getOperand(0)); 1550 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 1551 WidenVT, WidenLHS, DAG.getValueType(ExtVT)); 1552} 1553 1554SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) { 1555 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo); 1556 return GetWidenedVector(WidenVec); 1557} 1558 1559SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) { 1560 SDValue InOp = N->getOperand(0); 1561 EVT InVT = InOp.getValueType(); 1562 EVT VT = N->getValueType(0); 1563 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1564 DebugLoc dl = N->getDebugLoc(); 1565 1566 switch (getTypeAction(InVT)) { 1567 default: 1568 assert(false && "Unknown type action!"); 1569 break; 1570 case TargetLowering::TypeLegal: 1571 break; 1572 case TargetLowering::TypePromoteInteger: 1573 // If the InOp is promoted to the same size, convert it. Otherwise, 1574 // fall out of the switch and widen the promoted input. 1575 InOp = GetPromotedInteger(InOp); 1576 InVT = InOp.getValueType(); 1577 if (WidenVT.bitsEq(InVT)) 1578 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1579 break; 1580 case TargetLowering::TypeSoftenFloat: 1581 case TargetLowering::TypeExpandInteger: 1582 case TargetLowering::TypeExpandFloat: 1583 case TargetLowering::TypeScalarizeVector: 1584 case TargetLowering::TypeSplitVector: 1585 break; 1586 case TargetLowering::TypeWidenVector: 1587 // If the InOp is widened to the same size, convert it. Otherwise, fall 1588 // out of the switch and widen the widened input. 1589 InOp = GetWidenedVector(InOp); 1590 InVT = InOp.getValueType(); 1591 if (WidenVT.bitsEq(InVT)) 1592 // The input widens to the same size. Convert to the widen value. 1593 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1594 break; 1595 } 1596 1597 unsigned WidenSize = WidenVT.getSizeInBits(); 1598 unsigned InSize = InVT.getSizeInBits(); 1599 // x86mmx is not an acceptable vector element type, so don't try. 1600 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) { 1601 // Determine new input vector type. The new input vector type will use 1602 // the same element type (if its a vector) or use the input type as a 1603 // vector. It is the same size as the type to widen to. 1604 EVT NewInVT; 1605 unsigned NewNumElts = WidenSize / InSize; 1606 if (InVT.isVector()) { 1607 EVT InEltVT = InVT.getVectorElementType(); 1608 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, 1609 WidenSize / InEltVT.getSizeInBits()); 1610 } else { 1611 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts); 1612 } 1613 1614 if (TLI.isTypeLegal(NewInVT)) { 1615 // Because the result and the input are different vector types, widening 1616 // the result could create a legal type but widening the input might make 1617 // it an illegal type that might lead to repeatedly splitting the input 1618 // and then widening it. To avoid this, we widen the input only if 1619 // it results in a legal type. 1620 SmallVector<SDValue, 16> Ops(NewNumElts); 1621 SDValue UndefVal = DAG.getUNDEF(InVT); 1622 Ops[0] = InOp; 1623 for (unsigned i = 1; i < NewNumElts; ++i) 1624 Ops[i] = UndefVal; 1625 1626 SDValue NewVec; 1627 if (InVT.isVector()) 1628 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1629 NewInVT, &Ops[0], NewNumElts); 1630 else 1631 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, 1632 NewInVT, &Ops[0], NewNumElts); 1633 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec); 1634 } 1635 } 1636 1637 return CreateStackStoreLoad(InOp, WidenVT); 1638} 1639 1640SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) { 1641 DebugLoc dl = N->getDebugLoc(); 1642 // Build a vector with undefined for the new nodes. 1643 EVT VT = N->getValueType(0); 1644 EVT EltVT = VT.getVectorElementType(); 1645 unsigned NumElts = VT.getVectorNumElements(); 1646 1647 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1648 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1649 1650 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end()); 1651 NewOps.reserve(WidenNumElts); 1652 for (unsigned i = NumElts; i < WidenNumElts; ++i) 1653 NewOps.push_back(DAG.getUNDEF(EltVT)); 1654 1655 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size()); 1656} 1657 1658SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) { 1659 EVT InVT = N->getOperand(0).getValueType(); 1660 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1661 DebugLoc dl = N->getDebugLoc(); 1662 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1663 unsigned NumInElts = InVT.getVectorNumElements(); 1664 unsigned NumOperands = N->getNumOperands(); 1665 1666 bool InputWidened = false; // Indicates we need to widen the input. 1667 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) { 1668 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) { 1669 // Add undef vectors to widen to correct length. 1670 unsigned NumConcat = WidenVT.getVectorNumElements() / 1671 InVT.getVectorNumElements(); 1672 SDValue UndefVal = DAG.getUNDEF(InVT); 1673 SmallVector<SDValue, 16> Ops(NumConcat); 1674 for (unsigned i=0; i < NumOperands; ++i) 1675 Ops[i] = N->getOperand(i); 1676 for (unsigned i = NumOperands; i != NumConcat; ++i) 1677 Ops[i] = UndefVal; 1678 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat); 1679 } 1680 } else { 1681 InputWidened = true; 1682 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) { 1683 // The inputs and the result are widen to the same value. 1684 unsigned i; 1685 for (i=1; i < NumOperands; ++i) 1686 if (N->getOperand(i).getOpcode() != ISD::UNDEF) 1687 break; 1688 1689 if (i == NumOperands) 1690 // Everything but the first operand is an UNDEF so just return the 1691 // widened first operand. 1692 return GetWidenedVector(N->getOperand(0)); 1693 1694 if (NumOperands == 2) { 1695 // Replace concat of two operands with a shuffle. 1696 SmallVector<int, 16> MaskOps(WidenNumElts, -1); 1697 for (unsigned i = 0; i < NumInElts; ++i) { 1698 MaskOps[i] = i; 1699 MaskOps[i + NumInElts] = i + WidenNumElts; 1700 } 1701 return DAG.getVectorShuffle(WidenVT, dl, 1702 GetWidenedVector(N->getOperand(0)), 1703 GetWidenedVector(N->getOperand(1)), 1704 &MaskOps[0]); 1705 } 1706 } 1707 } 1708 1709 // Fall back to use extracts and build vector. 1710 EVT EltVT = WidenVT.getVectorElementType(); 1711 SmallVector<SDValue, 16> Ops(WidenNumElts); 1712 unsigned Idx = 0; 1713 for (unsigned i=0; i < NumOperands; ++i) { 1714 SDValue InOp = N->getOperand(i); 1715 if (InputWidened) 1716 InOp = GetWidenedVector(InOp); 1717 for (unsigned j=0; j < NumInElts; ++j) 1718 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1719 DAG.getIntPtrConstant(j)); 1720 } 1721 SDValue UndefVal = DAG.getUNDEF(EltVT); 1722 for (; Idx < WidenNumElts; ++Idx) 1723 Ops[Idx] = UndefVal; 1724 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1725} 1726 1727SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { 1728 DebugLoc dl = N->getDebugLoc(); 1729 SDValue InOp = N->getOperand(0); 1730 SDValue RndOp = N->getOperand(3); 1731 SDValue SatOp = N->getOperand(4); 1732 1733 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1734 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1735 1736 EVT InVT = InOp.getValueType(); 1737 EVT InEltVT = InVT.getVectorElementType(); 1738 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1739 1740 SDValue DTyOp = DAG.getValueType(WidenVT); 1741 SDValue STyOp = DAG.getValueType(InWidenVT); 1742 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 1743 1744 unsigned InVTNumElts = InVT.getVectorNumElements(); 1745 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1746 InOp = GetWidenedVector(InOp); 1747 InVT = InOp.getValueType(); 1748 InVTNumElts = InVT.getVectorNumElements(); 1749 if (InVTNumElts == WidenNumElts) 1750 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1751 SatOp, CvtCode); 1752 } 1753 1754 if (TLI.isTypeLegal(InWidenVT)) { 1755 // Because the result and the input are different vector types, widening 1756 // the result could create a legal type but widening the input might make 1757 // it an illegal type that might lead to repeatedly splitting the input 1758 // and then widening it. To avoid this, we widen the input only if 1759 // it results in a legal type. 1760 if (WidenNumElts % InVTNumElts == 0) { 1761 // Widen the input and call convert on the widened input vector. 1762 unsigned NumConcat = WidenNumElts/InVTNumElts; 1763 SmallVector<SDValue, 16> Ops(NumConcat); 1764 Ops[0] = InOp; 1765 SDValue UndefVal = DAG.getUNDEF(InVT); 1766 for (unsigned i = 1; i != NumConcat; ++i) 1767 Ops[i] = UndefVal; 1768 1769 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat); 1770 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1771 SatOp, CvtCode); 1772 } 1773 1774 if (InVTNumElts % WidenNumElts == 0) { 1775 // Extract the input and convert the shorten input vector. 1776 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp, 1777 DAG.getIntPtrConstant(0)); 1778 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1779 SatOp, CvtCode); 1780 } 1781 } 1782 1783 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1784 SmallVector<SDValue, 16> Ops(WidenNumElts); 1785 EVT EltVT = WidenVT.getVectorElementType(); 1786 DTyOp = DAG.getValueType(EltVT); 1787 STyOp = DAG.getValueType(InEltVT); 1788 1789 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1790 unsigned i; 1791 for (i=0; i < MinElts; ++i) { 1792 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 1793 DAG.getIntPtrConstant(i)); 1794 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp, 1795 SatOp, CvtCode); 1796 } 1797 1798 SDValue UndefVal = DAG.getUNDEF(EltVT); 1799 for (; i < WidenNumElts; ++i) 1800 Ops[i] = UndefVal; 1801 1802 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1803} 1804 1805SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 1806 EVT VT = N->getValueType(0); 1807 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1808 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1809 SDValue InOp = N->getOperand(0); 1810 SDValue Idx = N->getOperand(1); 1811 DebugLoc dl = N->getDebugLoc(); 1812 1813 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 1814 InOp = GetWidenedVector(InOp); 1815 1816 EVT InVT = InOp.getValueType(); 1817 1818 // Check if we can just return the input vector after widening. 1819 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1820 if (IdxVal == 0 && InVT == WidenVT) 1821 return InOp; 1822 1823 // Check if we can extract from the vector. 1824 unsigned InNumElts = InVT.getVectorNumElements(); 1825 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts) 1826 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx); 1827 1828 // We could try widening the input to the right length but for now, extract 1829 // the original elements, fill the rest with undefs and build a vector. 1830 SmallVector<SDValue, 16> Ops(WidenNumElts); 1831 EVT EltVT = VT.getVectorElementType(); 1832 unsigned NumElts = VT.getVectorNumElements(); 1833 unsigned i; 1834 for (i=0; i < NumElts; ++i) 1835 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1836 DAG.getIntPtrConstant(IdxVal+i)); 1837 1838 SDValue UndefVal = DAG.getUNDEF(EltVT); 1839 for (; i < WidenNumElts; ++i) 1840 Ops[i] = UndefVal; 1841 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1842} 1843 1844SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) { 1845 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1846 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(), 1847 InOp.getValueType(), InOp, 1848 N->getOperand(1), N->getOperand(2)); 1849} 1850 1851SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) { 1852 LoadSDNode *LD = cast<LoadSDNode>(N); 1853 ISD::LoadExtType ExtType = LD->getExtensionType(); 1854 1855 SDValue Result; 1856 SmallVector<SDValue, 16> LdChain; // Chain for the series of load 1857 if (ExtType != ISD::NON_EXTLOAD) 1858 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); 1859 else 1860 Result = GenWidenVectorLoads(LdChain, LD); 1861 1862 // If we generate a single load, we can use that for the chain. Otherwise, 1863 // build a factor node to remember the multiple loads are independent and 1864 // chain to that. 1865 SDValue NewChain; 1866 if (LdChain.size() == 1) 1867 NewChain = LdChain[0]; 1868 else 1869 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other, 1870 &LdChain[0], LdChain.size()); 1871 1872 // Modified the chain - switch anything that used the old chain to use 1873 // the new one. 1874 ReplaceValueWith(SDValue(N, 1), NewChain); 1875 1876 return Result; 1877} 1878 1879SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) { 1880 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1881 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(), 1882 WidenVT, N->getOperand(0)); 1883} 1884 1885SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) { 1886 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1887 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1888 1889 SDValue Cond1 = N->getOperand(0); 1890 EVT CondVT = Cond1.getValueType(); 1891 if (CondVT.isVector()) { 1892 EVT CondEltVT = CondVT.getVectorElementType(); 1893 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), 1894 CondEltVT, WidenNumElts); 1895 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector) 1896 Cond1 = GetWidenedVector(Cond1); 1897 1898 if (Cond1.getValueType() != CondWidenVT) 1899 Cond1 = ModifyToType(Cond1, CondWidenVT); 1900 } 1901 1902 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 1903 SDValue InOp2 = GetWidenedVector(N->getOperand(2)); 1904 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT); 1905 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 1906 WidenVT, Cond1, InOp1, InOp2); 1907} 1908 1909SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) { 1910 SDValue InOp1 = GetWidenedVector(N->getOperand(2)); 1911 SDValue InOp2 = GetWidenedVector(N->getOperand(3)); 1912 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 1913 InOp1.getValueType(), N->getOperand(0), 1914 N->getOperand(1), InOp1, InOp2, N->getOperand(4)); 1915} 1916 1917SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) { 1918 assert(N->getValueType(0).isVector() == 1919 N->getOperand(0).getValueType().isVector() && 1920 "Scalar/Vector type mismatch"); 1921 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N); 1922 1923 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1924 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1925 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1926 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT, 1927 InOp1, InOp2, N->getOperand(2)); 1928} 1929 1930SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) { 1931 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1932 return DAG.getUNDEF(WidenVT); 1933} 1934 1935SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) { 1936 EVT VT = N->getValueType(0); 1937 DebugLoc dl = N->getDebugLoc(); 1938 1939 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1940 unsigned NumElts = VT.getVectorNumElements(); 1941 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1942 1943 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1944 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1945 1946 // Adjust mask based on new input vector length. 1947 SmallVector<int, 16> NewMask; 1948 for (unsigned i = 0; i != NumElts; ++i) { 1949 int Idx = N->getMaskElt(i); 1950 if (Idx < (int)NumElts) 1951 NewMask.push_back(Idx); 1952 else 1953 NewMask.push_back(Idx - NumElts + WidenNumElts); 1954 } 1955 for (unsigned i = NumElts; i != WidenNumElts; ++i) 1956 NewMask.push_back(-1); 1957 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]); 1958} 1959 1960SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) { 1961 assert(N->getValueType(0).isVector() && 1962 N->getOperand(0).getValueType().isVector() && 1963 "Operands must be vectors"); 1964 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1965 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1966 1967 SDValue InOp1 = N->getOperand(0); 1968 EVT InVT = InOp1.getValueType(); 1969 assert(InVT.isVector() && "can not widen non vector type"); 1970 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(), 1971 InVT.getVectorElementType(), WidenNumElts); 1972 InOp1 = GetWidenedVector(InOp1); 1973 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1974 1975 // Assume that the input and output will be widen appropriately. If not, 1976 // we will have to unroll it at some point. 1977 assert(InOp1.getValueType() == WidenInVT && 1978 InOp2.getValueType() == WidenInVT && 1979 "Input not widened to expected type!"); 1980 (void)WidenInVT; 1981 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), 1982 WidenVT, InOp1, InOp2, N->getOperand(2)); 1983} 1984 1985 1986//===----------------------------------------------------------------------===// 1987// Widen Vector Operand 1988//===----------------------------------------------------------------------===// 1989bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) { 1990 DEBUG(dbgs() << "Widen node operand " << ResNo << ": "; 1991 N->dump(&DAG); 1992 dbgs() << "\n"); 1993 SDValue Res = SDValue(); 1994 1995 switch (N->getOpcode()) { 1996 default: 1997#ifndef NDEBUG 1998 dbgs() << "WidenVectorOperand op #" << ResNo << ": "; 1999 N->dump(&DAG); 2000 dbgs() << "\n"; 2001#endif 2002 llvm_unreachable("Do not know how to widen this operator's operand!"); 2003 2004 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break; 2005 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break; 2006 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break; 2007 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break; 2008 case ISD::STORE: Res = WidenVecOp_STORE(N); break; 2009 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break; 2010 2011 case ISD::FP_EXTEND: 2012 case ISD::FP_TO_SINT: 2013 case ISD::FP_TO_UINT: 2014 case ISD::SINT_TO_FP: 2015 case ISD::UINT_TO_FP: 2016 case ISD::TRUNCATE: 2017 case ISD::SIGN_EXTEND: 2018 case ISD::ZERO_EXTEND: 2019 case ISD::ANY_EXTEND: 2020 Res = WidenVecOp_Convert(N); 2021 break; 2022 } 2023 2024 // If Res is null, the sub-method took care of registering the result. 2025 if (!Res.getNode()) return false; 2026 2027 // If the result is N, the sub-method updated N in place. Tell the legalizer 2028 // core about this. 2029 if (Res.getNode() == N) 2030 return true; 2031 2032 2033 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2034 "Invalid operand expansion"); 2035 2036 ReplaceValueWith(SDValue(N, 0), Res); 2037 return false; 2038} 2039 2040SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) { 2041 // Since the result is legal and the input is illegal, it is unlikely 2042 // that we can fix the input to a legal type so unroll the convert 2043 // into some scalar code and create a nasty build vector. 2044 EVT VT = N->getValueType(0); 2045 EVT EltVT = VT.getVectorElementType(); 2046 DebugLoc dl = N->getDebugLoc(); 2047 unsigned NumElts = VT.getVectorNumElements(); 2048 SDValue InOp = N->getOperand(0); 2049 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2050 InOp = GetWidenedVector(InOp); 2051 EVT InVT = InOp.getValueType(); 2052 EVT InEltVT = InVT.getVectorElementType(); 2053 2054 unsigned Opcode = N->getOpcode(); 2055 SmallVector<SDValue, 16> Ops(NumElts); 2056 for (unsigned i=0; i < NumElts; ++i) 2057 Ops[i] = DAG.getNode(Opcode, dl, EltVT, 2058 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 2059 DAG.getIntPtrConstant(i))); 2060 2061 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2062} 2063 2064SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) { 2065 EVT VT = N->getValueType(0); 2066 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2067 EVT InWidenVT = InOp.getValueType(); 2068 DebugLoc dl = N->getDebugLoc(); 2069 2070 // Check if we can convert between two legal vector types and extract. 2071 unsigned InWidenSize = InWidenVT.getSizeInBits(); 2072 unsigned Size = VT.getSizeInBits(); 2073 // x86mmx is not an acceptable vector element type, so don't try. 2074 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) { 2075 unsigned NewNumElts = InWidenSize / Size; 2076 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); 2077 if (TLI.isTypeLegal(NewVT)) { 2078 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp); 2079 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, 2080 DAG.getIntPtrConstant(0)); 2081 } 2082 } 2083 2084 return CreateStackStoreLoad(InOp, VT); 2085} 2086 2087SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) { 2088 // If the input vector is not legal, it is likely that we will not find a 2089 // legal vector of the same size. Replace the concatenate vector with a 2090 // nasty build vector. 2091 EVT VT = N->getValueType(0); 2092 EVT EltVT = VT.getVectorElementType(); 2093 DebugLoc dl = N->getDebugLoc(); 2094 unsigned NumElts = VT.getVectorNumElements(); 2095 SmallVector<SDValue, 16> Ops(NumElts); 2096 2097 EVT InVT = N->getOperand(0).getValueType(); 2098 unsigned NumInElts = InVT.getVectorNumElements(); 2099 2100 unsigned Idx = 0; 2101 unsigned NumOperands = N->getNumOperands(); 2102 for (unsigned i=0; i < NumOperands; ++i) { 2103 SDValue InOp = N->getOperand(i); 2104 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2105 InOp = GetWidenedVector(InOp); 2106 for (unsigned j=0; j < NumInElts; ++j) 2107 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2108 DAG.getIntPtrConstant(j)); 2109 } 2110 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2111} 2112 2113SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 2114 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2115 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), 2116 N->getValueType(0), InOp, N->getOperand(1)); 2117} 2118 2119SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 2120 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2121 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 2122 N->getValueType(0), InOp, N->getOperand(1)); 2123} 2124 2125SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) { 2126 // We have to widen the value but we want only to store the original 2127 // vector type. 2128 StoreSDNode *ST = cast<StoreSDNode>(N); 2129 2130 SmallVector<SDValue, 16> StChain; 2131 if (ST->isTruncatingStore()) 2132 GenWidenVectorTruncStores(StChain, ST); 2133 else 2134 GenWidenVectorStores(StChain, ST); 2135 2136 if (StChain.size() == 1) 2137 return StChain[0]; 2138 else 2139 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(), 2140 MVT::Other,&StChain[0],StChain.size()); 2141} 2142 2143SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) { 2144 SDValue InOp0 = GetWidenedVector(N->getOperand(0)); 2145 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 2146 DebugLoc dl = N->getDebugLoc(); 2147 2148 // WARNING: In this code we widen the compare instruction with garbage. 2149 // This garbage may contain denormal floats which may be slow. Is this a real 2150 // concern ? Should we zero the unused lanes if this is a float compare ? 2151 2152 // Get a new SETCC node to compare the newly widened operands. 2153 // Only some of the compared elements are legal. 2154 EVT SVT = TLI.getSetCCResultType(InOp0.getValueType()); 2155 SDValue WideSETCC = DAG.getNode(ISD::SETCC, N->getDebugLoc(), 2156 SVT, InOp0, InOp1, N->getOperand(2)); 2157 2158 // Extract the needed results from the result vector. 2159 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), 2160 SVT.getVectorElementType(), 2161 N->getValueType(0).getVectorNumElements()); 2162 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, 2163 ResVT, WideSETCC, DAG.getIntPtrConstant(0)); 2164 2165 return PromoteTargetBoolean(CC, N->getValueType(0)); 2166} 2167 2168 2169//===----------------------------------------------------------------------===// 2170// Vector Widening Utilities 2171//===----------------------------------------------------------------------===// 2172 2173// Utility function to find the type to chop up a widen vector for load/store 2174// TLI: Target lowering used to determine legal types. 2175// Width: Width left need to load/store. 2176// WidenVT: The widen vector type to load to/store from 2177// Align: If 0, don't allow use of a wider type 2178// WidenEx: If Align is not 0, the amount additional we can load/store from. 2179 2180static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, 2181 unsigned Width, EVT WidenVT, 2182 unsigned Align = 0, unsigned WidenEx = 0) { 2183 EVT WidenEltVT = WidenVT.getVectorElementType(); 2184 unsigned WidenWidth = WidenVT.getSizeInBits(); 2185 unsigned WidenEltWidth = WidenEltVT.getSizeInBits(); 2186 unsigned AlignInBits = Align*8; 2187 2188 // If we have one element to load/store, return it. 2189 EVT RetVT = WidenEltVT; 2190 if (Width == WidenEltWidth) 2191 return RetVT; 2192 2193 // See if there is larger legal integer than the element type to load/store 2194 unsigned VT; 2195 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE; 2196 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) { 2197 EVT MemVT((MVT::SimpleValueType) VT); 2198 unsigned MemVTWidth = MemVT.getSizeInBits(); 2199 if (MemVT.getSizeInBits() <= WidenEltWidth) 2200 break; 2201 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 && 2202 isPowerOf2_32(WidenWidth / MemVTWidth) && 2203 (MemVTWidth <= Width || 2204 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2205 RetVT = MemVT; 2206 break; 2207 } 2208 } 2209 2210 // See if there is a larger vector type to load/store that has the same vector 2211 // element type and is evenly divisible with the WidenVT. 2212 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; 2213 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) { 2214 EVT MemVT = (MVT::SimpleValueType) VT; 2215 unsigned MemVTWidth = MemVT.getSizeInBits(); 2216 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() && 2217 (WidenWidth % MemVTWidth) == 0 && 2218 isPowerOf2_32(WidenWidth / MemVTWidth) && 2219 (MemVTWidth <= Width || 2220 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2221 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT) 2222 return MemVT; 2223 } 2224 } 2225 2226 return RetVT; 2227} 2228 2229// Builds a vector type from scalar loads 2230// VecTy: Resulting Vector type 2231// LDOps: Load operators to build a vector type 2232// [Start,End) the list of loads to use. 2233static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, 2234 SmallVector<SDValue, 16>& LdOps, 2235 unsigned Start, unsigned End) { 2236 DebugLoc dl = LdOps[Start].getDebugLoc(); 2237 EVT LdTy = LdOps[Start].getValueType(); 2238 unsigned Width = VecTy.getSizeInBits(); 2239 unsigned NumElts = Width / LdTy.getSizeInBits(); 2240 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts); 2241 2242 unsigned Idx = 1; 2243 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]); 2244 2245 for (unsigned i = Start + 1; i != End; ++i) { 2246 EVT NewLdTy = LdOps[i].getValueType(); 2247 if (NewLdTy != LdTy) { 2248 NumElts = Width / NewLdTy.getSizeInBits(); 2249 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts); 2250 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp); 2251 // Readjust position and vector position based on new load type 2252 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits(); 2253 LdTy = NewLdTy; 2254 } 2255 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], 2256 DAG.getIntPtrConstant(Idx++)); 2257 } 2258 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp); 2259} 2260 2261SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain, 2262 LoadSDNode *LD) { 2263 // The strategy assumes that we can efficiently load powers of two widths. 2264 // The routines chops the vector into the largest vector loads with the same 2265 // element type or scalar loads and then recombines it to the widen vector 2266 // type. 2267 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2268 unsigned WidenWidth = WidenVT.getSizeInBits(); 2269 EVT LdVT = LD->getMemoryVT(); 2270 DebugLoc dl = LD->getDebugLoc(); 2271 assert(LdVT.isVector() && WidenVT.isVector()); 2272 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType()); 2273 2274 // Load information 2275 SDValue Chain = LD->getChain(); 2276 SDValue BasePtr = LD->getBasePtr(); 2277 unsigned Align = LD->getAlignment(); 2278 bool isVolatile = LD->isVolatile(); 2279 bool isNonTemporal = LD->isNonTemporal(); 2280 bool isInvariant = LD->isInvariant(); 2281 2282 int LdWidth = LdVT.getSizeInBits(); 2283 int WidthDiff = WidenWidth - LdWidth; // Difference 2284 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads 2285 2286 // Find the vector type that can load from. 2287 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2288 int NewVTWidth = NewVT.getSizeInBits(); 2289 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(), 2290 isVolatile, isNonTemporal, isInvariant, Align); 2291 LdChain.push_back(LdOp.getValue(1)); 2292 2293 // Check if we can load the element with one instruction 2294 if (LdWidth <= NewVTWidth) { 2295 if (!NewVT.isVector()) { 2296 unsigned NumElts = WidenWidth / NewVTWidth; 2297 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2298 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp); 2299 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp); 2300 } 2301 if (NewVT == WidenVT) 2302 return LdOp; 2303 2304 assert(WidenWidth % NewVTWidth == 0); 2305 unsigned NumConcat = WidenWidth / NewVTWidth; 2306 SmallVector<SDValue, 16> ConcatOps(NumConcat); 2307 SDValue UndefVal = DAG.getUNDEF(NewVT); 2308 ConcatOps[0] = LdOp; 2309 for (unsigned i = 1; i != NumConcat; ++i) 2310 ConcatOps[i] = UndefVal; 2311 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], 2312 NumConcat); 2313 } 2314 2315 // Load vector by using multiple loads from largest vector to scalar 2316 SmallVector<SDValue, 16> LdOps; 2317 LdOps.push_back(LdOp); 2318 2319 LdWidth -= NewVTWidth; 2320 unsigned Offset = 0; 2321 2322 while (LdWidth > 0) { 2323 unsigned Increment = NewVTWidth / 8; 2324 Offset += Increment; 2325 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2326 DAG.getIntPtrConstant(Increment)); 2327 2328 if (LdWidth < NewVTWidth) { 2329 // Our current type we are using is too large, find a better size 2330 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2331 NewVTWidth = NewVT.getSizeInBits(); 2332 } 2333 2334 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, 2335 LD->getPointerInfo().getWithOffset(Offset), 2336 isVolatile, 2337 isNonTemporal, isInvariant, 2338 MinAlign(Align, Increment)); 2339 LdChain.push_back(LdOp.getValue(1)); 2340 LdOps.push_back(LdOp); 2341 2342 LdWidth -= NewVTWidth; 2343 } 2344 2345 // Build the vector from the loads operations 2346 unsigned End = LdOps.size(); 2347 if (!LdOps[0].getValueType().isVector()) 2348 // All the loads are scalar loads. 2349 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End); 2350 2351 // If the load contains vectors, build the vector using concat vector. 2352 // All of the vectors used to loads are power of 2 and the scalars load 2353 // can be combined to make a power of 2 vector. 2354 SmallVector<SDValue, 16> ConcatOps(End); 2355 int i = End - 1; 2356 int Idx = End; 2357 EVT LdTy = LdOps[i].getValueType(); 2358 // First combine the scalar loads to a vector 2359 if (!LdTy.isVector()) { 2360 for (--i; i >= 0; --i) { 2361 LdTy = LdOps[i].getValueType(); 2362 if (LdTy.isVector()) 2363 break; 2364 } 2365 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End); 2366 } 2367 ConcatOps[--Idx] = LdOps[i]; 2368 for (--i; i >= 0; --i) { 2369 EVT NewLdTy = LdOps[i].getValueType(); 2370 if (NewLdTy != LdTy) { 2371 // Create a larger vector 2372 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy, 2373 &ConcatOps[Idx], End - Idx); 2374 Idx = End - 1; 2375 LdTy = NewLdTy; 2376 } 2377 ConcatOps[--Idx] = LdOps[i]; 2378 } 2379 2380 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx)) 2381 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, 2382 &ConcatOps[Idx], End - Idx); 2383 2384 // We need to fill the rest with undefs to build the vector 2385 unsigned NumOps = WidenWidth / LdTy.getSizeInBits(); 2386 SmallVector<SDValue, 16> WidenOps(NumOps); 2387 SDValue UndefVal = DAG.getUNDEF(LdTy); 2388 { 2389 unsigned i = 0; 2390 for (; i != End-Idx; ++i) 2391 WidenOps[i] = ConcatOps[Idx+i]; 2392 for (; i != NumOps; ++i) 2393 WidenOps[i] = UndefVal; 2394 } 2395 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps); 2396} 2397 2398SDValue 2399DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain, 2400 LoadSDNode * LD, 2401 ISD::LoadExtType ExtType) { 2402 // For extension loads, it may not be more efficient to chop up the vector 2403 // and then extended it. Instead, we unroll the load and build a new vector. 2404 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2405 EVT LdVT = LD->getMemoryVT(); 2406 DebugLoc dl = LD->getDebugLoc(); 2407 assert(LdVT.isVector() && WidenVT.isVector()); 2408 2409 // Load information 2410 SDValue Chain = LD->getChain(); 2411 SDValue BasePtr = LD->getBasePtr(); 2412 unsigned Align = LD->getAlignment(); 2413 bool isVolatile = LD->isVolatile(); 2414 bool isNonTemporal = LD->isNonTemporal(); 2415 2416 EVT EltVT = WidenVT.getVectorElementType(); 2417 EVT LdEltVT = LdVT.getVectorElementType(); 2418 unsigned NumElts = LdVT.getVectorNumElements(); 2419 2420 // Load each element and widen 2421 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2422 SmallVector<SDValue, 16> Ops(WidenNumElts); 2423 unsigned Increment = LdEltVT.getSizeInBits() / 8; 2424 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, 2425 LD->getPointerInfo(), 2426 LdEltVT, isVolatile, isNonTemporal, Align); 2427 LdChain.push_back(Ops[0].getValue(1)); 2428 unsigned i = 0, Offset = Increment; 2429 for (i=1; i < NumElts; ++i, Offset += Increment) { 2430 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2431 BasePtr, DAG.getIntPtrConstant(Offset)); 2432 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, 2433 LD->getPointerInfo().getWithOffset(Offset), LdEltVT, 2434 isVolatile, isNonTemporal, Align); 2435 LdChain.push_back(Ops[i].getValue(1)); 2436 } 2437 2438 // Fill the rest with undefs 2439 SDValue UndefVal = DAG.getUNDEF(EltVT); 2440 for (; i != WidenNumElts; ++i) 2441 Ops[i] = UndefVal; 2442 2443 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size()); 2444} 2445 2446 2447void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, 2448 StoreSDNode *ST) { 2449 // The strategy assumes that we can efficiently store powers of two widths. 2450 // The routines chops the vector into the largest vector stores with the same 2451 // element type or scalar stores. 2452 SDValue Chain = ST->getChain(); 2453 SDValue BasePtr = ST->getBasePtr(); 2454 unsigned Align = ST->getAlignment(); 2455 bool isVolatile = ST->isVolatile(); 2456 bool isNonTemporal = ST->isNonTemporal(); 2457 SDValue ValOp = GetWidenedVector(ST->getValue()); 2458 DebugLoc dl = ST->getDebugLoc(); 2459 2460 EVT StVT = ST->getMemoryVT(); 2461 unsigned StWidth = StVT.getSizeInBits(); 2462 EVT ValVT = ValOp.getValueType(); 2463 unsigned ValWidth = ValVT.getSizeInBits(); 2464 EVT ValEltVT = ValVT.getVectorElementType(); 2465 unsigned ValEltWidth = ValEltVT.getSizeInBits(); 2466 assert(StVT.getVectorElementType() == ValEltVT); 2467 2468 int Idx = 0; // current index to store 2469 unsigned Offset = 0; // offset from base to store 2470 while (StWidth != 0) { 2471 // Find the largest vector type we can store with 2472 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT); 2473 unsigned NewVTWidth = NewVT.getSizeInBits(); 2474 unsigned Increment = NewVTWidth / 8; 2475 if (NewVT.isVector()) { 2476 unsigned NumVTElts = NewVT.getVectorNumElements(); 2477 do { 2478 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, 2479 DAG.getIntPtrConstant(Idx)); 2480 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2481 ST->getPointerInfo().getWithOffset(Offset), 2482 isVolatile, isNonTemporal, 2483 MinAlign(Align, Offset))); 2484 StWidth -= NewVTWidth; 2485 Offset += Increment; 2486 Idx += NumVTElts; 2487 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2488 DAG.getIntPtrConstant(Increment)); 2489 } while (StWidth != 0 && StWidth >= NewVTWidth); 2490 } else { 2491 // Cast the vector to the scalar type we can store 2492 unsigned NumElts = ValWidth / NewVTWidth; 2493 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2494 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); 2495 // Readjust index position based on new vector type 2496 Idx = Idx * ValEltWidth / NewVTWidth; 2497 do { 2498 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp, 2499 DAG.getIntPtrConstant(Idx++)); 2500 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2501 ST->getPointerInfo().getWithOffset(Offset), 2502 isVolatile, isNonTemporal, 2503 MinAlign(Align, Offset))); 2504 StWidth -= NewVTWidth; 2505 Offset += Increment; 2506 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2507 DAG.getIntPtrConstant(Increment)); 2508 } while (StWidth != 0 && StWidth >= NewVTWidth); 2509 // Restore index back to be relative to the original widen element type 2510 Idx = Idx * NewVTWidth / ValEltWidth; 2511 } 2512 } 2513} 2514 2515void 2516DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain, 2517 StoreSDNode *ST) { 2518 // For extension loads, it may not be more efficient to truncate the vector 2519 // and then store it. Instead, we extract each element and then store it. 2520 SDValue Chain = ST->getChain(); 2521 SDValue BasePtr = ST->getBasePtr(); 2522 unsigned Align = ST->getAlignment(); 2523 bool isVolatile = ST->isVolatile(); 2524 bool isNonTemporal = ST->isNonTemporal(); 2525 SDValue ValOp = GetWidenedVector(ST->getValue()); 2526 DebugLoc dl = ST->getDebugLoc(); 2527 2528 EVT StVT = ST->getMemoryVT(); 2529 EVT ValVT = ValOp.getValueType(); 2530 2531 // It must be true that we the widen vector type is bigger than where 2532 // we need to store. 2533 assert(StVT.isVector() && ValOp.getValueType().isVector()); 2534 assert(StVT.bitsLT(ValOp.getValueType())); 2535 2536 // For truncating stores, we can not play the tricks of chopping legal 2537 // vector types and bit cast it to the right type. Instead, we unroll 2538 // the store. 2539 EVT StEltVT = StVT.getVectorElementType(); 2540 EVT ValEltVT = ValVT.getVectorElementType(); 2541 unsigned Increment = ValEltVT.getSizeInBits() / 8; 2542 unsigned NumElts = StVT.getVectorNumElements(); 2543 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2544 DAG.getIntPtrConstant(0)); 2545 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, 2546 ST->getPointerInfo(), StEltVT, 2547 isVolatile, isNonTemporal, Align)); 2548 unsigned Offset = Increment; 2549 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) { 2550 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2551 BasePtr, DAG.getIntPtrConstant(Offset)); 2552 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2553 DAG.getIntPtrConstant(0)); 2554 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, 2555 ST->getPointerInfo().getWithOffset(Offset), 2556 StEltVT, isVolatile, isNonTemporal, 2557 MinAlign(Align, Offset))); 2558 } 2559} 2560 2561/// Modifies a vector input (widen or narrows) to a vector of NVT. The 2562/// input vector must have the same element type as NVT. 2563SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) { 2564 // Note that InOp might have been widened so it might already have 2565 // the right width or it might need be narrowed. 2566 EVT InVT = InOp.getValueType(); 2567 assert(InVT.getVectorElementType() == NVT.getVectorElementType() && 2568 "input and widen element type must match"); 2569 DebugLoc dl = InOp.getDebugLoc(); 2570 2571 // Check if InOp already has the right width. 2572 if (InVT == NVT) 2573 return InOp; 2574 2575 unsigned InNumElts = InVT.getVectorNumElements(); 2576 unsigned WidenNumElts = NVT.getVectorNumElements(); 2577 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) { 2578 unsigned NumConcat = WidenNumElts / InNumElts; 2579 SmallVector<SDValue, 16> Ops(NumConcat); 2580 SDValue UndefVal = DAG.getUNDEF(InVT); 2581 Ops[0] = InOp; 2582 for (unsigned i = 1; i != NumConcat; ++i) 2583 Ops[i] = UndefVal; 2584 2585 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat); 2586 } 2587 2588 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts) 2589 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp, 2590 DAG.getIntPtrConstant(0)); 2591 2592 // Fall back to extract and build. 2593 SmallVector<SDValue, 16> Ops(WidenNumElts); 2594 EVT EltVT = NVT.getVectorElementType(); 2595 unsigned MinNumElts = std::min(WidenNumElts, InNumElts); 2596 unsigned Idx; 2597 for (Idx = 0; Idx < MinNumElts; ++Idx) 2598 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2599 DAG.getIntPtrConstant(Idx)); 2600 2601 SDValue UndefVal = DAG.getUNDEF(EltVT); 2602 for ( ; Idx < WidenNumElts; ++Idx) 2603 Ops[Idx] = UndefVal; 2604 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts); 2605} 2606