LegalizeVectorTypes.cpp revision ecf42c4720aba6ee315d0166045c54187ac2de4d
1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file performs vector type splitting and scalarization for LegalizeTypes. 11// Scalarization is the act of changing a computation in an illegal one-element 12// vector type to be a computation in its scalar element type. For example, 13// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed 14// as a base case when scalarizing vector arithmetic like <4 x f32>, which 15// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32 16// types. 17// Splitting is the act of changing a computation in an invalid vector type to 18// be a computation in two vectors of half the size. For example, implementing 19// <128 x f32> operations in terms of two <64 x f32> operations. 20// 21//===----------------------------------------------------------------------===// 22 23#include "LegalizeTypes.h" 24#include "llvm/CodeGen/PseudoSourceValue.h" 25#include "llvm/Target/TargetData.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Support/raw_ostream.h" 28using namespace llvm; 29 30//===----------------------------------------------------------------------===// 31// Result Vector Scalarization: <1 x ty> -> ty. 32//===----------------------------------------------------------------------===// 33 34void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { 35 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; 36 N->dump(&DAG); 37 dbgs() << "\n"); 38 SDValue R = SDValue(); 39 40 switch (N->getOpcode()) { 41 default: 42#ifndef NDEBUG 43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": "; 44 N->dump(&DAG); 45 dbgs() << "\n"; 46#endif 47 llvm_unreachable("Do not know how to scalarize the result of this operator!"); 48 49 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break; 50 case ISD::BUILD_VECTOR: R = N->getOperand(0); break; 51 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; 52 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 53 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; 54 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 55 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 56 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; 57 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; 58 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; 59 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break; 60 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; 61 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; 62 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; 63 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; 64 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break; 65 66 case ISD::CTLZ: 67 case ISD::CTPOP: 68 case ISD::CTTZ: 69 case ISD::FABS: 70 case ISD::FCOS: 71 case ISD::FNEG: 72 case ISD::FP_TO_SINT: 73 case ISD::FP_TO_UINT: 74 case ISD::FSIN: 75 case ISD::FSQRT: 76 case ISD::FTRUNC: 77 case ISD::FFLOOR: 78 case ISD::FCEIL: 79 case ISD::FRINT: 80 case ISD::FNEARBYINT: 81 case ISD::UINT_TO_FP: 82 case ISD::SINT_TO_FP: 83 case ISD::TRUNCATE: 84 case ISD::SIGN_EXTEND: 85 case ISD::ZERO_EXTEND: 86 case ISD::ANY_EXTEND: 87 R = ScalarizeVecRes_UnaryOp(N); 88 break; 89 90 case ISD::ADD: 91 case ISD::AND: 92 case ISD::FADD: 93 case ISD::FDIV: 94 case ISD::FMUL: 95 case ISD::FPOW: 96 case ISD::FREM: 97 case ISD::FSUB: 98 case ISD::MUL: 99 case ISD::OR: 100 case ISD::SDIV: 101 case ISD::SREM: 102 case ISD::SUB: 103 case ISD::UDIV: 104 case ISD::UREM: 105 case ISD::XOR: 106 case ISD::SHL: 107 case ISD::SRA: 108 case ISD::SRL: 109 R = ScalarizeVecRes_BinOp(N); 110 break; 111 } 112 113 // If R is null, the sub-method took care of registering the result. 114 if (R.getNode()) 115 SetScalarizedVector(SDValue(N, ResNo), R); 116} 117 118SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { 119 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 120 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 121 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 122 LHS.getValueType(), LHS, RHS); 123} 124 125SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) { 126 EVT NewVT = N->getValueType(0).getVectorElementType(); 127 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 128 NewVT, N->getOperand(0)); 129} 130 131SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) { 132 EVT NewVT = N->getValueType(0).getVectorElementType(); 133 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); 134 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(), 135 Op0, DAG.getValueType(NewVT), 136 DAG.getValueType(Op0.getValueType()), 137 N->getOperand(3), 138 N->getOperand(4), 139 cast<CvtRndSatSDNode>(N)->getCvtCode()); 140} 141 142SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 143 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 144 N->getValueType(0).getVectorElementType(), 145 N->getOperand(0), N->getOperand(1)); 146} 147 148SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) { 149 SDValue Op = GetScalarizedVector(N->getOperand(0)); 150 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(), 151 Op.getValueType(), Op, N->getOperand(1)); 152} 153 154SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { 155 // The value to insert may have a wider type than the vector element type, 156 // so be sure to truncate it to the element type if necessary. 157 SDValue Op = N->getOperand(1); 158 EVT EltVT = N->getValueType(0).getVectorElementType(); 159 if (Op.getValueType() != EltVT) 160 // FIXME: Can this happen for floating point types? 161 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op); 162 return Op; 163} 164 165SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { 166 assert(N->isUnindexed() && "Indexed vector load?"); 167 168 SDValue Result = DAG.getLoad(ISD::UNINDEXED, 169 N->getExtensionType(), 170 N->getValueType(0).getVectorElementType(), 171 N->getDebugLoc(), 172 N->getChain(), N->getBasePtr(), 173 DAG.getUNDEF(N->getBasePtr().getValueType()), 174 N->getSrcValue(), N->getSrcValueOffset(), 175 N->getMemoryVT().getVectorElementType(), 176 N->isVolatile(), N->isNonTemporal(), 177 N->getOriginalAlignment()); 178 179 // Legalized the chain result - switch anything that used the old chain to 180 // use the new one. 181 ReplaceValueWith(SDValue(N, 1), Result.getValue(1)); 182 return Result; 183} 184 185SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { 186 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp. 187 EVT DestVT = N->getValueType(0).getVectorElementType(); 188 SDValue Op = GetScalarizedVector(N->getOperand(0)); 189 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op); 190} 191 192SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) { 193 EVT EltVT = N->getValueType(0).getVectorElementType(); 194 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType(); 195 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 196 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT, 197 LHS, DAG.getValueType(ExtVT)); 198} 199 200SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) { 201 // If the operand is wider than the vector element type then it is implicitly 202 // truncated. Make that explicit here. 203 EVT EltVT = N->getValueType(0).getVectorElementType(); 204 SDValue InOp = N->getOperand(0); 205 if (InOp.getValueType() != EltVT) 206 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp); 207 return InOp; 208} 209 210SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) { 211 SDValue LHS = GetScalarizedVector(N->getOperand(1)); 212 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 213 LHS.getValueType(), N->getOperand(0), LHS, 214 GetScalarizedVector(N->getOperand(2))); 215} 216 217SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) { 218 SDValue LHS = GetScalarizedVector(N->getOperand(2)); 219 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(), 220 N->getOperand(0), N->getOperand(1), 221 LHS, GetScalarizedVector(N->getOperand(3)), 222 N->getOperand(4)); 223} 224 225SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) { 226 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 227 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 228 DebugLoc DL = N->getDebugLoc(); 229 230 // Turn it into a scalar SETCC. 231 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); 232} 233 234SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { 235 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 236} 237 238SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { 239 // Figure out if the scalar is the LHS or RHS and return it. 240 SDValue Arg = N->getOperand(2).getOperand(0); 241 if (Arg.getOpcode() == ISD::UNDEF) 242 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 243 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue(); 244 return GetScalarizedVector(N->getOperand(Op)); 245} 246 247SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) { 248 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 249 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 250 EVT NVT = N->getValueType(0).getVectorElementType(); 251 EVT SVT = TLI.getSetCCResultType(LHS.getValueType()); 252 DebugLoc DL = N->getDebugLoc(); 253 254 // Turn it into a scalar SETCC. 255 SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2)); 256 257 // VSETCC always returns a sign-extended value, while SETCC may not. The 258 // SETCC result type may not match the vector element type. Correct these. 259 if (NVT.bitsLE(SVT)) { 260 // The SETCC result type is bigger than the vector element type. 261 // Ensure the SETCC result is sign-extended. 262 if (TLI.getBooleanContents() != 263 TargetLowering::ZeroOrNegativeOneBooleanContent) 264 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res, 265 DAG.getValueType(MVT::i1)); 266 // Truncate to the final type. 267 return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res); 268 } 269 270 // The SETCC result type is smaller than the vector element type. 271 // If the SetCC result is not sign-extended, chop it down to MVT::i1. 272 if (TLI.getBooleanContents() != 273 TargetLowering::ZeroOrNegativeOneBooleanContent) 274 Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res); 275 // Sign extend to the final type. 276 return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res); 277} 278 279 280//===----------------------------------------------------------------------===// 281// Operand Vector Scalarization <1 x ty> -> ty. 282//===----------------------------------------------------------------------===// 283 284bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { 285 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; 286 N->dump(&DAG); 287 dbgs() << "\n"); 288 SDValue Res = SDValue(); 289 290 if (Res.getNode() == 0) { 291 switch (N->getOpcode()) { 292 default: 293#ifndef NDEBUG 294 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": "; 295 N->dump(&DAG); 296 dbgs() << "\n"; 297#endif 298 llvm_unreachable("Do not know how to scalarize this operator's operand!"); 299 case ISD::BIT_CONVERT: 300 Res = ScalarizeVecOp_BIT_CONVERT(N); 301 break; 302 case ISD::CONCAT_VECTORS: 303 Res = ScalarizeVecOp_CONCAT_VECTORS(N); 304 break; 305 case ISD::EXTRACT_VECTOR_ELT: 306 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); 307 break; 308 case ISD::STORE: 309 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); 310 break; 311 } 312 } 313 314 // If the result is null, the sub-method took care of registering results etc. 315 if (!Res.getNode()) return false; 316 317 // If the result is N, the sub-method updated N in place. Tell the legalizer 318 // core about this. 319 if (Res.getNode() == N) 320 return true; 321 322 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 323 "Invalid operand expansion"); 324 325 ReplaceValueWith(SDValue(N, 0), Res); 326 return false; 327} 328 329/// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs 330/// to be scalarized, it must be <1 x ty>. Convert the element instead. 331SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) { 332 SDValue Elt = GetScalarizedVector(N->getOperand(0)); 333 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 334 N->getValueType(0), Elt); 335} 336 337/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one - 338/// use a BUILD_VECTOR instead. 339SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) { 340 SmallVector<SDValue, 8> Ops(N->getNumOperands()); 341 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 342 Ops[i] = GetScalarizedVector(N->getOperand(i)); 343 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0), 344 &Ops[0], Ops.size()); 345} 346 347/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to 348/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the 349/// index. 350SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 351 SDValue Res = GetScalarizedVector(N->getOperand(0)); 352 if (Res.getValueType() != N->getValueType(0)) 353 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), 354 Res); 355 return Res; 356} 357 358/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be 359/// scalarized, it must be <1 x ty>. Just store the element. 360SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ 361 assert(N->isUnindexed() && "Indexed store of one-element vector?"); 362 assert(OpNo == 1 && "Do not know how to scalarize this operand!"); 363 DebugLoc dl = N->getDebugLoc(); 364 365 if (N->isTruncatingStore()) 366 return DAG.getTruncStore(N->getChain(), dl, 367 GetScalarizedVector(N->getOperand(1)), 368 N->getBasePtr(), 369 N->getSrcValue(), N->getSrcValueOffset(), 370 N->getMemoryVT().getVectorElementType(), 371 N->isVolatile(), N->isNonTemporal(), 372 N->getAlignment()); 373 374 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)), 375 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(), 376 N->isVolatile(), N->isNonTemporal(), 377 N->getOriginalAlignment()); 378} 379 380 381//===----------------------------------------------------------------------===// 382// Result Vector Splitting 383//===----------------------------------------------------------------------===// 384 385/// SplitVectorResult - This method is called when the specified result of the 386/// specified node is found to need vector splitting. At this point, the node 387/// may also have invalid operands or may have other results that need 388/// legalization, we just know that (at least) one result needs vector 389/// splitting. 390void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { 391 DEBUG(dbgs() << "Split node result: "; 392 N->dump(&DAG); 393 dbgs() << "\n"); 394 SDValue Lo, Hi; 395 396 switch (N->getOpcode()) { 397 default: 398#ifndef NDEBUG 399 dbgs() << "SplitVectorResult #" << ResNo << ": "; 400 N->dump(&DAG); 401 dbgs() << "\n"; 402#endif 403 llvm_unreachable("Do not know how to split the result of this operator!"); 404 405 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 406 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 407 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 408 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 409 410 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break; 411 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 412 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 413 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break; 414 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; 415 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 416 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; 417 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 418 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break; 419 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 420 case ISD::LOAD: 421 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); 422 break; 423 case ISD::SETCC: 424 case ISD::VSETCC: 425 SplitVecRes_SETCC(N, Lo, Hi); 426 break; 427 case ISD::VECTOR_SHUFFLE: 428 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); 429 break; 430 431 case ISD::CTTZ: 432 case ISD::CTLZ: 433 case ISD::CTPOP: 434 case ISD::FNEG: 435 case ISD::FABS: 436 case ISD::FSQRT: 437 case ISD::FSIN: 438 case ISD::FCOS: 439 case ISD::FTRUNC: 440 case ISD::FFLOOR: 441 case ISD::FCEIL: 442 case ISD::FRINT: 443 case ISD::FNEARBYINT: 444 case ISD::FP_TO_SINT: 445 case ISD::FP_TO_UINT: 446 case ISD::SINT_TO_FP: 447 case ISD::UINT_TO_FP: 448 case ISD::TRUNCATE: 449 case ISD::SIGN_EXTEND: 450 case ISD::ZERO_EXTEND: 451 case ISD::ANY_EXTEND: 452 case ISD::FEXP: 453 case ISD::FEXP2: 454 case ISD::FLOG: 455 case ISD::FLOG2: 456 case ISD::FLOG10: 457 SplitVecRes_UnaryOp(N, Lo, Hi); 458 break; 459 460 case ISD::ADD: 461 case ISD::SUB: 462 case ISD::MUL: 463 case ISD::FADD: 464 case ISD::FSUB: 465 case ISD::FMUL: 466 case ISD::SDIV: 467 case ISD::UDIV: 468 case ISD::FDIV: 469 case ISD::FPOW: 470 case ISD::AND: 471 case ISD::OR: 472 case ISD::XOR: 473 case ISD::SHL: 474 case ISD::SRA: 475 case ISD::SRL: 476 case ISD::UREM: 477 case ISD::SREM: 478 case ISD::FREM: 479 SplitVecRes_BinOp(N, Lo, Hi); 480 break; 481 } 482 483 // If Lo/Hi is null, the sub-method took care of registering results etc. 484 if (Lo.getNode()) 485 SetSplitVector(SDValue(N, ResNo), Lo, Hi); 486} 487 488void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo, 489 SDValue &Hi) { 490 SDValue LHSLo, LHSHi; 491 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 492 SDValue RHSLo, RHSHi; 493 GetSplitVector(N->getOperand(1), RHSLo, RHSHi); 494 DebugLoc dl = N->getDebugLoc(); 495 496 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo); 497 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi); 498} 499 500void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo, 501 SDValue &Hi) { 502 // We know the result is a vector. The input may be either a vector or a 503 // scalar value. 504 EVT LoVT, HiVT; 505 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 506 DebugLoc dl = N->getDebugLoc(); 507 508 SDValue InOp = N->getOperand(0); 509 EVT InVT = InOp.getValueType(); 510 511 // Handle some special cases efficiently. 512 switch (getTypeAction(InVT)) { 513 default: 514 assert(false && "Unknown type action!"); 515 case Legal: 516 case PromoteInteger: 517 case SoftenFloat: 518 case ScalarizeVector: 519 break; 520 case ExpandInteger: 521 case ExpandFloat: 522 // A scalar to vector conversion, where the scalar needs expansion. 523 // If the vector is being split in two then we can just convert the 524 // expanded pieces. 525 if (LoVT == HiVT) { 526 GetExpandedOp(InOp, Lo, Hi); 527 if (TLI.isBigEndian()) 528 std::swap(Lo, Hi); 529 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo); 530 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi); 531 return; 532 } 533 break; 534 case SplitVector: 535 // If the input is a vector that needs to be split, convert each split 536 // piece of the input now. 537 GetSplitVector(InOp, Lo, Hi); 538 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo); 539 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi); 540 return; 541 } 542 543 // In the general case, convert the input to an integer and split it by hand. 544 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits()); 545 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits()); 546 if (TLI.isBigEndian()) 547 std::swap(LoIntVT, HiIntVT); 548 549 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); 550 551 if (TLI.isBigEndian()) 552 std::swap(Lo, Hi); 553 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo); 554 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi); 555} 556 557void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, 558 SDValue &Hi) { 559 EVT LoVT, HiVT; 560 DebugLoc dl = N->getDebugLoc(); 561 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 562 unsigned LoNumElts = LoVT.getVectorNumElements(); 563 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts); 564 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size()); 565 566 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end()); 567 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size()); 568} 569 570void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, 571 SDValue &Hi) { 572 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"); 573 DebugLoc dl = N->getDebugLoc(); 574 unsigned NumSubvectors = N->getNumOperands() / 2; 575 if (NumSubvectors == 1) { 576 Lo = N->getOperand(0); 577 Hi = N->getOperand(1); 578 return; 579 } 580 581 EVT LoVT, HiVT; 582 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 583 584 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); 585 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size()); 586 587 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end()); 588 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size()); 589} 590 591void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo, 592 SDValue &Hi) { 593 EVT LoVT, HiVT; 594 DebugLoc dl = N->getDebugLoc(); 595 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 596 597 SDValue DTyOpLo = DAG.getValueType(LoVT); 598 SDValue DTyOpHi = DAG.getValueType(HiVT); 599 600 SDValue RndOp = N->getOperand(3); 601 SDValue SatOp = N->getOperand(4); 602 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 603 604 // Split the input. 605 SDValue VLo, VHi; 606 EVT InVT = N->getOperand(0).getValueType(); 607 switch (getTypeAction(InVT)) { 608 default: llvm_unreachable("Unexpected type action!"); 609 case Legal: { 610 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 611 LoVT.getVectorNumElements()); 612 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 613 DAG.getIntPtrConstant(0)); 614 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 615 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 616 break; 617 } 618 case SplitVector: 619 GetSplitVector(N->getOperand(0), VLo, VHi); 620 break; 621 case WidenVector: { 622 // If the result needs to be split and the input needs to be widened, 623 // the two types must have different lengths. Use the widened result 624 // and extract from it to do the split. 625 SDValue InOp = GetWidenedVector(N->getOperand(0)); 626 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 627 LoVT.getVectorNumElements()); 628 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 629 DAG.getIntPtrConstant(0)); 630 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 631 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 632 break; 633 } 634 } 635 636 SDValue STyOpLo = DAG.getValueType(VLo.getValueType()); 637 SDValue STyOpHi = DAG.getValueType(VHi.getValueType()); 638 639 Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, 640 CvtCode); 641 Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp, 642 CvtCode); 643} 644 645void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, 646 SDValue &Hi) { 647 SDValue Vec = N->getOperand(0); 648 SDValue Idx = N->getOperand(1); 649 EVT IdxVT = Idx.getValueType(); 650 DebugLoc dl = N->getDebugLoc(); 651 652 EVT LoVT, HiVT; 653 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 654 655 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); 656 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx, 657 DAG.getConstant(LoVT.getVectorNumElements(), IdxVT)); 658 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, Idx); 659} 660 661void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, 662 SDValue &Hi) { 663 DebugLoc dl = N->getDebugLoc(); 664 GetSplitVector(N->getOperand(0), Lo, Hi); 665 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1)); 666 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1)); 667} 668 669void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo, 670 SDValue &Hi) { 671 SDValue LHSLo, LHSHi; 672 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 673 DebugLoc dl = N->getDebugLoc(); 674 675 EVT LoVT, HiVT; 676 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT); 677 678 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, 679 DAG.getValueType(LoVT)); 680 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, 681 DAG.getValueType(HiVT)); 682} 683 684void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, 685 SDValue &Hi) { 686 SDValue Vec = N->getOperand(0); 687 SDValue Elt = N->getOperand(1); 688 SDValue Idx = N->getOperand(2); 689 DebugLoc dl = N->getDebugLoc(); 690 GetSplitVector(Vec, Lo, Hi); 691 692 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 693 unsigned IdxVal = CIdx->getZExtValue(); 694 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 695 if (IdxVal < LoNumElts) 696 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 697 Lo.getValueType(), Lo, Elt, Idx); 698 else 699 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, 700 DAG.getIntPtrConstant(IdxVal - LoNumElts)); 701 return; 702 } 703 704 // Spill the vector to the stack. 705 EVT VecVT = Vec.getValueType(); 706 EVT EltVT = VecVT.getVectorElementType(); 707 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 708 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 709 MachinePointerInfo(), false, false, 0); 710 711 // Store the new element. This may be larger than the vector element type, 712 // so use a truncating store. 713 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 714 const Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); 715 unsigned Alignment = 716 TLI.getTargetData()->getPrefTypeAlignment(VecType); 717 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT, 718 false, false, 0); 719 720 // Load the Lo part from the stack slot. 721 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 722 false, false, 0); 723 724 // Increment the pointer to the other part. 725 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; 726 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 727 DAG.getIntPtrConstant(IncrementSize)); 728 729 // Load the Hi part from the stack slot. 730 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 731 false, false, MinAlign(Alignment, IncrementSize)); 732} 733 734void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, 735 SDValue &Hi) { 736 EVT LoVT, HiVT; 737 DebugLoc dl = N->getDebugLoc(); 738 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 739 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0)); 740 Hi = DAG.getUNDEF(HiVT); 741} 742 743void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, 744 SDValue &Hi) { 745 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"); 746 EVT LoVT, HiVT; 747 DebugLoc dl = LD->getDebugLoc(); 748 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); 749 750 ISD::LoadExtType ExtType = LD->getExtensionType(); 751 SDValue Ch = LD->getChain(); 752 SDValue Ptr = LD->getBasePtr(); 753 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 754 const Value *SV = LD->getSrcValue(); 755 int SVOffset = LD->getSrcValueOffset(); 756 EVT MemoryVT = LD->getMemoryVT(); 757 unsigned Alignment = LD->getOriginalAlignment(); 758 bool isVolatile = LD->isVolatile(); 759 bool isNonTemporal = LD->isNonTemporal(); 760 761 EVT LoMemVT, HiMemVT; 762 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 763 764 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, 765 SV, SVOffset, LoMemVT, isVolatile, isNonTemporal, Alignment); 766 767 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 768 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 769 DAG.getIntPtrConstant(IncrementSize)); 770 SVOffset += IncrementSize; 771 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, 772 SV, SVOffset, HiMemVT, isVolatile, isNonTemporal, Alignment); 773 774 // Build a factor node to remember that this load is independent of the 775 // other one. 776 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 777 Hi.getValue(1)); 778 779 // Legalized the chain result - switch anything that used the old chain to 780 // use the new one. 781 ReplaceValueWith(SDValue(LD, 1), Ch); 782} 783 784void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) { 785 EVT LoVT, HiVT; 786 DebugLoc DL = N->getDebugLoc(); 787 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 788 789 // Split the input. 790 EVT InVT = N->getOperand(0).getValueType(); 791 SDValue LL, LH, RL, RH; 792 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 793 LoVT.getVectorNumElements()); 794 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 795 DAG.getIntPtrConstant(0)); 796 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 797 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 798 799 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 800 DAG.getIntPtrConstant(0)); 801 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 802 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 803 804 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2)); 805 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2)); 806} 807 808void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, 809 SDValue &Hi) { 810 // Get the dest types - they may not match the input types, e.g. int_to_fp. 811 EVT LoVT, HiVT; 812 DebugLoc dl = N->getDebugLoc(); 813 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 814 815 // Split the input. 816 EVT InVT = N->getOperand(0).getValueType(); 817 switch (getTypeAction(InVT)) { 818 default: llvm_unreachable("Unexpected type action!"); 819 case Legal: { 820 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 821 LoVT.getVectorNumElements()); 822 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 823 DAG.getIntPtrConstant(0)); 824 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 825 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 826 break; 827 } 828 case SplitVector: 829 GetSplitVector(N->getOperand(0), Lo, Hi); 830 break; 831 case WidenVector: { 832 // If the result needs to be split and the input needs to be widened, 833 // the two types must have different lengths. Use the widened result 834 // and extract from it to do the split. 835 SDValue InOp = GetWidenedVector(N->getOperand(0)); 836 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 837 LoVT.getVectorNumElements()); 838 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 839 DAG.getIntPtrConstant(0)); 840 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 841 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 842 break; 843 } 844 } 845 846 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo); 847 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi); 848} 849 850void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, 851 SDValue &Lo, SDValue &Hi) { 852 // The low and high parts of the original input give four input vectors. 853 SDValue Inputs[4]; 854 DebugLoc dl = N->getDebugLoc(); 855 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]); 856 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]); 857 EVT NewVT = Inputs[0].getValueType(); 858 unsigned NewElts = NewVT.getVectorNumElements(); 859 860 // If Lo or Hi uses elements from at most two of the four input vectors, then 861 // express it as a vector shuffle of those two inputs. Otherwise extract the 862 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. 863 SmallVector<int, 16> Ops; 864 for (unsigned High = 0; High < 2; ++High) { 865 SDValue &Output = High ? Hi : Lo; 866 867 // Build a shuffle mask for the output, discovering on the fly which 868 // input vectors to use as shuffle operands (recorded in InputUsed). 869 // If building a suitable shuffle vector proves too hard, then bail 870 // out with useBuildVector set. 871 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered. 872 unsigned FirstMaskIdx = High * NewElts; 873 bool useBuildVector = false; 874 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 875 // The mask element. This indexes into the input. 876 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 877 878 // The input vector this mask element indexes into. 879 unsigned Input = (unsigned)Idx / NewElts; 880 881 if (Input >= array_lengthof(Inputs)) { 882 // The mask element does not index into any input vector. 883 Ops.push_back(-1); 884 continue; 885 } 886 887 // Turn the index into an offset from the start of the input vector. 888 Idx -= Input * NewElts; 889 890 // Find or create a shuffle vector operand to hold this input. 891 unsigned OpNo; 892 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 893 if (InputUsed[OpNo] == Input) { 894 // This input vector is already an operand. 895 break; 896 } else if (InputUsed[OpNo] == -1U) { 897 // Create a new operand for this input vector. 898 InputUsed[OpNo] = Input; 899 break; 900 } 901 } 902 903 if (OpNo >= array_lengthof(InputUsed)) { 904 // More than two input vectors used! Give up on trying to create a 905 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 906 useBuildVector = true; 907 break; 908 } 909 910 // Add the mask index for the new shuffle vector. 911 Ops.push_back(Idx + OpNo * NewElts); 912 } 913 914 if (useBuildVector) { 915 EVT EltVT = NewVT.getVectorElementType(); 916 SmallVector<SDValue, 16> SVOps; 917 918 // Extract the input elements by hand. 919 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 920 // The mask element. This indexes into the input. 921 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 922 923 // The input vector this mask element indexes into. 924 unsigned Input = (unsigned)Idx / NewElts; 925 926 if (Input >= array_lengthof(Inputs)) { 927 // The mask element is "undef" or indexes off the end of the input. 928 SVOps.push_back(DAG.getUNDEF(EltVT)); 929 continue; 930 } 931 932 // Turn the index into an offset from the start of the input vector. 933 Idx -= Input * NewElts; 934 935 // Extract the vector element by hand. 936 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 937 Inputs[Input], DAG.getIntPtrConstant(Idx))); 938 } 939 940 // Construct the Lo/Hi output using a BUILD_VECTOR. 941 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size()); 942 } else if (InputUsed[0] == -1U) { 943 // No input vectors were used! The result is undefined. 944 Output = DAG.getUNDEF(NewVT); 945 } else { 946 SDValue Op0 = Inputs[InputUsed[0]]; 947 // If only one input was used, use an undefined vector for the other. 948 SDValue Op1 = InputUsed[1] == -1U ? 949 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]]; 950 // At least one input vector was used. Create a new shuffle vector. 951 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]); 952 } 953 954 Ops.clear(); 955 } 956} 957 958 959//===----------------------------------------------------------------------===// 960// Operand Vector Splitting 961//===----------------------------------------------------------------------===// 962 963/// SplitVectorOperand - This method is called when the specified operand of the 964/// specified node is found to need vector splitting. At this point, all of the 965/// result types of the node are known to be legal, but other operands of the 966/// node may need legalization as well as the specified one. 967bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { 968 DEBUG(dbgs() << "Split node operand: "; 969 N->dump(&DAG); 970 dbgs() << "\n"); 971 SDValue Res = SDValue(); 972 973 if (Res.getNode() == 0) { 974 switch (N->getOpcode()) { 975 default: 976#ifndef NDEBUG 977 dbgs() << "SplitVectorOperand Op #" << OpNo << ": "; 978 N->dump(&DAG); 979 dbgs() << "\n"; 980#endif 981 llvm_unreachable("Do not know how to split this operator's operand!"); 982 983 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break; 984 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; 985 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; 986 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; 987 case ISD::STORE: 988 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo); 989 break; 990 991 case ISD::CTTZ: 992 case ISD::CTLZ: 993 case ISD::CTPOP: 994 case ISD::FP_TO_SINT: 995 case ISD::FP_TO_UINT: 996 case ISD::SINT_TO_FP: 997 case ISD::UINT_TO_FP: 998 case ISD::TRUNCATE: 999 case ISD::SIGN_EXTEND: 1000 case ISD::ZERO_EXTEND: 1001 case ISD::ANY_EXTEND: 1002 Res = SplitVecOp_UnaryOp(N); 1003 break; 1004 } 1005 } 1006 1007 // If the result is null, the sub-method took care of registering results etc. 1008 if (!Res.getNode()) return false; 1009 1010 // If the result is N, the sub-method updated N in place. Tell the legalizer 1011 // core about this. 1012 if (Res.getNode() == N) 1013 return true; 1014 1015 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1016 "Invalid operand expansion"); 1017 1018 ReplaceValueWith(SDValue(N, 0), Res); 1019 return false; 1020} 1021 1022SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) { 1023 // The result has a legal vector type, but the input needs splitting. 1024 EVT ResVT = N->getValueType(0); 1025 SDValue Lo, Hi; 1026 DebugLoc dl = N->getDebugLoc(); 1027 GetSplitVector(N->getOperand(0), Lo, Hi); 1028 EVT InVT = Lo.getValueType(); 1029 1030 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1031 InVT.getVectorNumElements()); 1032 1033 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); 1034 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); 1035 1036 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); 1037} 1038 1039SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) { 1040 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will 1041 // end up being split all the way down to individual components. Convert the 1042 // split pieces into integers and reassemble. 1043 SDValue Lo, Hi; 1044 GetSplitVector(N->getOperand(0), Lo, Hi); 1045 Lo = BitConvertToInteger(Lo); 1046 Hi = BitConvertToInteger(Hi); 1047 1048 if (TLI.isBigEndian()) 1049 std::swap(Lo, Hi); 1050 1051 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), N->getValueType(0), 1052 JoinIntegers(Lo, Hi)); 1053} 1054 1055SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 1056 // We know that the extracted result type is legal. For now, assume the index 1057 // is a constant. 1058 EVT SubVT = N->getValueType(0); 1059 SDValue Idx = N->getOperand(1); 1060 DebugLoc dl = N->getDebugLoc(); 1061 SDValue Lo, Hi; 1062 GetSplitVector(N->getOperand(0), Lo, Hi); 1063 1064 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1065 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1066 1067 if (IdxVal < LoElts) { 1068 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && 1069 "Extracted subvector crosses vector split!"); 1070 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); 1071 } else { 1072 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, 1073 DAG.getConstant(IdxVal - LoElts, Idx.getValueType())); 1074 } 1075} 1076 1077SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 1078 SDValue Vec = N->getOperand(0); 1079 SDValue Idx = N->getOperand(1); 1080 EVT VecVT = Vec.getValueType(); 1081 1082 if (isa<ConstantSDNode>(Idx)) { 1083 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1084 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); 1085 1086 SDValue Lo, Hi; 1087 GetSplitVector(Vec, Lo, Hi); 1088 1089 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1090 1091 if (IdxVal < LoElts) 1092 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0); 1093 return SDValue(DAG.UpdateNodeOperands(N, Hi, 1094 DAG.getConstant(IdxVal - LoElts, 1095 Idx.getValueType())), 0); 1096 } 1097 1098 // Store the vector to the stack. 1099 EVT EltVT = VecVT.getVectorElementType(); 1100 DebugLoc dl = N->getDebugLoc(); 1101 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 1102 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 1103 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1104 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, SV, 0, 1105 false, false, 0); 1106 1107 // Load back the required element. 1108 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 1109 return DAG.getExtLoad(ISD::EXTLOAD, N->getValueType(0), dl, Store, StackPtr, 1110 SV, 0, EltVT, false, false, 0); 1111} 1112 1113SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { 1114 assert(N->isUnindexed() && "Indexed store of vector?"); 1115 assert(OpNo == 1 && "Can only split the stored value"); 1116 DebugLoc DL = N->getDebugLoc(); 1117 1118 bool isTruncating = N->isTruncatingStore(); 1119 SDValue Ch = N->getChain(); 1120 SDValue Ptr = N->getBasePtr(); 1121 int SVOffset = N->getSrcValueOffset(); 1122 EVT MemoryVT = N->getMemoryVT(); 1123 unsigned Alignment = N->getOriginalAlignment(); 1124 bool isVol = N->isVolatile(); 1125 bool isNT = N->isNonTemporal(); 1126 SDValue Lo, Hi; 1127 GetSplitVector(N->getOperand(1), Lo, Hi); 1128 1129 EVT LoMemVT, HiMemVT; 1130 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 1131 1132 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 1133 1134 if (isTruncating) 1135 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getSrcValue(), SVOffset, 1136 LoMemVT, isVol, isNT, Alignment); 1137 else 1138 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getSrcValue(), SVOffset, 1139 isVol, isNT, Alignment); 1140 1141 // Increment the pointer to the other half. 1142 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, 1143 DAG.getIntPtrConstant(IncrementSize)); 1144 SVOffset += IncrementSize; 1145 1146 if (isTruncating) 1147 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr, N->getSrcValue(), SVOffset, 1148 HiMemVT, isVol, isNT, Alignment); 1149 else 1150 Hi = DAG.getStore(Ch, DL, Hi, Ptr, N->getSrcValue(), SVOffset, 1151 isVol, isNT, Alignment); 1152 1153 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi); 1154} 1155 1156SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) { 1157 DebugLoc DL = N->getDebugLoc(); 1158 1159 // The input operands all must have the same type, and we know the result the 1160 // result type is valid. Convert this to a buildvector which extracts all the 1161 // input elements. 1162 // TODO: If the input elements are power-two vectors, we could convert this to 1163 // a new CONCAT_VECTORS node with elements that are half-wide. 1164 SmallVector<SDValue, 32> Elts; 1165 EVT EltVT = N->getValueType(0).getVectorElementType(); 1166 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1167 SDValue Op = N->getOperand(op); 1168 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements(); 1169 i != e; ++i) { 1170 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, 1171 Op, DAG.getIntPtrConstant(i))); 1172 1173 } 1174 } 1175 1176 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), 1177 &Elts[0], Elts.size()); 1178} 1179 1180 1181//===----------------------------------------------------------------------===// 1182// Result Vector Widening 1183//===----------------------------------------------------------------------===// 1184 1185void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { 1186 DEBUG(dbgs() << "Widen node result " << ResNo << ": "; 1187 N->dump(&DAG); 1188 dbgs() << "\n"); 1189 1190 // See if the target wants to custom widen this node. 1191 if (CustomWidenLowerNode(N, N->getValueType(ResNo))) 1192 return; 1193 1194 SDValue Res = SDValue(); 1195 switch (N->getOpcode()) { 1196 default: 1197#ifndef NDEBUG 1198 dbgs() << "WidenVectorResult #" << ResNo << ": "; 1199 N->dump(&DAG); 1200 dbgs() << "\n"; 1201#endif 1202 llvm_unreachable("Do not know how to widen the result of this operator!"); 1203 1204 case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break; 1205 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; 1206 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break; 1207 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break; 1208 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; 1209 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break; 1210 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; 1211 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break; 1212 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break; 1213 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break; 1214 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break; 1215 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; 1216 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; 1217 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break; 1218 case ISD::VECTOR_SHUFFLE: 1219 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N)); 1220 break; 1221 case ISD::VSETCC: 1222 Res = WidenVecRes_VSETCC(N); 1223 break; 1224 1225 case ISD::ADD: 1226 case ISD::AND: 1227 case ISD::BSWAP: 1228 case ISD::FADD: 1229 case ISD::FCOPYSIGN: 1230 case ISD::FDIV: 1231 case ISD::FMUL: 1232 case ISD::FPOW: 1233 case ISD::FREM: 1234 case ISD::FSUB: 1235 case ISD::MUL: 1236 case ISD::MULHS: 1237 case ISD::MULHU: 1238 case ISD::OR: 1239 case ISD::SDIV: 1240 case ISD::SREM: 1241 case ISD::UDIV: 1242 case ISD::UREM: 1243 case ISD::SUB: 1244 case ISD::XOR: 1245 Res = WidenVecRes_Binary(N); 1246 break; 1247 1248 case ISD::FPOWI: 1249 Res = WidenVecRes_POWI(N); 1250 break; 1251 1252 case ISD::SHL: 1253 case ISD::SRA: 1254 case ISD::SRL: 1255 Res = WidenVecRes_Shift(N); 1256 break; 1257 1258 case ISD::FP_ROUND: 1259 case ISD::FP_TO_SINT: 1260 case ISD::FP_TO_UINT: 1261 case ISD::SINT_TO_FP: 1262 case ISD::UINT_TO_FP: 1263 case ISD::TRUNCATE: 1264 case ISD::SIGN_EXTEND: 1265 case ISD::ZERO_EXTEND: 1266 case ISD::ANY_EXTEND: 1267 Res = WidenVecRes_Convert(N); 1268 break; 1269 1270 case ISD::CTLZ: 1271 case ISD::CTPOP: 1272 case ISD::CTTZ: 1273 case ISD::FABS: 1274 case ISD::FCOS: 1275 case ISD::FNEG: 1276 case ISD::FSIN: 1277 case ISD::FSQRT: 1278 case ISD::FEXP: 1279 case ISD::FEXP2: 1280 case ISD::FLOG: 1281 case ISD::FLOG2: 1282 case ISD::FLOG10: 1283 Res = WidenVecRes_Unary(N); 1284 break; 1285 } 1286 1287 // If Res is null, the sub-method took care of registering the result. 1288 if (Res.getNode()) 1289 SetWidenedVector(SDValue(N, ResNo), Res); 1290} 1291 1292SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) { 1293 // Binary op widening. 1294 unsigned Opcode = N->getOpcode(); 1295 DebugLoc dl = N->getDebugLoc(); 1296 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1297 EVT WidenEltVT = WidenVT.getVectorElementType(); 1298 EVT VT = WidenVT; 1299 unsigned NumElts = VT.getVectorNumElements(); 1300 while (!TLI.isTypeSynthesizable(VT) && NumElts != 1) { 1301 NumElts = NumElts / 2; 1302 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1303 } 1304 1305 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) { 1306 // Operation doesn't trap so just widen as normal. 1307 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1308 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1309 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2); 1310 } 1311 1312 // No legal vector version so unroll the vector operation and then widen. 1313 if (NumElts == 1) 1314 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()); 1315 1316 // Since the operation can trap, apply operation on the original vector. 1317 EVT MaxVT = VT; 1318 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1319 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1320 unsigned CurNumElts = N->getValueType(0).getVectorNumElements(); 1321 1322 SmallVector<SDValue, 16> ConcatOps(CurNumElts); 1323 unsigned ConcatEnd = 0; // Current ConcatOps index. 1324 int Idx = 0; // Current Idx into input vectors. 1325 1326 // NumElts := greatest synthesizable vector size (at most WidenVT) 1327 // while (orig. vector has unhandled elements) { 1328 // take munches of size NumElts from the beginning and add to ConcatOps 1329 // NumElts := next smaller supported vector size or 1 1330 // } 1331 while (CurNumElts != 0) { 1332 while (CurNumElts >= NumElts) { 1333 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, 1334 DAG.getIntPtrConstant(Idx)); 1335 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, 1336 DAG.getIntPtrConstant(Idx)); 1337 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2); 1338 Idx += NumElts; 1339 CurNumElts -= NumElts; 1340 } 1341 do { 1342 NumElts = NumElts / 2; 1343 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1344 } while (!TLI.isTypeSynthesizable(VT) && NumElts != 1); 1345 1346 if (NumElts == 1) { 1347 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) { 1348 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1349 InOp1, DAG.getIntPtrConstant(Idx)); 1350 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1351 InOp2, DAG.getIntPtrConstant(Idx)); 1352 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT, 1353 EOp1, EOp2); 1354 } 1355 CurNumElts = 0; 1356 } 1357 } 1358 1359 // Check to see if we have a single operation with the widen type. 1360 if (ConcatEnd == 1) { 1361 VT = ConcatOps[0].getValueType(); 1362 if (VT == WidenVT) 1363 return ConcatOps[0]; 1364 } 1365 1366 // while (Some element of ConcatOps is not of type MaxVT) { 1367 // From the end of ConcatOps, collect elements of the same type and put 1368 // them into an op of the next larger supported type 1369 // } 1370 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) { 1371 Idx = ConcatEnd - 1; 1372 VT = ConcatOps[Idx--].getValueType(); 1373 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT) 1374 Idx--; 1375 1376 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1; 1377 EVT NextVT; 1378 do { 1379 NextSize *= 2; 1380 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize); 1381 } while (!TLI.isTypeSynthesizable(NextVT)); 1382 1383 if (!VT.isVector()) { 1384 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT 1385 SDValue VecOp = DAG.getUNDEF(NextVT); 1386 unsigned NumToInsert = ConcatEnd - Idx - 1; 1387 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) { 1388 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, 1389 ConcatOps[OpIdx], DAG.getIntPtrConstant(i)); 1390 } 1391 ConcatOps[Idx+1] = VecOp; 1392 ConcatEnd = Idx + 2; 1393 } else { 1394 // Vector type, create a CONCAT_VECTORS of type NextVT 1395 SDValue undefVec = DAG.getUNDEF(VT); 1396 unsigned OpsToConcat = NextSize/VT.getVectorNumElements(); 1397 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat); 1398 unsigned RealVals = ConcatEnd - Idx - 1; 1399 unsigned SubConcatEnd = 0; 1400 unsigned SubConcatIdx = Idx + 1; 1401 while (SubConcatEnd < RealVals) 1402 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx]; 1403 while (SubConcatEnd < OpsToConcat) 1404 SubConcatOps[SubConcatEnd++] = undefVec; 1405 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1406 NextVT, &SubConcatOps[0], 1407 OpsToConcat); 1408 ConcatEnd = SubConcatIdx + 1; 1409 } 1410 } 1411 1412 // Check to see if we have a single operation with the widen type. 1413 if (ConcatEnd == 1) { 1414 VT = ConcatOps[0].getValueType(); 1415 if (VT == WidenVT) 1416 return ConcatOps[0]; 1417 } 1418 1419 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT 1420 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements(); 1421 if (NumOps != ConcatEnd ) { 1422 SDValue UndefVal = DAG.getUNDEF(MaxVT); 1423 for (unsigned j = ConcatEnd; j < NumOps; ++j) 1424 ConcatOps[j] = UndefVal; 1425 } 1426 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps); 1427} 1428 1429SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { 1430 SDValue InOp = N->getOperand(0); 1431 DebugLoc dl = N->getDebugLoc(); 1432 1433 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1434 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1435 1436 EVT InVT = InOp.getValueType(); 1437 EVT InEltVT = InVT.getVectorElementType(); 1438 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1439 1440 unsigned Opcode = N->getOpcode(); 1441 unsigned InVTNumElts = InVT.getVectorNumElements(); 1442 1443 if (getTypeAction(InVT) == WidenVector) { 1444 InOp = GetWidenedVector(N->getOperand(0)); 1445 InVT = InOp.getValueType(); 1446 InVTNumElts = InVT.getVectorNumElements(); 1447 if (InVTNumElts == WidenNumElts) 1448 return DAG.getNode(Opcode, dl, WidenVT, InOp); 1449 } 1450 1451 if (TLI.isTypeSynthesizable(InWidenVT)) { 1452 // Because the result and the input are different vector types, widening 1453 // the result could create a legal type but widening the input might make 1454 // it an illegal type that might lead to repeatedly splitting the input 1455 // and then widening it. To avoid this, we widen the input only if 1456 // it results in a legal type. 1457 if (WidenNumElts % InVTNumElts == 0) { 1458 // Widen the input and call convert on the widened input vector. 1459 unsigned NumConcat = WidenNumElts/InVTNumElts; 1460 SmallVector<SDValue, 16> Ops(NumConcat); 1461 Ops[0] = InOp; 1462 SDValue UndefVal = DAG.getUNDEF(InVT); 1463 for (unsigned i = 1; i != NumConcat; ++i) 1464 Ops[i] = UndefVal; 1465 return DAG.getNode(Opcode, dl, WidenVT, 1466 DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, 1467 &Ops[0], NumConcat)); 1468 } 1469 1470 if (InVTNumElts % WidenNumElts == 0) { 1471 // Extract the input and convert the shorten input vector. 1472 return DAG.getNode(Opcode, dl, WidenVT, 1473 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, 1474 InOp, DAG.getIntPtrConstant(0))); 1475 } 1476 } 1477 1478 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1479 SmallVector<SDValue, 16> Ops(WidenNumElts); 1480 EVT EltVT = WidenVT.getVectorElementType(); 1481 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1482 unsigned i; 1483 for (i=0; i < MinElts; ++i) 1484 Ops[i] = DAG.getNode(Opcode, dl, EltVT, 1485 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 1486 DAG.getIntPtrConstant(i))); 1487 1488 SDValue UndefVal = DAG.getUNDEF(EltVT); 1489 for (; i < WidenNumElts; ++i) 1490 Ops[i] = UndefVal; 1491 1492 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1493} 1494 1495SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) { 1496 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1497 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1498 SDValue ShOp = N->getOperand(1); 1499 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1500} 1501 1502SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) { 1503 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1504 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1505 SDValue ShOp = N->getOperand(1); 1506 1507 EVT ShVT = ShOp.getValueType(); 1508 if (getTypeAction(ShVT) == WidenVector) { 1509 ShOp = GetWidenedVector(ShOp); 1510 ShVT = ShOp.getValueType(); 1511 } 1512 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(), 1513 ShVT.getVectorElementType(), 1514 WidenVT.getVectorNumElements()); 1515 if (ShVT != ShWidenVT) 1516 ShOp = ModifyToType(ShOp, ShWidenVT); 1517 1518 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1519} 1520 1521SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) { 1522 // Unary op widening. 1523 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1524 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1525 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp); 1526} 1527 1528SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) { 1529 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1530 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), 1531 cast<VTSDNode>(N->getOperand(1))->getVT() 1532 .getVectorElementType(), 1533 WidenVT.getVectorNumElements()); 1534 SDValue WidenLHS = GetWidenedVector(N->getOperand(0)); 1535 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 1536 WidenVT, WidenLHS, DAG.getValueType(ExtVT)); 1537} 1538 1539SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) { 1540 SDValue InOp = N->getOperand(0); 1541 EVT InVT = InOp.getValueType(); 1542 EVT VT = N->getValueType(0); 1543 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1544 DebugLoc dl = N->getDebugLoc(); 1545 1546 switch (getTypeAction(InVT)) { 1547 default: 1548 assert(false && "Unknown type action!"); 1549 break; 1550 case Legal: 1551 break; 1552 case PromoteInteger: 1553 // If the InOp is promoted to the same size, convert it. Otherwise, 1554 // fall out of the switch and widen the promoted input. 1555 InOp = GetPromotedInteger(InOp); 1556 InVT = InOp.getValueType(); 1557 if (WidenVT.bitsEq(InVT)) 1558 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp); 1559 break; 1560 case SoftenFloat: 1561 case ExpandInteger: 1562 case ExpandFloat: 1563 case ScalarizeVector: 1564 case SplitVector: 1565 break; 1566 case WidenVector: 1567 // If the InOp is widened to the same size, convert it. Otherwise, fall 1568 // out of the switch and widen the widened input. 1569 InOp = GetWidenedVector(InOp); 1570 InVT = InOp.getValueType(); 1571 if (WidenVT.bitsEq(InVT)) 1572 // The input widens to the same size. Convert to the widen value. 1573 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp); 1574 break; 1575 } 1576 1577 unsigned WidenSize = WidenVT.getSizeInBits(); 1578 unsigned InSize = InVT.getSizeInBits(); 1579 if (WidenSize % InSize == 0) { 1580 // Determine new input vector type. The new input vector type will use 1581 // the same element type (if its a vector) or use the input type as a 1582 // vector. It is the same size as the type to widen to. 1583 EVT NewInVT; 1584 unsigned NewNumElts = WidenSize / InSize; 1585 if (InVT.isVector()) { 1586 EVT InEltVT = InVT.getVectorElementType(); 1587 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, 1588 WidenSize / InEltVT.getSizeInBits()); 1589 } else { 1590 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts); 1591 } 1592 1593 if (TLI.isTypeSynthesizable(NewInVT)) { 1594 // Because the result and the input are different vector types, widening 1595 // the result could create a legal type but widening the input might make 1596 // it an illegal type that might lead to repeatedly splitting the input 1597 // and then widening it. To avoid this, we widen the input only if 1598 // it results in a legal type. 1599 SmallVector<SDValue, 16> Ops(NewNumElts); 1600 SDValue UndefVal = DAG.getUNDEF(InVT); 1601 Ops[0] = InOp; 1602 for (unsigned i = 1; i < NewNumElts; ++i) 1603 Ops[i] = UndefVal; 1604 1605 SDValue NewVec; 1606 if (InVT.isVector()) 1607 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1608 NewInVT, &Ops[0], NewNumElts); 1609 else 1610 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, 1611 NewInVT, &Ops[0], NewNumElts); 1612 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, NewVec); 1613 } 1614 } 1615 1616 return CreateStackStoreLoad(InOp, WidenVT); 1617} 1618 1619SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) { 1620 DebugLoc dl = N->getDebugLoc(); 1621 // Build a vector with undefined for the new nodes. 1622 EVT VT = N->getValueType(0); 1623 EVT EltVT = VT.getVectorElementType(); 1624 unsigned NumElts = VT.getVectorNumElements(); 1625 1626 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1627 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1628 1629 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end()); 1630 NewOps.reserve(WidenNumElts); 1631 for (unsigned i = NumElts; i < WidenNumElts; ++i) 1632 NewOps.push_back(DAG.getUNDEF(EltVT)); 1633 1634 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size()); 1635} 1636 1637SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) { 1638 EVT InVT = N->getOperand(0).getValueType(); 1639 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1640 DebugLoc dl = N->getDebugLoc(); 1641 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1642 unsigned NumOperands = N->getNumOperands(); 1643 1644 bool InputWidened = false; // Indicates we need to widen the input. 1645 if (getTypeAction(InVT) != WidenVector) { 1646 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) { 1647 // Add undef vectors to widen to correct length. 1648 unsigned NumConcat = WidenVT.getVectorNumElements() / 1649 InVT.getVectorNumElements(); 1650 SDValue UndefVal = DAG.getUNDEF(InVT); 1651 SmallVector<SDValue, 16> Ops(NumConcat); 1652 for (unsigned i=0; i < NumOperands; ++i) 1653 Ops[i] = N->getOperand(i); 1654 for (unsigned i = NumOperands; i != NumConcat; ++i) 1655 Ops[i] = UndefVal; 1656 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat); 1657 } 1658 } else { 1659 InputWidened = true; 1660 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) { 1661 // The inputs and the result are widen to the same value. 1662 unsigned i; 1663 for (i=1; i < NumOperands; ++i) 1664 if (N->getOperand(i).getOpcode() != ISD::UNDEF) 1665 break; 1666 1667 if (i > NumOperands) 1668 // Everything but the first operand is an UNDEF so just return the 1669 // widened first operand. 1670 return GetWidenedVector(N->getOperand(0)); 1671 1672 if (NumOperands == 2) { 1673 // Replace concat of two operands with a shuffle. 1674 SmallVector<int, 16> MaskOps(WidenNumElts); 1675 for (unsigned i=0; i < WidenNumElts/2; ++i) { 1676 MaskOps[i] = i; 1677 MaskOps[i+WidenNumElts/2] = i+WidenNumElts; 1678 } 1679 return DAG.getVectorShuffle(WidenVT, dl, 1680 GetWidenedVector(N->getOperand(0)), 1681 GetWidenedVector(N->getOperand(1)), 1682 &MaskOps[0]); 1683 } 1684 } 1685 } 1686 1687 // Fall back to use extracts and build vector. 1688 EVT EltVT = WidenVT.getVectorElementType(); 1689 unsigned NumInElts = InVT.getVectorNumElements(); 1690 SmallVector<SDValue, 16> Ops(WidenNumElts); 1691 unsigned Idx = 0; 1692 for (unsigned i=0; i < NumOperands; ++i) { 1693 SDValue InOp = N->getOperand(i); 1694 if (InputWidened) 1695 InOp = GetWidenedVector(InOp); 1696 for (unsigned j=0; j < NumInElts; ++j) 1697 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1698 DAG.getIntPtrConstant(j)); 1699 } 1700 SDValue UndefVal = DAG.getUNDEF(EltVT); 1701 for (; Idx < WidenNumElts; ++Idx) 1702 Ops[Idx] = UndefVal; 1703 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1704} 1705 1706SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { 1707 DebugLoc dl = N->getDebugLoc(); 1708 SDValue InOp = N->getOperand(0); 1709 SDValue RndOp = N->getOperand(3); 1710 SDValue SatOp = N->getOperand(4); 1711 1712 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1713 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1714 1715 EVT InVT = InOp.getValueType(); 1716 EVT InEltVT = InVT.getVectorElementType(); 1717 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1718 1719 SDValue DTyOp = DAG.getValueType(WidenVT); 1720 SDValue STyOp = DAG.getValueType(InWidenVT); 1721 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 1722 1723 unsigned InVTNumElts = InVT.getVectorNumElements(); 1724 if (getTypeAction(InVT) == WidenVector) { 1725 InOp = GetWidenedVector(InOp); 1726 InVT = InOp.getValueType(); 1727 InVTNumElts = InVT.getVectorNumElements(); 1728 if (InVTNumElts == WidenNumElts) 1729 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1730 SatOp, CvtCode); 1731 } 1732 1733 if (TLI.isTypeSynthesizable(InWidenVT)) { 1734 // Because the result and the input are different vector types, widening 1735 // the result could create a legal type but widening the input might make 1736 // it an illegal type that might lead to repeatedly splitting the input 1737 // and then widening it. To avoid this, we widen the input only if 1738 // it results in a legal type. 1739 if (WidenNumElts % InVTNumElts == 0) { 1740 // Widen the input and call convert on the widened input vector. 1741 unsigned NumConcat = WidenNumElts/InVTNumElts; 1742 SmallVector<SDValue, 16> Ops(NumConcat); 1743 Ops[0] = InOp; 1744 SDValue UndefVal = DAG.getUNDEF(InVT); 1745 for (unsigned i = 1; i != NumConcat; ++i) 1746 Ops[i] = UndefVal; 1747 1748 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat); 1749 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1750 SatOp, CvtCode); 1751 } 1752 1753 if (InVTNumElts % WidenNumElts == 0) { 1754 // Extract the input and convert the shorten input vector. 1755 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp, 1756 DAG.getIntPtrConstant(0)); 1757 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1758 SatOp, CvtCode); 1759 } 1760 } 1761 1762 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1763 SmallVector<SDValue, 16> Ops(WidenNumElts); 1764 EVT EltVT = WidenVT.getVectorElementType(); 1765 DTyOp = DAG.getValueType(EltVT); 1766 STyOp = DAG.getValueType(InEltVT); 1767 1768 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1769 unsigned i; 1770 for (i=0; i < MinElts; ++i) { 1771 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 1772 DAG.getIntPtrConstant(i)); 1773 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp, 1774 SatOp, CvtCode); 1775 } 1776 1777 SDValue UndefVal = DAG.getUNDEF(EltVT); 1778 for (; i < WidenNumElts; ++i) 1779 Ops[i] = UndefVal; 1780 1781 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1782} 1783 1784SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 1785 EVT VT = N->getValueType(0); 1786 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1787 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1788 SDValue InOp = N->getOperand(0); 1789 SDValue Idx = N->getOperand(1); 1790 DebugLoc dl = N->getDebugLoc(); 1791 1792 if (getTypeAction(InOp.getValueType()) == WidenVector) 1793 InOp = GetWidenedVector(InOp); 1794 1795 EVT InVT = InOp.getValueType(); 1796 1797 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx); 1798 if (CIdx) { 1799 unsigned IdxVal = CIdx->getZExtValue(); 1800 // Check if we can just return the input vector after widening. 1801 if (IdxVal == 0 && InVT == WidenVT) 1802 return InOp; 1803 1804 // Check if we can extract from the vector. 1805 unsigned InNumElts = InVT.getVectorNumElements(); 1806 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts) 1807 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx); 1808 } 1809 1810 // We could try widening the input to the right length but for now, extract 1811 // the original elements, fill the rest with undefs and build a vector. 1812 SmallVector<SDValue, 16> Ops(WidenNumElts); 1813 EVT EltVT = VT.getVectorElementType(); 1814 EVT IdxVT = Idx.getValueType(); 1815 unsigned NumElts = VT.getVectorNumElements(); 1816 unsigned i; 1817 if (CIdx) { 1818 unsigned IdxVal = CIdx->getZExtValue(); 1819 for (i=0; i < NumElts; ++i) 1820 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1821 DAG.getConstant(IdxVal+i, IdxVT)); 1822 } else { 1823 Ops[0] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, Idx); 1824 for (i=1; i < NumElts; ++i) { 1825 SDValue NewIdx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, 1826 DAG.getConstant(i, IdxVT)); 1827 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, NewIdx); 1828 } 1829 } 1830 1831 SDValue UndefVal = DAG.getUNDEF(EltVT); 1832 for (; i < WidenNumElts; ++i) 1833 Ops[i] = UndefVal; 1834 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1835} 1836 1837SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) { 1838 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1839 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(), 1840 InOp.getValueType(), InOp, 1841 N->getOperand(1), N->getOperand(2)); 1842} 1843 1844SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) { 1845 LoadSDNode *LD = cast<LoadSDNode>(N); 1846 ISD::LoadExtType ExtType = LD->getExtensionType(); 1847 1848 SDValue Result; 1849 SmallVector<SDValue, 16> LdChain; // Chain for the series of load 1850 if (ExtType != ISD::NON_EXTLOAD) 1851 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); 1852 else 1853 Result = GenWidenVectorLoads(LdChain, LD); 1854 1855 // If we generate a single load, we can use that for the chain. Otherwise, 1856 // build a factor node to remember the multiple loads are independent and 1857 // chain to that. 1858 SDValue NewChain; 1859 if (LdChain.size() == 1) 1860 NewChain = LdChain[0]; 1861 else 1862 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other, 1863 &LdChain[0], LdChain.size()); 1864 1865 // Modified the chain - switch anything that used the old chain to use 1866 // the new one. 1867 ReplaceValueWith(SDValue(N, 1), NewChain); 1868 1869 return Result; 1870} 1871 1872SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) { 1873 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1874 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(), 1875 WidenVT, N->getOperand(0)); 1876} 1877 1878SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) { 1879 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1880 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1881 1882 SDValue Cond1 = N->getOperand(0); 1883 EVT CondVT = Cond1.getValueType(); 1884 if (CondVT.isVector()) { 1885 EVT CondEltVT = CondVT.getVectorElementType(); 1886 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), 1887 CondEltVT, WidenNumElts); 1888 if (getTypeAction(CondVT) == WidenVector) 1889 Cond1 = GetWidenedVector(Cond1); 1890 1891 if (Cond1.getValueType() != CondWidenVT) 1892 Cond1 = ModifyToType(Cond1, CondWidenVT); 1893 } 1894 1895 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 1896 SDValue InOp2 = GetWidenedVector(N->getOperand(2)); 1897 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT); 1898 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 1899 WidenVT, Cond1, InOp1, InOp2); 1900} 1901 1902SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) { 1903 SDValue InOp1 = GetWidenedVector(N->getOperand(2)); 1904 SDValue InOp2 = GetWidenedVector(N->getOperand(3)); 1905 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 1906 InOp1.getValueType(), N->getOperand(0), 1907 N->getOperand(1), InOp1, InOp2, N->getOperand(4)); 1908} 1909 1910SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) { 1911 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1912 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1913 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1914 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT, 1915 InOp1, InOp2, N->getOperand(2)); 1916} 1917 1918SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) { 1919 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1920 return DAG.getUNDEF(WidenVT); 1921} 1922 1923SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) { 1924 EVT VT = N->getValueType(0); 1925 DebugLoc dl = N->getDebugLoc(); 1926 1927 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1928 unsigned NumElts = VT.getVectorNumElements(); 1929 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1930 1931 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1932 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1933 1934 // Adjust mask based on new input vector length. 1935 SmallVector<int, 16> NewMask; 1936 for (unsigned i = 0; i != NumElts; ++i) { 1937 int Idx = N->getMaskElt(i); 1938 if (Idx < (int)NumElts) 1939 NewMask.push_back(Idx); 1940 else 1941 NewMask.push_back(Idx - NumElts + WidenNumElts); 1942 } 1943 for (unsigned i = NumElts; i != WidenNumElts; ++i) 1944 NewMask.push_back(-1); 1945 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]); 1946} 1947 1948SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) { 1949 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1950 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1951 1952 SDValue InOp1 = N->getOperand(0); 1953 EVT InVT = InOp1.getValueType(); 1954 assert(InVT.isVector() && "can not widen non vector type"); 1955 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(), 1956 InVT.getVectorElementType(), WidenNumElts); 1957 InOp1 = GetWidenedVector(InOp1); 1958 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1959 1960 // Assume that the input and output will be widen appropriately. If not, 1961 // we will have to unroll it at some point. 1962 assert(InOp1.getValueType() == WidenInVT && 1963 InOp2.getValueType() == WidenInVT && 1964 "Input not widened to expected type!"); 1965 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(), 1966 WidenVT, InOp1, InOp2, N->getOperand(2)); 1967} 1968 1969 1970//===----------------------------------------------------------------------===// 1971// Widen Vector Operand 1972//===----------------------------------------------------------------------===// 1973bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) { 1974 DEBUG(dbgs() << "Widen node operand " << ResNo << ": "; 1975 N->dump(&DAG); 1976 dbgs() << "\n"); 1977 SDValue Res = SDValue(); 1978 1979 switch (N->getOpcode()) { 1980 default: 1981#ifndef NDEBUG 1982 dbgs() << "WidenVectorOperand op #" << ResNo << ": "; 1983 N->dump(&DAG); 1984 dbgs() << "\n"; 1985#endif 1986 llvm_unreachable("Do not know how to widen this operator's operand!"); 1987 1988 case ISD::BIT_CONVERT: Res = WidenVecOp_BIT_CONVERT(N); break; 1989 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break; 1990 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break; 1991 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break; 1992 case ISD::STORE: Res = WidenVecOp_STORE(N); break; 1993 1994 case ISD::FP_ROUND: 1995 case ISD::FP_TO_SINT: 1996 case ISD::FP_TO_UINT: 1997 case ISD::SINT_TO_FP: 1998 case ISD::UINT_TO_FP: 1999 case ISD::TRUNCATE: 2000 case ISD::SIGN_EXTEND: 2001 case ISD::ZERO_EXTEND: 2002 case ISD::ANY_EXTEND: 2003 Res = WidenVecOp_Convert(N); 2004 break; 2005 } 2006 2007 // If Res is null, the sub-method took care of registering the result. 2008 if (!Res.getNode()) return false; 2009 2010 // If the result is N, the sub-method updated N in place. Tell the legalizer 2011 // core about this. 2012 if (Res.getNode() == N) 2013 return true; 2014 2015 2016 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2017 "Invalid operand expansion"); 2018 2019 ReplaceValueWith(SDValue(N, 0), Res); 2020 return false; 2021} 2022 2023SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) { 2024 // Since the result is legal and the input is illegal, it is unlikely 2025 // that we can fix the input to a legal type so unroll the convert 2026 // into some scalar code and create a nasty build vector. 2027 EVT VT = N->getValueType(0); 2028 EVT EltVT = VT.getVectorElementType(); 2029 DebugLoc dl = N->getDebugLoc(); 2030 unsigned NumElts = VT.getVectorNumElements(); 2031 SDValue InOp = N->getOperand(0); 2032 if (getTypeAction(InOp.getValueType()) == WidenVector) 2033 InOp = GetWidenedVector(InOp); 2034 EVT InVT = InOp.getValueType(); 2035 EVT InEltVT = InVT.getVectorElementType(); 2036 2037 unsigned Opcode = N->getOpcode(); 2038 SmallVector<SDValue, 16> Ops(NumElts); 2039 for (unsigned i=0; i < NumElts; ++i) 2040 Ops[i] = DAG.getNode(Opcode, dl, EltVT, 2041 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 2042 DAG.getIntPtrConstant(i))); 2043 2044 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2045} 2046 2047SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) { 2048 EVT VT = N->getValueType(0); 2049 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2050 EVT InWidenVT = InOp.getValueType(); 2051 DebugLoc dl = N->getDebugLoc(); 2052 2053 // Check if we can convert between two legal vector types and extract. 2054 unsigned InWidenSize = InWidenVT.getSizeInBits(); 2055 unsigned Size = VT.getSizeInBits(); 2056 if (InWidenSize % Size == 0 && !VT.isVector()) { 2057 unsigned NewNumElts = InWidenSize / Size; 2058 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); 2059 if (TLI.isTypeSynthesizable(NewVT)) { 2060 SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp); 2061 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, 2062 DAG.getIntPtrConstant(0)); 2063 } 2064 } 2065 2066 return CreateStackStoreLoad(InOp, VT); 2067} 2068 2069SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) { 2070 // If the input vector is not legal, it is likely that we will not find a 2071 // legal vector of the same size. Replace the concatenate vector with a 2072 // nasty build vector. 2073 EVT VT = N->getValueType(0); 2074 EVT EltVT = VT.getVectorElementType(); 2075 DebugLoc dl = N->getDebugLoc(); 2076 unsigned NumElts = VT.getVectorNumElements(); 2077 SmallVector<SDValue, 16> Ops(NumElts); 2078 2079 EVT InVT = N->getOperand(0).getValueType(); 2080 unsigned NumInElts = InVT.getVectorNumElements(); 2081 2082 unsigned Idx = 0; 2083 unsigned NumOperands = N->getNumOperands(); 2084 for (unsigned i=0; i < NumOperands; ++i) { 2085 SDValue InOp = N->getOperand(i); 2086 if (getTypeAction(InOp.getValueType()) == WidenVector) 2087 InOp = GetWidenedVector(InOp); 2088 for (unsigned j=0; j < NumInElts; ++j) 2089 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2090 DAG.getIntPtrConstant(j)); 2091 } 2092 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2093} 2094 2095SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 2096 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2097 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), 2098 N->getValueType(0), InOp, N->getOperand(1)); 2099} 2100 2101SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 2102 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2103 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 2104 N->getValueType(0), InOp, N->getOperand(1)); 2105} 2106 2107SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) { 2108 // We have to widen the value but we want only to store the original 2109 // vector type. 2110 StoreSDNode *ST = cast<StoreSDNode>(N); 2111 2112 SmallVector<SDValue, 16> StChain; 2113 if (ST->isTruncatingStore()) 2114 GenWidenVectorTruncStores(StChain, ST); 2115 else 2116 GenWidenVectorStores(StChain, ST); 2117 2118 if (StChain.size() == 1) 2119 return StChain[0]; 2120 else 2121 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(), 2122 MVT::Other,&StChain[0],StChain.size()); 2123} 2124 2125//===----------------------------------------------------------------------===// 2126// Vector Widening Utilities 2127//===----------------------------------------------------------------------===// 2128 2129// Utility function to find the type to chop up a widen vector for load/store 2130// TLI: Target lowering used to determine legal types. 2131// Width: Width left need to load/store. 2132// WidenVT: The widen vector type to load to/store from 2133// Align: If 0, don't allow use of a wider type 2134// WidenEx: If Align is not 0, the amount additional we can load/store from. 2135 2136static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, 2137 unsigned Width, EVT WidenVT, 2138 unsigned Align = 0, unsigned WidenEx = 0) { 2139 EVT WidenEltVT = WidenVT.getVectorElementType(); 2140 unsigned WidenWidth = WidenVT.getSizeInBits(); 2141 unsigned WidenEltWidth = WidenEltVT.getSizeInBits(); 2142 unsigned AlignInBits = Align*8; 2143 2144 // If we have one element to load/store, return it. 2145 EVT RetVT = WidenEltVT; 2146 if (Width == WidenEltWidth) 2147 return RetVT; 2148 2149 // See if there is larger legal integer than the element type to load/store 2150 unsigned VT; 2151 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE; 2152 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) { 2153 EVT MemVT((MVT::SimpleValueType) VT); 2154 unsigned MemVTWidth = MemVT.getSizeInBits(); 2155 if (MemVT.getSizeInBits() <= WidenEltWidth) 2156 break; 2157 if (TLI.isTypeSynthesizable(MemVT) && (WidenWidth % MemVTWidth) == 0 && 2158 (MemVTWidth <= Width || 2159 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2160 RetVT = MemVT; 2161 break; 2162 } 2163 } 2164 2165 // See if there is a larger vector type to load/store that has the same vector 2166 // element type and is evenly divisible with the WidenVT. 2167 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; 2168 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) { 2169 EVT MemVT = (MVT::SimpleValueType) VT; 2170 unsigned MemVTWidth = MemVT.getSizeInBits(); 2171 if (TLI.isTypeSynthesizable(MemVT) && WidenEltVT == MemVT.getVectorElementType() && 2172 (WidenWidth % MemVTWidth) == 0 && 2173 (MemVTWidth <= Width || 2174 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2175 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT) 2176 return MemVT; 2177 } 2178 } 2179 2180 return RetVT; 2181} 2182 2183// Builds a vector type from scalar loads 2184// VecTy: Resulting Vector type 2185// LDOps: Load operators to build a vector type 2186// [Start,End) the list of loads to use. 2187static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, 2188 SmallVector<SDValue, 16>& LdOps, 2189 unsigned Start, unsigned End) { 2190 DebugLoc dl = LdOps[Start].getDebugLoc(); 2191 EVT LdTy = LdOps[Start].getValueType(); 2192 unsigned Width = VecTy.getSizeInBits(); 2193 unsigned NumElts = Width / LdTy.getSizeInBits(); 2194 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts); 2195 2196 unsigned Idx = 1; 2197 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]); 2198 2199 for (unsigned i = Start + 1; i != End; ++i) { 2200 EVT NewLdTy = LdOps[i].getValueType(); 2201 if (NewLdTy != LdTy) { 2202 NumElts = Width / NewLdTy.getSizeInBits(); 2203 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts); 2204 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp); 2205 // Readjust position and vector position based on new load type 2206 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits(); 2207 LdTy = NewLdTy; 2208 } 2209 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], 2210 DAG.getIntPtrConstant(Idx++)); 2211 } 2212 return DAG.getNode(ISD::BIT_CONVERT, dl, VecTy, VecOp); 2213} 2214 2215SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain, 2216 LoadSDNode *LD) { 2217 // The strategy assumes that we can efficiently load powers of two widths. 2218 // The routines chops the vector into the largest vector loads with the same 2219 // element type or scalar loads and then recombines it to the widen vector 2220 // type. 2221 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2222 unsigned WidenWidth = WidenVT.getSizeInBits(); 2223 EVT LdVT = LD->getMemoryVT(); 2224 DebugLoc dl = LD->getDebugLoc(); 2225 assert(LdVT.isVector() && WidenVT.isVector()); 2226 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType()); 2227 2228 // Load information 2229 SDValue Chain = LD->getChain(); 2230 SDValue BasePtr = LD->getBasePtr(); 2231 unsigned Align = LD->getAlignment(); 2232 bool isVolatile = LD->isVolatile(); 2233 bool isNonTemporal = LD->isNonTemporal(); 2234 2235 int LdWidth = LdVT.getSizeInBits(); 2236 int WidthDiff = WidenWidth - LdWidth; // Difference 2237 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads 2238 2239 // Find the vector type that can load from. 2240 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2241 int NewVTWidth = NewVT.getSizeInBits(); 2242 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(), 2243 isVolatile, isNonTemporal, Align); 2244 LdChain.push_back(LdOp.getValue(1)); 2245 2246 // Check if we can load the element with one instruction 2247 if (LdWidth <= NewVTWidth) { 2248 if (!NewVT.isVector()) { 2249 unsigned NumElts = WidenWidth / NewVTWidth; 2250 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2251 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp); 2252 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, VecOp); 2253 } 2254 if (NewVT == WidenVT) 2255 return LdOp; 2256 2257 assert(WidenWidth % NewVTWidth == 0); 2258 unsigned NumConcat = WidenWidth / NewVTWidth; 2259 SmallVector<SDValue, 16> ConcatOps(NumConcat); 2260 SDValue UndefVal = DAG.getUNDEF(NewVT); 2261 ConcatOps[0] = LdOp; 2262 for (unsigned i = 1; i != NumConcat; ++i) 2263 ConcatOps[i] = UndefVal; 2264 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], 2265 NumConcat); 2266 } 2267 2268 // Load vector by using multiple loads from largest vector to scalar 2269 SmallVector<SDValue, 16> LdOps; 2270 LdOps.push_back(LdOp); 2271 2272 LdWidth -= NewVTWidth; 2273 unsigned Offset = 0; 2274 2275 while (LdWidth > 0) { 2276 unsigned Increment = NewVTWidth / 8; 2277 Offset += Increment; 2278 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2279 DAG.getIntPtrConstant(Increment)); 2280 2281 if (LdWidth < NewVTWidth) { 2282 // Our current type we are using is too large, find a better size 2283 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2284 NewVTWidth = NewVT.getSizeInBits(); 2285 } 2286 2287 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, 2288 LD->getPointerInfo().getWithOffset(Offset), 2289 isVolatile, 2290 isNonTemporal, MinAlign(Align, Increment)); 2291 LdChain.push_back(LdOp.getValue(1)); 2292 LdOps.push_back(LdOp); 2293 2294 LdWidth -= NewVTWidth; 2295 } 2296 2297 // Build the vector from the loads operations 2298 unsigned End = LdOps.size(); 2299 if (!LdOps[0].getValueType().isVector()) 2300 // All the loads are scalar loads. 2301 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End); 2302 2303 // If the load contains vectors, build the vector using concat vector. 2304 // All of the vectors used to loads are power of 2 and the scalars load 2305 // can be combined to make a power of 2 vector. 2306 SmallVector<SDValue, 16> ConcatOps(End); 2307 int i = End - 1; 2308 int Idx = End; 2309 EVT LdTy = LdOps[i].getValueType(); 2310 // First combine the scalar loads to a vector 2311 if (!LdTy.isVector()) { 2312 for (--i; i >= 0; --i) { 2313 LdTy = LdOps[i].getValueType(); 2314 if (LdTy.isVector()) 2315 break; 2316 } 2317 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End); 2318 } 2319 ConcatOps[--Idx] = LdOps[i]; 2320 for (--i; i >= 0; --i) { 2321 EVT NewLdTy = LdOps[i].getValueType(); 2322 if (NewLdTy != LdTy) { 2323 // Create a larger vector 2324 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy, 2325 &ConcatOps[Idx], End - Idx); 2326 Idx = End - 1; 2327 LdTy = NewLdTy; 2328 } 2329 ConcatOps[--Idx] = LdOps[i]; 2330 } 2331 2332 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx)) 2333 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, 2334 &ConcatOps[Idx], End - Idx); 2335 2336 // We need to fill the rest with undefs to build the vector 2337 unsigned NumOps = WidenWidth / LdTy.getSizeInBits(); 2338 SmallVector<SDValue, 16> WidenOps(NumOps); 2339 SDValue UndefVal = DAG.getUNDEF(LdTy); 2340 { 2341 unsigned i = 0; 2342 for (; i != End-Idx; ++i) 2343 WidenOps[i] = ConcatOps[Idx+i]; 2344 for (; i != NumOps; ++i) 2345 WidenOps[i] = UndefVal; 2346 } 2347 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps); 2348} 2349 2350SDValue 2351DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain, 2352 LoadSDNode * LD, 2353 ISD::LoadExtType ExtType) { 2354 // For extension loads, it may not be more efficient to chop up the vector 2355 // and then extended it. Instead, we unroll the load and build a new vector. 2356 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2357 EVT LdVT = LD->getMemoryVT(); 2358 DebugLoc dl = LD->getDebugLoc(); 2359 assert(LdVT.isVector() && WidenVT.isVector()); 2360 2361 // Load information 2362 SDValue Chain = LD->getChain(); 2363 SDValue BasePtr = LD->getBasePtr(); 2364 int SVOffset = LD->getSrcValueOffset(); 2365 unsigned Align = LD->getAlignment(); 2366 bool isVolatile = LD->isVolatile(); 2367 bool isNonTemporal = LD->isNonTemporal(); 2368 const Value *SV = LD->getSrcValue(); 2369 2370 EVT EltVT = WidenVT.getVectorElementType(); 2371 EVT LdEltVT = LdVT.getVectorElementType(); 2372 unsigned NumElts = LdVT.getVectorNumElements(); 2373 2374 // Load each element and widen 2375 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2376 SmallVector<SDValue, 16> Ops(WidenNumElts); 2377 unsigned Increment = LdEltVT.getSizeInBits() / 8; 2378 Ops[0] = DAG.getExtLoad(ExtType, EltVT, dl, Chain, BasePtr, SV, SVOffset, 2379 LdEltVT, isVolatile, isNonTemporal, Align); 2380 LdChain.push_back(Ops[0].getValue(1)); 2381 unsigned i = 0, Offset = Increment; 2382 for (i=1; i < NumElts; ++i, Offset += Increment) { 2383 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2384 BasePtr, DAG.getIntPtrConstant(Offset)); 2385 Ops[i] = DAG.getExtLoad(ExtType, EltVT, dl, Chain, NewBasePtr, SV, 2386 SVOffset + Offset, LdEltVT, isVolatile, 2387 isNonTemporal, Align); 2388 LdChain.push_back(Ops[i].getValue(1)); 2389 } 2390 2391 // Fill the rest with undefs 2392 SDValue UndefVal = DAG.getUNDEF(EltVT); 2393 for (; i != WidenNumElts; ++i) 2394 Ops[i] = UndefVal; 2395 2396 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size()); 2397} 2398 2399 2400void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, 2401 StoreSDNode *ST) { 2402 // The strategy assumes that we can efficiently store powers of two widths. 2403 // The routines chops the vector into the largest vector stores with the same 2404 // element type or scalar stores. 2405 SDValue Chain = ST->getChain(); 2406 SDValue BasePtr = ST->getBasePtr(); 2407 const Value *SV = ST->getSrcValue(); 2408 int SVOffset = ST->getSrcValueOffset(); 2409 unsigned Align = ST->getAlignment(); 2410 bool isVolatile = ST->isVolatile(); 2411 bool isNonTemporal = ST->isNonTemporal(); 2412 SDValue ValOp = GetWidenedVector(ST->getValue()); 2413 DebugLoc dl = ST->getDebugLoc(); 2414 2415 EVT StVT = ST->getMemoryVT(); 2416 unsigned StWidth = StVT.getSizeInBits(); 2417 EVT ValVT = ValOp.getValueType(); 2418 unsigned ValWidth = ValVT.getSizeInBits(); 2419 EVT ValEltVT = ValVT.getVectorElementType(); 2420 unsigned ValEltWidth = ValEltVT.getSizeInBits(); 2421 assert(StVT.getVectorElementType() == ValEltVT); 2422 2423 int Idx = 0; // current index to store 2424 unsigned Offset = 0; // offset from base to store 2425 while (StWidth != 0) { 2426 // Find the largest vector type we can store with 2427 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT); 2428 unsigned NewVTWidth = NewVT.getSizeInBits(); 2429 unsigned Increment = NewVTWidth / 8; 2430 if (NewVT.isVector()) { 2431 unsigned NumVTElts = NewVT.getVectorNumElements(); 2432 do { 2433 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, 2434 DAG.getIntPtrConstant(Idx)); 2435 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV, 2436 SVOffset + Offset, isVolatile, 2437 isNonTemporal, 2438 MinAlign(Align, Offset))); 2439 StWidth -= NewVTWidth; 2440 Offset += Increment; 2441 Idx += NumVTElts; 2442 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2443 DAG.getIntPtrConstant(Increment)); 2444 } while (StWidth != 0 && StWidth >= NewVTWidth); 2445 } else { 2446 // Cast the vector to the scalar type we can store 2447 unsigned NumElts = ValWidth / NewVTWidth; 2448 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2449 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, ValOp); 2450 // Readjust index position based on new vector type 2451 Idx = Idx * ValEltWidth / NewVTWidth; 2452 do { 2453 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp, 2454 DAG.getIntPtrConstant(Idx++)); 2455 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV, 2456 SVOffset + Offset, isVolatile, 2457 isNonTemporal, MinAlign(Align, Offset))); 2458 StWidth -= NewVTWidth; 2459 Offset += Increment; 2460 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2461 DAG.getIntPtrConstant(Increment)); 2462 } while (StWidth != 0 && StWidth >= NewVTWidth); 2463 // Restore index back to be relative to the original widen element type 2464 Idx = Idx * NewVTWidth / ValEltWidth; 2465 } 2466 } 2467} 2468 2469void 2470DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain, 2471 StoreSDNode *ST) { 2472 // For extension loads, it may not be more efficient to truncate the vector 2473 // and then store it. Instead, we extract each element and then store it. 2474 SDValue Chain = ST->getChain(); 2475 SDValue BasePtr = ST->getBasePtr(); 2476 const Value *SV = ST->getSrcValue(); 2477 int SVOffset = ST->getSrcValueOffset(); 2478 unsigned Align = ST->getAlignment(); 2479 bool isVolatile = ST->isVolatile(); 2480 bool isNonTemporal = ST->isNonTemporal(); 2481 SDValue ValOp = GetWidenedVector(ST->getValue()); 2482 DebugLoc dl = ST->getDebugLoc(); 2483 2484 EVT StVT = ST->getMemoryVT(); 2485 EVT ValVT = ValOp.getValueType(); 2486 2487 // It must be true that we the widen vector type is bigger than where 2488 // we need to store. 2489 assert(StVT.isVector() && ValOp.getValueType().isVector()); 2490 assert(StVT.bitsLT(ValOp.getValueType())); 2491 2492 // For truncating stores, we can not play the tricks of chopping legal 2493 // vector types and bit cast it to the right type. Instead, we unroll 2494 // the store. 2495 EVT StEltVT = StVT.getVectorElementType(); 2496 EVT ValEltVT = ValVT.getVectorElementType(); 2497 unsigned Increment = ValEltVT.getSizeInBits() / 8; 2498 unsigned NumElts = StVT.getVectorNumElements(); 2499 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2500 DAG.getIntPtrConstant(0)); 2501 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, SV, 2502 SVOffset, StEltVT, 2503 isVolatile, isNonTemporal, Align)); 2504 unsigned Offset = Increment; 2505 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) { 2506 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2507 BasePtr, DAG.getIntPtrConstant(Offset)); 2508 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2509 DAG.getIntPtrConstant(0)); 2510 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, SV, 2511 SVOffset + Offset, StEltVT, 2512 isVolatile, isNonTemporal, 2513 MinAlign(Align, Offset))); 2514 } 2515} 2516 2517/// Modifies a vector input (widen or narrows) to a vector of NVT. The 2518/// input vector must have the same element type as NVT. 2519SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) { 2520 // Note that InOp might have been widened so it might already have 2521 // the right width or it might need be narrowed. 2522 EVT InVT = InOp.getValueType(); 2523 assert(InVT.getVectorElementType() == NVT.getVectorElementType() && 2524 "input and widen element type must match"); 2525 DebugLoc dl = InOp.getDebugLoc(); 2526 2527 // Check if InOp already has the right width. 2528 if (InVT == NVT) 2529 return InOp; 2530 2531 unsigned InNumElts = InVT.getVectorNumElements(); 2532 unsigned WidenNumElts = NVT.getVectorNumElements(); 2533 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) { 2534 unsigned NumConcat = WidenNumElts / InNumElts; 2535 SmallVector<SDValue, 16> Ops(NumConcat); 2536 SDValue UndefVal = DAG.getUNDEF(InVT); 2537 Ops[0] = InOp; 2538 for (unsigned i = 1; i != NumConcat; ++i) 2539 Ops[i] = UndefVal; 2540 2541 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat); 2542 } 2543 2544 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts) 2545 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp, 2546 DAG.getIntPtrConstant(0)); 2547 2548 // Fall back to extract and build. 2549 SmallVector<SDValue, 16> Ops(WidenNumElts); 2550 EVT EltVT = NVT.getVectorElementType(); 2551 unsigned MinNumElts = std::min(WidenNumElts, InNumElts); 2552 unsigned Idx; 2553 for (Idx = 0; Idx < MinNumElts; ++Idx) 2554 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2555 DAG.getIntPtrConstant(Idx)); 2556 2557 SDValue UndefVal = DAG.getUNDEF(EltVT); 2558 for ( ; Idx < WidenNumElts; ++Idx) 2559 Ops[Idx] = UndefVal; 2560 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts); 2561} 2562