ScheduleDAGSDNodes.cpp revision 0b299309c54a51e8a7eef7e807f71749863ebebb 
1//===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the ScheduleDAG class, which is a base class used by
11// scheduling implementation classes.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "pre-RA-sched"
16#include "llvm/CodeGen/ScheduleDAGSDNodes.h"
17#include "llvm/CodeGen/SelectionDAG.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/raw_ostream.h"
23using namespace llvm;
24
25ScheduleDAGSDNodes::ScheduleDAGSDNodes(SelectionDAG *dag, MachineBasicBlock *bb,
26                                       const TargetMachine &tm)
27  : ScheduleDAG(dag, bb, tm) {
28}
29
30SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
31  SUnit *SU = NewSUnit(Old->getNode());
32  SU->OrigNode = Old->OrigNode;
33  SU->Latency = Old->Latency;
34  SU->isTwoAddress = Old->isTwoAddress;
35  SU->isCommutable = Old->isCommutable;
36  SU->hasPhysRegDefs = Old->hasPhysRegDefs;
37  return SU;
38}
39
40/// CheckForPhysRegDependency - Check if the dependency between def and use of
41/// a specified operand is a physical register dependency. If so, returns the
42/// register and the cost of copying the register.
43static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
44                                      const TargetRegisterInfo *TRI,
45                                      const TargetInstrInfo *TII,
46                                      unsigned &PhysReg, int &Cost) {
47  if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
48    return;
49
50  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
51  if (TargetRegisterInfo::isVirtualRegister(Reg))
52    return;
53
54  unsigned ResNo = User->getOperand(2).getResNo();
55  if (Def->isMachineOpcode()) {
56    const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
57    if (ResNo >= II.getNumDefs() &&
58        II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
59      PhysReg = Reg;
60      const TargetRegisterClass *RC =
61        TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo));
62      Cost = RC->getCopyCost();
63    }
64  }
65}
66
67/// BuildSchedUnits - Build SUnits from the selection dag that we are input.
68/// This SUnit graph is similar to the SelectionDAG, but represents flagged
69/// together nodes with a single SUnit.
70void ScheduleDAGSDNodes::BuildSchedUnits() {
71  // Reserve entries in the vector for each of the SUnits we are creating.  This
72  // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
73  // invalidated.
74  // FIXME: Multiply by 2 because we may clone nodes during scheduling.
75  // This is a temporary workaround.
76  SUnits.reserve(DAG->allnodes_size() * 2);
77
78  // During scheduling, the NodeId field of SDNode is used to map SDNodes
79  // to their associated SUnits by holding SUnits table indices. A value
80  // of -1 means the SDNode does not yet have an associated SUnit.
81  for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
82       E = DAG->allnodes_end(); NI != E; ++NI)
83    NI->setNodeId(-1);
84
85  // Check to see if the scheduler cares about latencies.
86  bool UnitLatencies = ForceUnitLatencies();
87
88  for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
89       E = DAG->allnodes_end(); NI != E; ++NI) {
90    if (isPassiveNode(NI))  // Leaf node, e.g. a TargetImmediate.
91      continue;
92
93    // If this node has already been processed, stop now.
94    if (NI->getNodeId() != -1) continue;
95
96    SUnit *NodeSUnit = NewSUnit(NI);
97
98    // See if anything is flagged to this node, if so, add them to flagged
99    // nodes.  Nodes can have at most one flag input and one flag output.  Flags
100    // are required the be the last operand and result of a node.
101
102    // Scan up to find flagged preds.
103    SDNode *N = NI;
104    if (N->getNumOperands() &&
105        N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
106      do {
107        N = N->getOperand(N->getNumOperands()-1).getNode();
108        assert(N->getNodeId() == -1 && "Node already inserted!");
109        N->setNodeId(NodeSUnit->NodeNum);
110      } while (N->getNumOperands() &&
111               N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
112    }
113
114    // Scan down to find any flagged succs.
115    N = NI;
116    while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
117      SDValue FlagVal(N, N->getNumValues()-1);
118
119      // There are either zero or one users of the Flag result.
120      bool HasFlagUse = false;
121      for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
122           UI != E; ++UI)
123        if (FlagVal.isOperandOf(*UI)) {
124          HasFlagUse = true;
125          assert(N->getNodeId() == -1 && "Node already inserted!");
126          N->setNodeId(NodeSUnit->NodeNum);
127          N = *UI;
128          break;
129        }
130      if (!HasFlagUse) break;
131    }
132
133    // If there are flag operands involved, N is now the bottom-most node
134    // of the sequence of nodes that are flagged together.
135    // Update the SUnit.
136    NodeSUnit->setNode(N);
137    assert(N->getNodeId() == -1 && "Node already inserted!");
138    N->setNodeId(NodeSUnit->NodeNum);
139
140    // Assign the Latency field of NodeSUnit using target-provided information.
141    if (UnitLatencies)
142      NodeSUnit->Latency = 1;
143    else
144      ComputeLatency(NodeSUnit);
145  }
146
147  // Pass 2: add the preds, succs, etc.
148  for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
149    SUnit *SU = &SUnits[su];
150    SDNode *MainNode = SU->getNode();
151
152    if (MainNode->isMachineOpcode()) {
153      unsigned Opc = MainNode->getMachineOpcode();
154      const TargetInstrDesc &TID = TII->get(Opc);
155      for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
156        if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
157          SU->isTwoAddress = true;
158          break;
159        }
160      }
161      if (TID.isCommutable())
162        SU->isCommutable = true;
163    }
164
165    // Find all predecessors and successors of the group.
166    for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
167      if (N->isMachineOpcode() &&
168          TII->get(N->getMachineOpcode()).getImplicitDefs() &&
169          CountResults(N) > TII->get(N->getMachineOpcode()).getNumDefs())
170        SU->hasPhysRegDefs = true;
171
172      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
173        SDNode *OpN = N->getOperand(i).getNode();
174        if (isPassiveNode(OpN)) continue;   // Not scheduled.
175        SUnit *OpSU = &SUnits[OpN->getNodeId()];
176        assert(OpSU && "Node has no SUnit!");
177        if (OpSU == SU) continue;           // In the same group.
178
179        MVT OpVT = N->getOperand(i).getValueType();
180        assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
181        bool isChain = OpVT == MVT::Other;
182
183        unsigned PhysReg = 0;
184        int Cost = 1;
185        // Determine if this is a physical register dependency.
186        CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
187        assert((PhysReg == 0 || !isChain) &&
188               "Chain dependence via physreg data?");
189        SU->addPred(SDep(OpSU, isChain ? SDep::Order : SDep::Data,
190                         OpSU->Latency, PhysReg));
191      }
192    }
193  }
194}
195
196void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
197  const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
198
199  // Compute the latency for the node.  We use the sum of the latencies for
200  // all nodes flagged together into this SUnit.
201  SU->Latency = 0;
202  bool SawMachineOpcode = false;
203  for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
204    if (N->isMachineOpcode()) {
205      SawMachineOpcode = true;
206      SU->Latency +=
207        InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass());
208    }
209}
210
211/// CountResults - The results of target nodes have register or immediate
212/// operands first, then an optional chain, and optional flag operands (which do
213/// not go into the resulting MachineInstr).
214unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) {
215  unsigned N = Node->getNumValues();
216  while (N && Node->getValueType(N - 1) == MVT::Flag)
217    --N;
218  if (N && Node->getValueType(N - 1) == MVT::Other)
219    --N;    // Skip over chain result.
220  return N;
221}
222
223/// CountOperands - The inputs to target nodes have any actual inputs first,
224/// followed by special operands that describe memory references, then an
225/// optional chain operand, then an optional flag operand.  Compute the number
226/// of actual operands that will go into the resulting MachineInstr.
227unsigned ScheduleDAGSDNodes::CountOperands(SDNode *Node) {
228  unsigned N = ComputeMemOperandsEnd(Node);
229  while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).getNode()))
230    --N; // Ignore MEMOPERAND nodes
231  return N;
232}
233
234/// ComputeMemOperandsEnd - Find the index one past the last MemOperandSDNode
235/// operand
236unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
237  unsigned N = Node->getNumOperands();
238  while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
239    --N;
240  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
241    --N; // Ignore chain if it exists.
242  return N;
243}
244
245
246void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
247  if (SU->getNode())
248    SU->getNode()->dump(DAG);
249  else
250    cerr << "CROSS RC COPY ";
251  cerr << "\n";
252  SmallVector<SDNode *, 4> FlaggedNodes;
253  for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
254    FlaggedNodes.push_back(N);
255  while (!FlaggedNodes.empty()) {
256    cerr << "    ";
257    FlaggedNodes.back()->dump(DAG);
258    cerr << "\n";
259    FlaggedNodes.pop_back();
260  }
261}
262