ScheduleDAGSDNodes.cpp revision 1bd8afcfb510c8b0826bc152ae72b67b4dbbcf1b
1//===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the ScheduleDAG class, which is a base class used by 11// scheduling implementation classes. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "pre-RA-sched" 16#include "SDNodeDbgValue.h" 17#include "ScheduleDAGSDNodes.h" 18#include "InstrEmitter.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "llvm/Target/TargetMachine.h" 21#include "llvm/Target/TargetInstrInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetRegisterInfo.h" 24#include "llvm/Target/TargetSubtarget.h" 25#include "llvm/ADT/DenseMap.h" 26#include "llvm/ADT/SmallPtrSet.h" 27#include "llvm/ADT/SmallSet.h" 28#include "llvm/ADT/SmallVector.h" 29#include "llvm/ADT/Statistic.h" 30#include "llvm/Support/Debug.h" 31#include "llvm/Support/raw_ostream.h" 32using namespace llvm; 33 34STATISTIC(LoadsClustered, "Number of loads clustered together"); 35 36ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf) 37 : ScheduleDAG(mf) { 38} 39 40/// Run - perform scheduling. 41/// 42void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb, 43 MachineBasicBlock::iterator insertPos) { 44 DAG = dag; 45 ScheduleDAG::Run(bb, insertPos); 46} 47 48/// NewSUnit - Creates a new SUnit and return a ptr to it. 49/// 50SUnit *ScheduleDAGSDNodes::NewSUnit(SDNode *N) { 51#ifndef NDEBUG 52 const SUnit *Addr = 0; 53 if (!SUnits.empty()) 54 Addr = &SUnits[0]; 55#endif 56 SUnits.push_back(SUnit(N, (unsigned)SUnits.size())); 57 assert((Addr == 0 || Addr == &SUnits[0]) && 58 "SUnits std::vector reallocated on the fly!"); 59 SUnits.back().OrigNode = &SUnits.back(); 60 SUnit *SU = &SUnits.back(); 61 const TargetLowering &TLI = DAG->getTargetLoweringInfo(); 62 if (N->isMachineOpcode() && 63 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) 64 SU->SchedulingPref = Sched::None; 65 else 66 SU->SchedulingPref = TLI.getSchedulingPreference(N); 67 return SU; 68} 69 70SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) { 71 SUnit *SU = NewSUnit(Old->getNode()); 72 SU->OrigNode = Old->OrigNode; 73 SU->Latency = Old->Latency; 74 SU->isTwoAddress = Old->isTwoAddress; 75 SU->isCommutable = Old->isCommutable; 76 SU->hasPhysRegDefs = Old->hasPhysRegDefs; 77 SU->hasPhysRegClobbers = Old->hasPhysRegClobbers; 78 SU->SchedulingPref = Old->SchedulingPref; 79 Old->isCloned = true; 80 return SU; 81} 82 83/// CheckForPhysRegDependency - Check if the dependency between def and use of 84/// a specified operand is a physical register dependency. If so, returns the 85/// register and the cost of copying the register. 86static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, 87 const TargetRegisterInfo *TRI, 88 const TargetInstrInfo *TII, 89 unsigned &PhysReg, int &Cost) { 90 if (Op != 2 || User->getOpcode() != ISD::CopyToReg) 91 return; 92 93 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 94 if (TargetRegisterInfo::isVirtualRegister(Reg)) 95 return; 96 97 unsigned ResNo = User->getOperand(2).getResNo(); 98 if (Def->isMachineOpcode()) { 99 const TargetInstrDesc &II = TII->get(Def->getMachineOpcode()); 100 if (ResNo >= II.getNumDefs() && 101 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { 102 PhysReg = Reg; 103 const TargetRegisterClass *RC = 104 TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo)); 105 Cost = RC->getCopyCost(); 106 } 107 } 108} 109 110static void AddFlags(SDNode *N, SDValue Flag, bool AddFlag, 111 SelectionDAG *DAG) { 112 SmallVector<EVT, 4> VTs; 113 SDNode *FlagDestNode = Flag.getNode(); 114 115 // Don't add a flag from a node to itself. 116 if (FlagDestNode == N) return; 117 118 // Don't add a flag to something which already has a flag. 119 if (N->getValueType(N->getNumValues() - 1) == MVT::Flag) return; 120 121 for (unsigned I = 0, E = N->getNumValues(); I != E; ++I) 122 VTs.push_back(N->getValueType(I)); 123 124 if (AddFlag) 125 VTs.push_back(MVT::Flag); 126 127 SmallVector<SDValue, 4> Ops; 128 for (unsigned I = 0, E = N->getNumOperands(); I != E; ++I) 129 Ops.push_back(N->getOperand(I)); 130 131 if (FlagDestNode) 132 Ops.push_back(Flag); 133 134 SDVTList VTList = DAG->getVTList(&VTs[0], VTs.size()); 135 MachineSDNode::mmo_iterator Begin = 0, End = 0; 136 MachineSDNode *MN = dyn_cast<MachineSDNode>(N); 137 138 // Store memory references. 139 if (MN) { 140 Begin = MN->memoperands_begin(); 141 End = MN->memoperands_end(); 142 } 143 144 DAG->MorphNodeTo(N, N->getOpcode(), VTList, &Ops[0], Ops.size()); 145 146 // Reset the memory references 147 if (MN) 148 MN->setMemRefs(Begin, End); 149} 150 151/// ClusterNeighboringLoads - Force nearby loads together by "flagging" them. 152/// This function finds loads of the same base and different offsets. If the 153/// offsets are not far apart (target specific), it add MVT::Flag inputs and 154/// outputs to ensure they are scheduled together and in order. This 155/// optimization may benefit some targets by improving cache locality. 156void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) { 157 SDNode *Chain = 0; 158 unsigned NumOps = Node->getNumOperands(); 159 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other) 160 Chain = Node->getOperand(NumOps-1).getNode(); 161 if (!Chain) 162 return; 163 164 // Look for other loads of the same chain. Find loads that are loading from 165 // the same base pointer and different offsets. 166 SmallPtrSet<SDNode*, 16> Visited; 167 SmallVector<int64_t, 4> Offsets; 168 DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode. 169 bool Cluster = false; 170 SDNode *Base = Node; 171 int64_t BaseOffset; 172 for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end(); 173 I != E; ++I) { 174 SDNode *User = *I; 175 if (User == Node || !Visited.insert(User)) 176 continue; 177 int64_t Offset1, Offset2; 178 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || 179 Offset1 == Offset2) 180 // FIXME: Should be ok if they addresses are identical. But earlier 181 // optimizations really should have eliminated one of the loads. 182 continue; 183 if (O2SMap.insert(std::make_pair(Offset1, Base)).second) 184 Offsets.push_back(Offset1); 185 O2SMap.insert(std::make_pair(Offset2, User)); 186 Offsets.push_back(Offset2); 187 if (Offset2 < Offset1) { 188 Base = User; 189 BaseOffset = Offset2; 190 } else { 191 BaseOffset = Offset1; 192 } 193 Cluster = true; 194 } 195 196 if (!Cluster) 197 return; 198 199 // Sort them in increasing order. 200 std::sort(Offsets.begin(), Offsets.end()); 201 202 // Check if the loads are close enough. 203 SmallVector<SDNode*, 4> Loads; 204 unsigned NumLoads = 0; 205 int64_t BaseOff = Offsets[0]; 206 SDNode *BaseLoad = O2SMap[BaseOff]; 207 Loads.push_back(BaseLoad); 208 for (unsigned i = 1, e = Offsets.size(); i != e; ++i) { 209 int64_t Offset = Offsets[i]; 210 SDNode *Load = O2SMap[Offset]; 211 if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads)) 212 break; // Stop right here. Ignore loads that are further away. 213 Loads.push_back(Load); 214 ++NumLoads; 215 } 216 217 if (NumLoads == 0) 218 return; 219 220 // Cluster loads by adding MVT::Flag outputs and inputs. This also 221 // ensure they are scheduled in order of increasing addresses. 222 SDNode *Lead = Loads[0]; 223 AddFlags(Lead, SDValue(0, 0), true, DAG); 224 225 SDValue InFlag = SDValue(Lead, Lead->getNumValues() - 1); 226 for (unsigned I = 1, E = Loads.size(); I != E; ++I) { 227 bool OutFlag = I < E - 1; 228 SDNode *Load = Loads[I]; 229 230 AddFlags(Load, InFlag, OutFlag, DAG); 231 232 if (OutFlag) 233 InFlag = SDValue(Load, Load->getNumValues() - 1); 234 235 ++LoadsClustered; 236 } 237} 238 239/// ClusterNodes - Cluster certain nodes which should be scheduled together. 240/// 241void ScheduleDAGSDNodes::ClusterNodes() { 242 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(), 243 E = DAG->allnodes_end(); NI != E; ++NI) { 244 SDNode *Node = &*NI; 245 if (!Node || !Node->isMachineOpcode()) 246 continue; 247 248 unsigned Opc = Node->getMachineOpcode(); 249 const TargetInstrDesc &TID = TII->get(Opc); 250 if (TID.mayLoad()) 251 // Cluster loads from "near" addresses into combined SUnits. 252 ClusterNeighboringLoads(Node); 253 } 254} 255 256void ScheduleDAGSDNodes::BuildSchedUnits() { 257 // During scheduling, the NodeId field of SDNode is used to map SDNodes 258 // to their associated SUnits by holding SUnits table indices. A value 259 // of -1 means the SDNode does not yet have an associated SUnit. 260 unsigned NumNodes = 0; 261 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(), 262 E = DAG->allnodes_end(); NI != E; ++NI) { 263 NI->setNodeId(-1); 264 ++NumNodes; 265 } 266 267 // Reserve entries in the vector for each of the SUnits we are creating. This 268 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get 269 // invalidated. 270 // FIXME: Multiply by 2 because we may clone nodes during scheduling. 271 // This is a temporary workaround. 272 SUnits.reserve(NumNodes * 2); 273 274 // Add all nodes in depth first order. 275 SmallVector<SDNode*, 64> Worklist; 276 SmallPtrSet<SDNode*, 64> Visited; 277 Worklist.push_back(DAG->getRoot().getNode()); 278 Visited.insert(DAG->getRoot().getNode()); 279 280 while (!Worklist.empty()) { 281 SDNode *NI = Worklist.pop_back_val(); 282 283 // Add all operands to the worklist unless they've already been added. 284 for (unsigned i = 0, e = NI->getNumOperands(); i != e; ++i) 285 if (Visited.insert(NI->getOperand(i).getNode())) 286 Worklist.push_back(NI->getOperand(i).getNode()); 287 288 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate. 289 continue; 290 291 // If this node has already been processed, stop now. 292 if (NI->getNodeId() != -1) continue; 293 294 SUnit *NodeSUnit = NewSUnit(NI); 295 296 // See if anything is flagged to this node, if so, add them to flagged 297 // nodes. Nodes can have at most one flag input and one flag output. Flags 298 // are required to be the last operand and result of a node. 299 300 // Scan up to find flagged preds. 301 SDNode *N = NI; 302 while (N->getNumOperands() && 303 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) { 304 N = N->getOperand(N->getNumOperands()-1).getNode(); 305 assert(N->getNodeId() == -1 && "Node already inserted!"); 306 N->setNodeId(NodeSUnit->NodeNum); 307 } 308 309 // Scan down to find any flagged succs. 310 N = NI; 311 while (N->getValueType(N->getNumValues()-1) == MVT::Flag) { 312 SDValue FlagVal(N, N->getNumValues()-1); 313 314 // There are either zero or one users of the Flag result. 315 bool HasFlagUse = false; 316 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 317 UI != E; ++UI) 318 if (FlagVal.isOperandOf(*UI)) { 319 HasFlagUse = true; 320 assert(N->getNodeId() == -1 && "Node already inserted!"); 321 N->setNodeId(NodeSUnit->NodeNum); 322 N = *UI; 323 break; 324 } 325 if (!HasFlagUse) break; 326 } 327 328 // If there are flag operands involved, N is now the bottom-most node 329 // of the sequence of nodes that are flagged together. 330 // Update the SUnit. 331 NodeSUnit->setNode(N); 332 assert(N->getNodeId() == -1 && "Node already inserted!"); 333 N->setNodeId(NodeSUnit->NodeNum); 334 335 // Assign the Latency field of NodeSUnit using target-provided information. 336 ComputeLatency(NodeSUnit); 337 } 338} 339 340void ScheduleDAGSDNodes::AddSchedEdges() { 341 const TargetSubtarget &ST = TM.getSubtarget<TargetSubtarget>(); 342 343 // Check to see if the scheduler cares about latencies. 344 bool UnitLatencies = ForceUnitLatencies(); 345 346 // Pass 2: add the preds, succs, etc. 347 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) { 348 SUnit *SU = &SUnits[su]; 349 SDNode *MainNode = SU->getNode(); 350 351 if (MainNode->isMachineOpcode()) { 352 unsigned Opc = MainNode->getMachineOpcode(); 353 const TargetInstrDesc &TID = TII->get(Opc); 354 for (unsigned i = 0; i != TID.getNumOperands(); ++i) { 355 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) { 356 SU->isTwoAddress = true; 357 break; 358 } 359 } 360 if (TID.isCommutable()) 361 SU->isCommutable = true; 362 } 363 364 // Find all predecessors and successors of the group. 365 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) { 366 if (N->isMachineOpcode() && 367 TII->get(N->getMachineOpcode()).getImplicitDefs()) { 368 SU->hasPhysRegClobbers = true; 369 unsigned NumUsed = InstrEmitter::CountResults(N); 370 while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1)) 371 --NumUsed; // Skip over unused values at the end. 372 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs()) 373 SU->hasPhysRegDefs = true; 374 } 375 376 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 377 SDNode *OpN = N->getOperand(i).getNode(); 378 if (isPassiveNode(OpN)) continue; // Not scheduled. 379 SUnit *OpSU = &SUnits[OpN->getNodeId()]; 380 assert(OpSU && "Node has no SUnit!"); 381 if (OpSU == SU) continue; // In the same group. 382 383 EVT OpVT = N->getOperand(i).getValueType(); 384 assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!"); 385 bool isChain = OpVT == MVT::Other; 386 387 unsigned PhysReg = 0; 388 int Cost = 1; 389 // Determine if this is a physical register dependency. 390 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); 391 assert((PhysReg == 0 || !isChain) && 392 "Chain dependence via physreg data?"); 393 // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler 394 // emits a copy from the physical register to a virtual register unless 395 // it requires a cross class copy (cost < 0). That means we are only 396 // treating "expensive to copy" register dependency as physical register 397 // dependency. This may change in the future though. 398 if (Cost >= 0) 399 PhysReg = 0; 400 401 // If this is a ctrl dep, latency is 1. 402 unsigned OpLatency = isChain ? 1 : OpSU->Latency; 403 const SDep &dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data, 404 OpLatency, PhysReg); 405 if (!isChain && !UnitLatencies) { 406 ComputeOperandLatency(OpN, N, i, const_cast<SDep &>(dep)); 407 ST.adjustSchedDependency(OpSU, SU, const_cast<SDep &>(dep)); 408 } 409 410 SU->addPred(dep); 411 } 412 } 413 } 414} 415 416/// BuildSchedGraph - Build the SUnit graph from the selection dag that we 417/// are input. This SUnit graph is similar to the SelectionDAG, but 418/// excludes nodes that aren't interesting to scheduling, and represents 419/// flagged together nodes with a single SUnit. 420void ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) { 421 // Cluster certain nodes which should be scheduled together. 422 ClusterNodes(); 423 // Populate the SUnits array. 424 BuildSchedUnits(); 425 // Compute all the scheduling dependencies between nodes. 426 AddSchedEdges(); 427} 428 429void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) { 430 // Check to see if the scheduler cares about latencies. 431 if (ForceUnitLatencies()) { 432 SU->Latency = 1; 433 return; 434 } 435 436 const InstrItineraryData &InstrItins = TM.getInstrItineraryData(); 437 if (InstrItins.isEmpty()) { 438 SU->Latency = 1; 439 return; 440 } 441 442 // Compute the latency for the node. We use the sum of the latencies for 443 // all nodes flagged together into this SUnit. 444 SU->Latency = 0; 445 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) 446 if (N->isMachineOpcode()) { 447 SU->Latency += InstrItins. 448 getStageLatency(TII->get(N->getMachineOpcode()).getSchedClass()); 449 } 450} 451 452void ScheduleDAGSDNodes::ComputeOperandLatency(SDNode *Def, SDNode *Use, 453 unsigned OpIdx, SDep& dep) const{ 454 // Check to see if the scheduler cares about latencies. 455 if (ForceUnitLatencies()) 456 return; 457 458 const InstrItineraryData &InstrItins = TM.getInstrItineraryData(); 459 if (InstrItins.isEmpty()) 460 return; 461 462 if (dep.getKind() != SDep::Data) 463 return; 464 465 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); 466 if (Def->isMachineOpcode()) { 467 const TargetInstrDesc &II = TII->get(Def->getMachineOpcode()); 468 if (DefIdx >= II.getNumDefs()) 469 return; 470 int DefCycle = InstrItins.getOperandCycle(II.getSchedClass(), DefIdx); 471 if (DefCycle < 0) 472 return; 473 int UseCycle = 1; 474 if (Use->isMachineOpcode()) { 475 const unsigned UseClass = TII->get(Use->getMachineOpcode()).getSchedClass(); 476 UseCycle = InstrItins.getOperandCycle(UseClass, OpIdx); 477 } 478 if (UseCycle >= 0) { 479 int Latency = DefCycle - UseCycle + 1; 480 if (Latency >= 0) 481 dep.setLatency(Latency); 482 } 483 } 484} 485 486void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const { 487 if (!SU->getNode()) { 488 dbgs() << "PHYS REG COPY\n"; 489 return; 490 } 491 492 SU->getNode()->dump(DAG); 493 dbgs() << "\n"; 494 SmallVector<SDNode *, 4> FlaggedNodes; 495 for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode()) 496 FlaggedNodes.push_back(N); 497 while (!FlaggedNodes.empty()) { 498 dbgs() << " "; 499 FlaggedNodes.back()->dump(DAG); 500 dbgs() << "\n"; 501 FlaggedNodes.pop_back(); 502 } 503} 504 505namespace { 506 struct OrderSorter { 507 bool operator()(const std::pair<unsigned, MachineInstr*> &A, 508 const std::pair<unsigned, MachineInstr*> &B) { 509 return A.first < B.first; 510 } 511 }; 512} 513 514// ProcessSourceNode - Process nodes with source order numbers. These are added 515// to a vector which EmitSchedule use to determine how to insert dbg_value 516// instructions in the right order. 517static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG, 518 InstrEmitter &Emitter, 519 DenseMap<SDValue, unsigned> &VRBaseMap, 520 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders, 521 SmallSet<unsigned, 8> &Seen) { 522 unsigned Order = DAG->GetOrdering(N); 523 if (!Order || !Seen.insert(Order)) 524 return; 525 526 MachineBasicBlock *BB = Emitter.getBlock(); 527 if (BB->empty() || BB->back().isPHI()) { 528 // Did not insert any instruction. 529 Orders.push_back(std::make_pair(Order, (MachineInstr*)0)); 530 return; 531 } 532 533 Orders.push_back(std::make_pair(Order, &BB->back())); 534 if (!N->getHasDebugValue()) 535 return; 536 // Opportunistically insert immediate dbg_value uses, i.e. those with source 537 // order number right after the N. 538 MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos(); 539 SmallVector<SDDbgValue*,2> &DVs = DAG->GetDbgValues(N); 540 for (unsigned i = 0, e = DVs.size(); i != e; ++i) { 541 if (DVs[i]->isInvalidated()) 542 continue; 543 unsigned DVOrder = DVs[i]->getOrder(); 544 if (DVOrder == ++Order) { 545 MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap); 546 if (DbgMI) { 547 Orders.push_back(std::make_pair(DVOrder, DbgMI)); 548 BB->insert(InsertPos, DbgMI); 549 } 550 DVs[i]->setIsInvalidated(); 551 } 552 } 553} 554 555 556/// EmitSchedule - Emit the machine code in scheduled order. 557MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() { 558 InstrEmitter Emitter(BB, InsertPos); 559 DenseMap<SDValue, unsigned> VRBaseMap; 560 DenseMap<SUnit*, unsigned> CopyVRBaseMap; 561 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; 562 SmallSet<unsigned, 8> Seen; 563 bool HasDbg = DAG->hasDebugValues(); 564 565 // If this is the first BB, emit byval parameter dbg_value's. 566 if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) { 567 SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin(); 568 SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd(); 569 for (; PDI != PDE; ++PDI) { 570 MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap); 571 if (DbgMI) 572 BB->push_back(DbgMI); 573 } 574 } 575 576 for (unsigned i = 0, e = Sequence.size(); i != e; i++) { 577 SUnit *SU = Sequence[i]; 578 if (!SU) { 579 // Null SUnit* is a noop. 580 EmitNoop(); 581 continue; 582 } 583 584 // For pre-regalloc scheduling, create instructions corresponding to the 585 // SDNode and any flagged SDNodes and append them to the block. 586 if (!SU->getNode()) { 587 // Emit a copy. 588 EmitPhysRegCopy(SU, CopyVRBaseMap); 589 continue; 590 } 591 592 SmallVector<SDNode *, 4> FlaggedNodes; 593 for (SDNode *N = SU->getNode()->getFlaggedNode(); N; 594 N = N->getFlaggedNode()) 595 FlaggedNodes.push_back(N); 596 while (!FlaggedNodes.empty()) { 597 SDNode *N = FlaggedNodes.back(); 598 Emitter.EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned, 599 VRBaseMap); 600 // Remember the source order of the inserted instruction. 601 if (HasDbg) 602 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen); 603 FlaggedNodes.pop_back(); 604 } 605 Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, 606 VRBaseMap); 607 // Remember the source order of the inserted instruction. 608 if (HasDbg) 609 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders, 610 Seen); 611 } 612 613 // Insert all the dbg_values which have not already been inserted in source 614 // order sequence. 615 if (HasDbg) { 616 MachineBasicBlock::iterator BBBegin = BB->empty() ? BB->end() : BB->begin(); 617 while (BBBegin != BB->end() && BBBegin->isPHI()) 618 ++BBBegin; 619 620 // Sort the source order instructions and use the order to insert debug 621 // values. 622 std::sort(Orders.begin(), Orders.end(), OrderSorter()); 623 624 SDDbgInfo::DbgIterator DI = DAG->DbgBegin(); 625 SDDbgInfo::DbgIterator DE = DAG->DbgEnd(); 626 // Now emit the rest according to source order. 627 unsigned LastOrder = 0; 628 MachineInstr *LastMI = 0; 629 for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) { 630 unsigned Order = Orders[i].first; 631 MachineInstr *MI = Orders[i].second; 632 // Insert all SDDbgValue's whose order(s) are before "Order". 633 if (!MI) 634 continue; 635 MachineBasicBlock *MIBB = MI->getParent(); 636#ifndef NDEBUG 637 unsigned LastDIOrder = 0; 638#endif 639 for (; DI != DE && 640 (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) { 641#ifndef NDEBUG 642 assert((*DI)->getOrder() >= LastDIOrder && 643 "SDDbgValue nodes must be in source order!"); 644 LastDIOrder = (*DI)->getOrder(); 645#endif 646 if ((*DI)->isInvalidated()) 647 continue; 648 MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap); 649 if (DbgMI) { 650 if (!LastOrder) 651 // Insert to start of the BB (after PHIs). 652 BB->insert(BBBegin, DbgMI); 653 else { 654 MachineBasicBlock::iterator Pos = MI; 655 MIBB->insert(llvm::next(Pos), DbgMI); 656 } 657 } 658 } 659 LastOrder = Order; 660 LastMI = MI; 661 } 662 // Add trailing DbgValue's before the terminator. FIXME: May want to add 663 // some of them before one or more conditional branches? 664 while (DI != DE) { 665 MachineBasicBlock *InsertBB = Emitter.getBlock(); 666 MachineBasicBlock::iterator Pos= Emitter.getBlock()->getFirstTerminator(); 667 if (!(*DI)->isInvalidated()) { 668 MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, VRBaseMap); 669 if (DbgMI) 670 InsertBB->insert(Pos, DbgMI); 671 } 672 ++DI; 673 } 674 } 675 676 BB = Emitter.getBlock(); 677 InsertPos = Emitter.getInsertPos(); 678 return BB; 679} 680