ScheduleDAGSDNodes.cpp revision 3f23744df4809eba94284e601e81489212c974d4
1//===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the ScheduleDAG class, which is a base class used by 11// scheduling implementation classes. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "pre-RA-sched" 16#include "llvm/CodeGen/ScheduleDAGSDNodes.h" 17#include "llvm/CodeGen/SelectionDAG.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetInstrInfo.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/Support/Debug.h" 22#include "llvm/Support/raw_ostream.h" 23using namespace llvm; 24 25ScheduleDAGSDNodes::ScheduleDAGSDNodes(SelectionDAG *dag, MachineBasicBlock *bb, 26 const TargetMachine &tm) 27 : ScheduleDAG(dag, bb, tm) { 28} 29 30SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) { 31 SUnit *SU = NewSUnit(Old->getNode()); 32 SU->OrigNode = Old->OrigNode; 33 SU->Latency = Old->Latency; 34 SU->isTwoAddress = Old->isTwoAddress; 35 SU->isCommutable = Old->isCommutable; 36 SU->hasPhysRegDefs = Old->hasPhysRegDefs; 37 return SU; 38} 39 40/// CheckForPhysRegDependency - Check if the dependency between def and use of 41/// a specified operand is a physical register dependency. If so, returns the 42/// register and the cost of copying the register. 43static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, 44 const TargetRegisterInfo *TRI, 45 const TargetInstrInfo *TII, 46 unsigned &PhysReg, int &Cost) { 47 if (Op != 2 || User->getOpcode() != ISD::CopyToReg) 48 return; 49 50 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 51 if (TargetRegisterInfo::isVirtualRegister(Reg)) 52 return; 53 54 unsigned ResNo = User->getOperand(2).getResNo(); 55 if (Def->isMachineOpcode()) { 56 const TargetInstrDesc &II = TII->get(Def->getMachineOpcode()); 57 if (ResNo >= II.getNumDefs() && 58 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { 59 PhysReg = Reg; 60 const TargetRegisterClass *RC = 61 TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo)); 62 Cost = RC->getCopyCost(); 63 } 64 } 65} 66 67/// BuildSchedUnits - Build SUnits from the selection dag that we are input. 68/// This SUnit graph is similar to the SelectionDAG, but represents flagged 69/// together nodes with a single SUnit. 70void ScheduleDAGSDNodes::BuildSchedUnits() { 71 // Reserve entries in the vector for each of the SUnits we are creating. This 72 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get 73 // invalidated. 74 SUnits.reserve(DAG->allnodes_size()); 75 76 // During scheduling, the NodeId field of SDNode is used to map SDNodes 77 // to their associated SUnits by holding SUnits table indices. A value 78 // of -1 means the SDNode does not yet have an associated SUnit. 79 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(), 80 E = DAG->allnodes_end(); NI != E; ++NI) 81 NI->setNodeId(-1); 82 83 // Check to see if the scheduler cares about latencies. 84 bool UnitLatencies = ForceUnitLatencies(); 85 86 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(), 87 E = DAG->allnodes_end(); NI != E; ++NI) { 88 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate. 89 continue; 90 91 // If this node has already been processed, stop now. 92 if (NI->getNodeId() != -1) continue; 93 94 SUnit *NodeSUnit = NewSUnit(NI); 95 96 // See if anything is flagged to this node, if so, add them to flagged 97 // nodes. Nodes can have at most one flag input and one flag output. Flags 98 // are required the be the last operand and result of a node. 99 100 // Scan up to find flagged preds. 101 SDNode *N = NI; 102 if (N->getNumOperands() && 103 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) { 104 do { 105 N = N->getOperand(N->getNumOperands()-1).getNode(); 106 assert(N->getNodeId() == -1 && "Node already inserted!"); 107 N->setNodeId(NodeSUnit->NodeNum); 108 } while (N->getNumOperands() && 109 N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag); 110 } 111 112 // Scan down to find any flagged succs. 113 N = NI; 114 while (N->getValueType(N->getNumValues()-1) == MVT::Flag) { 115 SDValue FlagVal(N, N->getNumValues()-1); 116 117 // There are either zero or one users of the Flag result. 118 bool HasFlagUse = false; 119 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 120 UI != E; ++UI) 121 if (FlagVal.isOperandOf(*UI)) { 122 HasFlagUse = true; 123 assert(N->getNodeId() == -1 && "Node already inserted!"); 124 N->setNodeId(NodeSUnit->NodeNum); 125 N = *UI; 126 break; 127 } 128 if (!HasFlagUse) break; 129 } 130 131 // If there are flag operands involved, N is now the bottom-most node 132 // of the sequence of nodes that are flagged together. 133 // Update the SUnit. 134 NodeSUnit->setNode(N); 135 assert(N->getNodeId() == -1 && "Node already inserted!"); 136 N->setNodeId(NodeSUnit->NodeNum); 137 138 // Assign the Latency field of NodeSUnit using target-provided information. 139 if (UnitLatencies) 140 NodeSUnit->Latency = 1; 141 else 142 ComputeLatency(NodeSUnit); 143 } 144 145 // Pass 2: add the preds, succs, etc. 146 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) { 147 SUnit *SU = &SUnits[su]; 148 SDNode *MainNode = SU->getNode(); 149 150 if (MainNode->isMachineOpcode()) { 151 unsigned Opc = MainNode->getMachineOpcode(); 152 const TargetInstrDesc &TID = TII->get(Opc); 153 for (unsigned i = 0; i != TID.getNumOperands(); ++i) { 154 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) { 155 SU->isTwoAddress = true; 156 break; 157 } 158 } 159 if (TID.isCommutable()) 160 SU->isCommutable = true; 161 } 162 163 // Find all predecessors and successors of the group. 164 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) { 165 if (N->isMachineOpcode() && 166 TII->get(N->getMachineOpcode()).getImplicitDefs() && 167 CountResults(N) > TII->get(N->getMachineOpcode()).getNumDefs()) 168 SU->hasPhysRegDefs = true; 169 170 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 171 SDNode *OpN = N->getOperand(i).getNode(); 172 if (isPassiveNode(OpN)) continue; // Not scheduled. 173 SUnit *OpSU = &SUnits[OpN->getNodeId()]; 174 assert(OpSU && "Node has no SUnit!"); 175 if (OpSU == SU) continue; // In the same group. 176 177 MVT OpVT = N->getOperand(i).getValueType(); 178 assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!"); 179 bool isChain = OpVT == MVT::Other; 180 181 unsigned PhysReg = 0; 182 int Cost = 1; 183 // Determine if this is a physical register dependency. 184 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); 185 assert((PhysReg == 0 || !isChain) && 186 "Chain dependence via physreg data?"); 187 SU->addPred(SDep(OpSU, isChain ? SDep::Order : SDep::Data, 188 OpSU->Latency, PhysReg)); 189 } 190 } 191 } 192} 193 194void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) { 195 const InstrItineraryData &InstrItins = TM.getInstrItineraryData(); 196 197 // Compute the latency for the node. We use the sum of the latencies for 198 // all nodes flagged together into this SUnit. 199 if (InstrItins.isEmpty()) { 200 // No latency information. 201 SU->Latency = 1; 202 return; 203 } 204 205 SU->Latency = 0; 206 bool SawMachineOpcode = false; 207 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) 208 if (N->isMachineOpcode()) { 209 SawMachineOpcode = true; 210 SU->Latency += 211 InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass()); 212 } 213 214 // Ensure that CopyToReg and similar nodes have a non-zero latency. 215 if (!SawMachineOpcode) 216 SU->Latency = 1; 217} 218 219/// CountResults - The results of target nodes have register or immediate 220/// operands first, then an optional chain, and optional flag operands (which do 221/// not go into the resulting MachineInstr). 222unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) { 223 unsigned N = Node->getNumValues(); 224 while (N && Node->getValueType(N - 1) == MVT::Flag) 225 --N; 226 if (N && Node->getValueType(N - 1) == MVT::Other) 227 --N; // Skip over chain result. 228 return N; 229} 230 231/// CountOperands - The inputs to target nodes have any actual inputs first, 232/// followed by special operands that describe memory references, then an 233/// optional chain operand, then an optional flag operand. Compute the number 234/// of actual operands that will go into the resulting MachineInstr. 235unsigned ScheduleDAGSDNodes::CountOperands(SDNode *Node) { 236 unsigned N = ComputeMemOperandsEnd(Node); 237 while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).getNode())) 238 --N; // Ignore MEMOPERAND nodes 239 return N; 240} 241 242/// ComputeMemOperandsEnd - Find the index one past the last MemOperandSDNode 243/// operand 244unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) { 245 unsigned N = Node->getNumOperands(); 246 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) 247 --N; 248 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 249 --N; // Ignore chain if it exists. 250 return N; 251} 252 253 254void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const { 255 if (SU->getNode()) 256 SU->getNode()->dump(DAG); 257 else 258 cerr << "CROSS RC COPY "; 259 cerr << "\n"; 260 SmallVector<SDNode *, 4> FlaggedNodes; 261 for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode()) 262 FlaggedNodes.push_back(N); 263 while (!FlaggedNodes.empty()) { 264 cerr << " "; 265 FlaggedNodes.back()->dump(DAG); 266 cerr << "\n"; 267 FlaggedNodes.pop_back(); 268 } 269} 270