ScheduleDAGSDNodes.cpp revision 787782f4ca0cca2523825131c24a6f78535a3eb8 
1//===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the ScheduleDAG class, which is a base class used by
11// scheduling implementation classes.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "pre-RA-sched"
16#include "llvm/CodeGen/ScheduleDAGSDNodes.h"
17#include "llvm/CodeGen/SelectionDAG.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/raw_ostream.h"
23using namespace llvm;
24
25ScheduleDAGSDNodes::ScheduleDAGSDNodes(SelectionDAG *dag, MachineBasicBlock *bb,
26                                       const TargetMachine &tm)
27  : ScheduleDAG(dag, bb, tm) {
28}
29
30SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
31  SUnit *SU = NewSUnit(Old->getNode());
32  SU->OrigNode = Old->OrigNode;
33  SU->Latency = Old->Latency;
34  SU->isTwoAddress = Old->isTwoAddress;
35  SU->isCommutable = Old->isCommutable;
36  SU->hasPhysRegDefs = Old->hasPhysRegDefs;
37  return SU;
38}
39
40/// CheckForPhysRegDependency - Check if the dependency between def and use of
41/// a specified operand is a physical register dependency. If so, returns the
42/// register and the cost of copying the register.
43static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
44                                      const TargetRegisterInfo *TRI,
45                                      const TargetInstrInfo *TII,
46                                      unsigned &PhysReg, int &Cost) {
47  if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
48    return;
49
50  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
51  if (TargetRegisterInfo::isVirtualRegister(Reg))
52    return;
53
54  unsigned ResNo = User->getOperand(2).getResNo();
55  if (Def->isMachineOpcode()) {
56    const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
57    if (ResNo >= II.getNumDefs() &&
58        II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
59      PhysReg = Reg;
60      const TargetRegisterClass *RC =
61        TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo));
62      Cost = RC->getCopyCost();
63    }
64  }
65}
66
67/// BuildSchedUnits - Build SUnits from the selection dag that we are input.
68/// This SUnit graph is similar to the SelectionDAG, but represents flagged
69/// together nodes with a single SUnit.
70void ScheduleDAGSDNodes::BuildSchedUnits() {
71  // Reserve entries in the vector for each of the SUnits we are creating.  This
72  // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
73  // invalidated.
74  SUnits.reserve(DAG->allnodes_size());
75
76  // During scheduling, the NodeId field of SDNode is used to map SDNodes
77  // to their associated SUnits by holding SUnits table indices. A value
78  // of -1 means the SDNode does not yet have an associated SUnit.
79  for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
80       E = DAG->allnodes_end(); NI != E; ++NI)
81    NI->setNodeId(-1);
82
83  for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
84       E = DAG->allnodes_end(); NI != E; ++NI) {
85    if (isPassiveNode(NI))  // Leaf node, e.g. a TargetImmediate.
86      continue;
87
88    // If this node has already been processed, stop now.
89    if (NI->getNodeId() != -1) continue;
90
91    SUnit *NodeSUnit = NewSUnit(NI);
92
93    // See if anything is flagged to this node, if so, add them to flagged
94    // nodes.  Nodes can have at most one flag input and one flag output.  Flags
95    // are required the be the last operand and result of a node.
96
97    // Scan up to find flagged preds.
98    SDNode *N = NI;
99    if (N->getNumOperands() &&
100        N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
101      do {
102        N = N->getOperand(N->getNumOperands()-1).getNode();
103        assert(N->getNodeId() == -1 && "Node already inserted!");
104        N->setNodeId(NodeSUnit->NodeNum);
105      } while (N->getNumOperands() &&
106               N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
107    }
108
109    // Scan down to find any flagged succs.
110    N = NI;
111    while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
112      SDValue FlagVal(N, N->getNumValues()-1);
113
114      // There are either zero or one users of the Flag result.
115      bool HasFlagUse = false;
116      for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
117           UI != E; ++UI)
118        if (FlagVal.isOperandOf(*UI)) {
119          HasFlagUse = true;
120          assert(N->getNodeId() == -1 && "Node already inserted!");
121          N->setNodeId(NodeSUnit->NodeNum);
122          N = *UI;
123          break;
124        }
125      if (!HasFlagUse) break;
126    }
127
128    // If there are flag operands involved, N is now the bottom-most node
129    // of the sequence of nodes that are flagged together.
130    // Update the SUnit.
131    NodeSUnit->setNode(N);
132    assert(N->getNodeId() == -1 && "Node already inserted!");
133    N->setNodeId(NodeSUnit->NodeNum);
134
135    // Assign the Latency field of NodeSUnit using target-provided information.
136    ComputeLatency(NodeSUnit);
137  }
138
139  // Pass 2: add the preds, succs, etc.
140  for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
141    SUnit *SU = &SUnits[su];
142    SDNode *MainNode = SU->getNode();
143
144    if (MainNode->isMachineOpcode()) {
145      unsigned Opc = MainNode->getMachineOpcode();
146      const TargetInstrDesc &TID = TII->get(Opc);
147      for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
148        if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
149          SU->isTwoAddress = true;
150          break;
151        }
152      }
153      if (TID.isCommutable())
154        SU->isCommutable = true;
155    }
156
157    // Find all predecessors and successors of the group.
158    for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
159      if (N->isMachineOpcode() &&
160          TII->get(N->getMachineOpcode()).getImplicitDefs() &&
161          CountResults(N) > TII->get(N->getMachineOpcode()).getNumDefs())
162        SU->hasPhysRegDefs = true;
163
164      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
165        SDNode *OpN = N->getOperand(i).getNode();
166        if (isPassiveNode(OpN)) continue;   // Not scheduled.
167        SUnit *OpSU = &SUnits[OpN->getNodeId()];
168        assert(OpSU && "Node has no SUnit!");
169        if (OpSU == SU) continue;           // In the same group.
170
171        MVT OpVT = N->getOperand(i).getValueType();
172        assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
173        bool isChain = OpVT == MVT::Other;
174
175        unsigned PhysReg = 0;
176        int Cost = 1;
177        // Determine if this is a physical register dependency.
178        CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
179        SU->addPred(OpSU, isChain, false, PhysReg, Cost);
180      }
181    }
182  }
183}
184
185void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
186  const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
187
188  // Compute the latency for the node.  We use the sum of the latencies for
189  // all nodes flagged together into this SUnit.
190  if (InstrItins.isEmpty()) {
191    // No latency information.
192    SU->Latency = 1;
193    return;
194  }
195
196  SU->Latency = 0;
197  bool SawMachineOpcode = false;
198  for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
199    if (N->isMachineOpcode()) {
200      SawMachineOpcode = true;
201      SU->Latency +=
202        InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass());
203    }
204
205  // Ensure that CopyToReg and similar nodes have a non-zero latency.
206  if (!SawMachineOpcode)
207    SU->Latency = 1;
208}
209
210/// CountResults - The results of target nodes have register or immediate
211/// operands first, then an optional chain, and optional flag operands (which do
212/// not go into the resulting MachineInstr).
213unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) {
214  unsigned N = Node->getNumValues();
215  while (N && Node->getValueType(N - 1) == MVT::Flag)
216    --N;
217  if (N && Node->getValueType(N - 1) == MVT::Other)
218    --N;    // Skip over chain result.
219  return N;
220}
221
222/// CountOperands - The inputs to target nodes have any actual inputs first,
223/// followed by special operands that describe memory references, then an
224/// optional chain operand, then an optional flag operand.  Compute the number
225/// of actual operands that will go into the resulting MachineInstr.
226unsigned ScheduleDAGSDNodes::CountOperands(SDNode *Node) {
227  unsigned N = ComputeMemOperandsEnd(Node);
228  while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).getNode()))
229    --N; // Ignore MEMOPERAND nodes
230  return N;
231}
232
233/// ComputeMemOperandsEnd - Find the index one past the last MemOperandSDNode
234/// operand
235unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
236  unsigned N = Node->getNumOperands();
237  while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
238    --N;
239  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
240    --N; // Ignore chain if it exists.
241  return N;
242}
243
244
245void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
246  if (SU->getNode())
247    SU->getNode()->dump(DAG);
248  else
249    cerr << "CROSS RC COPY ";
250  cerr << "\n";
251  SmallVector<SDNode *, 4> FlaggedNodes;
252  for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
253    FlaggedNodes.push_back(N);
254  while (!FlaggedNodes.empty()) {
255    cerr << "    ";
256    FlaggedNodes.back()->dump(DAG);
257    cerr << "\n";
258    FlaggedNodes.pop_back();
259  }
260}
261