ScheduleDAGSDNodes.cpp revision 7c968a8b1f4168e54fda5f3c418be83d86dcc68f 
1//===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the ScheduleDAG class, which is a base class used by
11// scheduling implementation classes.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "pre-RA-sched"
16#include "ScheduleDAGSDNodes.h"
17#include "llvm/CodeGen/SelectionDAG.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/raw_ostream.h"
23using namespace llvm;
24
25ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
26  : ScheduleDAG(mf) {
27}
28
29/// Run - perform scheduling.
30///
31void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb,
32                             MachineBasicBlock::iterator insertPos) {
33  DAG = dag;
34  ScheduleDAG::Run(bb, insertPos);
35}
36
37SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
38  SUnit *SU = NewSUnit(Old->getNode());
39  SU->OrigNode = Old->OrigNode;
40  SU->Latency = Old->Latency;
41  SU->isTwoAddress = Old->isTwoAddress;
42  SU->isCommutable = Old->isCommutable;
43  SU->hasPhysRegDefs = Old->hasPhysRegDefs;
44  Old->isCloned = true;
45  return SU;
46}
47
48/// CheckForPhysRegDependency - Check if the dependency between def and use of
49/// a specified operand is a physical register dependency. If so, returns the
50/// register and the cost of copying the register.
51static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
52                                      const TargetRegisterInfo *TRI,
53                                      const TargetInstrInfo *TII,
54                                      unsigned &PhysReg, int &Cost) {
55  if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
56    return;
57
58  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
59  if (TargetRegisterInfo::isVirtualRegister(Reg))
60    return;
61
62  unsigned ResNo = User->getOperand(2).getResNo();
63  if (Def->isMachineOpcode()) {
64    const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
65    if (ResNo >= II.getNumDefs() &&
66        II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
67      PhysReg = Reg;
68      const TargetRegisterClass *RC =
69        TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo));
70      Cost = RC->getCopyCost();
71    }
72  }
73}
74
75void ScheduleDAGSDNodes::BuildSchedUnits() {
76  // During scheduling, the NodeId field of SDNode is used to map SDNodes
77  // to their associated SUnits by holding SUnits table indices. A value
78  // of -1 means the SDNode does not yet have an associated SUnit.
79  unsigned NumNodes = 0;
80  for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
81       E = DAG->allnodes_end(); NI != E; ++NI) {
82    NI->setNodeId(-1);
83    ++NumNodes;
84  }
85
86  // Reserve entries in the vector for each of the SUnits we are creating.  This
87  // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
88  // invalidated.
89  // FIXME: Multiply by 2 because we may clone nodes during scheduling.
90  // This is a temporary workaround.
91  SUnits.reserve(NumNodes * 2);
92
93  // Check to see if the scheduler cares about latencies.
94  bool UnitLatencies = ForceUnitLatencies();
95
96  for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
97       E = DAG->allnodes_end(); NI != E; ++NI) {
98    if (isPassiveNode(NI))  // Leaf node, e.g. a TargetImmediate.
99      continue;
100
101    // If this node has already been processed, stop now.
102    if (NI->getNodeId() != -1) continue;
103
104    SUnit *NodeSUnit = NewSUnit(NI);
105
106    // See if anything is flagged to this node, if so, add them to flagged
107    // nodes.  Nodes can have at most one flag input and one flag output.  Flags
108    // are required the be the last operand and result of a node.
109
110    // Scan up to find flagged preds.
111    SDNode *N = NI;
112    if (N->getNumOperands() &&
113        N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
114      do {
115        N = N->getOperand(N->getNumOperands()-1).getNode();
116        assert(N->getNodeId() == -1 && "Node already inserted!");
117        N->setNodeId(NodeSUnit->NodeNum);
118      } while (N->getNumOperands() &&
119               N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
120    }
121
122    // Scan down to find any flagged succs.
123    N = NI;
124    while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
125      SDValue FlagVal(N, N->getNumValues()-1);
126
127      // There are either zero or one users of the Flag result.
128      bool HasFlagUse = false;
129      for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
130           UI != E; ++UI)
131        if (FlagVal.isOperandOf(*UI)) {
132          HasFlagUse = true;
133          assert(N->getNodeId() == -1 && "Node already inserted!");
134          N->setNodeId(NodeSUnit->NodeNum);
135          N = *UI;
136          break;
137        }
138      if (!HasFlagUse) break;
139    }
140
141    // If there are flag operands involved, N is now the bottom-most node
142    // of the sequence of nodes that are flagged together.
143    // Update the SUnit.
144    NodeSUnit->setNode(N);
145    assert(N->getNodeId() == -1 && "Node already inserted!");
146    N->setNodeId(NodeSUnit->NodeNum);
147
148    // Assign the Latency field of NodeSUnit using target-provided information.
149    if (UnitLatencies)
150      NodeSUnit->Latency = 1;
151    else
152      ComputeLatency(NodeSUnit);
153  }
154}
155
156void ScheduleDAGSDNodes::AddSchedEdges() {
157  // Pass 2: add the preds, succs, etc.
158  for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
159    SUnit *SU = &SUnits[su];
160    SDNode *MainNode = SU->getNode();
161
162    if (MainNode->isMachineOpcode()) {
163      unsigned Opc = MainNode->getMachineOpcode();
164      const TargetInstrDesc &TID = TII->get(Opc);
165      for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
166        if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
167          SU->isTwoAddress = true;
168          break;
169        }
170      }
171      if (TID.isCommutable())
172        SU->isCommutable = true;
173    }
174
175    // Find all predecessors and successors of the group.
176    for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
177      if (N->isMachineOpcode() &&
178          TII->get(N->getMachineOpcode()).getImplicitDefs() &&
179          CountResults(N) > TII->get(N->getMachineOpcode()).getNumDefs())
180        SU->hasPhysRegDefs = true;
181
182      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
183        SDNode *OpN = N->getOperand(i).getNode();
184        if (isPassiveNode(OpN)) continue;   // Not scheduled.
185        SUnit *OpSU = &SUnits[OpN->getNodeId()];
186        assert(OpSU && "Node has no SUnit!");
187        if (OpSU == SU) continue;           // In the same group.
188
189        MVT OpVT = N->getOperand(i).getValueType();
190        assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
191        bool isChain = OpVT == MVT::Other;
192
193        unsigned PhysReg = 0;
194        int Cost = 1;
195        // Determine if this is a physical register dependency.
196        CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
197        assert((PhysReg == 0 || !isChain) &&
198               "Chain dependence via physreg data?");
199        // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
200        // emits a copy from the physical register to a virtual register unless
201        // it requires a cross class copy (cost < 0). That means we are only
202        // treating "expensive to copy" register dependency as physical register
203        // dependency. This may change in the future though.
204        if (Cost >= 0)
205          PhysReg = 0;
206        SU->addPred(SDep(OpSU, isChain ? SDep::Order : SDep::Data,
207                         OpSU->Latency, PhysReg));
208      }
209    }
210  }
211}
212
213/// BuildSchedGraph - Build the SUnit graph from the selection dag that we
214/// are input.  This SUnit graph is similar to the SelectionDAG, but
215/// excludes nodes that aren't interesting to scheduling, and represents
216/// flagged together nodes with a single SUnit.
217void ScheduleDAGSDNodes::BuildSchedGraph() {
218  // Populate the SUnits array.
219  BuildSchedUnits();
220  // Compute all the scheduling dependencies between nodes.
221  AddSchedEdges();
222}
223
224void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
225  const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
226
227  // Compute the latency for the node.  We use the sum of the latencies for
228  // all nodes flagged together into this SUnit.
229  SU->Latency = 0;
230  bool SawMachineOpcode = false;
231  for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
232    if (N->isMachineOpcode()) {
233      SawMachineOpcode = true;
234      SU->Latency +=
235        InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass());
236    }
237}
238
239/// CountResults - The results of target nodes have register or immediate
240/// operands first, then an optional chain, and optional flag operands (which do
241/// not go into the resulting MachineInstr).
242unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) {
243  unsigned N = Node->getNumValues();
244  while (N && Node->getValueType(N - 1) == MVT::Flag)
245    --N;
246  if (N && Node->getValueType(N - 1) == MVT::Other)
247    --N;    // Skip over chain result.
248  return N;
249}
250
251/// CountOperands - The inputs to target nodes have any actual inputs first,
252/// followed by special operands that describe memory references, then an
253/// optional chain operand, then an optional flag operand.  Compute the number
254/// of actual operands that will go into the resulting MachineInstr.
255unsigned ScheduleDAGSDNodes::CountOperands(SDNode *Node) {
256  unsigned N = ComputeMemOperandsEnd(Node);
257  while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).getNode()))
258    --N; // Ignore MEMOPERAND nodes
259  return N;
260}
261
262/// ComputeMemOperandsEnd - Find the index one past the last MemOperandSDNode
263/// operand
264unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
265  unsigned N = Node->getNumOperands();
266  while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
267    --N;
268  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
269    --N; // Ignore chain if it exists.
270  return N;
271}
272
273
274void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
275  if (!SU->getNode()) {
276    cerr << "PHYS REG COPY\n";
277    return;
278  }
279
280  SU->getNode()->dump(DAG);
281  cerr << "\n";
282  SmallVector<SDNode *, 4> FlaggedNodes;
283  for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
284    FlaggedNodes.push_back(N);
285  while (!FlaggedNodes.empty()) {
286    cerr << "    ";
287    FlaggedNodes.back()->dump(DAG);
288    cerr << "\n";
289    FlaggedNodes.pop_back();
290  }
291}
292