ScheduleDAGSDNodes.cpp revision ef59ca0839362d4f6135366910502b41fe2c2ed9 
1//===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the ScheduleDAG class, which is a base class used by
11// scheduling implementation classes.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "pre-RA-sched"
16#include "llvm/CodeGen/ScheduleDAGSDNodes.h"
17#include "llvm/CodeGen/SelectionDAG.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/raw_ostream.h"
23using namespace llvm;
24
25ScheduleDAGSDNodes::ScheduleDAGSDNodes(SelectionDAG *dag, MachineBasicBlock *bb,
26                                       const TargetMachine &tm)
27  : ScheduleDAG(dag, bb, tm) {
28}
29
30SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
31  SUnit *SU = NewSUnit(Old->getNode());
32  SU->OrigNode = Old->OrigNode;
33  SU->Latency = Old->Latency;
34  SU->isTwoAddress = Old->isTwoAddress;
35  SU->isCommutable = Old->isCommutable;
36  SU->hasPhysRegDefs = Old->hasPhysRegDefs;
37  return SU;
38}
39
40/// CheckForPhysRegDependency - Check if the dependency between def and use of
41/// a specified operand is a physical register dependency. If so, returns the
42/// register.
43static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
44                                      const TargetRegisterInfo *TRI,
45                                      const TargetInstrInfo *TII,
46                                      unsigned &PhysReg) {
47  if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
48    return;
49
50  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
51  if (TargetRegisterInfo::isVirtualRegister(Reg))
52    return;
53
54  unsigned ResNo = User->getOperand(2).getResNo();
55  if (Def->isMachineOpcode()) {
56    const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
57    if (ResNo >= II.getNumDefs() &&
58        II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg)
59      PhysReg = Reg;
60  }
61}
62
63void ScheduleDAGSDNodes::BuildSchedUnits() {
64  // During scheduling, the NodeId field of SDNode is used to map SDNodes
65  // to their associated SUnits by holding SUnits table indices. A value
66  // of -1 means the SDNode does not yet have an associated SUnit.
67  unsigned NumNodes = 0;
68  for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
69       E = DAG->allnodes_end(); NI != E; ++NI) {
70    NI->setNodeId(-1);
71    ++NumNodes;
72  }
73
74  // Reserve entries in the vector for each of the SUnits we are creating.  This
75  // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
76  // invalidated.
77  // FIXME: Multiply by 2 because we may clone nodes during scheduling.
78  // This is a temporary workaround.
79  SUnits.reserve(NumNodes * 2);
80
81  // Check to see if the scheduler cares about latencies.
82  bool UnitLatencies = ForceUnitLatencies();
83
84  for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
85       E = DAG->allnodes_end(); NI != E; ++NI) {
86    if (isPassiveNode(NI))  // Leaf node, e.g. a TargetImmediate.
87      continue;
88
89    // If this node has already been processed, stop now.
90    if (NI->getNodeId() != -1) continue;
91
92    SUnit *NodeSUnit = NewSUnit(NI);
93
94    // See if anything is flagged to this node, if so, add them to flagged
95    // nodes.  Nodes can have at most one flag input and one flag output.  Flags
96    // are required the be the last operand and result of a node.
97
98    // Scan up to find flagged preds.
99    SDNode *N = NI;
100    if (N->getNumOperands() &&
101        N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
102      do {
103        N = N->getOperand(N->getNumOperands()-1).getNode();
104        assert(N->getNodeId() == -1 && "Node already inserted!");
105        N->setNodeId(NodeSUnit->NodeNum);
106      } while (N->getNumOperands() &&
107               N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
108    }
109
110    // Scan down to find any flagged succs.
111    N = NI;
112    while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
113      SDValue FlagVal(N, N->getNumValues()-1);
114
115      // There are either zero or one users of the Flag result.
116      bool HasFlagUse = false;
117      for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
118           UI != E; ++UI)
119        if (FlagVal.isOperandOf(*UI)) {
120          HasFlagUse = true;
121          assert(N->getNodeId() == -1 && "Node already inserted!");
122          N->setNodeId(NodeSUnit->NodeNum);
123          N = *UI;
124          break;
125        }
126      if (!HasFlagUse) break;
127    }
128
129    // If there are flag operands involved, N is now the bottom-most node
130    // of the sequence of nodes that are flagged together.
131    // Update the SUnit.
132    NodeSUnit->setNode(N);
133    assert(N->getNodeId() == -1 && "Node already inserted!");
134    N->setNodeId(NodeSUnit->NodeNum);
135
136    // Assign the Latency field of NodeSUnit using target-provided information.
137    if (UnitLatencies)
138      NodeSUnit->Latency = 1;
139    else
140      ComputeLatency(NodeSUnit);
141  }
142}
143
144void ScheduleDAGSDNodes::AddSchedEdges() {
145  // Pass 2: add the preds, succs, etc.
146  for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
147    SUnit *SU = &SUnits[su];
148    SDNode *MainNode = SU->getNode();
149
150    if (MainNode->isMachineOpcode()) {
151      unsigned Opc = MainNode->getMachineOpcode();
152      const TargetInstrDesc &TID = TII->get(Opc);
153      for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
154        if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
155          SU->isTwoAddress = true;
156          break;
157        }
158      }
159      if (TID.isCommutable())
160        SU->isCommutable = true;
161    }
162
163    // Find all predecessors and successors of the group.
164    for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
165      if (N->isMachineOpcode() &&
166          TII->get(N->getMachineOpcode()).getImplicitDefs() &&
167          CountResults(N) > TII->get(N->getMachineOpcode()).getNumDefs())
168        SU->hasPhysRegDefs = true;
169
170      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
171        SDNode *OpN = N->getOperand(i).getNode();
172        if (isPassiveNode(OpN)) continue;   // Not scheduled.
173        SUnit *OpSU = &SUnits[OpN->getNodeId()];
174        assert(OpSU && "Node has no SUnit!");
175        if (OpSU == SU) continue;           // In the same group.
176
177        MVT OpVT = N->getOperand(i).getValueType();
178        assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
179        bool isChain = OpVT == MVT::Other;
180
181        unsigned PhysReg = 0;
182        // Determine if this is a physical register dependency.
183        CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg);
184        assert((PhysReg == 0 || !isChain) &&
185               "Chain dependence via physreg data?");
186        SU->addPred(SDep(OpSU, isChain ? SDep::Order : SDep::Data,
187                         OpSU->Latency, PhysReg));
188      }
189    }
190  }
191}
192
193/// BuildSchedGraph - Build the SUnit graph from the selection dag that we
194/// are input.  This SUnit graph is similar to the SelectionDAG, but
195/// excludes nodes that aren't interesting to scheduling, and represents
196/// flagged together nodes with a single SUnit.
197void ScheduleDAGSDNodes::BuildSchedGraph() {
198  // Populate the SUnits array.
199  BuildSchedUnits();
200  // Compute all the scheduling dependencies between nodes.
201  AddSchedEdges();
202}
203
204void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
205  const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
206
207  // Compute the latency for the node.  We use the sum of the latencies for
208  // all nodes flagged together into this SUnit.
209  SU->Latency = 0;
210  bool SawMachineOpcode = false;
211  for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
212    if (N->isMachineOpcode()) {
213      SawMachineOpcode = true;
214      SU->Latency +=
215        InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass());
216    }
217}
218
219/// CountResults - The results of target nodes have register or immediate
220/// operands first, then an optional chain, and optional flag operands (which do
221/// not go into the resulting MachineInstr).
222unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) {
223  unsigned N = Node->getNumValues();
224  while (N && Node->getValueType(N - 1) == MVT::Flag)
225    --N;
226  if (N && Node->getValueType(N - 1) == MVT::Other)
227    --N;    // Skip over chain result.
228  return N;
229}
230
231/// CountOperands - The inputs to target nodes have any actual inputs first,
232/// followed by special operands that describe memory references, then an
233/// optional chain operand, then an optional flag operand.  Compute the number
234/// of actual operands that will go into the resulting MachineInstr.
235unsigned ScheduleDAGSDNodes::CountOperands(SDNode *Node) {
236  unsigned N = ComputeMemOperandsEnd(Node);
237  while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).getNode()))
238    --N; // Ignore MEMOPERAND nodes
239  return N;
240}
241
242/// ComputeMemOperandsEnd - Find the index one past the last MemOperandSDNode
243/// operand
244unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
245  unsigned N = Node->getNumOperands();
246  while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
247    --N;
248  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
249    --N; // Ignore chain if it exists.
250  return N;
251}
252
253
254void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
255  if (SU->getNode())
256    SU->getNode()->dump(DAG);
257  else
258    cerr << "CROSS RC COPY ";
259  cerr << "\n";
260  SmallVector<SDNode *, 4> FlaggedNodes;
261  for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
262    FlaggedNodes.push_back(N);
263  while (!FlaggedNodes.empty()) {
264    cerr << "    ";
265    FlaggedNodes.back()->dump(DAG);
266    cerr << "\n";
267    FlaggedNodes.pop_back();
268  }
269}
270