SelectionDAG.cpp revision 32c392a3a5e397b5f1cc83aaedfab96368d11e8a
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/Constants.h" 16#include "llvm/GlobalValue.h" 17#include "llvm/Assembly/Writer.h" 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/Support/MathExtras.h" 20#include "llvm/Target/TargetLowering.h" 21#include <iostream> 22#include <set> 23#include <cmath> 24#include <algorithm> 25using namespace llvm; 26 27static bool isCommutativeBinOp(unsigned Opcode) { 28 switch (Opcode) { 29 case ISD::ADD: 30 case ISD::MUL: 31 case ISD::AND: 32 case ISD::OR: 33 case ISD::XOR: return true; 34 default: return false; // FIXME: Need commutative info for user ops! 35 } 36} 37 38static bool isAssociativeBinOp(unsigned Opcode) { 39 switch (Opcode) { 40 case ISD::ADD: 41 case ISD::MUL: 42 case ISD::AND: 43 case ISD::OR: 44 case ISD::XOR: return true; 45 default: return false; // FIXME: Need associative info for user ops! 46 } 47} 48 49// isInvertibleForFree - Return true if there is no cost to emitting the logical 50// inverse of this node. 51static bool isInvertibleForFree(SDOperand N) { 52 if (isa<ConstantSDNode>(N.Val)) return true; 53 if (N.Val->getOpcode() == ISD::SETCC && N.Val->hasOneUse()) 54 return true; 55 return false; 56} 57 58 59/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 60/// when given the operation for (X op Y). 61ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 62 // To perform this operation, we just need to swap the L and G bits of the 63 // operation. 64 unsigned OldL = (Operation >> 2) & 1; 65 unsigned OldG = (Operation >> 1) & 1; 66 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 67 (OldL << 1) | // New G bit 68 (OldG << 2)); // New L bit. 69} 70 71/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 72/// 'op' is a valid SetCC operation. 73ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 74 unsigned Operation = Op; 75 if (isInteger) 76 Operation ^= 7; // Flip L, G, E bits, but not U. 77 else 78 Operation ^= 15; // Flip all of the condition bits. 79 if (Operation > ISD::SETTRUE2) 80 Operation &= ~8; // Don't let N and U bits get set. 81 return ISD::CondCode(Operation); 82} 83 84 85/// isSignedOp - For an integer comparison, return 1 if the comparison is a 86/// signed operation and 2 if the result is an unsigned comparison. Return zero 87/// if the operation does not depend on the sign of the input (setne and seteq). 88static int isSignedOp(ISD::CondCode Opcode) { 89 switch (Opcode) { 90 default: assert(0 && "Illegal integer setcc operation!"); 91 case ISD::SETEQ: 92 case ISD::SETNE: return 0; 93 case ISD::SETLT: 94 case ISD::SETLE: 95 case ISD::SETGT: 96 case ISD::SETGE: return 1; 97 case ISD::SETULT: 98 case ISD::SETULE: 99 case ISD::SETUGT: 100 case ISD::SETUGE: return 2; 101 } 102} 103 104/// getSetCCOrOperation - Return the result of a logical OR between different 105/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 106/// returns SETCC_INVALID if it is not possible to represent the resultant 107/// comparison. 108ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 109 bool isInteger) { 110 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 111 // Cannot fold a signed integer setcc with an unsigned integer setcc. 112 return ISD::SETCC_INVALID; 113 114 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 115 116 // If the N and U bits get set then the resultant comparison DOES suddenly 117 // care about orderedness, and is true when ordered. 118 if (Op > ISD::SETTRUE2) 119 Op &= ~16; // Clear the N bit. 120 return ISD::CondCode(Op); 121} 122 123/// getSetCCAndOperation - Return the result of a logical AND between different 124/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 125/// function returns zero if it is not possible to represent the resultant 126/// comparison. 127ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 128 bool isInteger) { 129 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 130 // Cannot fold a signed setcc with an unsigned setcc. 131 return ISD::SETCC_INVALID; 132 133 // Combine all of the condition bits. 134 return ISD::CondCode(Op1 & Op2); 135} 136 137const TargetMachine &SelectionDAG::getTarget() const { 138 return TLI.getTargetMachine(); 139} 140 141 142/// RemoveDeadNodes - This method deletes all unreachable nodes in the 143/// SelectionDAG, including nodes (like loads) that have uses of their token 144/// chain but no other uses and no side effect. If a node is passed in as an 145/// argument, it is used as the seed for node deletion. 146void SelectionDAG::RemoveDeadNodes(SDNode *N) { 147 std::set<SDNode*> AllNodeSet(AllNodes.begin(), AllNodes.end()); 148 149 // Create a dummy node (which is not added to allnodes), that adds a reference 150 // to the root node, preventing it from being deleted. 151 SDNode *DummyNode = new SDNode(ISD::EntryToken, getRoot()); 152 153 DeleteNodeIfDead(N, &AllNodeSet); 154 155 Restart: 156 unsigned NumNodes = AllNodeSet.size(); 157 for (std::set<SDNode*>::iterator I = AllNodeSet.begin(), E = AllNodeSet.end(); 158 I != E; ++I) { 159 // Try to delete this node. 160 DeleteNodeIfDead(*I, &AllNodeSet); 161 162 // If we actually deleted any nodes, do not use invalid iterators in 163 // AllNodeSet. 164 if (AllNodeSet.size() != NumNodes) 165 goto Restart; 166 } 167 168 // Restore AllNodes. 169 if (AllNodes.size() != NumNodes) 170 AllNodes.assign(AllNodeSet.begin(), AllNodeSet.end()); 171 172 // If the root changed (e.g. it was a dead load, update the root). 173 setRoot(DummyNode->getOperand(0)); 174 175 // Now that we are done with the dummy node, delete it. 176 DummyNode->getOperand(0).Val->removeUser(DummyNode); 177 delete DummyNode; 178} 179 180void SelectionDAG::DeleteNodeIfDead(SDNode *N, void *NodeSet) { 181 if (!N->use_empty()) 182 return; 183 184 // Okay, we really are going to delete this node. First take this out of the 185 // appropriate CSE map. 186 switch (N->getOpcode()) { 187 case ISD::Constant: 188 Constants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 189 N->getValueType(0))); 190 break; 191 case ISD::ConstantFP: { 192 union { 193 double DV; 194 uint64_t IV; 195 }; 196 DV = cast<ConstantFPSDNode>(N)->getValue(); 197 ConstantFPs.erase(std::make_pair(IV, N->getValueType(0))); 198 break; 199 } 200 case ISD::CONDCODE: 201 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 202 "Cond code doesn't exist!"); 203 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 204 break; 205 case ISD::GlobalAddress: 206 GlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 207 break; 208 case ISD::FrameIndex: 209 FrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex()); 210 break; 211 case ISD::ConstantPool: 212 ConstantPoolIndices.erase(cast<ConstantPoolSDNode>(N)->getIndex()); 213 break; 214 case ISD::BasicBlock: 215 BBNodes.erase(cast<BasicBlockSDNode>(N)->getBasicBlock()); 216 break; 217 case ISD::ExternalSymbol: 218 ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 219 break; 220 case ISD::VALUETYPE: 221 ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0; 222 break; 223 case ISD::SRCVALUE: { 224 SrcValueSDNode *SVN = cast<SrcValueSDNode>(N); 225 ValueNodes.erase(std::make_pair(SVN->getValue(), SVN->getOffset())); 226 break; 227 } 228 case ISD::LOAD: 229 Loads.erase(std::make_pair(N->getOperand(1), 230 std::make_pair(N->getOperand(0), 231 N->getValueType(0)))); 232 break; 233 default: 234 if (N->getNumOperands() == 1) 235 UnaryOps.erase(std::make_pair(N->getOpcode(), 236 std::make_pair(N->getOperand(0), 237 N->getValueType(0)))); 238 else if (N->getNumOperands() == 2) 239 BinaryOps.erase(std::make_pair(N->getOpcode(), 240 std::make_pair(N->getOperand(0), 241 N->getOperand(1)))); 242 else if (N->getNumValues() == 1) { 243 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 244 OneResultNodes.erase(std::make_pair(N->getOpcode(), 245 std::make_pair(N->getValueType(0), 246 Ops))); 247 } else { 248 // Remove the node from the ArbitraryNodes map. 249 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 250 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 251 ArbitraryNodes.erase(std::make_pair(N->getOpcode(), 252 std::make_pair(RV, Ops))); 253 } 254 break; 255 } 256 257 // Next, brutally remove the operand list. 258 while (!N->Operands.empty()) { 259 SDNode *O = N->Operands.back().Val; 260 N->Operands.pop_back(); 261 O->removeUser(N); 262 263 // Now that we removed this operand, see if there are no uses of it left. 264 DeleteNodeIfDead(O, NodeSet); 265 } 266 267 // Remove the node from the nodes set and delete it. 268 std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet; 269 AllNodeSet.erase(N); 270 271 // Now that the node is gone, check to see if any of the operands of this node 272 // are dead now. 273 delete N; 274} 275 276 277SelectionDAG::~SelectionDAG() { 278 for (unsigned i = 0, e = AllNodes.size(); i != e; ++i) 279 delete AllNodes[i]; 280} 281 282SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT::ValueType VT) { 283 if (Op.getValueType() == VT) return Op; 284 int64_t Imm = ~0ULL >> (64-MVT::getSizeInBits(VT)); 285 return getNode(ISD::AND, Op.getValueType(), Op, 286 getConstant(Imm, Op.getValueType())); 287} 288 289SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) { 290 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 291 // Mask out any bits that are not valid for this constant. 292 if (VT != MVT::i64) 293 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 294 295 SDNode *&N = Constants[std::make_pair(Val, VT)]; 296 if (N) return SDOperand(N, 0); 297 N = new ConstantSDNode(Val, VT); 298 AllNodes.push_back(N); 299 return SDOperand(N, 0); 300} 301 302SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT) { 303 assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!"); 304 if (VT == MVT::f32) 305 Val = (float)Val; // Mask out extra precision. 306 307 // Do the map lookup using the actual bit pattern for the floating point 308 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 309 // we don't have issues with SNANs. 310 union { 311 double DV; 312 uint64_t IV; 313 }; 314 315 DV = Val; 316 317 SDNode *&N = ConstantFPs[std::make_pair(IV, VT)]; 318 if (N) return SDOperand(N, 0); 319 N = new ConstantFPSDNode(Val, VT); 320 AllNodes.push_back(N); 321 return SDOperand(N, 0); 322} 323 324 325 326SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV, 327 MVT::ValueType VT) { 328 SDNode *&N = GlobalValues[GV]; 329 if (N) return SDOperand(N, 0); 330 N = new GlobalAddressSDNode(GV,VT); 331 AllNodes.push_back(N); 332 return SDOperand(N, 0); 333} 334 335SDOperand SelectionDAG::getFrameIndex(int FI, MVT::ValueType VT) { 336 SDNode *&N = FrameIndices[FI]; 337 if (N) return SDOperand(N, 0); 338 N = new FrameIndexSDNode(FI, VT); 339 AllNodes.push_back(N); 340 return SDOperand(N, 0); 341} 342 343SDOperand SelectionDAG::getConstantPool(unsigned CPIdx, MVT::ValueType VT) { 344 SDNode *N = ConstantPoolIndices[CPIdx]; 345 if (N) return SDOperand(N, 0); 346 N = new ConstantPoolSDNode(CPIdx, VT); 347 AllNodes.push_back(N); 348 return SDOperand(N, 0); 349} 350 351SDOperand SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 352 SDNode *&N = BBNodes[MBB]; 353 if (N) return SDOperand(N, 0); 354 N = new BasicBlockSDNode(MBB); 355 AllNodes.push_back(N); 356 return SDOperand(N, 0); 357} 358 359SDOperand SelectionDAG::getValueType(MVT::ValueType VT) { 360 if ((unsigned)VT >= ValueTypeNodes.size()) 361 ValueTypeNodes.resize(VT+1); 362 if (ValueTypeNodes[VT] == 0) { 363 ValueTypeNodes[VT] = new VTSDNode(VT); 364 AllNodes.push_back(ValueTypeNodes[VT]); 365 } 366 367 return SDOperand(ValueTypeNodes[VT], 0); 368} 369 370SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT::ValueType VT) { 371 SDNode *&N = ExternalSymbols[Sym]; 372 if (N) return SDOperand(N, 0); 373 N = new ExternalSymbolSDNode(Sym, VT); 374 AllNodes.push_back(N); 375 return SDOperand(N, 0); 376} 377 378SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) { 379 if ((unsigned)Cond >= CondCodeNodes.size()) 380 CondCodeNodes.resize(Cond+1); 381 382 if (CondCodeNodes[Cond] == 0) { 383 CondCodeNodes[Cond] = new CondCodeSDNode(Cond); 384 AllNodes.push_back(CondCodeNodes[Cond]); 385 } 386 return SDOperand(CondCodeNodes[Cond], 0); 387} 388 389SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1, 390 SDOperand N2, ISD::CondCode Cond) { 391 // These setcc operations always fold. 392 switch (Cond) { 393 default: break; 394 case ISD::SETFALSE: 395 case ISD::SETFALSE2: return getConstant(0, VT); 396 case ISD::SETTRUE: 397 case ISD::SETTRUE2: return getConstant(1, VT); 398 } 399 400 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) { 401 uint64_t C2 = N2C->getValue(); 402 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 403 uint64_t C1 = N1C->getValue(); 404 405 // Sign extend the operands if required 406 if (ISD::isSignedIntSetCC(Cond)) { 407 C1 = N1C->getSignExtended(); 408 C2 = N2C->getSignExtended(); 409 } 410 411 switch (Cond) { 412 default: assert(0 && "Unknown integer setcc!"); 413 case ISD::SETEQ: return getConstant(C1 == C2, VT); 414 case ISD::SETNE: return getConstant(C1 != C2, VT); 415 case ISD::SETULT: return getConstant(C1 < C2, VT); 416 case ISD::SETUGT: return getConstant(C1 > C2, VT); 417 case ISD::SETULE: return getConstant(C1 <= C2, VT); 418 case ISD::SETUGE: return getConstant(C1 >= C2, VT); 419 case ISD::SETLT: return getConstant((int64_t)C1 < (int64_t)C2, VT); 420 case ISD::SETGT: return getConstant((int64_t)C1 > (int64_t)C2, VT); 421 case ISD::SETLE: return getConstant((int64_t)C1 <= (int64_t)C2, VT); 422 case ISD::SETGE: return getConstant((int64_t)C1 >= (int64_t)C2, VT); 423 } 424 } else { 425 // If the LHS is a ZERO_EXTEND and if this is an ==/!= comparison, perform 426 // the comparison on the input. 427 if (N1.getOpcode() == ISD::ZERO_EXTEND) { 428 unsigned InSize = MVT::getSizeInBits(N1.getOperand(0).getValueType()); 429 430 // If the comparison constant has bits in the upper part, the 431 // zero-extended value could never match. 432 if (C2 & (~0ULL << InSize)) { 433 unsigned VSize = MVT::getSizeInBits(N1.getValueType()); 434 switch (Cond) { 435 case ISD::SETUGT: 436 case ISD::SETUGE: 437 case ISD::SETEQ: return getConstant(0, VT); 438 case ISD::SETULT: 439 case ISD::SETULE: 440 case ISD::SETNE: return getConstant(1, VT); 441 case ISD::SETGT: 442 case ISD::SETGE: 443 // True if the sign bit of C2 is set. 444 return getConstant((C2 & (1ULL << VSize)) != 0, VT); 445 case ISD::SETLT: 446 case ISD::SETLE: 447 // True if the sign bit of C2 isn't set. 448 return getConstant((C2 & (1ULL << VSize)) == 0, VT); 449 default: 450 break; 451 } 452 } 453 454 // Otherwise, we can perform the comparison with the low bits. 455 switch (Cond) { 456 case ISD::SETEQ: 457 case ISD::SETNE: 458 case ISD::SETUGT: 459 case ISD::SETUGE: 460 case ISD::SETULT: 461 case ISD::SETULE: 462 return getSetCC(VT, N1.getOperand(0), 463 getConstant(C2, N1.getOperand(0).getValueType()), 464 Cond); 465 default: 466 break; // todo, be more careful with signed comparisons 467 } 468 } 469 470 uint64_t MinVal, MaxVal; 471 unsigned OperandBitSize = MVT::getSizeInBits(N2C->getValueType(0)); 472 if (ISD::isSignedIntSetCC(Cond)) { 473 MinVal = 1ULL << (OperandBitSize-1); 474 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 475 MaxVal = ~0ULL >> (65-OperandBitSize); 476 else 477 MaxVal = 0; 478 } else { 479 MinVal = 0; 480 MaxVal = ~0ULL >> (64-OperandBitSize); 481 } 482 483 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 484 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 485 if (C2 == MinVal) return getConstant(1, VT); // X >= MIN --> true 486 --C2; // X >= C1 --> X > (C1-1) 487 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 488 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 489 } 490 491 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 492 if (C2 == MaxVal) return getConstant(1, VT); // X <= MAX --> true 493 ++C2; // X <= C1 --> X < (C1+1) 494 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 495 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 496 } 497 498 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal) 499 return getConstant(0, VT); // X < MIN --> false 500 501 // Canonicalize setgt X, Min --> setne X, Min 502 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal) 503 return getSetCC(VT, N1, N2, ISD::SETNE); 504 505 // If we have setult X, 1, turn it into seteq X, 0 506 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1) 507 return getSetCC(VT, N1, getConstant(MinVal, N1.getValueType()), 508 ISD::SETEQ); 509 // If we have setugt X, Max-1, turn it into seteq X, Max 510 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MaxVal-1) 511 return getSetCC(VT, N1, getConstant(MaxVal, N1.getValueType()), 512 ISD::SETEQ); 513 514 // If we have "setcc X, C1", check to see if we can shrink the immediate 515 // by changing cc. 516 517 // SETUGT X, SINTMAX -> SETLT X, 0 518 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 519 C2 == (~0ULL >> (65-OperandBitSize))) 520 return getSetCC(VT, N1, getConstant(0, N2.getValueType()), ISD::SETLT); 521 522 // FIXME: Implement the rest of these. 523 524 525 // Fold bit comparisons when we can. 526 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 527 VT == N1.getValueType() && N1.getOpcode() == ISD::AND) 528 if (ConstantSDNode *AndRHS = 529 dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 530 if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 531 // Perform the xform if the AND RHS is a single bit. 532 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 533 return getNode(ISD::SRL, VT, N1, 534 getConstant(Log2_64(AndRHS->getValue()), 535 TLI.getShiftAmountTy())); 536 } 537 } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) { 538 // (X & 8) == 8 --> (X & 8) >> 3 539 // Perform the xform if C2 is a single bit. 540 if ((C2 & (C2-1)) == 0) { 541 return getNode(ISD::SRL, VT, N1, 542 getConstant(Log2_64(C2),TLI.getShiftAmountTy())); 543 } 544 } 545 } 546 } 547 } else if (isa<ConstantSDNode>(N1.Val)) { 548 // Ensure that the constant occurs on the RHS. 549 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 550 } 551 552 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) 553 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) { 554 double C1 = N1C->getValue(), C2 = N2C->getValue(); 555 556 switch (Cond) { 557 default: break; // FIXME: Implement the rest of these! 558 case ISD::SETEQ: return getConstant(C1 == C2, VT); 559 case ISD::SETNE: return getConstant(C1 != C2, VT); 560 case ISD::SETLT: return getConstant(C1 < C2, VT); 561 case ISD::SETGT: return getConstant(C1 > C2, VT); 562 case ISD::SETLE: return getConstant(C1 <= C2, VT); 563 case ISD::SETGE: return getConstant(C1 >= C2, VT); 564 } 565 } else { 566 // Ensure that the constant occurs on the RHS. 567 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 568 } 569 570 if (N1 == N2) { 571 // We can always fold X == Y for integer setcc's. 572 if (MVT::isInteger(N1.getValueType())) 573 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 574 unsigned UOF = ISD::getUnorderedFlavor(Cond); 575 if (UOF == 2) // FP operators that are undefined on NaNs. 576 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 577 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 578 return getConstant(UOF, VT); 579 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 580 // if it is not already. 581 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 582 if (NewCond != Cond) 583 return getSetCC(VT, N1, N2, NewCond); 584 } 585 586 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 587 MVT::isInteger(N1.getValueType())) { 588 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 589 N1.getOpcode() == ISD::XOR) { 590 // Simplify (X+Y) == (X+Z) --> Y == Z 591 if (N1.getOpcode() == N2.getOpcode()) { 592 if (N1.getOperand(0) == N2.getOperand(0)) 593 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 594 if (N1.getOperand(1) == N2.getOperand(1)) 595 return getSetCC(VT, N1.getOperand(0), N2.getOperand(0), Cond); 596 if (isCommutativeBinOp(N1.getOpcode())) { 597 // If X op Y == Y op X, try other combinations. 598 if (N1.getOperand(0) == N2.getOperand(1)) 599 return getSetCC(VT, N1.getOperand(1), N2.getOperand(0), Cond); 600 if (N1.getOperand(1) == N2.getOperand(0)) 601 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 602 } 603 } 604 605 // FIXME: move this stuff to the DAG Combiner when it exists! 606 607 // Simplify (X+Z) == X --> Z == 0 608 if (N1.getOperand(0) == N2) 609 return getSetCC(VT, N1.getOperand(1), 610 getConstant(0, N1.getValueType()), Cond); 611 if (N1.getOperand(1) == N2) { 612 if (isCommutativeBinOp(N1.getOpcode())) 613 return getSetCC(VT, N1.getOperand(0), 614 getConstant(0, N1.getValueType()), Cond); 615 else { 616 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 617 // (Z-X) == X --> Z == X<<1 618 return getSetCC(VT, N1.getOperand(0), 619 getNode(ISD::SHL, N2.getValueType(), 620 N2, getConstant(1, TLI.getShiftAmountTy())), 621 Cond); 622 } 623 } 624 } 625 626 if (N2.getOpcode() == ISD::ADD || N2.getOpcode() == ISD::SUB || 627 N2.getOpcode() == ISD::XOR) { 628 // Simplify X == (X+Z) --> Z == 0 629 if (N2.getOperand(0) == N1) { 630 return getSetCC(VT, N2.getOperand(1), 631 getConstant(0, N2.getValueType()), Cond); 632 } else if (N2.getOperand(1) == N1) { 633 if (isCommutativeBinOp(N2.getOpcode())) { 634 return getSetCC(VT, N2.getOperand(0), 635 getConstant(0, N2.getValueType()), Cond); 636 } else { 637 assert(N2.getOpcode() == ISD::SUB && "Unexpected operation!"); 638 // X == (Z-X) --> X<<1 == Z 639 return getSetCC(VT, getNode(ISD::SHL, N2.getValueType(), N1, 640 getConstant(1, TLI.getShiftAmountTy())), 641 N2.getOperand(0), Cond); 642 } 643 } 644 } 645 } 646 647 // Fold away ALL boolean setcc's. 648 if (N1.getValueType() == MVT::i1) { 649 switch (Cond) { 650 default: assert(0 && "Unknown integer setcc!"); 651 case ISD::SETEQ: // X == Y -> (X^Y)^1 652 N1 = getNode(ISD::XOR, MVT::i1, 653 getNode(ISD::XOR, MVT::i1, N1, N2), 654 getConstant(1, MVT::i1)); 655 break; 656 case ISD::SETNE: // X != Y --> (X^Y) 657 N1 = getNode(ISD::XOR, MVT::i1, N1, N2); 658 break; 659 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 660 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 661 N1 = getNode(ISD::AND, MVT::i1, N2, 662 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 663 break; 664 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 665 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 666 N1 = getNode(ISD::AND, MVT::i1, N1, 667 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 668 break; 669 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 670 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 671 N1 = getNode(ISD::OR, MVT::i1, N2, 672 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 673 break; 674 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 675 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 676 N1 = getNode(ISD::OR, MVT::i1, N1, 677 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 678 break; 679 } 680 if (VT != MVT::i1) 681 N1 = getNode(ISD::ZERO_EXTEND, VT, N1); 682 return N1; 683 } 684 685 // Could not fold it. 686 return SDOperand(); 687} 688 689SDOperand SelectionDAG::SimplifySelectCC(MVT::ValueType VT, ISD::CondCode CC, 690 SDOperand N1, SDOperand N2, SDOperand N3, 691 SDOperand N4) { 692 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 693 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 694 ConstantSDNode *N4C = dyn_cast<ConstantSDNode>(N4.Val); 695 696 // Check to see if we can simplify the select into an fabs node 697 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) { 698 // Allow either -0.0 or 0.0 699 if (CFP->getValue() == 0.0) { 700 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 701 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 702 N1 == N3 && N4.getOpcode() == ISD::FNEG && 703 N1 == N4.getOperand(0)) 704 return getNode(ISD::FABS, VT, N1); 705 706 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 707 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 708 N1 == N4 && N3.getOpcode() == ISD::FNEG && 709 N3.getOperand(0) == N4) 710 return getNode(ISD::FABS, VT, N4); 711 } 712 } 713 714 // Check to see if we can perform the "gzip trick", transforming 715 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 716 if (N2C && N2C->isNullValue() && N4C && N4C->isNullValue() && 717 MVT::isInteger(N1.getValueType()) && 718 MVT::isInteger(N3.getValueType()) && CC == ISD::SETLT) { 719 MVT::ValueType XType = N1.getValueType(); 720 MVT::ValueType AType = N3.getValueType(); 721 if (XType >= AType) { 722 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 723 // single-bit constant. FIXME: remove once the dag combiner 724 // exists. 725 if (N3C && ((N3C->getValue() & (N3C->getValue()-1)) == 0)) { 726 unsigned ShCtV = Log2_64(N3C->getValue()); 727 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 728 SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy()); 729 SDOperand Shift = getNode(ISD::SRL, XType, N1, ShCt); 730 if (XType > AType) 731 Shift = getNode(ISD::TRUNCATE, AType, Shift); 732 return getNode(ISD::AND, AType, Shift, N3); 733 } 734 SDOperand Shift = getNode(ISD::SRA, XType, N1, 735 getConstant(MVT::getSizeInBits(XType)-1, 736 TLI.getShiftAmountTy())); 737 if (XType > AType) 738 Shift = getNode(ISD::TRUNCATE, AType, Shift); 739 return getNode(ISD::AND, AType, Shift, N3); 740 } 741 } 742 743 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 744 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 745 if (N2C && N2C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 746 N1 == N4 && N3.getOpcode() == ISD::SUB && N1 == N3.getOperand(1)) { 747 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 748 MVT::ValueType XType = N1.getValueType(); 749 if (SubC->isNullValue() && MVT::isInteger(XType)) { 750 SDOperand Shift = getNode(ISD::SRA, XType, N1, 751 getConstant(MVT::getSizeInBits(XType)-1, 752 TLI.getShiftAmountTy())); 753 return getNode(ISD::XOR, XType, getNode(ISD::ADD, XType, N1, Shift), 754 Shift); 755 } 756 } 757 } 758 759 // Could not fold it. 760 return SDOperand(); 761} 762 763/// getNode - Gets or creates the specified node. 764/// 765SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) { 766 SDNode *N = new SDNode(Opcode, VT); 767 AllNodes.push_back(N); 768 return SDOperand(N, 0); 769} 770 771SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 772 SDOperand Operand) { 773 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) { 774 uint64_t Val = C->getValue(); 775 switch (Opcode) { 776 default: break; 777 case ISD::SIGN_EXTEND: return getConstant(C->getSignExtended(), VT); 778 case ISD::ZERO_EXTEND: return getConstant(Val, VT); 779 case ISD::TRUNCATE: return getConstant(Val, VT); 780 case ISD::SINT_TO_FP: return getConstantFP(C->getSignExtended(), VT); 781 case ISD::UINT_TO_FP: return getConstantFP(C->getValue(), VT); 782 } 783 } 784 785 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) 786 switch (Opcode) { 787 case ISD::FNEG: 788 return getConstantFP(-C->getValue(), VT); 789 case ISD::FP_ROUND: 790 case ISD::FP_EXTEND: 791 return getConstantFP(C->getValue(), VT); 792 case ISD::FP_TO_SINT: 793 return getConstant((int64_t)C->getValue(), VT); 794 case ISD::FP_TO_UINT: 795 return getConstant((uint64_t)C->getValue(), VT); 796 } 797 798 unsigned OpOpcode = Operand.Val->getOpcode(); 799 switch (Opcode) { 800 case ISD::TokenFactor: 801 return Operand; // Factor of one node? No factor. 802 case ISD::SIGN_EXTEND: 803 if (Operand.getValueType() == VT) return Operand; // noop extension 804 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 805 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 806 break; 807 case ISD::ZERO_EXTEND: 808 if (Operand.getValueType() == VT) return Operand; // noop extension 809 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 810 return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); 811 break; 812 case ISD::TRUNCATE: 813 if (Operand.getValueType() == VT) return Operand; // noop truncate 814 if (OpOpcode == ISD::TRUNCATE) 815 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 816 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) { 817 // If the source is smaller than the dest, we still need an extend. 818 if (Operand.Val->getOperand(0).getValueType() < VT) 819 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 820 else if (Operand.Val->getOperand(0).getValueType() > VT) 821 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 822 else 823 return Operand.Val->getOperand(0); 824 } 825 break; 826 case ISD::FNEG: 827 if (OpOpcode == ISD::SUB) // -(X-Y) -> (Y-X) 828 return getNode(ISD::SUB, VT, Operand.Val->getOperand(1), 829 Operand.Val->getOperand(0)); 830 if (OpOpcode == ISD::FNEG) // --X -> X 831 return Operand.Val->getOperand(0); 832 break; 833 case ISD::FABS: 834 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 835 return getNode(ISD::FABS, VT, Operand.Val->getOperand(0)); 836 break; 837 } 838 839 SDNode *&N = UnaryOps[std::make_pair(Opcode, std::make_pair(Operand, VT))]; 840 if (N) return SDOperand(N, 0); 841 N = new SDNode(Opcode, Operand); 842 N->setValueTypes(VT); 843 AllNodes.push_back(N); 844 return SDOperand(N, 0); 845} 846 847/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 848/// this predicate to simplify operations downstream. V and Mask are known to 849/// be the same type. 850static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 851 const TargetLowering &TLI) { 852 unsigned SrcBits; 853 if (Mask == 0) return true; 854 855 // If we know the result of a setcc has the top bits zero, use this info. 856 switch (Op.getOpcode()) { 857 case ISD::Constant: 858 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 859 860 case ISD::SETCC: 861 return ((Mask & 1) == 0) && 862 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 863 864 case ISD::ZEXTLOAD: 865 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 866 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 867 case ISD::ZERO_EXTEND: 868 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 869 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 870 871 case ISD::AND: 872 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 873 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 874 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 875 876 // FALL THROUGH 877 case ISD::OR: 878 case ISD::XOR: 879 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 880 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 881 case ISD::SELECT: 882 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 883 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 884 885 case ISD::SRL: 886 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 887 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 888 uint64_t NewVal = Mask << ShAmt->getValue(); 889 SrcBits = MVT::getSizeInBits(Op.getValueType()); 890 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 891 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 892 } 893 return false; 894 case ISD::SHL: 895 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 896 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 897 uint64_t NewVal = Mask >> ShAmt->getValue(); 898 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 899 } 900 return false; 901 // TODO we could handle some SRA cases here. 902 default: break; 903 } 904 905 return false; 906} 907 908 909 910SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 911 SDOperand N1, SDOperand N2) { 912#ifndef NDEBUG 913 switch (Opcode) { 914 case ISD::TokenFactor: 915 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 916 N2.getValueType() == MVT::Other && "Invalid token factor!"); 917 break; 918 case ISD::AND: 919 case ISD::OR: 920 case ISD::XOR: 921 case ISD::UDIV: 922 case ISD::UREM: 923 case ISD::MULHU: 924 case ISD::MULHS: 925 assert(MVT::isInteger(VT) && "This operator does not apply to FP types!"); 926 // fall through 927 case ISD::ADD: 928 case ISD::SUB: 929 case ISD::MUL: 930 case ISD::SDIV: 931 case ISD::SREM: 932 assert(N1.getValueType() == N2.getValueType() && 933 N1.getValueType() == VT && "Binary operator types must match!"); 934 break; 935 936 case ISD::SHL: 937 case ISD::SRA: 938 case ISD::SRL: 939 assert(VT == N1.getValueType() && 940 "Shift operators return type must be the same as their first arg"); 941 assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) && 942 VT != MVT::i1 && "Shifts only work on integers"); 943 break; 944 case ISD::FP_ROUND_INREG: { 945 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 946 assert(VT == N1.getValueType() && "Not an inreg round!"); 947 assert(MVT::isFloatingPoint(VT) && MVT::isFloatingPoint(EVT) && 948 "Cannot FP_ROUND_INREG integer types"); 949 assert(EVT <= VT && "Not rounding down!"); 950 break; 951 } 952 case ISD::SIGN_EXTEND_INREG: { 953 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 954 assert(VT == N1.getValueType() && "Not an inreg extend!"); 955 assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && 956 "Cannot *_EXTEND_INREG FP types"); 957 assert(EVT <= VT && "Not extending!"); 958 } 959 960 default: break; 961 } 962#endif 963 964 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 965 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 966 if (N1C) { 967 if (N2C) { 968 uint64_t C1 = N1C->getValue(), C2 = N2C->getValue(); 969 switch (Opcode) { 970 case ISD::ADD: return getConstant(C1 + C2, VT); 971 case ISD::SUB: return getConstant(C1 - C2, VT); 972 case ISD::MUL: return getConstant(C1 * C2, VT); 973 case ISD::UDIV: 974 if (C2) return getConstant(C1 / C2, VT); 975 break; 976 case ISD::UREM : 977 if (C2) return getConstant(C1 % C2, VT); 978 break; 979 case ISD::SDIV : 980 if (C2) return getConstant(N1C->getSignExtended() / 981 N2C->getSignExtended(), VT); 982 break; 983 case ISD::SREM : 984 if (C2) return getConstant(N1C->getSignExtended() % 985 N2C->getSignExtended(), VT); 986 break; 987 case ISD::AND : return getConstant(C1 & C2, VT); 988 case ISD::OR : return getConstant(C1 | C2, VT); 989 case ISD::XOR : return getConstant(C1 ^ C2, VT); 990 case ISD::SHL : return getConstant(C1 << (int)C2, VT); 991 case ISD::SRL : return getConstant(C1 >> (unsigned)C2, VT); 992 case ISD::SRA : return getConstant(N1C->getSignExtended() >>(int)C2, VT); 993 default: break; 994 } 995 996 } else { // Cannonicalize constant to RHS if commutative 997 if (isCommutativeBinOp(Opcode)) { 998 std::swap(N1C, N2C); 999 std::swap(N1, N2); 1000 } 1001 } 1002 1003 switch (Opcode) { 1004 default: break; 1005 case ISD::SHL: // shl 0, X -> 0 1006 if (N1C->isNullValue()) return N1; 1007 break; 1008 case ISD::SRL: // srl 0, X -> 0 1009 if (N1C->isNullValue()) return N1; 1010 break; 1011 case ISD::SRA: // sra -1, X -> -1 1012 if (N1C->isAllOnesValue()) return N1; 1013 break; 1014 case ISD::SIGN_EXTEND_INREG: // SIGN_EXTEND_INREG N1C, EVT 1015 // Extending a constant? Just return the extended constant. 1016 SDOperand Tmp = getNode(ISD::TRUNCATE, cast<VTSDNode>(N2)->getVT(), N1); 1017 return getNode(ISD::SIGN_EXTEND, VT, Tmp); 1018 } 1019 } 1020 1021 if (N2C) { 1022 uint64_t C2 = N2C->getValue(); 1023 1024 switch (Opcode) { 1025 case ISD::ADD: 1026 if (!C2) return N1; // add X, 0 -> X 1027 break; 1028 case ISD::SUB: 1029 if (!C2) return N1; // sub X, 0 -> X 1030 return getNode(ISD::ADD, VT, N1, getConstant(-C2, VT)); 1031 case ISD::MUL: 1032 if (!C2) return N2; // mul X, 0 -> 0 1033 if (N2C->isAllOnesValue()) // mul X, -1 -> 0-X 1034 return getNode(ISD::SUB, VT, getConstant(0, VT), N1); 1035 1036 // FIXME: Move this to the DAG combiner when it exists. 1037 if ((C2 & C2-1) == 0) { 1038 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1039 return getNode(ISD::SHL, VT, N1, ShAmt); 1040 } 1041 break; 1042 1043 case ISD::MULHU: 1044 case ISD::MULHS: 1045 if (!C2) return N2; // mul X, 0 -> 0 1046 1047 if (C2 == 1) // 0X*01 -> 0X hi(0X) == 0 1048 return getConstant(0, VT); 1049 1050 // Many others could be handled here, including -1, powers of 2, etc. 1051 break; 1052 1053 case ISD::UDIV: 1054 // FIXME: Move this to the DAG combiner when it exists. 1055 if ((C2 & C2-1) == 0 && C2) { 1056 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1057 return getNode(ISD::SRL, VT, N1, ShAmt); 1058 } 1059 break; 1060 1061 case ISD::SHL: 1062 case ISD::SRL: 1063 case ISD::SRA: 1064 // If the shift amount is bigger than the size of the data, then all the 1065 // bits are shifted out. Simplify to undef. 1066 if (C2 >= MVT::getSizeInBits(N1.getValueType())) { 1067 return getNode(ISD::UNDEF, N1.getValueType()); 1068 } 1069 if (C2 == 0) return N1; 1070 1071 if (Opcode == ISD::SRA) { 1072 // If the sign bit is known to be zero, switch this to a SRL. 1073 if (MaskedValueIsZero(N1, 1074 1ULL << MVT::getSizeInBits(N1.getValueType())-1, 1075 TLI)) 1076 return getNode(ISD::SRL, N1.getValueType(), N1, N2); 1077 } else { 1078 // If the part left over is known to be zero, the whole thing is zero. 1079 uint64_t TypeMask = ~0ULL >> (64-MVT::getSizeInBits(N1.getValueType())); 1080 if (Opcode == ISD::SRL) { 1081 if (MaskedValueIsZero(N1, TypeMask << C2, TLI)) 1082 return getConstant(0, N1.getValueType()); 1083 } else if (Opcode == ISD::SHL) { 1084 if (MaskedValueIsZero(N1, TypeMask >> C2, TLI)) 1085 return getConstant(0, N1.getValueType()); 1086 } 1087 } 1088 1089 if (Opcode == ISD::SHL && N1.getNumOperands() == 2) 1090 if (ConstantSDNode *OpSA = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1091 unsigned OpSAC = OpSA->getValue(); 1092 if (N1.getOpcode() == ISD::SHL) { 1093 if (C2+OpSAC >= MVT::getSizeInBits(N1.getValueType())) 1094 return getConstant(0, N1.getValueType()); 1095 return getNode(ISD::SHL, N1.getValueType(), N1.getOperand(0), 1096 getConstant(C2+OpSAC, N2.getValueType())); 1097 } else if (N1.getOpcode() == ISD::SRL) { 1098 // (X >> C1) << C2: if C2 > C1, ((X & ~0<<C1) << C2-C1) 1099 SDOperand Mask = getNode(ISD::AND, VT, N1.getOperand(0), 1100 getConstant(~0ULL << OpSAC, VT)); 1101 if (C2 > OpSAC) { 1102 return getNode(ISD::SHL, VT, Mask, 1103 getConstant(C2-OpSAC, N2.getValueType())); 1104 } else { 1105 // (X >> C1) << C2: if C2 <= C1, ((X & ~0<<C1) >> C1-C2) 1106 return getNode(ISD::SRL, VT, Mask, 1107 getConstant(OpSAC-C2, N2.getValueType())); 1108 } 1109 } else if (N1.getOpcode() == ISD::SRA) { 1110 // if C1 == C2, just mask out low bits. 1111 if (C2 == OpSAC) 1112 return getNode(ISD::AND, VT, N1.getOperand(0), 1113 getConstant(~0ULL << C2, VT)); 1114 } 1115 } 1116 break; 1117 1118 case ISD::AND: 1119 if (!C2) return N2; // X and 0 -> 0 1120 if (N2C->isAllOnesValue()) 1121 return N1; // X and -1 -> X 1122 1123 if (MaskedValueIsZero(N1, C2, TLI)) // X and 0 -> 0 1124 return getConstant(0, VT); 1125 1126 { 1127 uint64_t NotC2 = ~C2; 1128 if (VT != MVT::i64) 1129 NotC2 &= (1ULL << MVT::getSizeInBits(VT))-1; 1130 1131 if (MaskedValueIsZero(N1, NotC2, TLI)) 1132 return N1; // if (X & ~C2) -> 0, the and is redundant 1133 } 1134 1135 // FIXME: Should add a corresponding version of this for 1136 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 1137 // we don't have yet. 1138 1139 // and (sign_extend_inreg x:16:32), 1 -> and x, 1 1140 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { 1141 // If we are masking out the part of our input that was extended, just 1142 // mask the input to the extension directly. 1143 unsigned ExtendBits = 1144 MVT::getSizeInBits(cast<VTSDNode>(N1.getOperand(1))->getVT()); 1145 if ((C2 & (~0ULL << ExtendBits)) == 0) 1146 return getNode(ISD::AND, VT, N1.getOperand(0), N2); 1147 } else if (N1.getOpcode() == ISD::OR) { 1148 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 1149 if ((ORI->getValue() & C2) == C2) { 1150 // If the 'or' is setting all of the bits that we are masking for, 1151 // we know the result of the AND will be the AND mask itself. 1152 return N2; 1153 } 1154 } 1155 break; 1156 case ISD::OR: 1157 if (!C2)return N1; // X or 0 -> X 1158 if (N2C->isAllOnesValue()) 1159 return N2; // X or -1 -> -1 1160 break; 1161 case ISD::XOR: 1162 if (!C2) return N1; // X xor 0 -> X 1163 if (N2C->isAllOnesValue()) { 1164 if (N1.Val->getOpcode() == ISD::SETCC){ 1165 SDNode *SetCC = N1.Val; 1166 // !(X op Y) -> (X !op Y) 1167 bool isInteger = MVT::isInteger(SetCC->getOperand(0).getValueType()); 1168 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); 1169 return getSetCC(SetCC->getValueType(0), 1170 SetCC->getOperand(0), SetCC->getOperand(1), 1171 ISD::getSetCCInverse(CC, isInteger)); 1172 } else if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { 1173 SDNode *Op = N1.Val; 1174 // !(X or Y) -> (!X and !Y) iff X or Y are freely invertible 1175 // !(X and Y) -> (!X or !Y) iff X or Y are freely invertible 1176 SDOperand LHS = Op->getOperand(0), RHS = Op->getOperand(1); 1177 if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) { 1178 LHS = getNode(ISD::XOR, VT, LHS, N2); // RHS = ~LHS 1179 RHS = getNode(ISD::XOR, VT, RHS, N2); // RHS = ~RHS 1180 if (Op->getOpcode() == ISD::AND) 1181 return getNode(ISD::OR, VT, LHS, RHS); 1182 return getNode(ISD::AND, VT, LHS, RHS); 1183 } 1184 } 1185 // X xor -1 -> not(x) ? 1186 } 1187 break; 1188 } 1189 1190 // Reassociate ((X op C1) op C2) if possible. 1191 if (N1.getOpcode() == Opcode && isAssociativeBinOp(Opcode)) 1192 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N1.Val->getOperand(1))) 1193 return getNode(Opcode, VT, N1.Val->getOperand(0), 1194 getNode(Opcode, VT, N2, N1.Val->getOperand(1))); 1195 } 1196 1197 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 1198 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val); 1199 if (N1CFP) { 1200 if (N2CFP) { 1201 double C1 = N1CFP->getValue(), C2 = N2CFP->getValue(); 1202 switch (Opcode) { 1203 case ISD::ADD: return getConstantFP(C1 + C2, VT); 1204 case ISD::SUB: return getConstantFP(C1 - C2, VT); 1205 case ISD::MUL: return getConstantFP(C1 * C2, VT); 1206 case ISD::SDIV: 1207 if (C2) return getConstantFP(C1 / C2, VT); 1208 break; 1209 case ISD::SREM : 1210 if (C2) return getConstantFP(fmod(C1, C2), VT); 1211 break; 1212 default: break; 1213 } 1214 1215 } else { // Cannonicalize constant to RHS if commutative 1216 if (isCommutativeBinOp(Opcode)) { 1217 std::swap(N1CFP, N2CFP); 1218 std::swap(N1, N2); 1219 } 1220 } 1221 1222 if (Opcode == ISD::FP_ROUND_INREG) 1223 return getNode(ISD::FP_EXTEND, VT, 1224 getNode(ISD::FP_ROUND, cast<VTSDNode>(N2)->getVT(), N1)); 1225 } 1226 1227 // Finally, fold operations that do not require constants. 1228 switch (Opcode) { 1229 case ISD::TokenFactor: 1230 if (N1.getOpcode() == ISD::EntryToken) 1231 return N2; 1232 if (N2.getOpcode() == ISD::EntryToken) 1233 return N1; 1234 break; 1235 1236 case ISD::AND: 1237 case ISD::OR: 1238 if (N1.Val->getOpcode() == ISD::SETCC && N2.Val->getOpcode() == ISD::SETCC){ 1239 SDNode *LHS = N1.Val, *RHS = N2.Val; 1240 SDOperand LL = LHS->getOperand(0), RL = RHS->getOperand(0); 1241 SDOperand LR = LHS->getOperand(1), RR = RHS->getOperand(1); 1242 ISD::CondCode Op1 = cast<CondCodeSDNode>(LHS->getOperand(2))->get(); 1243 ISD::CondCode Op2 = cast<CondCodeSDNode>(RHS->getOperand(2))->get(); 1244 1245 if (LR == RR && isa<ConstantSDNode>(LR) && 1246 Op2 == Op1 && MVT::isInteger(LL.getValueType())) { 1247 // (X != 0) | (Y != 0) -> (X|Y != 0) 1248 // (X == 0) & (Y == 0) -> (X|Y == 0) 1249 // (X < 0) | (Y < 0) -> (X|Y < 0) 1250 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1251 ((Op2 == ISD::SETEQ && Opcode == ISD::AND) || 1252 (Op2 == ISD::SETNE && Opcode == ISD::OR) || 1253 (Op2 == ISD::SETLT && Opcode == ISD::OR))) 1254 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), LR, 1255 Op2); 1256 1257 if (cast<ConstantSDNode>(LR)->isAllOnesValue()) { 1258 // (X == -1) & (Y == -1) -> (X&Y == -1) 1259 // (X != -1) | (Y != -1) -> (X&Y != -1) 1260 // (X > -1) | (Y > -1) -> (X&Y > -1) 1261 if ((Opcode == ISD::AND && Op2 == ISD::SETEQ) || 1262 (Opcode == ISD::OR && Op2 == ISD::SETNE) || 1263 (Opcode == ISD::OR && Op2 == ISD::SETGT)) 1264 return getSetCC(VT, getNode(ISD::AND, LR.getValueType(), LL, RL), 1265 LR, Op2); 1266 // (X > -1) & (Y > -1) -> (X|Y > -1) 1267 if (Opcode == ISD::AND && Op2 == ISD::SETGT) 1268 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), 1269 LR, Op2); 1270 } 1271 } 1272 1273 // (X op1 Y) | (Y op2 X) -> (X op1 Y) | (X swapop2 Y) 1274 if (LL == RR && LR == RL) { 1275 Op2 = ISD::getSetCCSwappedOperands(Op2); 1276 goto MatchedBackwards; 1277 } 1278 1279 if (LL == RL && LR == RR) { 1280 MatchedBackwards: 1281 ISD::CondCode Result; 1282 bool isInteger = MVT::isInteger(LL.getValueType()); 1283 if (Opcode == ISD::OR) 1284 Result = ISD::getSetCCOrOperation(Op1, Op2, isInteger); 1285 else 1286 Result = ISD::getSetCCAndOperation(Op1, Op2, isInteger); 1287 1288 if (Result != ISD::SETCC_INVALID) 1289 return getSetCC(LHS->getValueType(0), LL, LR, Result); 1290 } 1291 } 1292 1293 // and/or zext(a), zext(b) -> zext(and/or a, b) 1294 if (N1.getOpcode() == ISD::ZERO_EXTEND && 1295 N2.getOpcode() == ISD::ZERO_EXTEND && 1296 N1.getOperand(0).getValueType() == N2.getOperand(0).getValueType()) 1297 return getNode(ISD::ZERO_EXTEND, VT, 1298 getNode(Opcode, N1.getOperand(0).getValueType(), 1299 N1.getOperand(0), N2.getOperand(0))); 1300 break; 1301 case ISD::XOR: 1302 if (N1 == N2) return getConstant(0, VT); // xor X, Y -> 0 1303 break; 1304 case ISD::ADD: 1305 if (N2.getOpcode() == ISD::FNEG) // (A+ (-B) -> A-B 1306 return getNode(ISD::SUB, VT, N1, N2.getOperand(0)); 1307 if (N1.getOpcode() == ISD::FNEG) // ((-A)+B) -> B-A 1308 return getNode(ISD::SUB, VT, N2, N1.getOperand(0)); 1309 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1310 cast<ConstantSDNode>(N1.getOperand(0))->getValue() == 0) 1311 return getNode(ISD::SUB, VT, N2, N1.getOperand(1)); // (0-A)+B -> B-A 1312 if (N2.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N2.getOperand(0)) && 1313 cast<ConstantSDNode>(N2.getOperand(0))->getValue() == 0) 1314 return getNode(ISD::SUB, VT, N1, N2.getOperand(1)); // A+(0-B) -> A-B 1315 if (N2.getOpcode() == ISD::SUB && N1 == N2.Val->getOperand(1) && 1316 !MVT::isFloatingPoint(N2.getValueType())) 1317 return N2.Val->getOperand(0); // A+(B-A) -> B 1318 break; 1319 case ISD::SUB: 1320 if (N1.getOpcode() == ISD::ADD) { 1321 if (N1.Val->getOperand(0) == N2 && 1322 !MVT::isFloatingPoint(N2.getValueType())) 1323 return N1.Val->getOperand(1); // (A+B)-A == B 1324 if (N1.Val->getOperand(1) == N2 && 1325 !MVT::isFloatingPoint(N2.getValueType())) 1326 return N1.Val->getOperand(0); // (A+B)-B == A 1327 } 1328 if (N2.getOpcode() == ISD::FNEG) // (A- (-B) -> A+B 1329 return getNode(ISD::ADD, VT, N1, N2.getOperand(0)); 1330 break; 1331 case ISD::FP_ROUND_INREG: 1332 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 1333 break; 1334 case ISD::SIGN_EXTEND_INREG: { 1335 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1336 if (EVT == VT) return N1; // Not actually extending 1337 1338 // If we are sign extending an extension, use the original source. 1339 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) 1340 if (cast<VTSDNode>(N1.getOperand(1))->getVT() <= EVT) 1341 return N1; 1342 1343 // If we are sign extending a sextload, return just the load. 1344 if (N1.getOpcode() == ISD::SEXTLOAD) 1345 if (cast<VTSDNode>(N1.getOperand(3))->getVT() <= EVT) 1346 return N1; 1347 1348 // If we are extending the result of a setcc, and we already know the 1349 // contents of the top bits, eliminate the extension. 1350 if (N1.getOpcode() == ISD::SETCC && 1351 TLI.getSetCCResultContents() == 1352 TargetLowering::ZeroOrNegativeOneSetCCResult) 1353 return N1; 1354 1355 // If we are sign extending the result of an (and X, C) operation, and we 1356 // know the extended bits are zeros already, don't do the extend. 1357 if (N1.getOpcode() == ISD::AND) 1358 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1359 uint64_t Mask = N1C->getValue(); 1360 unsigned NumBits = MVT::getSizeInBits(EVT); 1361 if ((Mask & (~0ULL << (NumBits-1))) == 0) 1362 return N1; 1363 } 1364 break; 1365 } 1366 1367 // FIXME: figure out how to safely handle things like 1368 // int foo(int x) { return 1 << (x & 255); } 1369 // int bar() { return foo(256); } 1370#if 0 1371 case ISD::SHL: 1372 case ISD::SRL: 1373 case ISD::SRA: 1374 if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG && 1375 cast<VTSDNode>(N2.getOperand(1))->getVT() != MVT::i1) 1376 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1377 else if (N2.getOpcode() == ISD::AND) 1378 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) { 1379 // If the and is only masking out bits that cannot effect the shift, 1380 // eliminate the and. 1381 unsigned NumBits = MVT::getSizeInBits(VT); 1382 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1383 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1384 } 1385 break; 1386#endif 1387 } 1388 1389 // Memoize this node if possible. 1390 SDNode *N; 1391 if (Opcode != ISD::CALLSEQ_START && Opcode != ISD::CALLSEQ_END) { 1392 SDNode *&BON = BinaryOps[std::make_pair(Opcode, std::make_pair(N1, N2))]; 1393 if (BON) return SDOperand(BON, 0); 1394 1395 BON = N = new SDNode(Opcode, N1, N2); 1396 } else { 1397 N = new SDNode(Opcode, N1, N2); 1398 } 1399 1400 N->setValueTypes(VT); 1401 AllNodes.push_back(N); 1402 return SDOperand(N, 0); 1403} 1404 1405// setAdjCallChain - This method changes the token chain of an 1406// CALLSEQ_START/END node to be the specified operand. 1407void SDNode::setAdjCallChain(SDOperand N) { 1408 assert(N.getValueType() == MVT::Other); 1409 assert((getOpcode() == ISD::CALLSEQ_START || 1410 getOpcode() == ISD::CALLSEQ_END) && "Cannot adjust this node!"); 1411 1412 Operands[0].Val->removeUser(this); 1413 Operands[0] = N; 1414 N.Val->Uses.push_back(this); 1415} 1416 1417 1418 1419SDOperand SelectionDAG::getLoad(MVT::ValueType VT, 1420 SDOperand Chain, SDOperand Ptr, 1421 SDOperand SV) { 1422 SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))]; 1423 if (N) return SDOperand(N, 0); 1424 N = new SDNode(ISD::LOAD, Chain, Ptr, SV); 1425 1426 // Loads have a token chain. 1427 N->setValueTypes(VT, MVT::Other); 1428 AllNodes.push_back(N); 1429 return SDOperand(N, 0); 1430} 1431 1432 1433SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT, 1434 SDOperand Chain, SDOperand Ptr, SDOperand SV, 1435 MVT::ValueType EVT) { 1436 std::vector<SDOperand> Ops; 1437 Ops.reserve(4); 1438 Ops.push_back(Chain); 1439 Ops.push_back(Ptr); 1440 Ops.push_back(SV); 1441 Ops.push_back(getValueType(EVT)); 1442 std::vector<MVT::ValueType> VTs; 1443 VTs.reserve(2); 1444 VTs.push_back(VT); VTs.push_back(MVT::Other); // Add token chain. 1445 return getNode(Opcode, VTs, Ops); 1446} 1447 1448SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1449 SDOperand N1, SDOperand N2, SDOperand N3) { 1450 // Perform various simplifications. 1451 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1452 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1453 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1454 switch (Opcode) { 1455 case ISD::SETCC: { 1456 // Use SimplifySetCC to simplify SETCC's. 1457 SDOperand Simp = SimplifySetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 1458 if (Simp.Val) return Simp; 1459 break; 1460 } 1461 case ISD::SELECT: 1462 if (N1C) 1463 if (N1C->getValue()) 1464 return N2; // select true, X, Y -> X 1465 else 1466 return N3; // select false, X, Y -> Y 1467 1468 if (N2 == N3) return N2; // select C, X, X -> X 1469 1470 if (VT == MVT::i1) { // Boolean SELECT 1471 if (N2C) { 1472 if (N2C->getValue()) // select C, 1, X -> C | X 1473 return getNode(ISD::OR, VT, N1, N3); 1474 else // select C, 0, X -> ~C & X 1475 return getNode(ISD::AND, VT, 1476 getNode(ISD::XOR, N1.getValueType(), N1, 1477 getConstant(1, N1.getValueType())), N3); 1478 } else if (N3C) { 1479 if (N3C->getValue()) // select C, X, 1 -> ~C | X 1480 return getNode(ISD::OR, VT, 1481 getNode(ISD::XOR, N1.getValueType(), N1, 1482 getConstant(1, N1.getValueType())), N2); 1483 else // select C, X, 0 -> C & X 1484 return getNode(ISD::AND, VT, N1, N2); 1485 } 1486 1487 if (N1 == N2) // X ? X : Y --> X ? 1 : Y --> X | Y 1488 return getNode(ISD::OR, VT, N1, N3); 1489 if (N1 == N3) // X ? Y : X --> X ? Y : 0 --> X & Y 1490 return getNode(ISD::AND, VT, N1, N2); 1491 } 1492 if (N1.getOpcode() == ISD::SETCC) { 1493 SDOperand Simp = SimplifySelectCC(VT, 1494 cast<CondCodeSDNode>(N1.getOperand(2))->get(), 1495 N1.getOperand(0), N1.getOperand(1), N2, N3); 1496 if (Simp.Val) return Simp; 1497 } 1498 break; 1499 case ISD::BRCOND: 1500 if (N2C) 1501 if (N2C->getValue()) // Unconditional branch 1502 return getNode(ISD::BR, MVT::Other, N1, N3); 1503 else 1504 return N1; // Never-taken branch 1505 break; 1506 } 1507 1508 std::vector<SDOperand> Ops; 1509 Ops.reserve(3); 1510 Ops.push_back(N1); 1511 Ops.push_back(N2); 1512 Ops.push_back(N3); 1513 1514 // Memoize nodes. 1515 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1516 if (N) return SDOperand(N, 0); 1517 1518 N = new SDNode(Opcode, N1, N2, N3); 1519 N->setValueTypes(VT); 1520 AllNodes.push_back(N); 1521 return SDOperand(N, 0); 1522} 1523 1524SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1525 SDOperand N1, SDOperand N2, SDOperand N3, 1526 SDOperand N4) { 1527 std::vector<SDOperand> Ops; 1528 Ops.reserve(4); 1529 Ops.push_back(N1); 1530 Ops.push_back(N2); 1531 Ops.push_back(N3); 1532 Ops.push_back(N4); 1533 return getNode(Opcode, VT, Ops); 1534} 1535 1536SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1537 SDOperand N1, SDOperand N2, SDOperand N3, 1538 SDOperand N4, SDOperand N5) { 1539 if (ISD::SELECT_CC == Opcode) { 1540 assert(N1.getValueType() == N2.getValueType() && 1541 "LHS and RHS of condition must have same type!"); 1542 assert(N3.getValueType() == N4.getValueType() && 1543 "True and False arms of SelectCC must have same type!"); 1544 SDOperand Simp = SimplifySelectCC(VT, cast<CondCodeSDNode>(N5)->get(), N1, 1545 N2, N3, N4); 1546 if (Simp.Val) return Simp; 1547 } 1548 1549 std::vector<SDOperand> Ops; 1550 Ops.reserve(5); 1551 Ops.push_back(N1); 1552 Ops.push_back(N2); 1553 Ops.push_back(N3); 1554 Ops.push_back(N4); 1555 Ops.push_back(N5); 1556 return getNode(Opcode, VT, Ops); 1557} 1558 1559 1560SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { 1561 assert((!V || isa<PointerType>(V->getType())) && 1562 "SrcValue is not a pointer?"); 1563 SDNode *&N = ValueNodes[std::make_pair(V, Offset)]; 1564 if (N) return SDOperand(N, 0); 1565 1566 N = new SrcValueSDNode(V, Offset); 1567 AllNodes.push_back(N); 1568 return SDOperand(N, 0); 1569} 1570 1571SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1572 std::vector<SDOperand> &Ops) { 1573 switch (Ops.size()) { 1574 case 0: return getNode(Opcode, VT); 1575 case 1: return getNode(Opcode, VT, Ops[0]); 1576 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 1577 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 1578 default: break; 1579 } 1580 1581 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Ops[1].Val); 1582 switch (Opcode) { 1583 default: break; 1584 case ISD::BRCONDTWOWAY: 1585 if (N1C) 1586 if (N1C->getValue()) // Unconditional branch to true dest. 1587 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[2]); 1588 else // Unconditional branch to false dest. 1589 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]); 1590 break; 1591 1592 case ISD::TRUNCSTORE: { 1593 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1594 MVT::ValueType EVT = cast<VTSDNode>(Ops[4])->getVT(); 1595#if 0 // FIXME: If the target supports EVT natively, convert to a truncate/store 1596 // If this is a truncating store of a constant, convert to the desired type 1597 // and store it instead. 1598 if (isa<Constant>(Ops[0])) { 1599 SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1); 1600 if (isa<Constant>(Op)) 1601 N1 = Op; 1602 } 1603 // Also for ConstantFP? 1604#endif 1605 if (Ops[0].getValueType() == EVT) // Normal store? 1606 return getNode(ISD::STORE, VT, Ops[0], Ops[1], Ops[2], Ops[3]); 1607 assert(Ops[1].getValueType() > EVT && "Not a truncation?"); 1608 assert(MVT::isInteger(Ops[1].getValueType()) == MVT::isInteger(EVT) && 1609 "Can't do FP-INT conversion!"); 1610 break; 1611 } 1612 } 1613 1614 // Memoize nodes. 1615 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1616 if (N) return SDOperand(N, 0); 1617 N = new SDNode(Opcode, Ops); 1618 N->setValueTypes(VT); 1619 AllNodes.push_back(N); 1620 return SDOperand(N, 0); 1621} 1622 1623SDOperand SelectionDAG::getNode(unsigned Opcode, 1624 std::vector<MVT::ValueType> &ResultTys, 1625 std::vector<SDOperand> &Ops) { 1626 if (ResultTys.size() == 1) 1627 return getNode(Opcode, ResultTys[0], Ops); 1628 1629 switch (Opcode) { 1630 case ISD::EXTLOAD: 1631 case ISD::SEXTLOAD: 1632 case ISD::ZEXTLOAD: { 1633 MVT::ValueType EVT = cast<VTSDNode>(Ops[3])->getVT(); 1634 assert(Ops.size() == 4 && ResultTys.size() == 2 && "Bad *EXTLOAD!"); 1635 // If they are asking for an extending load from/to the same thing, return a 1636 // normal load. 1637 if (ResultTys[0] == EVT) 1638 return getLoad(ResultTys[0], Ops[0], Ops[1], Ops[2]); 1639 assert(EVT < ResultTys[0] && 1640 "Should only be an extending load, not truncating!"); 1641 assert((Opcode == ISD::EXTLOAD || MVT::isInteger(ResultTys[0])) && 1642 "Cannot sign/zero extend a FP load!"); 1643 assert(MVT::isInteger(ResultTys[0]) == MVT::isInteger(EVT) && 1644 "Cannot convert from FP to Int or Int -> FP!"); 1645 break; 1646 } 1647 1648 // FIXME: figure out how to safely handle things like 1649 // int foo(int x) { return 1 << (x & 255); } 1650 // int bar() { return foo(256); } 1651#if 0 1652 case ISD::SRA_PARTS: 1653 case ISD::SRL_PARTS: 1654 case ISD::SHL_PARTS: 1655 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 1656 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 1657 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1658 else if (N3.getOpcode() == ISD::AND) 1659 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 1660 // If the and is only masking out bits that cannot effect the shift, 1661 // eliminate the and. 1662 unsigned NumBits = MVT::getSizeInBits(VT)*2; 1663 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1664 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1665 } 1666 break; 1667#endif 1668 } 1669 1670 // Memoize the node. 1671 SDNode *&N = ArbitraryNodes[std::make_pair(Opcode, std::make_pair(ResultTys, 1672 Ops))]; 1673 if (N) return SDOperand(N, 0); 1674 N = new SDNode(Opcode, Ops); 1675 N->setValueTypes(ResultTys); 1676 AllNodes.push_back(N); 1677 return SDOperand(N, 0); 1678} 1679 1680/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 1681/// indicated value. This method ignores uses of other values defined by this 1682/// operation. 1683bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) { 1684 assert(Value < getNumValues() && "Bad value!"); 1685 1686 // If there is only one value, this is easy. 1687 if (getNumValues() == 1) 1688 return use_size() == NUses; 1689 if (Uses.size() < NUses) return false; 1690 1691 SDOperand TheValue(this, Value); 1692 1693 std::set<SDNode*> UsersHandled; 1694 1695 for (std::vector<SDNode*>::iterator UI = Uses.begin(), E = Uses.end(); 1696 UI != E; ++UI) { 1697 SDNode *User = *UI; 1698 if (User->getNumOperands() == 1 || 1699 UsersHandled.insert(User).second) // First time we've seen this? 1700 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 1701 if (User->getOperand(i) == TheValue) { 1702 if (NUses == 0) 1703 return false; // too many uses 1704 --NUses; 1705 } 1706 } 1707 1708 // Found exactly the right number of uses? 1709 return NUses == 0; 1710} 1711 1712 1713const char *SDNode::getOperationName() const { 1714 switch (getOpcode()) { 1715 default: return "<<Unknown>>"; 1716 case ISD::PCMARKER: return "PCMarker"; 1717 case ISD::SRCVALUE: return "SrcValue"; 1718 case ISD::EntryToken: return "EntryToken"; 1719 case ISD::TokenFactor: return "TokenFactor"; 1720 case ISD::Constant: return "Constant"; 1721 case ISD::ConstantFP: return "ConstantFP"; 1722 case ISD::GlobalAddress: return "GlobalAddress"; 1723 case ISD::FrameIndex: return "FrameIndex"; 1724 case ISD::BasicBlock: return "BasicBlock"; 1725 case ISD::ExternalSymbol: return "ExternalSymbol"; 1726 case ISD::ConstantPool: return "ConstantPoolIndex"; 1727 case ISD::CopyToReg: return "CopyToReg"; 1728 case ISD::CopyFromReg: return "CopyFromReg"; 1729 case ISD::ImplicitDef: return "ImplicitDef"; 1730 case ISD::UNDEF: return "undef"; 1731 1732 // Unary operators 1733 case ISD::FABS: return "fabs"; 1734 case ISD::FNEG: return "fneg"; 1735 case ISD::FSQRT: return "fsqrt"; 1736 case ISD::FSIN: return "fsin"; 1737 case ISD::FCOS: return "fcos"; 1738 1739 // Binary operators 1740 case ISD::ADD: return "add"; 1741 case ISD::SUB: return "sub"; 1742 case ISD::MUL: return "mul"; 1743 case ISD::MULHU: return "mulhu"; 1744 case ISD::MULHS: return "mulhs"; 1745 case ISD::SDIV: return "sdiv"; 1746 case ISD::UDIV: return "udiv"; 1747 case ISD::SREM: return "srem"; 1748 case ISD::UREM: return "urem"; 1749 case ISD::AND: return "and"; 1750 case ISD::OR: return "or"; 1751 case ISD::XOR: return "xor"; 1752 case ISD::SHL: return "shl"; 1753 case ISD::SRA: return "sra"; 1754 case ISD::SRL: return "srl"; 1755 1756 case ISD::SETCC: return "setcc"; 1757 case ISD::SELECT: return "select"; 1758 case ISD::SELECT_CC: return "select_cc"; 1759 case ISD::ADD_PARTS: return "add_parts"; 1760 case ISD::SUB_PARTS: return "sub_parts"; 1761 case ISD::SHL_PARTS: return "shl_parts"; 1762 case ISD::SRA_PARTS: return "sra_parts"; 1763 case ISD::SRL_PARTS: return "srl_parts"; 1764 1765 // Conversion operators. 1766 case ISD::SIGN_EXTEND: return "sign_extend"; 1767 case ISD::ZERO_EXTEND: return "zero_extend"; 1768 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 1769 case ISD::TRUNCATE: return "truncate"; 1770 case ISD::FP_ROUND: return "fp_round"; 1771 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 1772 case ISD::FP_EXTEND: return "fp_extend"; 1773 1774 case ISD::SINT_TO_FP: return "sint_to_fp"; 1775 case ISD::UINT_TO_FP: return "uint_to_fp"; 1776 case ISD::FP_TO_SINT: return "fp_to_sint"; 1777 case ISD::FP_TO_UINT: return "fp_to_uint"; 1778 1779 // Control flow instructions 1780 case ISD::BR: return "br"; 1781 case ISD::BRCOND: return "brcond"; 1782 case ISD::BRCONDTWOWAY: return "brcondtwoway"; 1783 case ISD::RET: return "ret"; 1784 case ISD::CALL: return "call"; 1785 case ISD::TAILCALL:return "tailcall"; 1786 case ISD::CALLSEQ_START: return "callseq_start"; 1787 case ISD::CALLSEQ_END: return "callseq_end"; 1788 1789 // Other operators 1790 case ISD::LOAD: return "load"; 1791 case ISD::STORE: return "store"; 1792 case ISD::EXTLOAD: return "extload"; 1793 case ISD::SEXTLOAD: return "sextload"; 1794 case ISD::ZEXTLOAD: return "zextload"; 1795 case ISD::TRUNCSTORE: return "truncstore"; 1796 1797 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 1798 case ISD::EXTRACT_ELEMENT: return "extract_element"; 1799 case ISD::BUILD_PAIR: return "build_pair"; 1800 case ISD::MEMSET: return "memset"; 1801 case ISD::MEMCPY: return "memcpy"; 1802 case ISD::MEMMOVE: return "memmove"; 1803 1804 // Bit counting 1805 case ISD::CTPOP: return "ctpop"; 1806 case ISD::CTTZ: return "cttz"; 1807 case ISD::CTLZ: return "ctlz"; 1808 1809 // IO Intrinsics 1810 case ISD::READPORT: return "readport"; 1811 case ISD::WRITEPORT: return "writeport"; 1812 case ISD::READIO: return "readio"; 1813 case ISD::WRITEIO: return "writeio"; 1814 1815 case ISD::CONDCODE: 1816 switch (cast<CondCodeSDNode>(this)->get()) { 1817 default: assert(0 && "Unknown setcc condition!"); 1818 case ISD::SETOEQ: return "setoeq"; 1819 case ISD::SETOGT: return "setogt"; 1820 case ISD::SETOGE: return "setoge"; 1821 case ISD::SETOLT: return "setolt"; 1822 case ISD::SETOLE: return "setole"; 1823 case ISD::SETONE: return "setone"; 1824 1825 case ISD::SETO: return "seto"; 1826 case ISD::SETUO: return "setuo"; 1827 case ISD::SETUEQ: return "setue"; 1828 case ISD::SETUGT: return "setugt"; 1829 case ISD::SETUGE: return "setuge"; 1830 case ISD::SETULT: return "setult"; 1831 case ISD::SETULE: return "setule"; 1832 case ISD::SETUNE: return "setune"; 1833 1834 case ISD::SETEQ: return "seteq"; 1835 case ISD::SETGT: return "setgt"; 1836 case ISD::SETGE: return "setge"; 1837 case ISD::SETLT: return "setlt"; 1838 case ISD::SETLE: return "setle"; 1839 case ISD::SETNE: return "setne"; 1840 } 1841 } 1842} 1843 1844void SDNode::dump() const { 1845 std::cerr << (void*)this << ": "; 1846 1847 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 1848 if (i) std::cerr << ","; 1849 if (getValueType(i) == MVT::Other) 1850 std::cerr << "ch"; 1851 else 1852 std::cerr << MVT::getValueTypeString(getValueType(i)); 1853 } 1854 std::cerr << " = " << getOperationName(); 1855 1856 std::cerr << " "; 1857 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1858 if (i) std::cerr << ", "; 1859 std::cerr << (void*)getOperand(i).Val; 1860 if (unsigned RN = getOperand(i).ResNo) 1861 std::cerr << ":" << RN; 1862 } 1863 1864 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 1865 std::cerr << "<" << CSDN->getValue() << ">"; 1866 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 1867 std::cerr << "<" << CSDN->getValue() << ">"; 1868 } else if (const GlobalAddressSDNode *GADN = 1869 dyn_cast<GlobalAddressSDNode>(this)) { 1870 std::cerr << "<"; 1871 WriteAsOperand(std::cerr, GADN->getGlobal()) << ">"; 1872 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 1873 std::cerr << "<" << FIDN->getIndex() << ">"; 1874 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 1875 std::cerr << "<" << CP->getIndex() << ">"; 1876 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 1877 std::cerr << "<"; 1878 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 1879 if (LBB) 1880 std::cerr << LBB->getName() << " "; 1881 std::cerr << (const void*)BBDN->getBasicBlock() << ">"; 1882 } else if (const RegSDNode *C2V = dyn_cast<RegSDNode>(this)) { 1883 std::cerr << "<reg #" << C2V->getReg() << ">"; 1884 } else if (const ExternalSymbolSDNode *ES = 1885 dyn_cast<ExternalSymbolSDNode>(this)) { 1886 std::cerr << "'" << ES->getSymbol() << "'"; 1887 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 1888 if (M->getValue()) 1889 std::cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; 1890 else 1891 std::cerr << "<null:" << M->getOffset() << ">"; 1892 } 1893} 1894 1895static void DumpNodes(SDNode *N, unsigned indent) { 1896 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1897 if (N->getOperand(i).Val->hasOneUse()) 1898 DumpNodes(N->getOperand(i).Val, indent+2); 1899 else 1900 std::cerr << "\n" << std::string(indent+2, ' ') 1901 << (void*)N->getOperand(i).Val << ": <multiple use>"; 1902 1903 1904 std::cerr << "\n" << std::string(indent, ' '); 1905 N->dump(); 1906} 1907 1908void SelectionDAG::dump() const { 1909 std::cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 1910 std::vector<SDNode*> Nodes(AllNodes); 1911 std::sort(Nodes.begin(), Nodes.end()); 1912 1913 for (unsigned i = 0, e = Nodes.size(); i != e; ++i) { 1914 if (!Nodes[i]->hasOneUse() && Nodes[i] != getRoot().Val) 1915 DumpNodes(Nodes[i], 2); 1916 } 1917 1918 DumpNodes(getRoot().Val, 2); 1919 1920 std::cerr << "\n\n"; 1921} 1922 1923