SelectionDAG.cpp revision 4da7620a38a361d4a28e3a5e267c8cfe13c8873f
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/ADT/SetVector.h" 37#include "llvm/ADT/SmallPtrSet.h" 38#include "llvm/ADT/SmallSet.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/ADT/StringExtras.h" 41#include <algorithm> 42#include <cmath> 43using namespace llvm; 44 45/// makeVTList - Return an instance of the SDVTList struct initialized with the 46/// specified members. 47static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 48 SDVTList Res = {VTs, NumVTs}; 49 return Res; 50} 51 52static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 53 switch (VT.getSimpleVT()) { 54 default: assert(0 && "Unknown FP format"); 55 case MVT::f32: return &APFloat::IEEEsingle; 56 case MVT::f64: return &APFloat::IEEEdouble; 57 case MVT::f80: return &APFloat::x87DoubleExtended; 58 case MVT::f128: return &APFloat::IEEEquad; 59 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 60 } 61} 62 63SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 64 65//===----------------------------------------------------------------------===// 66// ConstantFPSDNode Class 67//===----------------------------------------------------------------------===// 68 69/// isExactlyValue - We don't rely on operator== working on double values, as 70/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 71/// As such, this method can be used to do an exact bit-for-bit comparison of 72/// two floating point values. 73bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 74 return getValueAPF().bitwiseIsEqual(V); 75} 76 77bool ConstantFPSDNode::isValueValidForType(MVT VT, 78 const APFloat& Val) { 79 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 80 81 // PPC long double cannot be converted to any other type. 82 if (VT == MVT::ppcf128 || 83 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 84 return false; 85 86 // convert modifies in place, so make a copy. 87 APFloat Val2 = APFloat(Val); 88 bool losesInfo; 89 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 90 &losesInfo); 91 return !losesInfo; 92} 93 94//===----------------------------------------------------------------------===// 95// ISD Namespace 96//===----------------------------------------------------------------------===// 97 98/// isBuildVectorAllOnes - Return true if the specified node is a 99/// BUILD_VECTOR where all of the elements are ~0 or undef. 100bool ISD::isBuildVectorAllOnes(const SDNode *N) { 101 // Look through a bit convert. 102 if (N->getOpcode() == ISD::BIT_CONVERT) 103 N = N->getOperand(0).getNode(); 104 105 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 106 107 unsigned i = 0, e = N->getNumOperands(); 108 109 // Skip over all of the undef values. 110 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 111 ++i; 112 113 // Do not accept an all-undef vector. 114 if (i == e) return false; 115 116 // Do not accept build_vectors that aren't all constants or which have non-~0 117 // elements. 118 SDValue NotZero = N->getOperand(i); 119 if (isa<ConstantSDNode>(NotZero)) { 120 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 121 return false; 122 } else if (isa<ConstantFPSDNode>(NotZero)) { 123 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 124 bitcastToAPInt().isAllOnesValue()) 125 return false; 126 } else 127 return false; 128 129 // Okay, we have at least one ~0 value, check to see if the rest match or are 130 // undefs. 131 for (++i; i != e; ++i) 132 if (N->getOperand(i) != NotZero && 133 N->getOperand(i).getOpcode() != ISD::UNDEF) 134 return false; 135 return true; 136} 137 138 139/// isBuildVectorAllZeros - Return true if the specified node is a 140/// BUILD_VECTOR where all of the elements are 0 or undef. 141bool ISD::isBuildVectorAllZeros(const SDNode *N) { 142 // Look through a bit convert. 143 if (N->getOpcode() == ISD::BIT_CONVERT) 144 N = N->getOperand(0).getNode(); 145 146 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 147 148 unsigned i = 0, e = N->getNumOperands(); 149 150 // Skip over all of the undef values. 151 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 152 ++i; 153 154 // Do not accept an all-undef vector. 155 if (i == e) return false; 156 157 // Do not accept build_vectors that aren't all constants or which have non-~0 158 // elements. 159 SDValue Zero = N->getOperand(i); 160 if (isa<ConstantSDNode>(Zero)) { 161 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 162 return false; 163 } else if (isa<ConstantFPSDNode>(Zero)) { 164 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 165 return false; 166 } else 167 return false; 168 169 // Okay, we have at least one ~0 value, check to see if the rest match or are 170 // undefs. 171 for (++i; i != e; ++i) 172 if (N->getOperand(i) != Zero && 173 N->getOperand(i).getOpcode() != ISD::UNDEF) 174 return false; 175 return true; 176} 177 178/// isScalarToVector - Return true if the specified node is a 179/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 180/// element is not an undef. 181bool ISD::isScalarToVector(const SDNode *N) { 182 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 183 return true; 184 185 if (N->getOpcode() != ISD::BUILD_VECTOR) 186 return false; 187 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 188 return false; 189 unsigned NumElems = N->getNumOperands(); 190 for (unsigned i = 1; i < NumElems; ++i) { 191 SDValue V = N->getOperand(i); 192 if (V.getOpcode() != ISD::UNDEF) 193 return false; 194 } 195 return true; 196} 197 198 199/// isDebugLabel - Return true if the specified node represents a debug 200/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 201bool ISD::isDebugLabel(const SDNode *N) { 202 SDValue Zero; 203 if (N->getOpcode() == ISD::DBG_LABEL) 204 return true; 205 if (N->isMachineOpcode() && 206 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 207 return true; 208 return false; 209} 210 211/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 212/// when given the operation for (X op Y). 213ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 214 // To perform this operation, we just need to swap the L and G bits of the 215 // operation. 216 unsigned OldL = (Operation >> 2) & 1; 217 unsigned OldG = (Operation >> 1) & 1; 218 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 219 (OldL << 1) | // New G bit 220 (OldG << 2)); // New L bit. 221} 222 223/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 224/// 'op' is a valid SetCC operation. 225ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 226 unsigned Operation = Op; 227 if (isInteger) 228 Operation ^= 7; // Flip L, G, E bits, but not U. 229 else 230 Operation ^= 15; // Flip all of the condition bits. 231 232 if (Operation > ISD::SETTRUE2) 233 Operation &= ~8; // Don't let N and U bits get set. 234 235 return ISD::CondCode(Operation); 236} 237 238 239/// isSignedOp - For an integer comparison, return 1 if the comparison is a 240/// signed operation and 2 if the result is an unsigned comparison. Return zero 241/// if the operation does not depend on the sign of the input (setne and seteq). 242static int isSignedOp(ISD::CondCode Opcode) { 243 switch (Opcode) { 244 default: assert(0 && "Illegal integer setcc operation!"); 245 case ISD::SETEQ: 246 case ISD::SETNE: return 0; 247 case ISD::SETLT: 248 case ISD::SETLE: 249 case ISD::SETGT: 250 case ISD::SETGE: return 1; 251 case ISD::SETULT: 252 case ISD::SETULE: 253 case ISD::SETUGT: 254 case ISD::SETUGE: return 2; 255 } 256} 257 258/// getSetCCOrOperation - Return the result of a logical OR between different 259/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 260/// returns SETCC_INVALID if it is not possible to represent the resultant 261/// comparison. 262ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 263 bool isInteger) { 264 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 265 // Cannot fold a signed integer setcc with an unsigned integer setcc. 266 return ISD::SETCC_INVALID; 267 268 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 269 270 // If the N and U bits get set then the resultant comparison DOES suddenly 271 // care about orderedness, and is true when ordered. 272 if (Op > ISD::SETTRUE2) 273 Op &= ~16; // Clear the U bit if the N bit is set. 274 275 // Canonicalize illegal integer setcc's. 276 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 277 Op = ISD::SETNE; 278 279 return ISD::CondCode(Op); 280} 281 282/// getSetCCAndOperation - Return the result of a logical AND between different 283/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 284/// function returns zero if it is not possible to represent the resultant 285/// comparison. 286ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 287 bool isInteger) { 288 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 289 // Cannot fold a signed setcc with an unsigned setcc. 290 return ISD::SETCC_INVALID; 291 292 // Combine all of the condition bits. 293 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 294 295 // Canonicalize illegal integer setcc's. 296 if (isInteger) { 297 switch (Result) { 298 default: break; 299 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 300 case ISD::SETOEQ: // SETEQ & SETU[LG]E 301 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 302 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 303 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 304 } 305 } 306 307 return Result; 308} 309 310const TargetMachine &SelectionDAG::getTarget() const { 311 return MF->getTarget(); 312} 313 314//===----------------------------------------------------------------------===// 315// SDNode Profile Support 316//===----------------------------------------------------------------------===// 317 318/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 319/// 320static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 321 ID.AddInteger(OpC); 322} 323 324/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 325/// solely with their pointer. 326static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 327 ID.AddPointer(VTList.VTs); 328} 329 330/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 331/// 332static void AddNodeIDOperands(FoldingSetNodeID &ID, 333 const SDValue *Ops, unsigned NumOps) { 334 for (; NumOps; --NumOps, ++Ops) { 335 ID.AddPointer(Ops->getNode()); 336 ID.AddInteger(Ops->getResNo()); 337 } 338} 339 340/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 341/// 342static void AddNodeIDOperands(FoldingSetNodeID &ID, 343 const SDUse *Ops, unsigned NumOps) { 344 for (; NumOps; --NumOps, ++Ops) { 345 ID.AddPointer(Ops->getNode()); 346 ID.AddInteger(Ops->getResNo()); 347 } 348} 349 350static void AddNodeIDNode(FoldingSetNodeID &ID, 351 unsigned short OpC, SDVTList VTList, 352 const SDValue *OpList, unsigned N) { 353 AddNodeIDOpcode(ID, OpC); 354 AddNodeIDValueTypes(ID, VTList); 355 AddNodeIDOperands(ID, OpList, N); 356} 357 358/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 359/// the NodeID data. 360static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 361 switch (N->getOpcode()) { 362 default: break; // Normal nodes don't need extra info. 363 case ISD::ARG_FLAGS: 364 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 365 break; 366 case ISD::TargetConstant: 367 case ISD::Constant: 368 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 369 break; 370 case ISD::TargetConstantFP: 371 case ISD::ConstantFP: { 372 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 373 break; 374 } 375 case ISD::TargetGlobalAddress: 376 case ISD::GlobalAddress: 377 case ISD::TargetGlobalTLSAddress: 378 case ISD::GlobalTLSAddress: { 379 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 380 ID.AddPointer(GA->getGlobal()); 381 ID.AddInteger(GA->getOffset()); 382 break; 383 } 384 case ISD::BasicBlock: 385 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 386 break; 387 case ISD::Register: 388 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 389 break; 390 case ISD::DBG_STOPPOINT: { 391 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 392 ID.AddInteger(DSP->getLine()); 393 ID.AddInteger(DSP->getColumn()); 394 ID.AddPointer(DSP->getCompileUnit()); 395 break; 396 } 397 case ISD::SRCVALUE: 398 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 399 break; 400 case ISD::MEMOPERAND: { 401 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 402 MO.Profile(ID); 403 break; 404 } 405 case ISD::FrameIndex: 406 case ISD::TargetFrameIndex: 407 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 408 break; 409 case ISD::JumpTable: 410 case ISD::TargetJumpTable: 411 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 412 break; 413 case ISD::ConstantPool: 414 case ISD::TargetConstantPool: { 415 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 416 ID.AddInteger(CP->getAlignment()); 417 ID.AddInteger(CP->getOffset()); 418 if (CP->isMachineConstantPoolEntry()) 419 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 420 else 421 ID.AddPointer(CP->getConstVal()); 422 break; 423 } 424 case ISD::CALL: { 425 const CallSDNode *Call = cast<CallSDNode>(N); 426 ID.AddInteger(Call->getCallingConv()); 427 ID.AddInteger(Call->isVarArg()); 428 break; 429 } 430 case ISD::LOAD: { 431 const LoadSDNode *LD = cast<LoadSDNode>(N); 432 ID.AddInteger(LD->getMemoryVT().getRawBits()); 433 ID.AddInteger(LD->getRawSubclassData()); 434 break; 435 } 436 case ISD::STORE: { 437 const StoreSDNode *ST = cast<StoreSDNode>(N); 438 ID.AddInteger(ST->getMemoryVT().getRawBits()); 439 ID.AddInteger(ST->getRawSubclassData()); 440 break; 441 } 442 case ISD::ATOMIC_CMP_SWAP: 443 case ISD::ATOMIC_SWAP: 444 case ISD::ATOMIC_LOAD_ADD: 445 case ISD::ATOMIC_LOAD_SUB: 446 case ISD::ATOMIC_LOAD_AND: 447 case ISD::ATOMIC_LOAD_OR: 448 case ISD::ATOMIC_LOAD_XOR: 449 case ISD::ATOMIC_LOAD_NAND: 450 case ISD::ATOMIC_LOAD_MIN: 451 case ISD::ATOMIC_LOAD_MAX: 452 case ISD::ATOMIC_LOAD_UMIN: 453 case ISD::ATOMIC_LOAD_UMAX: { 454 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 455 ID.AddInteger(AT->getMemoryVT().getRawBits()); 456 ID.AddInteger(AT->getRawSubclassData()); 457 break; 458 } 459 case ISD::VECTOR_SHUFFLE: { 460 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 461 for (unsigned i = 0, e = N->getValueType(0).getVectorNumElements(); 462 i != e; ++i) 463 ID.AddInteger(SVN->getMaskElt(i)); 464 break; 465 } 466 } // end switch (N->getOpcode()) 467} 468 469/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 470/// data. 471static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 472 AddNodeIDOpcode(ID, N->getOpcode()); 473 // Add the return value info. 474 AddNodeIDValueTypes(ID, N->getVTList()); 475 // Add the operand info. 476 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 477 478 // Handle SDNode leafs with special info. 479 AddNodeIDCustom(ID, N); 480} 481 482/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 483/// the CSE map that carries alignment, volatility, indexing mode, and 484/// extension/truncation information. 485/// 486static inline unsigned 487encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, 488 bool isVolatile, unsigned Alignment) { 489 assert((ConvType & 3) == ConvType && 490 "ConvType may not require more than 2 bits!"); 491 assert((AM & 7) == AM && 492 "AM may not require more than 3 bits!"); 493 return ConvType | 494 (AM << 2) | 495 (isVolatile << 5) | 496 ((Log2_32(Alignment) + 1) << 6); 497} 498 499//===----------------------------------------------------------------------===// 500// SelectionDAG Class 501//===----------------------------------------------------------------------===// 502 503/// doNotCSE - Return true if CSE should not be performed for this node. 504static bool doNotCSE(SDNode *N) { 505 if (N->getValueType(0) == MVT::Flag) 506 return true; // Never CSE anything that produces a flag. 507 508 switch (N->getOpcode()) { 509 default: break; 510 case ISD::HANDLENODE: 511 case ISD::DBG_LABEL: 512 case ISD::DBG_STOPPOINT: 513 case ISD::EH_LABEL: 514 case ISD::DECLARE: 515 return true; // Never CSE these nodes. 516 } 517 518 // Check that remaining values produced are not flags. 519 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 520 if (N->getValueType(i) == MVT::Flag) 521 return true; // Never CSE anything that produces a flag. 522 523 return false; 524} 525 526/// RemoveDeadNodes - This method deletes all unreachable nodes in the 527/// SelectionDAG. 528void SelectionDAG::RemoveDeadNodes() { 529 // Create a dummy node (which is not added to allnodes), that adds a reference 530 // to the root node, preventing it from being deleted. 531 HandleSDNode Dummy(getRoot()); 532 533 SmallVector<SDNode*, 128> DeadNodes; 534 535 // Add all obviously-dead nodes to the DeadNodes worklist. 536 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 537 if (I->use_empty()) 538 DeadNodes.push_back(I); 539 540 RemoveDeadNodes(DeadNodes); 541 542 // If the root changed (e.g. it was a dead load, update the root). 543 setRoot(Dummy.getValue()); 544} 545 546/// RemoveDeadNodes - This method deletes the unreachable nodes in the 547/// given list, and any nodes that become unreachable as a result. 548void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 549 DAGUpdateListener *UpdateListener) { 550 551 // Process the worklist, deleting the nodes and adding their uses to the 552 // worklist. 553 while (!DeadNodes.empty()) { 554 SDNode *N = DeadNodes.pop_back_val(); 555 556 if (UpdateListener) 557 UpdateListener->NodeDeleted(N, 0); 558 559 // Take the node out of the appropriate CSE map. 560 RemoveNodeFromCSEMaps(N); 561 562 // Next, brutally remove the operand list. This is safe to do, as there are 563 // no cycles in the graph. 564 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 565 SDUse &Use = *I++; 566 SDNode *Operand = Use.getNode(); 567 Use.set(SDValue()); 568 569 // Now that we removed this operand, see if there are no uses of it left. 570 if (Operand->use_empty()) 571 DeadNodes.push_back(Operand); 572 } 573 574 DeallocateNode(N); 575 } 576} 577 578void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 579 SmallVector<SDNode*, 16> DeadNodes(1, N); 580 RemoveDeadNodes(DeadNodes, UpdateListener); 581} 582 583void SelectionDAG::DeleteNode(SDNode *N) { 584 // First take this out of the appropriate CSE map. 585 RemoveNodeFromCSEMaps(N); 586 587 // Finally, remove uses due to operands of this node, remove from the 588 // AllNodes list, and delete the node. 589 DeleteNodeNotInCSEMaps(N); 590} 591 592void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 593 assert(N != AllNodes.begin() && "Cannot delete the entry node!"); 594 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 595 596 // Drop all of the operands and decrement used node's use counts. 597 N->DropOperands(); 598 599 DeallocateNode(N); 600} 601 602void SelectionDAG::DeallocateNode(SDNode *N) { 603 if (N->OperandsNeedDelete) 604 delete[] N->OperandList; 605 606 // Set the opcode to DELETED_NODE to help catch bugs when node 607 // memory is reallocated. 608 N->NodeType = ISD::DELETED_NODE; 609 610 NodeAllocator.Deallocate(AllNodes.remove(N)); 611} 612 613/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 614/// correspond to it. This is useful when we're about to delete or repurpose 615/// the node. We don't want future request for structurally identical nodes 616/// to return N anymore. 617bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 618 bool Erased = false; 619 switch (N->getOpcode()) { 620 case ISD::EntryToken: 621 assert(0 && "EntryToken should not be in CSEMaps!"); 622 return false; 623 case ISD::HANDLENODE: return false; // noop. 624 case ISD::CONDCODE: 625 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 626 "Cond code doesn't exist!"); 627 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 628 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 629 break; 630 case ISD::ExternalSymbol: 631 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 632 break; 633 case ISD::TargetExternalSymbol: 634 Erased = 635 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 636 break; 637 case ISD::VALUETYPE: { 638 MVT VT = cast<VTSDNode>(N)->getVT(); 639 if (VT.isExtended()) { 640 Erased = ExtendedValueTypeNodes.erase(VT); 641 } else { 642 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 643 ValueTypeNodes[VT.getSimpleVT()] = 0; 644 } 645 break; 646 } 647 default: 648 // Remove it from the CSE Map. 649 Erased = CSEMap.RemoveNode(N); 650 break; 651 } 652#ifndef NDEBUG 653 // Verify that the node was actually in one of the CSE maps, unless it has a 654 // flag result (which cannot be CSE'd) or is one of the special cases that are 655 // not subject to CSE. 656 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 657 !N->isMachineOpcode() && !doNotCSE(N)) { 658 N->dump(this); 659 cerr << "\n"; 660 assert(0 && "Node is not in map!"); 661 } 662#endif 663 return Erased; 664} 665 666/// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE 667/// maps and modified in place. Add it back to the CSE maps, unless an identical 668/// node already exists, in which case transfer all its users to the existing 669/// node. This transfer can potentially trigger recursive merging. 670/// 671void 672SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N, 673 DAGUpdateListener *UpdateListener) { 674 // For node types that aren't CSE'd, just act as if no identical node 675 // already exists. 676 if (!doNotCSE(N)) { 677 SDNode *Existing = CSEMap.GetOrInsertNode(N); 678 if (Existing != N) { 679 // If there was already an existing matching node, use ReplaceAllUsesWith 680 // to replace the dead one with the existing one. This can cause 681 // recursive merging of other unrelated nodes down the line. 682 ReplaceAllUsesWith(N, Existing, UpdateListener); 683 684 // N is now dead. Inform the listener if it exists and delete it. 685 if (UpdateListener) 686 UpdateListener->NodeDeleted(N, Existing); 687 DeleteNodeNotInCSEMaps(N); 688 return; 689 } 690 } 691 692 // If the node doesn't already exist, we updated it. Inform a listener if 693 // it exists. 694 if (UpdateListener) 695 UpdateListener->NodeUpdated(N); 696} 697 698/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 699/// were replaced with those specified. If this node is never memoized, 700/// return null, otherwise return a pointer to the slot it would take. If a 701/// node already exists with these operands, the slot will be non-null. 702SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 703 void *&InsertPos) { 704 if (doNotCSE(N)) 705 return 0; 706 707 SDValue Ops[] = { Op }; 708 FoldingSetNodeID ID; 709 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 710 AddNodeIDCustom(ID, N); 711 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 712} 713 714/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 715/// were replaced with those specified. If this node is never memoized, 716/// return null, otherwise return a pointer to the slot it would take. If a 717/// node already exists with these operands, the slot will be non-null. 718SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 719 SDValue Op1, SDValue Op2, 720 void *&InsertPos) { 721 if (doNotCSE(N)) 722 return 0; 723 724 SDValue Ops[] = { Op1, Op2 }; 725 FoldingSetNodeID ID; 726 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 727 AddNodeIDCustom(ID, N); 728 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 729} 730 731 732/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 733/// were replaced with those specified. If this node is never memoized, 734/// return null, otherwise return a pointer to the slot it would take. If a 735/// node already exists with these operands, the slot will be non-null. 736SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 737 const SDValue *Ops,unsigned NumOps, 738 void *&InsertPos) { 739 if (doNotCSE(N)) 740 return 0; 741 742 FoldingSetNodeID ID; 743 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 744 AddNodeIDCustom(ID, N); 745 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 746} 747 748/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 749void SelectionDAG::VerifyNode(SDNode *N) { 750 switch (N->getOpcode()) { 751 default: 752 break; 753 case ISD::BUILD_PAIR: { 754 MVT VT = N->getValueType(0); 755 assert(N->getNumValues() == 1 && "Too many results!"); 756 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 757 "Wrong return type!"); 758 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 759 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 760 "Mismatched operand types!"); 761 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 762 "Wrong operand type!"); 763 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 764 "Wrong return type size"); 765 break; 766 } 767 case ISD::BUILD_VECTOR: { 768 assert(N->getNumValues() == 1 && "Too many results!"); 769 assert(N->getValueType(0).isVector() && "Wrong return type!"); 770 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 771 "Wrong number of operands!"); 772 MVT EltVT = N->getValueType(0).getVectorElementType(); 773 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 774 assert((I->getValueType() == EltVT || 775 (EltVT.isInteger() && I->getValueType().isInteger() && 776 EltVT.bitsLE(I->getValueType()))) && 777 "Wrong operand type!"); 778 break; 779 } 780 } 781} 782 783/// getMVTAlignment - Compute the default alignment value for the 784/// given type. 785/// 786unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 787 const Type *Ty = VT == MVT::iPTR ? 788 PointerType::get(Type::Int8Ty, 0) : 789 VT.getTypeForMVT(); 790 791 return TLI.getTargetData()->getABITypeAlignment(Ty); 792} 793 794// EntryNode could meaningfully have debug info if we can find it... 795SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 796 : TLI(tli), FLI(fli), DW(0), 797 EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(), 798 getVTList(MVT::Other)), Root(getEntryNode()) { 799 AllNodes.push_back(&EntryNode); 800} 801 802void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi, 803 DwarfWriter *dw) { 804 MF = &mf; 805 MMI = mmi; 806 DW = dw; 807} 808 809SelectionDAG::~SelectionDAG() { 810 allnodes_clear(); 811} 812 813void SelectionDAG::allnodes_clear() { 814 assert(&*AllNodes.begin() == &EntryNode); 815 AllNodes.remove(AllNodes.begin()); 816 while (!AllNodes.empty()) 817 DeallocateNode(AllNodes.begin()); 818} 819 820void SelectionDAG::clear() { 821 allnodes_clear(); 822 OperandAllocator.Reset(); 823 CSEMap.clear(); 824 825 ExtendedValueTypeNodes.clear(); 826 ExternalSymbols.clear(); 827 TargetExternalSymbols.clear(); 828 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 829 static_cast<CondCodeSDNode*>(0)); 830 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 831 static_cast<SDNode*>(0)); 832 833 EntryNode.UseList = 0; 834 AllNodes.push_back(&EntryNode); 835 Root = getEntryNode(); 836} 837 838SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { 839 if (Op.getValueType() == VT) return Op; 840 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 841 VT.getSizeInBits()); 842 return getNode(ISD::AND, DL, Op.getValueType(), Op, 843 getConstant(Imm, Op.getValueType())); 844} 845 846/// getNOT - Create a bitwise NOT operation as (XOR Val, -1). 847/// 848SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) { 849 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 850 SDValue NegOne = 851 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 852 return getNode(ISD::XOR, DL, VT, Val, NegOne); 853} 854 855SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 856 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 857 assert((EltVT.getSizeInBits() >= 64 || 858 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) && 859 "getConstant with a uint64_t value that doesn't fit in the type!"); 860 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 861} 862 863SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 864 return getConstant(*ConstantInt::get(Val), VT, isT); 865} 866 867SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 868 assert(VT.isInteger() && "Cannot create FP integer constant!"); 869 870 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 871 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 872 "APInt size does not match type size!"); 873 874 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 875 FoldingSetNodeID ID; 876 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 877 ID.AddPointer(&Val); 878 void *IP = 0; 879 SDNode *N = NULL; 880 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 881 if (!VT.isVector()) 882 return SDValue(N, 0); 883 if (!N) { 884 N = NodeAllocator.Allocate<ConstantSDNode>(); 885 new (N) ConstantSDNode(isT, &Val, EltVT); 886 CSEMap.InsertNode(N, IP); 887 AllNodes.push_back(N); 888 } 889 890 SDValue Result(N, 0); 891 if (VT.isVector()) { 892 SmallVector<SDValue, 8> Ops; 893 Ops.assign(VT.getVectorNumElements(), Result); 894 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 895 VT, &Ops[0], Ops.size()); 896 } 897 return Result; 898} 899 900SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 901 return getConstant(Val, TLI.getPointerTy(), isTarget); 902} 903 904 905SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 906 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 907} 908 909SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 910 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 911 912 MVT EltVT = 913 VT.isVector() ? VT.getVectorElementType() : VT; 914 915 // Do the map lookup using the actual bit pattern for the floating point 916 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 917 // we don't have issues with SNANs. 918 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 919 FoldingSetNodeID ID; 920 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 921 ID.AddPointer(&V); 922 void *IP = 0; 923 SDNode *N = NULL; 924 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 925 if (!VT.isVector()) 926 return SDValue(N, 0); 927 if (!N) { 928 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 929 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 930 CSEMap.InsertNode(N, IP); 931 AllNodes.push_back(N); 932 } 933 934 SDValue Result(N, 0); 935 if (VT.isVector()) { 936 SmallVector<SDValue, 8> Ops; 937 Ops.assign(VT.getVectorNumElements(), Result); 938 // FIXME DebugLoc info might be appropriate here 939 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 940 VT, &Ops[0], Ops.size()); 941 } 942 return Result; 943} 944 945SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 946 MVT EltVT = 947 VT.isVector() ? VT.getVectorElementType() : VT; 948 if (EltVT==MVT::f32) 949 return getConstantFP(APFloat((float)Val), VT, isTarget); 950 else 951 return getConstantFP(APFloat(Val), VT, isTarget); 952} 953 954SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 955 MVT VT, int64_t Offset, 956 bool isTargetGA) { 957 unsigned Opc; 958 959 // Truncate (with sign-extension) the offset value to the pointer size. 960 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 961 if (BitWidth < 64) 962 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 963 964 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 965 if (!GVar) { 966 // If GV is an alias then use the aliasee for determining thread-localness. 967 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 968 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 969 } 970 971 if (GVar && GVar->isThreadLocal()) 972 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 973 else 974 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 975 976 FoldingSetNodeID ID; 977 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 978 ID.AddPointer(GV); 979 ID.AddInteger(Offset); 980 void *IP = 0; 981 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 982 return SDValue(E, 0); 983 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 984 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 985 CSEMap.InsertNode(N, IP); 986 AllNodes.push_back(N); 987 return SDValue(N, 0); 988} 989 990SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 991 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 992 FoldingSetNodeID ID; 993 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 994 ID.AddInteger(FI); 995 void *IP = 0; 996 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 997 return SDValue(E, 0); 998 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 999 new (N) FrameIndexSDNode(FI, VT, isTarget); 1000 CSEMap.InsertNode(N, IP); 1001 AllNodes.push_back(N); 1002 return SDValue(N, 0); 1003} 1004 1005SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 1006 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1007 FoldingSetNodeID ID; 1008 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1009 ID.AddInteger(JTI); 1010 void *IP = 0; 1011 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1012 return SDValue(E, 0); 1013 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1014 new (N) JumpTableSDNode(JTI, VT, isTarget); 1015 CSEMap.InsertNode(N, IP); 1016 AllNodes.push_back(N); 1017 return SDValue(N, 0); 1018} 1019 1020SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1021 unsigned Alignment, int Offset, 1022 bool isTarget) { 1023 if (Alignment == 0) 1024 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1025 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1026 FoldingSetNodeID ID; 1027 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1028 ID.AddInteger(Alignment); 1029 ID.AddInteger(Offset); 1030 ID.AddPointer(C); 1031 void *IP = 0; 1032 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1033 return SDValue(E, 0); 1034 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1035 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1036 CSEMap.InsertNode(N, IP); 1037 AllNodes.push_back(N); 1038 return SDValue(N, 0); 1039} 1040 1041 1042SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1043 unsigned Alignment, int Offset, 1044 bool isTarget) { 1045 if (Alignment == 0) 1046 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1047 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1048 FoldingSetNodeID ID; 1049 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1050 ID.AddInteger(Alignment); 1051 ID.AddInteger(Offset); 1052 C->AddSelectionDAGCSEId(ID); 1053 void *IP = 0; 1054 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1055 return SDValue(E, 0); 1056 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1057 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1058 CSEMap.InsertNode(N, IP); 1059 AllNodes.push_back(N); 1060 return SDValue(N, 0); 1061} 1062 1063SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1064 FoldingSetNodeID ID; 1065 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1066 ID.AddPointer(MBB); 1067 void *IP = 0; 1068 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1069 return SDValue(E, 0); 1070 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1071 new (N) BasicBlockSDNode(MBB); 1072 CSEMap.InsertNode(N, IP); 1073 AllNodes.push_back(N); 1074 return SDValue(N, 0); 1075} 1076 1077SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1078 FoldingSetNodeID ID; 1079 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1080 ID.AddInteger(Flags.getRawBits()); 1081 void *IP = 0; 1082 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1083 return SDValue(E, 0); 1084 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1085 new (N) ARG_FLAGSSDNode(Flags); 1086 CSEMap.InsertNode(N, IP); 1087 AllNodes.push_back(N); 1088 return SDValue(N, 0); 1089} 1090 1091SDValue SelectionDAG::getValueType(MVT VT) { 1092 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1093 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1094 1095 SDNode *&N = VT.isExtended() ? 1096 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1097 1098 if (N) return SDValue(N, 0); 1099 N = NodeAllocator.Allocate<VTSDNode>(); 1100 new (N) VTSDNode(VT); 1101 AllNodes.push_back(N); 1102 return SDValue(N, 0); 1103} 1104 1105SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1106 SDNode *&N = ExternalSymbols[Sym]; 1107 if (N) return SDValue(N, 0); 1108 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1109 new (N) ExternalSymbolSDNode(false, Sym, VT); 1110 AllNodes.push_back(N); 1111 return SDValue(N, 0); 1112} 1113 1114SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1115 SDNode *&N = TargetExternalSymbols[Sym]; 1116 if (N) return SDValue(N, 0); 1117 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1118 new (N) ExternalSymbolSDNode(true, Sym, VT); 1119 AllNodes.push_back(N); 1120 return SDValue(N, 0); 1121} 1122 1123SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1124 if ((unsigned)Cond >= CondCodeNodes.size()) 1125 CondCodeNodes.resize(Cond+1); 1126 1127 if (CondCodeNodes[Cond] == 0) { 1128 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1129 new (N) CondCodeSDNode(Cond); 1130 CondCodeNodes[Cond] = N; 1131 AllNodes.push_back(N); 1132 } 1133 return SDValue(CondCodeNodes[Cond], 0); 1134} 1135 1136// commuteShuffle - swaps the values of N1 and N2, and swaps all indices in 1137// the shuffle mask M that point at N1 to point at N2, and indices that point 1138// N2 to point at N1. 1139static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) { 1140 std::swap(N1, N2); 1141 int NElts = M.size(); 1142 for (int i = 0; i != NElts; ++i) { 1143 if (M[i] >= NElts) 1144 M[i] -= NElts; 1145 else if (M[i] >= 0) 1146 M[i] += NElts; 1147 } 1148} 1149 1150SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1, 1151 SDValue N2, const int *Mask) { 1152 assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE"); 1153 assert(VT.isVector() && N1.getValueType().isVector() && 1154 "Vector Shuffle VTs must be a vectors"); 1155 assert(VT.getVectorElementType() == N1.getValueType().getVectorElementType() 1156 && "Vector Shuffle VTs must have same element type"); 1157 1158 // Canonicalize shuffle undef, undef -> undef 1159 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF) 1160 return N1; 1161 1162 // Validate that all indices in Mask are within the range of the elements 1163 // input to the shuffle. 1164 unsigned NElts = VT.getVectorNumElements(); 1165 SmallVector<int, 8> MaskVec; 1166 for (unsigned i = 0; i != NElts; ++i) { 1167 assert(Mask[i] < (int)(NElts * 2) && "Index out of range"); 1168 MaskVec.push_back(Mask[i]); 1169 } 1170 1171 // Canonicalize shuffle v, v -> v, undef 1172 if (N1 == N2) { 1173 N2 = getUNDEF(VT); 1174 for (unsigned i = 0; i != NElts; ++i) 1175 if (MaskVec[i] >= (int)NElts) MaskVec[i] -= NElts; 1176 } 1177 1178 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 1179 if (N1.getOpcode() == ISD::UNDEF) 1180 commuteShuffle(N1, N2, MaskVec); 1181 1182 // Canonicalize all index into lhs, -> shuffle lhs, undef 1183 // Canonicalize all index into rhs, -> shuffle rhs, undef 1184 bool AllLHS = true, AllRHS = true; 1185 bool N2Undef = N2.getOpcode() == ISD::UNDEF; 1186 for (unsigned i = 0; i != NElts; ++i) { 1187 if (MaskVec[i] >= (int)NElts) { 1188 if (N2Undef) 1189 MaskVec[i] = -1; 1190 else 1191 AllLHS = false; 1192 } else if (MaskVec[i] >= 0) { 1193 AllRHS = false; 1194 } 1195 } 1196 if (AllLHS && AllRHS) 1197 return getUNDEF(VT); 1198 if (AllLHS && !N2Undef) 1199 N2 = getUNDEF(VT); 1200 if (AllRHS) { 1201 N1 = getUNDEF(VT); 1202 commuteShuffle(N1, N2, MaskVec); 1203 } 1204 1205 // If Identity shuffle, or all shuffle in to undef, return that node. 1206 bool AllUndef = true; 1207 bool Identity = true; 1208 for (unsigned i = 0; i != NElts; ++i) { 1209 if (MaskVec[i] >= 0 && MaskVec[i] != (int)i) Identity = false; 1210 if (MaskVec[i] >= 0) AllUndef = false; 1211 } 1212 if (Identity) 1213 return N1; 1214 if (AllUndef) 1215 return getUNDEF(VT); 1216 1217 FoldingSetNodeID ID; 1218 SDValue Ops[2] = { N1, N2 }; 1219 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2); 1220 for (unsigned i = 0; i != NElts; ++i) 1221 ID.AddInteger(MaskVec[i]); 1222 1223 void* IP = 0; 1224 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1225 return SDValue(E, 0); 1226 1227 // Allocate the mask array for the node out of the BumpPtrAllocator, since 1228 // SDNode doesn't have access to it. This memory will be "leaked" when 1229 // the node is deallocated, but recovered when the NodeAllocator is released. 1230 int *MaskAlloc = OperandAllocator.Allocate<int>(NElts); 1231 memcpy(MaskAlloc, &MaskVec[0], NElts * sizeof(int)); 1232 1233 ShuffleVectorSDNode *N = NodeAllocator.Allocate<ShuffleVectorSDNode>(); 1234 new (N) ShuffleVectorSDNode(VT, dl, N1, N2, MaskAlloc); 1235 CSEMap.InsertNode(N, IP); 1236 AllNodes.push_back(N); 1237 return SDValue(N, 0); 1238} 1239 1240SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl, 1241 SDValue Val, SDValue DTy, 1242 SDValue STy, SDValue Rnd, SDValue Sat, 1243 ISD::CvtCode Code) { 1244 // If the src and dest types are the same and the conversion is between 1245 // integer types of the same sign or two floats, no conversion is necessary. 1246 if (DTy == STy && 1247 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF)) 1248 return Val; 1249 1250 FoldingSetNodeID ID; 1251 void* IP = 0; 1252 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1253 return SDValue(E, 0); 1254 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1255 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1256 new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code); 1257 CSEMap.InsertNode(N, IP); 1258 AllNodes.push_back(N); 1259 return SDValue(N, 0); 1260} 1261 1262SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1263 FoldingSetNodeID ID; 1264 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1265 ID.AddInteger(RegNo); 1266 void *IP = 0; 1267 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1268 return SDValue(E, 0); 1269 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1270 new (N) RegisterSDNode(RegNo, VT); 1271 CSEMap.InsertNode(N, IP); 1272 AllNodes.push_back(N); 1273 return SDValue(N, 0); 1274} 1275 1276SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1277 unsigned Line, unsigned Col, 1278 Value *CU) { 1279 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1280 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1281 AllNodes.push_back(N); 1282 return SDValue(N, 0); 1283} 1284 1285SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, 1286 SDValue Root, 1287 unsigned LabelID) { 1288 FoldingSetNodeID ID; 1289 SDValue Ops[] = { Root }; 1290 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1291 ID.AddInteger(LabelID); 1292 void *IP = 0; 1293 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1294 return SDValue(E, 0); 1295 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1296 new (N) LabelSDNode(Opcode, dl, Root, LabelID); 1297 CSEMap.InsertNode(N, IP); 1298 AllNodes.push_back(N); 1299 return SDValue(N, 0); 1300} 1301 1302SDValue SelectionDAG::getSrcValue(const Value *V) { 1303 assert((!V || isa<PointerType>(V->getType())) && 1304 "SrcValue is not a pointer?"); 1305 1306 FoldingSetNodeID ID; 1307 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1308 ID.AddPointer(V); 1309 1310 void *IP = 0; 1311 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1312 return SDValue(E, 0); 1313 1314 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1315 new (N) SrcValueSDNode(V); 1316 CSEMap.InsertNode(N, IP); 1317 AllNodes.push_back(N); 1318 return SDValue(N, 0); 1319} 1320 1321SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1322#ifndef NDEBUG 1323 const Value *v = MO.getValue(); 1324 assert((!v || isa<PointerType>(v->getType())) && 1325 "SrcValue is not a pointer?"); 1326#endif 1327 1328 FoldingSetNodeID ID; 1329 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1330 MO.Profile(ID); 1331 1332 void *IP = 0; 1333 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1334 return SDValue(E, 0); 1335 1336 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1337 new (N) MemOperandSDNode(MO); 1338 CSEMap.InsertNode(N, IP); 1339 AllNodes.push_back(N); 1340 return SDValue(N, 0); 1341} 1342 1343/// getShiftAmountOperand - Return the specified value casted to 1344/// the target's desired shift amount type. 1345SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { 1346 MVT OpTy = Op.getValueType(); 1347 MVT ShTy = TLI.getShiftAmountTy(); 1348 if (OpTy == ShTy || OpTy.isVector()) return Op; 1349 1350 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1351 return getNode(Opcode, Op.getDebugLoc(), ShTy, Op); 1352} 1353 1354/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1355/// specified value type. 1356SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1357 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1358 unsigned ByteSize = VT.getStoreSizeInBits()/8; 1359 const Type *Ty = VT.getTypeForMVT(); 1360 unsigned StackAlign = 1361 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1362 1363 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1364 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1365} 1366 1367/// CreateStackTemporary - Create a stack temporary suitable for holding 1368/// either of the specified value types. 1369SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) { 1370 unsigned Bytes = std::max(VT1.getStoreSizeInBits(), 1371 VT2.getStoreSizeInBits())/8; 1372 const Type *Ty1 = VT1.getTypeForMVT(); 1373 const Type *Ty2 = VT2.getTypeForMVT(); 1374 const TargetData *TD = TLI.getTargetData(); 1375 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1), 1376 TD->getPrefTypeAlignment(Ty2)); 1377 1378 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1379 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align); 1380 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1381} 1382 1383SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1384 SDValue N2, ISD::CondCode Cond, DebugLoc dl) { 1385 // These setcc operations always fold. 1386 switch (Cond) { 1387 default: break; 1388 case ISD::SETFALSE: 1389 case ISD::SETFALSE2: return getConstant(0, VT); 1390 case ISD::SETTRUE: 1391 case ISD::SETTRUE2: return getConstant(1, VT); 1392 1393 case ISD::SETOEQ: 1394 case ISD::SETOGT: 1395 case ISD::SETOGE: 1396 case ISD::SETOLT: 1397 case ISD::SETOLE: 1398 case ISD::SETONE: 1399 case ISD::SETO: 1400 case ISD::SETUO: 1401 case ISD::SETUEQ: 1402 case ISD::SETUNE: 1403 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1404 break; 1405 } 1406 1407 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1408 const APInt &C2 = N2C->getAPIntValue(); 1409 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1410 const APInt &C1 = N1C->getAPIntValue(); 1411 1412 switch (Cond) { 1413 default: assert(0 && "Unknown integer setcc!"); 1414 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1415 case ISD::SETNE: return getConstant(C1 != C2, VT); 1416 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1417 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1418 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1419 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1420 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1421 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1422 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1423 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1424 } 1425 } 1426 } 1427 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1428 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1429 // No compile time operations on this type yet. 1430 if (N1C->getValueType(0) == MVT::ppcf128) 1431 return SDValue(); 1432 1433 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1434 switch (Cond) { 1435 default: break; 1436 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1437 return getUNDEF(VT); 1438 // fall through 1439 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1440 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1441 return getUNDEF(VT); 1442 // fall through 1443 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1444 R==APFloat::cmpLessThan, VT); 1445 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1446 return getUNDEF(VT); 1447 // fall through 1448 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1449 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1450 return getUNDEF(VT); 1451 // fall through 1452 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1453 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1454 return getUNDEF(VT); 1455 // fall through 1456 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1457 R==APFloat::cmpEqual, VT); 1458 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1459 return getUNDEF(VT); 1460 // fall through 1461 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1462 R==APFloat::cmpEqual, VT); 1463 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1464 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1465 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1466 R==APFloat::cmpEqual, VT); 1467 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1468 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1469 R==APFloat::cmpLessThan, VT); 1470 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1471 R==APFloat::cmpUnordered, VT); 1472 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1473 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1474 } 1475 } else { 1476 // Ensure that the constant occurs on the RHS. 1477 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1478 } 1479 } 1480 1481 // Could not fold it. 1482 return SDValue(); 1483} 1484 1485/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1486/// use this predicate to simplify operations downstream. 1487bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1488 unsigned BitWidth = Op.getValueSizeInBits(); 1489 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1490} 1491 1492/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1493/// this predicate to simplify operations downstream. Mask is known to be zero 1494/// for bits that V cannot have. 1495bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1496 unsigned Depth) const { 1497 APInt KnownZero, KnownOne; 1498 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1499 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1500 return (KnownZero & Mask) == Mask; 1501} 1502 1503/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1504/// known to be either zero or one and return them in the KnownZero/KnownOne 1505/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1506/// processing. 1507void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1508 APInt &KnownZero, APInt &KnownOne, 1509 unsigned Depth) const { 1510 unsigned BitWidth = Mask.getBitWidth(); 1511 assert(BitWidth == Op.getValueType().getSizeInBits() && 1512 "Mask size mismatches value type size!"); 1513 1514 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1515 if (Depth == 6 || Mask == 0) 1516 return; // Limit search depth. 1517 1518 APInt KnownZero2, KnownOne2; 1519 1520 switch (Op.getOpcode()) { 1521 case ISD::Constant: 1522 // We know all of the bits for a constant! 1523 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1524 KnownZero = ~KnownOne & Mask; 1525 return; 1526 case ISD::AND: 1527 // If either the LHS or the RHS are Zero, the result is zero. 1528 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1529 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1530 KnownZero2, KnownOne2, Depth+1); 1531 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1532 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1533 1534 // Output known-1 bits are only known if set in both the LHS & RHS. 1535 KnownOne &= KnownOne2; 1536 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1537 KnownZero |= KnownZero2; 1538 return; 1539 case ISD::OR: 1540 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1541 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1542 KnownZero2, KnownOne2, Depth+1); 1543 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1544 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1545 1546 // Output known-0 bits are only known if clear in both the LHS & RHS. 1547 KnownZero &= KnownZero2; 1548 // Output known-1 are known to be set if set in either the LHS | RHS. 1549 KnownOne |= KnownOne2; 1550 return; 1551 case ISD::XOR: { 1552 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1553 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1554 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1555 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1556 1557 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1558 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1559 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1560 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1561 KnownZero = KnownZeroOut; 1562 return; 1563 } 1564 case ISD::MUL: { 1565 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1566 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1567 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1568 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1569 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1570 1571 // If low bits are zero in either operand, output low known-0 bits. 1572 // Also compute a conserative estimate for high known-0 bits. 1573 // More trickiness is possible, but this is sufficient for the 1574 // interesting case of alignment computation. 1575 KnownOne.clear(); 1576 unsigned TrailZ = KnownZero.countTrailingOnes() + 1577 KnownZero2.countTrailingOnes(); 1578 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1579 KnownZero2.countLeadingOnes(), 1580 BitWidth) - BitWidth; 1581 1582 TrailZ = std::min(TrailZ, BitWidth); 1583 LeadZ = std::min(LeadZ, BitWidth); 1584 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1585 APInt::getHighBitsSet(BitWidth, LeadZ); 1586 KnownZero &= Mask; 1587 return; 1588 } 1589 case ISD::UDIV: { 1590 // For the purposes of computing leading zeros we can conservatively 1591 // treat a udiv as a logical right shift by the power of 2 known to 1592 // be less than the denominator. 1593 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1594 ComputeMaskedBits(Op.getOperand(0), 1595 AllOnes, KnownZero2, KnownOne2, Depth+1); 1596 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1597 1598 KnownOne2.clear(); 1599 KnownZero2.clear(); 1600 ComputeMaskedBits(Op.getOperand(1), 1601 AllOnes, KnownZero2, KnownOne2, Depth+1); 1602 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1603 if (RHSUnknownLeadingOnes != BitWidth) 1604 LeadZ = std::min(BitWidth, 1605 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1606 1607 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1608 return; 1609 } 1610 case ISD::SELECT: 1611 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1612 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1613 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1614 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1615 1616 // Only known if known in both the LHS and RHS. 1617 KnownOne &= KnownOne2; 1618 KnownZero &= KnownZero2; 1619 return; 1620 case ISD::SELECT_CC: 1621 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1622 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1623 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1624 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1625 1626 // Only known if known in both the LHS and RHS. 1627 KnownOne &= KnownOne2; 1628 KnownZero &= KnownZero2; 1629 return; 1630 case ISD::SADDO: 1631 case ISD::UADDO: 1632 case ISD::SSUBO: 1633 case ISD::USUBO: 1634 case ISD::SMULO: 1635 case ISD::UMULO: 1636 if (Op.getResNo() != 1) 1637 return; 1638 // The boolean result conforms to getBooleanContents. Fall through. 1639 case ISD::SETCC: 1640 // If we know the result of a setcc has the top bits zero, use this info. 1641 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1642 BitWidth > 1) 1643 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1644 return; 1645 case ISD::SHL: 1646 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1647 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1648 unsigned ShAmt = SA->getZExtValue(); 1649 1650 // If the shift count is an invalid immediate, don't do anything. 1651 if (ShAmt >= BitWidth) 1652 return; 1653 1654 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1655 KnownZero, KnownOne, Depth+1); 1656 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1657 KnownZero <<= ShAmt; 1658 KnownOne <<= ShAmt; 1659 // low bits known zero. 1660 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1661 } 1662 return; 1663 case ISD::SRL: 1664 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1665 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1666 unsigned ShAmt = SA->getZExtValue(); 1667 1668 // If the shift count is an invalid immediate, don't do anything. 1669 if (ShAmt >= BitWidth) 1670 return; 1671 1672 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1673 KnownZero, KnownOne, Depth+1); 1674 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1675 KnownZero = KnownZero.lshr(ShAmt); 1676 KnownOne = KnownOne.lshr(ShAmt); 1677 1678 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1679 KnownZero |= HighBits; // High bits known zero. 1680 } 1681 return; 1682 case ISD::SRA: 1683 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1684 unsigned ShAmt = SA->getZExtValue(); 1685 1686 // If the shift count is an invalid immediate, don't do anything. 1687 if (ShAmt >= BitWidth) 1688 return; 1689 1690 APInt InDemandedMask = (Mask << ShAmt); 1691 // If any of the demanded bits are produced by the sign extension, we also 1692 // demand the input sign bit. 1693 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1694 if (HighBits.getBoolValue()) 1695 InDemandedMask |= APInt::getSignBit(BitWidth); 1696 1697 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1698 Depth+1); 1699 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1700 KnownZero = KnownZero.lshr(ShAmt); 1701 KnownOne = KnownOne.lshr(ShAmt); 1702 1703 // Handle the sign bits. 1704 APInt SignBit = APInt::getSignBit(BitWidth); 1705 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1706 1707 if (KnownZero.intersects(SignBit)) { 1708 KnownZero |= HighBits; // New bits are known zero. 1709 } else if (KnownOne.intersects(SignBit)) { 1710 KnownOne |= HighBits; // New bits are known one. 1711 } 1712 } 1713 return; 1714 case ISD::SIGN_EXTEND_INREG: { 1715 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1716 unsigned EBits = EVT.getSizeInBits(); 1717 1718 // Sign extension. Compute the demanded bits in the result that are not 1719 // present in the input. 1720 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1721 1722 APInt InSignBit = APInt::getSignBit(EBits); 1723 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1724 1725 // If the sign extended bits are demanded, we know that the sign 1726 // bit is demanded. 1727 InSignBit.zext(BitWidth); 1728 if (NewBits.getBoolValue()) 1729 InputDemandedBits |= InSignBit; 1730 1731 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1732 KnownZero, KnownOne, Depth+1); 1733 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1734 1735 // If the sign bit of the input is known set or clear, then we know the 1736 // top bits of the result. 1737 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1738 KnownZero |= NewBits; 1739 KnownOne &= ~NewBits; 1740 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1741 KnownOne |= NewBits; 1742 KnownZero &= ~NewBits; 1743 } else { // Input sign bit unknown 1744 KnownZero &= ~NewBits; 1745 KnownOne &= ~NewBits; 1746 } 1747 return; 1748 } 1749 case ISD::CTTZ: 1750 case ISD::CTLZ: 1751 case ISD::CTPOP: { 1752 unsigned LowBits = Log2_32(BitWidth)+1; 1753 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1754 KnownOne.clear(); 1755 return; 1756 } 1757 case ISD::LOAD: { 1758 if (ISD::isZEXTLoad(Op.getNode())) { 1759 LoadSDNode *LD = cast<LoadSDNode>(Op); 1760 MVT VT = LD->getMemoryVT(); 1761 unsigned MemBits = VT.getSizeInBits(); 1762 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1763 } 1764 return; 1765 } 1766 case ISD::ZERO_EXTEND: { 1767 MVT InVT = Op.getOperand(0).getValueType(); 1768 unsigned InBits = InVT.getSizeInBits(); 1769 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1770 APInt InMask = Mask; 1771 InMask.trunc(InBits); 1772 KnownZero.trunc(InBits); 1773 KnownOne.trunc(InBits); 1774 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1775 KnownZero.zext(BitWidth); 1776 KnownOne.zext(BitWidth); 1777 KnownZero |= NewBits; 1778 return; 1779 } 1780 case ISD::SIGN_EXTEND: { 1781 MVT InVT = Op.getOperand(0).getValueType(); 1782 unsigned InBits = InVT.getSizeInBits(); 1783 APInt InSignBit = APInt::getSignBit(InBits); 1784 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1785 APInt InMask = Mask; 1786 InMask.trunc(InBits); 1787 1788 // If any of the sign extended bits are demanded, we know that the sign 1789 // bit is demanded. Temporarily set this bit in the mask for our callee. 1790 if (NewBits.getBoolValue()) 1791 InMask |= InSignBit; 1792 1793 KnownZero.trunc(InBits); 1794 KnownOne.trunc(InBits); 1795 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1796 1797 // Note if the sign bit is known to be zero or one. 1798 bool SignBitKnownZero = KnownZero.isNegative(); 1799 bool SignBitKnownOne = KnownOne.isNegative(); 1800 assert(!(SignBitKnownZero && SignBitKnownOne) && 1801 "Sign bit can't be known to be both zero and one!"); 1802 1803 // If the sign bit wasn't actually demanded by our caller, we don't 1804 // want it set in the KnownZero and KnownOne result values. Reset the 1805 // mask and reapply it to the result values. 1806 InMask = Mask; 1807 InMask.trunc(InBits); 1808 KnownZero &= InMask; 1809 KnownOne &= InMask; 1810 1811 KnownZero.zext(BitWidth); 1812 KnownOne.zext(BitWidth); 1813 1814 // If the sign bit is known zero or one, the top bits match. 1815 if (SignBitKnownZero) 1816 KnownZero |= NewBits; 1817 else if (SignBitKnownOne) 1818 KnownOne |= NewBits; 1819 return; 1820 } 1821 case ISD::ANY_EXTEND: { 1822 MVT InVT = Op.getOperand(0).getValueType(); 1823 unsigned InBits = InVT.getSizeInBits(); 1824 APInt InMask = Mask; 1825 InMask.trunc(InBits); 1826 KnownZero.trunc(InBits); 1827 KnownOne.trunc(InBits); 1828 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1829 KnownZero.zext(BitWidth); 1830 KnownOne.zext(BitWidth); 1831 return; 1832 } 1833 case ISD::TRUNCATE: { 1834 MVT InVT = Op.getOperand(0).getValueType(); 1835 unsigned InBits = InVT.getSizeInBits(); 1836 APInt InMask = Mask; 1837 InMask.zext(InBits); 1838 KnownZero.zext(InBits); 1839 KnownOne.zext(InBits); 1840 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1841 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1842 KnownZero.trunc(BitWidth); 1843 KnownOne.trunc(BitWidth); 1844 break; 1845 } 1846 case ISD::AssertZext: { 1847 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1848 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1849 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1850 KnownOne, Depth+1); 1851 KnownZero |= (~InMask) & Mask; 1852 return; 1853 } 1854 case ISD::FGETSIGN: 1855 // All bits are zero except the low bit. 1856 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1857 return; 1858 1859 case ISD::SUB: { 1860 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1861 // We know that the top bits of C-X are clear if X contains less bits 1862 // than C (i.e. no wrap-around can happen). For example, 20-X is 1863 // positive if we can prove that X is >= 0 and < 16. 1864 if (CLHS->getAPIntValue().isNonNegative()) { 1865 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1866 // NLZ can't be BitWidth with no sign bit 1867 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1868 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1869 Depth+1); 1870 1871 // If all of the MaskV bits are known to be zero, then we know the 1872 // output top bits are zero, because we now know that the output is 1873 // from [0-C]. 1874 if ((KnownZero2 & MaskV) == MaskV) { 1875 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1876 // Top bits known zero. 1877 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1878 } 1879 } 1880 } 1881 } 1882 // fall through 1883 case ISD::ADD: { 1884 // Output known-0 bits are known if clear or set in both the low clear bits 1885 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1886 // low 3 bits clear. 1887 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1888 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1889 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1890 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1891 1892 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1893 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1894 KnownZeroOut = std::min(KnownZeroOut, 1895 KnownZero2.countTrailingOnes()); 1896 1897 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1898 return; 1899 } 1900 case ISD::SREM: 1901 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1902 const APInt &RA = Rem->getAPIntValue(); 1903 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1904 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1905 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1906 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1907 1908 // If the sign bit of the first operand is zero, the sign bit of 1909 // the result is zero. If the first operand has no one bits below 1910 // the second operand's single 1 bit, its sign will be zero. 1911 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1912 KnownZero2 |= ~LowBits; 1913 1914 KnownZero |= KnownZero2 & Mask; 1915 1916 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1917 } 1918 } 1919 return; 1920 case ISD::UREM: { 1921 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1922 const APInt &RA = Rem->getAPIntValue(); 1923 if (RA.isPowerOf2()) { 1924 APInt LowBits = (RA - 1); 1925 APInt Mask2 = LowBits & Mask; 1926 KnownZero |= ~LowBits & Mask; 1927 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1928 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1929 break; 1930 } 1931 } 1932 1933 // Since the result is less than or equal to either operand, any leading 1934 // zero bits in either operand must also exist in the result. 1935 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1936 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1937 Depth+1); 1938 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1939 Depth+1); 1940 1941 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1942 KnownZero2.countLeadingOnes()); 1943 KnownOne.clear(); 1944 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1945 return; 1946 } 1947 default: 1948 // Allow the target to implement this method for its nodes. 1949 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1950 case ISD::INTRINSIC_WO_CHAIN: 1951 case ISD::INTRINSIC_W_CHAIN: 1952 case ISD::INTRINSIC_VOID: 1953 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1954 } 1955 return; 1956 } 1957} 1958 1959/// ComputeNumSignBits - Return the number of times the sign bit of the 1960/// register is replicated into the other bits. We know that at least 1 bit 1961/// is always equal to the sign bit (itself), but other cases can give us 1962/// information. For example, immediately after an "SRA X, 2", we know that 1963/// the top 3 bits are all equal to each other, so we return 3. 1964unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1965 MVT VT = Op.getValueType(); 1966 assert(VT.isInteger() && "Invalid VT!"); 1967 unsigned VTBits = VT.getSizeInBits(); 1968 unsigned Tmp, Tmp2; 1969 unsigned FirstAnswer = 1; 1970 1971 if (Depth == 6) 1972 return 1; // Limit search depth. 1973 1974 switch (Op.getOpcode()) { 1975 default: break; 1976 case ISD::AssertSext: 1977 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1978 return VTBits-Tmp+1; 1979 case ISD::AssertZext: 1980 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1981 return VTBits-Tmp; 1982 1983 case ISD::Constant: { 1984 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1985 // If negative, return # leading ones. 1986 if (Val.isNegative()) 1987 return Val.countLeadingOnes(); 1988 1989 // Return # leading zeros. 1990 return Val.countLeadingZeros(); 1991 } 1992 1993 case ISD::SIGN_EXTEND: 1994 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1995 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1996 1997 case ISD::SIGN_EXTEND_INREG: 1998 // Max of the input and what this extends. 1999 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 2000 Tmp = VTBits-Tmp+1; 2001 2002 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2003 return std::max(Tmp, Tmp2); 2004 2005 case ISD::SRA: 2006 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2007 // SRA X, C -> adds C sign bits. 2008 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2009 Tmp += C->getZExtValue(); 2010 if (Tmp > VTBits) Tmp = VTBits; 2011 } 2012 return Tmp; 2013 case ISD::SHL: 2014 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2015 // shl destroys sign bits. 2016 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2017 if (C->getZExtValue() >= VTBits || // Bad shift. 2018 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 2019 return Tmp - C->getZExtValue(); 2020 } 2021 break; 2022 case ISD::AND: 2023 case ISD::OR: 2024 case ISD::XOR: // NOT is handled here. 2025 // Logical binary ops preserve the number of sign bits at the worst. 2026 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2027 if (Tmp != 1) { 2028 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2029 FirstAnswer = std::min(Tmp, Tmp2); 2030 // We computed what we know about the sign bits as our first 2031 // answer. Now proceed to the generic code that uses 2032 // ComputeMaskedBits, and pick whichever answer is better. 2033 } 2034 break; 2035 2036 case ISD::SELECT: 2037 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2038 if (Tmp == 1) return 1; // Early out. 2039 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 2040 return std::min(Tmp, Tmp2); 2041 2042 case ISD::SADDO: 2043 case ISD::UADDO: 2044 case ISD::SSUBO: 2045 case ISD::USUBO: 2046 case ISD::SMULO: 2047 case ISD::UMULO: 2048 if (Op.getResNo() != 1) 2049 break; 2050 // The boolean result conforms to getBooleanContents. Fall through. 2051 case ISD::SETCC: 2052 // If setcc returns 0/-1, all bits are sign bits. 2053 if (TLI.getBooleanContents() == 2054 TargetLowering::ZeroOrNegativeOneBooleanContent) 2055 return VTBits; 2056 break; 2057 case ISD::ROTL: 2058 case ISD::ROTR: 2059 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2060 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 2061 2062 // Handle rotate right by N like a rotate left by 32-N. 2063 if (Op.getOpcode() == ISD::ROTR) 2064 RotAmt = (VTBits-RotAmt) & (VTBits-1); 2065 2066 // If we aren't rotating out all of the known-in sign bits, return the 2067 // number that are left. This handles rotl(sext(x), 1) for example. 2068 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2069 if (Tmp > RotAmt+1) return Tmp-RotAmt; 2070 } 2071 break; 2072 case ISD::ADD: 2073 // Add can have at most one carry bit. Thus we know that the output 2074 // is, at worst, one more bit than the inputs. 2075 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2076 if (Tmp == 1) return 1; // Early out. 2077 2078 // Special case decrementing a value (ADD X, -1): 2079 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 2080 if (CRHS->isAllOnesValue()) { 2081 APInt KnownZero, KnownOne; 2082 APInt Mask = APInt::getAllOnesValue(VTBits); 2083 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 2084 2085 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2086 // sign bits set. 2087 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2088 return VTBits; 2089 2090 // If we are subtracting one from a positive number, there is no carry 2091 // out of the result. 2092 if (KnownZero.isNegative()) 2093 return Tmp; 2094 } 2095 2096 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2097 if (Tmp2 == 1) return 1; 2098 return std::min(Tmp, Tmp2)-1; 2099 break; 2100 2101 case ISD::SUB: 2102 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2103 if (Tmp2 == 1) return 1; 2104 2105 // Handle NEG. 2106 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 2107 if (CLHS->isNullValue()) { 2108 APInt KnownZero, KnownOne; 2109 APInt Mask = APInt::getAllOnesValue(VTBits); 2110 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 2111 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2112 // sign bits set. 2113 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2114 return VTBits; 2115 2116 // If the input is known to be positive (the sign bit is known clear), 2117 // the output of the NEG has the same number of sign bits as the input. 2118 if (KnownZero.isNegative()) 2119 return Tmp2; 2120 2121 // Otherwise, we treat this like a SUB. 2122 } 2123 2124 // Sub can have at most one carry bit. Thus we know that the output 2125 // is, at worst, one more bit than the inputs. 2126 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2127 if (Tmp == 1) return 1; // Early out. 2128 return std::min(Tmp, Tmp2)-1; 2129 break; 2130 case ISD::TRUNCATE: 2131 // FIXME: it's tricky to do anything useful for this, but it is an important 2132 // case for targets like X86. 2133 break; 2134 } 2135 2136 // Handle LOADX separately here. EXTLOAD case will fallthrough. 2137 if (Op.getOpcode() == ISD::LOAD) { 2138 LoadSDNode *LD = cast<LoadSDNode>(Op); 2139 unsigned ExtType = LD->getExtensionType(); 2140 switch (ExtType) { 2141 default: break; 2142 case ISD::SEXTLOAD: // '17' bits known 2143 Tmp = LD->getMemoryVT().getSizeInBits(); 2144 return VTBits-Tmp+1; 2145 case ISD::ZEXTLOAD: // '16' bits known 2146 Tmp = LD->getMemoryVT().getSizeInBits(); 2147 return VTBits-Tmp; 2148 } 2149 } 2150 2151 // Allow the target to implement this method for its nodes. 2152 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2153 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2154 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2155 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2156 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2157 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2158 } 2159 2160 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2161 // use this information. 2162 APInt KnownZero, KnownOne; 2163 APInt Mask = APInt::getAllOnesValue(VTBits); 2164 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2165 2166 if (KnownZero.isNegative()) { // sign bit is 0 2167 Mask = KnownZero; 2168 } else if (KnownOne.isNegative()) { // sign bit is 1; 2169 Mask = KnownOne; 2170 } else { 2171 // Nothing known. 2172 return FirstAnswer; 2173 } 2174 2175 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2176 // the number of identical bits in the top of the input value. 2177 Mask = ~Mask; 2178 Mask <<= Mask.getBitWidth()-VTBits; 2179 // Return # leading zeros. We use 'min' here in case Val was zero before 2180 // shifting. We don't want to return '64' as for an i32 "0". 2181 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2182} 2183 2184 2185bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2186 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2187 if (!GA) return false; 2188 if (GA->getOffset() != 0) return false; 2189 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2190 if (!GV) return false; 2191 MachineModuleInfo *MMI = getMachineModuleInfo(); 2192 return MMI && MMI->hasDebugInfo(); 2193} 2194 2195 2196/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2197/// element of the result of the vector shuffle. 2198SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N, 2199 unsigned i) { 2200 MVT VT = N->getValueType(0); 2201 DebugLoc dl = N->getDebugLoc(); 2202 if (N->getMaskElt(i) < 0) 2203 return getUNDEF(VT.getVectorElementType()); 2204 unsigned Index = N->getMaskElt(i); 2205 unsigned NumElems = VT.getVectorNumElements(); 2206 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2207 Index %= NumElems; 2208 2209 if (V.getOpcode() == ISD::BIT_CONVERT) { 2210 V = V.getOperand(0); 2211 MVT VVT = V.getValueType(); 2212 if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems) 2213 return SDValue(); 2214 } 2215 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2216 return (Index == 0) ? V.getOperand(0) 2217 : getUNDEF(VT.getVectorElementType()); 2218 if (V.getOpcode() == ISD::BUILD_VECTOR) 2219 return V.getOperand(Index); 2220 if (const ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(V)) 2221 return getShuffleScalarElt(SVN, Index); 2222 return SDValue(); 2223} 2224 2225 2226/// getNode - Gets or creates the specified node. 2227/// 2228SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) { 2229 FoldingSetNodeID ID; 2230 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2231 void *IP = 0; 2232 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2233 return SDValue(E, 0); 2234 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2235 new (N) SDNode(Opcode, DL, getVTList(VT)); 2236 CSEMap.InsertNode(N, IP); 2237 2238 AllNodes.push_back(N); 2239#ifndef NDEBUG 2240 VerifyNode(N); 2241#endif 2242 return SDValue(N, 0); 2243} 2244 2245SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 2246 MVT VT, SDValue Operand) { 2247 // Constant fold unary operations with an integer constant operand. 2248 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2249 const APInt &Val = C->getAPIntValue(); 2250 unsigned BitWidth = VT.getSizeInBits(); 2251 switch (Opcode) { 2252 default: break; 2253 case ISD::SIGN_EXTEND: 2254 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2255 case ISD::ANY_EXTEND: 2256 case ISD::ZERO_EXTEND: 2257 case ISD::TRUNCATE: 2258 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2259 case ISD::UINT_TO_FP: 2260 case ISD::SINT_TO_FP: { 2261 const uint64_t zero[] = {0, 0}; 2262 // No compile time operations on this type. 2263 if (VT==MVT::ppcf128) 2264 break; 2265 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2266 (void)apf.convertFromAPInt(Val, 2267 Opcode==ISD::SINT_TO_FP, 2268 APFloat::rmNearestTiesToEven); 2269 return getConstantFP(apf, VT); 2270 } 2271 case ISD::BIT_CONVERT: 2272 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2273 return getConstantFP(Val.bitsToFloat(), VT); 2274 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2275 return getConstantFP(Val.bitsToDouble(), VT); 2276 break; 2277 case ISD::BSWAP: 2278 return getConstant(Val.byteSwap(), VT); 2279 case ISD::CTPOP: 2280 return getConstant(Val.countPopulation(), VT); 2281 case ISD::CTLZ: 2282 return getConstant(Val.countLeadingZeros(), VT); 2283 case ISD::CTTZ: 2284 return getConstant(Val.countTrailingZeros(), VT); 2285 } 2286 } 2287 2288 // Constant fold unary operations with a floating point constant operand. 2289 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2290 APFloat V = C->getValueAPF(); // make copy 2291 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2292 switch (Opcode) { 2293 case ISD::FNEG: 2294 V.changeSign(); 2295 return getConstantFP(V, VT); 2296 case ISD::FABS: 2297 V.clearSign(); 2298 return getConstantFP(V, VT); 2299 case ISD::FP_ROUND: 2300 case ISD::FP_EXTEND: { 2301 bool ignored; 2302 // This can return overflow, underflow, or inexact; we don't care. 2303 // FIXME need to be more flexible about rounding mode. 2304 (void)V.convert(*MVTToAPFloatSemantics(VT), 2305 APFloat::rmNearestTiesToEven, &ignored); 2306 return getConstantFP(V, VT); 2307 } 2308 case ISD::FP_TO_SINT: 2309 case ISD::FP_TO_UINT: { 2310 integerPart x[2]; 2311 bool ignored; 2312 assert(integerPartWidth >= 64); 2313 // FIXME need to be more flexible about rounding mode. 2314 APFloat::opStatus s = V.convertToInteger(x, VT.getSizeInBits(), 2315 Opcode==ISD::FP_TO_SINT, 2316 APFloat::rmTowardZero, &ignored); 2317 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2318 break; 2319 APInt api(VT.getSizeInBits(), 2, x); 2320 return getConstant(api, VT); 2321 } 2322 case ISD::BIT_CONVERT: 2323 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2324 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2325 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2326 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2327 break; 2328 } 2329 } 2330 } 2331 2332 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2333 switch (Opcode) { 2334 case ISD::TokenFactor: 2335 case ISD::MERGE_VALUES: 2336 case ISD::CONCAT_VECTORS: 2337 return Operand; // Factor, merge or concat of one node? No need. 2338 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2339 case ISD::FP_EXTEND: 2340 assert(VT.isFloatingPoint() && 2341 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2342 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2343 if (Operand.getOpcode() == ISD::UNDEF) 2344 return getUNDEF(VT); 2345 break; 2346 case ISD::SIGN_EXTEND: 2347 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2348 "Invalid SIGN_EXTEND!"); 2349 if (Operand.getValueType() == VT) return Operand; // noop extension 2350 assert(Operand.getValueType().bitsLT(VT) 2351 && "Invalid sext node, dst < src!"); 2352 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2353 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2354 break; 2355 case ISD::ZERO_EXTEND: 2356 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2357 "Invalid ZERO_EXTEND!"); 2358 if (Operand.getValueType() == VT) return Operand; // noop extension 2359 assert(Operand.getValueType().bitsLT(VT) 2360 && "Invalid zext node, dst < src!"); 2361 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2362 return getNode(ISD::ZERO_EXTEND, DL, VT, 2363 Operand.getNode()->getOperand(0)); 2364 break; 2365 case ISD::ANY_EXTEND: 2366 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2367 "Invalid ANY_EXTEND!"); 2368 if (Operand.getValueType() == VT) return Operand; // noop extension 2369 assert(Operand.getValueType().bitsLT(VT) 2370 && "Invalid anyext node, dst < src!"); 2371 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2372 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2373 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2374 break; 2375 case ISD::TRUNCATE: 2376 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2377 "Invalid TRUNCATE!"); 2378 if (Operand.getValueType() == VT) return Operand; // noop truncate 2379 assert(Operand.getValueType().bitsGT(VT) 2380 && "Invalid truncate node, src < dst!"); 2381 if (OpOpcode == ISD::TRUNCATE) 2382 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2383 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2384 OpOpcode == ISD::ANY_EXTEND) { 2385 // If the source is smaller than the dest, we still need an extend. 2386 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2387 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2388 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2389 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2390 else 2391 return Operand.getNode()->getOperand(0); 2392 } 2393 break; 2394 case ISD::BIT_CONVERT: 2395 // Basic sanity checking. 2396 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2397 && "Cannot BIT_CONVERT between types of different sizes!"); 2398 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2399 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2400 return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0)); 2401 if (OpOpcode == ISD::UNDEF) 2402 return getUNDEF(VT); 2403 break; 2404 case ISD::SCALAR_TO_VECTOR: 2405 assert(VT.isVector() && !Operand.getValueType().isVector() && 2406 (VT.getVectorElementType() == Operand.getValueType() || 2407 (VT.getVectorElementType().isInteger() && 2408 Operand.getValueType().isInteger() && 2409 VT.getVectorElementType().bitsLE(Operand.getValueType()))) && 2410 "Illegal SCALAR_TO_VECTOR node!"); 2411 if (OpOpcode == ISD::UNDEF) 2412 return getUNDEF(VT); 2413 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2414 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2415 isa<ConstantSDNode>(Operand.getOperand(1)) && 2416 Operand.getConstantOperandVal(1) == 0 && 2417 Operand.getOperand(0).getValueType() == VT) 2418 return Operand.getOperand(0); 2419 break; 2420 case ISD::FNEG: 2421 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 2422 if (UnsafeFPMath && OpOpcode == ISD::FSUB) 2423 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1), 2424 Operand.getNode()->getOperand(0)); 2425 if (OpOpcode == ISD::FNEG) // --X -> X 2426 return Operand.getNode()->getOperand(0); 2427 break; 2428 case ISD::FABS: 2429 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2430 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0)); 2431 break; 2432 } 2433 2434 SDNode *N; 2435 SDVTList VTs = getVTList(VT); 2436 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2437 FoldingSetNodeID ID; 2438 SDValue Ops[1] = { Operand }; 2439 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2440 void *IP = 0; 2441 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2442 return SDValue(E, 0); 2443 N = NodeAllocator.Allocate<UnarySDNode>(); 2444 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2445 CSEMap.InsertNode(N, IP); 2446 } else { 2447 N = NodeAllocator.Allocate<UnarySDNode>(); 2448 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2449 } 2450 2451 AllNodes.push_back(N); 2452#ifndef NDEBUG 2453 VerifyNode(N); 2454#endif 2455 return SDValue(N, 0); 2456} 2457 2458SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2459 MVT VT, 2460 ConstantSDNode *Cst1, 2461 ConstantSDNode *Cst2) { 2462 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2463 2464 switch (Opcode) { 2465 case ISD::ADD: return getConstant(C1 + C2, VT); 2466 case ISD::SUB: return getConstant(C1 - C2, VT); 2467 case ISD::MUL: return getConstant(C1 * C2, VT); 2468 case ISD::UDIV: 2469 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2470 break; 2471 case ISD::UREM: 2472 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2473 break; 2474 case ISD::SDIV: 2475 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2476 break; 2477 case ISD::SREM: 2478 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2479 break; 2480 case ISD::AND: return getConstant(C1 & C2, VT); 2481 case ISD::OR: return getConstant(C1 | C2, VT); 2482 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2483 case ISD::SHL: return getConstant(C1 << C2, VT); 2484 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2485 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2486 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2487 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2488 default: break; 2489 } 2490 2491 return SDValue(); 2492} 2493 2494SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2495 SDValue N1, SDValue N2) { 2496 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2497 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2498 switch (Opcode) { 2499 default: break; 2500 case ISD::TokenFactor: 2501 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2502 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2503 // Fold trivial token factors. 2504 if (N1.getOpcode() == ISD::EntryToken) return N2; 2505 if (N2.getOpcode() == ISD::EntryToken) return N1; 2506 if (N1 == N2) return N1; 2507 break; 2508 case ISD::CONCAT_VECTORS: 2509 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2510 // one big BUILD_VECTOR. 2511 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2512 N2.getOpcode() == ISD::BUILD_VECTOR) { 2513 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2514 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2515 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2516 } 2517 break; 2518 case ISD::AND: 2519 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2520 N1.getValueType() == VT && "Binary operator types must match!"); 2521 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2522 // worth handling here. 2523 if (N2C && N2C->isNullValue()) 2524 return N2; 2525 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2526 return N1; 2527 break; 2528 case ISD::OR: 2529 case ISD::XOR: 2530 case ISD::ADD: 2531 case ISD::SUB: 2532 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2533 N1.getValueType() == VT && "Binary operator types must match!"); 2534 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2535 // it's worth handling here. 2536 if (N2C && N2C->isNullValue()) 2537 return N1; 2538 break; 2539 case ISD::UDIV: 2540 case ISD::UREM: 2541 case ISD::MULHU: 2542 case ISD::MULHS: 2543 case ISD::MUL: 2544 case ISD::SDIV: 2545 case ISD::SREM: 2546 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2547 // fall through 2548 case ISD::FADD: 2549 case ISD::FSUB: 2550 case ISD::FMUL: 2551 case ISD::FDIV: 2552 case ISD::FREM: 2553 if (UnsafeFPMath) { 2554 if (Opcode == ISD::FADD) { 2555 // 0+x --> x 2556 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) 2557 if (CFP->getValueAPF().isZero()) 2558 return N2; 2559 // x+0 --> x 2560 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2561 if (CFP->getValueAPF().isZero()) 2562 return N1; 2563 } else if (Opcode == ISD::FSUB) { 2564 // x-0 --> x 2565 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2566 if (CFP->getValueAPF().isZero()) 2567 return N1; 2568 } 2569 } 2570 assert(N1.getValueType() == N2.getValueType() && 2571 N1.getValueType() == VT && "Binary operator types must match!"); 2572 break; 2573 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2574 assert(N1.getValueType() == VT && 2575 N1.getValueType().isFloatingPoint() && 2576 N2.getValueType().isFloatingPoint() && 2577 "Invalid FCOPYSIGN!"); 2578 break; 2579 case ISD::SHL: 2580 case ISD::SRA: 2581 case ISD::SRL: 2582 case ISD::ROTL: 2583 case ISD::ROTR: 2584 assert(VT == N1.getValueType() && 2585 "Shift operators return type must be the same as their first arg"); 2586 assert(VT.isInteger() && N2.getValueType().isInteger() && 2587 "Shifts only work on integers"); 2588 2589 // Always fold shifts of i1 values so the code generator doesn't need to 2590 // handle them. Since we know the size of the shift has to be less than the 2591 // size of the value, the shift/rotate count is guaranteed to be zero. 2592 if (VT == MVT::i1) 2593 return N1; 2594 break; 2595 case ISD::FP_ROUND_INREG: { 2596 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2597 assert(VT == N1.getValueType() && "Not an inreg round!"); 2598 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2599 "Cannot FP_ROUND_INREG integer types"); 2600 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2601 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2602 break; 2603 } 2604 case ISD::FP_ROUND: 2605 assert(VT.isFloatingPoint() && 2606 N1.getValueType().isFloatingPoint() && 2607 VT.bitsLE(N1.getValueType()) && 2608 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2609 if (N1.getValueType() == VT) return N1; // noop conversion. 2610 break; 2611 case ISD::AssertSext: 2612 case ISD::AssertZext: { 2613 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2614 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2615 assert(VT.isInteger() && EVT.isInteger() && 2616 "Cannot *_EXTEND_INREG FP types"); 2617 assert(EVT.bitsLE(VT) && "Not extending!"); 2618 if (VT == EVT) return N1; // noop assertion. 2619 break; 2620 } 2621 case ISD::SIGN_EXTEND_INREG: { 2622 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2623 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2624 assert(VT.isInteger() && EVT.isInteger() && 2625 "Cannot *_EXTEND_INREG FP types"); 2626 assert(EVT.bitsLE(VT) && "Not extending!"); 2627 if (EVT == VT) return N1; // Not actually extending 2628 2629 if (N1C) { 2630 APInt Val = N1C->getAPIntValue(); 2631 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2632 Val <<= Val.getBitWidth()-FromBits; 2633 Val = Val.ashr(Val.getBitWidth()-FromBits); 2634 return getConstant(Val, VT); 2635 } 2636 break; 2637 } 2638 case ISD::EXTRACT_VECTOR_ELT: 2639 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2640 if (N1.getOpcode() == ISD::UNDEF) 2641 return getUNDEF(VT); 2642 2643 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2644 // expanding copies of large vectors from registers. 2645 if (N2C && 2646 N1.getOpcode() == ISD::CONCAT_VECTORS && 2647 N1.getNumOperands() > 0) { 2648 unsigned Factor = 2649 N1.getOperand(0).getValueType().getVectorNumElements(); 2650 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, 2651 N1.getOperand(N2C->getZExtValue() / Factor), 2652 getConstant(N2C->getZExtValue() % Factor, 2653 N2.getValueType())); 2654 } 2655 2656 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2657 // expanding large vector constants. 2658 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) { 2659 SDValue Elt = N1.getOperand(N2C->getZExtValue()); 2660 if (Elt.getValueType() != VT) { 2661 // If the vector element type is not legal, the BUILD_VECTOR operands 2662 // are promoted and implicitly truncated. Make that explicit here. 2663 assert(VT.isInteger() && Elt.getValueType().isInteger() && 2664 VT.bitsLE(Elt.getValueType()) && 2665 "Bad type for BUILD_VECTOR operand"); 2666 Elt = getNode(ISD::TRUNCATE, DL, VT, Elt); 2667 } 2668 return Elt; 2669 } 2670 2671 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2672 // operations are lowered to scalars. 2673 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2674 // If the indices are the same, return the inserted element. 2675 if (N1.getOperand(2) == N2) 2676 return N1.getOperand(1); 2677 // If the indices are known different, extract the element from 2678 // the original vector. 2679 else if (isa<ConstantSDNode>(N1.getOperand(2)) && 2680 isa<ConstantSDNode>(N2)) 2681 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2); 2682 } 2683 break; 2684 case ISD::EXTRACT_ELEMENT: 2685 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2686 assert(!N1.getValueType().isVector() && !VT.isVector() && 2687 (N1.getValueType().isInteger() == VT.isInteger()) && 2688 "Wrong types for EXTRACT_ELEMENT!"); 2689 2690 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2691 // 64-bit integers into 32-bit parts. Instead of building the extract of 2692 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2693 if (N1.getOpcode() == ISD::BUILD_PAIR) 2694 return N1.getOperand(N2C->getZExtValue()); 2695 2696 // EXTRACT_ELEMENT of a constant int is also very common. 2697 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2698 unsigned ElementSize = VT.getSizeInBits(); 2699 unsigned Shift = ElementSize * N2C->getZExtValue(); 2700 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2701 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2702 } 2703 break; 2704 case ISD::EXTRACT_SUBVECTOR: 2705 if (N1.getValueType() == VT) // Trivial extraction. 2706 return N1; 2707 break; 2708 } 2709 2710 if (N1C) { 2711 if (N2C) { 2712 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2713 if (SV.getNode()) return SV; 2714 } else { // Cannonicalize constant to RHS if commutative 2715 if (isCommutativeBinOp(Opcode)) { 2716 std::swap(N1C, N2C); 2717 std::swap(N1, N2); 2718 } 2719 } 2720 } 2721 2722 // Constant fold FP operations. 2723 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2724 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2725 if (N1CFP) { 2726 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2727 // Cannonicalize constant to RHS if commutative 2728 std::swap(N1CFP, N2CFP); 2729 std::swap(N1, N2); 2730 } else if (N2CFP && VT != MVT::ppcf128) { 2731 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2732 APFloat::opStatus s; 2733 switch (Opcode) { 2734 case ISD::FADD: 2735 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2736 if (s != APFloat::opInvalidOp) 2737 return getConstantFP(V1, VT); 2738 break; 2739 case ISD::FSUB: 2740 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2741 if (s!=APFloat::opInvalidOp) 2742 return getConstantFP(V1, VT); 2743 break; 2744 case ISD::FMUL: 2745 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2746 if (s!=APFloat::opInvalidOp) 2747 return getConstantFP(V1, VT); 2748 break; 2749 case ISD::FDIV: 2750 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2751 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2752 return getConstantFP(V1, VT); 2753 break; 2754 case ISD::FREM : 2755 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2756 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2757 return getConstantFP(V1, VT); 2758 break; 2759 case ISD::FCOPYSIGN: 2760 V1.copySign(V2); 2761 return getConstantFP(V1, VT); 2762 default: break; 2763 } 2764 } 2765 } 2766 2767 // Canonicalize an UNDEF to the RHS, even over a constant. 2768 if (N1.getOpcode() == ISD::UNDEF) { 2769 if (isCommutativeBinOp(Opcode)) { 2770 std::swap(N1, N2); 2771 } else { 2772 switch (Opcode) { 2773 case ISD::FP_ROUND_INREG: 2774 case ISD::SIGN_EXTEND_INREG: 2775 case ISD::SUB: 2776 case ISD::FSUB: 2777 case ISD::FDIV: 2778 case ISD::FREM: 2779 case ISD::SRA: 2780 return N1; // fold op(undef, arg2) -> undef 2781 case ISD::UDIV: 2782 case ISD::SDIV: 2783 case ISD::UREM: 2784 case ISD::SREM: 2785 case ISD::SRL: 2786 case ISD::SHL: 2787 if (!VT.isVector()) 2788 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2789 // For vectors, we can't easily build an all zero vector, just return 2790 // the LHS. 2791 return N2; 2792 } 2793 } 2794 } 2795 2796 // Fold a bunch of operators when the RHS is undef. 2797 if (N2.getOpcode() == ISD::UNDEF) { 2798 switch (Opcode) { 2799 case ISD::XOR: 2800 if (N1.getOpcode() == ISD::UNDEF) 2801 // Handle undef ^ undef -> 0 special case. This is a common 2802 // idiom (misuse). 2803 return getConstant(0, VT); 2804 // fallthrough 2805 case ISD::ADD: 2806 case ISD::ADDC: 2807 case ISD::ADDE: 2808 case ISD::SUB: 2809 case ISD::FADD: 2810 case ISD::FSUB: 2811 case ISD::FMUL: 2812 case ISD::FDIV: 2813 case ISD::FREM: 2814 case ISD::UDIV: 2815 case ISD::SDIV: 2816 case ISD::UREM: 2817 case ISD::SREM: 2818 return N2; // fold op(arg1, undef) -> undef 2819 case ISD::MUL: 2820 case ISD::AND: 2821 case ISD::SRL: 2822 case ISD::SHL: 2823 if (!VT.isVector()) 2824 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2825 // For vectors, we can't easily build an all zero vector, just return 2826 // the LHS. 2827 return N1; 2828 case ISD::OR: 2829 if (!VT.isVector()) 2830 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 2831 // For vectors, we can't easily build an all one vector, just return 2832 // the LHS. 2833 return N1; 2834 case ISD::SRA: 2835 return N1; 2836 } 2837 } 2838 2839 // Memoize this node if possible. 2840 SDNode *N; 2841 SDVTList VTs = getVTList(VT); 2842 if (VT != MVT::Flag) { 2843 SDValue Ops[] = { N1, N2 }; 2844 FoldingSetNodeID ID; 2845 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2846 void *IP = 0; 2847 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2848 return SDValue(E, 0); 2849 N = NodeAllocator.Allocate<BinarySDNode>(); 2850 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2851 CSEMap.InsertNode(N, IP); 2852 } else { 2853 N = NodeAllocator.Allocate<BinarySDNode>(); 2854 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2855 } 2856 2857 AllNodes.push_back(N); 2858#ifndef NDEBUG 2859 VerifyNode(N); 2860#endif 2861 return SDValue(N, 0); 2862} 2863 2864SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2865 SDValue N1, SDValue N2, SDValue N3) { 2866 // Perform various simplifications. 2867 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2868 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2869 switch (Opcode) { 2870 case ISD::CONCAT_VECTORS: 2871 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2872 // one big BUILD_VECTOR. 2873 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2874 N2.getOpcode() == ISD::BUILD_VECTOR && 2875 N3.getOpcode() == ISD::BUILD_VECTOR) { 2876 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2877 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2878 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2879 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2880 } 2881 break; 2882 case ISD::SETCC: { 2883 // Use FoldSetCC to simplify SETCC's. 2884 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL); 2885 if (Simp.getNode()) return Simp; 2886 break; 2887 } 2888 case ISD::SELECT: 2889 if (N1C) { 2890 if (N1C->getZExtValue()) 2891 return N2; // select true, X, Y -> X 2892 else 2893 return N3; // select false, X, Y -> Y 2894 } 2895 2896 if (N2 == N3) return N2; // select C, X, X -> X 2897 break; 2898 case ISD::BRCOND: 2899 if (N2C) { 2900 if (N2C->getZExtValue()) // Unconditional branch 2901 return getNode(ISD::BR, DL, MVT::Other, N1, N3); 2902 else 2903 return N1; // Never-taken branch 2904 } 2905 break; 2906 case ISD::VECTOR_SHUFFLE: 2907 assert(0 && "should use getVectorShuffle constructor!"); 2908 break; 2909 case ISD::BIT_CONVERT: 2910 // Fold bit_convert nodes from a type to themselves. 2911 if (N1.getValueType() == VT) 2912 return N1; 2913 break; 2914 } 2915 2916 // Memoize node if it doesn't produce a flag. 2917 SDNode *N; 2918 SDVTList VTs = getVTList(VT); 2919 if (VT != MVT::Flag) { 2920 SDValue Ops[] = { N1, N2, N3 }; 2921 FoldingSetNodeID ID; 2922 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2923 void *IP = 0; 2924 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2925 return SDValue(E, 0); 2926 N = NodeAllocator.Allocate<TernarySDNode>(); 2927 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2928 CSEMap.InsertNode(N, IP); 2929 } else { 2930 N = NodeAllocator.Allocate<TernarySDNode>(); 2931 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2932 } 2933 AllNodes.push_back(N); 2934#ifndef NDEBUG 2935 VerifyNode(N); 2936#endif 2937 return SDValue(N, 0); 2938} 2939 2940SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2941 SDValue N1, SDValue N2, SDValue N3, 2942 SDValue N4) { 2943 SDValue Ops[] = { N1, N2, N3, N4 }; 2944 return getNode(Opcode, DL, VT, Ops, 4); 2945} 2946 2947SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2948 SDValue N1, SDValue N2, SDValue N3, 2949 SDValue N4, SDValue N5) { 2950 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2951 return getNode(Opcode, DL, VT, Ops, 5); 2952} 2953 2954/// getMemsetValue - Vectorized representation of the memset value 2955/// operand. 2956static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG, 2957 DebugLoc dl) { 2958 unsigned NumBits = VT.isVector() ? 2959 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2960 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2961 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2962 unsigned Shift = 8; 2963 for (unsigned i = NumBits; i > 8; i >>= 1) { 2964 Val = (Val << Shift) | Val; 2965 Shift <<= 1; 2966 } 2967 if (VT.isInteger()) 2968 return DAG.getConstant(Val, VT); 2969 return DAG.getConstantFP(APFloat(Val), VT); 2970 } 2971 2972 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2973 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); 2974 unsigned Shift = 8; 2975 for (unsigned i = NumBits; i > 8; i >>= 1) { 2976 Value = DAG.getNode(ISD::OR, dl, VT, 2977 DAG.getNode(ISD::SHL, dl, VT, Value, 2978 DAG.getConstant(Shift, 2979 TLI.getShiftAmountTy())), 2980 Value); 2981 Shift <<= 1; 2982 } 2983 2984 return Value; 2985} 2986 2987/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2988/// used when a memcpy is turned into a memset when the source is a constant 2989/// string ptr. 2990static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, 2991 const TargetLowering &TLI, 2992 std::string &Str, unsigned Offset) { 2993 // Handle vector with all elements zero. 2994 if (Str.empty()) { 2995 if (VT.isInteger()) 2996 return DAG.getConstant(0, VT); 2997 unsigned NumElts = VT.getVectorNumElements(); 2998 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2999 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3000 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 3001 } 3002 3003 assert(!VT.isVector() && "Can't handle vector type here!"); 3004 unsigned NumBits = VT.getSizeInBits(); 3005 unsigned MSB = NumBits / 8; 3006 uint64_t Val = 0; 3007 if (TLI.isLittleEndian()) 3008 Offset = Offset + MSB - 1; 3009 for (unsigned i = 0; i != MSB; ++i) { 3010 Val = (Val << 8) | (unsigned char)Str[Offset]; 3011 Offset += TLI.isLittleEndian() ? -1 : 1; 3012 } 3013 return DAG.getConstant(Val, VT); 3014} 3015 3016/// getMemBasePlusOffset - Returns base and offset node for the 3017/// 3018static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 3019 SelectionDAG &DAG) { 3020 MVT VT = Base.getValueType(); 3021 return DAG.getNode(ISD::ADD, Base.getDebugLoc(), 3022 VT, Base, DAG.getConstant(Offset, VT)); 3023} 3024 3025/// isMemSrcFromString - Returns true if memcpy source is a string constant. 3026/// 3027static bool isMemSrcFromString(SDValue Src, std::string &Str) { 3028 unsigned SrcDelta = 0; 3029 GlobalAddressSDNode *G = NULL; 3030 if (Src.getOpcode() == ISD::GlobalAddress) 3031 G = cast<GlobalAddressSDNode>(Src); 3032 else if (Src.getOpcode() == ISD::ADD && 3033 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 3034 Src.getOperand(1).getOpcode() == ISD::Constant) { 3035 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 3036 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 3037 } 3038 if (!G) 3039 return false; 3040 3041 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 3042 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 3043 return true; 3044 3045 return false; 3046} 3047 3048/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 3049/// to replace the memset / memcpy is below the threshold. It also returns the 3050/// types of the sequence of memory ops to perform memset / memcpy. 3051static 3052bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 3053 SDValue Dst, SDValue Src, 3054 unsigned Limit, uint64_t Size, unsigned &Align, 3055 std::string &Str, bool &isSrcStr, 3056 SelectionDAG &DAG, 3057 const TargetLowering &TLI) { 3058 isSrcStr = isMemSrcFromString(Src, Str); 3059 bool isSrcConst = isa<ConstantSDNode>(Src); 3060 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 3061 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 3062 if (VT != MVT::iAny) { 3063 unsigned NewAlign = (unsigned) 3064 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 3065 // If source is a string constant, this will require an unaligned load. 3066 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 3067 if (Dst.getOpcode() != ISD::FrameIndex) { 3068 // Can't change destination alignment. It requires a unaligned store. 3069 if (AllowUnalign) 3070 VT = MVT::iAny; 3071 } else { 3072 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 3073 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3074 if (MFI->isFixedObjectIndex(FI)) { 3075 // Can't change destination alignment. It requires a unaligned store. 3076 if (AllowUnalign) 3077 VT = MVT::iAny; 3078 } else { 3079 // Give the stack frame object a larger alignment if needed. 3080 if (MFI->getObjectAlignment(FI) < NewAlign) 3081 MFI->setObjectAlignment(FI, NewAlign); 3082 Align = NewAlign; 3083 } 3084 } 3085 } 3086 } 3087 3088 if (VT == MVT::iAny) { 3089 if (AllowUnalign) { 3090 VT = MVT::i64; 3091 } else { 3092 switch (Align & 7) { 3093 case 0: VT = MVT::i64; break; 3094 case 4: VT = MVT::i32; break; 3095 case 2: VT = MVT::i16; break; 3096 default: VT = MVT::i8; break; 3097 } 3098 } 3099 3100 MVT LVT = MVT::i64; 3101 while (!TLI.isTypeLegal(LVT)) 3102 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 3103 assert(LVT.isInteger()); 3104 3105 if (VT.bitsGT(LVT)) 3106 VT = LVT; 3107 } 3108 3109 unsigned NumMemOps = 0; 3110 while (Size != 0) { 3111 unsigned VTSize = VT.getSizeInBits() / 8; 3112 while (VTSize > Size) { 3113 // For now, only use non-vector load / store's for the left-over pieces. 3114 if (VT.isVector()) { 3115 VT = MVT::i64; 3116 while (!TLI.isTypeLegal(VT)) 3117 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3118 VTSize = VT.getSizeInBits() / 8; 3119 } else { 3120 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3121 VTSize >>= 1; 3122 } 3123 } 3124 3125 if (++NumMemOps > Limit) 3126 return false; 3127 MemOps.push_back(VT); 3128 Size -= VTSize; 3129 } 3130 3131 return true; 3132} 3133 3134static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3135 SDValue Chain, SDValue Dst, 3136 SDValue Src, uint64_t Size, 3137 unsigned Align, bool AlwaysInline, 3138 const Value *DstSV, uint64_t DstSVOff, 3139 const Value *SrcSV, uint64_t SrcSVOff){ 3140 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3141 3142 // Expand memcpy to a series of load and store ops if the size operand falls 3143 // below a certain threshold. 3144 std::vector<MVT> MemOps; 3145 uint64_t Limit = -1ULL; 3146 if (!AlwaysInline) 3147 Limit = TLI.getMaxStoresPerMemcpy(); 3148 unsigned DstAlign = Align; // Destination alignment can change. 3149 std::string Str; 3150 bool CopyFromStr; 3151 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3152 Str, CopyFromStr, DAG, TLI)) 3153 return SDValue(); 3154 3155 3156 bool isZeroStr = CopyFromStr && Str.empty(); 3157 SmallVector<SDValue, 8> OutChains; 3158 unsigned NumMemOps = MemOps.size(); 3159 uint64_t SrcOff = 0, DstOff = 0; 3160 for (unsigned i = 0; i < NumMemOps; i++) { 3161 MVT VT = MemOps[i]; 3162 unsigned VTSize = VT.getSizeInBits() / 8; 3163 SDValue Value, Store; 3164 3165 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 3166 // It's unlikely a store of a vector immediate can be done in a single 3167 // instruction. It would require a load from a constantpool first. 3168 // We also handle store a vector with all zero's. 3169 // FIXME: Handle other cases where store of vector immediate is done in 3170 // a single instruction. 3171 Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff); 3172 Store = DAG.getStore(Chain, dl, Value, 3173 getMemBasePlusOffset(Dst, DstOff, DAG), 3174 DstSV, DstSVOff + DstOff, false, DstAlign); 3175 } else { 3176 Value = DAG.getLoad(VT, dl, Chain, 3177 getMemBasePlusOffset(Src, SrcOff, DAG), 3178 SrcSV, SrcSVOff + SrcOff, false, Align); 3179 Store = DAG.getStore(Chain, dl, Value, 3180 getMemBasePlusOffset(Dst, DstOff, DAG), 3181 DstSV, DstSVOff + DstOff, false, DstAlign); 3182 } 3183 OutChains.push_back(Store); 3184 SrcOff += VTSize; 3185 DstOff += VTSize; 3186 } 3187 3188 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3189 &OutChains[0], OutChains.size()); 3190} 3191 3192static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3193 SDValue Chain, SDValue Dst, 3194 SDValue Src, uint64_t Size, 3195 unsigned Align, bool AlwaysInline, 3196 const Value *DstSV, uint64_t DstSVOff, 3197 const Value *SrcSV, uint64_t SrcSVOff){ 3198 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3199 3200 // Expand memmove to a series of load and store ops if the size operand falls 3201 // below a certain threshold. 3202 std::vector<MVT> MemOps; 3203 uint64_t Limit = -1ULL; 3204 if (!AlwaysInline) 3205 Limit = TLI.getMaxStoresPerMemmove(); 3206 unsigned DstAlign = Align; // Destination alignment can change. 3207 std::string Str; 3208 bool CopyFromStr; 3209 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3210 Str, CopyFromStr, DAG, TLI)) 3211 return SDValue(); 3212 3213 uint64_t SrcOff = 0, DstOff = 0; 3214 3215 SmallVector<SDValue, 8> LoadValues; 3216 SmallVector<SDValue, 8> LoadChains; 3217 SmallVector<SDValue, 8> OutChains; 3218 unsigned NumMemOps = MemOps.size(); 3219 for (unsigned i = 0; i < NumMemOps; i++) { 3220 MVT VT = MemOps[i]; 3221 unsigned VTSize = VT.getSizeInBits() / 8; 3222 SDValue Value, Store; 3223 3224 Value = DAG.getLoad(VT, dl, Chain, 3225 getMemBasePlusOffset(Src, SrcOff, DAG), 3226 SrcSV, SrcSVOff + SrcOff, false, Align); 3227 LoadValues.push_back(Value); 3228 LoadChains.push_back(Value.getValue(1)); 3229 SrcOff += VTSize; 3230 } 3231 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3232 &LoadChains[0], LoadChains.size()); 3233 OutChains.clear(); 3234 for (unsigned i = 0; i < NumMemOps; i++) { 3235 MVT VT = MemOps[i]; 3236 unsigned VTSize = VT.getSizeInBits() / 8; 3237 SDValue Value, Store; 3238 3239 Store = DAG.getStore(Chain, dl, LoadValues[i], 3240 getMemBasePlusOffset(Dst, DstOff, DAG), 3241 DstSV, DstSVOff + DstOff, false, DstAlign); 3242 OutChains.push_back(Store); 3243 DstOff += VTSize; 3244 } 3245 3246 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3247 &OutChains[0], OutChains.size()); 3248} 3249 3250static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, 3251 SDValue Chain, SDValue Dst, 3252 SDValue Src, uint64_t Size, 3253 unsigned Align, 3254 const Value *DstSV, uint64_t DstSVOff) { 3255 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3256 3257 // Expand memset to a series of load/store ops if the size operand 3258 // falls below a certain threshold. 3259 std::vector<MVT> MemOps; 3260 std::string Str; 3261 bool CopyFromStr; 3262 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3263 Size, Align, Str, CopyFromStr, DAG, TLI)) 3264 return SDValue(); 3265 3266 SmallVector<SDValue, 8> OutChains; 3267 uint64_t DstOff = 0; 3268 3269 unsigned NumMemOps = MemOps.size(); 3270 for (unsigned i = 0; i < NumMemOps; i++) { 3271 MVT VT = MemOps[i]; 3272 unsigned VTSize = VT.getSizeInBits() / 8; 3273 SDValue Value = getMemsetValue(Src, VT, DAG, dl); 3274 SDValue Store = DAG.getStore(Chain, dl, Value, 3275 getMemBasePlusOffset(Dst, DstOff, DAG), 3276 DstSV, DstSVOff + DstOff); 3277 OutChains.push_back(Store); 3278 DstOff += VTSize; 3279 } 3280 3281 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3282 &OutChains[0], OutChains.size()); 3283} 3284 3285SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, 3286 SDValue Src, SDValue Size, 3287 unsigned Align, bool AlwaysInline, 3288 const Value *DstSV, uint64_t DstSVOff, 3289 const Value *SrcSV, uint64_t SrcSVOff) { 3290 3291 // Check to see if we should lower the memcpy to loads and stores first. 3292 // For cases within the target-specified limits, this is the best choice. 3293 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3294 if (ConstantSize) { 3295 // Memcpy with size zero? Just return the original chain. 3296 if (ConstantSize->isNullValue()) 3297 return Chain; 3298 3299 SDValue Result = 3300 getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3301 ConstantSize->getZExtValue(), 3302 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3303 if (Result.getNode()) 3304 return Result; 3305 } 3306 3307 // Then check to see if we should lower the memcpy with target-specific 3308 // code. If the target chooses to do this, this is the next best. 3309 SDValue Result = 3310 TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align, 3311 AlwaysInline, 3312 DstSV, DstSVOff, SrcSV, SrcSVOff); 3313 if (Result.getNode()) 3314 return Result; 3315 3316 // If we really need inline code and the target declined to provide it, 3317 // use a (potentially long) sequence of loads and stores. 3318 if (AlwaysInline) { 3319 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3320 return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3321 ConstantSize->getZExtValue(), Align, true, 3322 DstSV, DstSVOff, SrcSV, SrcSVOff); 3323 } 3324 3325 // Emit a library call. 3326 TargetLowering::ArgListTy Args; 3327 TargetLowering::ArgListEntry Entry; 3328 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3329 Entry.Node = Dst; Args.push_back(Entry); 3330 Entry.Node = Src; Args.push_back(Entry); 3331 Entry.Node = Size; Args.push_back(Entry); 3332 // FIXME: pass in DebugLoc 3333 std::pair<SDValue,SDValue> CallResult = 3334 TLI.LowerCallTo(Chain, Type::VoidTy, 3335 false, false, false, false, CallingConv::C, false, 3336 getExternalSymbol("memcpy", TLI.getPointerTy()), 3337 Args, *this, dl); 3338 return CallResult.second; 3339} 3340 3341SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, 3342 SDValue Src, SDValue Size, 3343 unsigned Align, 3344 const Value *DstSV, uint64_t DstSVOff, 3345 const Value *SrcSV, uint64_t SrcSVOff) { 3346 3347 // Check to see if we should lower the memmove to loads and stores first. 3348 // For cases within the target-specified limits, this is the best choice. 3349 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3350 if (ConstantSize) { 3351 // Memmove with size zero? Just return the original chain. 3352 if (ConstantSize->isNullValue()) 3353 return Chain; 3354 3355 SDValue Result = 3356 getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src, 3357 ConstantSize->getZExtValue(), 3358 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3359 if (Result.getNode()) 3360 return Result; 3361 } 3362 3363 // Then check to see if we should lower the memmove with target-specific 3364 // code. If the target chooses to do this, this is the next best. 3365 SDValue Result = 3366 TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align, 3367 DstSV, DstSVOff, SrcSV, SrcSVOff); 3368 if (Result.getNode()) 3369 return Result; 3370 3371 // Emit a library call. 3372 TargetLowering::ArgListTy Args; 3373 TargetLowering::ArgListEntry Entry; 3374 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3375 Entry.Node = Dst; Args.push_back(Entry); 3376 Entry.Node = Src; Args.push_back(Entry); 3377 Entry.Node = Size; Args.push_back(Entry); 3378 // FIXME: pass in DebugLoc 3379 std::pair<SDValue,SDValue> CallResult = 3380 TLI.LowerCallTo(Chain, Type::VoidTy, 3381 false, false, false, false, CallingConv::C, false, 3382 getExternalSymbol("memmove", TLI.getPointerTy()), 3383 Args, *this, dl); 3384 return CallResult.second; 3385} 3386 3387SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, 3388 SDValue Src, SDValue Size, 3389 unsigned Align, 3390 const Value *DstSV, uint64_t DstSVOff) { 3391 3392 // Check to see if we should lower the memset to stores first. 3393 // For cases within the target-specified limits, this is the best choice. 3394 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3395 if (ConstantSize) { 3396 // Memset with size zero? Just return the original chain. 3397 if (ConstantSize->isNullValue()) 3398 return Chain; 3399 3400 SDValue Result = 3401 getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), 3402 Align, DstSV, DstSVOff); 3403 if (Result.getNode()) 3404 return Result; 3405 } 3406 3407 // Then check to see if we should lower the memset with target-specific 3408 // code. If the target chooses to do this, this is the next best. 3409 SDValue Result = 3410 TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align, 3411 DstSV, DstSVOff); 3412 if (Result.getNode()) 3413 return Result; 3414 3415 // Emit a library call. 3416 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3417 TargetLowering::ArgListTy Args; 3418 TargetLowering::ArgListEntry Entry; 3419 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3420 Args.push_back(Entry); 3421 // Extend or truncate the argument to be an i32 value for the call. 3422 if (Src.getValueType().bitsGT(MVT::i32)) 3423 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src); 3424 else 3425 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); 3426 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3427 Args.push_back(Entry); 3428 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3429 Args.push_back(Entry); 3430 // FIXME: pass in DebugLoc 3431 std::pair<SDValue,SDValue> CallResult = 3432 TLI.LowerCallTo(Chain, Type::VoidTy, 3433 false, false, false, false, CallingConv::C, false, 3434 getExternalSymbol("memset", TLI.getPointerTy()), 3435 Args, *this, dl); 3436 return CallResult.second; 3437} 3438 3439SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3440 SDValue Chain, 3441 SDValue Ptr, SDValue Cmp, 3442 SDValue Swp, const Value* PtrVal, 3443 unsigned Alignment) { 3444 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); 3445 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3446 3447 MVT VT = Cmp.getValueType(); 3448 3449 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3450 Alignment = getMVTAlignment(MemVT); 3451 3452 SDVTList VTs = getVTList(VT, MVT::Other); 3453 FoldingSetNodeID ID; 3454 ID.AddInteger(MemVT.getRawBits()); 3455 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3456 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3457 void* IP = 0; 3458 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3459 return SDValue(E, 0); 3460 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3461 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3462 Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3463 CSEMap.InsertNode(N, IP); 3464 AllNodes.push_back(N); 3465 return SDValue(N, 0); 3466} 3467 3468SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3469 SDValue Chain, 3470 SDValue Ptr, SDValue Val, 3471 const Value* PtrVal, 3472 unsigned Alignment) { 3473 assert((Opcode == ISD::ATOMIC_LOAD_ADD || 3474 Opcode == ISD::ATOMIC_LOAD_SUB || 3475 Opcode == ISD::ATOMIC_LOAD_AND || 3476 Opcode == ISD::ATOMIC_LOAD_OR || 3477 Opcode == ISD::ATOMIC_LOAD_XOR || 3478 Opcode == ISD::ATOMIC_LOAD_NAND || 3479 Opcode == ISD::ATOMIC_LOAD_MIN || 3480 Opcode == ISD::ATOMIC_LOAD_MAX || 3481 Opcode == ISD::ATOMIC_LOAD_UMIN || 3482 Opcode == ISD::ATOMIC_LOAD_UMAX || 3483 Opcode == ISD::ATOMIC_SWAP) && 3484 "Invalid Atomic Op"); 3485 3486 MVT VT = Val.getValueType(); 3487 3488 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3489 Alignment = getMVTAlignment(MemVT); 3490 3491 SDVTList VTs = getVTList(VT, MVT::Other); 3492 FoldingSetNodeID ID; 3493 ID.AddInteger(MemVT.getRawBits()); 3494 SDValue Ops[] = {Chain, Ptr, Val}; 3495 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3496 void* IP = 0; 3497 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3498 return SDValue(E, 0); 3499 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3500 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3501 Chain, Ptr, Val, PtrVal, Alignment); 3502 CSEMap.InsertNode(N, IP); 3503 AllNodes.push_back(N); 3504 return SDValue(N, 0); 3505} 3506 3507/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3508/// Allowed to return something different (and simpler) if Simplify is true. 3509SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3510 DebugLoc dl) { 3511 if (NumOps == 1) 3512 return Ops[0]; 3513 3514 SmallVector<MVT, 4> VTs; 3515 VTs.reserve(NumOps); 3516 for (unsigned i = 0; i < NumOps; ++i) 3517 VTs.push_back(Ops[i].getValueType()); 3518 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps), 3519 Ops, NumOps); 3520} 3521 3522SDValue 3523SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, 3524 const MVT *VTs, unsigned NumVTs, 3525 const SDValue *Ops, unsigned NumOps, 3526 MVT MemVT, const Value *srcValue, int SVOff, 3527 unsigned Align, bool Vol, 3528 bool ReadMem, bool WriteMem) { 3529 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps, 3530 MemVT, srcValue, SVOff, Align, Vol, 3531 ReadMem, WriteMem); 3532} 3533 3534SDValue 3535SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, 3536 const SDValue *Ops, unsigned NumOps, 3537 MVT MemVT, const Value *srcValue, int SVOff, 3538 unsigned Align, bool Vol, 3539 bool ReadMem, bool WriteMem) { 3540 // Memoize the node unless it returns a flag. 3541 MemIntrinsicSDNode *N; 3542 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3543 FoldingSetNodeID ID; 3544 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3545 void *IP = 0; 3546 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3547 return SDValue(E, 0); 3548 3549 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3550 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3551 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3552 CSEMap.InsertNode(N, IP); 3553 } else { 3554 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3555 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3556 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3557 } 3558 AllNodes.push_back(N); 3559 return SDValue(N, 0); 3560} 3561 3562SDValue 3563SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, 3564 bool IsTailCall, bool IsInreg, SDVTList VTs, 3565 const SDValue *Operands, unsigned NumOperands) { 3566 // Do not include isTailCall in the folding set profile. 3567 FoldingSetNodeID ID; 3568 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3569 ID.AddInteger(CallingConv); 3570 ID.AddInteger(IsVarArgs); 3571 void *IP = 0; 3572 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3573 // Instead of including isTailCall in the folding set, we just 3574 // set the flag of the existing node. 3575 if (!IsTailCall) 3576 cast<CallSDNode>(E)->setNotTailCall(); 3577 return SDValue(E, 0); 3578 } 3579 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3580 new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg, 3581 VTs, Operands, NumOperands); 3582 CSEMap.InsertNode(N, IP); 3583 AllNodes.push_back(N); 3584 return SDValue(N, 0); 3585} 3586 3587SDValue 3588SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, 3589 ISD::LoadExtType ExtType, MVT VT, SDValue Chain, 3590 SDValue Ptr, SDValue Offset, 3591 const Value *SV, int SVOffset, MVT EVT, 3592 bool isVolatile, unsigned Alignment) { 3593 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3594 Alignment = getMVTAlignment(VT); 3595 3596 if (VT == EVT) { 3597 ExtType = ISD::NON_EXTLOAD; 3598 } else if (ExtType == ISD::NON_EXTLOAD) { 3599 assert(VT == EVT && "Non-extending load from different memory type!"); 3600 } else { 3601 // Extending load. 3602 if (VT.isVector()) 3603 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3604 "Invalid vector extload!"); 3605 else 3606 assert(EVT.bitsLT(VT) && 3607 "Should only be an extending load, not truncating!"); 3608 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3609 "Cannot sign/zero extend a FP/Vector load!"); 3610 assert(VT.isInteger() == EVT.isInteger() && 3611 "Cannot convert from FP to Int or Int -> FP!"); 3612 } 3613 3614 bool Indexed = AM != ISD::UNINDEXED; 3615 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3616 "Unindexed load with an offset!"); 3617 3618 SDVTList VTs = Indexed ? 3619 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3620 SDValue Ops[] = { Chain, Ptr, Offset }; 3621 FoldingSetNodeID ID; 3622 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3623 ID.AddInteger(EVT.getRawBits()); 3624 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); 3625 void *IP = 0; 3626 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3627 return SDValue(E, 0); 3628 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3629 new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset, 3630 Alignment, isVolatile); 3631 CSEMap.InsertNode(N, IP); 3632 AllNodes.push_back(N); 3633 return SDValue(N, 0); 3634} 3635 3636SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, 3637 SDValue Chain, SDValue Ptr, 3638 const Value *SV, int SVOffset, 3639 bool isVolatile, unsigned Alignment) { 3640 SDValue Undef = getUNDEF(Ptr.getValueType()); 3641 return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3642 SV, SVOffset, VT, isVolatile, Alignment); 3643} 3644 3645SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, 3646 SDValue Chain, SDValue Ptr, 3647 const Value *SV, 3648 int SVOffset, MVT EVT, 3649 bool isVolatile, unsigned Alignment) { 3650 SDValue Undef = getUNDEF(Ptr.getValueType()); 3651 return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef, 3652 SV, SVOffset, EVT, isVolatile, Alignment); 3653} 3654 3655SDValue 3656SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, 3657 SDValue Offset, ISD::MemIndexedMode AM) { 3658 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3659 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3660 "Load is already a indexed load!"); 3661 return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(), 3662 LD->getChain(), Base, Offset, LD->getSrcValue(), 3663 LD->getSrcValueOffset(), LD->getMemoryVT(), 3664 LD->isVolatile(), LD->getAlignment()); 3665} 3666 3667SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, 3668 SDValue Ptr, const Value *SV, int SVOffset, 3669 bool isVolatile, unsigned Alignment) { 3670 MVT VT = Val.getValueType(); 3671 3672 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3673 Alignment = getMVTAlignment(VT); 3674 3675 SDVTList VTs = getVTList(MVT::Other); 3676 SDValue Undef = getUNDEF(Ptr.getValueType()); 3677 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3678 FoldingSetNodeID ID; 3679 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3680 ID.AddInteger(VT.getRawBits()); 3681 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, 3682 isVolatile, Alignment)); 3683 void *IP = 0; 3684 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3685 return SDValue(E, 0); 3686 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3687 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false, 3688 VT, SV, SVOffset, Alignment, isVolatile); 3689 CSEMap.InsertNode(N, IP); 3690 AllNodes.push_back(N); 3691 return SDValue(N, 0); 3692} 3693 3694SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, 3695 SDValue Ptr, const Value *SV, 3696 int SVOffset, MVT SVT, 3697 bool isVolatile, unsigned Alignment) { 3698 MVT VT = Val.getValueType(); 3699 3700 if (VT == SVT) 3701 return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3702 3703 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3704 assert(VT.isInteger() == SVT.isInteger() && 3705 "Can't do FP-INT conversion!"); 3706 3707 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3708 Alignment = getMVTAlignment(VT); 3709 3710 SDVTList VTs = getVTList(MVT::Other); 3711 SDValue Undef = getUNDEF(Ptr.getValueType()); 3712 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3713 FoldingSetNodeID ID; 3714 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3715 ID.AddInteger(SVT.getRawBits()); 3716 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, 3717 isVolatile, Alignment)); 3718 void *IP = 0; 3719 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3720 return SDValue(E, 0); 3721 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3722 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true, 3723 SVT, SV, SVOffset, Alignment, isVolatile); 3724 CSEMap.InsertNode(N, IP); 3725 AllNodes.push_back(N); 3726 return SDValue(N, 0); 3727} 3728 3729SDValue 3730SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, 3731 SDValue Offset, ISD::MemIndexedMode AM) { 3732 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3733 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3734 "Store is already a indexed store!"); 3735 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3736 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3737 FoldingSetNodeID ID; 3738 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3739 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3740 ID.AddInteger(ST->getRawSubclassData()); 3741 void *IP = 0; 3742 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3743 return SDValue(E, 0); 3744 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3745 new (N) StoreSDNode(Ops, dl, VTs, AM, 3746 ST->isTruncatingStore(), ST->getMemoryVT(), 3747 ST->getSrcValue(), ST->getSrcValueOffset(), 3748 ST->getAlignment(), ST->isVolatile()); 3749 CSEMap.InsertNode(N, IP); 3750 AllNodes.push_back(N); 3751 return SDValue(N, 0); 3752} 3753 3754SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl, 3755 SDValue Chain, SDValue Ptr, 3756 SDValue SV) { 3757 SDValue Ops[] = { Chain, Ptr, SV }; 3758 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3); 3759} 3760 3761SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3762 const SDUse *Ops, unsigned NumOps) { 3763 switch (NumOps) { 3764 case 0: return getNode(Opcode, DL, VT); 3765 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3766 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3767 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3768 default: break; 3769 } 3770 3771 // Copy from an SDUse array into an SDValue array for use with 3772 // the regular getNode logic. 3773 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3774 return getNode(Opcode, DL, VT, &NewOps[0], NumOps); 3775} 3776 3777SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3778 const SDValue *Ops, unsigned NumOps) { 3779 switch (NumOps) { 3780 case 0: return getNode(Opcode, DL, VT); 3781 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3782 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3783 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3784 default: break; 3785 } 3786 3787 switch (Opcode) { 3788 default: break; 3789 case ISD::SELECT_CC: { 3790 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3791 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3792 "LHS and RHS of condition must have same type!"); 3793 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3794 "True and False arms of SelectCC must have same type!"); 3795 assert(Ops[2].getValueType() == VT && 3796 "select_cc node must be of same type as true and false value!"); 3797 break; 3798 } 3799 case ISD::BR_CC: { 3800 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3801 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3802 "LHS/RHS of comparison should match types!"); 3803 break; 3804 } 3805 } 3806 3807 // Memoize nodes. 3808 SDNode *N; 3809 SDVTList VTs = getVTList(VT); 3810 3811 if (VT != MVT::Flag) { 3812 FoldingSetNodeID ID; 3813 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3814 void *IP = 0; 3815 3816 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3817 return SDValue(E, 0); 3818 3819 N = NodeAllocator.Allocate<SDNode>(); 3820 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3821 CSEMap.InsertNode(N, IP); 3822 } else { 3823 N = NodeAllocator.Allocate<SDNode>(); 3824 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3825 } 3826 3827 AllNodes.push_back(N); 3828#ifndef NDEBUG 3829 VerifyNode(N); 3830#endif 3831 return SDValue(N, 0); 3832} 3833 3834SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3835 const std::vector<MVT> &ResultTys, 3836 const SDValue *Ops, unsigned NumOps) { 3837 return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()), 3838 Ops, NumOps); 3839} 3840 3841SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3842 const MVT *VTs, unsigned NumVTs, 3843 const SDValue *Ops, unsigned NumOps) { 3844 if (NumVTs == 1) 3845 return getNode(Opcode, DL, VTs[0], Ops, NumOps); 3846 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps); 3847} 3848 3849SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3850 const SDValue *Ops, unsigned NumOps) { 3851 if (VTList.NumVTs == 1) 3852 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps); 3853 3854 switch (Opcode) { 3855 // FIXME: figure out how to safely handle things like 3856 // int foo(int x) { return 1 << (x & 255); } 3857 // int bar() { return foo(256); } 3858#if 0 3859 case ISD::SRA_PARTS: 3860 case ISD::SRL_PARTS: 3861 case ISD::SHL_PARTS: 3862 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3863 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3864 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3865 else if (N3.getOpcode() == ISD::AND) 3866 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3867 // If the and is only masking out bits that cannot effect the shift, 3868 // eliminate the and. 3869 unsigned NumBits = VT.getSizeInBits()*2; 3870 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3871 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3872 } 3873 break; 3874#endif 3875 } 3876 3877 // Memoize the node unless it returns a flag. 3878 SDNode *N; 3879 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3880 FoldingSetNodeID ID; 3881 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3882 void *IP = 0; 3883 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3884 return SDValue(E, 0); 3885 if (NumOps == 1) { 3886 N = NodeAllocator.Allocate<UnarySDNode>(); 3887 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3888 } else if (NumOps == 2) { 3889 N = NodeAllocator.Allocate<BinarySDNode>(); 3890 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3891 } else if (NumOps == 3) { 3892 N = NodeAllocator.Allocate<TernarySDNode>(); 3893 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3894 } else { 3895 N = NodeAllocator.Allocate<SDNode>(); 3896 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3897 } 3898 CSEMap.InsertNode(N, IP); 3899 } else { 3900 if (NumOps == 1) { 3901 N = NodeAllocator.Allocate<UnarySDNode>(); 3902 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3903 } else if (NumOps == 2) { 3904 N = NodeAllocator.Allocate<BinarySDNode>(); 3905 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3906 } else if (NumOps == 3) { 3907 N = NodeAllocator.Allocate<TernarySDNode>(); 3908 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3909 } else { 3910 N = NodeAllocator.Allocate<SDNode>(); 3911 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3912 } 3913 } 3914 AllNodes.push_back(N); 3915#ifndef NDEBUG 3916 VerifyNode(N); 3917#endif 3918 return SDValue(N, 0); 3919} 3920 3921SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) { 3922 return getNode(Opcode, DL, VTList, 0, 0); 3923} 3924 3925SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3926 SDValue N1) { 3927 SDValue Ops[] = { N1 }; 3928 return getNode(Opcode, DL, VTList, Ops, 1); 3929} 3930 3931SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3932 SDValue N1, SDValue N2) { 3933 SDValue Ops[] = { N1, N2 }; 3934 return getNode(Opcode, DL, VTList, Ops, 2); 3935} 3936 3937SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3938 SDValue N1, SDValue N2, SDValue N3) { 3939 SDValue Ops[] = { N1, N2, N3 }; 3940 return getNode(Opcode, DL, VTList, Ops, 3); 3941} 3942 3943SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3944 SDValue N1, SDValue N2, SDValue N3, 3945 SDValue N4) { 3946 SDValue Ops[] = { N1, N2, N3, N4 }; 3947 return getNode(Opcode, DL, VTList, Ops, 4); 3948} 3949 3950SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3951 SDValue N1, SDValue N2, SDValue N3, 3952 SDValue N4, SDValue N5) { 3953 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3954 return getNode(Opcode, DL, VTList, Ops, 5); 3955} 3956 3957SDVTList SelectionDAG::getVTList(MVT VT) { 3958 return makeVTList(SDNode::getValueTypeList(VT), 1); 3959} 3960 3961SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3962 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3963 E = VTList.rend(); I != E; ++I) 3964 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3965 return *I; 3966 3967 MVT *Array = Allocator.Allocate<MVT>(2); 3968 Array[0] = VT1; 3969 Array[1] = VT2; 3970 SDVTList Result = makeVTList(Array, 2); 3971 VTList.push_back(Result); 3972 return Result; 3973} 3974 3975SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3976 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3977 E = VTList.rend(); I != E; ++I) 3978 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3979 I->VTs[2] == VT3) 3980 return *I; 3981 3982 MVT *Array = Allocator.Allocate<MVT>(3); 3983 Array[0] = VT1; 3984 Array[1] = VT2; 3985 Array[2] = VT3; 3986 SDVTList Result = makeVTList(Array, 3); 3987 VTList.push_back(Result); 3988 return Result; 3989} 3990 3991SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { 3992 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3993 E = VTList.rend(); I != E; ++I) 3994 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3995 I->VTs[2] == VT3 && I->VTs[3] == VT4) 3996 return *I; 3997 3998 MVT *Array = Allocator.Allocate<MVT>(3); 3999 Array[0] = VT1; 4000 Array[1] = VT2; 4001 Array[2] = VT3; 4002 Array[3] = VT4; 4003 SDVTList Result = makeVTList(Array, 4); 4004 VTList.push_back(Result); 4005 return Result; 4006} 4007 4008SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 4009 switch (NumVTs) { 4010 case 0: assert(0 && "Cannot have nodes without results!"); 4011 case 1: return getVTList(VTs[0]); 4012 case 2: return getVTList(VTs[0], VTs[1]); 4013 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 4014 default: break; 4015 } 4016 4017 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4018 E = VTList.rend(); I != E; ++I) { 4019 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 4020 continue; 4021 4022 bool NoMatch = false; 4023 for (unsigned i = 2; i != NumVTs; ++i) 4024 if (VTs[i] != I->VTs[i]) { 4025 NoMatch = true; 4026 break; 4027 } 4028 if (!NoMatch) 4029 return *I; 4030 } 4031 4032 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 4033 std::copy(VTs, VTs+NumVTs, Array); 4034 SDVTList Result = makeVTList(Array, NumVTs); 4035 VTList.push_back(Result); 4036 return Result; 4037} 4038 4039 4040/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 4041/// specified operands. If the resultant node already exists in the DAG, 4042/// this does not modify the specified node, instead it returns the node that 4043/// already exists. If the resultant node does not exist in the DAG, the 4044/// input node is returned. As a degenerate case, if you specify the same 4045/// input operands as the node already has, the input node is returned. 4046SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 4047 SDNode *N = InN.getNode(); 4048 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 4049 4050 // Check to see if there is no change. 4051 if (Op == N->getOperand(0)) return InN; 4052 4053 // See if the modified node already exists. 4054 void *InsertPos = 0; 4055 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 4056 return SDValue(Existing, InN.getResNo()); 4057 4058 // Nope it doesn't. Remove the node from its current place in the maps. 4059 if (InsertPos) 4060 if (!RemoveNodeFromCSEMaps(N)) 4061 InsertPos = 0; 4062 4063 // Now we update the operands. 4064 N->OperandList[0].set(Op); 4065 4066 // If this gets put into a CSE map, add it. 4067 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4068 return InN; 4069} 4070 4071SDValue SelectionDAG:: 4072UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 4073 SDNode *N = InN.getNode(); 4074 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 4075 4076 // Check to see if there is no change. 4077 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 4078 return InN; // No operands changed, just return the input node. 4079 4080 // See if the modified node already exists. 4081 void *InsertPos = 0; 4082 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 4083 return SDValue(Existing, InN.getResNo()); 4084 4085 // Nope it doesn't. Remove the node from its current place in the maps. 4086 if (InsertPos) 4087 if (!RemoveNodeFromCSEMaps(N)) 4088 InsertPos = 0; 4089 4090 // Now we update the operands. 4091 if (N->OperandList[0] != Op1) 4092 N->OperandList[0].set(Op1); 4093 if (N->OperandList[1] != Op2) 4094 N->OperandList[1].set(Op2); 4095 4096 // If this gets put into a CSE map, add it. 4097 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4098 return InN; 4099} 4100 4101SDValue SelectionDAG:: 4102UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 4103 SDValue Ops[] = { Op1, Op2, Op3 }; 4104 return UpdateNodeOperands(N, Ops, 3); 4105} 4106 4107SDValue SelectionDAG:: 4108UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4109 SDValue Op3, SDValue Op4) { 4110 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 4111 return UpdateNodeOperands(N, Ops, 4); 4112} 4113 4114SDValue SelectionDAG:: 4115UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4116 SDValue Op3, SDValue Op4, SDValue Op5) { 4117 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 4118 return UpdateNodeOperands(N, Ops, 5); 4119} 4120 4121SDValue SelectionDAG:: 4122UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 4123 SDNode *N = InN.getNode(); 4124 assert(N->getNumOperands() == NumOps && 4125 "Update with wrong number of operands"); 4126 4127 // Check to see if there is no change. 4128 bool AnyChange = false; 4129 for (unsigned i = 0; i != NumOps; ++i) { 4130 if (Ops[i] != N->getOperand(i)) { 4131 AnyChange = true; 4132 break; 4133 } 4134 } 4135 4136 // No operands changed, just return the input node. 4137 if (!AnyChange) return InN; 4138 4139 // See if the modified node already exists. 4140 void *InsertPos = 0; 4141 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 4142 return SDValue(Existing, InN.getResNo()); 4143 4144 // Nope it doesn't. Remove the node from its current place in the maps. 4145 if (InsertPos) 4146 if (!RemoveNodeFromCSEMaps(N)) 4147 InsertPos = 0; 4148 4149 // Now we update the operands. 4150 for (unsigned i = 0; i != NumOps; ++i) 4151 if (N->OperandList[i] != Ops[i]) 4152 N->OperandList[i].set(Ops[i]); 4153 4154 // If this gets put into a CSE map, add it. 4155 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4156 return InN; 4157} 4158 4159/// DropOperands - Release the operands and set this node to have 4160/// zero operands. 4161void SDNode::DropOperands() { 4162 // Unlike the code in MorphNodeTo that does this, we don't need to 4163 // watch for dead nodes here. 4164 for (op_iterator I = op_begin(), E = op_end(); I != E; ) { 4165 SDUse &Use = *I++; 4166 Use.set(SDValue()); 4167 } 4168} 4169 4170/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4171/// machine opcode. 4172/// 4173SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4174 MVT VT) { 4175 SDVTList VTs = getVTList(VT); 4176 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4177} 4178 4179SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4180 MVT VT, SDValue Op1) { 4181 SDVTList VTs = getVTList(VT); 4182 SDValue Ops[] = { Op1 }; 4183 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4184} 4185 4186SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4187 MVT VT, SDValue Op1, 4188 SDValue Op2) { 4189 SDVTList VTs = getVTList(VT); 4190 SDValue Ops[] = { Op1, Op2 }; 4191 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4192} 4193 4194SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4195 MVT VT, SDValue Op1, 4196 SDValue Op2, SDValue Op3) { 4197 SDVTList VTs = getVTList(VT); 4198 SDValue Ops[] = { Op1, Op2, Op3 }; 4199 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4200} 4201 4202SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4203 MVT VT, const SDValue *Ops, 4204 unsigned NumOps) { 4205 SDVTList VTs = getVTList(VT); 4206 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4207} 4208 4209SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4210 MVT VT1, MVT VT2, const SDValue *Ops, 4211 unsigned NumOps) { 4212 SDVTList VTs = getVTList(VT1, VT2); 4213 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4214} 4215 4216SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4217 MVT VT1, MVT VT2) { 4218 SDVTList VTs = getVTList(VT1, VT2); 4219 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4220} 4221 4222SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4223 MVT VT1, MVT VT2, MVT VT3, 4224 const SDValue *Ops, unsigned NumOps) { 4225 SDVTList VTs = getVTList(VT1, VT2, VT3); 4226 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4227} 4228 4229SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4230 MVT VT1, MVT VT2, MVT VT3, MVT VT4, 4231 const SDValue *Ops, unsigned NumOps) { 4232 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4233 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4234} 4235 4236SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4237 MVT VT1, MVT VT2, 4238 SDValue Op1) { 4239 SDVTList VTs = getVTList(VT1, VT2); 4240 SDValue Ops[] = { Op1 }; 4241 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4242} 4243 4244SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4245 MVT VT1, MVT VT2, 4246 SDValue Op1, SDValue Op2) { 4247 SDVTList VTs = getVTList(VT1, VT2); 4248 SDValue Ops[] = { Op1, Op2 }; 4249 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4250} 4251 4252SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4253 MVT VT1, MVT VT2, 4254 SDValue Op1, SDValue Op2, 4255 SDValue Op3) { 4256 SDVTList VTs = getVTList(VT1, VT2); 4257 SDValue Ops[] = { Op1, Op2, Op3 }; 4258 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4259} 4260 4261SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4262 MVT VT1, MVT VT2, MVT VT3, 4263 SDValue Op1, SDValue Op2, 4264 SDValue Op3) { 4265 SDVTList VTs = getVTList(VT1, VT2, VT3); 4266 SDValue Ops[] = { Op1, Op2, Op3 }; 4267 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4268} 4269 4270SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4271 SDVTList VTs, const SDValue *Ops, 4272 unsigned NumOps) { 4273 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4274} 4275 4276SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4277 MVT VT) { 4278 SDVTList VTs = getVTList(VT); 4279 return MorphNodeTo(N, Opc, VTs, 0, 0); 4280} 4281 4282SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4283 MVT VT, SDValue Op1) { 4284 SDVTList VTs = getVTList(VT); 4285 SDValue Ops[] = { Op1 }; 4286 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4287} 4288 4289SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4290 MVT VT, SDValue Op1, 4291 SDValue Op2) { 4292 SDVTList VTs = getVTList(VT); 4293 SDValue Ops[] = { Op1, Op2 }; 4294 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4295} 4296 4297SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4298 MVT VT, SDValue Op1, 4299 SDValue Op2, SDValue Op3) { 4300 SDVTList VTs = getVTList(VT); 4301 SDValue Ops[] = { Op1, Op2, Op3 }; 4302 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4303} 4304 4305SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4306 MVT VT, const SDValue *Ops, 4307 unsigned NumOps) { 4308 SDVTList VTs = getVTList(VT); 4309 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4310} 4311 4312SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4313 MVT VT1, MVT VT2, const SDValue *Ops, 4314 unsigned NumOps) { 4315 SDVTList VTs = getVTList(VT1, VT2); 4316 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4317} 4318 4319SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4320 MVT VT1, MVT VT2) { 4321 SDVTList VTs = getVTList(VT1, VT2); 4322 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4323} 4324 4325SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4326 MVT VT1, MVT VT2, MVT VT3, 4327 const SDValue *Ops, unsigned NumOps) { 4328 SDVTList VTs = getVTList(VT1, VT2, VT3); 4329 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4330} 4331 4332SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4333 MVT VT1, MVT VT2, 4334 SDValue Op1) { 4335 SDVTList VTs = getVTList(VT1, VT2); 4336 SDValue Ops[] = { Op1 }; 4337 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4338} 4339 4340SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4341 MVT VT1, MVT VT2, 4342 SDValue Op1, SDValue Op2) { 4343 SDVTList VTs = getVTList(VT1, VT2); 4344 SDValue Ops[] = { Op1, Op2 }; 4345 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4346} 4347 4348SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4349 MVT VT1, MVT VT2, 4350 SDValue Op1, SDValue Op2, 4351 SDValue Op3) { 4352 SDVTList VTs = getVTList(VT1, VT2); 4353 SDValue Ops[] = { Op1, Op2, Op3 }; 4354 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4355} 4356 4357/// MorphNodeTo - These *mutate* the specified node to have the specified 4358/// return type, opcode, and operands. 4359/// 4360/// Note that MorphNodeTo returns the resultant node. If there is already a 4361/// node of the specified opcode and operands, it returns that node instead of 4362/// the current one. Note that the DebugLoc need not be the same. 4363/// 4364/// Using MorphNodeTo is faster than creating a new node and swapping it in 4365/// with ReplaceAllUsesWith both because it often avoids allocating a new 4366/// node, and because it doesn't require CSE recalculation for any of 4367/// the node's users. 4368/// 4369SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4370 SDVTList VTs, const SDValue *Ops, 4371 unsigned NumOps) { 4372 // If an identical node already exists, use it. 4373 void *IP = 0; 4374 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4375 FoldingSetNodeID ID; 4376 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4377 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4378 return ON; 4379 } 4380 4381 if (!RemoveNodeFromCSEMaps(N)) 4382 IP = 0; 4383 4384 // Start the morphing. 4385 N->NodeType = Opc; 4386 N->ValueList = VTs.VTs; 4387 N->NumValues = VTs.NumVTs; 4388 4389 // Clear the operands list, updating used nodes to remove this from their 4390 // use list. Keep track of any operands that become dead as a result. 4391 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4392 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 4393 SDUse &Use = *I++; 4394 SDNode *Used = Use.getNode(); 4395 Use.set(SDValue()); 4396 if (Used->use_empty()) 4397 DeadNodeSet.insert(Used); 4398 } 4399 4400 // If NumOps is larger than the # of operands we currently have, reallocate 4401 // the operand list. 4402 if (NumOps > N->NumOperands) { 4403 if (N->OperandsNeedDelete) 4404 delete[] N->OperandList; 4405 4406 if (N->isMachineOpcode()) { 4407 // We're creating a final node that will live unmorphed for the 4408 // remainder of the current SelectionDAG iteration, so we can allocate 4409 // the operands directly out of a pool with no recycling metadata. 4410 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4411 N->OperandsNeedDelete = false; 4412 } else { 4413 N->OperandList = new SDUse[NumOps]; 4414 N->OperandsNeedDelete = true; 4415 } 4416 } 4417 4418 // Assign the new operands. 4419 N->NumOperands = NumOps; 4420 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4421 N->OperandList[i].setUser(N); 4422 N->OperandList[i].setInitial(Ops[i]); 4423 } 4424 4425 // Delete any nodes that are still dead after adding the uses for the 4426 // new operands. 4427 SmallVector<SDNode *, 16> DeadNodes; 4428 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4429 E = DeadNodeSet.end(); I != E; ++I) 4430 if ((*I)->use_empty()) 4431 DeadNodes.push_back(*I); 4432 RemoveDeadNodes(DeadNodes); 4433 4434 if (IP) 4435 CSEMap.InsertNode(N, IP); // Memoize the new node. 4436 return N; 4437} 4438 4439 4440/// getTargetNode - These are used for target selectors to create a new node 4441/// with specified return type(s), target opcode, and operands. 4442/// 4443/// Note that getTargetNode returns the resultant node. If there is already a 4444/// node of the specified opcode and operands, it returns that node instead of 4445/// the current one. 4446SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) { 4447 return getNode(~Opcode, dl, VT).getNode(); 4448} 4449 4450SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4451 SDValue Op1) { 4452 return getNode(~Opcode, dl, VT, Op1).getNode(); 4453} 4454 4455SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4456 SDValue Op1, SDValue Op2) { 4457 return getNode(~Opcode, dl, VT, Op1, Op2).getNode(); 4458} 4459 4460SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4461 SDValue Op1, SDValue Op2, 4462 SDValue Op3) { 4463 return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode(); 4464} 4465 4466SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4467 const SDValue *Ops, unsigned NumOps) { 4468 return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); 4469} 4470 4471SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4472 MVT VT1, MVT VT2) { 4473 SDVTList VTs = getVTList(VT1, VT2); 4474 SDValue Op; 4475 return getNode(~Opcode, dl, VTs, &Op, 0).getNode(); 4476} 4477 4478SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4479 MVT VT2, SDValue Op1) { 4480 SDVTList VTs = getVTList(VT1, VT2); 4481 return getNode(~Opcode, dl, VTs, &Op1, 1).getNode(); 4482} 4483 4484SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4485 MVT VT2, SDValue Op1, 4486 SDValue Op2) { 4487 SDVTList VTs = getVTList(VT1, VT2); 4488 SDValue Ops[] = { Op1, Op2 }; 4489 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4490} 4491 4492SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4493 MVT VT2, SDValue Op1, 4494 SDValue Op2, SDValue Op3) { 4495 SDVTList VTs = getVTList(VT1, VT2); 4496 SDValue Ops[] = { Op1, Op2, Op3 }; 4497 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4498} 4499 4500SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4501 MVT VT1, MVT VT2, 4502 const SDValue *Ops, unsigned NumOps) { 4503 SDVTList VTs = getVTList(VT1, VT2); 4504 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4505} 4506 4507SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4508 MVT VT1, MVT VT2, MVT VT3, 4509 SDValue Op1, SDValue Op2) { 4510 SDVTList VTs = getVTList(VT1, VT2, VT3); 4511 SDValue Ops[] = { Op1, Op2 }; 4512 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4513} 4514 4515SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4516 MVT VT1, MVT VT2, MVT VT3, 4517 SDValue Op1, SDValue Op2, 4518 SDValue Op3) { 4519 SDVTList VTs = getVTList(VT1, VT2, VT3); 4520 SDValue Ops[] = { Op1, Op2, Op3 }; 4521 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4522} 4523 4524SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4525 MVT VT1, MVT VT2, MVT VT3, 4526 const SDValue *Ops, unsigned NumOps) { 4527 SDVTList VTs = getVTList(VT1, VT2, VT3); 4528 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4529} 4530 4531SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4532 MVT VT2, MVT VT3, MVT VT4, 4533 const SDValue *Ops, unsigned NumOps) { 4534 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4535 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4536} 4537 4538SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4539 const std::vector<MVT> &ResultTys, 4540 const SDValue *Ops, unsigned NumOps) { 4541 return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode(); 4542} 4543 4544/// getNodeIfExists - Get the specified node if it's already available, or 4545/// else return NULL. 4546SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4547 const SDValue *Ops, unsigned NumOps) { 4548 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4549 FoldingSetNodeID ID; 4550 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4551 void *IP = 0; 4552 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4553 return E; 4554 } 4555 return NULL; 4556} 4557 4558/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4559/// This can cause recursive merging of nodes in the DAG. 4560/// 4561/// This version assumes From has a single result value. 4562/// 4563void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4564 DAGUpdateListener *UpdateListener) { 4565 SDNode *From = FromN.getNode(); 4566 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4567 "Cannot replace with this method!"); 4568 assert(From != To.getNode() && "Cannot replace uses of with self"); 4569 4570 // Iterate over all the existing uses of From. New uses will be added 4571 // to the beginning of the use list, which we avoid visiting. 4572 // This specifically avoids visiting uses of From that arise while the 4573 // replacement is happening, because any such uses would be the result 4574 // of CSE: If an existing node looks like From after one of its operands 4575 // is replaced by To, we don't want to replace of all its users with To 4576 // too. See PR3018 for more info. 4577 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4578 while (UI != UE) { 4579 SDNode *User = *UI; 4580 4581 // This node is about to morph, remove its old self from the CSE maps. 4582 RemoveNodeFromCSEMaps(User); 4583 4584 // A user can appear in a use list multiple times, and when this 4585 // happens the uses are usually next to each other in the list. 4586 // To help reduce the number of CSE recomputations, process all 4587 // the uses of this user that we can find this way. 4588 do { 4589 SDUse &Use = UI.getUse(); 4590 ++UI; 4591 Use.set(To); 4592 } while (UI != UE && *UI == User); 4593 4594 // Now that we have modified User, add it back to the CSE maps. If it 4595 // already exists there, recursively merge the results together. 4596 AddModifiedNodeToCSEMaps(User, UpdateListener); 4597 } 4598} 4599 4600/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4601/// This can cause recursive merging of nodes in the DAG. 4602/// 4603/// This version assumes that for each value of From, there is a 4604/// corresponding value in To in the same position with the same type. 4605/// 4606void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4607 DAGUpdateListener *UpdateListener) { 4608#ifndef NDEBUG 4609 for (unsigned i = 0, e = From->getNumValues(); i != e; ++i) 4610 assert((!From->hasAnyUseOfValue(i) || 4611 From->getValueType(i) == To->getValueType(i)) && 4612 "Cannot use this version of ReplaceAllUsesWith!"); 4613#endif 4614 4615 // Handle the trivial case. 4616 if (From == To) 4617 return; 4618 4619 // Iterate over just the existing users of From. See the comments in 4620 // the ReplaceAllUsesWith above. 4621 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4622 while (UI != UE) { 4623 SDNode *User = *UI; 4624 4625 // This node is about to morph, remove its old self from the CSE maps. 4626 RemoveNodeFromCSEMaps(User); 4627 4628 // A user can appear in a use list multiple times, and when this 4629 // happens the uses are usually next to each other in the list. 4630 // To help reduce the number of CSE recomputations, process all 4631 // the uses of this user that we can find this way. 4632 do { 4633 SDUse &Use = UI.getUse(); 4634 ++UI; 4635 Use.setNode(To); 4636 } while (UI != UE && *UI == User); 4637 4638 // Now that we have modified User, add it back to the CSE maps. If it 4639 // already exists there, recursively merge the results together. 4640 AddModifiedNodeToCSEMaps(User, UpdateListener); 4641 } 4642} 4643 4644/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4645/// This can cause recursive merging of nodes in the DAG. 4646/// 4647/// This version can replace From with any result values. To must match the 4648/// number and types of values returned by From. 4649void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4650 const SDValue *To, 4651 DAGUpdateListener *UpdateListener) { 4652 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4653 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4654 4655 // Iterate over just the existing users of From. See the comments in 4656 // the ReplaceAllUsesWith above. 4657 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4658 while (UI != UE) { 4659 SDNode *User = *UI; 4660 4661 // This node is about to morph, remove its old self from the CSE maps. 4662 RemoveNodeFromCSEMaps(User); 4663 4664 // A user can appear in a use list multiple times, and when this 4665 // happens the uses are usually next to each other in the list. 4666 // To help reduce the number of CSE recomputations, process all 4667 // the uses of this user that we can find this way. 4668 do { 4669 SDUse &Use = UI.getUse(); 4670 const SDValue &ToOp = To[Use.getResNo()]; 4671 ++UI; 4672 Use.set(ToOp); 4673 } while (UI != UE && *UI == User); 4674 4675 // Now that we have modified User, add it back to the CSE maps. If it 4676 // already exists there, recursively merge the results together. 4677 AddModifiedNodeToCSEMaps(User, UpdateListener); 4678 } 4679} 4680 4681/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4682/// uses of other values produced by From.getNode() alone. The Deleted 4683/// vector is handled the same way as for ReplaceAllUsesWith. 4684void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4685 DAGUpdateListener *UpdateListener){ 4686 // Handle the really simple, really trivial case efficiently. 4687 if (From == To) return; 4688 4689 // Handle the simple, trivial, case efficiently. 4690 if (From.getNode()->getNumValues() == 1) { 4691 ReplaceAllUsesWith(From, To, UpdateListener); 4692 return; 4693 } 4694 4695 // Iterate over just the existing users of From. See the comments in 4696 // the ReplaceAllUsesWith above. 4697 SDNode::use_iterator UI = From.getNode()->use_begin(), 4698 UE = From.getNode()->use_end(); 4699 while (UI != UE) { 4700 SDNode *User = *UI; 4701 bool UserRemovedFromCSEMaps = false; 4702 4703 // A user can appear in a use list multiple times, and when this 4704 // happens the uses are usually next to each other in the list. 4705 // To help reduce the number of CSE recomputations, process all 4706 // the uses of this user that we can find this way. 4707 do { 4708 SDUse &Use = UI.getUse(); 4709 4710 // Skip uses of different values from the same node. 4711 if (Use.getResNo() != From.getResNo()) { 4712 ++UI; 4713 continue; 4714 } 4715 4716 // If this node hasn't been modified yet, it's still in the CSE maps, 4717 // so remove its old self from the CSE maps. 4718 if (!UserRemovedFromCSEMaps) { 4719 RemoveNodeFromCSEMaps(User); 4720 UserRemovedFromCSEMaps = true; 4721 } 4722 4723 ++UI; 4724 Use.set(To); 4725 } while (UI != UE && *UI == User); 4726 4727 // We are iterating over all uses of the From node, so if a use 4728 // doesn't use the specific value, no changes are made. 4729 if (!UserRemovedFromCSEMaps) 4730 continue; 4731 4732 // Now that we have modified User, add it back to the CSE maps. If it 4733 // already exists there, recursively merge the results together. 4734 AddModifiedNodeToCSEMaps(User, UpdateListener); 4735 } 4736} 4737 4738namespace { 4739 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith 4740 /// to record information about a use. 4741 struct UseMemo { 4742 SDNode *User; 4743 unsigned Index; 4744 SDUse *Use; 4745 }; 4746 4747 /// operator< - Sort Memos by User. 4748 bool operator<(const UseMemo &L, const UseMemo &R) { 4749 return (intptr_t)L.User < (intptr_t)R.User; 4750 } 4751} 4752 4753/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4754/// uses of other values produced by From.getNode() alone. The same value 4755/// may appear in both the From and To list. The Deleted vector is 4756/// handled the same way as for ReplaceAllUsesWith. 4757void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4758 const SDValue *To, 4759 unsigned Num, 4760 DAGUpdateListener *UpdateListener){ 4761 // Handle the simple, trivial case efficiently. 4762 if (Num == 1) 4763 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4764 4765 // Read up all the uses and make records of them. This helps 4766 // processing new uses that are introduced during the 4767 // replacement process. 4768 SmallVector<UseMemo, 4> Uses; 4769 for (unsigned i = 0; i != Num; ++i) { 4770 unsigned FromResNo = From[i].getResNo(); 4771 SDNode *FromNode = From[i].getNode(); 4772 for (SDNode::use_iterator UI = FromNode->use_begin(), 4773 E = FromNode->use_end(); UI != E; ++UI) { 4774 SDUse &Use = UI.getUse(); 4775 if (Use.getResNo() == FromResNo) { 4776 UseMemo Memo = { *UI, i, &Use }; 4777 Uses.push_back(Memo); 4778 } 4779 } 4780 } 4781 4782 // Sort the uses, so that all the uses from a given User are together. 4783 std::sort(Uses.begin(), Uses.end()); 4784 4785 for (unsigned UseIndex = 0, UseIndexEnd = Uses.size(); 4786 UseIndex != UseIndexEnd; ) { 4787 // We know that this user uses some value of From. If it is the right 4788 // value, update it. 4789 SDNode *User = Uses[UseIndex].User; 4790 4791 // This node is about to morph, remove its old self from the CSE maps. 4792 RemoveNodeFromCSEMaps(User); 4793 4794 // The Uses array is sorted, so all the uses for a given User 4795 // are next to each other in the list. 4796 // To help reduce the number of CSE recomputations, process all 4797 // the uses of this user that we can find this way. 4798 do { 4799 unsigned i = Uses[UseIndex].Index; 4800 SDUse &Use = *Uses[UseIndex].Use; 4801 ++UseIndex; 4802 4803 Use.set(To[i]); 4804 } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User); 4805 4806 // Now that we have modified User, add it back to the CSE maps. If it 4807 // already exists there, recursively merge the results together. 4808 AddModifiedNodeToCSEMaps(User, UpdateListener); 4809 } 4810} 4811 4812/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4813/// based on their topological order. It returns the maximum id and a vector 4814/// of the SDNodes* in assigned order by reference. 4815unsigned SelectionDAG::AssignTopologicalOrder() { 4816 4817 unsigned DAGSize = 0; 4818 4819 // SortedPos tracks the progress of the algorithm. Nodes before it are 4820 // sorted, nodes after it are unsorted. When the algorithm completes 4821 // it is at the end of the list. 4822 allnodes_iterator SortedPos = allnodes_begin(); 4823 4824 // Visit all the nodes. Move nodes with no operands to the front of 4825 // the list immediately. Annotate nodes that do have operands with their 4826 // operand count. Before we do this, the Node Id fields of the nodes 4827 // may contain arbitrary values. After, the Node Id fields for nodes 4828 // before SortedPos will contain the topological sort index, and the 4829 // Node Id fields for nodes At SortedPos and after will contain the 4830 // count of outstanding operands. 4831 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4832 SDNode *N = I++; 4833 unsigned Degree = N->getNumOperands(); 4834 if (Degree == 0) { 4835 // A node with no uses, add it to the result array immediately. 4836 N->setNodeId(DAGSize++); 4837 allnodes_iterator Q = N; 4838 if (Q != SortedPos) 4839 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4840 ++SortedPos; 4841 } else { 4842 // Temporarily use the Node Id as scratch space for the degree count. 4843 N->setNodeId(Degree); 4844 } 4845 } 4846 4847 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4848 // such that by the time the end is reached all nodes will be sorted. 4849 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4850 SDNode *N = I; 4851 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4852 UI != UE; ++UI) { 4853 SDNode *P = *UI; 4854 unsigned Degree = P->getNodeId(); 4855 --Degree; 4856 if (Degree == 0) { 4857 // All of P's operands are sorted, so P may sorted now. 4858 P->setNodeId(DAGSize++); 4859 if (P != SortedPos) 4860 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4861 ++SortedPos; 4862 } else { 4863 // Update P's outstanding operand count. 4864 P->setNodeId(Degree); 4865 } 4866 } 4867 } 4868 4869 assert(SortedPos == AllNodes.end() && 4870 "Topological sort incomplete!"); 4871 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4872 "First node in topological sort is not the entry token!"); 4873 assert(AllNodes.front().getNodeId() == 0 && 4874 "First node in topological sort has non-zero id!"); 4875 assert(AllNodes.front().getNumOperands() == 0 && 4876 "First node in topological sort has operands!"); 4877 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4878 "Last node in topologic sort has unexpected id!"); 4879 assert(AllNodes.back().use_empty() && 4880 "Last node in topologic sort has users!"); 4881 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 4882 return DAGSize; 4883} 4884 4885 4886 4887//===----------------------------------------------------------------------===// 4888// SDNode Class 4889//===----------------------------------------------------------------------===// 4890 4891HandleSDNode::~HandleSDNode() { 4892 DropOperands(); 4893} 4894 4895GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4896 MVT VT, int64_t o) 4897 : SDNode(isa<GlobalVariable>(GA) && 4898 cast<GlobalVariable>(GA)->isThreadLocal() ? 4899 // Thread Local 4900 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4901 // Non Thread Local 4902 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4903 DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o) { 4904 TheGlobal = const_cast<GlobalValue*>(GA); 4905} 4906 4907MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt, 4908 const Value *srcValue, int SVO, 4909 unsigned alignment, bool vol) 4910 : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4911 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4912 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4913 assert(getAlignment() == alignment && "Alignment representation error!"); 4914 assert(isVolatile() == vol && "Volatile representation error!"); 4915} 4916 4917MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, 4918 const SDValue *Ops, 4919 unsigned NumOps, MVT memvt, const Value *srcValue, 4920 int SVO, unsigned alignment, bool vol) 4921 : SDNode(Opc, dl, VTs, Ops, NumOps), 4922 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4923 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4924 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4925 assert(getAlignment() == alignment && "Alignment representation error!"); 4926 assert(isVolatile() == vol && "Volatile representation error!"); 4927} 4928 4929/// getMemOperand - Return a MachineMemOperand object describing the memory 4930/// reference performed by this memory reference. 4931MachineMemOperand MemSDNode::getMemOperand() const { 4932 int Flags = 0; 4933 if (isa<LoadSDNode>(this)) 4934 Flags = MachineMemOperand::MOLoad; 4935 else if (isa<StoreSDNode>(this)) 4936 Flags = MachineMemOperand::MOStore; 4937 else if (isa<AtomicSDNode>(this)) { 4938 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4939 } 4940 else { 4941 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4942 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4943 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4944 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4945 } 4946 4947 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4948 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4949 4950 // Check if the memory reference references a frame index 4951 const FrameIndexSDNode *FI = 4952 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4953 if (!getSrcValue() && FI) 4954 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4955 Flags, 0, Size, getAlignment()); 4956 else 4957 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4958 Size, getAlignment()); 4959} 4960 4961/// Profile - Gather unique data for the node. 4962/// 4963void SDNode::Profile(FoldingSetNodeID &ID) const { 4964 AddNodeIDNode(ID, this); 4965} 4966 4967/// getValueTypeList - Return a pointer to the specified value type. 4968/// 4969const MVT *SDNode::getValueTypeList(MVT VT) { 4970 if (VT.isExtended()) { 4971 static std::set<MVT, MVT::compareRawBits> EVTs; 4972 return &(*EVTs.insert(VT).first); 4973 } else { 4974 static MVT VTs[MVT::LAST_VALUETYPE]; 4975 VTs[VT.getSimpleVT()] = VT; 4976 return &VTs[VT.getSimpleVT()]; 4977 } 4978} 4979 4980/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4981/// indicated value. This method ignores uses of other values defined by this 4982/// operation. 4983bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4984 assert(Value < getNumValues() && "Bad value!"); 4985 4986 // TODO: Only iterate over uses of a given value of the node 4987 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4988 if (UI.getUse().getResNo() == Value) { 4989 if (NUses == 0) 4990 return false; 4991 --NUses; 4992 } 4993 } 4994 4995 // Found exactly the right number of uses? 4996 return NUses == 0; 4997} 4998 4999 5000/// hasAnyUseOfValue - Return true if there are any use of the indicated 5001/// value. This method ignores uses of other values defined by this operation. 5002bool SDNode::hasAnyUseOfValue(unsigned Value) const { 5003 assert(Value < getNumValues() && "Bad value!"); 5004 5005 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 5006 if (UI.getUse().getResNo() == Value) 5007 return true; 5008 5009 return false; 5010} 5011 5012 5013/// isOnlyUserOf - Return true if this node is the only use of N. 5014/// 5015bool SDNode::isOnlyUserOf(SDNode *N) const { 5016 bool Seen = false; 5017 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 5018 SDNode *User = *I; 5019 if (User == this) 5020 Seen = true; 5021 else 5022 return false; 5023 } 5024 5025 return Seen; 5026} 5027 5028/// isOperand - Return true if this node is an operand of N. 5029/// 5030bool SDValue::isOperandOf(SDNode *N) const { 5031 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5032 if (*this == N->getOperand(i)) 5033 return true; 5034 return false; 5035} 5036 5037bool SDNode::isOperandOf(SDNode *N) const { 5038 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 5039 if (this == N->OperandList[i].getNode()) 5040 return true; 5041 return false; 5042} 5043 5044/// reachesChainWithoutSideEffects - Return true if this operand (which must 5045/// be a chain) reaches the specified operand without crossing any 5046/// side-effecting instructions. In practice, this looks through token 5047/// factors and non-volatile loads. In order to remain efficient, this only 5048/// looks a couple of nodes in, it does not do an exhaustive search. 5049bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 5050 unsigned Depth) const { 5051 if (*this == Dest) return true; 5052 5053 // Don't search too deeply, we just want to be able to see through 5054 // TokenFactor's etc. 5055 if (Depth == 0) return false; 5056 5057 // If this is a token factor, all inputs to the TF happen in parallel. If any 5058 // of the operands of the TF reach dest, then we can do the xform. 5059 if (getOpcode() == ISD::TokenFactor) { 5060 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 5061 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 5062 return true; 5063 return false; 5064 } 5065 5066 // Loads don't have side effects, look through them. 5067 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 5068 if (!Ld->isVolatile()) 5069 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 5070 } 5071 return false; 5072} 5073 5074 5075static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 5076 SmallPtrSet<SDNode *, 32> &Visited) { 5077 if (found || !Visited.insert(N)) 5078 return; 5079 5080 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 5081 SDNode *Op = N->getOperand(i).getNode(); 5082 if (Op == P) { 5083 found = true; 5084 return; 5085 } 5086 findPredecessor(Op, P, found, Visited); 5087 } 5088} 5089 5090/// isPredecessorOf - Return true if this node is a predecessor of N. This node 5091/// is either an operand of N or it can be reached by recursively traversing 5092/// up the operands. 5093/// NOTE: this is an expensive method. Use it carefully. 5094bool SDNode::isPredecessorOf(SDNode *N) const { 5095 SmallPtrSet<SDNode *, 32> Visited; 5096 bool found = false; 5097 findPredecessor(N, this, found, Visited); 5098 return found; 5099} 5100 5101uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 5102 assert(Num < NumOperands && "Invalid child # of SDNode!"); 5103 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 5104} 5105 5106std::string SDNode::getOperationName(const SelectionDAG *G) const { 5107 switch (getOpcode()) { 5108 default: 5109 if (getOpcode() < ISD::BUILTIN_OP_END) 5110 return "<<Unknown DAG Node>>"; 5111 if (isMachineOpcode()) { 5112 if (G) 5113 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 5114 if (getMachineOpcode() < TII->getNumOpcodes()) 5115 return TII->get(getMachineOpcode()).getName(); 5116 return "<<Unknown Machine Node>>"; 5117 } 5118 if (G) { 5119 const TargetLowering &TLI = G->getTargetLoweringInfo(); 5120 const char *Name = TLI.getTargetNodeName(getOpcode()); 5121 if (Name) return Name; 5122 return "<<Unknown Target Node>>"; 5123 } 5124 return "<<Unknown Node>>"; 5125 5126#ifndef NDEBUG 5127 case ISD::DELETED_NODE: 5128 return "<<Deleted Node!>>"; 5129#endif 5130 case ISD::PREFETCH: return "Prefetch"; 5131 case ISD::MEMBARRIER: return "MemBarrier"; 5132 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 5133 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 5134 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 5135 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 5136 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; 5137 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; 5138 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor"; 5139 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand"; 5140 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin"; 5141 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; 5142 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; 5143 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; 5144 case ISD::PCMARKER: return "PCMarker"; 5145 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5146 case ISD::SRCVALUE: return "SrcValue"; 5147 case ISD::MEMOPERAND: return "MemOperand"; 5148 case ISD::EntryToken: return "EntryToken"; 5149 case ISD::TokenFactor: return "TokenFactor"; 5150 case ISD::AssertSext: return "AssertSext"; 5151 case ISD::AssertZext: return "AssertZext"; 5152 5153 case ISD::BasicBlock: return "BasicBlock"; 5154 case ISD::ARG_FLAGS: return "ArgFlags"; 5155 case ISD::VALUETYPE: return "ValueType"; 5156 case ISD::Register: return "Register"; 5157 5158 case ISD::Constant: return "Constant"; 5159 case ISD::ConstantFP: return "ConstantFP"; 5160 case ISD::GlobalAddress: return "GlobalAddress"; 5161 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5162 case ISD::FrameIndex: return "FrameIndex"; 5163 case ISD::JumpTable: return "JumpTable"; 5164 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5165 case ISD::RETURNADDR: return "RETURNADDR"; 5166 case ISD::FRAMEADDR: return "FRAMEADDR"; 5167 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5168 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5169 case ISD::EHSELECTION: return "EHSELECTION"; 5170 case ISD::EH_RETURN: return "EH_RETURN"; 5171 case ISD::ConstantPool: return "ConstantPool"; 5172 case ISD::ExternalSymbol: return "ExternalSymbol"; 5173 case ISD::INTRINSIC_WO_CHAIN: { 5174 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5175 return Intrinsic::getName((Intrinsic::ID)IID); 5176 } 5177 case ISD::INTRINSIC_VOID: 5178 case ISD::INTRINSIC_W_CHAIN: { 5179 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5180 return Intrinsic::getName((Intrinsic::ID)IID); 5181 } 5182 5183 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5184 case ISD::TargetConstant: return "TargetConstant"; 5185 case ISD::TargetConstantFP:return "TargetConstantFP"; 5186 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5187 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5188 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5189 case ISD::TargetJumpTable: return "TargetJumpTable"; 5190 case ISD::TargetConstantPool: return "TargetConstantPool"; 5191 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5192 5193 case ISD::CopyToReg: return "CopyToReg"; 5194 case ISD::CopyFromReg: return "CopyFromReg"; 5195 case ISD::UNDEF: return "undef"; 5196 case ISD::MERGE_VALUES: return "merge_values"; 5197 case ISD::INLINEASM: return "inlineasm"; 5198 case ISD::DBG_LABEL: return "dbg_label"; 5199 case ISD::EH_LABEL: return "eh_label"; 5200 case ISD::DECLARE: return "declare"; 5201 case ISD::HANDLENODE: return "handlenode"; 5202 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5203 case ISD::CALL: return "call"; 5204 5205 // Unary operators 5206 case ISD::FABS: return "fabs"; 5207 case ISD::FNEG: return "fneg"; 5208 case ISD::FSQRT: return "fsqrt"; 5209 case ISD::FSIN: return "fsin"; 5210 case ISD::FCOS: return "fcos"; 5211 case ISD::FPOWI: return "fpowi"; 5212 case ISD::FPOW: return "fpow"; 5213 case ISD::FTRUNC: return "ftrunc"; 5214 case ISD::FFLOOR: return "ffloor"; 5215 case ISD::FCEIL: return "fceil"; 5216 case ISD::FRINT: return "frint"; 5217 case ISD::FNEARBYINT: return "fnearbyint"; 5218 5219 // Binary operators 5220 case ISD::ADD: return "add"; 5221 case ISD::SUB: return "sub"; 5222 case ISD::MUL: return "mul"; 5223 case ISD::MULHU: return "mulhu"; 5224 case ISD::MULHS: return "mulhs"; 5225 case ISD::SDIV: return "sdiv"; 5226 case ISD::UDIV: return "udiv"; 5227 case ISD::SREM: return "srem"; 5228 case ISD::UREM: return "urem"; 5229 case ISD::SMUL_LOHI: return "smul_lohi"; 5230 case ISD::UMUL_LOHI: return "umul_lohi"; 5231 case ISD::SDIVREM: return "sdivrem"; 5232 case ISD::UDIVREM: return "udivrem"; 5233 case ISD::AND: return "and"; 5234 case ISD::OR: return "or"; 5235 case ISD::XOR: return "xor"; 5236 case ISD::SHL: return "shl"; 5237 case ISD::SRA: return "sra"; 5238 case ISD::SRL: return "srl"; 5239 case ISD::ROTL: return "rotl"; 5240 case ISD::ROTR: return "rotr"; 5241 case ISD::FADD: return "fadd"; 5242 case ISD::FSUB: return "fsub"; 5243 case ISD::FMUL: return "fmul"; 5244 case ISD::FDIV: return "fdiv"; 5245 case ISD::FREM: return "frem"; 5246 case ISD::FCOPYSIGN: return "fcopysign"; 5247 case ISD::FGETSIGN: return "fgetsign"; 5248 5249 case ISD::SETCC: return "setcc"; 5250 case ISD::VSETCC: return "vsetcc"; 5251 case ISD::SELECT: return "select"; 5252 case ISD::SELECT_CC: return "select_cc"; 5253 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5254 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5255 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5256 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5257 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5258 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5259 case ISD::CARRY_FALSE: return "carry_false"; 5260 case ISD::ADDC: return "addc"; 5261 case ISD::ADDE: return "adde"; 5262 case ISD::SADDO: return "saddo"; 5263 case ISD::UADDO: return "uaddo"; 5264 case ISD::SSUBO: return "ssubo"; 5265 case ISD::USUBO: return "usubo"; 5266 case ISD::SMULO: return "smulo"; 5267 case ISD::UMULO: return "umulo"; 5268 case ISD::SUBC: return "subc"; 5269 case ISD::SUBE: return "sube"; 5270 case ISD::SHL_PARTS: return "shl_parts"; 5271 case ISD::SRA_PARTS: return "sra_parts"; 5272 case ISD::SRL_PARTS: return "srl_parts"; 5273 5274 // Conversion operators. 5275 case ISD::SIGN_EXTEND: return "sign_extend"; 5276 case ISD::ZERO_EXTEND: return "zero_extend"; 5277 case ISD::ANY_EXTEND: return "any_extend"; 5278 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5279 case ISD::TRUNCATE: return "truncate"; 5280 case ISD::FP_ROUND: return "fp_round"; 5281 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5282 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5283 case ISD::FP_EXTEND: return "fp_extend"; 5284 5285 case ISD::SINT_TO_FP: return "sint_to_fp"; 5286 case ISD::UINT_TO_FP: return "uint_to_fp"; 5287 case ISD::FP_TO_SINT: return "fp_to_sint"; 5288 case ISD::FP_TO_UINT: return "fp_to_uint"; 5289 case ISD::BIT_CONVERT: return "bit_convert"; 5290 5291 case ISD::CONVERT_RNDSAT: { 5292 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5293 default: assert(0 && "Unknown cvt code!"); 5294 case ISD::CVT_FF: return "cvt_ff"; 5295 case ISD::CVT_FS: return "cvt_fs"; 5296 case ISD::CVT_FU: return "cvt_fu"; 5297 case ISD::CVT_SF: return "cvt_sf"; 5298 case ISD::CVT_UF: return "cvt_uf"; 5299 case ISD::CVT_SS: return "cvt_ss"; 5300 case ISD::CVT_SU: return "cvt_su"; 5301 case ISD::CVT_US: return "cvt_us"; 5302 case ISD::CVT_UU: return "cvt_uu"; 5303 } 5304 } 5305 5306 // Control flow instructions 5307 case ISD::BR: return "br"; 5308 case ISD::BRIND: return "brind"; 5309 case ISD::BR_JT: return "br_jt"; 5310 case ISD::BRCOND: return "brcond"; 5311 case ISD::BR_CC: return "br_cc"; 5312 case ISD::RET: return "ret"; 5313 case ISD::CALLSEQ_START: return "callseq_start"; 5314 case ISD::CALLSEQ_END: return "callseq_end"; 5315 5316 // Other operators 5317 case ISD::LOAD: return "load"; 5318 case ISD::STORE: return "store"; 5319 case ISD::VAARG: return "vaarg"; 5320 case ISD::VACOPY: return "vacopy"; 5321 case ISD::VAEND: return "vaend"; 5322 case ISD::VASTART: return "vastart"; 5323 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5324 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5325 case ISD::BUILD_PAIR: return "build_pair"; 5326 case ISD::STACKSAVE: return "stacksave"; 5327 case ISD::STACKRESTORE: return "stackrestore"; 5328 case ISD::TRAP: return "trap"; 5329 5330 // Bit manipulation 5331 case ISD::BSWAP: return "bswap"; 5332 case ISD::CTPOP: return "ctpop"; 5333 case ISD::CTTZ: return "cttz"; 5334 case ISD::CTLZ: return "ctlz"; 5335 5336 // Debug info 5337 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5338 case ISD::DEBUG_LOC: return "debug_loc"; 5339 5340 // Trampolines 5341 case ISD::TRAMPOLINE: return "trampoline"; 5342 5343 case ISD::CONDCODE: 5344 switch (cast<CondCodeSDNode>(this)->get()) { 5345 default: assert(0 && "Unknown setcc condition!"); 5346 case ISD::SETOEQ: return "setoeq"; 5347 case ISD::SETOGT: return "setogt"; 5348 case ISD::SETOGE: return "setoge"; 5349 case ISD::SETOLT: return "setolt"; 5350 case ISD::SETOLE: return "setole"; 5351 case ISD::SETONE: return "setone"; 5352 5353 case ISD::SETO: return "seto"; 5354 case ISD::SETUO: return "setuo"; 5355 case ISD::SETUEQ: return "setue"; 5356 case ISD::SETUGT: return "setugt"; 5357 case ISD::SETUGE: return "setuge"; 5358 case ISD::SETULT: return "setult"; 5359 case ISD::SETULE: return "setule"; 5360 case ISD::SETUNE: return "setune"; 5361 5362 case ISD::SETEQ: return "seteq"; 5363 case ISD::SETGT: return "setgt"; 5364 case ISD::SETGE: return "setge"; 5365 case ISD::SETLT: return "setlt"; 5366 case ISD::SETLE: return "setle"; 5367 case ISD::SETNE: return "setne"; 5368 } 5369 } 5370} 5371 5372const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5373 switch (AM) { 5374 default: 5375 return ""; 5376 case ISD::PRE_INC: 5377 return "<pre-inc>"; 5378 case ISD::PRE_DEC: 5379 return "<pre-dec>"; 5380 case ISD::POST_INC: 5381 return "<post-inc>"; 5382 case ISD::POST_DEC: 5383 return "<post-dec>"; 5384 } 5385} 5386 5387std::string ISD::ArgFlagsTy::getArgFlagsString() { 5388 std::string S = "< "; 5389 5390 if (isZExt()) 5391 S += "zext "; 5392 if (isSExt()) 5393 S += "sext "; 5394 if (isInReg()) 5395 S += "inreg "; 5396 if (isSRet()) 5397 S += "sret "; 5398 if (isByVal()) 5399 S += "byval "; 5400 if (isNest()) 5401 S += "nest "; 5402 if (getByValAlign()) 5403 S += "byval-align:" + utostr(getByValAlign()) + " "; 5404 if (getOrigAlign()) 5405 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5406 if (getByValSize()) 5407 S += "byval-size:" + utostr(getByValSize()) + " "; 5408 return S + ">"; 5409} 5410 5411void SDNode::dump() const { dump(0); } 5412void SDNode::dump(const SelectionDAG *G) const { 5413 print(errs(), G); 5414} 5415 5416void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const { 5417 OS << (void*)this << ": "; 5418 5419 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5420 if (i) OS << ","; 5421 if (getValueType(i) == MVT::Other) 5422 OS << "ch"; 5423 else 5424 OS << getValueType(i).getMVTString(); 5425 } 5426 OS << " = " << getOperationName(G); 5427} 5428 5429void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { 5430 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5431 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(this); 5432 OS << "<"; 5433 for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) { 5434 int Idx = SVN->getMaskElt(i); 5435 if (i) OS << ","; 5436 if (Idx < 0) 5437 OS << "u"; 5438 else 5439 OS << Idx; 5440 } 5441 OS << ">"; 5442 } 5443 5444 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5445 OS << '<' << CSDN->getAPIntValue() << '>'; 5446 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5447 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5448 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5449 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5450 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5451 else { 5452 OS << "<APFloat("; 5453 CSDN->getValueAPF().bitcastToAPInt().dump(); 5454 OS << ")>"; 5455 } 5456 } else if (const GlobalAddressSDNode *GADN = 5457 dyn_cast<GlobalAddressSDNode>(this)) { 5458 int64_t offset = GADN->getOffset(); 5459 OS << '<'; 5460 WriteAsOperand(OS, GADN->getGlobal()); 5461 OS << '>'; 5462 if (offset > 0) 5463 OS << " + " << offset; 5464 else 5465 OS << " " << offset; 5466 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5467 OS << "<" << FIDN->getIndex() << ">"; 5468 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5469 OS << "<" << JTDN->getIndex() << ">"; 5470 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5471 int offset = CP->getOffset(); 5472 if (CP->isMachineConstantPoolEntry()) 5473 OS << "<" << *CP->getMachineCPVal() << ">"; 5474 else 5475 OS << "<" << *CP->getConstVal() << ">"; 5476 if (offset > 0) 5477 OS << " + " << offset; 5478 else 5479 OS << " " << offset; 5480 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5481 OS << "<"; 5482 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5483 if (LBB) 5484 OS << LBB->getName() << " "; 5485 OS << (const void*)BBDN->getBasicBlock() << ">"; 5486 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5487 if (G && R->getReg() && 5488 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5489 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5490 } else { 5491 OS << " #" << R->getReg(); 5492 } 5493 } else if (const ExternalSymbolSDNode *ES = 5494 dyn_cast<ExternalSymbolSDNode>(this)) { 5495 OS << "'" << ES->getSymbol() << "'"; 5496 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5497 if (M->getValue()) 5498 OS << "<" << M->getValue() << ">"; 5499 else 5500 OS << "<null>"; 5501 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5502 if (M->MO.getValue()) 5503 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5504 else 5505 OS << "<null:" << M->MO.getOffset() << ">"; 5506 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5507 OS << N->getArgFlags().getArgFlagsString(); 5508 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5509 OS << ":" << N->getVT().getMVTString(); 5510 } 5511 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5512 const Value *SrcValue = LD->getSrcValue(); 5513 int SrcOffset = LD->getSrcValueOffset(); 5514 OS << " <"; 5515 if (SrcValue) 5516 OS << SrcValue; 5517 else 5518 OS << "null"; 5519 OS << ":" << SrcOffset << ">"; 5520 5521 bool doExt = true; 5522 switch (LD->getExtensionType()) { 5523 default: doExt = false; break; 5524 case ISD::EXTLOAD: OS << " <anyext "; break; 5525 case ISD::SEXTLOAD: OS << " <sext "; break; 5526 case ISD::ZEXTLOAD: OS << " <zext "; break; 5527 } 5528 if (doExt) 5529 OS << LD->getMemoryVT().getMVTString() << ">"; 5530 5531 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5532 if (*AM) 5533 OS << " " << AM; 5534 if (LD->isVolatile()) 5535 OS << " <volatile>"; 5536 OS << " alignment=" << LD->getAlignment(); 5537 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5538 const Value *SrcValue = ST->getSrcValue(); 5539 int SrcOffset = ST->getSrcValueOffset(); 5540 OS << " <"; 5541 if (SrcValue) 5542 OS << SrcValue; 5543 else 5544 OS << "null"; 5545 OS << ":" << SrcOffset << ">"; 5546 5547 if (ST->isTruncatingStore()) 5548 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5549 5550 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5551 if (*AM) 5552 OS << " " << AM; 5553 if (ST->isVolatile()) 5554 OS << " <volatile>"; 5555 OS << " alignment=" << ST->getAlignment(); 5556 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5557 const Value *SrcValue = AT->getSrcValue(); 5558 int SrcOffset = AT->getSrcValueOffset(); 5559 OS << " <"; 5560 if (SrcValue) 5561 OS << SrcValue; 5562 else 5563 OS << "null"; 5564 OS << ":" << SrcOffset << ">"; 5565 if (AT->isVolatile()) 5566 OS << " <volatile>"; 5567 OS << " alignment=" << AT->getAlignment(); 5568 } 5569} 5570 5571void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5572 print_types(OS, G); 5573 OS << " "; 5574 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5575 if (i) OS << ", "; 5576 OS << (void*)getOperand(i).getNode(); 5577 if (unsigned RN = getOperand(i).getResNo()) 5578 OS << ":" << RN; 5579 } 5580 print_details(OS, G); 5581} 5582 5583static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5584 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5585 if (N->getOperand(i).getNode()->hasOneUse()) 5586 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5587 else 5588 cerr << "\n" << std::string(indent+2, ' ') 5589 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5590 5591 5592 cerr << "\n" << std::string(indent, ' '); 5593 N->dump(G); 5594} 5595 5596void SelectionDAG::dump() const { 5597 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5598 5599 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5600 I != E; ++I) { 5601 const SDNode *N = I; 5602 if (!N->hasOneUse() && N != getRoot().getNode()) 5603 DumpNodes(N, 2, this); 5604 } 5605 5606 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5607 5608 cerr << "\n\n"; 5609} 5610 5611void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const { 5612 print_types(OS, G); 5613 print_details(OS, G); 5614} 5615 5616typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet; 5617static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, 5618 const SelectionDAG *G, VisitedSDNodeSet &once) { 5619 if (!once.insert(N)) // If we've been here before, return now. 5620 return; 5621 // Dump the current SDNode, but don't end the line yet. 5622 OS << std::string(indent, ' '); 5623 N->printr(OS, G); 5624 // Having printed this SDNode, walk the children: 5625 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5626 const SDNode *child = N->getOperand(i).getNode(); 5627 if (i) OS << ","; 5628 OS << " "; 5629 if (child->getNumOperands() == 0) { 5630 // This child has no grandchildren; print it inline right here. 5631 child->printr(OS, G); 5632 once.insert(child); 5633 } else { // Just the address. FIXME: also print the child's opcode 5634 OS << (void*)child; 5635 if (unsigned RN = N->getOperand(i).getResNo()) 5636 OS << ":" << RN; 5637 } 5638 } 5639 OS << "\n"; 5640 // Dump children that have grandchildren on their own line(s). 5641 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5642 const SDNode *child = N->getOperand(i).getNode(); 5643 DumpNodesr(OS, child, indent+2, G, once); 5644 } 5645} 5646 5647void SDNode::dumpr() const { 5648 VisitedSDNodeSet once; 5649 DumpNodesr(errs(), this, 0, 0, once); 5650} 5651 5652 5653// getAddressSpace - Return the address space this GlobalAddress belongs to. 5654unsigned GlobalAddressSDNode::getAddressSpace() const { 5655 return getGlobal()->getType()->getAddressSpace(); 5656} 5657 5658 5659const Type *ConstantPoolSDNode::getType() const { 5660 if (isMachineConstantPoolEntry()) 5661 return Val.MachineCPVal->getType(); 5662 return Val.ConstVal->getType(); 5663} 5664 5665bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue, 5666 APInt &SplatUndef, 5667 unsigned &SplatBitSize, 5668 bool &HasAnyUndefs, 5669 unsigned MinSplatBits) { 5670 MVT VT = getValueType(0); 5671 assert(VT.isVector() && "Expected a vector type"); 5672 unsigned sz = VT.getSizeInBits(); 5673 if (MinSplatBits > sz) 5674 return false; 5675 5676 SplatValue = APInt(sz, 0); 5677 SplatUndef = APInt(sz, 0); 5678 5679 // Get the bits. Bits with undefined values (when the corresponding element 5680 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared 5681 // in SplatValue. If any of the values are not constant, give up and return 5682 // false. 5683 unsigned int nOps = getNumOperands(); 5684 assert(nOps > 0 && "isConstantSplat has 0-size build vector"); 5685 unsigned EltBitSize = VT.getVectorElementType().getSizeInBits(); 5686 for (unsigned i = 0; i < nOps; ++i) { 5687 SDValue OpVal = getOperand(i); 5688 unsigned BitPos = i * EltBitSize; 5689 5690 if (OpVal.getOpcode() == ISD::UNDEF) 5691 SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos +EltBitSize); 5692 else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) 5693 SplatValue |= (APInt(CN->getAPIntValue()).zextOrTrunc(EltBitSize). 5694 zextOrTrunc(sz) << BitPos); 5695 else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) 5696 SplatValue |= CN->getValueAPF().bitcastToAPInt().zextOrTrunc(sz) <<BitPos; 5697 else 5698 return false; 5699 } 5700 5701 // The build_vector is all constants or undefs. Find the smallest element 5702 // size that splats the vector. 5703 5704 HasAnyUndefs = (SplatUndef != 0); 5705 while (sz > 8) { 5706 5707 unsigned HalfSize = sz / 2; 5708 APInt HighValue = APInt(SplatValue).lshr(HalfSize).trunc(HalfSize); 5709 APInt LowValue = APInt(SplatValue).trunc(HalfSize); 5710 APInt HighUndef = APInt(SplatUndef).lshr(HalfSize).trunc(HalfSize); 5711 APInt LowUndef = APInt(SplatUndef).trunc(HalfSize); 5712 5713 // If the two halves do not match (ignoring undef bits), stop here. 5714 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) || 5715 MinSplatBits > HalfSize) 5716 break; 5717 5718 SplatValue = HighValue | LowValue; 5719 SplatUndef = HighUndef & LowUndef; 5720 5721 sz = HalfSize; 5722 } 5723 5724 SplatBitSize = sz; 5725 return true; 5726} 5727 5728bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) { 5729 // Find the first non-undef value in the shuffle mask. 5730 unsigned i, e; 5731 for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i) 5732 /* search */; 5733 5734 assert(i != e && "VECTOR_SHUFFLE node with all undef indices!"); 5735 5736 // Make sure all remaining elements are either undef or the same as the first 5737 // non-undef value. 5738 for (int Idx = Mask[i]; i != e; ++i) 5739 if (Mask[i] >= 0 && Mask[i] != Idx) 5740 return false; 5741 return true; 5742} 5743