SelectionDAG.cpp revision 5ebb9308d8bec5fdc2fd0e1cfd556a86ced3eff2
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/ADT/SetVector.h" 37#include "llvm/ADT/SmallPtrSet.h" 38#include "llvm/ADT/SmallSet.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/ADT/StringExtras.h" 41#include <algorithm> 42#include <cmath> 43using namespace llvm; 44 45/// makeVTList - Return an instance of the SDVTList struct initialized with the 46/// specified members. 47static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 48 SDVTList Res = {VTs, NumVTs}; 49 return Res; 50} 51 52static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 53 switch (VT.getSimpleVT()) { 54 default: assert(0 && "Unknown FP format"); 55 case MVT::f32: return &APFloat::IEEEsingle; 56 case MVT::f64: return &APFloat::IEEEdouble; 57 case MVT::f80: return &APFloat::x87DoubleExtended; 58 case MVT::f128: return &APFloat::IEEEquad; 59 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 60 } 61} 62 63SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 64 65//===----------------------------------------------------------------------===// 66// ConstantFPSDNode Class 67//===----------------------------------------------------------------------===// 68 69/// isExactlyValue - We don't rely on operator== working on double values, as 70/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 71/// As such, this method can be used to do an exact bit-for-bit comparison of 72/// two floating point values. 73bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 74 return getValueAPF().bitwiseIsEqual(V); 75} 76 77bool ConstantFPSDNode::isValueValidForType(MVT VT, 78 const APFloat& Val) { 79 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 80 81 // PPC long double cannot be converted to any other type. 82 if (VT == MVT::ppcf128 || 83 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 84 return false; 85 86 // convert modifies in place, so make a copy. 87 APFloat Val2 = APFloat(Val); 88 bool losesInfo; 89 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 90 &losesInfo); 91 return !losesInfo; 92} 93 94//===----------------------------------------------------------------------===// 95// ISD Namespace 96//===----------------------------------------------------------------------===// 97 98/// isBuildVectorAllOnes - Return true if the specified node is a 99/// BUILD_VECTOR where all of the elements are ~0 or undef. 100bool ISD::isBuildVectorAllOnes(const SDNode *N) { 101 // Look through a bit convert. 102 if (N->getOpcode() == ISD::BIT_CONVERT) 103 N = N->getOperand(0).getNode(); 104 105 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 106 107 unsigned i = 0, e = N->getNumOperands(); 108 109 // Skip over all of the undef values. 110 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 111 ++i; 112 113 // Do not accept an all-undef vector. 114 if (i == e) return false; 115 116 // Do not accept build_vectors that aren't all constants or which have non-~0 117 // elements. 118 SDValue NotZero = N->getOperand(i); 119 if (isa<ConstantSDNode>(NotZero)) { 120 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 121 return false; 122 } else if (isa<ConstantFPSDNode>(NotZero)) { 123 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 124 bitcastToAPInt().isAllOnesValue()) 125 return false; 126 } else 127 return false; 128 129 // Okay, we have at least one ~0 value, check to see if the rest match or are 130 // undefs. 131 for (++i; i != e; ++i) 132 if (N->getOperand(i) != NotZero && 133 N->getOperand(i).getOpcode() != ISD::UNDEF) 134 return false; 135 return true; 136} 137 138 139/// isBuildVectorAllZeros - Return true if the specified node is a 140/// BUILD_VECTOR where all of the elements are 0 or undef. 141bool ISD::isBuildVectorAllZeros(const SDNode *N) { 142 // Look through a bit convert. 143 if (N->getOpcode() == ISD::BIT_CONVERT) 144 N = N->getOperand(0).getNode(); 145 146 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 147 148 unsigned i = 0, e = N->getNumOperands(); 149 150 // Skip over all of the undef values. 151 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 152 ++i; 153 154 // Do not accept an all-undef vector. 155 if (i == e) return false; 156 157 // Do not accept build_vectors that aren't all constants or which have non-0 158 // elements. 159 SDValue Zero = N->getOperand(i); 160 if (isa<ConstantSDNode>(Zero)) { 161 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 162 return false; 163 } else if (isa<ConstantFPSDNode>(Zero)) { 164 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 165 return false; 166 } else 167 return false; 168 169 // Okay, we have at least one 0 value, check to see if the rest match or are 170 // undefs. 171 for (++i; i != e; ++i) 172 if (N->getOperand(i) != Zero && 173 N->getOperand(i).getOpcode() != ISD::UNDEF) 174 return false; 175 return true; 176} 177 178/// isScalarToVector - Return true if the specified node is a 179/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 180/// element is not an undef. 181bool ISD::isScalarToVector(const SDNode *N) { 182 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 183 return true; 184 185 if (N->getOpcode() != ISD::BUILD_VECTOR) 186 return false; 187 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 188 return false; 189 unsigned NumElems = N->getNumOperands(); 190 for (unsigned i = 1; i < NumElems; ++i) { 191 SDValue V = N->getOperand(i); 192 if (V.getOpcode() != ISD::UNDEF) 193 return false; 194 } 195 return true; 196} 197 198 199/// isDebugLabel - Return true if the specified node represents a debug 200/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 201bool ISD::isDebugLabel(const SDNode *N) { 202 SDValue Zero; 203 if (N->getOpcode() == ISD::DBG_LABEL) 204 return true; 205 if (N->isMachineOpcode() && 206 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 207 return true; 208 return false; 209} 210 211/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 212/// when given the operation for (X op Y). 213ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 214 // To perform this operation, we just need to swap the L and G bits of the 215 // operation. 216 unsigned OldL = (Operation >> 2) & 1; 217 unsigned OldG = (Operation >> 1) & 1; 218 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 219 (OldL << 1) | // New G bit 220 (OldG << 2)); // New L bit. 221} 222 223/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 224/// 'op' is a valid SetCC operation. 225ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 226 unsigned Operation = Op; 227 if (isInteger) 228 Operation ^= 7; // Flip L, G, E bits, but not U. 229 else 230 Operation ^= 15; // Flip all of the condition bits. 231 232 if (Operation > ISD::SETTRUE2) 233 Operation &= ~8; // Don't let N and U bits get set. 234 235 return ISD::CondCode(Operation); 236} 237 238 239/// isSignedOp - For an integer comparison, return 1 if the comparison is a 240/// signed operation and 2 if the result is an unsigned comparison. Return zero 241/// if the operation does not depend on the sign of the input (setne and seteq). 242static int isSignedOp(ISD::CondCode Opcode) { 243 switch (Opcode) { 244 default: assert(0 && "Illegal integer setcc operation!"); 245 case ISD::SETEQ: 246 case ISD::SETNE: return 0; 247 case ISD::SETLT: 248 case ISD::SETLE: 249 case ISD::SETGT: 250 case ISD::SETGE: return 1; 251 case ISD::SETULT: 252 case ISD::SETULE: 253 case ISD::SETUGT: 254 case ISD::SETUGE: return 2; 255 } 256} 257 258/// getSetCCOrOperation - Return the result of a logical OR between different 259/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 260/// returns SETCC_INVALID if it is not possible to represent the resultant 261/// comparison. 262ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 263 bool isInteger) { 264 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 265 // Cannot fold a signed integer setcc with an unsigned integer setcc. 266 return ISD::SETCC_INVALID; 267 268 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 269 270 // If the N and U bits get set then the resultant comparison DOES suddenly 271 // care about orderedness, and is true when ordered. 272 if (Op > ISD::SETTRUE2) 273 Op &= ~16; // Clear the U bit if the N bit is set. 274 275 // Canonicalize illegal integer setcc's. 276 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 277 Op = ISD::SETNE; 278 279 return ISD::CondCode(Op); 280} 281 282/// getSetCCAndOperation - Return the result of a logical AND between different 283/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 284/// function returns zero if it is not possible to represent the resultant 285/// comparison. 286ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 287 bool isInteger) { 288 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 289 // Cannot fold a signed setcc with an unsigned setcc. 290 return ISD::SETCC_INVALID; 291 292 // Combine all of the condition bits. 293 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 294 295 // Canonicalize illegal integer setcc's. 296 if (isInteger) { 297 switch (Result) { 298 default: break; 299 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 300 case ISD::SETOEQ: // SETEQ & SETU[LG]E 301 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 302 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 303 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 304 } 305 } 306 307 return Result; 308} 309 310const TargetMachine &SelectionDAG::getTarget() const { 311 return MF->getTarget(); 312} 313 314//===----------------------------------------------------------------------===// 315// SDNode Profile Support 316//===----------------------------------------------------------------------===// 317 318/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 319/// 320static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 321 ID.AddInteger(OpC); 322} 323 324/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 325/// solely with their pointer. 326static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 327 ID.AddPointer(VTList.VTs); 328} 329 330/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 331/// 332static void AddNodeIDOperands(FoldingSetNodeID &ID, 333 const SDValue *Ops, unsigned NumOps) { 334 for (; NumOps; --NumOps, ++Ops) { 335 ID.AddPointer(Ops->getNode()); 336 ID.AddInteger(Ops->getResNo()); 337 } 338} 339 340/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 341/// 342static void AddNodeIDOperands(FoldingSetNodeID &ID, 343 const SDUse *Ops, unsigned NumOps) { 344 for (; NumOps; --NumOps, ++Ops) { 345 ID.AddPointer(Ops->getNode()); 346 ID.AddInteger(Ops->getResNo()); 347 } 348} 349 350static void AddNodeIDNode(FoldingSetNodeID &ID, 351 unsigned short OpC, SDVTList VTList, 352 const SDValue *OpList, unsigned N) { 353 AddNodeIDOpcode(ID, OpC); 354 AddNodeIDValueTypes(ID, VTList); 355 AddNodeIDOperands(ID, OpList, N); 356} 357 358/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 359/// the NodeID data. 360static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 361 switch (N->getOpcode()) { 362 default: break; // Normal nodes don't need extra info. 363 case ISD::ARG_FLAGS: 364 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 365 break; 366 case ISD::TargetConstant: 367 case ISD::Constant: 368 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 369 break; 370 case ISD::TargetConstantFP: 371 case ISD::ConstantFP: { 372 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 373 break; 374 } 375 case ISD::TargetGlobalAddress: 376 case ISD::GlobalAddress: 377 case ISD::TargetGlobalTLSAddress: 378 case ISD::GlobalTLSAddress: { 379 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 380 ID.AddPointer(GA->getGlobal()); 381 ID.AddInteger(GA->getOffset()); 382 break; 383 } 384 case ISD::BasicBlock: 385 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 386 break; 387 case ISD::Register: 388 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 389 break; 390 case ISD::DBG_STOPPOINT: { 391 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 392 ID.AddInteger(DSP->getLine()); 393 ID.AddInteger(DSP->getColumn()); 394 ID.AddPointer(DSP->getCompileUnit()); 395 break; 396 } 397 case ISD::SRCVALUE: 398 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 399 break; 400 case ISD::MEMOPERAND: { 401 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 402 MO.Profile(ID); 403 break; 404 } 405 case ISD::FrameIndex: 406 case ISD::TargetFrameIndex: 407 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 408 break; 409 case ISD::JumpTable: 410 case ISD::TargetJumpTable: 411 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 412 break; 413 case ISD::ConstantPool: 414 case ISD::TargetConstantPool: { 415 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 416 ID.AddInteger(CP->getAlignment()); 417 ID.AddInteger(CP->getOffset()); 418 if (CP->isMachineConstantPoolEntry()) 419 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 420 else 421 ID.AddPointer(CP->getConstVal()); 422 break; 423 } 424 case ISD::CALL: { 425 const CallSDNode *Call = cast<CallSDNode>(N); 426 ID.AddInteger(Call->getCallingConv()); 427 ID.AddInteger(Call->isVarArg()); 428 break; 429 } 430 case ISD::LOAD: { 431 const LoadSDNode *LD = cast<LoadSDNode>(N); 432 ID.AddInteger(LD->getMemoryVT().getRawBits()); 433 ID.AddInteger(LD->getRawSubclassData()); 434 break; 435 } 436 case ISD::STORE: { 437 const StoreSDNode *ST = cast<StoreSDNode>(N); 438 ID.AddInteger(ST->getMemoryVT().getRawBits()); 439 ID.AddInteger(ST->getRawSubclassData()); 440 break; 441 } 442 case ISD::ATOMIC_CMP_SWAP: 443 case ISD::ATOMIC_SWAP: 444 case ISD::ATOMIC_LOAD_ADD: 445 case ISD::ATOMIC_LOAD_SUB: 446 case ISD::ATOMIC_LOAD_AND: 447 case ISD::ATOMIC_LOAD_OR: 448 case ISD::ATOMIC_LOAD_XOR: 449 case ISD::ATOMIC_LOAD_NAND: 450 case ISD::ATOMIC_LOAD_MIN: 451 case ISD::ATOMIC_LOAD_MAX: 452 case ISD::ATOMIC_LOAD_UMIN: 453 case ISD::ATOMIC_LOAD_UMAX: { 454 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 455 ID.AddInteger(AT->getMemoryVT().getRawBits()); 456 ID.AddInteger(AT->getRawSubclassData()); 457 break; 458 } 459 case ISD::VECTOR_SHUFFLE: { 460 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 461 for (unsigned i = 0, e = N->getValueType(0).getVectorNumElements(); 462 i != e; ++i) 463 ID.AddInteger(SVN->getMaskElt(i)); 464 break; 465 } 466 } // end switch (N->getOpcode()) 467} 468 469/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 470/// data. 471static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 472 AddNodeIDOpcode(ID, N->getOpcode()); 473 // Add the return value info. 474 AddNodeIDValueTypes(ID, N->getVTList()); 475 // Add the operand info. 476 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 477 478 // Handle SDNode leafs with special info. 479 AddNodeIDCustom(ID, N); 480} 481 482/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 483/// the CSE map that carries alignment, volatility, indexing mode, and 484/// extension/truncation information. 485/// 486static inline unsigned 487encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, 488 bool isVolatile, unsigned Alignment) { 489 assert((ConvType & 3) == ConvType && 490 "ConvType may not require more than 2 bits!"); 491 assert((AM & 7) == AM && 492 "AM may not require more than 3 bits!"); 493 return ConvType | 494 (AM << 2) | 495 (isVolatile << 5) | 496 ((Log2_32(Alignment) + 1) << 6); 497} 498 499//===----------------------------------------------------------------------===// 500// SelectionDAG Class 501//===----------------------------------------------------------------------===// 502 503/// doNotCSE - Return true if CSE should not be performed for this node. 504static bool doNotCSE(SDNode *N) { 505 if (N->getValueType(0) == MVT::Flag) 506 return true; // Never CSE anything that produces a flag. 507 508 switch (N->getOpcode()) { 509 default: break; 510 case ISD::HANDLENODE: 511 case ISD::DBG_LABEL: 512 case ISD::DBG_STOPPOINT: 513 case ISD::EH_LABEL: 514 case ISD::DECLARE: 515 return true; // Never CSE these nodes. 516 } 517 518 // Check that remaining values produced are not flags. 519 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 520 if (N->getValueType(i) == MVT::Flag) 521 return true; // Never CSE anything that produces a flag. 522 523 return false; 524} 525 526/// RemoveDeadNodes - This method deletes all unreachable nodes in the 527/// SelectionDAG. 528void SelectionDAG::RemoveDeadNodes() { 529 // Create a dummy node (which is not added to allnodes), that adds a reference 530 // to the root node, preventing it from being deleted. 531 HandleSDNode Dummy(getRoot()); 532 533 SmallVector<SDNode*, 128> DeadNodes; 534 535 // Add all obviously-dead nodes to the DeadNodes worklist. 536 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 537 if (I->use_empty()) 538 DeadNodes.push_back(I); 539 540 RemoveDeadNodes(DeadNodes); 541 542 // If the root changed (e.g. it was a dead load, update the root). 543 setRoot(Dummy.getValue()); 544} 545 546/// RemoveDeadNodes - This method deletes the unreachable nodes in the 547/// given list, and any nodes that become unreachable as a result. 548void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 549 DAGUpdateListener *UpdateListener) { 550 551 // Process the worklist, deleting the nodes and adding their uses to the 552 // worklist. 553 while (!DeadNodes.empty()) { 554 SDNode *N = DeadNodes.pop_back_val(); 555 556 if (UpdateListener) 557 UpdateListener->NodeDeleted(N, 0); 558 559 // Take the node out of the appropriate CSE map. 560 RemoveNodeFromCSEMaps(N); 561 562 // Next, brutally remove the operand list. This is safe to do, as there are 563 // no cycles in the graph. 564 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 565 SDUse &Use = *I++; 566 SDNode *Operand = Use.getNode(); 567 Use.set(SDValue()); 568 569 // Now that we removed this operand, see if there are no uses of it left. 570 if (Operand->use_empty()) 571 DeadNodes.push_back(Operand); 572 } 573 574 DeallocateNode(N); 575 } 576} 577 578void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 579 SmallVector<SDNode*, 16> DeadNodes(1, N); 580 RemoveDeadNodes(DeadNodes, UpdateListener); 581} 582 583void SelectionDAG::DeleteNode(SDNode *N) { 584 // First take this out of the appropriate CSE map. 585 RemoveNodeFromCSEMaps(N); 586 587 // Finally, remove uses due to operands of this node, remove from the 588 // AllNodes list, and delete the node. 589 DeleteNodeNotInCSEMaps(N); 590} 591 592void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 593 assert(N != AllNodes.begin() && "Cannot delete the entry node!"); 594 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 595 596 // Drop all of the operands and decrement used node's use counts. 597 N->DropOperands(); 598 599 DeallocateNode(N); 600} 601 602void SelectionDAG::DeallocateNode(SDNode *N) { 603 if (N->OperandsNeedDelete) 604 delete[] N->OperandList; 605 606 // Set the opcode to DELETED_NODE to help catch bugs when node 607 // memory is reallocated. 608 N->NodeType = ISD::DELETED_NODE; 609 610 NodeAllocator.Deallocate(AllNodes.remove(N)); 611} 612 613/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 614/// correspond to it. This is useful when we're about to delete or repurpose 615/// the node. We don't want future request for structurally identical nodes 616/// to return N anymore. 617bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 618 bool Erased = false; 619 switch (N->getOpcode()) { 620 case ISD::EntryToken: 621 assert(0 && "EntryToken should not be in CSEMaps!"); 622 return false; 623 case ISD::HANDLENODE: return false; // noop. 624 case ISD::CONDCODE: 625 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 626 "Cond code doesn't exist!"); 627 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 628 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 629 break; 630 case ISD::ExternalSymbol: 631 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 632 break; 633 case ISD::TargetExternalSymbol: 634 Erased = 635 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 636 break; 637 case ISD::VALUETYPE: { 638 MVT VT = cast<VTSDNode>(N)->getVT(); 639 if (VT.isExtended()) { 640 Erased = ExtendedValueTypeNodes.erase(VT); 641 } else { 642 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 643 ValueTypeNodes[VT.getSimpleVT()] = 0; 644 } 645 break; 646 } 647 default: 648 // Remove it from the CSE Map. 649 Erased = CSEMap.RemoveNode(N); 650 break; 651 } 652#ifndef NDEBUG 653 // Verify that the node was actually in one of the CSE maps, unless it has a 654 // flag result (which cannot be CSE'd) or is one of the special cases that are 655 // not subject to CSE. 656 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 657 !N->isMachineOpcode() && !doNotCSE(N)) { 658 N->dump(this); 659 cerr << "\n"; 660 assert(0 && "Node is not in map!"); 661 } 662#endif 663 return Erased; 664} 665 666/// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE 667/// maps and modified in place. Add it back to the CSE maps, unless an identical 668/// node already exists, in which case transfer all its users to the existing 669/// node. This transfer can potentially trigger recursive merging. 670/// 671void 672SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N, 673 DAGUpdateListener *UpdateListener) { 674 // For node types that aren't CSE'd, just act as if no identical node 675 // already exists. 676 if (!doNotCSE(N)) { 677 SDNode *Existing = CSEMap.GetOrInsertNode(N); 678 if (Existing != N) { 679 // If there was already an existing matching node, use ReplaceAllUsesWith 680 // to replace the dead one with the existing one. This can cause 681 // recursive merging of other unrelated nodes down the line. 682 ReplaceAllUsesWith(N, Existing, UpdateListener); 683 684 // N is now dead. Inform the listener if it exists and delete it. 685 if (UpdateListener) 686 UpdateListener->NodeDeleted(N, Existing); 687 DeleteNodeNotInCSEMaps(N); 688 return; 689 } 690 } 691 692 // If the node doesn't already exist, we updated it. Inform a listener if 693 // it exists. 694 if (UpdateListener) 695 UpdateListener->NodeUpdated(N); 696} 697 698/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 699/// were replaced with those specified. If this node is never memoized, 700/// return null, otherwise return a pointer to the slot it would take. If a 701/// node already exists with these operands, the slot will be non-null. 702SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 703 void *&InsertPos) { 704 if (doNotCSE(N)) 705 return 0; 706 707 SDValue Ops[] = { Op }; 708 FoldingSetNodeID ID; 709 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 710 AddNodeIDCustom(ID, N); 711 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 712} 713 714/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 715/// were replaced with those specified. If this node is never memoized, 716/// return null, otherwise return a pointer to the slot it would take. If a 717/// node already exists with these operands, the slot will be non-null. 718SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 719 SDValue Op1, SDValue Op2, 720 void *&InsertPos) { 721 if (doNotCSE(N)) 722 return 0; 723 724 SDValue Ops[] = { Op1, Op2 }; 725 FoldingSetNodeID ID; 726 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 727 AddNodeIDCustom(ID, N); 728 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 729} 730 731 732/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 733/// were replaced with those specified. If this node is never memoized, 734/// return null, otherwise return a pointer to the slot it would take. If a 735/// node already exists with these operands, the slot will be non-null. 736SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 737 const SDValue *Ops,unsigned NumOps, 738 void *&InsertPos) { 739 if (doNotCSE(N)) 740 return 0; 741 742 FoldingSetNodeID ID; 743 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 744 AddNodeIDCustom(ID, N); 745 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 746} 747 748/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 749void SelectionDAG::VerifyNode(SDNode *N) { 750 switch (N->getOpcode()) { 751 default: 752 break; 753 case ISD::BUILD_PAIR: { 754 MVT VT = N->getValueType(0); 755 assert(N->getNumValues() == 1 && "Too many results!"); 756 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 757 "Wrong return type!"); 758 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 759 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 760 "Mismatched operand types!"); 761 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 762 "Wrong operand type!"); 763 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 764 "Wrong return type size"); 765 break; 766 } 767 case ISD::BUILD_VECTOR: { 768 assert(N->getNumValues() == 1 && "Too many results!"); 769 assert(N->getValueType(0).isVector() && "Wrong return type!"); 770 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 771 "Wrong number of operands!"); 772 MVT EltVT = N->getValueType(0).getVectorElementType(); 773 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 774 assert((I->getValueType() == EltVT || 775 (EltVT.isInteger() && I->getValueType().isInteger() && 776 EltVT.bitsLE(I->getValueType()))) && 777 "Wrong operand type!"); 778 break; 779 } 780 } 781} 782 783/// getMVTAlignment - Compute the default alignment value for the 784/// given type. 785/// 786unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 787 const Type *Ty = VT == MVT::iPTR ? 788 PointerType::get(Type::Int8Ty, 0) : 789 VT.getTypeForMVT(); 790 791 return TLI.getTargetData()->getABITypeAlignment(Ty); 792} 793 794// EntryNode could meaningfully have debug info if we can find it... 795SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 796 : TLI(tli), FLI(fli), DW(0), 797 EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(), 798 getVTList(MVT::Other)), Root(getEntryNode()) { 799 AllNodes.push_back(&EntryNode); 800} 801 802void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi, 803 DwarfWriter *dw) { 804 MF = &mf; 805 MMI = mmi; 806 DW = dw; 807} 808 809SelectionDAG::~SelectionDAG() { 810 allnodes_clear(); 811} 812 813void SelectionDAG::allnodes_clear() { 814 assert(&*AllNodes.begin() == &EntryNode); 815 AllNodes.remove(AllNodes.begin()); 816 while (!AllNodes.empty()) 817 DeallocateNode(AllNodes.begin()); 818} 819 820void SelectionDAG::clear() { 821 allnodes_clear(); 822 OperandAllocator.Reset(); 823 CSEMap.clear(); 824 825 ExtendedValueTypeNodes.clear(); 826 ExternalSymbols.clear(); 827 TargetExternalSymbols.clear(); 828 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 829 static_cast<CondCodeSDNode*>(0)); 830 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 831 static_cast<SDNode*>(0)); 832 833 EntryNode.UseList = 0; 834 AllNodes.push_back(&EntryNode); 835 Root = getEntryNode(); 836} 837 838SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { 839 if (Op.getValueType() == VT) return Op; 840 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 841 VT.getSizeInBits()); 842 return getNode(ISD::AND, DL, Op.getValueType(), Op, 843 getConstant(Imm, Op.getValueType())); 844} 845 846/// getNOT - Create a bitwise NOT operation as (XOR Val, -1). 847/// 848SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) { 849 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 850 SDValue NegOne = 851 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 852 return getNode(ISD::XOR, DL, VT, Val, NegOne); 853} 854 855SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 856 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 857 assert((EltVT.getSizeInBits() >= 64 || 858 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) && 859 "getConstant with a uint64_t value that doesn't fit in the type!"); 860 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 861} 862 863SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 864 return getConstant(*ConstantInt::get(Val), VT, isT); 865} 866 867SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 868 assert(VT.isInteger() && "Cannot create FP integer constant!"); 869 870 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 871 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 872 "APInt size does not match type size!"); 873 874 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 875 FoldingSetNodeID ID; 876 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 877 ID.AddPointer(&Val); 878 void *IP = 0; 879 SDNode *N = NULL; 880 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 881 if (!VT.isVector()) 882 return SDValue(N, 0); 883 if (!N) { 884 N = NodeAllocator.Allocate<ConstantSDNode>(); 885 new (N) ConstantSDNode(isT, &Val, EltVT); 886 CSEMap.InsertNode(N, IP); 887 AllNodes.push_back(N); 888 } 889 890 SDValue Result(N, 0); 891 if (VT.isVector()) { 892 SmallVector<SDValue, 8> Ops; 893 Ops.assign(VT.getVectorNumElements(), Result); 894 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 895 VT, &Ops[0], Ops.size()); 896 } 897 return Result; 898} 899 900SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 901 return getConstant(Val, TLI.getPointerTy(), isTarget); 902} 903 904 905SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 906 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 907} 908 909SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 910 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 911 912 MVT EltVT = 913 VT.isVector() ? VT.getVectorElementType() : VT; 914 915 // Do the map lookup using the actual bit pattern for the floating point 916 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 917 // we don't have issues with SNANs. 918 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 919 FoldingSetNodeID ID; 920 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 921 ID.AddPointer(&V); 922 void *IP = 0; 923 SDNode *N = NULL; 924 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 925 if (!VT.isVector()) 926 return SDValue(N, 0); 927 if (!N) { 928 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 929 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 930 CSEMap.InsertNode(N, IP); 931 AllNodes.push_back(N); 932 } 933 934 SDValue Result(N, 0); 935 if (VT.isVector()) { 936 SmallVector<SDValue, 8> Ops; 937 Ops.assign(VT.getVectorNumElements(), Result); 938 // FIXME DebugLoc info might be appropriate here 939 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 940 VT, &Ops[0], Ops.size()); 941 } 942 return Result; 943} 944 945SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 946 MVT EltVT = 947 VT.isVector() ? VT.getVectorElementType() : VT; 948 if (EltVT==MVT::f32) 949 return getConstantFP(APFloat((float)Val), VT, isTarget); 950 else 951 return getConstantFP(APFloat(Val), VT, isTarget); 952} 953 954SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 955 MVT VT, int64_t Offset, 956 bool isTargetGA) { 957 unsigned Opc; 958 959 // Truncate (with sign-extension) the offset value to the pointer size. 960 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 961 if (BitWidth < 64) 962 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 963 964 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 965 if (!GVar) { 966 // If GV is an alias then use the aliasee for determining thread-localness. 967 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 968 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 969 } 970 971 if (GVar && GVar->isThreadLocal()) 972 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 973 else 974 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 975 976 FoldingSetNodeID ID; 977 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 978 ID.AddPointer(GV); 979 ID.AddInteger(Offset); 980 void *IP = 0; 981 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 982 return SDValue(E, 0); 983 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 984 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 985 CSEMap.InsertNode(N, IP); 986 AllNodes.push_back(N); 987 return SDValue(N, 0); 988} 989 990SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 991 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 992 FoldingSetNodeID ID; 993 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 994 ID.AddInteger(FI); 995 void *IP = 0; 996 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 997 return SDValue(E, 0); 998 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 999 new (N) FrameIndexSDNode(FI, VT, isTarget); 1000 CSEMap.InsertNode(N, IP); 1001 AllNodes.push_back(N); 1002 return SDValue(N, 0); 1003} 1004 1005SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 1006 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1007 FoldingSetNodeID ID; 1008 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1009 ID.AddInteger(JTI); 1010 void *IP = 0; 1011 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1012 return SDValue(E, 0); 1013 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1014 new (N) JumpTableSDNode(JTI, VT, isTarget); 1015 CSEMap.InsertNode(N, IP); 1016 AllNodes.push_back(N); 1017 return SDValue(N, 0); 1018} 1019 1020SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1021 unsigned Alignment, int Offset, 1022 bool isTarget) { 1023 if (Alignment == 0) 1024 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1025 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1026 FoldingSetNodeID ID; 1027 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1028 ID.AddInteger(Alignment); 1029 ID.AddInteger(Offset); 1030 ID.AddPointer(C); 1031 void *IP = 0; 1032 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1033 return SDValue(E, 0); 1034 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1035 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1036 CSEMap.InsertNode(N, IP); 1037 AllNodes.push_back(N); 1038 return SDValue(N, 0); 1039} 1040 1041 1042SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1043 unsigned Alignment, int Offset, 1044 bool isTarget) { 1045 if (Alignment == 0) 1046 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1047 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1048 FoldingSetNodeID ID; 1049 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1050 ID.AddInteger(Alignment); 1051 ID.AddInteger(Offset); 1052 C->AddSelectionDAGCSEId(ID); 1053 void *IP = 0; 1054 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1055 return SDValue(E, 0); 1056 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1057 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1058 CSEMap.InsertNode(N, IP); 1059 AllNodes.push_back(N); 1060 return SDValue(N, 0); 1061} 1062 1063SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1064 FoldingSetNodeID ID; 1065 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1066 ID.AddPointer(MBB); 1067 void *IP = 0; 1068 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1069 return SDValue(E, 0); 1070 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1071 new (N) BasicBlockSDNode(MBB); 1072 CSEMap.InsertNode(N, IP); 1073 AllNodes.push_back(N); 1074 return SDValue(N, 0); 1075} 1076 1077SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1078 FoldingSetNodeID ID; 1079 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1080 ID.AddInteger(Flags.getRawBits()); 1081 void *IP = 0; 1082 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1083 return SDValue(E, 0); 1084 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1085 new (N) ARG_FLAGSSDNode(Flags); 1086 CSEMap.InsertNode(N, IP); 1087 AllNodes.push_back(N); 1088 return SDValue(N, 0); 1089} 1090 1091SDValue SelectionDAG::getValueType(MVT VT) { 1092 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1093 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1094 1095 SDNode *&N = VT.isExtended() ? 1096 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1097 1098 if (N) return SDValue(N, 0); 1099 N = NodeAllocator.Allocate<VTSDNode>(); 1100 new (N) VTSDNode(VT); 1101 AllNodes.push_back(N); 1102 return SDValue(N, 0); 1103} 1104 1105SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1106 SDNode *&N = ExternalSymbols[Sym]; 1107 if (N) return SDValue(N, 0); 1108 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1109 new (N) ExternalSymbolSDNode(false, Sym, VT); 1110 AllNodes.push_back(N); 1111 return SDValue(N, 0); 1112} 1113 1114SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1115 SDNode *&N = TargetExternalSymbols[Sym]; 1116 if (N) return SDValue(N, 0); 1117 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1118 new (N) ExternalSymbolSDNode(true, Sym, VT); 1119 AllNodes.push_back(N); 1120 return SDValue(N, 0); 1121} 1122 1123SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1124 if ((unsigned)Cond >= CondCodeNodes.size()) 1125 CondCodeNodes.resize(Cond+1); 1126 1127 if (CondCodeNodes[Cond] == 0) { 1128 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1129 new (N) CondCodeSDNode(Cond); 1130 CondCodeNodes[Cond] = N; 1131 AllNodes.push_back(N); 1132 } 1133 return SDValue(CondCodeNodes[Cond], 0); 1134} 1135 1136// commuteShuffle - swaps the values of N1 and N2, and swaps all indices in 1137// the shuffle mask M that point at N1 to point at N2, and indices that point 1138// N2 to point at N1. 1139static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) { 1140 std::swap(N1, N2); 1141 int NElts = M.size(); 1142 for (int i = 0; i != NElts; ++i) { 1143 if (M[i] >= NElts) 1144 M[i] -= NElts; 1145 else if (M[i] >= 0) 1146 M[i] += NElts; 1147 } 1148} 1149 1150SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1, 1151 SDValue N2, const int *Mask) { 1152 assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE"); 1153 assert(VT.isVector() && N1.getValueType().isVector() && 1154 "Vector Shuffle VTs must be a vectors"); 1155 assert(VT.getVectorElementType() == N1.getValueType().getVectorElementType() 1156 && "Vector Shuffle VTs must have same element type"); 1157 1158 // Canonicalize shuffle undef, undef -> undef 1159 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF) 1160 return N1; 1161 1162 // Validate that all indices in Mask are within the range of the elements 1163 // input to the shuffle. 1164 unsigned NElts = VT.getVectorNumElements(); 1165 SmallVector<int, 8> MaskVec; 1166 for (unsigned i = 0; i != NElts; ++i) { 1167 assert(Mask[i] < (int)(NElts * 2) && "Index out of range"); 1168 MaskVec.push_back(Mask[i]); 1169 } 1170 1171 // Canonicalize shuffle v, v -> v, undef 1172 if (N1 == N2) { 1173 N2 = getUNDEF(VT); 1174 for (unsigned i = 0; i != NElts; ++i) 1175 if (MaskVec[i] >= (int)NElts) MaskVec[i] -= NElts; 1176 } 1177 1178 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 1179 if (N1.getOpcode() == ISD::UNDEF) 1180 commuteShuffle(N1, N2, MaskVec); 1181 1182 // Canonicalize all index into lhs, -> shuffle lhs, undef 1183 // Canonicalize all index into rhs, -> shuffle rhs, undef 1184 bool AllLHS = true, AllRHS = true; 1185 bool N2Undef = N2.getOpcode() == ISD::UNDEF; 1186 for (unsigned i = 0; i != NElts; ++i) { 1187 if (MaskVec[i] >= (int)NElts) { 1188 if (N2Undef) 1189 MaskVec[i] = -1; 1190 else 1191 AllLHS = false; 1192 } else if (MaskVec[i] >= 0) { 1193 AllRHS = false; 1194 } 1195 } 1196 if (AllLHS && AllRHS) 1197 return getUNDEF(VT); 1198 if (AllLHS && !N2Undef) 1199 N2 = getUNDEF(VT); 1200 if (AllRHS) { 1201 N1 = getUNDEF(VT); 1202 commuteShuffle(N1, N2, MaskVec); 1203 } 1204 1205 // If Identity shuffle, or all shuffle in to undef, return that node. 1206 bool AllUndef = true; 1207 bool Identity = true; 1208 for (unsigned i = 0; i != NElts; ++i) { 1209 if (MaskVec[i] >= 0 && MaskVec[i] != (int)i) Identity = false; 1210 if (MaskVec[i] >= 0) AllUndef = false; 1211 } 1212 if (Identity) 1213 return N1; 1214 if (AllUndef) 1215 return getUNDEF(VT); 1216 1217 FoldingSetNodeID ID; 1218 SDValue Ops[2] = { N1, N2 }; 1219 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2); 1220 for (unsigned i = 0; i != NElts; ++i) 1221 ID.AddInteger(MaskVec[i]); 1222 1223 void* IP = 0; 1224 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1225 return SDValue(E, 0); 1226 1227 // Allocate the mask array for the node out of the BumpPtrAllocator, since 1228 // SDNode doesn't have access to it. This memory will be "leaked" when 1229 // the node is deallocated, but recovered when the NodeAllocator is released. 1230 int *MaskAlloc = OperandAllocator.Allocate<int>(NElts); 1231 memcpy(MaskAlloc, &MaskVec[0], NElts * sizeof(int)); 1232 1233 ShuffleVectorSDNode *N = NodeAllocator.Allocate<ShuffleVectorSDNode>(); 1234 new (N) ShuffleVectorSDNode(VT, dl, N1, N2, MaskAlloc); 1235 CSEMap.InsertNode(N, IP); 1236 AllNodes.push_back(N); 1237 return SDValue(N, 0); 1238} 1239 1240SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl, 1241 SDValue Val, SDValue DTy, 1242 SDValue STy, SDValue Rnd, SDValue Sat, 1243 ISD::CvtCode Code) { 1244 // If the src and dest types are the same and the conversion is between 1245 // integer types of the same sign or two floats, no conversion is necessary. 1246 if (DTy == STy && 1247 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF)) 1248 return Val; 1249 1250 FoldingSetNodeID ID; 1251 void* IP = 0; 1252 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1253 return SDValue(E, 0); 1254 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1255 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1256 new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code); 1257 CSEMap.InsertNode(N, IP); 1258 AllNodes.push_back(N); 1259 return SDValue(N, 0); 1260} 1261 1262SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1263 FoldingSetNodeID ID; 1264 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1265 ID.AddInteger(RegNo); 1266 void *IP = 0; 1267 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1268 return SDValue(E, 0); 1269 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1270 new (N) RegisterSDNode(RegNo, VT); 1271 CSEMap.InsertNode(N, IP); 1272 AllNodes.push_back(N); 1273 return SDValue(N, 0); 1274} 1275 1276SDValue SelectionDAG::getDbgStopPoint(DebugLoc DL, SDValue Root, 1277 unsigned Line, unsigned Col, 1278 Value *CU) { 1279 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1280 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1281 N->setDebugLoc(DL); 1282 AllNodes.push_back(N); 1283 return SDValue(N, 0); 1284} 1285 1286SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, 1287 SDValue Root, 1288 unsigned LabelID) { 1289 FoldingSetNodeID ID; 1290 SDValue Ops[] = { Root }; 1291 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1292 ID.AddInteger(LabelID); 1293 void *IP = 0; 1294 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1295 return SDValue(E, 0); 1296 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1297 new (N) LabelSDNode(Opcode, dl, Root, LabelID); 1298 CSEMap.InsertNode(N, IP); 1299 AllNodes.push_back(N); 1300 return SDValue(N, 0); 1301} 1302 1303SDValue SelectionDAG::getSrcValue(const Value *V) { 1304 assert((!V || isa<PointerType>(V->getType())) && 1305 "SrcValue is not a pointer?"); 1306 1307 FoldingSetNodeID ID; 1308 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1309 ID.AddPointer(V); 1310 1311 void *IP = 0; 1312 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1313 return SDValue(E, 0); 1314 1315 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1316 new (N) SrcValueSDNode(V); 1317 CSEMap.InsertNode(N, IP); 1318 AllNodes.push_back(N); 1319 return SDValue(N, 0); 1320} 1321 1322SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1323#ifndef NDEBUG 1324 const Value *v = MO.getValue(); 1325 assert((!v || isa<PointerType>(v->getType())) && 1326 "SrcValue is not a pointer?"); 1327#endif 1328 1329 FoldingSetNodeID ID; 1330 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1331 MO.Profile(ID); 1332 1333 void *IP = 0; 1334 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1335 return SDValue(E, 0); 1336 1337 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1338 new (N) MemOperandSDNode(MO); 1339 CSEMap.InsertNode(N, IP); 1340 AllNodes.push_back(N); 1341 return SDValue(N, 0); 1342} 1343 1344/// getShiftAmountOperand - Return the specified value casted to 1345/// the target's desired shift amount type. 1346SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { 1347 MVT OpTy = Op.getValueType(); 1348 MVT ShTy = TLI.getShiftAmountTy(); 1349 if (OpTy == ShTy || OpTy.isVector()) return Op; 1350 1351 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1352 return getNode(Opcode, Op.getDebugLoc(), ShTy, Op); 1353} 1354 1355/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1356/// specified value type. 1357SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1358 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1359 unsigned ByteSize = VT.getStoreSizeInBits()/8; 1360 const Type *Ty = VT.getTypeForMVT(); 1361 unsigned StackAlign = 1362 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1363 1364 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1365 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1366} 1367 1368/// CreateStackTemporary - Create a stack temporary suitable for holding 1369/// either of the specified value types. 1370SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) { 1371 unsigned Bytes = std::max(VT1.getStoreSizeInBits(), 1372 VT2.getStoreSizeInBits())/8; 1373 const Type *Ty1 = VT1.getTypeForMVT(); 1374 const Type *Ty2 = VT2.getTypeForMVT(); 1375 const TargetData *TD = TLI.getTargetData(); 1376 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1), 1377 TD->getPrefTypeAlignment(Ty2)); 1378 1379 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1380 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align); 1381 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1382} 1383 1384SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1385 SDValue N2, ISD::CondCode Cond, DebugLoc dl) { 1386 // These setcc operations always fold. 1387 switch (Cond) { 1388 default: break; 1389 case ISD::SETFALSE: 1390 case ISD::SETFALSE2: return getConstant(0, VT); 1391 case ISD::SETTRUE: 1392 case ISD::SETTRUE2: return getConstant(1, VT); 1393 1394 case ISD::SETOEQ: 1395 case ISD::SETOGT: 1396 case ISD::SETOGE: 1397 case ISD::SETOLT: 1398 case ISD::SETOLE: 1399 case ISD::SETONE: 1400 case ISD::SETO: 1401 case ISD::SETUO: 1402 case ISD::SETUEQ: 1403 case ISD::SETUNE: 1404 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1405 break; 1406 } 1407 1408 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1409 const APInt &C2 = N2C->getAPIntValue(); 1410 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1411 const APInt &C1 = N1C->getAPIntValue(); 1412 1413 switch (Cond) { 1414 default: assert(0 && "Unknown integer setcc!"); 1415 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1416 case ISD::SETNE: return getConstant(C1 != C2, VT); 1417 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1418 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1419 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1420 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1421 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1422 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1423 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1424 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1425 } 1426 } 1427 } 1428 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1429 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1430 // No compile time operations on this type yet. 1431 if (N1C->getValueType(0) == MVT::ppcf128) 1432 return SDValue(); 1433 1434 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1435 switch (Cond) { 1436 default: break; 1437 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1438 return getUNDEF(VT); 1439 // fall through 1440 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1441 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1442 return getUNDEF(VT); 1443 // fall through 1444 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1445 R==APFloat::cmpLessThan, VT); 1446 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1447 return getUNDEF(VT); 1448 // fall through 1449 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1450 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1451 return getUNDEF(VT); 1452 // fall through 1453 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1454 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1455 return getUNDEF(VT); 1456 // fall through 1457 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1458 R==APFloat::cmpEqual, VT); 1459 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1460 return getUNDEF(VT); 1461 // fall through 1462 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1463 R==APFloat::cmpEqual, VT); 1464 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1465 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1466 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1467 R==APFloat::cmpEqual, VT); 1468 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1469 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1470 R==APFloat::cmpLessThan, VT); 1471 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1472 R==APFloat::cmpUnordered, VT); 1473 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1474 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1475 } 1476 } else { 1477 // Ensure that the constant occurs on the RHS. 1478 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1479 } 1480 } 1481 1482 // Could not fold it. 1483 return SDValue(); 1484} 1485 1486/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1487/// use this predicate to simplify operations downstream. 1488bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1489 unsigned BitWidth = Op.getValueSizeInBits(); 1490 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1491} 1492 1493/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1494/// this predicate to simplify operations downstream. Mask is known to be zero 1495/// for bits that V cannot have. 1496bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1497 unsigned Depth) const { 1498 APInt KnownZero, KnownOne; 1499 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1500 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1501 return (KnownZero & Mask) == Mask; 1502} 1503 1504/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1505/// known to be either zero or one and return them in the KnownZero/KnownOne 1506/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1507/// processing. 1508void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1509 APInt &KnownZero, APInt &KnownOne, 1510 unsigned Depth) const { 1511 unsigned BitWidth = Mask.getBitWidth(); 1512 assert(BitWidth == Op.getValueType().getSizeInBits() && 1513 "Mask size mismatches value type size!"); 1514 1515 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1516 if (Depth == 6 || Mask == 0) 1517 return; // Limit search depth. 1518 1519 APInt KnownZero2, KnownOne2; 1520 1521 switch (Op.getOpcode()) { 1522 case ISD::Constant: 1523 // We know all of the bits for a constant! 1524 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1525 KnownZero = ~KnownOne & Mask; 1526 return; 1527 case ISD::AND: 1528 // If either the LHS or the RHS are Zero, the result is zero. 1529 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1530 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1531 KnownZero2, KnownOne2, Depth+1); 1532 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1533 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1534 1535 // Output known-1 bits are only known if set in both the LHS & RHS. 1536 KnownOne &= KnownOne2; 1537 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1538 KnownZero |= KnownZero2; 1539 return; 1540 case ISD::OR: 1541 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1542 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1543 KnownZero2, KnownOne2, Depth+1); 1544 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1545 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1546 1547 // Output known-0 bits are only known if clear in both the LHS & RHS. 1548 KnownZero &= KnownZero2; 1549 // Output known-1 are known to be set if set in either the LHS | RHS. 1550 KnownOne |= KnownOne2; 1551 return; 1552 case ISD::XOR: { 1553 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1554 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1555 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1556 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1557 1558 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1559 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1560 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1561 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1562 KnownZero = KnownZeroOut; 1563 return; 1564 } 1565 case ISD::MUL: { 1566 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1567 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1568 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1569 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1570 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1571 1572 // If low bits are zero in either operand, output low known-0 bits. 1573 // Also compute a conserative estimate for high known-0 bits. 1574 // More trickiness is possible, but this is sufficient for the 1575 // interesting case of alignment computation. 1576 KnownOne.clear(); 1577 unsigned TrailZ = KnownZero.countTrailingOnes() + 1578 KnownZero2.countTrailingOnes(); 1579 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1580 KnownZero2.countLeadingOnes(), 1581 BitWidth) - BitWidth; 1582 1583 TrailZ = std::min(TrailZ, BitWidth); 1584 LeadZ = std::min(LeadZ, BitWidth); 1585 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1586 APInt::getHighBitsSet(BitWidth, LeadZ); 1587 KnownZero &= Mask; 1588 return; 1589 } 1590 case ISD::UDIV: { 1591 // For the purposes of computing leading zeros we can conservatively 1592 // treat a udiv as a logical right shift by the power of 2 known to 1593 // be less than the denominator. 1594 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1595 ComputeMaskedBits(Op.getOperand(0), 1596 AllOnes, KnownZero2, KnownOne2, Depth+1); 1597 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1598 1599 KnownOne2.clear(); 1600 KnownZero2.clear(); 1601 ComputeMaskedBits(Op.getOperand(1), 1602 AllOnes, KnownZero2, KnownOne2, Depth+1); 1603 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1604 if (RHSUnknownLeadingOnes != BitWidth) 1605 LeadZ = std::min(BitWidth, 1606 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1607 1608 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1609 return; 1610 } 1611 case ISD::SELECT: 1612 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1613 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1614 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1615 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1616 1617 // Only known if known in both the LHS and RHS. 1618 KnownOne &= KnownOne2; 1619 KnownZero &= KnownZero2; 1620 return; 1621 case ISD::SELECT_CC: 1622 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1623 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1624 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1625 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1626 1627 // Only known if known in both the LHS and RHS. 1628 KnownOne &= KnownOne2; 1629 KnownZero &= KnownZero2; 1630 return; 1631 case ISD::SADDO: 1632 case ISD::UADDO: 1633 case ISD::SSUBO: 1634 case ISD::USUBO: 1635 case ISD::SMULO: 1636 case ISD::UMULO: 1637 if (Op.getResNo() != 1) 1638 return; 1639 // The boolean result conforms to getBooleanContents. Fall through. 1640 case ISD::SETCC: 1641 // If we know the result of a setcc has the top bits zero, use this info. 1642 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1643 BitWidth > 1) 1644 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1645 return; 1646 case ISD::SHL: 1647 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1648 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1649 unsigned ShAmt = SA->getZExtValue(); 1650 1651 // If the shift count is an invalid immediate, don't do anything. 1652 if (ShAmt >= BitWidth) 1653 return; 1654 1655 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1656 KnownZero, KnownOne, Depth+1); 1657 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1658 KnownZero <<= ShAmt; 1659 KnownOne <<= ShAmt; 1660 // low bits known zero. 1661 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1662 } 1663 return; 1664 case ISD::SRL: 1665 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1666 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1667 unsigned ShAmt = SA->getZExtValue(); 1668 1669 // If the shift count is an invalid immediate, don't do anything. 1670 if (ShAmt >= BitWidth) 1671 return; 1672 1673 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1674 KnownZero, KnownOne, Depth+1); 1675 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1676 KnownZero = KnownZero.lshr(ShAmt); 1677 KnownOne = KnownOne.lshr(ShAmt); 1678 1679 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1680 KnownZero |= HighBits; // High bits known zero. 1681 } 1682 return; 1683 case ISD::SRA: 1684 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1685 unsigned ShAmt = SA->getZExtValue(); 1686 1687 // If the shift count is an invalid immediate, don't do anything. 1688 if (ShAmt >= BitWidth) 1689 return; 1690 1691 APInt InDemandedMask = (Mask << ShAmt); 1692 // If any of the demanded bits are produced by the sign extension, we also 1693 // demand the input sign bit. 1694 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1695 if (HighBits.getBoolValue()) 1696 InDemandedMask |= APInt::getSignBit(BitWidth); 1697 1698 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1699 Depth+1); 1700 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1701 KnownZero = KnownZero.lshr(ShAmt); 1702 KnownOne = KnownOne.lshr(ShAmt); 1703 1704 // Handle the sign bits. 1705 APInt SignBit = APInt::getSignBit(BitWidth); 1706 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1707 1708 if (KnownZero.intersects(SignBit)) { 1709 KnownZero |= HighBits; // New bits are known zero. 1710 } else if (KnownOne.intersects(SignBit)) { 1711 KnownOne |= HighBits; // New bits are known one. 1712 } 1713 } 1714 return; 1715 case ISD::SIGN_EXTEND_INREG: { 1716 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1717 unsigned EBits = EVT.getSizeInBits(); 1718 1719 // Sign extension. Compute the demanded bits in the result that are not 1720 // present in the input. 1721 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1722 1723 APInt InSignBit = APInt::getSignBit(EBits); 1724 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1725 1726 // If the sign extended bits are demanded, we know that the sign 1727 // bit is demanded. 1728 InSignBit.zext(BitWidth); 1729 if (NewBits.getBoolValue()) 1730 InputDemandedBits |= InSignBit; 1731 1732 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1733 KnownZero, KnownOne, Depth+1); 1734 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1735 1736 // If the sign bit of the input is known set or clear, then we know the 1737 // top bits of the result. 1738 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1739 KnownZero |= NewBits; 1740 KnownOne &= ~NewBits; 1741 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1742 KnownOne |= NewBits; 1743 KnownZero &= ~NewBits; 1744 } else { // Input sign bit unknown 1745 KnownZero &= ~NewBits; 1746 KnownOne &= ~NewBits; 1747 } 1748 return; 1749 } 1750 case ISD::CTTZ: 1751 case ISD::CTLZ: 1752 case ISD::CTPOP: { 1753 unsigned LowBits = Log2_32(BitWidth)+1; 1754 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1755 KnownOne.clear(); 1756 return; 1757 } 1758 case ISD::LOAD: { 1759 if (ISD::isZEXTLoad(Op.getNode())) { 1760 LoadSDNode *LD = cast<LoadSDNode>(Op); 1761 MVT VT = LD->getMemoryVT(); 1762 unsigned MemBits = VT.getSizeInBits(); 1763 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1764 } 1765 return; 1766 } 1767 case ISD::ZERO_EXTEND: { 1768 MVT InVT = Op.getOperand(0).getValueType(); 1769 unsigned InBits = InVT.getSizeInBits(); 1770 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1771 APInt InMask = Mask; 1772 InMask.trunc(InBits); 1773 KnownZero.trunc(InBits); 1774 KnownOne.trunc(InBits); 1775 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1776 KnownZero.zext(BitWidth); 1777 KnownOne.zext(BitWidth); 1778 KnownZero |= NewBits; 1779 return; 1780 } 1781 case ISD::SIGN_EXTEND: { 1782 MVT InVT = Op.getOperand(0).getValueType(); 1783 unsigned InBits = InVT.getSizeInBits(); 1784 APInt InSignBit = APInt::getSignBit(InBits); 1785 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1786 APInt InMask = Mask; 1787 InMask.trunc(InBits); 1788 1789 // If any of the sign extended bits are demanded, we know that the sign 1790 // bit is demanded. Temporarily set this bit in the mask for our callee. 1791 if (NewBits.getBoolValue()) 1792 InMask |= InSignBit; 1793 1794 KnownZero.trunc(InBits); 1795 KnownOne.trunc(InBits); 1796 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1797 1798 // Note if the sign bit is known to be zero or one. 1799 bool SignBitKnownZero = KnownZero.isNegative(); 1800 bool SignBitKnownOne = KnownOne.isNegative(); 1801 assert(!(SignBitKnownZero && SignBitKnownOne) && 1802 "Sign bit can't be known to be both zero and one!"); 1803 1804 // If the sign bit wasn't actually demanded by our caller, we don't 1805 // want it set in the KnownZero and KnownOne result values. Reset the 1806 // mask and reapply it to the result values. 1807 InMask = Mask; 1808 InMask.trunc(InBits); 1809 KnownZero &= InMask; 1810 KnownOne &= InMask; 1811 1812 KnownZero.zext(BitWidth); 1813 KnownOne.zext(BitWidth); 1814 1815 // If the sign bit is known zero or one, the top bits match. 1816 if (SignBitKnownZero) 1817 KnownZero |= NewBits; 1818 else if (SignBitKnownOne) 1819 KnownOne |= NewBits; 1820 return; 1821 } 1822 case ISD::ANY_EXTEND: { 1823 MVT InVT = Op.getOperand(0).getValueType(); 1824 unsigned InBits = InVT.getSizeInBits(); 1825 APInt InMask = Mask; 1826 InMask.trunc(InBits); 1827 KnownZero.trunc(InBits); 1828 KnownOne.trunc(InBits); 1829 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1830 KnownZero.zext(BitWidth); 1831 KnownOne.zext(BitWidth); 1832 return; 1833 } 1834 case ISD::TRUNCATE: { 1835 MVT InVT = Op.getOperand(0).getValueType(); 1836 unsigned InBits = InVT.getSizeInBits(); 1837 APInt InMask = Mask; 1838 InMask.zext(InBits); 1839 KnownZero.zext(InBits); 1840 KnownOne.zext(InBits); 1841 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1842 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1843 KnownZero.trunc(BitWidth); 1844 KnownOne.trunc(BitWidth); 1845 break; 1846 } 1847 case ISD::AssertZext: { 1848 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1849 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1850 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1851 KnownOne, Depth+1); 1852 KnownZero |= (~InMask) & Mask; 1853 return; 1854 } 1855 case ISD::FGETSIGN: 1856 // All bits are zero except the low bit. 1857 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1858 return; 1859 1860 case ISD::SUB: { 1861 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1862 // We know that the top bits of C-X are clear if X contains less bits 1863 // than C (i.e. no wrap-around can happen). For example, 20-X is 1864 // positive if we can prove that X is >= 0 and < 16. 1865 if (CLHS->getAPIntValue().isNonNegative()) { 1866 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1867 // NLZ can't be BitWidth with no sign bit 1868 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1869 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1870 Depth+1); 1871 1872 // If all of the MaskV bits are known to be zero, then we know the 1873 // output top bits are zero, because we now know that the output is 1874 // from [0-C]. 1875 if ((KnownZero2 & MaskV) == MaskV) { 1876 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1877 // Top bits known zero. 1878 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1879 } 1880 } 1881 } 1882 } 1883 // fall through 1884 case ISD::ADD: { 1885 // Output known-0 bits are known if clear or set in both the low clear bits 1886 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1887 // low 3 bits clear. 1888 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1889 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1890 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1891 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1892 1893 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1894 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1895 KnownZeroOut = std::min(KnownZeroOut, 1896 KnownZero2.countTrailingOnes()); 1897 1898 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1899 return; 1900 } 1901 case ISD::SREM: 1902 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1903 const APInt &RA = Rem->getAPIntValue(); 1904 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1905 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1906 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1907 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1908 1909 // If the sign bit of the first operand is zero, the sign bit of 1910 // the result is zero. If the first operand has no one bits below 1911 // the second operand's single 1 bit, its sign will be zero. 1912 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1913 KnownZero2 |= ~LowBits; 1914 1915 KnownZero |= KnownZero2 & Mask; 1916 1917 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1918 } 1919 } 1920 return; 1921 case ISD::UREM: { 1922 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1923 const APInt &RA = Rem->getAPIntValue(); 1924 if (RA.isPowerOf2()) { 1925 APInt LowBits = (RA - 1); 1926 APInt Mask2 = LowBits & Mask; 1927 KnownZero |= ~LowBits & Mask; 1928 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1929 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1930 break; 1931 } 1932 } 1933 1934 // Since the result is less than or equal to either operand, any leading 1935 // zero bits in either operand must also exist in the result. 1936 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1937 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1938 Depth+1); 1939 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1940 Depth+1); 1941 1942 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1943 KnownZero2.countLeadingOnes()); 1944 KnownOne.clear(); 1945 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1946 return; 1947 } 1948 default: 1949 // Allow the target to implement this method for its nodes. 1950 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1951 case ISD::INTRINSIC_WO_CHAIN: 1952 case ISD::INTRINSIC_W_CHAIN: 1953 case ISD::INTRINSIC_VOID: 1954 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1955 } 1956 return; 1957 } 1958} 1959 1960/// ComputeNumSignBits - Return the number of times the sign bit of the 1961/// register is replicated into the other bits. We know that at least 1 bit 1962/// is always equal to the sign bit (itself), but other cases can give us 1963/// information. For example, immediately after an "SRA X, 2", we know that 1964/// the top 3 bits are all equal to each other, so we return 3. 1965unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1966 MVT VT = Op.getValueType(); 1967 assert(VT.isInteger() && "Invalid VT!"); 1968 unsigned VTBits = VT.getSizeInBits(); 1969 unsigned Tmp, Tmp2; 1970 unsigned FirstAnswer = 1; 1971 1972 if (Depth == 6) 1973 return 1; // Limit search depth. 1974 1975 switch (Op.getOpcode()) { 1976 default: break; 1977 case ISD::AssertSext: 1978 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1979 return VTBits-Tmp+1; 1980 case ISD::AssertZext: 1981 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1982 return VTBits-Tmp; 1983 1984 case ISD::Constant: { 1985 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1986 // If negative, return # leading ones. 1987 if (Val.isNegative()) 1988 return Val.countLeadingOnes(); 1989 1990 // Return # leading zeros. 1991 return Val.countLeadingZeros(); 1992 } 1993 1994 case ISD::SIGN_EXTEND: 1995 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1996 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1997 1998 case ISD::SIGN_EXTEND_INREG: 1999 // Max of the input and what this extends. 2000 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 2001 Tmp = VTBits-Tmp+1; 2002 2003 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2004 return std::max(Tmp, Tmp2); 2005 2006 case ISD::SRA: 2007 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2008 // SRA X, C -> adds C sign bits. 2009 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2010 Tmp += C->getZExtValue(); 2011 if (Tmp > VTBits) Tmp = VTBits; 2012 } 2013 return Tmp; 2014 case ISD::SHL: 2015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2016 // shl destroys sign bits. 2017 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2018 if (C->getZExtValue() >= VTBits || // Bad shift. 2019 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 2020 return Tmp - C->getZExtValue(); 2021 } 2022 break; 2023 case ISD::AND: 2024 case ISD::OR: 2025 case ISD::XOR: // NOT is handled here. 2026 // Logical binary ops preserve the number of sign bits at the worst. 2027 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2028 if (Tmp != 1) { 2029 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2030 FirstAnswer = std::min(Tmp, Tmp2); 2031 // We computed what we know about the sign bits as our first 2032 // answer. Now proceed to the generic code that uses 2033 // ComputeMaskedBits, and pick whichever answer is better. 2034 } 2035 break; 2036 2037 case ISD::SELECT: 2038 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2039 if (Tmp == 1) return 1; // Early out. 2040 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 2041 return std::min(Tmp, Tmp2); 2042 2043 case ISD::SADDO: 2044 case ISD::UADDO: 2045 case ISD::SSUBO: 2046 case ISD::USUBO: 2047 case ISD::SMULO: 2048 case ISD::UMULO: 2049 if (Op.getResNo() != 1) 2050 break; 2051 // The boolean result conforms to getBooleanContents. Fall through. 2052 case ISD::SETCC: 2053 // If setcc returns 0/-1, all bits are sign bits. 2054 if (TLI.getBooleanContents() == 2055 TargetLowering::ZeroOrNegativeOneBooleanContent) 2056 return VTBits; 2057 break; 2058 case ISD::ROTL: 2059 case ISD::ROTR: 2060 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2061 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 2062 2063 // Handle rotate right by N like a rotate left by 32-N. 2064 if (Op.getOpcode() == ISD::ROTR) 2065 RotAmt = (VTBits-RotAmt) & (VTBits-1); 2066 2067 // If we aren't rotating out all of the known-in sign bits, return the 2068 // number that are left. This handles rotl(sext(x), 1) for example. 2069 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2070 if (Tmp > RotAmt+1) return Tmp-RotAmt; 2071 } 2072 break; 2073 case ISD::ADD: 2074 // Add can have at most one carry bit. Thus we know that the output 2075 // is, at worst, one more bit than the inputs. 2076 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2077 if (Tmp == 1) return 1; // Early out. 2078 2079 // Special case decrementing a value (ADD X, -1): 2080 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 2081 if (CRHS->isAllOnesValue()) { 2082 APInt KnownZero, KnownOne; 2083 APInt Mask = APInt::getAllOnesValue(VTBits); 2084 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 2085 2086 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2087 // sign bits set. 2088 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2089 return VTBits; 2090 2091 // If we are subtracting one from a positive number, there is no carry 2092 // out of the result. 2093 if (KnownZero.isNegative()) 2094 return Tmp; 2095 } 2096 2097 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2098 if (Tmp2 == 1) return 1; 2099 return std::min(Tmp, Tmp2)-1; 2100 break; 2101 2102 case ISD::SUB: 2103 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2104 if (Tmp2 == 1) return 1; 2105 2106 // Handle NEG. 2107 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 2108 if (CLHS->isNullValue()) { 2109 APInt KnownZero, KnownOne; 2110 APInt Mask = APInt::getAllOnesValue(VTBits); 2111 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 2112 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2113 // sign bits set. 2114 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2115 return VTBits; 2116 2117 // If the input is known to be positive (the sign bit is known clear), 2118 // the output of the NEG has the same number of sign bits as the input. 2119 if (KnownZero.isNegative()) 2120 return Tmp2; 2121 2122 // Otherwise, we treat this like a SUB. 2123 } 2124 2125 // Sub can have at most one carry bit. Thus we know that the output 2126 // is, at worst, one more bit than the inputs. 2127 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2128 if (Tmp == 1) return 1; // Early out. 2129 return std::min(Tmp, Tmp2)-1; 2130 break; 2131 case ISD::TRUNCATE: 2132 // FIXME: it's tricky to do anything useful for this, but it is an important 2133 // case for targets like X86. 2134 break; 2135 } 2136 2137 // Handle LOADX separately here. EXTLOAD case will fallthrough. 2138 if (Op.getOpcode() == ISD::LOAD) { 2139 LoadSDNode *LD = cast<LoadSDNode>(Op); 2140 unsigned ExtType = LD->getExtensionType(); 2141 switch (ExtType) { 2142 default: break; 2143 case ISD::SEXTLOAD: // '17' bits known 2144 Tmp = LD->getMemoryVT().getSizeInBits(); 2145 return VTBits-Tmp+1; 2146 case ISD::ZEXTLOAD: // '16' bits known 2147 Tmp = LD->getMemoryVT().getSizeInBits(); 2148 return VTBits-Tmp; 2149 } 2150 } 2151 2152 // Allow the target to implement this method for its nodes. 2153 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2154 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2155 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2156 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2157 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2158 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2159 } 2160 2161 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2162 // use this information. 2163 APInt KnownZero, KnownOne; 2164 APInt Mask = APInt::getAllOnesValue(VTBits); 2165 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2166 2167 if (KnownZero.isNegative()) { // sign bit is 0 2168 Mask = KnownZero; 2169 } else if (KnownOne.isNegative()) { // sign bit is 1; 2170 Mask = KnownOne; 2171 } else { 2172 // Nothing known. 2173 return FirstAnswer; 2174 } 2175 2176 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2177 // the number of identical bits in the top of the input value. 2178 Mask = ~Mask; 2179 Mask <<= Mask.getBitWidth()-VTBits; 2180 // Return # leading zeros. We use 'min' here in case Val was zero before 2181 // shifting. We don't want to return '64' as for an i32 "0". 2182 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2183} 2184 2185 2186bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2187 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2188 if (!GA) return false; 2189 if (GA->getOffset() != 0) return false; 2190 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2191 if (!GV) return false; 2192 MachineModuleInfo *MMI = getMachineModuleInfo(); 2193 return MMI && MMI->hasDebugInfo(); 2194} 2195 2196 2197/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2198/// element of the result of the vector shuffle. 2199SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N, 2200 unsigned i) { 2201 MVT VT = N->getValueType(0); 2202 DebugLoc dl = N->getDebugLoc(); 2203 if (N->getMaskElt(i) < 0) 2204 return getUNDEF(VT.getVectorElementType()); 2205 unsigned Index = N->getMaskElt(i); 2206 unsigned NumElems = VT.getVectorNumElements(); 2207 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2208 Index %= NumElems; 2209 2210 if (V.getOpcode() == ISD::BIT_CONVERT) { 2211 V = V.getOperand(0); 2212 MVT VVT = V.getValueType(); 2213 if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems) 2214 return SDValue(); 2215 } 2216 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2217 return (Index == 0) ? V.getOperand(0) 2218 : getUNDEF(VT.getVectorElementType()); 2219 if (V.getOpcode() == ISD::BUILD_VECTOR) 2220 return V.getOperand(Index); 2221 if (const ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(V)) 2222 return getShuffleScalarElt(SVN, Index); 2223 return SDValue(); 2224} 2225 2226 2227/// getNode - Gets or creates the specified node. 2228/// 2229SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) { 2230 FoldingSetNodeID ID; 2231 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2232 void *IP = 0; 2233 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2234 return SDValue(E, 0); 2235 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2236 new (N) SDNode(Opcode, DL, getVTList(VT)); 2237 CSEMap.InsertNode(N, IP); 2238 2239 AllNodes.push_back(N); 2240#ifndef NDEBUG 2241 VerifyNode(N); 2242#endif 2243 return SDValue(N, 0); 2244} 2245 2246SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 2247 MVT VT, SDValue Operand) { 2248 // Constant fold unary operations with an integer constant operand. 2249 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2250 const APInt &Val = C->getAPIntValue(); 2251 unsigned BitWidth = VT.getSizeInBits(); 2252 switch (Opcode) { 2253 default: break; 2254 case ISD::SIGN_EXTEND: 2255 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2256 case ISD::ANY_EXTEND: 2257 case ISD::ZERO_EXTEND: 2258 case ISD::TRUNCATE: 2259 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2260 case ISD::UINT_TO_FP: 2261 case ISD::SINT_TO_FP: { 2262 const uint64_t zero[] = {0, 0}; 2263 // No compile time operations on this type. 2264 if (VT==MVT::ppcf128) 2265 break; 2266 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2267 (void)apf.convertFromAPInt(Val, 2268 Opcode==ISD::SINT_TO_FP, 2269 APFloat::rmNearestTiesToEven); 2270 return getConstantFP(apf, VT); 2271 } 2272 case ISD::BIT_CONVERT: 2273 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2274 return getConstantFP(Val.bitsToFloat(), VT); 2275 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2276 return getConstantFP(Val.bitsToDouble(), VT); 2277 break; 2278 case ISD::BSWAP: 2279 return getConstant(Val.byteSwap(), VT); 2280 case ISD::CTPOP: 2281 return getConstant(Val.countPopulation(), VT); 2282 case ISD::CTLZ: 2283 return getConstant(Val.countLeadingZeros(), VT); 2284 case ISD::CTTZ: 2285 return getConstant(Val.countTrailingZeros(), VT); 2286 } 2287 } 2288 2289 // Constant fold unary operations with a floating point constant operand. 2290 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2291 APFloat V = C->getValueAPF(); // make copy 2292 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2293 switch (Opcode) { 2294 case ISD::FNEG: 2295 V.changeSign(); 2296 return getConstantFP(V, VT); 2297 case ISD::FABS: 2298 V.clearSign(); 2299 return getConstantFP(V, VT); 2300 case ISD::FP_ROUND: 2301 case ISD::FP_EXTEND: { 2302 bool ignored; 2303 // This can return overflow, underflow, or inexact; we don't care. 2304 // FIXME need to be more flexible about rounding mode. 2305 (void)V.convert(*MVTToAPFloatSemantics(VT), 2306 APFloat::rmNearestTiesToEven, &ignored); 2307 return getConstantFP(V, VT); 2308 } 2309 case ISD::FP_TO_SINT: 2310 case ISD::FP_TO_UINT: { 2311 integerPart x[2]; 2312 bool ignored; 2313 assert(integerPartWidth >= 64); 2314 // FIXME need to be more flexible about rounding mode. 2315 APFloat::opStatus s = V.convertToInteger(x, VT.getSizeInBits(), 2316 Opcode==ISD::FP_TO_SINT, 2317 APFloat::rmTowardZero, &ignored); 2318 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2319 break; 2320 APInt api(VT.getSizeInBits(), 2, x); 2321 return getConstant(api, VT); 2322 } 2323 case ISD::BIT_CONVERT: 2324 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2325 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2326 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2327 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2328 break; 2329 } 2330 } 2331 } 2332 2333 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2334 switch (Opcode) { 2335 case ISD::TokenFactor: 2336 case ISD::MERGE_VALUES: 2337 case ISD::CONCAT_VECTORS: 2338 return Operand; // Factor, merge or concat of one node? No need. 2339 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2340 case ISD::FP_EXTEND: 2341 assert(VT.isFloatingPoint() && 2342 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2343 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2344 if (Operand.getOpcode() == ISD::UNDEF) 2345 return getUNDEF(VT); 2346 break; 2347 case ISD::SIGN_EXTEND: 2348 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2349 "Invalid SIGN_EXTEND!"); 2350 if (Operand.getValueType() == VT) return Operand; // noop extension 2351 assert(Operand.getValueType().bitsLT(VT) 2352 && "Invalid sext node, dst < src!"); 2353 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2354 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2355 break; 2356 case ISD::ZERO_EXTEND: 2357 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2358 "Invalid ZERO_EXTEND!"); 2359 if (Operand.getValueType() == VT) return Operand; // noop extension 2360 assert(Operand.getValueType().bitsLT(VT) 2361 && "Invalid zext node, dst < src!"); 2362 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2363 return getNode(ISD::ZERO_EXTEND, DL, VT, 2364 Operand.getNode()->getOperand(0)); 2365 break; 2366 case ISD::ANY_EXTEND: 2367 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2368 "Invalid ANY_EXTEND!"); 2369 if (Operand.getValueType() == VT) return Operand; // noop extension 2370 assert(Operand.getValueType().bitsLT(VT) 2371 && "Invalid anyext node, dst < src!"); 2372 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2373 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2374 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2375 break; 2376 case ISD::TRUNCATE: 2377 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2378 "Invalid TRUNCATE!"); 2379 if (Operand.getValueType() == VT) return Operand; // noop truncate 2380 assert(Operand.getValueType().bitsGT(VT) 2381 && "Invalid truncate node, src < dst!"); 2382 if (OpOpcode == ISD::TRUNCATE) 2383 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2384 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2385 OpOpcode == ISD::ANY_EXTEND) { 2386 // If the source is smaller than the dest, we still need an extend. 2387 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2388 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2389 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2390 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2391 else 2392 return Operand.getNode()->getOperand(0); 2393 } 2394 break; 2395 case ISD::BIT_CONVERT: 2396 // Basic sanity checking. 2397 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2398 && "Cannot BIT_CONVERT between types of different sizes!"); 2399 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2400 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2401 return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0)); 2402 if (OpOpcode == ISD::UNDEF) 2403 return getUNDEF(VT); 2404 break; 2405 case ISD::SCALAR_TO_VECTOR: 2406 assert(VT.isVector() && !Operand.getValueType().isVector() && 2407 (VT.getVectorElementType() == Operand.getValueType() || 2408 (VT.getVectorElementType().isInteger() && 2409 Operand.getValueType().isInteger() && 2410 VT.getVectorElementType().bitsLE(Operand.getValueType()))) && 2411 "Illegal SCALAR_TO_VECTOR node!"); 2412 if (OpOpcode == ISD::UNDEF) 2413 return getUNDEF(VT); 2414 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2415 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2416 isa<ConstantSDNode>(Operand.getOperand(1)) && 2417 Operand.getConstantOperandVal(1) == 0 && 2418 Operand.getOperand(0).getValueType() == VT) 2419 return Operand.getOperand(0); 2420 break; 2421 case ISD::FNEG: 2422 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 2423 if (UnsafeFPMath && OpOpcode == ISD::FSUB) 2424 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1), 2425 Operand.getNode()->getOperand(0)); 2426 if (OpOpcode == ISD::FNEG) // --X -> X 2427 return Operand.getNode()->getOperand(0); 2428 break; 2429 case ISD::FABS: 2430 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2431 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0)); 2432 break; 2433 } 2434 2435 SDNode *N; 2436 SDVTList VTs = getVTList(VT); 2437 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2438 FoldingSetNodeID ID; 2439 SDValue Ops[1] = { Operand }; 2440 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2441 void *IP = 0; 2442 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2443 return SDValue(E, 0); 2444 N = NodeAllocator.Allocate<UnarySDNode>(); 2445 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2446 CSEMap.InsertNode(N, IP); 2447 } else { 2448 N = NodeAllocator.Allocate<UnarySDNode>(); 2449 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2450 } 2451 2452 AllNodes.push_back(N); 2453#ifndef NDEBUG 2454 VerifyNode(N); 2455#endif 2456 return SDValue(N, 0); 2457} 2458 2459SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2460 MVT VT, 2461 ConstantSDNode *Cst1, 2462 ConstantSDNode *Cst2) { 2463 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2464 2465 switch (Opcode) { 2466 case ISD::ADD: return getConstant(C1 + C2, VT); 2467 case ISD::SUB: return getConstant(C1 - C2, VT); 2468 case ISD::MUL: return getConstant(C1 * C2, VT); 2469 case ISD::UDIV: 2470 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2471 break; 2472 case ISD::UREM: 2473 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2474 break; 2475 case ISD::SDIV: 2476 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2477 break; 2478 case ISD::SREM: 2479 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2480 break; 2481 case ISD::AND: return getConstant(C1 & C2, VT); 2482 case ISD::OR: return getConstant(C1 | C2, VT); 2483 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2484 case ISD::SHL: return getConstant(C1 << C2, VT); 2485 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2486 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2487 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2488 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2489 default: break; 2490 } 2491 2492 return SDValue(); 2493} 2494 2495SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2496 SDValue N1, SDValue N2) { 2497 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2498 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2499 switch (Opcode) { 2500 default: break; 2501 case ISD::TokenFactor: 2502 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2503 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2504 // Fold trivial token factors. 2505 if (N1.getOpcode() == ISD::EntryToken) return N2; 2506 if (N2.getOpcode() == ISD::EntryToken) return N1; 2507 if (N1 == N2) return N1; 2508 break; 2509 case ISD::CONCAT_VECTORS: 2510 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2511 // one big BUILD_VECTOR. 2512 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2513 N2.getOpcode() == ISD::BUILD_VECTOR) { 2514 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2515 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2516 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2517 } 2518 break; 2519 case ISD::AND: 2520 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2521 N1.getValueType() == VT && "Binary operator types must match!"); 2522 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2523 // worth handling here. 2524 if (N2C && N2C->isNullValue()) 2525 return N2; 2526 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2527 return N1; 2528 break; 2529 case ISD::OR: 2530 case ISD::XOR: 2531 case ISD::ADD: 2532 case ISD::SUB: 2533 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2534 N1.getValueType() == VT && "Binary operator types must match!"); 2535 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2536 // it's worth handling here. 2537 if (N2C && N2C->isNullValue()) 2538 return N1; 2539 break; 2540 case ISD::UDIV: 2541 case ISD::UREM: 2542 case ISD::MULHU: 2543 case ISD::MULHS: 2544 case ISD::MUL: 2545 case ISD::SDIV: 2546 case ISD::SREM: 2547 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2548 // fall through 2549 case ISD::FADD: 2550 case ISD::FSUB: 2551 case ISD::FMUL: 2552 case ISD::FDIV: 2553 case ISD::FREM: 2554 if (UnsafeFPMath) { 2555 if (Opcode == ISD::FADD) { 2556 // 0+x --> x 2557 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) 2558 if (CFP->getValueAPF().isZero()) 2559 return N2; 2560 // x+0 --> x 2561 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2562 if (CFP->getValueAPF().isZero()) 2563 return N1; 2564 } else if (Opcode == ISD::FSUB) { 2565 // x-0 --> x 2566 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2567 if (CFP->getValueAPF().isZero()) 2568 return N1; 2569 } 2570 } 2571 assert(N1.getValueType() == N2.getValueType() && 2572 N1.getValueType() == VT && "Binary operator types must match!"); 2573 break; 2574 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2575 assert(N1.getValueType() == VT && 2576 N1.getValueType().isFloatingPoint() && 2577 N2.getValueType().isFloatingPoint() && 2578 "Invalid FCOPYSIGN!"); 2579 break; 2580 case ISD::SHL: 2581 case ISD::SRA: 2582 case ISD::SRL: 2583 case ISD::ROTL: 2584 case ISD::ROTR: 2585 assert(VT == N1.getValueType() && 2586 "Shift operators return type must be the same as their first arg"); 2587 assert(VT.isInteger() && N2.getValueType().isInteger() && 2588 "Shifts only work on integers"); 2589 2590 // Always fold shifts of i1 values so the code generator doesn't need to 2591 // handle them. Since we know the size of the shift has to be less than the 2592 // size of the value, the shift/rotate count is guaranteed to be zero. 2593 if (VT == MVT::i1) 2594 return N1; 2595 break; 2596 case ISD::FP_ROUND_INREG: { 2597 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2598 assert(VT == N1.getValueType() && "Not an inreg round!"); 2599 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2600 "Cannot FP_ROUND_INREG integer types"); 2601 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2602 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2603 break; 2604 } 2605 case ISD::FP_ROUND: 2606 assert(VT.isFloatingPoint() && 2607 N1.getValueType().isFloatingPoint() && 2608 VT.bitsLE(N1.getValueType()) && 2609 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2610 if (N1.getValueType() == VT) return N1; // noop conversion. 2611 break; 2612 case ISD::AssertSext: 2613 case ISD::AssertZext: { 2614 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2615 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2616 assert(VT.isInteger() && EVT.isInteger() && 2617 "Cannot *_EXTEND_INREG FP types"); 2618 assert(EVT.bitsLE(VT) && "Not extending!"); 2619 if (VT == EVT) return N1; // noop assertion. 2620 break; 2621 } 2622 case ISD::SIGN_EXTEND_INREG: { 2623 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2624 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2625 assert(VT.isInteger() && EVT.isInteger() && 2626 "Cannot *_EXTEND_INREG FP types"); 2627 assert(EVT.bitsLE(VT) && "Not extending!"); 2628 if (EVT == VT) return N1; // Not actually extending 2629 2630 if (N1C) { 2631 APInt Val = N1C->getAPIntValue(); 2632 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2633 Val <<= Val.getBitWidth()-FromBits; 2634 Val = Val.ashr(Val.getBitWidth()-FromBits); 2635 return getConstant(Val, VT); 2636 } 2637 break; 2638 } 2639 case ISD::EXTRACT_VECTOR_ELT: 2640 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2641 if (N1.getOpcode() == ISD::UNDEF) 2642 return getUNDEF(VT); 2643 2644 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2645 // expanding copies of large vectors from registers. 2646 if (N2C && 2647 N1.getOpcode() == ISD::CONCAT_VECTORS && 2648 N1.getNumOperands() > 0) { 2649 unsigned Factor = 2650 N1.getOperand(0).getValueType().getVectorNumElements(); 2651 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, 2652 N1.getOperand(N2C->getZExtValue() / Factor), 2653 getConstant(N2C->getZExtValue() % Factor, 2654 N2.getValueType())); 2655 } 2656 2657 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2658 // expanding large vector constants. 2659 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) { 2660 SDValue Elt = N1.getOperand(N2C->getZExtValue()); 2661 if (Elt.getValueType() != VT) { 2662 // If the vector element type is not legal, the BUILD_VECTOR operands 2663 // are promoted and implicitly truncated. Make that explicit here. 2664 assert(VT.isInteger() && Elt.getValueType().isInteger() && 2665 VT.bitsLE(Elt.getValueType()) && 2666 "Bad type for BUILD_VECTOR operand"); 2667 Elt = getNode(ISD::TRUNCATE, DL, VT, Elt); 2668 } 2669 return Elt; 2670 } 2671 2672 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2673 // operations are lowered to scalars. 2674 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2675 // If the indices are the same, return the inserted element. 2676 if (N1.getOperand(2) == N2) 2677 return N1.getOperand(1); 2678 // If the indices are known different, extract the element from 2679 // the original vector. 2680 else if (isa<ConstantSDNode>(N1.getOperand(2)) && 2681 isa<ConstantSDNode>(N2)) 2682 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2); 2683 } 2684 break; 2685 case ISD::EXTRACT_ELEMENT: 2686 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2687 assert(!N1.getValueType().isVector() && !VT.isVector() && 2688 (N1.getValueType().isInteger() == VT.isInteger()) && 2689 "Wrong types for EXTRACT_ELEMENT!"); 2690 2691 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2692 // 64-bit integers into 32-bit parts. Instead of building the extract of 2693 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2694 if (N1.getOpcode() == ISD::BUILD_PAIR) 2695 return N1.getOperand(N2C->getZExtValue()); 2696 2697 // EXTRACT_ELEMENT of a constant int is also very common. 2698 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2699 unsigned ElementSize = VT.getSizeInBits(); 2700 unsigned Shift = ElementSize * N2C->getZExtValue(); 2701 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2702 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2703 } 2704 break; 2705 case ISD::EXTRACT_SUBVECTOR: 2706 if (N1.getValueType() == VT) // Trivial extraction. 2707 return N1; 2708 break; 2709 } 2710 2711 if (N1C) { 2712 if (N2C) { 2713 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2714 if (SV.getNode()) return SV; 2715 } else { // Cannonicalize constant to RHS if commutative 2716 if (isCommutativeBinOp(Opcode)) { 2717 std::swap(N1C, N2C); 2718 std::swap(N1, N2); 2719 } 2720 } 2721 } 2722 2723 // Constant fold FP operations. 2724 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2725 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2726 if (N1CFP) { 2727 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2728 // Cannonicalize constant to RHS if commutative 2729 std::swap(N1CFP, N2CFP); 2730 std::swap(N1, N2); 2731 } else if (N2CFP && VT != MVT::ppcf128) { 2732 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2733 APFloat::opStatus s; 2734 switch (Opcode) { 2735 case ISD::FADD: 2736 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2737 if (s != APFloat::opInvalidOp) 2738 return getConstantFP(V1, VT); 2739 break; 2740 case ISD::FSUB: 2741 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2742 if (s!=APFloat::opInvalidOp) 2743 return getConstantFP(V1, VT); 2744 break; 2745 case ISD::FMUL: 2746 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2747 if (s!=APFloat::opInvalidOp) 2748 return getConstantFP(V1, VT); 2749 break; 2750 case ISD::FDIV: 2751 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2752 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2753 return getConstantFP(V1, VT); 2754 break; 2755 case ISD::FREM : 2756 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2757 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2758 return getConstantFP(V1, VT); 2759 break; 2760 case ISD::FCOPYSIGN: 2761 V1.copySign(V2); 2762 return getConstantFP(V1, VT); 2763 default: break; 2764 } 2765 } 2766 } 2767 2768 // Canonicalize an UNDEF to the RHS, even over a constant. 2769 if (N1.getOpcode() == ISD::UNDEF) { 2770 if (isCommutativeBinOp(Opcode)) { 2771 std::swap(N1, N2); 2772 } else { 2773 switch (Opcode) { 2774 case ISD::FP_ROUND_INREG: 2775 case ISD::SIGN_EXTEND_INREG: 2776 case ISD::SUB: 2777 case ISD::FSUB: 2778 case ISD::FDIV: 2779 case ISD::FREM: 2780 case ISD::SRA: 2781 return N1; // fold op(undef, arg2) -> undef 2782 case ISD::UDIV: 2783 case ISD::SDIV: 2784 case ISD::UREM: 2785 case ISD::SREM: 2786 case ISD::SRL: 2787 case ISD::SHL: 2788 if (!VT.isVector()) 2789 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2790 // For vectors, we can't easily build an all zero vector, just return 2791 // the LHS. 2792 return N2; 2793 } 2794 } 2795 } 2796 2797 // Fold a bunch of operators when the RHS is undef. 2798 if (N2.getOpcode() == ISD::UNDEF) { 2799 switch (Opcode) { 2800 case ISD::XOR: 2801 if (N1.getOpcode() == ISD::UNDEF) 2802 // Handle undef ^ undef -> 0 special case. This is a common 2803 // idiom (misuse). 2804 return getConstant(0, VT); 2805 // fallthrough 2806 case ISD::ADD: 2807 case ISD::ADDC: 2808 case ISD::ADDE: 2809 case ISD::SUB: 2810 case ISD::UDIV: 2811 case ISD::SDIV: 2812 case ISD::UREM: 2813 case ISD::SREM: 2814 return N2; // fold op(arg1, undef) -> undef 2815 case ISD::FADD: 2816 case ISD::FSUB: 2817 case ISD::FMUL: 2818 case ISD::FDIV: 2819 case ISD::FREM: 2820 if (UnsafeFPMath) 2821 return N2; 2822 break; 2823 case ISD::MUL: 2824 case ISD::AND: 2825 case ISD::SRL: 2826 case ISD::SHL: 2827 if (!VT.isVector()) 2828 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2829 // For vectors, we can't easily build an all zero vector, just return 2830 // the LHS. 2831 return N1; 2832 case ISD::OR: 2833 if (!VT.isVector()) 2834 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 2835 // For vectors, we can't easily build an all one vector, just return 2836 // the LHS. 2837 return N1; 2838 case ISD::SRA: 2839 return N1; 2840 } 2841 } 2842 2843 // Memoize this node if possible. 2844 SDNode *N; 2845 SDVTList VTs = getVTList(VT); 2846 if (VT != MVT::Flag) { 2847 SDValue Ops[] = { N1, N2 }; 2848 FoldingSetNodeID ID; 2849 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2850 void *IP = 0; 2851 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2852 return SDValue(E, 0); 2853 N = NodeAllocator.Allocate<BinarySDNode>(); 2854 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2855 CSEMap.InsertNode(N, IP); 2856 } else { 2857 N = NodeAllocator.Allocate<BinarySDNode>(); 2858 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2859 } 2860 2861 AllNodes.push_back(N); 2862#ifndef NDEBUG 2863 VerifyNode(N); 2864#endif 2865 return SDValue(N, 0); 2866} 2867 2868SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2869 SDValue N1, SDValue N2, SDValue N3) { 2870 // Perform various simplifications. 2871 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2872 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2873 switch (Opcode) { 2874 case ISD::CONCAT_VECTORS: 2875 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2876 // one big BUILD_VECTOR. 2877 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2878 N2.getOpcode() == ISD::BUILD_VECTOR && 2879 N3.getOpcode() == ISD::BUILD_VECTOR) { 2880 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2881 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2882 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2883 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2884 } 2885 break; 2886 case ISD::SETCC: { 2887 // Use FoldSetCC to simplify SETCC's. 2888 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL); 2889 if (Simp.getNode()) return Simp; 2890 break; 2891 } 2892 case ISD::SELECT: 2893 if (N1C) { 2894 if (N1C->getZExtValue()) 2895 return N2; // select true, X, Y -> X 2896 else 2897 return N3; // select false, X, Y -> Y 2898 } 2899 2900 if (N2 == N3) return N2; // select C, X, X -> X 2901 break; 2902 case ISD::BRCOND: 2903 if (N2C) { 2904 if (N2C->getZExtValue()) // Unconditional branch 2905 return getNode(ISD::BR, DL, MVT::Other, N1, N3); 2906 else 2907 return N1; // Never-taken branch 2908 } 2909 break; 2910 case ISD::VECTOR_SHUFFLE: 2911 assert(0 && "should use getVectorShuffle constructor!"); 2912 break; 2913 case ISD::BIT_CONVERT: 2914 // Fold bit_convert nodes from a type to themselves. 2915 if (N1.getValueType() == VT) 2916 return N1; 2917 break; 2918 } 2919 2920 // Memoize node if it doesn't produce a flag. 2921 SDNode *N; 2922 SDVTList VTs = getVTList(VT); 2923 if (VT != MVT::Flag) { 2924 SDValue Ops[] = { N1, N2, N3 }; 2925 FoldingSetNodeID ID; 2926 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2927 void *IP = 0; 2928 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2929 return SDValue(E, 0); 2930 N = NodeAllocator.Allocate<TernarySDNode>(); 2931 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2932 CSEMap.InsertNode(N, IP); 2933 } else { 2934 N = NodeAllocator.Allocate<TernarySDNode>(); 2935 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2936 } 2937 AllNodes.push_back(N); 2938#ifndef NDEBUG 2939 VerifyNode(N); 2940#endif 2941 return SDValue(N, 0); 2942} 2943 2944SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2945 SDValue N1, SDValue N2, SDValue N3, 2946 SDValue N4) { 2947 SDValue Ops[] = { N1, N2, N3, N4 }; 2948 return getNode(Opcode, DL, VT, Ops, 4); 2949} 2950 2951SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2952 SDValue N1, SDValue N2, SDValue N3, 2953 SDValue N4, SDValue N5) { 2954 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2955 return getNode(Opcode, DL, VT, Ops, 5); 2956} 2957 2958/// getMemsetValue - Vectorized representation of the memset value 2959/// operand. 2960static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG, 2961 DebugLoc dl) { 2962 unsigned NumBits = VT.isVector() ? 2963 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2964 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2965 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2966 unsigned Shift = 8; 2967 for (unsigned i = NumBits; i > 8; i >>= 1) { 2968 Val = (Val << Shift) | Val; 2969 Shift <<= 1; 2970 } 2971 if (VT.isInteger()) 2972 return DAG.getConstant(Val, VT); 2973 return DAG.getConstantFP(APFloat(Val), VT); 2974 } 2975 2976 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2977 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); 2978 unsigned Shift = 8; 2979 for (unsigned i = NumBits; i > 8; i >>= 1) { 2980 Value = DAG.getNode(ISD::OR, dl, VT, 2981 DAG.getNode(ISD::SHL, dl, VT, Value, 2982 DAG.getConstant(Shift, 2983 TLI.getShiftAmountTy())), 2984 Value); 2985 Shift <<= 1; 2986 } 2987 2988 return Value; 2989} 2990 2991/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2992/// used when a memcpy is turned into a memset when the source is a constant 2993/// string ptr. 2994static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, 2995 const TargetLowering &TLI, 2996 std::string &Str, unsigned Offset) { 2997 // Handle vector with all elements zero. 2998 if (Str.empty()) { 2999 if (VT.isInteger()) 3000 return DAG.getConstant(0, VT); 3001 unsigned NumElts = VT.getVectorNumElements(); 3002 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 3003 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3004 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 3005 } 3006 3007 assert(!VT.isVector() && "Can't handle vector type here!"); 3008 unsigned NumBits = VT.getSizeInBits(); 3009 unsigned MSB = NumBits / 8; 3010 uint64_t Val = 0; 3011 if (TLI.isLittleEndian()) 3012 Offset = Offset + MSB - 1; 3013 for (unsigned i = 0; i != MSB; ++i) { 3014 Val = (Val << 8) | (unsigned char)Str[Offset]; 3015 Offset += TLI.isLittleEndian() ? -1 : 1; 3016 } 3017 return DAG.getConstant(Val, VT); 3018} 3019 3020/// getMemBasePlusOffset - Returns base and offset node for the 3021/// 3022static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 3023 SelectionDAG &DAG) { 3024 MVT VT = Base.getValueType(); 3025 return DAG.getNode(ISD::ADD, Base.getDebugLoc(), 3026 VT, Base, DAG.getConstant(Offset, VT)); 3027} 3028 3029/// isMemSrcFromString - Returns true if memcpy source is a string constant. 3030/// 3031static bool isMemSrcFromString(SDValue Src, std::string &Str) { 3032 unsigned SrcDelta = 0; 3033 GlobalAddressSDNode *G = NULL; 3034 if (Src.getOpcode() == ISD::GlobalAddress) 3035 G = cast<GlobalAddressSDNode>(Src); 3036 else if (Src.getOpcode() == ISD::ADD && 3037 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 3038 Src.getOperand(1).getOpcode() == ISD::Constant) { 3039 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 3040 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 3041 } 3042 if (!G) 3043 return false; 3044 3045 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 3046 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 3047 return true; 3048 3049 return false; 3050} 3051 3052/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 3053/// to replace the memset / memcpy is below the threshold. It also returns the 3054/// types of the sequence of memory ops to perform memset / memcpy. 3055static 3056bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 3057 SDValue Dst, SDValue Src, 3058 unsigned Limit, uint64_t Size, unsigned &Align, 3059 std::string &Str, bool &isSrcStr, 3060 SelectionDAG &DAG, 3061 const TargetLowering &TLI) { 3062 isSrcStr = isMemSrcFromString(Src, Str); 3063 bool isSrcConst = isa<ConstantSDNode>(Src); 3064 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 3065 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG); 3066 if (VT != MVT::iAny) { 3067 unsigned NewAlign = (unsigned) 3068 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 3069 // If source is a string constant, this will require an unaligned load. 3070 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 3071 if (Dst.getOpcode() != ISD::FrameIndex) { 3072 // Can't change destination alignment. It requires a unaligned store. 3073 if (AllowUnalign) 3074 VT = MVT::iAny; 3075 } else { 3076 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 3077 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3078 if (MFI->isFixedObjectIndex(FI)) { 3079 // Can't change destination alignment. It requires a unaligned store. 3080 if (AllowUnalign) 3081 VT = MVT::iAny; 3082 } else { 3083 // Give the stack frame object a larger alignment if needed. 3084 if (MFI->getObjectAlignment(FI) < NewAlign) 3085 MFI->setObjectAlignment(FI, NewAlign); 3086 Align = NewAlign; 3087 } 3088 } 3089 } 3090 } 3091 3092 if (VT == MVT::iAny) { 3093 if (AllowUnalign) { 3094 VT = MVT::i64; 3095 } else { 3096 switch (Align & 7) { 3097 case 0: VT = MVT::i64; break; 3098 case 4: VT = MVT::i32; break; 3099 case 2: VT = MVT::i16; break; 3100 default: VT = MVT::i8; break; 3101 } 3102 } 3103 3104 MVT LVT = MVT::i64; 3105 while (!TLI.isTypeLegal(LVT)) 3106 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 3107 assert(LVT.isInteger()); 3108 3109 if (VT.bitsGT(LVT)) 3110 VT = LVT; 3111 } 3112 3113 unsigned NumMemOps = 0; 3114 while (Size != 0) { 3115 unsigned VTSize = VT.getSizeInBits() / 8; 3116 while (VTSize > Size) { 3117 // For now, only use non-vector load / store's for the left-over pieces. 3118 if (VT.isVector()) { 3119 VT = MVT::i64; 3120 while (!TLI.isTypeLegal(VT)) 3121 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3122 VTSize = VT.getSizeInBits() / 8; 3123 } else { 3124 // This can result in a type that is not legal on the target, e.g. 3125 // 1 or 2 bytes on PPC. 3126 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3127 VTSize >>= 1; 3128 } 3129 } 3130 3131 if (++NumMemOps > Limit) 3132 return false; 3133 MemOps.push_back(VT); 3134 Size -= VTSize; 3135 } 3136 3137 return true; 3138} 3139 3140static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3141 SDValue Chain, SDValue Dst, 3142 SDValue Src, uint64_t Size, 3143 unsigned Align, bool AlwaysInline, 3144 const Value *DstSV, uint64_t DstSVOff, 3145 const Value *SrcSV, uint64_t SrcSVOff){ 3146 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3147 3148 // Expand memcpy to a series of load and store ops if the size operand falls 3149 // below a certain threshold. 3150 std::vector<MVT> MemOps; 3151 uint64_t Limit = -1ULL; 3152 if (!AlwaysInline) 3153 Limit = TLI.getMaxStoresPerMemcpy(); 3154 unsigned DstAlign = Align; // Destination alignment can change. 3155 std::string Str; 3156 bool CopyFromStr; 3157 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3158 Str, CopyFromStr, DAG, TLI)) 3159 return SDValue(); 3160 3161 3162 bool isZeroStr = CopyFromStr && Str.empty(); 3163 SmallVector<SDValue, 8> OutChains; 3164 unsigned NumMemOps = MemOps.size(); 3165 uint64_t SrcOff = 0, DstOff = 0; 3166 for (unsigned i = 0; i < NumMemOps; i++) { 3167 MVT VT = MemOps[i]; 3168 unsigned VTSize = VT.getSizeInBits() / 8; 3169 SDValue Value, Store; 3170 3171 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 3172 // It's unlikely a store of a vector immediate can be done in a single 3173 // instruction. It would require a load from a constantpool first. 3174 // We also handle store a vector with all zero's. 3175 // FIXME: Handle other cases where store of vector immediate is done in 3176 // a single instruction. 3177 Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff); 3178 Store = DAG.getStore(Chain, dl, Value, 3179 getMemBasePlusOffset(Dst, DstOff, DAG), 3180 DstSV, DstSVOff + DstOff, false, DstAlign); 3181 } else { 3182 // The type might not be legal for the target. This should only happen 3183 // if the type is smaller than a legal type, as on PPC, so the right 3184 // thing to do is generate a LoadExt/StoreTrunc pair. 3185 // FIXME does the case above also need this? 3186 if (TLI.isTypeLegal(VT)) { 3187 Value = DAG.getLoad(VT, dl, Chain, 3188 getMemBasePlusOffset(Src, SrcOff, DAG), 3189 SrcSV, SrcSVOff + SrcOff, false, Align); 3190 Store = DAG.getStore(Chain, dl, Value, 3191 getMemBasePlusOffset(Dst, DstOff, DAG), 3192 DstSV, DstSVOff + DstOff, false, DstAlign); 3193 } else { 3194 MVT NVT = VT; 3195 while (!TLI.isTypeLegal(NVT)) { 3196 NVT = (MVT::SimpleValueType(NVT.getSimpleVT() + 1)); 3197 } 3198 Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain, 3199 getMemBasePlusOffset(Src, SrcOff, DAG), 3200 SrcSV, SrcSVOff + SrcOff, VT, false, Align); 3201 Store = DAG.getTruncStore(Chain, dl, Value, 3202 getMemBasePlusOffset(Dst, DstOff, DAG), 3203 DstSV, DstSVOff + DstOff, VT, false, DstAlign); 3204 } 3205 } 3206 OutChains.push_back(Store); 3207 SrcOff += VTSize; 3208 DstOff += VTSize; 3209 } 3210 3211 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3212 &OutChains[0], OutChains.size()); 3213} 3214 3215static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3216 SDValue Chain, SDValue Dst, 3217 SDValue Src, uint64_t Size, 3218 unsigned Align, bool AlwaysInline, 3219 const Value *DstSV, uint64_t DstSVOff, 3220 const Value *SrcSV, uint64_t SrcSVOff){ 3221 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3222 3223 // Expand memmove to a series of load and store ops if the size operand falls 3224 // below a certain threshold. 3225 std::vector<MVT> MemOps; 3226 uint64_t Limit = -1ULL; 3227 if (!AlwaysInline) 3228 Limit = TLI.getMaxStoresPerMemmove(); 3229 unsigned DstAlign = Align; // Destination alignment can change. 3230 std::string Str; 3231 bool CopyFromStr; 3232 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3233 Str, CopyFromStr, DAG, TLI)) 3234 return SDValue(); 3235 3236 uint64_t SrcOff = 0, DstOff = 0; 3237 3238 SmallVector<SDValue, 8> LoadValues; 3239 SmallVector<SDValue, 8> LoadChains; 3240 SmallVector<SDValue, 8> OutChains; 3241 unsigned NumMemOps = MemOps.size(); 3242 for (unsigned i = 0; i < NumMemOps; i++) { 3243 MVT VT = MemOps[i]; 3244 unsigned VTSize = VT.getSizeInBits() / 8; 3245 SDValue Value, Store; 3246 3247 Value = DAG.getLoad(VT, dl, Chain, 3248 getMemBasePlusOffset(Src, SrcOff, DAG), 3249 SrcSV, SrcSVOff + SrcOff, false, Align); 3250 LoadValues.push_back(Value); 3251 LoadChains.push_back(Value.getValue(1)); 3252 SrcOff += VTSize; 3253 } 3254 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3255 &LoadChains[0], LoadChains.size()); 3256 OutChains.clear(); 3257 for (unsigned i = 0; i < NumMemOps; i++) { 3258 MVT VT = MemOps[i]; 3259 unsigned VTSize = VT.getSizeInBits() / 8; 3260 SDValue Value, Store; 3261 3262 Store = DAG.getStore(Chain, dl, LoadValues[i], 3263 getMemBasePlusOffset(Dst, DstOff, DAG), 3264 DstSV, DstSVOff + DstOff, false, DstAlign); 3265 OutChains.push_back(Store); 3266 DstOff += VTSize; 3267 } 3268 3269 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3270 &OutChains[0], OutChains.size()); 3271} 3272 3273static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, 3274 SDValue Chain, SDValue Dst, 3275 SDValue Src, uint64_t Size, 3276 unsigned Align, 3277 const Value *DstSV, uint64_t DstSVOff) { 3278 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3279 3280 // Expand memset to a series of load/store ops if the size operand 3281 // falls below a certain threshold. 3282 std::vector<MVT> MemOps; 3283 std::string Str; 3284 bool CopyFromStr; 3285 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3286 Size, Align, Str, CopyFromStr, DAG, TLI)) 3287 return SDValue(); 3288 3289 SmallVector<SDValue, 8> OutChains; 3290 uint64_t DstOff = 0; 3291 3292 unsigned NumMemOps = MemOps.size(); 3293 for (unsigned i = 0; i < NumMemOps; i++) { 3294 MVT VT = MemOps[i]; 3295 unsigned VTSize = VT.getSizeInBits() / 8; 3296 SDValue Value = getMemsetValue(Src, VT, DAG, dl); 3297 SDValue Store = DAG.getStore(Chain, dl, Value, 3298 getMemBasePlusOffset(Dst, DstOff, DAG), 3299 DstSV, DstSVOff + DstOff); 3300 OutChains.push_back(Store); 3301 DstOff += VTSize; 3302 } 3303 3304 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3305 &OutChains[0], OutChains.size()); 3306} 3307 3308SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, 3309 SDValue Src, SDValue Size, 3310 unsigned Align, bool AlwaysInline, 3311 const Value *DstSV, uint64_t DstSVOff, 3312 const Value *SrcSV, uint64_t SrcSVOff) { 3313 3314 // Check to see if we should lower the memcpy to loads and stores first. 3315 // For cases within the target-specified limits, this is the best choice. 3316 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3317 if (ConstantSize) { 3318 // Memcpy with size zero? Just return the original chain. 3319 if (ConstantSize->isNullValue()) 3320 return Chain; 3321 3322 SDValue Result = 3323 getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3324 ConstantSize->getZExtValue(), 3325 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3326 if (Result.getNode()) 3327 return Result; 3328 } 3329 3330 // Then check to see if we should lower the memcpy with target-specific 3331 // code. If the target chooses to do this, this is the next best. 3332 SDValue Result = 3333 TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align, 3334 AlwaysInline, 3335 DstSV, DstSVOff, SrcSV, SrcSVOff); 3336 if (Result.getNode()) 3337 return Result; 3338 3339 // If we really need inline code and the target declined to provide it, 3340 // use a (potentially long) sequence of loads and stores. 3341 if (AlwaysInline) { 3342 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3343 return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3344 ConstantSize->getZExtValue(), Align, true, 3345 DstSV, DstSVOff, SrcSV, SrcSVOff); 3346 } 3347 3348 // Emit a library call. 3349 TargetLowering::ArgListTy Args; 3350 TargetLowering::ArgListEntry Entry; 3351 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3352 Entry.Node = Dst; Args.push_back(Entry); 3353 Entry.Node = Src; Args.push_back(Entry); 3354 Entry.Node = Size; Args.push_back(Entry); 3355 // FIXME: pass in DebugLoc 3356 std::pair<SDValue,SDValue> CallResult = 3357 TLI.LowerCallTo(Chain, Type::VoidTy, 3358 false, false, false, false, CallingConv::C, false, 3359 getExternalSymbol("memcpy", TLI.getPointerTy()), 3360 Args, *this, dl); 3361 return CallResult.second; 3362} 3363 3364SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, 3365 SDValue Src, SDValue Size, 3366 unsigned Align, 3367 const Value *DstSV, uint64_t DstSVOff, 3368 const Value *SrcSV, uint64_t SrcSVOff) { 3369 3370 // Check to see if we should lower the memmove to loads and stores first. 3371 // For cases within the target-specified limits, this is the best choice. 3372 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3373 if (ConstantSize) { 3374 // Memmove with size zero? Just return the original chain. 3375 if (ConstantSize->isNullValue()) 3376 return Chain; 3377 3378 SDValue Result = 3379 getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src, 3380 ConstantSize->getZExtValue(), 3381 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3382 if (Result.getNode()) 3383 return Result; 3384 } 3385 3386 // Then check to see if we should lower the memmove with target-specific 3387 // code. If the target chooses to do this, this is the next best. 3388 SDValue Result = 3389 TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align, 3390 DstSV, DstSVOff, SrcSV, SrcSVOff); 3391 if (Result.getNode()) 3392 return Result; 3393 3394 // Emit a library call. 3395 TargetLowering::ArgListTy Args; 3396 TargetLowering::ArgListEntry Entry; 3397 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3398 Entry.Node = Dst; Args.push_back(Entry); 3399 Entry.Node = Src; Args.push_back(Entry); 3400 Entry.Node = Size; Args.push_back(Entry); 3401 // FIXME: pass in DebugLoc 3402 std::pair<SDValue,SDValue> CallResult = 3403 TLI.LowerCallTo(Chain, Type::VoidTy, 3404 false, false, false, false, CallingConv::C, false, 3405 getExternalSymbol("memmove", TLI.getPointerTy()), 3406 Args, *this, dl); 3407 return CallResult.second; 3408} 3409 3410SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, 3411 SDValue Src, SDValue Size, 3412 unsigned Align, 3413 const Value *DstSV, uint64_t DstSVOff) { 3414 3415 // Check to see if we should lower the memset to stores first. 3416 // For cases within the target-specified limits, this is the best choice. 3417 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3418 if (ConstantSize) { 3419 // Memset with size zero? Just return the original chain. 3420 if (ConstantSize->isNullValue()) 3421 return Chain; 3422 3423 SDValue Result = 3424 getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), 3425 Align, DstSV, DstSVOff); 3426 if (Result.getNode()) 3427 return Result; 3428 } 3429 3430 // Then check to see if we should lower the memset with target-specific 3431 // code. If the target chooses to do this, this is the next best. 3432 SDValue Result = 3433 TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align, 3434 DstSV, DstSVOff); 3435 if (Result.getNode()) 3436 return Result; 3437 3438 // Emit a library call. 3439 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3440 TargetLowering::ArgListTy Args; 3441 TargetLowering::ArgListEntry Entry; 3442 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3443 Args.push_back(Entry); 3444 // Extend or truncate the argument to be an i32 value for the call. 3445 if (Src.getValueType().bitsGT(MVT::i32)) 3446 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src); 3447 else 3448 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); 3449 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3450 Args.push_back(Entry); 3451 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3452 Args.push_back(Entry); 3453 // FIXME: pass in DebugLoc 3454 std::pair<SDValue,SDValue> CallResult = 3455 TLI.LowerCallTo(Chain, Type::VoidTy, 3456 false, false, false, false, CallingConv::C, false, 3457 getExternalSymbol("memset", TLI.getPointerTy()), 3458 Args, *this, dl); 3459 return CallResult.second; 3460} 3461 3462SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3463 SDValue Chain, 3464 SDValue Ptr, SDValue Cmp, 3465 SDValue Swp, const Value* PtrVal, 3466 unsigned Alignment) { 3467 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); 3468 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3469 3470 MVT VT = Cmp.getValueType(); 3471 3472 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3473 Alignment = getMVTAlignment(MemVT); 3474 3475 SDVTList VTs = getVTList(VT, MVT::Other); 3476 FoldingSetNodeID ID; 3477 ID.AddInteger(MemVT.getRawBits()); 3478 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3479 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3480 void* IP = 0; 3481 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3482 return SDValue(E, 0); 3483 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3484 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3485 Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3486 CSEMap.InsertNode(N, IP); 3487 AllNodes.push_back(N); 3488 return SDValue(N, 0); 3489} 3490 3491SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3492 SDValue Chain, 3493 SDValue Ptr, SDValue Val, 3494 const Value* PtrVal, 3495 unsigned Alignment) { 3496 assert((Opcode == ISD::ATOMIC_LOAD_ADD || 3497 Opcode == ISD::ATOMIC_LOAD_SUB || 3498 Opcode == ISD::ATOMIC_LOAD_AND || 3499 Opcode == ISD::ATOMIC_LOAD_OR || 3500 Opcode == ISD::ATOMIC_LOAD_XOR || 3501 Opcode == ISD::ATOMIC_LOAD_NAND || 3502 Opcode == ISD::ATOMIC_LOAD_MIN || 3503 Opcode == ISD::ATOMIC_LOAD_MAX || 3504 Opcode == ISD::ATOMIC_LOAD_UMIN || 3505 Opcode == ISD::ATOMIC_LOAD_UMAX || 3506 Opcode == ISD::ATOMIC_SWAP) && 3507 "Invalid Atomic Op"); 3508 3509 MVT VT = Val.getValueType(); 3510 3511 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3512 Alignment = getMVTAlignment(MemVT); 3513 3514 SDVTList VTs = getVTList(VT, MVT::Other); 3515 FoldingSetNodeID ID; 3516 ID.AddInteger(MemVT.getRawBits()); 3517 SDValue Ops[] = {Chain, Ptr, Val}; 3518 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3519 void* IP = 0; 3520 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3521 return SDValue(E, 0); 3522 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3523 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3524 Chain, Ptr, Val, PtrVal, Alignment); 3525 CSEMap.InsertNode(N, IP); 3526 AllNodes.push_back(N); 3527 return SDValue(N, 0); 3528} 3529 3530/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3531/// Allowed to return something different (and simpler) if Simplify is true. 3532SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3533 DebugLoc dl) { 3534 if (NumOps == 1) 3535 return Ops[0]; 3536 3537 SmallVector<MVT, 4> VTs; 3538 VTs.reserve(NumOps); 3539 for (unsigned i = 0; i < NumOps; ++i) 3540 VTs.push_back(Ops[i].getValueType()); 3541 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps), 3542 Ops, NumOps); 3543} 3544 3545SDValue 3546SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, 3547 const MVT *VTs, unsigned NumVTs, 3548 const SDValue *Ops, unsigned NumOps, 3549 MVT MemVT, const Value *srcValue, int SVOff, 3550 unsigned Align, bool Vol, 3551 bool ReadMem, bool WriteMem) { 3552 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps, 3553 MemVT, srcValue, SVOff, Align, Vol, 3554 ReadMem, WriteMem); 3555} 3556 3557SDValue 3558SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, 3559 const SDValue *Ops, unsigned NumOps, 3560 MVT MemVT, const Value *srcValue, int SVOff, 3561 unsigned Align, bool Vol, 3562 bool ReadMem, bool WriteMem) { 3563 // Memoize the node unless it returns a flag. 3564 MemIntrinsicSDNode *N; 3565 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3566 FoldingSetNodeID ID; 3567 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3568 void *IP = 0; 3569 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3570 return SDValue(E, 0); 3571 3572 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3573 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3574 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3575 CSEMap.InsertNode(N, IP); 3576 } else { 3577 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3578 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3579 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3580 } 3581 AllNodes.push_back(N); 3582 return SDValue(N, 0); 3583} 3584 3585SDValue 3586SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, 3587 bool IsTailCall, bool IsInreg, SDVTList VTs, 3588 const SDValue *Operands, unsigned NumOperands) { 3589 // Do not include isTailCall in the folding set profile. 3590 FoldingSetNodeID ID; 3591 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3592 ID.AddInteger(CallingConv); 3593 ID.AddInteger(IsVarArgs); 3594 void *IP = 0; 3595 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3596 // Instead of including isTailCall in the folding set, we just 3597 // set the flag of the existing node. 3598 if (!IsTailCall) 3599 cast<CallSDNode>(E)->setNotTailCall(); 3600 return SDValue(E, 0); 3601 } 3602 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3603 new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg, 3604 VTs, Operands, NumOperands); 3605 CSEMap.InsertNode(N, IP); 3606 AllNodes.push_back(N); 3607 return SDValue(N, 0); 3608} 3609 3610SDValue 3611SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, 3612 ISD::LoadExtType ExtType, MVT VT, SDValue Chain, 3613 SDValue Ptr, SDValue Offset, 3614 const Value *SV, int SVOffset, MVT EVT, 3615 bool isVolatile, unsigned Alignment) { 3616 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3617 Alignment = getMVTAlignment(VT); 3618 3619 if (VT == EVT) { 3620 ExtType = ISD::NON_EXTLOAD; 3621 } else if (ExtType == ISD::NON_EXTLOAD) { 3622 assert(VT == EVT && "Non-extending load from different memory type!"); 3623 } else { 3624 // Extending load. 3625 if (VT.isVector()) 3626 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3627 "Invalid vector extload!"); 3628 else 3629 assert(EVT.bitsLT(VT) && 3630 "Should only be an extending load, not truncating!"); 3631 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3632 "Cannot sign/zero extend a FP/Vector load!"); 3633 assert(VT.isInteger() == EVT.isInteger() && 3634 "Cannot convert from FP to Int or Int -> FP!"); 3635 } 3636 3637 bool Indexed = AM != ISD::UNINDEXED; 3638 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3639 "Unindexed load with an offset!"); 3640 3641 SDVTList VTs = Indexed ? 3642 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3643 SDValue Ops[] = { Chain, Ptr, Offset }; 3644 FoldingSetNodeID ID; 3645 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3646 ID.AddInteger(EVT.getRawBits()); 3647 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); 3648 void *IP = 0; 3649 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3650 return SDValue(E, 0); 3651 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3652 new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset, 3653 Alignment, isVolatile); 3654 CSEMap.InsertNode(N, IP); 3655 AllNodes.push_back(N); 3656 return SDValue(N, 0); 3657} 3658 3659SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, 3660 SDValue Chain, SDValue Ptr, 3661 const Value *SV, int SVOffset, 3662 bool isVolatile, unsigned Alignment) { 3663 SDValue Undef = getUNDEF(Ptr.getValueType()); 3664 return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3665 SV, SVOffset, VT, isVolatile, Alignment); 3666} 3667 3668SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, 3669 SDValue Chain, SDValue Ptr, 3670 const Value *SV, 3671 int SVOffset, MVT EVT, 3672 bool isVolatile, unsigned Alignment) { 3673 SDValue Undef = getUNDEF(Ptr.getValueType()); 3674 return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef, 3675 SV, SVOffset, EVT, isVolatile, Alignment); 3676} 3677 3678SDValue 3679SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, 3680 SDValue Offset, ISD::MemIndexedMode AM) { 3681 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3682 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3683 "Load is already a indexed load!"); 3684 return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(), 3685 LD->getChain(), Base, Offset, LD->getSrcValue(), 3686 LD->getSrcValueOffset(), LD->getMemoryVT(), 3687 LD->isVolatile(), LD->getAlignment()); 3688} 3689 3690SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, 3691 SDValue Ptr, const Value *SV, int SVOffset, 3692 bool isVolatile, unsigned Alignment) { 3693 MVT VT = Val.getValueType(); 3694 3695 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3696 Alignment = getMVTAlignment(VT); 3697 3698 SDVTList VTs = getVTList(MVT::Other); 3699 SDValue Undef = getUNDEF(Ptr.getValueType()); 3700 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3701 FoldingSetNodeID ID; 3702 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3703 ID.AddInteger(VT.getRawBits()); 3704 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, 3705 isVolatile, Alignment)); 3706 void *IP = 0; 3707 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3708 return SDValue(E, 0); 3709 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3710 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false, 3711 VT, SV, SVOffset, Alignment, isVolatile); 3712 CSEMap.InsertNode(N, IP); 3713 AllNodes.push_back(N); 3714 return SDValue(N, 0); 3715} 3716 3717SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, 3718 SDValue Ptr, const Value *SV, 3719 int SVOffset, MVT SVT, 3720 bool isVolatile, unsigned Alignment) { 3721 MVT VT = Val.getValueType(); 3722 3723 if (VT == SVT) 3724 return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3725 3726 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3727 assert(VT.isInteger() == SVT.isInteger() && 3728 "Can't do FP-INT conversion!"); 3729 3730 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3731 Alignment = getMVTAlignment(VT); 3732 3733 SDVTList VTs = getVTList(MVT::Other); 3734 SDValue Undef = getUNDEF(Ptr.getValueType()); 3735 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3736 FoldingSetNodeID ID; 3737 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3738 ID.AddInteger(SVT.getRawBits()); 3739 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, 3740 isVolatile, Alignment)); 3741 void *IP = 0; 3742 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3743 return SDValue(E, 0); 3744 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3745 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true, 3746 SVT, SV, SVOffset, Alignment, isVolatile); 3747 CSEMap.InsertNode(N, IP); 3748 AllNodes.push_back(N); 3749 return SDValue(N, 0); 3750} 3751 3752SDValue 3753SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, 3754 SDValue Offset, ISD::MemIndexedMode AM) { 3755 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3756 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3757 "Store is already a indexed store!"); 3758 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3759 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3760 FoldingSetNodeID ID; 3761 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3762 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3763 ID.AddInteger(ST->getRawSubclassData()); 3764 void *IP = 0; 3765 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3766 return SDValue(E, 0); 3767 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3768 new (N) StoreSDNode(Ops, dl, VTs, AM, 3769 ST->isTruncatingStore(), ST->getMemoryVT(), 3770 ST->getSrcValue(), ST->getSrcValueOffset(), 3771 ST->getAlignment(), ST->isVolatile()); 3772 CSEMap.InsertNode(N, IP); 3773 AllNodes.push_back(N); 3774 return SDValue(N, 0); 3775} 3776 3777SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl, 3778 SDValue Chain, SDValue Ptr, 3779 SDValue SV) { 3780 SDValue Ops[] = { Chain, Ptr, SV }; 3781 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3); 3782} 3783 3784SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3785 const SDUse *Ops, unsigned NumOps) { 3786 switch (NumOps) { 3787 case 0: return getNode(Opcode, DL, VT); 3788 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3789 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3790 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3791 default: break; 3792 } 3793 3794 // Copy from an SDUse array into an SDValue array for use with 3795 // the regular getNode logic. 3796 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3797 return getNode(Opcode, DL, VT, &NewOps[0], NumOps); 3798} 3799 3800SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3801 const SDValue *Ops, unsigned NumOps) { 3802 switch (NumOps) { 3803 case 0: return getNode(Opcode, DL, VT); 3804 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3805 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3806 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3807 default: break; 3808 } 3809 3810 switch (Opcode) { 3811 default: break; 3812 case ISD::SELECT_CC: { 3813 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3814 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3815 "LHS and RHS of condition must have same type!"); 3816 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3817 "True and False arms of SelectCC must have same type!"); 3818 assert(Ops[2].getValueType() == VT && 3819 "select_cc node must be of same type as true and false value!"); 3820 break; 3821 } 3822 case ISD::BR_CC: { 3823 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3824 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3825 "LHS/RHS of comparison should match types!"); 3826 break; 3827 } 3828 } 3829 3830 // Memoize nodes. 3831 SDNode *N; 3832 SDVTList VTs = getVTList(VT); 3833 3834 if (VT != MVT::Flag) { 3835 FoldingSetNodeID ID; 3836 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3837 void *IP = 0; 3838 3839 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3840 return SDValue(E, 0); 3841 3842 N = NodeAllocator.Allocate<SDNode>(); 3843 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3844 CSEMap.InsertNode(N, IP); 3845 } else { 3846 N = NodeAllocator.Allocate<SDNode>(); 3847 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3848 } 3849 3850 AllNodes.push_back(N); 3851#ifndef NDEBUG 3852 VerifyNode(N); 3853#endif 3854 return SDValue(N, 0); 3855} 3856 3857SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3858 const std::vector<MVT> &ResultTys, 3859 const SDValue *Ops, unsigned NumOps) { 3860 return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()), 3861 Ops, NumOps); 3862} 3863 3864SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3865 const MVT *VTs, unsigned NumVTs, 3866 const SDValue *Ops, unsigned NumOps) { 3867 if (NumVTs == 1) 3868 return getNode(Opcode, DL, VTs[0], Ops, NumOps); 3869 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps); 3870} 3871 3872SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3873 const SDValue *Ops, unsigned NumOps) { 3874 if (VTList.NumVTs == 1) 3875 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps); 3876 3877 switch (Opcode) { 3878 // FIXME: figure out how to safely handle things like 3879 // int foo(int x) { return 1 << (x & 255); } 3880 // int bar() { return foo(256); } 3881#if 0 3882 case ISD::SRA_PARTS: 3883 case ISD::SRL_PARTS: 3884 case ISD::SHL_PARTS: 3885 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3886 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3887 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3888 else if (N3.getOpcode() == ISD::AND) 3889 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3890 // If the and is only masking out bits that cannot effect the shift, 3891 // eliminate the and. 3892 unsigned NumBits = VT.getSizeInBits()*2; 3893 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3894 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3895 } 3896 break; 3897#endif 3898 } 3899 3900 // Memoize the node unless it returns a flag. 3901 SDNode *N; 3902 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3903 FoldingSetNodeID ID; 3904 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3905 void *IP = 0; 3906 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3907 return SDValue(E, 0); 3908 if (NumOps == 1) { 3909 N = NodeAllocator.Allocate<UnarySDNode>(); 3910 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3911 } else if (NumOps == 2) { 3912 N = NodeAllocator.Allocate<BinarySDNode>(); 3913 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3914 } else if (NumOps == 3) { 3915 N = NodeAllocator.Allocate<TernarySDNode>(); 3916 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3917 } else { 3918 N = NodeAllocator.Allocate<SDNode>(); 3919 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3920 } 3921 CSEMap.InsertNode(N, IP); 3922 } else { 3923 if (NumOps == 1) { 3924 N = NodeAllocator.Allocate<UnarySDNode>(); 3925 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3926 } else if (NumOps == 2) { 3927 N = NodeAllocator.Allocate<BinarySDNode>(); 3928 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3929 } else if (NumOps == 3) { 3930 N = NodeAllocator.Allocate<TernarySDNode>(); 3931 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3932 } else { 3933 N = NodeAllocator.Allocate<SDNode>(); 3934 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3935 } 3936 } 3937 AllNodes.push_back(N); 3938#ifndef NDEBUG 3939 VerifyNode(N); 3940#endif 3941 return SDValue(N, 0); 3942} 3943 3944SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) { 3945 return getNode(Opcode, DL, VTList, 0, 0); 3946} 3947 3948SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3949 SDValue N1) { 3950 SDValue Ops[] = { N1 }; 3951 return getNode(Opcode, DL, VTList, Ops, 1); 3952} 3953 3954SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3955 SDValue N1, SDValue N2) { 3956 SDValue Ops[] = { N1, N2 }; 3957 return getNode(Opcode, DL, VTList, Ops, 2); 3958} 3959 3960SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3961 SDValue N1, SDValue N2, SDValue N3) { 3962 SDValue Ops[] = { N1, N2, N3 }; 3963 return getNode(Opcode, DL, VTList, Ops, 3); 3964} 3965 3966SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3967 SDValue N1, SDValue N2, SDValue N3, 3968 SDValue N4) { 3969 SDValue Ops[] = { N1, N2, N3, N4 }; 3970 return getNode(Opcode, DL, VTList, Ops, 4); 3971} 3972 3973SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3974 SDValue N1, SDValue N2, SDValue N3, 3975 SDValue N4, SDValue N5) { 3976 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3977 return getNode(Opcode, DL, VTList, Ops, 5); 3978} 3979 3980SDVTList SelectionDAG::getVTList(MVT VT) { 3981 return makeVTList(SDNode::getValueTypeList(VT), 1); 3982} 3983 3984SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3985 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3986 E = VTList.rend(); I != E; ++I) 3987 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3988 return *I; 3989 3990 MVT *Array = Allocator.Allocate<MVT>(2); 3991 Array[0] = VT1; 3992 Array[1] = VT2; 3993 SDVTList Result = makeVTList(Array, 2); 3994 VTList.push_back(Result); 3995 return Result; 3996} 3997 3998SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3999 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4000 E = VTList.rend(); I != E; ++I) 4001 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 4002 I->VTs[2] == VT3) 4003 return *I; 4004 4005 MVT *Array = Allocator.Allocate<MVT>(3); 4006 Array[0] = VT1; 4007 Array[1] = VT2; 4008 Array[2] = VT3; 4009 SDVTList Result = makeVTList(Array, 3); 4010 VTList.push_back(Result); 4011 return Result; 4012} 4013 4014SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { 4015 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4016 E = VTList.rend(); I != E; ++I) 4017 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 4018 I->VTs[2] == VT3 && I->VTs[3] == VT4) 4019 return *I; 4020 4021 MVT *Array = Allocator.Allocate<MVT>(3); 4022 Array[0] = VT1; 4023 Array[1] = VT2; 4024 Array[2] = VT3; 4025 Array[3] = VT4; 4026 SDVTList Result = makeVTList(Array, 4); 4027 VTList.push_back(Result); 4028 return Result; 4029} 4030 4031SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 4032 switch (NumVTs) { 4033 case 0: assert(0 && "Cannot have nodes without results!"); 4034 case 1: return getVTList(VTs[0]); 4035 case 2: return getVTList(VTs[0], VTs[1]); 4036 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 4037 default: break; 4038 } 4039 4040 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4041 E = VTList.rend(); I != E; ++I) { 4042 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 4043 continue; 4044 4045 bool NoMatch = false; 4046 for (unsigned i = 2; i != NumVTs; ++i) 4047 if (VTs[i] != I->VTs[i]) { 4048 NoMatch = true; 4049 break; 4050 } 4051 if (!NoMatch) 4052 return *I; 4053 } 4054 4055 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 4056 std::copy(VTs, VTs+NumVTs, Array); 4057 SDVTList Result = makeVTList(Array, NumVTs); 4058 VTList.push_back(Result); 4059 return Result; 4060} 4061 4062 4063/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 4064/// specified operands. If the resultant node already exists in the DAG, 4065/// this does not modify the specified node, instead it returns the node that 4066/// already exists. If the resultant node does not exist in the DAG, the 4067/// input node is returned. As a degenerate case, if you specify the same 4068/// input operands as the node already has, the input node is returned. 4069SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 4070 SDNode *N = InN.getNode(); 4071 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 4072 4073 // Check to see if there is no change. 4074 if (Op == N->getOperand(0)) return InN; 4075 4076 // See if the modified node already exists. 4077 void *InsertPos = 0; 4078 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 4079 return SDValue(Existing, InN.getResNo()); 4080 4081 // Nope it doesn't. Remove the node from its current place in the maps. 4082 if (InsertPos) 4083 if (!RemoveNodeFromCSEMaps(N)) 4084 InsertPos = 0; 4085 4086 // Now we update the operands. 4087 N->OperandList[0].set(Op); 4088 4089 // If this gets put into a CSE map, add it. 4090 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4091 return InN; 4092} 4093 4094SDValue SelectionDAG:: 4095UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 4096 SDNode *N = InN.getNode(); 4097 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 4098 4099 // Check to see if there is no change. 4100 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 4101 return InN; // No operands changed, just return the input node. 4102 4103 // See if the modified node already exists. 4104 void *InsertPos = 0; 4105 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 4106 return SDValue(Existing, InN.getResNo()); 4107 4108 // Nope it doesn't. Remove the node from its current place in the maps. 4109 if (InsertPos) 4110 if (!RemoveNodeFromCSEMaps(N)) 4111 InsertPos = 0; 4112 4113 // Now we update the operands. 4114 if (N->OperandList[0] != Op1) 4115 N->OperandList[0].set(Op1); 4116 if (N->OperandList[1] != Op2) 4117 N->OperandList[1].set(Op2); 4118 4119 // If this gets put into a CSE map, add it. 4120 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4121 return InN; 4122} 4123 4124SDValue SelectionDAG:: 4125UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 4126 SDValue Ops[] = { Op1, Op2, Op3 }; 4127 return UpdateNodeOperands(N, Ops, 3); 4128} 4129 4130SDValue SelectionDAG:: 4131UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4132 SDValue Op3, SDValue Op4) { 4133 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 4134 return UpdateNodeOperands(N, Ops, 4); 4135} 4136 4137SDValue SelectionDAG:: 4138UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4139 SDValue Op3, SDValue Op4, SDValue Op5) { 4140 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 4141 return UpdateNodeOperands(N, Ops, 5); 4142} 4143 4144SDValue SelectionDAG:: 4145UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 4146 SDNode *N = InN.getNode(); 4147 assert(N->getNumOperands() == NumOps && 4148 "Update with wrong number of operands"); 4149 4150 // Check to see if there is no change. 4151 bool AnyChange = false; 4152 for (unsigned i = 0; i != NumOps; ++i) { 4153 if (Ops[i] != N->getOperand(i)) { 4154 AnyChange = true; 4155 break; 4156 } 4157 } 4158 4159 // No operands changed, just return the input node. 4160 if (!AnyChange) return InN; 4161 4162 // See if the modified node already exists. 4163 void *InsertPos = 0; 4164 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 4165 return SDValue(Existing, InN.getResNo()); 4166 4167 // Nope it doesn't. Remove the node from its current place in the maps. 4168 if (InsertPos) 4169 if (!RemoveNodeFromCSEMaps(N)) 4170 InsertPos = 0; 4171 4172 // Now we update the operands. 4173 for (unsigned i = 0; i != NumOps; ++i) 4174 if (N->OperandList[i] != Ops[i]) 4175 N->OperandList[i].set(Ops[i]); 4176 4177 // If this gets put into a CSE map, add it. 4178 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4179 return InN; 4180} 4181 4182/// DropOperands - Release the operands and set this node to have 4183/// zero operands. 4184void SDNode::DropOperands() { 4185 // Unlike the code in MorphNodeTo that does this, we don't need to 4186 // watch for dead nodes here. 4187 for (op_iterator I = op_begin(), E = op_end(); I != E; ) { 4188 SDUse &Use = *I++; 4189 Use.set(SDValue()); 4190 } 4191} 4192 4193/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4194/// machine opcode. 4195/// 4196SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4197 MVT VT) { 4198 SDVTList VTs = getVTList(VT); 4199 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4200} 4201 4202SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4203 MVT VT, SDValue Op1) { 4204 SDVTList VTs = getVTList(VT); 4205 SDValue Ops[] = { Op1 }; 4206 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4207} 4208 4209SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4210 MVT VT, SDValue Op1, 4211 SDValue Op2) { 4212 SDVTList VTs = getVTList(VT); 4213 SDValue Ops[] = { Op1, Op2 }; 4214 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4215} 4216 4217SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4218 MVT VT, SDValue Op1, 4219 SDValue Op2, SDValue Op3) { 4220 SDVTList VTs = getVTList(VT); 4221 SDValue Ops[] = { Op1, Op2, Op3 }; 4222 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4223} 4224 4225SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4226 MVT VT, const SDValue *Ops, 4227 unsigned NumOps) { 4228 SDVTList VTs = getVTList(VT); 4229 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4230} 4231 4232SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4233 MVT VT1, MVT VT2, const SDValue *Ops, 4234 unsigned NumOps) { 4235 SDVTList VTs = getVTList(VT1, VT2); 4236 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4237} 4238 4239SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4240 MVT VT1, MVT VT2) { 4241 SDVTList VTs = getVTList(VT1, VT2); 4242 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4243} 4244 4245SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4246 MVT VT1, MVT VT2, MVT VT3, 4247 const SDValue *Ops, unsigned NumOps) { 4248 SDVTList VTs = getVTList(VT1, VT2, VT3); 4249 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4250} 4251 4252SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4253 MVT VT1, MVT VT2, MVT VT3, MVT VT4, 4254 const SDValue *Ops, unsigned NumOps) { 4255 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4256 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4257} 4258 4259SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4260 MVT VT1, MVT VT2, 4261 SDValue Op1) { 4262 SDVTList VTs = getVTList(VT1, VT2); 4263 SDValue Ops[] = { Op1 }; 4264 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4265} 4266 4267SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4268 MVT VT1, MVT VT2, 4269 SDValue Op1, SDValue Op2) { 4270 SDVTList VTs = getVTList(VT1, VT2); 4271 SDValue Ops[] = { Op1, Op2 }; 4272 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4273} 4274 4275SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4276 MVT VT1, MVT VT2, 4277 SDValue Op1, SDValue Op2, 4278 SDValue Op3) { 4279 SDVTList VTs = getVTList(VT1, VT2); 4280 SDValue Ops[] = { Op1, Op2, Op3 }; 4281 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4282} 4283 4284SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4285 MVT VT1, MVT VT2, MVT VT3, 4286 SDValue Op1, SDValue Op2, 4287 SDValue Op3) { 4288 SDVTList VTs = getVTList(VT1, VT2, VT3); 4289 SDValue Ops[] = { Op1, Op2, Op3 }; 4290 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4291} 4292 4293SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4294 SDVTList VTs, const SDValue *Ops, 4295 unsigned NumOps) { 4296 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4297} 4298 4299SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4300 MVT VT) { 4301 SDVTList VTs = getVTList(VT); 4302 return MorphNodeTo(N, Opc, VTs, 0, 0); 4303} 4304 4305SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4306 MVT VT, SDValue Op1) { 4307 SDVTList VTs = getVTList(VT); 4308 SDValue Ops[] = { Op1 }; 4309 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4310} 4311 4312SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4313 MVT VT, SDValue Op1, 4314 SDValue Op2) { 4315 SDVTList VTs = getVTList(VT); 4316 SDValue Ops[] = { Op1, Op2 }; 4317 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4318} 4319 4320SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4321 MVT VT, SDValue Op1, 4322 SDValue Op2, SDValue Op3) { 4323 SDVTList VTs = getVTList(VT); 4324 SDValue Ops[] = { Op1, Op2, Op3 }; 4325 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4326} 4327 4328SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4329 MVT VT, const SDValue *Ops, 4330 unsigned NumOps) { 4331 SDVTList VTs = getVTList(VT); 4332 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4333} 4334 4335SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4336 MVT VT1, MVT VT2, const SDValue *Ops, 4337 unsigned NumOps) { 4338 SDVTList VTs = getVTList(VT1, VT2); 4339 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4340} 4341 4342SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4343 MVT VT1, MVT VT2) { 4344 SDVTList VTs = getVTList(VT1, VT2); 4345 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4346} 4347 4348SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4349 MVT VT1, MVT VT2, MVT VT3, 4350 const SDValue *Ops, unsigned NumOps) { 4351 SDVTList VTs = getVTList(VT1, VT2, VT3); 4352 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4353} 4354 4355SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4356 MVT VT1, MVT VT2, 4357 SDValue Op1) { 4358 SDVTList VTs = getVTList(VT1, VT2); 4359 SDValue Ops[] = { Op1 }; 4360 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4361} 4362 4363SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4364 MVT VT1, MVT VT2, 4365 SDValue Op1, SDValue Op2) { 4366 SDVTList VTs = getVTList(VT1, VT2); 4367 SDValue Ops[] = { Op1, Op2 }; 4368 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4369} 4370 4371SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4372 MVT VT1, MVT VT2, 4373 SDValue Op1, SDValue Op2, 4374 SDValue Op3) { 4375 SDVTList VTs = getVTList(VT1, VT2); 4376 SDValue Ops[] = { Op1, Op2, Op3 }; 4377 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4378} 4379 4380/// MorphNodeTo - These *mutate* the specified node to have the specified 4381/// return type, opcode, and operands. 4382/// 4383/// Note that MorphNodeTo returns the resultant node. If there is already a 4384/// node of the specified opcode and operands, it returns that node instead of 4385/// the current one. Note that the DebugLoc need not be the same. 4386/// 4387/// Using MorphNodeTo is faster than creating a new node and swapping it in 4388/// with ReplaceAllUsesWith both because it often avoids allocating a new 4389/// node, and because it doesn't require CSE recalculation for any of 4390/// the node's users. 4391/// 4392SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4393 SDVTList VTs, const SDValue *Ops, 4394 unsigned NumOps) { 4395 // If an identical node already exists, use it. 4396 void *IP = 0; 4397 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4398 FoldingSetNodeID ID; 4399 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4400 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4401 return ON; 4402 } 4403 4404 if (!RemoveNodeFromCSEMaps(N)) 4405 IP = 0; 4406 4407 // Start the morphing. 4408 N->NodeType = Opc; 4409 N->ValueList = VTs.VTs; 4410 N->NumValues = VTs.NumVTs; 4411 4412 // Clear the operands list, updating used nodes to remove this from their 4413 // use list. Keep track of any operands that become dead as a result. 4414 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4415 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 4416 SDUse &Use = *I++; 4417 SDNode *Used = Use.getNode(); 4418 Use.set(SDValue()); 4419 if (Used->use_empty()) 4420 DeadNodeSet.insert(Used); 4421 } 4422 4423 // If NumOps is larger than the # of operands we currently have, reallocate 4424 // the operand list. 4425 if (NumOps > N->NumOperands) { 4426 if (N->OperandsNeedDelete) 4427 delete[] N->OperandList; 4428 4429 if (N->isMachineOpcode()) { 4430 // We're creating a final node that will live unmorphed for the 4431 // remainder of the current SelectionDAG iteration, so we can allocate 4432 // the operands directly out of a pool with no recycling metadata. 4433 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4434 N->OperandsNeedDelete = false; 4435 } else { 4436 N->OperandList = new SDUse[NumOps]; 4437 N->OperandsNeedDelete = true; 4438 } 4439 } 4440 4441 // Assign the new operands. 4442 N->NumOperands = NumOps; 4443 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4444 N->OperandList[i].setUser(N); 4445 N->OperandList[i].setInitial(Ops[i]); 4446 } 4447 4448 // Delete any nodes that are still dead after adding the uses for the 4449 // new operands. 4450 SmallVector<SDNode *, 16> DeadNodes; 4451 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4452 E = DeadNodeSet.end(); I != E; ++I) 4453 if ((*I)->use_empty()) 4454 DeadNodes.push_back(*I); 4455 RemoveDeadNodes(DeadNodes); 4456 4457 if (IP) 4458 CSEMap.InsertNode(N, IP); // Memoize the new node. 4459 return N; 4460} 4461 4462 4463/// getTargetNode - These are used for target selectors to create a new node 4464/// with specified return type(s), target opcode, and operands. 4465/// 4466/// Note that getTargetNode returns the resultant node. If there is already a 4467/// node of the specified opcode and operands, it returns that node instead of 4468/// the current one. 4469SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) { 4470 return getNode(~Opcode, dl, VT).getNode(); 4471} 4472 4473SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4474 SDValue Op1) { 4475 return getNode(~Opcode, dl, VT, Op1).getNode(); 4476} 4477 4478SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4479 SDValue Op1, SDValue Op2) { 4480 return getNode(~Opcode, dl, VT, Op1, Op2).getNode(); 4481} 4482 4483SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4484 SDValue Op1, SDValue Op2, 4485 SDValue Op3) { 4486 return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode(); 4487} 4488 4489SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4490 const SDValue *Ops, unsigned NumOps) { 4491 return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); 4492} 4493 4494SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4495 MVT VT1, MVT VT2) { 4496 SDVTList VTs = getVTList(VT1, VT2); 4497 SDValue Op; 4498 return getNode(~Opcode, dl, VTs, &Op, 0).getNode(); 4499} 4500 4501SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4502 MVT VT2, SDValue Op1) { 4503 SDVTList VTs = getVTList(VT1, VT2); 4504 return getNode(~Opcode, dl, VTs, &Op1, 1).getNode(); 4505} 4506 4507SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4508 MVT VT2, SDValue Op1, 4509 SDValue Op2) { 4510 SDVTList VTs = getVTList(VT1, VT2); 4511 SDValue Ops[] = { Op1, Op2 }; 4512 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4513} 4514 4515SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4516 MVT VT2, SDValue Op1, 4517 SDValue Op2, SDValue Op3) { 4518 SDVTList VTs = getVTList(VT1, VT2); 4519 SDValue Ops[] = { Op1, Op2, Op3 }; 4520 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4521} 4522 4523SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4524 MVT VT1, MVT VT2, 4525 const SDValue *Ops, unsigned NumOps) { 4526 SDVTList VTs = getVTList(VT1, VT2); 4527 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4528} 4529 4530SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4531 MVT VT1, MVT VT2, MVT VT3, 4532 SDValue Op1, SDValue Op2) { 4533 SDVTList VTs = getVTList(VT1, VT2, VT3); 4534 SDValue Ops[] = { Op1, Op2 }; 4535 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4536} 4537 4538SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4539 MVT VT1, MVT VT2, MVT VT3, 4540 SDValue Op1, SDValue Op2, 4541 SDValue Op3) { 4542 SDVTList VTs = getVTList(VT1, VT2, VT3); 4543 SDValue Ops[] = { Op1, Op2, Op3 }; 4544 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4545} 4546 4547SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4548 MVT VT1, MVT VT2, MVT VT3, 4549 const SDValue *Ops, unsigned NumOps) { 4550 SDVTList VTs = getVTList(VT1, VT2, VT3); 4551 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4552} 4553 4554SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4555 MVT VT2, MVT VT3, MVT VT4, 4556 const SDValue *Ops, unsigned NumOps) { 4557 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4558 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4559} 4560 4561SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4562 const std::vector<MVT> &ResultTys, 4563 const SDValue *Ops, unsigned NumOps) { 4564 return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode(); 4565} 4566 4567/// getNodeIfExists - Get the specified node if it's already available, or 4568/// else return NULL. 4569SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4570 const SDValue *Ops, unsigned NumOps) { 4571 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4572 FoldingSetNodeID ID; 4573 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4574 void *IP = 0; 4575 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4576 return E; 4577 } 4578 return NULL; 4579} 4580 4581/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4582/// This can cause recursive merging of nodes in the DAG. 4583/// 4584/// This version assumes From has a single result value. 4585/// 4586void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4587 DAGUpdateListener *UpdateListener) { 4588 SDNode *From = FromN.getNode(); 4589 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4590 "Cannot replace with this method!"); 4591 assert(From != To.getNode() && "Cannot replace uses of with self"); 4592 4593 // Iterate over all the existing uses of From. New uses will be added 4594 // to the beginning of the use list, which we avoid visiting. 4595 // This specifically avoids visiting uses of From that arise while the 4596 // replacement is happening, because any such uses would be the result 4597 // of CSE: If an existing node looks like From after one of its operands 4598 // is replaced by To, we don't want to replace of all its users with To 4599 // too. See PR3018 for more info. 4600 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4601 while (UI != UE) { 4602 SDNode *User = *UI; 4603 4604 // This node is about to morph, remove its old self from the CSE maps. 4605 RemoveNodeFromCSEMaps(User); 4606 4607 // A user can appear in a use list multiple times, and when this 4608 // happens the uses are usually next to each other in the list. 4609 // To help reduce the number of CSE recomputations, process all 4610 // the uses of this user that we can find this way. 4611 do { 4612 SDUse &Use = UI.getUse(); 4613 ++UI; 4614 Use.set(To); 4615 } while (UI != UE && *UI == User); 4616 4617 // Now that we have modified User, add it back to the CSE maps. If it 4618 // already exists there, recursively merge the results together. 4619 AddModifiedNodeToCSEMaps(User, UpdateListener); 4620 } 4621} 4622 4623/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4624/// This can cause recursive merging of nodes in the DAG. 4625/// 4626/// This version assumes that for each value of From, there is a 4627/// corresponding value in To in the same position with the same type. 4628/// 4629void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4630 DAGUpdateListener *UpdateListener) { 4631#ifndef NDEBUG 4632 for (unsigned i = 0, e = From->getNumValues(); i != e; ++i) 4633 assert((!From->hasAnyUseOfValue(i) || 4634 From->getValueType(i) == To->getValueType(i)) && 4635 "Cannot use this version of ReplaceAllUsesWith!"); 4636#endif 4637 4638 // Handle the trivial case. 4639 if (From == To) 4640 return; 4641 4642 // Iterate over just the existing users of From. See the comments in 4643 // the ReplaceAllUsesWith above. 4644 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4645 while (UI != UE) { 4646 SDNode *User = *UI; 4647 4648 // This node is about to morph, remove its old self from the CSE maps. 4649 RemoveNodeFromCSEMaps(User); 4650 4651 // A user can appear in a use list multiple times, and when this 4652 // happens the uses are usually next to each other in the list. 4653 // To help reduce the number of CSE recomputations, process all 4654 // the uses of this user that we can find this way. 4655 do { 4656 SDUse &Use = UI.getUse(); 4657 ++UI; 4658 Use.setNode(To); 4659 } while (UI != UE && *UI == User); 4660 4661 // Now that we have modified User, add it back to the CSE maps. If it 4662 // already exists there, recursively merge the results together. 4663 AddModifiedNodeToCSEMaps(User, UpdateListener); 4664 } 4665} 4666 4667/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4668/// This can cause recursive merging of nodes in the DAG. 4669/// 4670/// This version can replace From with any result values. To must match the 4671/// number and types of values returned by From. 4672void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4673 const SDValue *To, 4674 DAGUpdateListener *UpdateListener) { 4675 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4676 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4677 4678 // Iterate over just the existing users of From. See the comments in 4679 // the ReplaceAllUsesWith above. 4680 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4681 while (UI != UE) { 4682 SDNode *User = *UI; 4683 4684 // This node is about to morph, remove its old self from the CSE maps. 4685 RemoveNodeFromCSEMaps(User); 4686 4687 // A user can appear in a use list multiple times, and when this 4688 // happens the uses are usually next to each other in the list. 4689 // To help reduce the number of CSE recomputations, process all 4690 // the uses of this user that we can find this way. 4691 do { 4692 SDUse &Use = UI.getUse(); 4693 const SDValue &ToOp = To[Use.getResNo()]; 4694 ++UI; 4695 Use.set(ToOp); 4696 } while (UI != UE && *UI == User); 4697 4698 // Now that we have modified User, add it back to the CSE maps. If it 4699 // already exists there, recursively merge the results together. 4700 AddModifiedNodeToCSEMaps(User, UpdateListener); 4701 } 4702} 4703 4704/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4705/// uses of other values produced by From.getNode() alone. The Deleted 4706/// vector is handled the same way as for ReplaceAllUsesWith. 4707void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4708 DAGUpdateListener *UpdateListener){ 4709 // Handle the really simple, really trivial case efficiently. 4710 if (From == To) return; 4711 4712 // Handle the simple, trivial, case efficiently. 4713 if (From.getNode()->getNumValues() == 1) { 4714 ReplaceAllUsesWith(From, To, UpdateListener); 4715 return; 4716 } 4717 4718 // Iterate over just the existing users of From. See the comments in 4719 // the ReplaceAllUsesWith above. 4720 SDNode::use_iterator UI = From.getNode()->use_begin(), 4721 UE = From.getNode()->use_end(); 4722 while (UI != UE) { 4723 SDNode *User = *UI; 4724 bool UserRemovedFromCSEMaps = false; 4725 4726 // A user can appear in a use list multiple times, and when this 4727 // happens the uses are usually next to each other in the list. 4728 // To help reduce the number of CSE recomputations, process all 4729 // the uses of this user that we can find this way. 4730 do { 4731 SDUse &Use = UI.getUse(); 4732 4733 // Skip uses of different values from the same node. 4734 if (Use.getResNo() != From.getResNo()) { 4735 ++UI; 4736 continue; 4737 } 4738 4739 // If this node hasn't been modified yet, it's still in the CSE maps, 4740 // so remove its old self from the CSE maps. 4741 if (!UserRemovedFromCSEMaps) { 4742 RemoveNodeFromCSEMaps(User); 4743 UserRemovedFromCSEMaps = true; 4744 } 4745 4746 ++UI; 4747 Use.set(To); 4748 } while (UI != UE && *UI == User); 4749 4750 // We are iterating over all uses of the From node, so if a use 4751 // doesn't use the specific value, no changes are made. 4752 if (!UserRemovedFromCSEMaps) 4753 continue; 4754 4755 // Now that we have modified User, add it back to the CSE maps. If it 4756 // already exists there, recursively merge the results together. 4757 AddModifiedNodeToCSEMaps(User, UpdateListener); 4758 } 4759} 4760 4761namespace { 4762 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith 4763 /// to record information about a use. 4764 struct UseMemo { 4765 SDNode *User; 4766 unsigned Index; 4767 SDUse *Use; 4768 }; 4769 4770 /// operator< - Sort Memos by User. 4771 bool operator<(const UseMemo &L, const UseMemo &R) { 4772 return (intptr_t)L.User < (intptr_t)R.User; 4773 } 4774} 4775 4776/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4777/// uses of other values produced by From.getNode() alone. The same value 4778/// may appear in both the From and To list. The Deleted vector is 4779/// handled the same way as for ReplaceAllUsesWith. 4780void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4781 const SDValue *To, 4782 unsigned Num, 4783 DAGUpdateListener *UpdateListener){ 4784 // Handle the simple, trivial case efficiently. 4785 if (Num == 1) 4786 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4787 4788 // Read up all the uses and make records of them. This helps 4789 // processing new uses that are introduced during the 4790 // replacement process. 4791 SmallVector<UseMemo, 4> Uses; 4792 for (unsigned i = 0; i != Num; ++i) { 4793 unsigned FromResNo = From[i].getResNo(); 4794 SDNode *FromNode = From[i].getNode(); 4795 for (SDNode::use_iterator UI = FromNode->use_begin(), 4796 E = FromNode->use_end(); UI != E; ++UI) { 4797 SDUse &Use = UI.getUse(); 4798 if (Use.getResNo() == FromResNo) { 4799 UseMemo Memo = { *UI, i, &Use }; 4800 Uses.push_back(Memo); 4801 } 4802 } 4803 } 4804 4805 // Sort the uses, so that all the uses from a given User are together. 4806 std::sort(Uses.begin(), Uses.end()); 4807 4808 for (unsigned UseIndex = 0, UseIndexEnd = Uses.size(); 4809 UseIndex != UseIndexEnd; ) { 4810 // We know that this user uses some value of From. If it is the right 4811 // value, update it. 4812 SDNode *User = Uses[UseIndex].User; 4813 4814 // This node is about to morph, remove its old self from the CSE maps. 4815 RemoveNodeFromCSEMaps(User); 4816 4817 // The Uses array is sorted, so all the uses for a given User 4818 // are next to each other in the list. 4819 // To help reduce the number of CSE recomputations, process all 4820 // the uses of this user that we can find this way. 4821 do { 4822 unsigned i = Uses[UseIndex].Index; 4823 SDUse &Use = *Uses[UseIndex].Use; 4824 ++UseIndex; 4825 4826 Use.set(To[i]); 4827 } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User); 4828 4829 // Now that we have modified User, add it back to the CSE maps. If it 4830 // already exists there, recursively merge the results together. 4831 AddModifiedNodeToCSEMaps(User, UpdateListener); 4832 } 4833} 4834 4835/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4836/// based on their topological order. It returns the maximum id and a vector 4837/// of the SDNodes* in assigned order by reference. 4838unsigned SelectionDAG::AssignTopologicalOrder() { 4839 4840 unsigned DAGSize = 0; 4841 4842 // SortedPos tracks the progress of the algorithm. Nodes before it are 4843 // sorted, nodes after it are unsorted. When the algorithm completes 4844 // it is at the end of the list. 4845 allnodes_iterator SortedPos = allnodes_begin(); 4846 4847 // Visit all the nodes. Move nodes with no operands to the front of 4848 // the list immediately. Annotate nodes that do have operands with their 4849 // operand count. Before we do this, the Node Id fields of the nodes 4850 // may contain arbitrary values. After, the Node Id fields for nodes 4851 // before SortedPos will contain the topological sort index, and the 4852 // Node Id fields for nodes At SortedPos and after will contain the 4853 // count of outstanding operands. 4854 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4855 SDNode *N = I++; 4856 unsigned Degree = N->getNumOperands(); 4857 if (Degree == 0) { 4858 // A node with no uses, add it to the result array immediately. 4859 N->setNodeId(DAGSize++); 4860 allnodes_iterator Q = N; 4861 if (Q != SortedPos) 4862 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4863 ++SortedPos; 4864 } else { 4865 // Temporarily use the Node Id as scratch space for the degree count. 4866 N->setNodeId(Degree); 4867 } 4868 } 4869 4870 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4871 // such that by the time the end is reached all nodes will be sorted. 4872 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4873 SDNode *N = I; 4874 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4875 UI != UE; ++UI) { 4876 SDNode *P = *UI; 4877 unsigned Degree = P->getNodeId(); 4878 --Degree; 4879 if (Degree == 0) { 4880 // All of P's operands are sorted, so P may sorted now. 4881 P->setNodeId(DAGSize++); 4882 if (P != SortedPos) 4883 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4884 ++SortedPos; 4885 } else { 4886 // Update P's outstanding operand count. 4887 P->setNodeId(Degree); 4888 } 4889 } 4890 } 4891 4892 assert(SortedPos == AllNodes.end() && 4893 "Topological sort incomplete!"); 4894 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4895 "First node in topological sort is not the entry token!"); 4896 assert(AllNodes.front().getNodeId() == 0 && 4897 "First node in topological sort has non-zero id!"); 4898 assert(AllNodes.front().getNumOperands() == 0 && 4899 "First node in topological sort has operands!"); 4900 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4901 "Last node in topologic sort has unexpected id!"); 4902 assert(AllNodes.back().use_empty() && 4903 "Last node in topologic sort has users!"); 4904 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 4905 return DAGSize; 4906} 4907 4908 4909 4910//===----------------------------------------------------------------------===// 4911// SDNode Class 4912//===----------------------------------------------------------------------===// 4913 4914HandleSDNode::~HandleSDNode() { 4915 DropOperands(); 4916} 4917 4918GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4919 MVT VT, int64_t o) 4920 : SDNode(isa<GlobalVariable>(GA) && 4921 cast<GlobalVariable>(GA)->isThreadLocal() ? 4922 // Thread Local 4923 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4924 // Non Thread Local 4925 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4926 DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o) { 4927 TheGlobal = const_cast<GlobalValue*>(GA); 4928} 4929 4930MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt, 4931 const Value *srcValue, int SVO, 4932 unsigned alignment, bool vol) 4933 : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4934 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4935 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4936 assert(getAlignment() == alignment && "Alignment representation error!"); 4937 assert(isVolatile() == vol && "Volatile representation error!"); 4938} 4939 4940MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, 4941 const SDValue *Ops, 4942 unsigned NumOps, MVT memvt, const Value *srcValue, 4943 int SVO, unsigned alignment, bool vol) 4944 : SDNode(Opc, dl, VTs, Ops, NumOps), 4945 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4946 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4947 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4948 assert(getAlignment() == alignment && "Alignment representation error!"); 4949 assert(isVolatile() == vol && "Volatile representation error!"); 4950} 4951 4952/// getMemOperand - Return a MachineMemOperand object describing the memory 4953/// reference performed by this memory reference. 4954MachineMemOperand MemSDNode::getMemOperand() const { 4955 int Flags = 0; 4956 if (isa<LoadSDNode>(this)) 4957 Flags = MachineMemOperand::MOLoad; 4958 else if (isa<StoreSDNode>(this)) 4959 Flags = MachineMemOperand::MOStore; 4960 else if (isa<AtomicSDNode>(this)) { 4961 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4962 } 4963 else { 4964 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4965 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4966 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4967 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4968 } 4969 4970 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4971 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4972 4973 // Check if the memory reference references a frame index 4974 const FrameIndexSDNode *FI = 4975 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4976 if (!getSrcValue() && FI) 4977 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4978 Flags, 0, Size, getAlignment()); 4979 else 4980 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4981 Size, getAlignment()); 4982} 4983 4984/// Profile - Gather unique data for the node. 4985/// 4986void SDNode::Profile(FoldingSetNodeID &ID) const { 4987 AddNodeIDNode(ID, this); 4988} 4989 4990/// getValueTypeList - Return a pointer to the specified value type. 4991/// 4992const MVT *SDNode::getValueTypeList(MVT VT) { 4993 if (VT.isExtended()) { 4994 static std::set<MVT, MVT::compareRawBits> EVTs; 4995 return &(*EVTs.insert(VT).first); 4996 } else { 4997 static MVT VTs[MVT::LAST_VALUETYPE]; 4998 VTs[VT.getSimpleVT()] = VT; 4999 return &VTs[VT.getSimpleVT()]; 5000 } 5001} 5002 5003/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 5004/// indicated value. This method ignores uses of other values defined by this 5005/// operation. 5006bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 5007 assert(Value < getNumValues() && "Bad value!"); 5008 5009 // TODO: Only iterate over uses of a given value of the node 5010 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 5011 if (UI.getUse().getResNo() == Value) { 5012 if (NUses == 0) 5013 return false; 5014 --NUses; 5015 } 5016 } 5017 5018 // Found exactly the right number of uses? 5019 return NUses == 0; 5020} 5021 5022 5023/// hasAnyUseOfValue - Return true if there are any use of the indicated 5024/// value. This method ignores uses of other values defined by this operation. 5025bool SDNode::hasAnyUseOfValue(unsigned Value) const { 5026 assert(Value < getNumValues() && "Bad value!"); 5027 5028 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 5029 if (UI.getUse().getResNo() == Value) 5030 return true; 5031 5032 return false; 5033} 5034 5035 5036/// isOnlyUserOf - Return true if this node is the only use of N. 5037/// 5038bool SDNode::isOnlyUserOf(SDNode *N) const { 5039 bool Seen = false; 5040 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 5041 SDNode *User = *I; 5042 if (User == this) 5043 Seen = true; 5044 else 5045 return false; 5046 } 5047 5048 return Seen; 5049} 5050 5051/// isOperand - Return true if this node is an operand of N. 5052/// 5053bool SDValue::isOperandOf(SDNode *N) const { 5054 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5055 if (*this == N->getOperand(i)) 5056 return true; 5057 return false; 5058} 5059 5060bool SDNode::isOperandOf(SDNode *N) const { 5061 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 5062 if (this == N->OperandList[i].getNode()) 5063 return true; 5064 return false; 5065} 5066 5067/// reachesChainWithoutSideEffects - Return true if this operand (which must 5068/// be a chain) reaches the specified operand without crossing any 5069/// side-effecting instructions. In practice, this looks through token 5070/// factors and non-volatile loads. In order to remain efficient, this only 5071/// looks a couple of nodes in, it does not do an exhaustive search. 5072bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 5073 unsigned Depth) const { 5074 if (*this == Dest) return true; 5075 5076 // Don't search too deeply, we just want to be able to see through 5077 // TokenFactor's etc. 5078 if (Depth == 0) return false; 5079 5080 // If this is a token factor, all inputs to the TF happen in parallel. If any 5081 // of the operands of the TF reach dest, then we can do the xform. 5082 if (getOpcode() == ISD::TokenFactor) { 5083 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 5084 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 5085 return true; 5086 return false; 5087 } 5088 5089 // Loads don't have side effects, look through them. 5090 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 5091 if (!Ld->isVolatile()) 5092 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 5093 } 5094 return false; 5095} 5096 5097 5098static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 5099 SmallPtrSet<SDNode *, 32> &Visited) { 5100 if (found || !Visited.insert(N)) 5101 return; 5102 5103 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 5104 SDNode *Op = N->getOperand(i).getNode(); 5105 if (Op == P) { 5106 found = true; 5107 return; 5108 } 5109 findPredecessor(Op, P, found, Visited); 5110 } 5111} 5112 5113/// isPredecessorOf - Return true if this node is a predecessor of N. This node 5114/// is either an operand of N or it can be reached by recursively traversing 5115/// up the operands. 5116/// NOTE: this is an expensive method. Use it carefully. 5117bool SDNode::isPredecessorOf(SDNode *N) const { 5118 SmallPtrSet<SDNode *, 32> Visited; 5119 bool found = false; 5120 findPredecessor(N, this, found, Visited); 5121 return found; 5122} 5123 5124uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 5125 assert(Num < NumOperands && "Invalid child # of SDNode!"); 5126 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 5127} 5128 5129std::string SDNode::getOperationName(const SelectionDAG *G) const { 5130 switch (getOpcode()) { 5131 default: 5132 if (getOpcode() < ISD::BUILTIN_OP_END) 5133 return "<<Unknown DAG Node>>"; 5134 if (isMachineOpcode()) { 5135 if (G) 5136 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 5137 if (getMachineOpcode() < TII->getNumOpcodes()) 5138 return TII->get(getMachineOpcode()).getName(); 5139 return "<<Unknown Machine Node>>"; 5140 } 5141 if (G) { 5142 const TargetLowering &TLI = G->getTargetLoweringInfo(); 5143 const char *Name = TLI.getTargetNodeName(getOpcode()); 5144 if (Name) return Name; 5145 return "<<Unknown Target Node>>"; 5146 } 5147 return "<<Unknown Node>>"; 5148 5149#ifndef NDEBUG 5150 case ISD::DELETED_NODE: 5151 return "<<Deleted Node!>>"; 5152#endif 5153 case ISD::PREFETCH: return "Prefetch"; 5154 case ISD::MEMBARRIER: return "MemBarrier"; 5155 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 5156 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 5157 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 5158 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 5159 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; 5160 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; 5161 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor"; 5162 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand"; 5163 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin"; 5164 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; 5165 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; 5166 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; 5167 case ISD::PCMARKER: return "PCMarker"; 5168 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5169 case ISD::SRCVALUE: return "SrcValue"; 5170 case ISD::MEMOPERAND: return "MemOperand"; 5171 case ISD::EntryToken: return "EntryToken"; 5172 case ISD::TokenFactor: return "TokenFactor"; 5173 case ISD::AssertSext: return "AssertSext"; 5174 case ISD::AssertZext: return "AssertZext"; 5175 5176 case ISD::BasicBlock: return "BasicBlock"; 5177 case ISD::ARG_FLAGS: return "ArgFlags"; 5178 case ISD::VALUETYPE: return "ValueType"; 5179 case ISD::Register: return "Register"; 5180 5181 case ISD::Constant: return "Constant"; 5182 case ISD::ConstantFP: return "ConstantFP"; 5183 case ISD::GlobalAddress: return "GlobalAddress"; 5184 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5185 case ISD::FrameIndex: return "FrameIndex"; 5186 case ISD::JumpTable: return "JumpTable"; 5187 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5188 case ISD::RETURNADDR: return "RETURNADDR"; 5189 case ISD::FRAMEADDR: return "FRAMEADDR"; 5190 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5191 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5192 case ISD::EHSELECTION: return "EHSELECTION"; 5193 case ISD::EH_RETURN: return "EH_RETURN"; 5194 case ISD::ConstantPool: return "ConstantPool"; 5195 case ISD::ExternalSymbol: return "ExternalSymbol"; 5196 case ISD::INTRINSIC_WO_CHAIN: { 5197 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5198 return Intrinsic::getName((Intrinsic::ID)IID); 5199 } 5200 case ISD::INTRINSIC_VOID: 5201 case ISD::INTRINSIC_W_CHAIN: { 5202 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5203 return Intrinsic::getName((Intrinsic::ID)IID); 5204 } 5205 5206 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5207 case ISD::TargetConstant: return "TargetConstant"; 5208 case ISD::TargetConstantFP:return "TargetConstantFP"; 5209 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5210 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5211 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5212 case ISD::TargetJumpTable: return "TargetJumpTable"; 5213 case ISD::TargetConstantPool: return "TargetConstantPool"; 5214 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5215 5216 case ISD::CopyToReg: return "CopyToReg"; 5217 case ISD::CopyFromReg: return "CopyFromReg"; 5218 case ISD::UNDEF: return "undef"; 5219 case ISD::MERGE_VALUES: return "merge_values"; 5220 case ISD::INLINEASM: return "inlineasm"; 5221 case ISD::DBG_LABEL: return "dbg_label"; 5222 case ISD::EH_LABEL: return "eh_label"; 5223 case ISD::DECLARE: return "declare"; 5224 case ISD::HANDLENODE: return "handlenode"; 5225 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5226 case ISD::CALL: return "call"; 5227 5228 // Unary operators 5229 case ISD::FABS: return "fabs"; 5230 case ISD::FNEG: return "fneg"; 5231 case ISD::FSQRT: return "fsqrt"; 5232 case ISD::FSIN: return "fsin"; 5233 case ISD::FCOS: return "fcos"; 5234 case ISD::FPOWI: return "fpowi"; 5235 case ISD::FPOW: return "fpow"; 5236 case ISD::FTRUNC: return "ftrunc"; 5237 case ISD::FFLOOR: return "ffloor"; 5238 case ISD::FCEIL: return "fceil"; 5239 case ISD::FRINT: return "frint"; 5240 case ISD::FNEARBYINT: return "fnearbyint"; 5241 5242 // Binary operators 5243 case ISD::ADD: return "add"; 5244 case ISD::SUB: return "sub"; 5245 case ISD::MUL: return "mul"; 5246 case ISD::MULHU: return "mulhu"; 5247 case ISD::MULHS: return "mulhs"; 5248 case ISD::SDIV: return "sdiv"; 5249 case ISD::UDIV: return "udiv"; 5250 case ISD::SREM: return "srem"; 5251 case ISD::UREM: return "urem"; 5252 case ISD::SMUL_LOHI: return "smul_lohi"; 5253 case ISD::UMUL_LOHI: return "umul_lohi"; 5254 case ISD::SDIVREM: return "sdivrem"; 5255 case ISD::UDIVREM: return "udivrem"; 5256 case ISD::AND: return "and"; 5257 case ISD::OR: return "or"; 5258 case ISD::XOR: return "xor"; 5259 case ISD::SHL: return "shl"; 5260 case ISD::SRA: return "sra"; 5261 case ISD::SRL: return "srl"; 5262 case ISD::ROTL: return "rotl"; 5263 case ISD::ROTR: return "rotr"; 5264 case ISD::FADD: return "fadd"; 5265 case ISD::FSUB: return "fsub"; 5266 case ISD::FMUL: return "fmul"; 5267 case ISD::FDIV: return "fdiv"; 5268 case ISD::FREM: return "frem"; 5269 case ISD::FCOPYSIGN: return "fcopysign"; 5270 case ISD::FGETSIGN: return "fgetsign"; 5271 5272 case ISD::SETCC: return "setcc"; 5273 case ISD::VSETCC: return "vsetcc"; 5274 case ISD::SELECT: return "select"; 5275 case ISD::SELECT_CC: return "select_cc"; 5276 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5277 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5278 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5279 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5280 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5281 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5282 case ISD::CARRY_FALSE: return "carry_false"; 5283 case ISD::ADDC: return "addc"; 5284 case ISD::ADDE: return "adde"; 5285 case ISD::SADDO: return "saddo"; 5286 case ISD::UADDO: return "uaddo"; 5287 case ISD::SSUBO: return "ssubo"; 5288 case ISD::USUBO: return "usubo"; 5289 case ISD::SMULO: return "smulo"; 5290 case ISD::UMULO: return "umulo"; 5291 case ISD::SUBC: return "subc"; 5292 case ISD::SUBE: return "sube"; 5293 case ISD::SHL_PARTS: return "shl_parts"; 5294 case ISD::SRA_PARTS: return "sra_parts"; 5295 case ISD::SRL_PARTS: return "srl_parts"; 5296 5297 // Conversion operators. 5298 case ISD::SIGN_EXTEND: return "sign_extend"; 5299 case ISD::ZERO_EXTEND: return "zero_extend"; 5300 case ISD::ANY_EXTEND: return "any_extend"; 5301 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5302 case ISD::TRUNCATE: return "truncate"; 5303 case ISD::FP_ROUND: return "fp_round"; 5304 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5305 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5306 case ISD::FP_EXTEND: return "fp_extend"; 5307 5308 case ISD::SINT_TO_FP: return "sint_to_fp"; 5309 case ISD::UINT_TO_FP: return "uint_to_fp"; 5310 case ISD::FP_TO_SINT: return "fp_to_sint"; 5311 case ISD::FP_TO_UINT: return "fp_to_uint"; 5312 case ISD::BIT_CONVERT: return "bit_convert"; 5313 5314 case ISD::CONVERT_RNDSAT: { 5315 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5316 default: assert(0 && "Unknown cvt code!"); 5317 case ISD::CVT_FF: return "cvt_ff"; 5318 case ISD::CVT_FS: return "cvt_fs"; 5319 case ISD::CVT_FU: return "cvt_fu"; 5320 case ISD::CVT_SF: return "cvt_sf"; 5321 case ISD::CVT_UF: return "cvt_uf"; 5322 case ISD::CVT_SS: return "cvt_ss"; 5323 case ISD::CVT_SU: return "cvt_su"; 5324 case ISD::CVT_US: return "cvt_us"; 5325 case ISD::CVT_UU: return "cvt_uu"; 5326 } 5327 } 5328 5329 // Control flow instructions 5330 case ISD::BR: return "br"; 5331 case ISD::BRIND: return "brind"; 5332 case ISD::BR_JT: return "br_jt"; 5333 case ISD::BRCOND: return "brcond"; 5334 case ISD::BR_CC: return "br_cc"; 5335 case ISD::RET: return "ret"; 5336 case ISD::CALLSEQ_START: return "callseq_start"; 5337 case ISD::CALLSEQ_END: return "callseq_end"; 5338 5339 // Other operators 5340 case ISD::LOAD: return "load"; 5341 case ISD::STORE: return "store"; 5342 case ISD::VAARG: return "vaarg"; 5343 case ISD::VACOPY: return "vacopy"; 5344 case ISD::VAEND: return "vaend"; 5345 case ISD::VASTART: return "vastart"; 5346 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5347 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5348 case ISD::BUILD_PAIR: return "build_pair"; 5349 case ISD::STACKSAVE: return "stacksave"; 5350 case ISD::STACKRESTORE: return "stackrestore"; 5351 case ISD::TRAP: return "trap"; 5352 5353 // Bit manipulation 5354 case ISD::BSWAP: return "bswap"; 5355 case ISD::CTPOP: return "ctpop"; 5356 case ISD::CTTZ: return "cttz"; 5357 case ISD::CTLZ: return "ctlz"; 5358 5359 // Debug info 5360 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5361 case ISD::DEBUG_LOC: return "debug_loc"; 5362 5363 // Trampolines 5364 case ISD::TRAMPOLINE: return "trampoline"; 5365 5366 case ISD::CONDCODE: 5367 switch (cast<CondCodeSDNode>(this)->get()) { 5368 default: assert(0 && "Unknown setcc condition!"); 5369 case ISD::SETOEQ: return "setoeq"; 5370 case ISD::SETOGT: return "setogt"; 5371 case ISD::SETOGE: return "setoge"; 5372 case ISD::SETOLT: return "setolt"; 5373 case ISD::SETOLE: return "setole"; 5374 case ISD::SETONE: return "setone"; 5375 5376 case ISD::SETO: return "seto"; 5377 case ISD::SETUO: return "setuo"; 5378 case ISD::SETUEQ: return "setue"; 5379 case ISD::SETUGT: return "setugt"; 5380 case ISD::SETUGE: return "setuge"; 5381 case ISD::SETULT: return "setult"; 5382 case ISD::SETULE: return "setule"; 5383 case ISD::SETUNE: return "setune"; 5384 5385 case ISD::SETEQ: return "seteq"; 5386 case ISD::SETGT: return "setgt"; 5387 case ISD::SETGE: return "setge"; 5388 case ISD::SETLT: return "setlt"; 5389 case ISD::SETLE: return "setle"; 5390 case ISD::SETNE: return "setne"; 5391 } 5392 } 5393} 5394 5395const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5396 switch (AM) { 5397 default: 5398 return ""; 5399 case ISD::PRE_INC: 5400 return "<pre-inc>"; 5401 case ISD::PRE_DEC: 5402 return "<pre-dec>"; 5403 case ISD::POST_INC: 5404 return "<post-inc>"; 5405 case ISD::POST_DEC: 5406 return "<post-dec>"; 5407 } 5408} 5409 5410std::string ISD::ArgFlagsTy::getArgFlagsString() { 5411 std::string S = "< "; 5412 5413 if (isZExt()) 5414 S += "zext "; 5415 if (isSExt()) 5416 S += "sext "; 5417 if (isInReg()) 5418 S += "inreg "; 5419 if (isSRet()) 5420 S += "sret "; 5421 if (isByVal()) 5422 S += "byval "; 5423 if (isNest()) 5424 S += "nest "; 5425 if (getByValAlign()) 5426 S += "byval-align:" + utostr(getByValAlign()) + " "; 5427 if (getOrigAlign()) 5428 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5429 if (getByValSize()) 5430 S += "byval-size:" + utostr(getByValSize()) + " "; 5431 return S + ">"; 5432} 5433 5434void SDNode::dump() const { dump(0); } 5435void SDNode::dump(const SelectionDAG *G) const { 5436 print(errs(), G); 5437} 5438 5439void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const { 5440 OS << (void*)this << ": "; 5441 5442 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5443 if (i) OS << ","; 5444 if (getValueType(i) == MVT::Other) 5445 OS << "ch"; 5446 else 5447 OS << getValueType(i).getMVTString(); 5448 } 5449 OS << " = " << getOperationName(G); 5450} 5451 5452void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { 5453 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5454 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(this); 5455 OS << "<"; 5456 for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) { 5457 int Idx = SVN->getMaskElt(i); 5458 if (i) OS << ","; 5459 if (Idx < 0) 5460 OS << "u"; 5461 else 5462 OS << Idx; 5463 } 5464 OS << ">"; 5465 } 5466 5467 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5468 OS << '<' << CSDN->getAPIntValue() << '>'; 5469 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5470 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5471 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5472 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5473 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5474 else { 5475 OS << "<APFloat("; 5476 CSDN->getValueAPF().bitcastToAPInt().dump(); 5477 OS << ")>"; 5478 } 5479 } else if (const GlobalAddressSDNode *GADN = 5480 dyn_cast<GlobalAddressSDNode>(this)) { 5481 int64_t offset = GADN->getOffset(); 5482 OS << '<'; 5483 WriteAsOperand(OS, GADN->getGlobal()); 5484 OS << '>'; 5485 if (offset > 0) 5486 OS << " + " << offset; 5487 else 5488 OS << " " << offset; 5489 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5490 OS << "<" << FIDN->getIndex() << ">"; 5491 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5492 OS << "<" << JTDN->getIndex() << ">"; 5493 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5494 int offset = CP->getOffset(); 5495 if (CP->isMachineConstantPoolEntry()) 5496 OS << "<" << *CP->getMachineCPVal() << ">"; 5497 else 5498 OS << "<" << *CP->getConstVal() << ">"; 5499 if (offset > 0) 5500 OS << " + " << offset; 5501 else 5502 OS << " " << offset; 5503 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5504 OS << "<"; 5505 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5506 if (LBB) 5507 OS << LBB->getName() << " "; 5508 OS << (const void*)BBDN->getBasicBlock() << ">"; 5509 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5510 if (G && R->getReg() && 5511 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5512 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5513 } else { 5514 OS << " #" << R->getReg(); 5515 } 5516 } else if (const ExternalSymbolSDNode *ES = 5517 dyn_cast<ExternalSymbolSDNode>(this)) { 5518 OS << "'" << ES->getSymbol() << "'"; 5519 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5520 if (M->getValue()) 5521 OS << "<" << M->getValue() << ">"; 5522 else 5523 OS << "<null>"; 5524 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5525 if (M->MO.getValue()) 5526 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5527 else 5528 OS << "<null:" << M->MO.getOffset() << ">"; 5529 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5530 OS << N->getArgFlags().getArgFlagsString(); 5531 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5532 OS << ":" << N->getVT().getMVTString(); 5533 } 5534 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5535 const Value *SrcValue = LD->getSrcValue(); 5536 int SrcOffset = LD->getSrcValueOffset(); 5537 OS << " <"; 5538 if (SrcValue) 5539 OS << SrcValue; 5540 else 5541 OS << "null"; 5542 OS << ":" << SrcOffset << ">"; 5543 5544 bool doExt = true; 5545 switch (LD->getExtensionType()) { 5546 default: doExt = false; break; 5547 case ISD::EXTLOAD: OS << " <anyext "; break; 5548 case ISD::SEXTLOAD: OS << " <sext "; break; 5549 case ISD::ZEXTLOAD: OS << " <zext "; break; 5550 } 5551 if (doExt) 5552 OS << LD->getMemoryVT().getMVTString() << ">"; 5553 5554 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5555 if (*AM) 5556 OS << " " << AM; 5557 if (LD->isVolatile()) 5558 OS << " <volatile>"; 5559 OS << " alignment=" << LD->getAlignment(); 5560 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5561 const Value *SrcValue = ST->getSrcValue(); 5562 int SrcOffset = ST->getSrcValueOffset(); 5563 OS << " <"; 5564 if (SrcValue) 5565 OS << SrcValue; 5566 else 5567 OS << "null"; 5568 OS << ":" << SrcOffset << ">"; 5569 5570 if (ST->isTruncatingStore()) 5571 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5572 5573 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5574 if (*AM) 5575 OS << " " << AM; 5576 if (ST->isVolatile()) 5577 OS << " <volatile>"; 5578 OS << " alignment=" << ST->getAlignment(); 5579 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5580 const Value *SrcValue = AT->getSrcValue(); 5581 int SrcOffset = AT->getSrcValueOffset(); 5582 OS << " <"; 5583 if (SrcValue) 5584 OS << SrcValue; 5585 else 5586 OS << "null"; 5587 OS << ":" << SrcOffset << ">"; 5588 if (AT->isVolatile()) 5589 OS << " <volatile>"; 5590 OS << " alignment=" << AT->getAlignment(); 5591 } 5592} 5593 5594void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5595 print_types(OS, G); 5596 OS << " "; 5597 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5598 if (i) OS << ", "; 5599 OS << (void*)getOperand(i).getNode(); 5600 if (unsigned RN = getOperand(i).getResNo()) 5601 OS << ":" << RN; 5602 } 5603 print_details(OS, G); 5604} 5605 5606static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5607 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5608 if (N->getOperand(i).getNode()->hasOneUse()) 5609 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5610 else 5611 cerr << "\n" << std::string(indent+2, ' ') 5612 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5613 5614 5615 cerr << "\n" << std::string(indent, ' '); 5616 N->dump(G); 5617} 5618 5619void SelectionDAG::dump() const { 5620 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5621 5622 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5623 I != E; ++I) { 5624 const SDNode *N = I; 5625 if (!N->hasOneUse() && N != getRoot().getNode()) 5626 DumpNodes(N, 2, this); 5627 } 5628 5629 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5630 5631 cerr << "\n\n"; 5632} 5633 5634void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const { 5635 print_types(OS, G); 5636 print_details(OS, G); 5637} 5638 5639typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet; 5640static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, 5641 const SelectionDAG *G, VisitedSDNodeSet &once) { 5642 if (!once.insert(N)) // If we've been here before, return now. 5643 return; 5644 // Dump the current SDNode, but don't end the line yet. 5645 OS << std::string(indent, ' '); 5646 N->printr(OS, G); 5647 // Having printed this SDNode, walk the children: 5648 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5649 const SDNode *child = N->getOperand(i).getNode(); 5650 if (i) OS << ","; 5651 OS << " "; 5652 if (child->getNumOperands() == 0) { 5653 // This child has no grandchildren; print it inline right here. 5654 child->printr(OS, G); 5655 once.insert(child); 5656 } else { // Just the address. FIXME: also print the child's opcode 5657 OS << (void*)child; 5658 if (unsigned RN = N->getOperand(i).getResNo()) 5659 OS << ":" << RN; 5660 } 5661 } 5662 OS << "\n"; 5663 // Dump children that have grandchildren on their own line(s). 5664 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5665 const SDNode *child = N->getOperand(i).getNode(); 5666 DumpNodesr(OS, child, indent+2, G, once); 5667 } 5668} 5669 5670void SDNode::dumpr() const { 5671 VisitedSDNodeSet once; 5672 DumpNodesr(errs(), this, 0, 0, once); 5673} 5674 5675 5676// getAddressSpace - Return the address space this GlobalAddress belongs to. 5677unsigned GlobalAddressSDNode::getAddressSpace() const { 5678 return getGlobal()->getType()->getAddressSpace(); 5679} 5680 5681 5682const Type *ConstantPoolSDNode::getType() const { 5683 if (isMachineConstantPoolEntry()) 5684 return Val.MachineCPVal->getType(); 5685 return Val.ConstVal->getType(); 5686} 5687 5688bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue, 5689 APInt &SplatUndef, 5690 unsigned &SplatBitSize, 5691 bool &HasAnyUndefs, 5692 unsigned MinSplatBits) { 5693 MVT VT = getValueType(0); 5694 assert(VT.isVector() && "Expected a vector type"); 5695 unsigned sz = VT.getSizeInBits(); 5696 if (MinSplatBits > sz) 5697 return false; 5698 5699 SplatValue = APInt(sz, 0); 5700 SplatUndef = APInt(sz, 0); 5701 5702 // Get the bits. Bits with undefined values (when the corresponding element 5703 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared 5704 // in SplatValue. If any of the values are not constant, give up and return 5705 // false. 5706 unsigned int nOps = getNumOperands(); 5707 assert(nOps > 0 && "isConstantSplat has 0-size build vector"); 5708 unsigned EltBitSize = VT.getVectorElementType().getSizeInBits(); 5709 for (unsigned i = 0; i < nOps; ++i) { 5710 SDValue OpVal = getOperand(i); 5711 unsigned BitPos = i * EltBitSize; 5712 5713 if (OpVal.getOpcode() == ISD::UNDEF) 5714 SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos +EltBitSize); 5715 else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) 5716 SplatValue |= (APInt(CN->getAPIntValue()).zextOrTrunc(EltBitSize). 5717 zextOrTrunc(sz) << BitPos); 5718 else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) 5719 SplatValue |= CN->getValueAPF().bitcastToAPInt().zextOrTrunc(sz) <<BitPos; 5720 else 5721 return false; 5722 } 5723 5724 // The build_vector is all constants or undefs. Find the smallest element 5725 // size that splats the vector. 5726 5727 HasAnyUndefs = (SplatUndef != 0); 5728 while (sz > 8) { 5729 5730 unsigned HalfSize = sz / 2; 5731 APInt HighValue = APInt(SplatValue).lshr(HalfSize).trunc(HalfSize); 5732 APInt LowValue = APInt(SplatValue).trunc(HalfSize); 5733 APInt HighUndef = APInt(SplatUndef).lshr(HalfSize).trunc(HalfSize); 5734 APInt LowUndef = APInt(SplatUndef).trunc(HalfSize); 5735 5736 // If the two halves do not match (ignoring undef bits), stop here. 5737 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) || 5738 MinSplatBits > HalfSize) 5739 break; 5740 5741 SplatValue = HighValue | LowValue; 5742 SplatUndef = HighUndef & LowUndef; 5743 5744 sz = HalfSize; 5745 } 5746 5747 SplatBitSize = sz; 5748 return true; 5749} 5750 5751bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) { 5752 // Find the first non-undef value in the shuffle mask. 5753 unsigned i, e; 5754 for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i) 5755 /* search */; 5756 5757 assert(i != e && "VECTOR_SHUFFLE node with all undef indices!"); 5758 5759 // Make sure all remaining elements are either undef or the same as the first 5760 // non-undef value. 5761 for (int Idx = Mask[i]; i != e; ++i) 5762 if (Mask[i] >= 0 && Mask[i] != Idx) 5763 return false; 5764 return true; 5765} 5766