SelectionDAG.cpp revision 6ab6422f25f3deb1041130ff6bb285b22586ab32
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Support/MathExtras.h" 28#include "llvm/Target/TargetRegisterInfo.h" 29#include "llvm/Target/TargetData.h" 30#include "llvm/Target/TargetLowering.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/ADT/SetVector.h" 34#include "llvm/ADT/SmallPtrSet.h" 35#include "llvm/ADT/SmallSet.h" 36#include "llvm/ADT/SmallVector.h" 37#include "llvm/ADT/StringExtras.h" 38#include <algorithm> 39#include <cmath> 40using namespace llvm; 41 42/// makeVTList - Return an instance of the SDVTList struct initialized with the 43/// specified members. 44static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 45 SDVTList Res = {VTs, NumVTs}; 46 return Res; 47} 48 49static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 50 switch (VT.getSimpleVT()) { 51 default: assert(0 && "Unknown FP format"); 52 case MVT::f32: return &APFloat::IEEEsingle; 53 case MVT::f64: return &APFloat::IEEEdouble; 54 case MVT::f80: return &APFloat::x87DoubleExtended; 55 case MVT::f128: return &APFloat::IEEEquad; 56 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 57 } 58} 59 60SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 61 62//===----------------------------------------------------------------------===// 63// ConstantFPSDNode Class 64//===----------------------------------------------------------------------===// 65 66/// isExactlyValue - We don't rely on operator== working on double values, as 67/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 68/// As such, this method can be used to do an exact bit-for-bit comparison of 69/// two floating point values. 70bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 71 return Value.bitwiseIsEqual(V); 72} 73 74bool ConstantFPSDNode::isValueValidForType(MVT VT, 75 const APFloat& Val) { 76 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 77 78 // PPC long double cannot be converted to any other type. 79 if (VT == MVT::ppcf128 || 80 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 81 return false; 82 83 // convert modifies in place, so make a copy. 84 APFloat Val2 = APFloat(Val); 85 return Val2.convert(*MVTToAPFloatSemantics(VT), 86 APFloat::rmNearestTiesToEven) == APFloat::opOK; 87} 88 89//===----------------------------------------------------------------------===// 90// ISD Namespace 91//===----------------------------------------------------------------------===// 92 93/// isBuildVectorAllOnes - Return true if the specified node is a 94/// BUILD_VECTOR where all of the elements are ~0 or undef. 95bool ISD::isBuildVectorAllOnes(const SDNode *N) { 96 // Look through a bit convert. 97 if (N->getOpcode() == ISD::BIT_CONVERT) 98 N = N->getOperand(0).Val; 99 100 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 101 102 unsigned i = 0, e = N->getNumOperands(); 103 104 // Skip over all of the undef values. 105 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 106 ++i; 107 108 // Do not accept an all-undef vector. 109 if (i == e) return false; 110 111 // Do not accept build_vectors that aren't all constants or which have non-~0 112 // elements. 113 SDValue NotZero = N->getOperand(i); 114 if (isa<ConstantSDNode>(NotZero)) { 115 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 116 return false; 117 } else if (isa<ConstantFPSDNode>(NotZero)) { 118 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 119 convertToAPInt().isAllOnesValue()) 120 return false; 121 } else 122 return false; 123 124 // Okay, we have at least one ~0 value, check to see if the rest match or are 125 // undefs. 126 for (++i; i != e; ++i) 127 if (N->getOperand(i) != NotZero && 128 N->getOperand(i).getOpcode() != ISD::UNDEF) 129 return false; 130 return true; 131} 132 133 134/// isBuildVectorAllZeros - Return true if the specified node is a 135/// BUILD_VECTOR where all of the elements are 0 or undef. 136bool ISD::isBuildVectorAllZeros(const SDNode *N) { 137 // Look through a bit convert. 138 if (N->getOpcode() == ISD::BIT_CONVERT) 139 N = N->getOperand(0).Val; 140 141 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 142 143 unsigned i = 0, e = N->getNumOperands(); 144 145 // Skip over all of the undef values. 146 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 147 ++i; 148 149 // Do not accept an all-undef vector. 150 if (i == e) return false; 151 152 // Do not accept build_vectors that aren't all constants or which have non-~0 153 // elements. 154 SDValue Zero = N->getOperand(i); 155 if (isa<ConstantSDNode>(Zero)) { 156 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 157 return false; 158 } else if (isa<ConstantFPSDNode>(Zero)) { 159 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 160 return false; 161 } else 162 return false; 163 164 // Okay, we have at least one ~0 value, check to see if the rest match or are 165 // undefs. 166 for (++i; i != e; ++i) 167 if (N->getOperand(i) != Zero && 168 N->getOperand(i).getOpcode() != ISD::UNDEF) 169 return false; 170 return true; 171} 172 173/// isScalarToVector - Return true if the specified node is a 174/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 175/// element is not an undef. 176bool ISD::isScalarToVector(const SDNode *N) { 177 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 178 return true; 179 180 if (N->getOpcode() != ISD::BUILD_VECTOR) 181 return false; 182 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 183 return false; 184 unsigned NumElems = N->getNumOperands(); 185 for (unsigned i = 1; i < NumElems; ++i) { 186 SDValue V = N->getOperand(i); 187 if (V.getOpcode() != ISD::UNDEF) 188 return false; 189 } 190 return true; 191} 192 193 194/// isDebugLabel - Return true if the specified node represents a debug 195/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 196bool ISD::isDebugLabel(const SDNode *N) { 197 SDValue Zero; 198 if (N->getOpcode() == ISD::DBG_LABEL) 199 return true; 200 if (N->isMachineOpcode() && 201 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 202 return true; 203 return false; 204} 205 206/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 207/// when given the operation for (X op Y). 208ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 209 // To perform this operation, we just need to swap the L and G bits of the 210 // operation. 211 unsigned OldL = (Operation >> 2) & 1; 212 unsigned OldG = (Operation >> 1) & 1; 213 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 214 (OldL << 1) | // New G bit 215 (OldG << 2)); // New L bit. 216} 217 218/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 219/// 'op' is a valid SetCC operation. 220ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 221 unsigned Operation = Op; 222 if (isInteger) 223 Operation ^= 7; // Flip L, G, E bits, but not U. 224 else 225 Operation ^= 15; // Flip all of the condition bits. 226 if (Operation > ISD::SETTRUE2) 227 Operation &= ~8; // Don't let N and U bits get set. 228 return ISD::CondCode(Operation); 229} 230 231 232/// isSignedOp - For an integer comparison, return 1 if the comparison is a 233/// signed operation and 2 if the result is an unsigned comparison. Return zero 234/// if the operation does not depend on the sign of the input (setne and seteq). 235static int isSignedOp(ISD::CondCode Opcode) { 236 switch (Opcode) { 237 default: assert(0 && "Illegal integer setcc operation!"); 238 case ISD::SETEQ: 239 case ISD::SETNE: return 0; 240 case ISD::SETLT: 241 case ISD::SETLE: 242 case ISD::SETGT: 243 case ISD::SETGE: return 1; 244 case ISD::SETULT: 245 case ISD::SETULE: 246 case ISD::SETUGT: 247 case ISD::SETUGE: return 2; 248 } 249} 250 251/// getSetCCOrOperation - Return the result of a logical OR between different 252/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 253/// returns SETCC_INVALID if it is not possible to represent the resultant 254/// comparison. 255ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 256 bool isInteger) { 257 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 258 // Cannot fold a signed integer setcc with an unsigned integer setcc. 259 return ISD::SETCC_INVALID; 260 261 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 262 263 // If the N and U bits get set then the resultant comparison DOES suddenly 264 // care about orderedness, and is true when ordered. 265 if (Op > ISD::SETTRUE2) 266 Op &= ~16; // Clear the U bit if the N bit is set. 267 268 // Canonicalize illegal integer setcc's. 269 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 270 Op = ISD::SETNE; 271 272 return ISD::CondCode(Op); 273} 274 275/// getSetCCAndOperation - Return the result of a logical AND between different 276/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 277/// function returns zero if it is not possible to represent the resultant 278/// comparison. 279ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 280 bool isInteger) { 281 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 282 // Cannot fold a signed setcc with an unsigned setcc. 283 return ISD::SETCC_INVALID; 284 285 // Combine all of the condition bits. 286 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 287 288 // Canonicalize illegal integer setcc's. 289 if (isInteger) { 290 switch (Result) { 291 default: break; 292 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 293 case ISD::SETOEQ: // SETEQ & SETU[LG]E 294 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 295 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 296 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 297 } 298 } 299 300 return Result; 301} 302 303const TargetMachine &SelectionDAG::getTarget() const { 304 return TLI.getTargetMachine(); 305} 306 307//===----------------------------------------------------------------------===// 308// SDNode Profile Support 309//===----------------------------------------------------------------------===// 310 311/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 312/// 313static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 314 ID.AddInteger(OpC); 315} 316 317/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 318/// solely with their pointer. 319static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 320 ID.AddPointer(VTList.VTs); 321} 322 323/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 324/// 325static void AddNodeIDOperands(FoldingSetNodeID &ID, 326 const SDValue *Ops, unsigned NumOps) { 327 for (; NumOps; --NumOps, ++Ops) { 328 ID.AddPointer(Ops->Val); 329 ID.AddInteger(Ops->ResNo); 330 } 331} 332 333/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 334/// 335static void AddNodeIDOperands(FoldingSetNodeID &ID, 336 const SDUse *Ops, unsigned NumOps) { 337 for (; NumOps; --NumOps, ++Ops) { 338 ID.AddPointer(Ops->getVal()); 339 ID.AddInteger(Ops->getSDValue().ResNo); 340 } 341} 342 343static void AddNodeIDNode(FoldingSetNodeID &ID, 344 unsigned short OpC, SDVTList VTList, 345 const SDValue *OpList, unsigned N) { 346 AddNodeIDOpcode(ID, OpC); 347 AddNodeIDValueTypes(ID, VTList); 348 AddNodeIDOperands(ID, OpList, N); 349} 350 351 352/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 353/// data. 354static void AddNodeIDNode(FoldingSetNodeID &ID, SDNode *N) { 355 AddNodeIDOpcode(ID, N->getOpcode()); 356 // Add the return value info. 357 AddNodeIDValueTypes(ID, N->getVTList()); 358 // Add the operand info. 359 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 360 361 // Handle SDNode leafs with special info. 362 switch (N->getOpcode()) { 363 default: break; // Normal nodes don't need extra info. 364 case ISD::ARG_FLAGS: 365 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 366 break; 367 case ISD::TargetConstant: 368 case ISD::Constant: 369 ID.Add(cast<ConstantSDNode>(N)->getAPIntValue()); 370 break; 371 case ISD::TargetConstantFP: 372 case ISD::ConstantFP: { 373 ID.Add(cast<ConstantFPSDNode>(N)->getValueAPF()); 374 break; 375 } 376 case ISD::TargetGlobalAddress: 377 case ISD::GlobalAddress: 378 case ISD::TargetGlobalTLSAddress: 379 case ISD::GlobalTLSAddress: { 380 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 381 ID.AddPointer(GA->getGlobal()); 382 ID.AddInteger(GA->getOffset()); 383 break; 384 } 385 case ISD::BasicBlock: 386 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 387 break; 388 case ISD::Register: 389 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 390 break; 391 case ISD::DBG_STOPPOINT: { 392 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 393 ID.AddInteger(DSP->getLine()); 394 ID.AddInteger(DSP->getColumn()); 395 ID.AddPointer(DSP->getCompileUnit()); 396 break; 397 } 398 case ISD::SRCVALUE: 399 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 400 break; 401 case ISD::MEMOPERAND: { 402 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 403 ID.AddPointer(MO.getValue()); 404 ID.AddInteger(MO.getFlags()); 405 ID.AddInteger(MO.getOffset()); 406 ID.AddInteger(MO.getSize()); 407 ID.AddInteger(MO.getAlignment()); 408 break; 409 } 410 case ISD::FrameIndex: 411 case ISD::TargetFrameIndex: 412 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 413 break; 414 case ISD::JumpTable: 415 case ISD::TargetJumpTable: 416 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 417 break; 418 case ISD::ConstantPool: 419 case ISD::TargetConstantPool: { 420 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 421 ID.AddInteger(CP->getAlignment()); 422 ID.AddInteger(CP->getOffset()); 423 if (CP->isMachineConstantPoolEntry()) 424 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 425 else 426 ID.AddPointer(CP->getConstVal()); 427 break; 428 } 429 case ISD::LOAD: { 430 LoadSDNode *LD = cast<LoadSDNode>(N); 431 ID.AddInteger(LD->getAddressingMode()); 432 ID.AddInteger(LD->getExtensionType()); 433 ID.AddInteger(LD->getMemoryVT().getRawBits()); 434 ID.AddInteger(LD->getAlignment()); 435 ID.AddInteger(LD->isVolatile()); 436 break; 437 } 438 case ISD::STORE: { 439 StoreSDNode *ST = cast<StoreSDNode>(N); 440 ID.AddInteger(ST->getAddressingMode()); 441 ID.AddInteger(ST->isTruncatingStore()); 442 ID.AddInteger(ST->getMemoryVT().getRawBits()); 443 ID.AddInteger(ST->getAlignment()); 444 ID.AddInteger(ST->isVolatile()); 445 break; 446 } 447 case ISD::ATOMIC_CMP_SWAP: 448 case ISD::ATOMIC_LOAD_ADD: 449 case ISD::ATOMIC_SWAP: 450 case ISD::ATOMIC_LOAD_SUB: 451 case ISD::ATOMIC_LOAD_AND: 452 case ISD::ATOMIC_LOAD_OR: 453 case ISD::ATOMIC_LOAD_XOR: 454 case ISD::ATOMIC_LOAD_NAND: 455 case ISD::ATOMIC_LOAD_MIN: 456 case ISD::ATOMIC_LOAD_MAX: 457 case ISD::ATOMIC_LOAD_UMIN: 458 case ISD::ATOMIC_LOAD_UMAX: { 459 AtomicSDNode *AT = cast<AtomicSDNode>(N); 460 ID.AddInteger(AT->getAlignment()); 461 ID.AddInteger(AT->isVolatile()); 462 break; 463 } 464 } // end switch (N->getOpcode()) 465} 466 467//===----------------------------------------------------------------------===// 468// SelectionDAG Class 469//===----------------------------------------------------------------------===// 470 471/// RemoveDeadNodes - This method deletes all unreachable nodes in the 472/// SelectionDAG. 473void SelectionDAG::RemoveDeadNodes() { 474 // Create a dummy node (which is not added to allnodes), that adds a reference 475 // to the root node, preventing it from being deleted. 476 HandleSDNode Dummy(getRoot()); 477 478 SmallVector<SDNode*, 128> DeadNodes; 479 480 // Add all obviously-dead nodes to the DeadNodes worklist. 481 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 482 if (I->use_empty()) 483 DeadNodes.push_back(I); 484 485 RemoveDeadNodes(DeadNodes); 486 487 // If the root changed (e.g. it was a dead load, update the root). 488 setRoot(Dummy.getValue()); 489} 490 491/// RemoveDeadNodes - This method deletes the unreachable nodes in the 492/// given list, and any nodes that become unreachable as a result. 493void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 494 DAGUpdateListener *UpdateListener) { 495 496 // Process the worklist, deleting the nodes and adding their uses to the 497 // worklist. 498 while (!DeadNodes.empty()) { 499 SDNode *N = DeadNodes.back(); 500 DeadNodes.pop_back(); 501 502 if (UpdateListener) 503 UpdateListener->NodeDeleted(N, 0); 504 505 // Take the node out of the appropriate CSE map. 506 RemoveNodeFromCSEMaps(N); 507 508 // Next, brutally remove the operand list. This is safe to do, as there are 509 // no cycles in the graph. 510 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) { 511 SDNode *Operand = I->getVal(); 512 Operand->removeUser(std::distance(N->op_begin(), I), N); 513 514 // Now that we removed this operand, see if there are no uses of it left. 515 if (Operand->use_empty()) 516 DeadNodes.push_back(Operand); 517 } 518 if (N->OperandsNeedDelete) { 519 delete[] N->OperandList; 520 } 521 N->OperandList = 0; 522 N->NumOperands = 0; 523 524 // Finally, remove N itself. 525 AllNodes.remove(N); 526 } 527} 528 529void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 530 SmallVector<SDNode*, 16> DeadNodes(1, N); 531 RemoveDeadNodes(DeadNodes, UpdateListener); 532} 533 534void SelectionDAG::DeleteNode(SDNode *N) { 535 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 536 537 // First take this out of the appropriate CSE map. 538 RemoveNodeFromCSEMaps(N); 539 540 // Finally, remove uses due to operands of this node, remove from the 541 // AllNodes list, and delete the node. 542 DeleteNodeNotInCSEMaps(N); 543} 544 545void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 546 547 // Drop all of the operands and decrement used nodes use counts. 548 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 549 I->getVal()->removeUser(std::distance(N->op_begin(), I), N); 550 if (N->OperandsNeedDelete) { 551 delete[] N->OperandList; 552 } 553 N->OperandList = 0; 554 N->NumOperands = 0; 555 556 AllNodes.remove(N); 557} 558 559/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 560/// correspond to it. This is useful when we're about to delete or repurpose 561/// the node. We don't want future request for structurally identical nodes 562/// to return N anymore. 563void SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 564 bool Erased = false; 565 switch (N->getOpcode()) { 566 case ISD::HANDLENODE: return; // noop. 567 case ISD::CONDCODE: 568 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 569 "Cond code doesn't exist!"); 570 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 571 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 572 break; 573 case ISD::ExternalSymbol: 574 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 575 break; 576 case ISD::TargetExternalSymbol: 577 Erased = 578 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 579 break; 580 case ISD::VALUETYPE: { 581 MVT VT = cast<VTSDNode>(N)->getVT(); 582 if (VT.isExtended()) { 583 Erased = ExtendedValueTypeNodes.erase(VT); 584 } else { 585 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 586 ValueTypeNodes[VT.getSimpleVT()] = 0; 587 } 588 break; 589 } 590 default: 591 // Remove it from the CSE Map. 592 Erased = CSEMap.RemoveNode(N); 593 break; 594 } 595#ifndef NDEBUG 596 // Verify that the node was actually in one of the CSE maps, unless it has a 597 // flag result (which cannot be CSE'd) or is one of the special cases that are 598 // not subject to CSE. 599 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 600 !N->isTargetOpcode() && 601 N->getOpcode() != ISD::DBG_LABEL && 602 N->getOpcode() != ISD::DBG_STOPPOINT && 603 N->getOpcode() != ISD::EH_LABEL && 604 N->getOpcode() != ISD::DECLARE) { 605 N->dump(this); 606 cerr << "\n"; 607 assert(0 && "Node is not in map!"); 608 } 609#endif 610} 611 612/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 613/// has been taken out and modified in some way. If the specified node already 614/// exists in the CSE maps, do not modify the maps, but return the existing node 615/// instead. If it doesn't exist, add it and return null. 616/// 617SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 618 assert(N->getNumOperands() && "This is a leaf node!"); 619 620 if (N->getValueType(0) == MVT::Flag) 621 return 0; // Never CSE anything that produces a flag. 622 623 switch (N->getOpcode()) { 624 default: break; 625 case ISD::HANDLENODE: 626 case ISD::DBG_LABEL: 627 case ISD::DBG_STOPPOINT: 628 case ISD::EH_LABEL: 629 case ISD::DECLARE: 630 return 0; // Never add these nodes. 631 } 632 633 // Check that remaining values produced are not flags. 634 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 635 if (N->getValueType(i) == MVT::Flag) 636 return 0; // Never CSE anything that produces a flag. 637 638 SDNode *New = CSEMap.GetOrInsertNode(N); 639 if (New != N) return New; // Node already existed. 640 return 0; 641} 642 643/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 644/// were replaced with those specified. If this node is never memoized, 645/// return null, otherwise return a pointer to the slot it would take. If a 646/// node already exists with these operands, the slot will be non-null. 647SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 648 void *&InsertPos) { 649 if (N->getValueType(0) == MVT::Flag) 650 return 0; // Never CSE anything that produces a flag. 651 652 switch (N->getOpcode()) { 653 default: break; 654 case ISD::HANDLENODE: 655 case ISD::DBG_LABEL: 656 case ISD::DBG_STOPPOINT: 657 case ISD::EH_LABEL: 658 return 0; // Never add these nodes. 659 } 660 661 // Check that remaining values produced are not flags. 662 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 663 if (N->getValueType(i) == MVT::Flag) 664 return 0; // Never CSE anything that produces a flag. 665 666 SDValue Ops[] = { Op }; 667 FoldingSetNodeID ID; 668 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 669 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 670} 671 672/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 673/// were replaced with those specified. If this node is never memoized, 674/// return null, otherwise return a pointer to the slot it would take. If a 675/// node already exists with these operands, the slot will be non-null. 676SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 677 SDValue Op1, SDValue Op2, 678 void *&InsertPos) { 679 if (N->getOpcode() == ISD::HANDLENODE || N->getValueType(0) == MVT::Flag) 680 681 // Check that remaining values produced are not flags. 682 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 683 if (N->getValueType(i) == MVT::Flag) 684 return 0; // Never CSE anything that produces a flag. 685 686 SDValue Ops[] = { Op1, Op2 }; 687 FoldingSetNodeID ID; 688 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 689 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 690} 691 692 693/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 694/// were replaced with those specified. If this node is never memoized, 695/// return null, otherwise return a pointer to the slot it would take. If a 696/// node already exists with these operands, the slot will be non-null. 697SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 698 const SDValue *Ops,unsigned NumOps, 699 void *&InsertPos) { 700 if (N->getValueType(0) == MVT::Flag) 701 return 0; // Never CSE anything that produces a flag. 702 703 switch (N->getOpcode()) { 704 default: break; 705 case ISD::HANDLENODE: 706 case ISD::DBG_LABEL: 707 case ISD::DBG_STOPPOINT: 708 case ISD::EH_LABEL: 709 case ISD::DECLARE: 710 return 0; // Never add these nodes. 711 } 712 713 // Check that remaining values produced are not flags. 714 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 715 if (N->getValueType(i) == MVT::Flag) 716 return 0; // Never CSE anything that produces a flag. 717 718 FoldingSetNodeID ID; 719 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 720 721 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 722 ID.AddInteger(LD->getAddressingMode()); 723 ID.AddInteger(LD->getExtensionType()); 724 ID.AddInteger(LD->getMemoryVT().getRawBits()); 725 ID.AddInteger(LD->getAlignment()); 726 ID.AddInteger(LD->isVolatile()); 727 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 728 ID.AddInteger(ST->getAddressingMode()); 729 ID.AddInteger(ST->isTruncatingStore()); 730 ID.AddInteger(ST->getMemoryVT().getRawBits()); 731 ID.AddInteger(ST->getAlignment()); 732 ID.AddInteger(ST->isVolatile()); 733 } 734 735 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 736} 737 738/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 739void SelectionDAG::VerifyNode(SDNode *N) { 740 switch (N->getOpcode()) { 741 default: 742 break; 743 case ISD::BUILD_VECTOR: { 744 assert(N->getNumValues() == 1 && "Too many results for BUILD_VECTOR!"); 745 assert(N->getValueType(0).isVector() && "Wrong BUILD_VECTOR return type!"); 746 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 747 "Wrong number of BUILD_VECTOR operands!"); 748 MVT EltVT = N->getValueType(0).getVectorElementType(); 749 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 750 assert(I->getSDValue().getValueType() == EltVT && 751 "Wrong BUILD_VECTOR operand type!"); 752 break; 753 } 754 } 755} 756 757/// getMVTAlignment - Compute the default alignment value for the 758/// given type. 759/// 760unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 761 const Type *Ty = VT == MVT::iPTR ? 762 PointerType::get(Type::Int8Ty, 0) : 763 VT.getTypeForMVT(); 764 765 return TLI.getTargetData()->getABITypeAlignment(Ty); 766} 767 768SelectionDAG::~SelectionDAG() { 769 while (!AllNodes.empty()) { 770 SDNode *N = AllNodes.remove(AllNodes.begin()); 771 N->SetNextInBucket(0); 772 if (N->OperandsNeedDelete) { 773 delete [] N->OperandList; 774 } 775 N->OperandList = 0; 776 N->NumOperands = 0; 777 } 778} 779 780SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) { 781 if (Op.getValueType() == VT) return Op; 782 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 783 VT.getSizeInBits()); 784 return getNode(ISD::AND, Op.getValueType(), Op, 785 getConstant(Imm, Op.getValueType())); 786} 787 788SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 789 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 790 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 791} 792 793SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 794 assert(VT.isInteger() && "Cannot create FP integer constant!"); 795 796 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 797 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 798 "APInt size does not match type size!"); 799 800 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 801 FoldingSetNodeID ID; 802 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 803 ID.Add(Val); 804 void *IP = 0; 805 SDNode *N = NULL; 806 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 807 if (!VT.isVector()) 808 return SDValue(N, 0); 809 if (!N) { 810 N = NodeAllocator.Allocate<ConstantSDNode>(); 811 new (N) ConstantSDNode(isT, Val, EltVT); 812 CSEMap.InsertNode(N, IP); 813 AllNodes.push_back(N); 814 } 815 816 SDValue Result(N, 0); 817 if (VT.isVector()) { 818 SmallVector<SDValue, 8> Ops; 819 Ops.assign(VT.getVectorNumElements(), Result); 820 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 821 } 822 return Result; 823} 824 825SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 826 return getConstant(Val, TLI.getPointerTy(), isTarget); 827} 828 829 830SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 831 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 832 833 MVT EltVT = 834 VT.isVector() ? VT.getVectorElementType() : VT; 835 836 // Do the map lookup using the actual bit pattern for the floating point 837 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 838 // we don't have issues with SNANs. 839 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 840 FoldingSetNodeID ID; 841 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 842 ID.Add(V); 843 void *IP = 0; 844 SDNode *N = NULL; 845 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 846 if (!VT.isVector()) 847 return SDValue(N, 0); 848 if (!N) { 849 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 850 new (N) ConstantFPSDNode(isTarget, V, EltVT); 851 CSEMap.InsertNode(N, IP); 852 AllNodes.push_back(N); 853 } 854 855 SDValue Result(N, 0); 856 if (VT.isVector()) { 857 SmallVector<SDValue, 8> Ops; 858 Ops.assign(VT.getVectorNumElements(), Result); 859 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 860 } 861 return Result; 862} 863 864SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 865 MVT EltVT = 866 VT.isVector() ? VT.getVectorElementType() : VT; 867 if (EltVT==MVT::f32) 868 return getConstantFP(APFloat((float)Val), VT, isTarget); 869 else 870 return getConstantFP(APFloat(Val), VT, isTarget); 871} 872 873SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 874 MVT VT, int Offset, 875 bool isTargetGA) { 876 unsigned Opc; 877 878 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 879 if (!GVar) { 880 // If GV is an alias then use the aliasee for determining thread-localness. 881 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 882 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal()); 883 } 884 885 if (GVar && GVar->isThreadLocal()) 886 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 887 else 888 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 889 890 FoldingSetNodeID ID; 891 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 892 ID.AddPointer(GV); 893 ID.AddInteger(Offset); 894 void *IP = 0; 895 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 896 return SDValue(E, 0); 897 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 898 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 899 CSEMap.InsertNode(N, IP); 900 AllNodes.push_back(N); 901 return SDValue(N, 0); 902} 903 904SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 905 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 906 FoldingSetNodeID ID; 907 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 908 ID.AddInteger(FI); 909 void *IP = 0; 910 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 911 return SDValue(E, 0); 912 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 913 new (N) FrameIndexSDNode(FI, VT, isTarget); 914 CSEMap.InsertNode(N, IP); 915 AllNodes.push_back(N); 916 return SDValue(N, 0); 917} 918 919SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 920 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 921 FoldingSetNodeID ID; 922 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 923 ID.AddInteger(JTI); 924 void *IP = 0; 925 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 926 return SDValue(E, 0); 927 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 928 new (N) JumpTableSDNode(JTI, VT, isTarget); 929 CSEMap.InsertNode(N, IP); 930 AllNodes.push_back(N); 931 return SDValue(N, 0); 932} 933 934SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 935 unsigned Alignment, int Offset, 936 bool isTarget) { 937 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 938 FoldingSetNodeID ID; 939 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 940 ID.AddInteger(Alignment); 941 ID.AddInteger(Offset); 942 ID.AddPointer(C); 943 void *IP = 0; 944 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 945 return SDValue(E, 0); 946 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 947 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 948 CSEMap.InsertNode(N, IP); 949 AllNodes.push_back(N); 950 return SDValue(N, 0); 951} 952 953 954SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 955 unsigned Alignment, int Offset, 956 bool isTarget) { 957 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 958 FoldingSetNodeID ID; 959 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 960 ID.AddInteger(Alignment); 961 ID.AddInteger(Offset); 962 C->AddSelectionDAGCSEId(ID); 963 void *IP = 0; 964 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 965 return SDValue(E, 0); 966 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 967 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 968 CSEMap.InsertNode(N, IP); 969 AllNodes.push_back(N); 970 return SDValue(N, 0); 971} 972 973 974SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 975 FoldingSetNodeID ID; 976 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 977 ID.AddPointer(MBB); 978 void *IP = 0; 979 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 980 return SDValue(E, 0); 981 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 982 new (N) BasicBlockSDNode(MBB); 983 CSEMap.InsertNode(N, IP); 984 AllNodes.push_back(N); 985 return SDValue(N, 0); 986} 987 988SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 989 FoldingSetNodeID ID; 990 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 991 ID.AddInteger(Flags.getRawBits()); 992 void *IP = 0; 993 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 994 return SDValue(E, 0); 995 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 996 new (N) ARG_FLAGSSDNode(Flags); 997 CSEMap.InsertNode(N, IP); 998 AllNodes.push_back(N); 999 return SDValue(N, 0); 1000} 1001 1002SDValue SelectionDAG::getValueType(MVT VT) { 1003 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1004 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1005 1006 SDNode *&N = VT.isExtended() ? 1007 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1008 1009 if (N) return SDValue(N, 0); 1010 N = NodeAllocator.Allocate<VTSDNode>(); 1011 new (N) VTSDNode(VT); 1012 AllNodes.push_back(N); 1013 return SDValue(N, 0); 1014} 1015 1016SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1017 SDNode *&N = ExternalSymbols[Sym]; 1018 if (N) return SDValue(N, 0); 1019 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1020 new (N) ExternalSymbolSDNode(false, Sym, VT); 1021 AllNodes.push_back(N); 1022 return SDValue(N, 0); 1023} 1024 1025SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1026 SDNode *&N = TargetExternalSymbols[Sym]; 1027 if (N) return SDValue(N, 0); 1028 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1029 new (N) ExternalSymbolSDNode(true, Sym, VT); 1030 AllNodes.push_back(N); 1031 return SDValue(N, 0); 1032} 1033 1034SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1035 if ((unsigned)Cond >= CondCodeNodes.size()) 1036 CondCodeNodes.resize(Cond+1); 1037 1038 if (CondCodeNodes[Cond] == 0) { 1039 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1040 new (N) CondCodeSDNode(Cond); 1041 CondCodeNodes[Cond] = N; 1042 AllNodes.push_back(N); 1043 } 1044 return SDValue(CondCodeNodes[Cond], 0); 1045} 1046 1047SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1048 FoldingSetNodeID ID; 1049 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1050 ID.AddInteger(RegNo); 1051 void *IP = 0; 1052 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1053 return SDValue(E, 0); 1054 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1055 new (N) RegisterSDNode(RegNo, VT); 1056 CSEMap.InsertNode(N, IP); 1057 AllNodes.push_back(N); 1058 return SDValue(N, 0); 1059} 1060 1061SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1062 unsigned Line, unsigned Col, 1063 const CompileUnitDesc *CU) { 1064 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1065 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1066 AllNodes.push_back(N); 1067 return SDValue(N, 0); 1068} 1069 1070SDValue SelectionDAG::getLabel(unsigned Opcode, 1071 SDValue Root, 1072 unsigned LabelID) { 1073 FoldingSetNodeID ID; 1074 SDValue Ops[] = { Root }; 1075 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1076 ID.AddInteger(LabelID); 1077 void *IP = 0; 1078 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1079 return SDValue(E, 0); 1080 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1081 new (N) LabelSDNode(Opcode, Root, LabelID); 1082 CSEMap.InsertNode(N, IP); 1083 AllNodes.push_back(N); 1084 return SDValue(N, 0); 1085} 1086 1087SDValue SelectionDAG::getSrcValue(const Value *V) { 1088 assert((!V || isa<PointerType>(V->getType())) && 1089 "SrcValue is not a pointer?"); 1090 1091 FoldingSetNodeID ID; 1092 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1093 ID.AddPointer(V); 1094 1095 void *IP = 0; 1096 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1097 return SDValue(E, 0); 1098 1099 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1100 new (N) SrcValueSDNode(V); 1101 CSEMap.InsertNode(N, IP); 1102 AllNodes.push_back(N); 1103 return SDValue(N, 0); 1104} 1105 1106SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1107 const Value *v = MO.getValue(); 1108 assert((!v || isa<PointerType>(v->getType())) && 1109 "SrcValue is not a pointer?"); 1110 1111 FoldingSetNodeID ID; 1112 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1113 ID.AddPointer(v); 1114 ID.AddInteger(MO.getFlags()); 1115 ID.AddInteger(MO.getOffset()); 1116 ID.AddInteger(MO.getSize()); 1117 ID.AddInteger(MO.getAlignment()); 1118 1119 void *IP = 0; 1120 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1121 return SDValue(E, 0); 1122 1123 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1124 new (N) MemOperandSDNode(MO); 1125 CSEMap.InsertNode(N, IP); 1126 AllNodes.push_back(N); 1127 return SDValue(N, 0); 1128} 1129 1130/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1131/// specified value type. 1132SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1133 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1134 unsigned ByteSize = VT.getSizeInBits()/8; 1135 const Type *Ty = VT.getTypeForMVT(); 1136 unsigned StackAlign = 1137 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1138 1139 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1140 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1141} 1142 1143SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1144 SDValue N2, ISD::CondCode Cond) { 1145 // These setcc operations always fold. 1146 switch (Cond) { 1147 default: break; 1148 case ISD::SETFALSE: 1149 case ISD::SETFALSE2: return getConstant(0, VT); 1150 case ISD::SETTRUE: 1151 case ISD::SETTRUE2: return getConstant(1, VT); 1152 1153 case ISD::SETOEQ: 1154 case ISD::SETOGT: 1155 case ISD::SETOGE: 1156 case ISD::SETOLT: 1157 case ISD::SETOLE: 1158 case ISD::SETONE: 1159 case ISD::SETO: 1160 case ISD::SETUO: 1161 case ISD::SETUEQ: 1162 case ISD::SETUNE: 1163 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1164 break; 1165 } 1166 1167 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) { 1168 const APInt &C2 = N2C->getAPIntValue(); 1169 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 1170 const APInt &C1 = N1C->getAPIntValue(); 1171 1172 switch (Cond) { 1173 default: assert(0 && "Unknown integer setcc!"); 1174 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1175 case ISD::SETNE: return getConstant(C1 != C2, VT); 1176 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1177 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1178 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1179 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1180 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1181 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1182 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1183 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1184 } 1185 } 1186 } 1187 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 1188 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) { 1189 // No compile time operations on this type yet. 1190 if (N1C->getValueType(0) == MVT::ppcf128) 1191 return SDValue(); 1192 1193 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1194 switch (Cond) { 1195 default: break; 1196 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1197 return getNode(ISD::UNDEF, VT); 1198 // fall through 1199 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1200 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1201 return getNode(ISD::UNDEF, VT); 1202 // fall through 1203 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1204 R==APFloat::cmpLessThan, VT); 1205 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1206 return getNode(ISD::UNDEF, VT); 1207 // fall through 1208 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1209 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1210 return getNode(ISD::UNDEF, VT); 1211 // fall through 1212 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1213 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1214 return getNode(ISD::UNDEF, VT); 1215 // fall through 1216 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1217 R==APFloat::cmpEqual, VT); 1218 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1219 return getNode(ISD::UNDEF, VT); 1220 // fall through 1221 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1222 R==APFloat::cmpEqual, VT); 1223 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1224 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1225 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1226 R==APFloat::cmpEqual, VT); 1227 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1228 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1229 R==APFloat::cmpLessThan, VT); 1230 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1231 R==APFloat::cmpUnordered, VT); 1232 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1233 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1234 } 1235 } else { 1236 // Ensure that the constant occurs on the RHS. 1237 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1238 } 1239 } 1240 1241 // Could not fold it. 1242 return SDValue(); 1243} 1244 1245/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1246/// use this predicate to simplify operations downstream. 1247bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1248 unsigned BitWidth = Op.getValueSizeInBits(); 1249 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1250} 1251 1252/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1253/// this predicate to simplify operations downstream. Mask is known to be zero 1254/// for bits that V cannot have. 1255bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1256 unsigned Depth) const { 1257 APInt KnownZero, KnownOne; 1258 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1259 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1260 return (KnownZero & Mask) == Mask; 1261} 1262 1263/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1264/// known to be either zero or one and return them in the KnownZero/KnownOne 1265/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1266/// processing. 1267void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1268 APInt &KnownZero, APInt &KnownOne, 1269 unsigned Depth) const { 1270 unsigned BitWidth = Mask.getBitWidth(); 1271 assert(BitWidth == Op.getValueType().getSizeInBits() && 1272 "Mask size mismatches value type size!"); 1273 1274 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1275 if (Depth == 6 || Mask == 0) 1276 return; // Limit search depth. 1277 1278 APInt KnownZero2, KnownOne2; 1279 1280 switch (Op.getOpcode()) { 1281 case ISD::Constant: 1282 // We know all of the bits for a constant! 1283 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1284 KnownZero = ~KnownOne & Mask; 1285 return; 1286 case ISD::AND: 1287 // If either the LHS or the RHS are Zero, the result is zero. 1288 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1289 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1290 KnownZero2, KnownOne2, Depth+1); 1291 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1292 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1293 1294 // Output known-1 bits are only known if set in both the LHS & RHS. 1295 KnownOne &= KnownOne2; 1296 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1297 KnownZero |= KnownZero2; 1298 return; 1299 case ISD::OR: 1300 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1301 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1302 KnownZero2, KnownOne2, Depth+1); 1303 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1304 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1305 1306 // Output known-0 bits are only known if clear in both the LHS & RHS. 1307 KnownZero &= KnownZero2; 1308 // Output known-1 are known to be set if set in either the LHS | RHS. 1309 KnownOne |= KnownOne2; 1310 return; 1311 case ISD::XOR: { 1312 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1313 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1314 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1315 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1316 1317 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1318 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1319 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1320 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1321 KnownZero = KnownZeroOut; 1322 return; 1323 } 1324 case ISD::MUL: { 1325 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1326 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1327 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1328 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1329 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1330 1331 // If low bits are zero in either operand, output low known-0 bits. 1332 // Also compute a conserative estimate for high known-0 bits. 1333 // More trickiness is possible, but this is sufficient for the 1334 // interesting case of alignment computation. 1335 KnownOne.clear(); 1336 unsigned TrailZ = KnownZero.countTrailingOnes() + 1337 KnownZero2.countTrailingOnes(); 1338 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1339 KnownZero2.countLeadingOnes(), 1340 BitWidth) - BitWidth; 1341 1342 TrailZ = std::min(TrailZ, BitWidth); 1343 LeadZ = std::min(LeadZ, BitWidth); 1344 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1345 APInt::getHighBitsSet(BitWidth, LeadZ); 1346 KnownZero &= Mask; 1347 return; 1348 } 1349 case ISD::UDIV: { 1350 // For the purposes of computing leading zeros we can conservatively 1351 // treat a udiv as a logical right shift by the power of 2 known to 1352 // be less than the denominator. 1353 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1354 ComputeMaskedBits(Op.getOperand(0), 1355 AllOnes, KnownZero2, KnownOne2, Depth+1); 1356 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1357 1358 KnownOne2.clear(); 1359 KnownZero2.clear(); 1360 ComputeMaskedBits(Op.getOperand(1), 1361 AllOnes, KnownZero2, KnownOne2, Depth+1); 1362 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1363 if (RHSUnknownLeadingOnes != BitWidth) 1364 LeadZ = std::min(BitWidth, 1365 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1366 1367 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1368 return; 1369 } 1370 case ISD::SELECT: 1371 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1372 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1373 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1374 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1375 1376 // Only known if known in both the LHS and RHS. 1377 KnownOne &= KnownOne2; 1378 KnownZero &= KnownZero2; 1379 return; 1380 case ISD::SELECT_CC: 1381 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1382 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1383 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1384 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1385 1386 // Only known if known in both the LHS and RHS. 1387 KnownOne &= KnownOne2; 1388 KnownZero &= KnownZero2; 1389 return; 1390 case ISD::SETCC: 1391 // If we know the result of a setcc has the top bits zero, use this info. 1392 if (TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult && 1393 BitWidth > 1) 1394 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1395 return; 1396 case ISD::SHL: 1397 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1398 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1399 unsigned ShAmt = SA->getValue(); 1400 1401 // If the shift count is an invalid immediate, don't do anything. 1402 if (ShAmt >= BitWidth) 1403 return; 1404 1405 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1406 KnownZero, KnownOne, Depth+1); 1407 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1408 KnownZero <<= ShAmt; 1409 KnownOne <<= ShAmt; 1410 // low bits known zero. 1411 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1412 } 1413 return; 1414 case ISD::SRL: 1415 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1416 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1417 unsigned ShAmt = SA->getValue(); 1418 1419 // If the shift count is an invalid immediate, don't do anything. 1420 if (ShAmt >= BitWidth) 1421 return; 1422 1423 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1424 KnownZero, KnownOne, Depth+1); 1425 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1426 KnownZero = KnownZero.lshr(ShAmt); 1427 KnownOne = KnownOne.lshr(ShAmt); 1428 1429 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1430 KnownZero |= HighBits; // High bits known zero. 1431 } 1432 return; 1433 case ISD::SRA: 1434 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1435 unsigned ShAmt = SA->getValue(); 1436 1437 // If the shift count is an invalid immediate, don't do anything. 1438 if (ShAmt >= BitWidth) 1439 return; 1440 1441 APInt InDemandedMask = (Mask << ShAmt); 1442 // If any of the demanded bits are produced by the sign extension, we also 1443 // demand the input sign bit. 1444 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1445 if (HighBits.getBoolValue()) 1446 InDemandedMask |= APInt::getSignBit(BitWidth); 1447 1448 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1449 Depth+1); 1450 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1451 KnownZero = KnownZero.lshr(ShAmt); 1452 KnownOne = KnownOne.lshr(ShAmt); 1453 1454 // Handle the sign bits. 1455 APInt SignBit = APInt::getSignBit(BitWidth); 1456 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1457 1458 if (KnownZero.intersects(SignBit)) { 1459 KnownZero |= HighBits; // New bits are known zero. 1460 } else if (KnownOne.intersects(SignBit)) { 1461 KnownOne |= HighBits; // New bits are known one. 1462 } 1463 } 1464 return; 1465 case ISD::SIGN_EXTEND_INREG: { 1466 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1467 unsigned EBits = EVT.getSizeInBits(); 1468 1469 // Sign extension. Compute the demanded bits in the result that are not 1470 // present in the input. 1471 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1472 1473 APInt InSignBit = APInt::getSignBit(EBits); 1474 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1475 1476 // If the sign extended bits are demanded, we know that the sign 1477 // bit is demanded. 1478 InSignBit.zext(BitWidth); 1479 if (NewBits.getBoolValue()) 1480 InputDemandedBits |= InSignBit; 1481 1482 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1483 KnownZero, KnownOne, Depth+1); 1484 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1485 1486 // If the sign bit of the input is known set or clear, then we know the 1487 // top bits of the result. 1488 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1489 KnownZero |= NewBits; 1490 KnownOne &= ~NewBits; 1491 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1492 KnownOne |= NewBits; 1493 KnownZero &= ~NewBits; 1494 } else { // Input sign bit unknown 1495 KnownZero &= ~NewBits; 1496 KnownOne &= ~NewBits; 1497 } 1498 return; 1499 } 1500 case ISD::CTTZ: 1501 case ISD::CTLZ: 1502 case ISD::CTPOP: { 1503 unsigned LowBits = Log2_32(BitWidth)+1; 1504 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1505 KnownOne.clear(); 1506 return; 1507 } 1508 case ISD::LOAD: { 1509 if (ISD::isZEXTLoad(Op.Val)) { 1510 LoadSDNode *LD = cast<LoadSDNode>(Op); 1511 MVT VT = LD->getMemoryVT(); 1512 unsigned MemBits = VT.getSizeInBits(); 1513 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1514 } 1515 return; 1516 } 1517 case ISD::ZERO_EXTEND: { 1518 MVT InVT = Op.getOperand(0).getValueType(); 1519 unsigned InBits = InVT.getSizeInBits(); 1520 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1521 APInt InMask = Mask; 1522 InMask.trunc(InBits); 1523 KnownZero.trunc(InBits); 1524 KnownOne.trunc(InBits); 1525 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1526 KnownZero.zext(BitWidth); 1527 KnownOne.zext(BitWidth); 1528 KnownZero |= NewBits; 1529 return; 1530 } 1531 case ISD::SIGN_EXTEND: { 1532 MVT InVT = Op.getOperand(0).getValueType(); 1533 unsigned InBits = InVT.getSizeInBits(); 1534 APInt InSignBit = APInt::getSignBit(InBits); 1535 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1536 APInt InMask = Mask; 1537 InMask.trunc(InBits); 1538 1539 // If any of the sign extended bits are demanded, we know that the sign 1540 // bit is demanded. Temporarily set this bit in the mask for our callee. 1541 if (NewBits.getBoolValue()) 1542 InMask |= InSignBit; 1543 1544 KnownZero.trunc(InBits); 1545 KnownOne.trunc(InBits); 1546 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1547 1548 // Note if the sign bit is known to be zero or one. 1549 bool SignBitKnownZero = KnownZero.isNegative(); 1550 bool SignBitKnownOne = KnownOne.isNegative(); 1551 assert(!(SignBitKnownZero && SignBitKnownOne) && 1552 "Sign bit can't be known to be both zero and one!"); 1553 1554 // If the sign bit wasn't actually demanded by our caller, we don't 1555 // want it set in the KnownZero and KnownOne result values. Reset the 1556 // mask and reapply it to the result values. 1557 InMask = Mask; 1558 InMask.trunc(InBits); 1559 KnownZero &= InMask; 1560 KnownOne &= InMask; 1561 1562 KnownZero.zext(BitWidth); 1563 KnownOne.zext(BitWidth); 1564 1565 // If the sign bit is known zero or one, the top bits match. 1566 if (SignBitKnownZero) 1567 KnownZero |= NewBits; 1568 else if (SignBitKnownOne) 1569 KnownOne |= NewBits; 1570 return; 1571 } 1572 case ISD::ANY_EXTEND: { 1573 MVT InVT = Op.getOperand(0).getValueType(); 1574 unsigned InBits = InVT.getSizeInBits(); 1575 APInt InMask = Mask; 1576 InMask.trunc(InBits); 1577 KnownZero.trunc(InBits); 1578 KnownOne.trunc(InBits); 1579 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1580 KnownZero.zext(BitWidth); 1581 KnownOne.zext(BitWidth); 1582 return; 1583 } 1584 case ISD::TRUNCATE: { 1585 MVT InVT = Op.getOperand(0).getValueType(); 1586 unsigned InBits = InVT.getSizeInBits(); 1587 APInt InMask = Mask; 1588 InMask.zext(InBits); 1589 KnownZero.zext(InBits); 1590 KnownOne.zext(InBits); 1591 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1592 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1593 KnownZero.trunc(BitWidth); 1594 KnownOne.trunc(BitWidth); 1595 break; 1596 } 1597 case ISD::AssertZext: { 1598 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1599 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1600 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1601 KnownOne, Depth+1); 1602 KnownZero |= (~InMask) & Mask; 1603 return; 1604 } 1605 case ISD::FGETSIGN: 1606 // All bits are zero except the low bit. 1607 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1608 return; 1609 1610 case ISD::SUB: { 1611 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1612 // We know that the top bits of C-X are clear if X contains less bits 1613 // than C (i.e. no wrap-around can happen). For example, 20-X is 1614 // positive if we can prove that X is >= 0 and < 16. 1615 if (CLHS->getAPIntValue().isNonNegative()) { 1616 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1617 // NLZ can't be BitWidth with no sign bit 1618 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1619 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1620 Depth+1); 1621 1622 // If all of the MaskV bits are known to be zero, then we know the 1623 // output top bits are zero, because we now know that the output is 1624 // from [0-C]. 1625 if ((KnownZero2 & MaskV) == MaskV) { 1626 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1627 // Top bits known zero. 1628 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1629 } 1630 } 1631 } 1632 } 1633 // fall through 1634 case ISD::ADD: { 1635 // Output known-0 bits are known if clear or set in both the low clear bits 1636 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1637 // low 3 bits clear. 1638 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1639 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1640 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1641 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1642 1643 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1644 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1645 KnownZeroOut = std::min(KnownZeroOut, 1646 KnownZero2.countTrailingOnes()); 1647 1648 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1649 return; 1650 } 1651 case ISD::SREM: 1652 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1653 const APInt &RA = Rem->getAPIntValue(); 1654 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1655 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1656 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1657 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1658 1659 // The sign of a remainder is equal to the sign of the first 1660 // operand (zero being positive). 1661 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1662 KnownZero2 |= ~LowBits; 1663 else if (KnownOne2[BitWidth-1]) 1664 KnownOne2 |= ~LowBits; 1665 1666 KnownZero |= KnownZero2 & Mask; 1667 KnownOne |= KnownOne2 & Mask; 1668 1669 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1670 } 1671 } 1672 return; 1673 case ISD::UREM: { 1674 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1675 const APInt &RA = Rem->getAPIntValue(); 1676 if (RA.isPowerOf2()) { 1677 APInt LowBits = (RA - 1); 1678 APInt Mask2 = LowBits & Mask; 1679 KnownZero |= ~LowBits & Mask; 1680 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1681 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1682 break; 1683 } 1684 } 1685 1686 // Since the result is less than or equal to either operand, any leading 1687 // zero bits in either operand must also exist in the result. 1688 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1689 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1690 Depth+1); 1691 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1692 Depth+1); 1693 1694 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1695 KnownZero2.countLeadingOnes()); 1696 KnownOne.clear(); 1697 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1698 return; 1699 } 1700 default: 1701 // Allow the target to implement this method for its nodes. 1702 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1703 case ISD::INTRINSIC_WO_CHAIN: 1704 case ISD::INTRINSIC_W_CHAIN: 1705 case ISD::INTRINSIC_VOID: 1706 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1707 } 1708 return; 1709 } 1710} 1711 1712/// ComputeNumSignBits - Return the number of times the sign bit of the 1713/// register is replicated into the other bits. We know that at least 1 bit 1714/// is always equal to the sign bit (itself), but other cases can give us 1715/// information. For example, immediately after an "SRA X, 2", we know that 1716/// the top 3 bits are all equal to each other, so we return 3. 1717unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1718 MVT VT = Op.getValueType(); 1719 assert(VT.isInteger() && "Invalid VT!"); 1720 unsigned VTBits = VT.getSizeInBits(); 1721 unsigned Tmp, Tmp2; 1722 unsigned FirstAnswer = 1; 1723 1724 if (Depth == 6) 1725 return 1; // Limit search depth. 1726 1727 switch (Op.getOpcode()) { 1728 default: break; 1729 case ISD::AssertSext: 1730 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1731 return VTBits-Tmp+1; 1732 case ISD::AssertZext: 1733 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1734 return VTBits-Tmp; 1735 1736 case ISD::Constant: { 1737 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1738 // If negative, return # leading ones. 1739 if (Val.isNegative()) 1740 return Val.countLeadingOnes(); 1741 1742 // Return # leading zeros. 1743 return Val.countLeadingZeros(); 1744 } 1745 1746 case ISD::SIGN_EXTEND: 1747 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1748 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1749 1750 case ISD::SIGN_EXTEND_INREG: 1751 // Max of the input and what this extends. 1752 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1753 Tmp = VTBits-Tmp+1; 1754 1755 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1756 return std::max(Tmp, Tmp2); 1757 1758 case ISD::SRA: 1759 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1760 // SRA X, C -> adds C sign bits. 1761 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1762 Tmp += C->getValue(); 1763 if (Tmp > VTBits) Tmp = VTBits; 1764 } 1765 return Tmp; 1766 case ISD::SHL: 1767 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1768 // shl destroys sign bits. 1769 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1770 if (C->getValue() >= VTBits || // Bad shift. 1771 C->getValue() >= Tmp) break; // Shifted all sign bits out. 1772 return Tmp - C->getValue(); 1773 } 1774 break; 1775 case ISD::AND: 1776 case ISD::OR: 1777 case ISD::XOR: // NOT is handled here. 1778 // Logical binary ops preserve the number of sign bits at the worst. 1779 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1780 if (Tmp != 1) { 1781 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1782 FirstAnswer = std::min(Tmp, Tmp2); 1783 // We computed what we know about the sign bits as our first 1784 // answer. Now proceed to the generic code that uses 1785 // ComputeMaskedBits, and pick whichever answer is better. 1786 } 1787 break; 1788 1789 case ISD::SELECT: 1790 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1791 if (Tmp == 1) return 1; // Early out. 1792 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1793 return std::min(Tmp, Tmp2); 1794 1795 case ISD::SETCC: 1796 // If setcc returns 0/-1, all bits are sign bits. 1797 if (TLI.getSetCCResultContents() == 1798 TargetLowering::ZeroOrNegativeOneSetCCResult) 1799 return VTBits; 1800 break; 1801 case ISD::ROTL: 1802 case ISD::ROTR: 1803 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1804 unsigned RotAmt = C->getValue() & (VTBits-1); 1805 1806 // Handle rotate right by N like a rotate left by 32-N. 1807 if (Op.getOpcode() == ISD::ROTR) 1808 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1809 1810 // If we aren't rotating out all of the known-in sign bits, return the 1811 // number that are left. This handles rotl(sext(x), 1) for example. 1812 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1813 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1814 } 1815 break; 1816 case ISD::ADD: 1817 // Add can have at most one carry bit. Thus we know that the output 1818 // is, at worst, one more bit than the inputs. 1819 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1820 if (Tmp == 1) return 1; // Early out. 1821 1822 // Special case decrementing a value (ADD X, -1): 1823 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1824 if (CRHS->isAllOnesValue()) { 1825 APInt KnownZero, KnownOne; 1826 APInt Mask = APInt::getAllOnesValue(VTBits); 1827 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1828 1829 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1830 // sign bits set. 1831 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1832 return VTBits; 1833 1834 // If we are subtracting one from a positive number, there is no carry 1835 // out of the result. 1836 if (KnownZero.isNegative()) 1837 return Tmp; 1838 } 1839 1840 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1841 if (Tmp2 == 1) return 1; 1842 return std::min(Tmp, Tmp2)-1; 1843 break; 1844 1845 case ISD::SUB: 1846 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1847 if (Tmp2 == 1) return 1; 1848 1849 // Handle NEG. 1850 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1851 if (CLHS->isNullValue()) { 1852 APInt KnownZero, KnownOne; 1853 APInt Mask = APInt::getAllOnesValue(VTBits); 1854 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1855 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1856 // sign bits set. 1857 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1858 return VTBits; 1859 1860 // If the input is known to be positive (the sign bit is known clear), 1861 // the output of the NEG has the same number of sign bits as the input. 1862 if (KnownZero.isNegative()) 1863 return Tmp2; 1864 1865 // Otherwise, we treat this like a SUB. 1866 } 1867 1868 // Sub can have at most one carry bit. Thus we know that the output 1869 // is, at worst, one more bit than the inputs. 1870 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1871 if (Tmp == 1) return 1; // Early out. 1872 return std::min(Tmp, Tmp2)-1; 1873 break; 1874 case ISD::TRUNCATE: 1875 // FIXME: it's tricky to do anything useful for this, but it is an important 1876 // case for targets like X86. 1877 break; 1878 } 1879 1880 // Handle LOADX separately here. EXTLOAD case will fallthrough. 1881 if (Op.getOpcode() == ISD::LOAD) { 1882 LoadSDNode *LD = cast<LoadSDNode>(Op); 1883 unsigned ExtType = LD->getExtensionType(); 1884 switch (ExtType) { 1885 default: break; 1886 case ISD::SEXTLOAD: // '17' bits known 1887 Tmp = LD->getMemoryVT().getSizeInBits(); 1888 return VTBits-Tmp+1; 1889 case ISD::ZEXTLOAD: // '16' bits known 1890 Tmp = LD->getMemoryVT().getSizeInBits(); 1891 return VTBits-Tmp; 1892 } 1893 } 1894 1895 // Allow the target to implement this method for its nodes. 1896 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 1897 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1898 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1899 Op.getOpcode() == ISD::INTRINSIC_VOID) { 1900 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 1901 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 1902 } 1903 1904 // Finally, if we can prove that the top bits of the result are 0's or 1's, 1905 // use this information. 1906 APInt KnownZero, KnownOne; 1907 APInt Mask = APInt::getAllOnesValue(VTBits); 1908 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1909 1910 if (KnownZero.isNegative()) { // sign bit is 0 1911 Mask = KnownZero; 1912 } else if (KnownOne.isNegative()) { // sign bit is 1; 1913 Mask = KnownOne; 1914 } else { 1915 // Nothing known. 1916 return FirstAnswer; 1917 } 1918 1919 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 1920 // the number of identical bits in the top of the input value. 1921 Mask = ~Mask; 1922 Mask <<= Mask.getBitWidth()-VTBits; 1923 // Return # leading zeros. We use 'min' here in case Val was zero before 1924 // shifting. We don't want to return '64' as for an i32 "0". 1925 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 1926} 1927 1928 1929bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 1930 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 1931 if (!GA) return false; 1932 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 1933 if (!GV) return false; 1934 MachineModuleInfo *MMI = getMachineModuleInfo(); 1935 return MMI && MMI->hasDebugInfo() && MMI->isVerified(GV); 1936} 1937 1938 1939/// getShuffleScalarElt - Returns the scalar element that will make up the ith 1940/// element of the result of the vector shuffle. 1941SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 1942 MVT VT = N->getValueType(0); 1943 SDValue PermMask = N->getOperand(2); 1944 SDValue Idx = PermMask.getOperand(i); 1945 if (Idx.getOpcode() == ISD::UNDEF) 1946 return getNode(ISD::UNDEF, VT.getVectorElementType()); 1947 unsigned Index = cast<ConstantSDNode>(Idx)->getValue(); 1948 unsigned NumElems = PermMask.getNumOperands(); 1949 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 1950 Index %= NumElems; 1951 1952 if (V.getOpcode() == ISD::BIT_CONVERT) { 1953 V = V.getOperand(0); 1954 if (V.getValueType().getVectorNumElements() != NumElems) 1955 return SDValue(); 1956 } 1957 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 1958 return (Index == 0) ? V.getOperand(0) 1959 : getNode(ISD::UNDEF, VT.getVectorElementType()); 1960 if (V.getOpcode() == ISD::BUILD_VECTOR) 1961 return V.getOperand(Index); 1962 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 1963 return getShuffleScalarElt(V.Val, Index); 1964 return SDValue(); 1965} 1966 1967 1968/// getNode - Gets or creates the specified node. 1969/// 1970SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) { 1971 FoldingSetNodeID ID; 1972 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 1973 void *IP = 0; 1974 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1975 return SDValue(E, 0); 1976 SDNode *N = NodeAllocator.Allocate<SDNode>(); 1977 new (N) SDNode(Opcode, SDNode::getSDVTList(VT)); 1978 CSEMap.InsertNode(N, IP); 1979 1980 AllNodes.push_back(N); 1981#ifndef NDEBUG 1982 VerifyNode(N); 1983#endif 1984 return SDValue(N, 0); 1985} 1986 1987SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) { 1988 // Constant fold unary operations with an integer constant operand. 1989 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) { 1990 const APInt &Val = C->getAPIntValue(); 1991 unsigned BitWidth = VT.getSizeInBits(); 1992 switch (Opcode) { 1993 default: break; 1994 case ISD::SIGN_EXTEND: 1995 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 1996 case ISD::ANY_EXTEND: 1997 case ISD::ZERO_EXTEND: 1998 case ISD::TRUNCATE: 1999 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2000 case ISD::UINT_TO_FP: 2001 case ISD::SINT_TO_FP: { 2002 const uint64_t zero[] = {0, 0}; 2003 // No compile time operations on this type. 2004 if (VT==MVT::ppcf128) 2005 break; 2006 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2007 (void)apf.convertFromAPInt(Val, 2008 Opcode==ISD::SINT_TO_FP, 2009 APFloat::rmNearestTiesToEven); 2010 return getConstantFP(apf, VT); 2011 } 2012 case ISD::BIT_CONVERT: 2013 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2014 return getConstantFP(Val.bitsToFloat(), VT); 2015 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2016 return getConstantFP(Val.bitsToDouble(), VT); 2017 break; 2018 case ISD::BSWAP: 2019 return getConstant(Val.byteSwap(), VT); 2020 case ISD::CTPOP: 2021 return getConstant(Val.countPopulation(), VT); 2022 case ISD::CTLZ: 2023 return getConstant(Val.countLeadingZeros(), VT); 2024 case ISD::CTTZ: 2025 return getConstant(Val.countTrailingZeros(), VT); 2026 } 2027 } 2028 2029 // Constant fold unary operations with a floating point constant operand. 2030 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) { 2031 APFloat V = C->getValueAPF(); // make copy 2032 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2033 switch (Opcode) { 2034 case ISD::FNEG: 2035 V.changeSign(); 2036 return getConstantFP(V, VT); 2037 case ISD::FABS: 2038 V.clearSign(); 2039 return getConstantFP(V, VT); 2040 case ISD::FP_ROUND: 2041 case ISD::FP_EXTEND: 2042 // This can return overflow, underflow, or inexact; we don't care. 2043 // FIXME need to be more flexible about rounding mode. 2044 (void)V.convert(*MVTToAPFloatSemantics(VT), 2045 APFloat::rmNearestTiesToEven); 2046 return getConstantFP(V, VT); 2047 case ISD::FP_TO_SINT: 2048 case ISD::FP_TO_UINT: { 2049 integerPart x; 2050 assert(integerPartWidth >= 64); 2051 // FIXME need to be more flexible about rounding mode. 2052 APFloat::opStatus s = V.convertToInteger(&x, 64U, 2053 Opcode==ISD::FP_TO_SINT, 2054 APFloat::rmTowardZero); 2055 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2056 break; 2057 return getConstant(x, VT); 2058 } 2059 case ISD::BIT_CONVERT: 2060 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2061 return getConstant((uint32_t)V.convertToAPInt().getZExtValue(), VT); 2062 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2063 return getConstant(V.convertToAPInt().getZExtValue(), VT); 2064 break; 2065 } 2066 } 2067 } 2068 2069 unsigned OpOpcode = Operand.Val->getOpcode(); 2070 switch (Opcode) { 2071 case ISD::TokenFactor: 2072 return Operand; // Factor of one node? No need. 2073 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2074 case ISD::FP_EXTEND: 2075 assert(VT.isFloatingPoint() && 2076 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2077 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2078 if (Operand.getOpcode() == ISD::UNDEF) 2079 return getNode(ISD::UNDEF, VT); 2080 break; 2081 case ISD::SIGN_EXTEND: 2082 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2083 "Invalid SIGN_EXTEND!"); 2084 if (Operand.getValueType() == VT) return Operand; // noop extension 2085 assert(Operand.getValueType().bitsLT(VT) 2086 && "Invalid sext node, dst < src!"); 2087 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2088 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 2089 break; 2090 case ISD::ZERO_EXTEND: 2091 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2092 "Invalid ZERO_EXTEND!"); 2093 if (Operand.getValueType() == VT) return Operand; // noop extension 2094 assert(Operand.getValueType().bitsLT(VT) 2095 && "Invalid zext node, dst < src!"); 2096 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2097 return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); 2098 break; 2099 case ISD::ANY_EXTEND: 2100 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2101 "Invalid ANY_EXTEND!"); 2102 if (Operand.getValueType() == VT) return Operand; // noop extension 2103 assert(Operand.getValueType().bitsLT(VT) 2104 && "Invalid anyext node, dst < src!"); 2105 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2106 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2107 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 2108 break; 2109 case ISD::TRUNCATE: 2110 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2111 "Invalid TRUNCATE!"); 2112 if (Operand.getValueType() == VT) return Operand; // noop truncate 2113 assert(Operand.getValueType().bitsGT(VT) 2114 && "Invalid truncate node, src < dst!"); 2115 if (OpOpcode == ISD::TRUNCATE) 2116 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 2117 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2118 OpOpcode == ISD::ANY_EXTEND) { 2119 // If the source is smaller than the dest, we still need an extend. 2120 if (Operand.Val->getOperand(0).getValueType().bitsLT(VT)) 2121 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 2122 else if (Operand.Val->getOperand(0).getValueType().bitsGT(VT)) 2123 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 2124 else 2125 return Operand.Val->getOperand(0); 2126 } 2127 break; 2128 case ISD::BIT_CONVERT: 2129 // Basic sanity checking. 2130 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2131 && "Cannot BIT_CONVERT between types of different sizes!"); 2132 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2133 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2134 return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0)); 2135 if (OpOpcode == ISD::UNDEF) 2136 return getNode(ISD::UNDEF, VT); 2137 break; 2138 case ISD::SCALAR_TO_VECTOR: 2139 assert(VT.isVector() && !Operand.getValueType().isVector() && 2140 VT.getVectorElementType() == Operand.getValueType() && 2141 "Illegal SCALAR_TO_VECTOR node!"); 2142 if (OpOpcode == ISD::UNDEF) 2143 return getNode(ISD::UNDEF, VT); 2144 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2145 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2146 isa<ConstantSDNode>(Operand.getOperand(1)) && 2147 Operand.getConstantOperandVal(1) == 0 && 2148 Operand.getOperand(0).getValueType() == VT) 2149 return Operand.getOperand(0); 2150 break; 2151 case ISD::FNEG: 2152 if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X) 2153 return getNode(ISD::FSUB, VT, Operand.Val->getOperand(1), 2154 Operand.Val->getOperand(0)); 2155 if (OpOpcode == ISD::FNEG) // --X -> X 2156 return Operand.Val->getOperand(0); 2157 break; 2158 case ISD::FABS: 2159 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2160 return getNode(ISD::FABS, VT, Operand.Val->getOperand(0)); 2161 break; 2162 } 2163 2164 SDNode *N; 2165 SDVTList VTs = getVTList(VT); 2166 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2167 FoldingSetNodeID ID; 2168 SDValue Ops[1] = { Operand }; 2169 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2170 void *IP = 0; 2171 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2172 return SDValue(E, 0); 2173 N = NodeAllocator.Allocate<UnarySDNode>(); 2174 new (N) UnarySDNode(Opcode, VTs, Operand); 2175 CSEMap.InsertNode(N, IP); 2176 } else { 2177 N = NodeAllocator.Allocate<UnarySDNode>(); 2178 new (N) UnarySDNode(Opcode, VTs, Operand); 2179 } 2180 2181 AllNodes.push_back(N); 2182#ifndef NDEBUG 2183 VerifyNode(N); 2184#endif 2185 return SDValue(N, 0); 2186} 2187 2188SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2189 SDValue N1, SDValue N2) { 2190 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 2191 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 2192 switch (Opcode) { 2193 default: break; 2194 case ISD::TokenFactor: 2195 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2196 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2197 // Fold trivial token factors. 2198 if (N1.getOpcode() == ISD::EntryToken) return N2; 2199 if (N2.getOpcode() == ISD::EntryToken) return N1; 2200 break; 2201 case ISD::AND: 2202 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2203 N1.getValueType() == VT && "Binary operator types must match!"); 2204 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2205 // worth handling here. 2206 if (N2C && N2C->isNullValue()) 2207 return N2; 2208 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2209 return N1; 2210 break; 2211 case ISD::OR: 2212 case ISD::XOR: 2213 case ISD::ADD: 2214 case ISD::SUB: 2215 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2216 N1.getValueType() == VT && "Binary operator types must match!"); 2217 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2218 // it's worth handling here. 2219 if (N2C && N2C->isNullValue()) 2220 return N1; 2221 break; 2222 case ISD::UDIV: 2223 case ISD::UREM: 2224 case ISD::MULHU: 2225 case ISD::MULHS: 2226 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2227 // fall through 2228 case ISD::MUL: 2229 case ISD::SDIV: 2230 case ISD::SREM: 2231 case ISD::FADD: 2232 case ISD::FSUB: 2233 case ISD::FMUL: 2234 case ISD::FDIV: 2235 case ISD::FREM: 2236 assert(N1.getValueType() == N2.getValueType() && 2237 N1.getValueType() == VT && "Binary operator types must match!"); 2238 break; 2239 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2240 assert(N1.getValueType() == VT && 2241 N1.getValueType().isFloatingPoint() && 2242 N2.getValueType().isFloatingPoint() && 2243 "Invalid FCOPYSIGN!"); 2244 break; 2245 case ISD::SHL: 2246 case ISD::SRA: 2247 case ISD::SRL: 2248 case ISD::ROTL: 2249 case ISD::ROTR: 2250 assert(VT == N1.getValueType() && 2251 "Shift operators return type must be the same as their first arg"); 2252 assert(VT.isInteger() && N2.getValueType().isInteger() && 2253 "Shifts only work on integers"); 2254 2255 // Always fold shifts of i1 values so the code generator doesn't need to 2256 // handle them. Since we know the size of the shift has to be less than the 2257 // size of the value, the shift/rotate count is guaranteed to be zero. 2258 if (VT == MVT::i1) 2259 return N1; 2260 break; 2261 case ISD::FP_ROUND_INREG: { 2262 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2263 assert(VT == N1.getValueType() && "Not an inreg round!"); 2264 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2265 "Cannot FP_ROUND_INREG integer types"); 2266 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2267 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2268 break; 2269 } 2270 case ISD::FP_ROUND: 2271 assert(VT.isFloatingPoint() && 2272 N1.getValueType().isFloatingPoint() && 2273 VT.bitsLE(N1.getValueType()) && 2274 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2275 if (N1.getValueType() == VT) return N1; // noop conversion. 2276 break; 2277 case ISD::AssertSext: 2278 case ISD::AssertZext: { 2279 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2280 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2281 assert(VT.isInteger() && EVT.isInteger() && 2282 "Cannot *_EXTEND_INREG FP types"); 2283 assert(EVT.bitsLE(VT) && "Not extending!"); 2284 if (VT == EVT) return N1; // noop assertion. 2285 break; 2286 } 2287 case ISD::SIGN_EXTEND_INREG: { 2288 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2289 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2290 assert(VT.isInteger() && EVT.isInteger() && 2291 "Cannot *_EXTEND_INREG FP types"); 2292 assert(EVT.bitsLE(VT) && "Not extending!"); 2293 if (EVT == VT) return N1; // Not actually extending 2294 2295 if (N1C) { 2296 APInt Val = N1C->getAPIntValue(); 2297 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2298 Val <<= Val.getBitWidth()-FromBits; 2299 Val = Val.ashr(Val.getBitWidth()-FromBits); 2300 return getConstant(Val, VT); 2301 } 2302 break; 2303 } 2304 case ISD::EXTRACT_VECTOR_ELT: 2305 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2306 if (N1.getOpcode() == ISD::UNDEF) 2307 return getNode(ISD::UNDEF, VT); 2308 2309 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2310 // expanding copies of large vectors from registers. 2311 if (N2C && 2312 N1.getOpcode() == ISD::CONCAT_VECTORS && 2313 N1.getNumOperands() > 0) { 2314 unsigned Factor = 2315 N1.getOperand(0).getValueType().getVectorNumElements(); 2316 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, 2317 N1.getOperand(N2C->getValue() / Factor), 2318 getConstant(N2C->getValue() % Factor, N2.getValueType())); 2319 } 2320 2321 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2322 // expanding large vector constants. 2323 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) 2324 return N1.getOperand(N2C->getValue()); 2325 2326 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2327 // operations are lowered to scalars. 2328 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2329 if (N1.getOperand(2) == N2) 2330 return N1.getOperand(1); 2331 else 2332 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2); 2333 } 2334 break; 2335 case ISD::EXTRACT_ELEMENT: 2336 assert(N2C && (unsigned)N2C->getValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2337 assert(!N1.getValueType().isVector() && !VT.isVector() && 2338 (N1.getValueType().isInteger() == VT.isInteger()) && 2339 "Wrong types for EXTRACT_ELEMENT!"); 2340 2341 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2342 // 64-bit integers into 32-bit parts. Instead of building the extract of 2343 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2344 if (N1.getOpcode() == ISD::BUILD_PAIR) 2345 return N1.getOperand(N2C->getValue()); 2346 2347 // EXTRACT_ELEMENT of a constant int is also very common. 2348 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2349 unsigned ElementSize = VT.getSizeInBits(); 2350 unsigned Shift = ElementSize * N2C->getValue(); 2351 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2352 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2353 } 2354 break; 2355 case ISD::EXTRACT_SUBVECTOR: 2356 if (N1.getValueType() == VT) // Trivial extraction. 2357 return N1; 2358 break; 2359 } 2360 2361 if (N1C) { 2362 if (N2C) { 2363 const APInt &C1 = N1C->getAPIntValue(), &C2 = N2C->getAPIntValue(); 2364 switch (Opcode) { 2365 case ISD::ADD: return getConstant(C1 + C2, VT); 2366 case ISD::SUB: return getConstant(C1 - C2, VT); 2367 case ISD::MUL: return getConstant(C1 * C2, VT); 2368 case ISD::UDIV: 2369 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2370 break; 2371 case ISD::UREM : 2372 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2373 break; 2374 case ISD::SDIV : 2375 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2376 break; 2377 case ISD::SREM : 2378 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2379 break; 2380 case ISD::AND : return getConstant(C1 & C2, VT); 2381 case ISD::OR : return getConstant(C1 | C2, VT); 2382 case ISD::XOR : return getConstant(C1 ^ C2, VT); 2383 case ISD::SHL : return getConstant(C1 << C2, VT); 2384 case ISD::SRL : return getConstant(C1.lshr(C2), VT); 2385 case ISD::SRA : return getConstant(C1.ashr(C2), VT); 2386 case ISD::ROTL : return getConstant(C1.rotl(C2), VT); 2387 case ISD::ROTR : return getConstant(C1.rotr(C2), VT); 2388 default: break; 2389 } 2390 } else { // Cannonicalize constant to RHS if commutative 2391 if (isCommutativeBinOp(Opcode)) { 2392 std::swap(N1C, N2C); 2393 std::swap(N1, N2); 2394 } 2395 } 2396 } 2397 2398 // Constant fold FP operations. 2399 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 2400 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val); 2401 if (N1CFP) { 2402 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2403 // Cannonicalize constant to RHS if commutative 2404 std::swap(N1CFP, N2CFP); 2405 std::swap(N1, N2); 2406 } else if (N2CFP && VT != MVT::ppcf128) { 2407 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2408 APFloat::opStatus s; 2409 switch (Opcode) { 2410 case ISD::FADD: 2411 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2412 if (s != APFloat::opInvalidOp) 2413 return getConstantFP(V1, VT); 2414 break; 2415 case ISD::FSUB: 2416 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2417 if (s!=APFloat::opInvalidOp) 2418 return getConstantFP(V1, VT); 2419 break; 2420 case ISD::FMUL: 2421 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2422 if (s!=APFloat::opInvalidOp) 2423 return getConstantFP(V1, VT); 2424 break; 2425 case ISD::FDIV: 2426 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2427 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2428 return getConstantFP(V1, VT); 2429 break; 2430 case ISD::FREM : 2431 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2432 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2433 return getConstantFP(V1, VT); 2434 break; 2435 case ISD::FCOPYSIGN: 2436 V1.copySign(V2); 2437 return getConstantFP(V1, VT); 2438 default: break; 2439 } 2440 } 2441 } 2442 2443 // Canonicalize an UNDEF to the RHS, even over a constant. 2444 if (N1.getOpcode() == ISD::UNDEF) { 2445 if (isCommutativeBinOp(Opcode)) { 2446 std::swap(N1, N2); 2447 } else { 2448 switch (Opcode) { 2449 case ISD::FP_ROUND_INREG: 2450 case ISD::SIGN_EXTEND_INREG: 2451 case ISD::SUB: 2452 case ISD::FSUB: 2453 case ISD::FDIV: 2454 case ISD::FREM: 2455 case ISD::SRA: 2456 return N1; // fold op(undef, arg2) -> undef 2457 case ISD::UDIV: 2458 case ISD::SDIV: 2459 case ISD::UREM: 2460 case ISD::SREM: 2461 case ISD::SRL: 2462 case ISD::SHL: 2463 if (!VT.isVector()) 2464 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2465 // For vectors, we can't easily build an all zero vector, just return 2466 // the LHS. 2467 return N2; 2468 } 2469 } 2470 } 2471 2472 // Fold a bunch of operators when the RHS is undef. 2473 if (N2.getOpcode() == ISD::UNDEF) { 2474 switch (Opcode) { 2475 case ISD::XOR: 2476 if (N1.getOpcode() == ISD::UNDEF) 2477 // Handle undef ^ undef -> 0 special case. This is a common 2478 // idiom (misuse). 2479 return getConstant(0, VT); 2480 // fallthrough 2481 case ISD::ADD: 2482 case ISD::ADDC: 2483 case ISD::ADDE: 2484 case ISD::SUB: 2485 case ISD::FADD: 2486 case ISD::FSUB: 2487 case ISD::FMUL: 2488 case ISD::FDIV: 2489 case ISD::FREM: 2490 case ISD::UDIV: 2491 case ISD::SDIV: 2492 case ISD::UREM: 2493 case ISD::SREM: 2494 return N2; // fold op(arg1, undef) -> undef 2495 case ISD::MUL: 2496 case ISD::AND: 2497 case ISD::SRL: 2498 case ISD::SHL: 2499 if (!VT.isVector()) 2500 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2501 // For vectors, we can't easily build an all zero vector, just return 2502 // the LHS. 2503 return N1; 2504 case ISD::OR: 2505 if (!VT.isVector()) 2506 return getConstant(VT.getIntegerVTBitMask(), VT); 2507 // For vectors, we can't easily build an all one vector, just return 2508 // the LHS. 2509 return N1; 2510 case ISD::SRA: 2511 return N1; 2512 } 2513 } 2514 2515 // Memoize this node if possible. 2516 SDNode *N; 2517 SDVTList VTs = getVTList(VT); 2518 if (VT != MVT::Flag) { 2519 SDValue Ops[] = { N1, N2 }; 2520 FoldingSetNodeID ID; 2521 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2522 void *IP = 0; 2523 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2524 return SDValue(E, 0); 2525 N = NodeAllocator.Allocate<BinarySDNode>(); 2526 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2527 CSEMap.InsertNode(N, IP); 2528 } else { 2529 N = NodeAllocator.Allocate<BinarySDNode>(); 2530 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2531 } 2532 2533 AllNodes.push_back(N); 2534#ifndef NDEBUG 2535 VerifyNode(N); 2536#endif 2537 return SDValue(N, 0); 2538} 2539 2540SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2541 SDValue N1, SDValue N2, SDValue N3) { 2542 // Perform various simplifications. 2543 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 2544 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 2545 switch (Opcode) { 2546 case ISD::SETCC: { 2547 // Use FoldSetCC to simplify SETCC's. 2548 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 2549 if (Simp.Val) return Simp; 2550 break; 2551 } 2552 case ISD::SELECT: 2553 if (N1C) { 2554 if (N1C->getValue()) 2555 return N2; // select true, X, Y -> X 2556 else 2557 return N3; // select false, X, Y -> Y 2558 } 2559 2560 if (N2 == N3) return N2; // select C, X, X -> X 2561 break; 2562 case ISD::BRCOND: 2563 if (N2C) { 2564 if (N2C->getValue()) // Unconditional branch 2565 return getNode(ISD::BR, MVT::Other, N1, N3); 2566 else 2567 return N1; // Never-taken branch 2568 } 2569 break; 2570 case ISD::VECTOR_SHUFFLE: 2571 assert(VT == N1.getValueType() && VT == N2.getValueType() && 2572 VT.isVector() && N3.getValueType().isVector() && 2573 N3.getOpcode() == ISD::BUILD_VECTOR && 2574 VT.getVectorNumElements() == N3.getNumOperands() && 2575 "Illegal VECTOR_SHUFFLE node!"); 2576 break; 2577 case ISD::BIT_CONVERT: 2578 // Fold bit_convert nodes from a type to themselves. 2579 if (N1.getValueType() == VT) 2580 return N1; 2581 break; 2582 } 2583 2584 // Memoize node if it doesn't produce a flag. 2585 SDNode *N; 2586 SDVTList VTs = getVTList(VT); 2587 if (VT != MVT::Flag) { 2588 SDValue Ops[] = { N1, N2, N3 }; 2589 FoldingSetNodeID ID; 2590 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2591 void *IP = 0; 2592 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2593 return SDValue(E, 0); 2594 N = NodeAllocator.Allocate<TernarySDNode>(); 2595 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2596 CSEMap.InsertNode(N, IP); 2597 } else { 2598 N = NodeAllocator.Allocate<TernarySDNode>(); 2599 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2600 } 2601 AllNodes.push_back(N); 2602#ifndef NDEBUG 2603 VerifyNode(N); 2604#endif 2605 return SDValue(N, 0); 2606} 2607 2608SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2609 SDValue N1, SDValue N2, SDValue N3, 2610 SDValue N4) { 2611 SDValue Ops[] = { N1, N2, N3, N4 }; 2612 return getNode(Opcode, VT, Ops, 4); 2613} 2614 2615SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2616 SDValue N1, SDValue N2, SDValue N3, 2617 SDValue N4, SDValue N5) { 2618 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2619 return getNode(Opcode, VT, Ops, 5); 2620} 2621 2622/// getMemsetValue - Vectorized representation of the memset value 2623/// operand. 2624static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) { 2625 unsigned NumBits = VT.isVector() ? 2626 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2627 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2628 APInt Val = APInt(NumBits, C->getValue() & 255); 2629 unsigned Shift = 8; 2630 for (unsigned i = NumBits; i > 8; i >>= 1) { 2631 Val = (Val << Shift) | Val; 2632 Shift <<= 1; 2633 } 2634 if (VT.isInteger()) 2635 return DAG.getConstant(Val, VT); 2636 return DAG.getConstantFP(APFloat(Val), VT); 2637 } 2638 2639 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 2640 unsigned Shift = 8; 2641 for (unsigned i = NumBits; i > 8; i >>= 1) { 2642 Value = DAG.getNode(ISD::OR, VT, 2643 DAG.getNode(ISD::SHL, VT, Value, 2644 DAG.getConstant(Shift, MVT::i8)), Value); 2645 Shift <<= 1; 2646 } 2647 2648 return Value; 2649} 2650 2651/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2652/// used when a memcpy is turned into a memset when the source is a constant 2653/// string ptr. 2654static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG, 2655 const TargetLowering &TLI, 2656 std::string &Str, unsigned Offset) { 2657 // Handle vector with all elements zero. 2658 if (Str.empty()) { 2659 if (VT.isInteger()) 2660 return DAG.getConstant(0, VT); 2661 unsigned NumElts = VT.getVectorNumElements(); 2662 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2663 return DAG.getNode(ISD::BIT_CONVERT, VT, 2664 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2665 } 2666 2667 assert(!VT.isVector() && "Can't handle vector type here!"); 2668 unsigned NumBits = VT.getSizeInBits(); 2669 unsigned MSB = NumBits / 8; 2670 uint64_t Val = 0; 2671 if (TLI.isLittleEndian()) 2672 Offset = Offset + MSB - 1; 2673 for (unsigned i = 0; i != MSB; ++i) { 2674 Val = (Val << 8) | (unsigned char)Str[Offset]; 2675 Offset += TLI.isLittleEndian() ? -1 : 1; 2676 } 2677 return DAG.getConstant(Val, VT); 2678} 2679 2680/// getMemBasePlusOffset - Returns base and offset node for the 2681/// 2682static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2683 SelectionDAG &DAG) { 2684 MVT VT = Base.getValueType(); 2685 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 2686} 2687 2688/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2689/// 2690static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2691 unsigned SrcDelta = 0; 2692 GlobalAddressSDNode *G = NULL; 2693 if (Src.getOpcode() == ISD::GlobalAddress) 2694 G = cast<GlobalAddressSDNode>(Src); 2695 else if (Src.getOpcode() == ISD::ADD && 2696 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2697 Src.getOperand(1).getOpcode() == ISD::Constant) { 2698 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2699 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getValue(); 2700 } 2701 if (!G) 2702 return false; 2703 2704 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2705 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 2706 return true; 2707 2708 return false; 2709} 2710 2711/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2712/// to replace the memset / memcpy is below the threshold. It also returns the 2713/// types of the sequence of memory ops to perform memset / memcpy. 2714static 2715bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 2716 SDValue Dst, SDValue Src, 2717 unsigned Limit, uint64_t Size, unsigned &Align, 2718 std::string &Str, bool &isSrcStr, 2719 SelectionDAG &DAG, 2720 const TargetLowering &TLI) { 2721 isSrcStr = isMemSrcFromString(Src, Str); 2722 bool isSrcConst = isa<ConstantSDNode>(Src); 2723 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 2724 MVT VT= TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 2725 if (VT != MVT::iAny) { 2726 unsigned NewAlign = (unsigned) 2727 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 2728 // If source is a string constant, this will require an unaligned load. 2729 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 2730 if (Dst.getOpcode() != ISD::FrameIndex) { 2731 // Can't change destination alignment. It requires a unaligned store. 2732 if (AllowUnalign) 2733 VT = MVT::iAny; 2734 } else { 2735 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 2736 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2737 if (MFI->isFixedObjectIndex(FI)) { 2738 // Can't change destination alignment. It requires a unaligned store. 2739 if (AllowUnalign) 2740 VT = MVT::iAny; 2741 } else { 2742 // Give the stack frame object a larger alignment if needed. 2743 if (MFI->getObjectAlignment(FI) < NewAlign) 2744 MFI->setObjectAlignment(FI, NewAlign); 2745 Align = NewAlign; 2746 } 2747 } 2748 } 2749 } 2750 2751 if (VT == MVT::iAny) { 2752 if (AllowUnalign) { 2753 VT = MVT::i64; 2754 } else { 2755 switch (Align & 7) { 2756 case 0: VT = MVT::i64; break; 2757 case 4: VT = MVT::i32; break; 2758 case 2: VT = MVT::i16; break; 2759 default: VT = MVT::i8; break; 2760 } 2761 } 2762 2763 MVT LVT = MVT::i64; 2764 while (!TLI.isTypeLegal(LVT)) 2765 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 2766 assert(LVT.isInteger()); 2767 2768 if (VT.bitsGT(LVT)) 2769 VT = LVT; 2770 } 2771 2772 unsigned NumMemOps = 0; 2773 while (Size != 0) { 2774 unsigned VTSize = VT.getSizeInBits() / 8; 2775 while (VTSize > Size) { 2776 // For now, only use non-vector load / store's for the left-over pieces. 2777 if (VT.isVector()) { 2778 VT = MVT::i64; 2779 while (!TLI.isTypeLegal(VT)) 2780 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2781 VTSize = VT.getSizeInBits() / 8; 2782 } else { 2783 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2784 VTSize >>= 1; 2785 } 2786 } 2787 2788 if (++NumMemOps > Limit) 2789 return false; 2790 MemOps.push_back(VT); 2791 Size -= VTSize; 2792 } 2793 2794 return true; 2795} 2796 2797static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, 2798 SDValue Chain, SDValue Dst, 2799 SDValue Src, uint64_t Size, 2800 unsigned Align, bool AlwaysInline, 2801 const Value *DstSV, uint64_t DstSVOff, 2802 const Value *SrcSV, uint64_t SrcSVOff){ 2803 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2804 2805 // Expand memcpy to a series of load and store ops if the size operand falls 2806 // below a certain threshold. 2807 std::vector<MVT> MemOps; 2808 uint64_t Limit = -1; 2809 if (!AlwaysInline) 2810 Limit = TLI.getMaxStoresPerMemcpy(); 2811 unsigned DstAlign = Align; // Destination alignment can change. 2812 std::string Str; 2813 bool CopyFromStr; 2814 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 2815 Str, CopyFromStr, DAG, TLI)) 2816 return SDValue(); 2817 2818 2819 bool isZeroStr = CopyFromStr && Str.empty(); 2820 SmallVector<SDValue, 8> OutChains; 2821 unsigned NumMemOps = MemOps.size(); 2822 uint64_t SrcOff = 0, DstOff = 0; 2823 for (unsigned i = 0; i < NumMemOps; i++) { 2824 MVT VT = MemOps[i]; 2825 unsigned VTSize = VT.getSizeInBits() / 8; 2826 SDValue Value, Store; 2827 2828 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 2829 // It's unlikely a store of a vector immediate can be done in a single 2830 // instruction. It would require a load from a constantpool first. 2831 // We also handle store a vector with all zero's. 2832 // FIXME: Handle other cases where store of vector immediate is done in 2833 // a single instruction. 2834 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 2835 Store = DAG.getStore(Chain, Value, 2836 getMemBasePlusOffset(Dst, DstOff, DAG), 2837 DstSV, DstSVOff + DstOff, false, DstAlign); 2838 } else { 2839 Value = DAG.getLoad(VT, Chain, 2840 getMemBasePlusOffset(Src, SrcOff, DAG), 2841 SrcSV, SrcSVOff + SrcOff, false, Align); 2842 Store = DAG.getStore(Chain, Value, 2843 getMemBasePlusOffset(Dst, DstOff, DAG), 2844 DstSV, DstSVOff + DstOff, false, DstAlign); 2845 } 2846 OutChains.push_back(Store); 2847 SrcOff += VTSize; 2848 DstOff += VTSize; 2849 } 2850 2851 return DAG.getNode(ISD::TokenFactor, MVT::Other, 2852 &OutChains[0], OutChains.size()); 2853} 2854 2855static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, 2856 SDValue Chain, SDValue Dst, 2857 SDValue Src, uint64_t Size, 2858 unsigned Align, bool AlwaysInline, 2859 const Value *DstSV, uint64_t DstSVOff, 2860 const Value *SrcSV, uint64_t SrcSVOff){ 2861 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2862 2863 // Expand memmove to a series of load and store ops if the size operand falls 2864 // below a certain threshold. 2865 std::vector<MVT> MemOps; 2866 uint64_t Limit = -1; 2867 if (!AlwaysInline) 2868 Limit = TLI.getMaxStoresPerMemmove(); 2869 unsigned DstAlign = Align; // Destination alignment can change. 2870 std::string Str; 2871 bool CopyFromStr; 2872 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 2873 Str, CopyFromStr, DAG, TLI)) 2874 return SDValue(); 2875 2876 uint64_t SrcOff = 0, DstOff = 0; 2877 2878 SmallVector<SDValue, 8> LoadValues; 2879 SmallVector<SDValue, 8> LoadChains; 2880 SmallVector<SDValue, 8> OutChains; 2881 unsigned NumMemOps = MemOps.size(); 2882 for (unsigned i = 0; i < NumMemOps; i++) { 2883 MVT VT = MemOps[i]; 2884 unsigned VTSize = VT.getSizeInBits() / 8; 2885 SDValue Value, Store; 2886 2887 Value = DAG.getLoad(VT, Chain, 2888 getMemBasePlusOffset(Src, SrcOff, DAG), 2889 SrcSV, SrcSVOff + SrcOff, false, Align); 2890 LoadValues.push_back(Value); 2891 LoadChains.push_back(Value.getValue(1)); 2892 SrcOff += VTSize; 2893 } 2894 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 2895 &LoadChains[0], LoadChains.size()); 2896 OutChains.clear(); 2897 for (unsigned i = 0; i < NumMemOps; i++) { 2898 MVT VT = MemOps[i]; 2899 unsigned VTSize = VT.getSizeInBits() / 8; 2900 SDValue Value, Store; 2901 2902 Store = DAG.getStore(Chain, LoadValues[i], 2903 getMemBasePlusOffset(Dst, DstOff, DAG), 2904 DstSV, DstSVOff + DstOff, false, DstAlign); 2905 OutChains.push_back(Store); 2906 DstOff += VTSize; 2907 } 2908 2909 return DAG.getNode(ISD::TokenFactor, MVT::Other, 2910 &OutChains[0], OutChains.size()); 2911} 2912 2913static SDValue getMemsetStores(SelectionDAG &DAG, 2914 SDValue Chain, SDValue Dst, 2915 SDValue Src, uint64_t Size, 2916 unsigned Align, 2917 const Value *DstSV, uint64_t DstSVOff) { 2918 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2919 2920 // Expand memset to a series of load/store ops if the size operand 2921 // falls below a certain threshold. 2922 std::vector<MVT> MemOps; 2923 std::string Str; 2924 bool CopyFromStr; 2925 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 2926 Size, Align, Str, CopyFromStr, DAG, TLI)) 2927 return SDValue(); 2928 2929 SmallVector<SDValue, 8> OutChains; 2930 uint64_t DstOff = 0; 2931 2932 unsigned NumMemOps = MemOps.size(); 2933 for (unsigned i = 0; i < NumMemOps; i++) { 2934 MVT VT = MemOps[i]; 2935 unsigned VTSize = VT.getSizeInBits() / 8; 2936 SDValue Value = getMemsetValue(Src, VT, DAG); 2937 SDValue Store = DAG.getStore(Chain, Value, 2938 getMemBasePlusOffset(Dst, DstOff, DAG), 2939 DstSV, DstSVOff + DstOff); 2940 OutChains.push_back(Store); 2941 DstOff += VTSize; 2942 } 2943 2944 return DAG.getNode(ISD::TokenFactor, MVT::Other, 2945 &OutChains[0], OutChains.size()); 2946} 2947 2948SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst, 2949 SDValue Src, SDValue Size, 2950 unsigned Align, bool AlwaysInline, 2951 const Value *DstSV, uint64_t DstSVOff, 2952 const Value *SrcSV, uint64_t SrcSVOff) { 2953 2954 // Check to see if we should lower the memcpy to loads and stores first. 2955 // For cases within the target-specified limits, this is the best choice. 2956 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 2957 if (ConstantSize) { 2958 // Memcpy with size zero? Just return the original chain. 2959 if (ConstantSize->isNullValue()) 2960 return Chain; 2961 2962 SDValue Result = 2963 getMemcpyLoadsAndStores(*this, Chain, Dst, Src, ConstantSize->getValue(), 2964 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 2965 if (Result.Val) 2966 return Result; 2967 } 2968 2969 // Then check to see if we should lower the memcpy with target-specific 2970 // code. If the target chooses to do this, this is the next best. 2971 SDValue Result = 2972 TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align, 2973 AlwaysInline, 2974 DstSV, DstSVOff, SrcSV, SrcSVOff); 2975 if (Result.Val) 2976 return Result; 2977 2978 // If we really need inline code and the target declined to provide it, 2979 // use a (potentially long) sequence of loads and stores. 2980 if (AlwaysInline) { 2981 assert(ConstantSize && "AlwaysInline requires a constant size!"); 2982 return getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 2983 ConstantSize->getValue(), Align, true, 2984 DstSV, DstSVOff, SrcSV, SrcSVOff); 2985 } 2986 2987 // Emit a library call. 2988 TargetLowering::ArgListTy Args; 2989 TargetLowering::ArgListEntry Entry; 2990 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 2991 Entry.Node = Dst; Args.push_back(Entry); 2992 Entry.Node = Src; Args.push_back(Entry); 2993 Entry.Node = Size; Args.push_back(Entry); 2994 std::pair<SDValue,SDValue> CallResult = 2995 TLI.LowerCallTo(Chain, Type::VoidTy, 2996 false, false, false, CallingConv::C, false, 2997 getExternalSymbol("memcpy", TLI.getPointerTy()), 2998 Args, *this); 2999 return CallResult.second; 3000} 3001 3002SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst, 3003 SDValue Src, SDValue Size, 3004 unsigned Align, 3005 const Value *DstSV, uint64_t DstSVOff, 3006 const Value *SrcSV, uint64_t SrcSVOff) { 3007 3008 // Check to see if we should lower the memmove to loads and stores first. 3009 // For cases within the target-specified limits, this is the best choice. 3010 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3011 if (ConstantSize) { 3012 // Memmove with size zero? Just return the original chain. 3013 if (ConstantSize->isNullValue()) 3014 return Chain; 3015 3016 SDValue Result = 3017 getMemmoveLoadsAndStores(*this, Chain, Dst, Src, ConstantSize->getValue(), 3018 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3019 if (Result.Val) 3020 return Result; 3021 } 3022 3023 // Then check to see if we should lower the memmove with target-specific 3024 // code. If the target chooses to do this, this is the next best. 3025 SDValue Result = 3026 TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align, 3027 DstSV, DstSVOff, SrcSV, SrcSVOff); 3028 if (Result.Val) 3029 return Result; 3030 3031 // Emit a library call. 3032 TargetLowering::ArgListTy Args; 3033 TargetLowering::ArgListEntry Entry; 3034 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3035 Entry.Node = Dst; Args.push_back(Entry); 3036 Entry.Node = Src; Args.push_back(Entry); 3037 Entry.Node = Size; Args.push_back(Entry); 3038 std::pair<SDValue,SDValue> CallResult = 3039 TLI.LowerCallTo(Chain, Type::VoidTy, 3040 false, false, false, CallingConv::C, false, 3041 getExternalSymbol("memmove", TLI.getPointerTy()), 3042 Args, *this); 3043 return CallResult.second; 3044} 3045 3046SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst, 3047 SDValue Src, SDValue Size, 3048 unsigned Align, 3049 const Value *DstSV, uint64_t DstSVOff) { 3050 3051 // Check to see if we should lower the memset to stores first. 3052 // For cases within the target-specified limits, this is the best choice. 3053 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3054 if (ConstantSize) { 3055 // Memset with size zero? Just return the original chain. 3056 if (ConstantSize->isNullValue()) 3057 return Chain; 3058 3059 SDValue Result = 3060 getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getValue(), Align, 3061 DstSV, DstSVOff); 3062 if (Result.Val) 3063 return Result; 3064 } 3065 3066 // Then check to see if we should lower the memset with target-specific 3067 // code. If the target chooses to do this, this is the next best. 3068 SDValue Result = 3069 TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align, 3070 DstSV, DstSVOff); 3071 if (Result.Val) 3072 return Result; 3073 3074 // Emit a library call. 3075 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3076 TargetLowering::ArgListTy Args; 3077 TargetLowering::ArgListEntry Entry; 3078 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3079 Args.push_back(Entry); 3080 // Extend or truncate the argument to be an i32 value for the call. 3081 if (Src.getValueType().bitsGT(MVT::i32)) 3082 Src = getNode(ISD::TRUNCATE, MVT::i32, Src); 3083 else 3084 Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src); 3085 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3086 Args.push_back(Entry); 3087 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3088 Args.push_back(Entry); 3089 std::pair<SDValue,SDValue> CallResult = 3090 TLI.LowerCallTo(Chain, Type::VoidTy, 3091 false, false, false, CallingConv::C, false, 3092 getExternalSymbol("memset", TLI.getPointerTy()), 3093 Args, *this); 3094 return CallResult.second; 3095} 3096 3097SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3098 SDValue Ptr, SDValue Cmp, 3099 SDValue Swp, const Value* PtrVal, 3100 unsigned Alignment) { 3101 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); 3102 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3103 3104 MVT VT = Cmp.getValueType(); 3105 3106 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3107 Alignment = getMVTAlignment(VT); 3108 3109 SDVTList VTs = getVTList(VT, MVT::Other); 3110 FoldingSetNodeID ID; 3111 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3112 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3113 void* IP = 0; 3114 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3115 return SDValue(E, 0); 3116 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3117 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3118 CSEMap.InsertNode(N, IP); 3119 AllNodes.push_back(N); 3120 return SDValue(N, 0); 3121} 3122 3123SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3124 SDValue Ptr, SDValue Val, 3125 const Value* PtrVal, 3126 unsigned Alignment) { 3127 assert(( Opcode == ISD::ATOMIC_LOAD_ADD || Opcode == ISD::ATOMIC_LOAD_SUB 3128 || Opcode == ISD::ATOMIC_SWAP || Opcode == ISD::ATOMIC_LOAD_AND 3129 || Opcode == ISD::ATOMIC_LOAD_OR || Opcode == ISD::ATOMIC_LOAD_XOR 3130 || Opcode == ISD::ATOMIC_LOAD_NAND 3131 || Opcode == ISD::ATOMIC_LOAD_MIN || Opcode == ISD::ATOMIC_LOAD_MAX 3132 || Opcode == ISD::ATOMIC_LOAD_UMIN || Opcode == ISD::ATOMIC_LOAD_UMAX) 3133 && "Invalid Atomic Op"); 3134 3135 MVT VT = Val.getValueType(); 3136 3137 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3138 Alignment = getMVTAlignment(VT); 3139 3140 SDVTList VTs = getVTList(VT, MVT::Other); 3141 FoldingSetNodeID ID; 3142 SDValue Ops[] = {Chain, Ptr, Val}; 3143 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3144 void* IP = 0; 3145 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3146 return SDValue(E, 0); 3147 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3148 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Val, PtrVal, Alignment); 3149 CSEMap.InsertNode(N, IP); 3150 AllNodes.push_back(N); 3151 return SDValue(N, 0); 3152} 3153 3154/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3155/// Allowed to return something different (and simpler) if Simplify is true. 3156SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3157 bool Simplify) { 3158 if (Simplify && NumOps == 1) 3159 return Ops[0]; 3160 3161 SmallVector<MVT, 4> VTs; 3162 VTs.reserve(NumOps); 3163 for (unsigned i = 0; i < NumOps; ++i) 3164 VTs.push_back(Ops[i].getValueType()); 3165 return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps); 3166} 3167 3168SDValue 3169SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, 3170 MVT VT, SDValue Chain, 3171 SDValue Ptr, SDValue Offset, 3172 const Value *SV, int SVOffset, MVT EVT, 3173 bool isVolatile, unsigned Alignment) { 3174 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3175 Alignment = getMVTAlignment(VT); 3176 3177 if (VT == EVT) { 3178 ExtType = ISD::NON_EXTLOAD; 3179 } else if (ExtType == ISD::NON_EXTLOAD) { 3180 assert(VT == EVT && "Non-extending load from different memory type!"); 3181 } else { 3182 // Extending load. 3183 if (VT.isVector()) 3184 assert(EVT == VT.getVectorElementType() && "Invalid vector extload!"); 3185 else 3186 assert(EVT.bitsLT(VT) && 3187 "Should only be an extending load, not truncating!"); 3188 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3189 "Cannot sign/zero extend a FP/Vector load!"); 3190 assert(VT.isInteger() == EVT.isInteger() && 3191 "Cannot convert from FP to Int or Int -> FP!"); 3192 } 3193 3194 bool Indexed = AM != ISD::UNINDEXED; 3195 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3196 "Unindexed load with an offset!"); 3197 3198 SDVTList VTs = Indexed ? 3199 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3200 SDValue Ops[] = { Chain, Ptr, Offset }; 3201 FoldingSetNodeID ID; 3202 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3203 ID.AddInteger(AM); 3204 ID.AddInteger(ExtType); 3205 ID.AddInteger(EVT.getRawBits()); 3206 ID.AddInteger(Alignment); 3207 ID.AddInteger(isVolatile); 3208 void *IP = 0; 3209 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3210 return SDValue(E, 0); 3211 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3212 new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset, 3213 Alignment, isVolatile); 3214 CSEMap.InsertNode(N, IP); 3215 AllNodes.push_back(N); 3216 return SDValue(N, 0); 3217} 3218 3219SDValue SelectionDAG::getLoad(MVT VT, 3220 SDValue Chain, SDValue Ptr, 3221 const Value *SV, int SVOffset, 3222 bool isVolatile, unsigned Alignment) { 3223 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3224 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3225 SV, SVOffset, VT, isVolatile, Alignment); 3226} 3227 3228SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT, 3229 SDValue Chain, SDValue Ptr, 3230 const Value *SV, 3231 int SVOffset, MVT EVT, 3232 bool isVolatile, unsigned Alignment) { 3233 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3234 return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef, 3235 SV, SVOffset, EVT, isVolatile, Alignment); 3236} 3237 3238SDValue 3239SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base, 3240 SDValue Offset, ISD::MemIndexedMode AM) { 3241 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3242 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3243 "Load is already a indexed load!"); 3244 return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), 3245 LD->getChain(), Base, Offset, LD->getSrcValue(), 3246 LD->getSrcValueOffset(), LD->getMemoryVT(), 3247 LD->isVolatile(), LD->getAlignment()); 3248} 3249 3250SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val, 3251 SDValue Ptr, const Value *SV, int SVOffset, 3252 bool isVolatile, unsigned Alignment) { 3253 MVT VT = Val.getValueType(); 3254 3255 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3256 Alignment = getMVTAlignment(VT); 3257 3258 SDVTList VTs = getVTList(MVT::Other); 3259 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3260 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3261 FoldingSetNodeID ID; 3262 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3263 ID.AddInteger(ISD::UNINDEXED); 3264 ID.AddInteger(false); 3265 ID.AddInteger(VT.getRawBits()); 3266 ID.AddInteger(Alignment); 3267 ID.AddInteger(isVolatile); 3268 void *IP = 0; 3269 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3270 return SDValue(E, 0); 3271 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3272 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false, 3273 VT, SV, SVOffset, Alignment, isVolatile); 3274 CSEMap.InsertNode(N, IP); 3275 AllNodes.push_back(N); 3276 return SDValue(N, 0); 3277} 3278 3279SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val, 3280 SDValue Ptr, const Value *SV, 3281 int SVOffset, MVT SVT, 3282 bool isVolatile, unsigned Alignment) { 3283 MVT VT = Val.getValueType(); 3284 3285 if (VT == SVT) 3286 return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3287 3288 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3289 assert(VT.isInteger() == SVT.isInteger() && 3290 "Can't do FP-INT conversion!"); 3291 3292 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3293 Alignment = getMVTAlignment(VT); 3294 3295 SDVTList VTs = getVTList(MVT::Other); 3296 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3297 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3298 FoldingSetNodeID ID; 3299 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3300 ID.AddInteger(ISD::UNINDEXED); 3301 ID.AddInteger(1); 3302 ID.AddInteger(SVT.getRawBits()); 3303 ID.AddInteger(Alignment); 3304 ID.AddInteger(isVolatile); 3305 void *IP = 0; 3306 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3307 return SDValue(E, 0); 3308 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3309 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true, 3310 SVT, SV, SVOffset, Alignment, isVolatile); 3311 CSEMap.InsertNode(N, IP); 3312 AllNodes.push_back(N); 3313 return SDValue(N, 0); 3314} 3315 3316SDValue 3317SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base, 3318 SDValue Offset, ISD::MemIndexedMode AM) { 3319 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3320 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3321 "Store is already a indexed store!"); 3322 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3323 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3324 FoldingSetNodeID ID; 3325 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3326 ID.AddInteger(AM); 3327 ID.AddInteger(ST->isTruncatingStore()); 3328 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3329 ID.AddInteger(ST->getAlignment()); 3330 ID.AddInteger(ST->isVolatile()); 3331 void *IP = 0; 3332 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3333 return SDValue(E, 0); 3334 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3335 new (N) StoreSDNode(Ops, VTs, AM, 3336 ST->isTruncatingStore(), ST->getMemoryVT(), 3337 ST->getSrcValue(), ST->getSrcValueOffset(), 3338 ST->getAlignment(), ST->isVolatile()); 3339 CSEMap.InsertNode(N, IP); 3340 AllNodes.push_back(N); 3341 return SDValue(N, 0); 3342} 3343 3344SDValue SelectionDAG::getVAArg(MVT VT, 3345 SDValue Chain, SDValue Ptr, 3346 SDValue SV) { 3347 SDValue Ops[] = { Chain, Ptr, SV }; 3348 return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); 3349} 3350 3351SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3352 const SDUse *Ops, unsigned NumOps) { 3353 switch (NumOps) { 3354 case 0: return getNode(Opcode, VT); 3355 case 1: return getNode(Opcode, VT, Ops[0]); 3356 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3357 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3358 default: break; 3359 } 3360 3361 // Copy from an SDUse array into an SDValue array for use with 3362 // the regular getNode logic. 3363 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3364 return getNode(Opcode, VT, &NewOps[0], NumOps); 3365} 3366 3367SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3368 const SDValue *Ops, unsigned NumOps) { 3369 switch (NumOps) { 3370 case 0: return getNode(Opcode, VT); 3371 case 1: return getNode(Opcode, VT, Ops[0]); 3372 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3373 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3374 default: break; 3375 } 3376 3377 switch (Opcode) { 3378 default: break; 3379 case ISD::SELECT_CC: { 3380 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3381 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3382 "LHS and RHS of condition must have same type!"); 3383 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3384 "True and False arms of SelectCC must have same type!"); 3385 assert(Ops[2].getValueType() == VT && 3386 "select_cc node must be of same type as true and false value!"); 3387 break; 3388 } 3389 case ISD::BR_CC: { 3390 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3391 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3392 "LHS/RHS of comparison should match types!"); 3393 break; 3394 } 3395 } 3396 3397 // Memoize nodes. 3398 SDNode *N; 3399 SDVTList VTs = getVTList(VT); 3400 if (VT != MVT::Flag) { 3401 FoldingSetNodeID ID; 3402 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3403 void *IP = 0; 3404 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3405 return SDValue(E, 0); 3406 N = NodeAllocator.Allocate<SDNode>(); 3407 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3408 CSEMap.InsertNode(N, IP); 3409 } else { 3410 N = NodeAllocator.Allocate<SDNode>(); 3411 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3412 } 3413 AllNodes.push_back(N); 3414#ifndef NDEBUG 3415 VerifyNode(N); 3416#endif 3417 return SDValue(N, 0); 3418} 3419 3420SDValue SelectionDAG::getNode(unsigned Opcode, 3421 const std::vector<MVT> &ResultTys, 3422 const SDValue *Ops, unsigned NumOps) { 3423 return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(), 3424 Ops, NumOps); 3425} 3426 3427SDValue SelectionDAG::getNode(unsigned Opcode, 3428 const MVT *VTs, unsigned NumVTs, 3429 const SDValue *Ops, unsigned NumOps) { 3430 if (NumVTs == 1) 3431 return getNode(Opcode, VTs[0], Ops, NumOps); 3432 return getNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps); 3433} 3434 3435SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3436 const SDValue *Ops, unsigned NumOps) { 3437 if (VTList.NumVTs == 1) 3438 return getNode(Opcode, VTList.VTs[0], Ops, NumOps); 3439 3440 switch (Opcode) { 3441 // FIXME: figure out how to safely handle things like 3442 // int foo(int x) { return 1 << (x & 255); } 3443 // int bar() { return foo(256); } 3444#if 0 3445 case ISD::SRA_PARTS: 3446 case ISD::SRL_PARTS: 3447 case ISD::SHL_PARTS: 3448 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3449 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3450 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3451 else if (N3.getOpcode() == ISD::AND) 3452 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3453 // If the and is only masking out bits that cannot effect the shift, 3454 // eliminate the and. 3455 unsigned NumBits = VT.getSizeInBits()*2; 3456 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3457 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3458 } 3459 break; 3460#endif 3461 } 3462 3463 // Memoize the node unless it returns a flag. 3464 SDNode *N; 3465 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3466 FoldingSetNodeID ID; 3467 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3468 void *IP = 0; 3469 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3470 return SDValue(E, 0); 3471 if (NumOps == 1) { 3472 N = NodeAllocator.Allocate<UnarySDNode>(); 3473 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3474 } else if (NumOps == 2) { 3475 N = NodeAllocator.Allocate<BinarySDNode>(); 3476 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3477 } else if (NumOps == 3) { 3478 N = NodeAllocator.Allocate<TernarySDNode>(); 3479 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3480 } else { 3481 N = NodeAllocator.Allocate<SDNode>(); 3482 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3483 } 3484 CSEMap.InsertNode(N, IP); 3485 } else { 3486 if (NumOps == 1) { 3487 N = NodeAllocator.Allocate<UnarySDNode>(); 3488 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3489 } else if (NumOps == 2) { 3490 N = NodeAllocator.Allocate<BinarySDNode>(); 3491 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3492 } else if (NumOps == 3) { 3493 N = NodeAllocator.Allocate<TernarySDNode>(); 3494 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3495 } else { 3496 N = NodeAllocator.Allocate<SDNode>(); 3497 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3498 } 3499 } 3500 AllNodes.push_back(N); 3501#ifndef NDEBUG 3502 VerifyNode(N); 3503#endif 3504 return SDValue(N, 0); 3505} 3506 3507SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) { 3508 return getNode(Opcode, VTList, 0, 0); 3509} 3510 3511SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3512 SDValue N1) { 3513 SDValue Ops[] = { N1 }; 3514 return getNode(Opcode, VTList, Ops, 1); 3515} 3516 3517SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3518 SDValue N1, SDValue N2) { 3519 SDValue Ops[] = { N1, N2 }; 3520 return getNode(Opcode, VTList, Ops, 2); 3521} 3522 3523SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3524 SDValue N1, SDValue N2, SDValue N3) { 3525 SDValue Ops[] = { N1, N2, N3 }; 3526 return getNode(Opcode, VTList, Ops, 3); 3527} 3528 3529SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3530 SDValue N1, SDValue N2, SDValue N3, 3531 SDValue N4) { 3532 SDValue Ops[] = { N1, N2, N3, N4 }; 3533 return getNode(Opcode, VTList, Ops, 4); 3534} 3535 3536SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3537 SDValue N1, SDValue N2, SDValue N3, 3538 SDValue N4, SDValue N5) { 3539 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3540 return getNode(Opcode, VTList, Ops, 5); 3541} 3542 3543SDVTList SelectionDAG::getVTList(MVT VT) { 3544 return makeVTList(SDNode::getValueTypeList(VT), 1); 3545} 3546 3547SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3548 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3549 E = VTList.rend(); I != E; ++I) 3550 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3551 return *I; 3552 3553 MVT *Array = Allocator.Allocate<MVT>(2); 3554 Array[0] = VT1; 3555 Array[1] = VT2; 3556 SDVTList Result = makeVTList(Array, 2); 3557 VTList.push_back(Result); 3558 return Result; 3559} 3560 3561SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3562 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3563 E = VTList.rend(); I != E; ++I) 3564 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3565 I->VTs[2] == VT3) 3566 return *I; 3567 3568 MVT *Array = Allocator.Allocate<MVT>(3); 3569 Array[0] = VT1; 3570 Array[1] = VT2; 3571 Array[2] = VT3; 3572 SDVTList Result = makeVTList(Array, 3); 3573 VTList.push_back(Result); 3574 return Result; 3575} 3576 3577SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3578 switch (NumVTs) { 3579 case 0: assert(0 && "Cannot have nodes without results!"); 3580 case 1: return getVTList(VTs[0]); 3581 case 2: return getVTList(VTs[0], VTs[1]); 3582 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3583 default: break; 3584 } 3585 3586 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3587 E = VTList.rend(); I != E; ++I) { 3588 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3589 continue; 3590 3591 bool NoMatch = false; 3592 for (unsigned i = 2; i != NumVTs; ++i) 3593 if (VTs[i] != I->VTs[i]) { 3594 NoMatch = true; 3595 break; 3596 } 3597 if (!NoMatch) 3598 return *I; 3599 } 3600 3601 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 3602 std::copy(VTs, VTs+NumVTs, Array); 3603 SDVTList Result = makeVTList(Array, NumVTs); 3604 VTList.push_back(Result); 3605 return Result; 3606} 3607 3608 3609/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 3610/// specified operands. If the resultant node already exists in the DAG, 3611/// this does not modify the specified node, instead it returns the node that 3612/// already exists. If the resultant node does not exist in the DAG, the 3613/// input node is returned. As a degenerate case, if you specify the same 3614/// input operands as the node already has, the input node is returned. 3615SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 3616 SDNode *N = InN.Val; 3617 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 3618 3619 // Check to see if there is no change. 3620 if (Op == N->getOperand(0)) return InN; 3621 3622 // See if the modified node already exists. 3623 void *InsertPos = 0; 3624 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 3625 return SDValue(Existing, InN.ResNo); 3626 3627 // Nope it doesn't. Remove the node from its current place in the maps. 3628 if (InsertPos) 3629 RemoveNodeFromCSEMaps(N); 3630 3631 // Now we update the operands. 3632 N->OperandList[0].getVal()->removeUser(0, N); 3633 N->OperandList[0] = Op; 3634 N->OperandList[0].setUser(N); 3635 Op.Val->addUser(0, N); 3636 3637 // If this gets put into a CSE map, add it. 3638 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3639 return InN; 3640} 3641 3642SDValue SelectionDAG:: 3643UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 3644 SDNode *N = InN.Val; 3645 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 3646 3647 // Check to see if there is no change. 3648 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 3649 return InN; // No operands changed, just return the input node. 3650 3651 // See if the modified node already exists. 3652 void *InsertPos = 0; 3653 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 3654 return SDValue(Existing, InN.ResNo); 3655 3656 // Nope it doesn't. Remove the node from its current place in the maps. 3657 if (InsertPos) 3658 RemoveNodeFromCSEMaps(N); 3659 3660 // Now we update the operands. 3661 if (N->OperandList[0] != Op1) { 3662 N->OperandList[0].getVal()->removeUser(0, N); 3663 N->OperandList[0] = Op1; 3664 N->OperandList[0].setUser(N); 3665 Op1.Val->addUser(0, N); 3666 } 3667 if (N->OperandList[1] != Op2) { 3668 N->OperandList[1].getVal()->removeUser(1, N); 3669 N->OperandList[1] = Op2; 3670 N->OperandList[1].setUser(N); 3671 Op2.Val->addUser(1, N); 3672 } 3673 3674 // If this gets put into a CSE map, add it. 3675 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3676 return InN; 3677} 3678 3679SDValue SelectionDAG:: 3680UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 3681 SDValue Ops[] = { Op1, Op2, Op3 }; 3682 return UpdateNodeOperands(N, Ops, 3); 3683} 3684 3685SDValue SelectionDAG:: 3686UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3687 SDValue Op3, SDValue Op4) { 3688 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 3689 return UpdateNodeOperands(N, Ops, 4); 3690} 3691 3692SDValue SelectionDAG:: 3693UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3694 SDValue Op3, SDValue Op4, SDValue Op5) { 3695 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 3696 return UpdateNodeOperands(N, Ops, 5); 3697} 3698 3699SDValue SelectionDAG:: 3700UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 3701 SDNode *N = InN.Val; 3702 assert(N->getNumOperands() == NumOps && 3703 "Update with wrong number of operands"); 3704 3705 // Check to see if there is no change. 3706 bool AnyChange = false; 3707 for (unsigned i = 0; i != NumOps; ++i) { 3708 if (Ops[i] != N->getOperand(i)) { 3709 AnyChange = true; 3710 break; 3711 } 3712 } 3713 3714 // No operands changed, just return the input node. 3715 if (!AnyChange) return InN; 3716 3717 // See if the modified node already exists. 3718 void *InsertPos = 0; 3719 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 3720 return SDValue(Existing, InN.ResNo); 3721 3722 // Nope it doesn't. Remove the node from its current place in the maps. 3723 if (InsertPos) 3724 RemoveNodeFromCSEMaps(N); 3725 3726 // Now we update the operands. 3727 for (unsigned i = 0; i != NumOps; ++i) { 3728 if (N->OperandList[i] != Ops[i]) { 3729 N->OperandList[i].getVal()->removeUser(i, N); 3730 N->OperandList[i] = Ops[i]; 3731 N->OperandList[i].setUser(N); 3732 Ops[i].Val->addUser(i, N); 3733 } 3734 } 3735 3736 // If this gets put into a CSE map, add it. 3737 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3738 return InN; 3739} 3740 3741/// DropOperands - Release the operands and set this node to have 3742/// zero operands. 3743void SDNode::DropOperands() { 3744 // Unlike the code in MorphNodeTo that does this, we don't need to 3745 // watch for dead nodes here. 3746 for (op_iterator I = op_begin(), E = op_end(); I != E; ++I) 3747 I->getVal()->removeUser(std::distance(op_begin(), I), this); 3748 3749 NumOperands = 0; 3750} 3751 3752/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 3753/// machine opcode. 3754/// 3755SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3756 MVT VT) { 3757 SDVTList VTs = getVTList(VT); 3758 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 3759} 3760 3761SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3762 MVT VT, SDValue Op1) { 3763 SDVTList VTs = getVTList(VT); 3764 SDValue Ops[] = { Op1 }; 3765 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 3766} 3767 3768SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3769 MVT VT, SDValue Op1, 3770 SDValue Op2) { 3771 SDVTList VTs = getVTList(VT); 3772 SDValue Ops[] = { Op1, Op2 }; 3773 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 3774} 3775 3776SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3777 MVT VT, SDValue Op1, 3778 SDValue Op2, SDValue Op3) { 3779 SDVTList VTs = getVTList(VT); 3780 SDValue Ops[] = { Op1, Op2, Op3 }; 3781 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 3782} 3783 3784SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3785 MVT VT, const SDValue *Ops, 3786 unsigned NumOps) { 3787 SDVTList VTs = getVTList(VT); 3788 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 3789} 3790 3791SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3792 MVT VT1, MVT VT2, const SDValue *Ops, 3793 unsigned NumOps) { 3794 SDVTList VTs = getVTList(VT1, VT2); 3795 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 3796} 3797 3798SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3799 MVT VT1, MVT VT2) { 3800 SDVTList VTs = getVTList(VT1, VT2); 3801 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 3802} 3803 3804SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3805 MVT VT1, MVT VT2, MVT VT3, 3806 const SDValue *Ops, unsigned NumOps) { 3807 SDVTList VTs = getVTList(VT1, VT2, VT3); 3808 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 3809} 3810 3811SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3812 MVT VT1, MVT VT2, 3813 SDValue Op1) { 3814 SDVTList VTs = getVTList(VT1, VT2); 3815 SDValue Ops[] = { Op1 }; 3816 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 3817} 3818 3819SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3820 MVT VT1, MVT VT2, 3821 SDValue Op1, SDValue Op2) { 3822 SDVTList VTs = getVTList(VT1, VT2); 3823 SDValue Ops[] = { Op1, Op2 }; 3824 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 3825} 3826 3827SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3828 MVT VT1, MVT VT2, 3829 SDValue Op1, SDValue Op2, 3830 SDValue Op3) { 3831 SDVTList VTs = getVTList(VT1, VT2); 3832 SDValue Ops[] = { Op1, Op2, Op3 }; 3833 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 3834} 3835 3836SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 3837 SDVTList VTs, const SDValue *Ops, 3838 unsigned NumOps) { 3839 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 3840} 3841 3842SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3843 MVT VT) { 3844 SDVTList VTs = getVTList(VT); 3845 return MorphNodeTo(N, Opc, VTs, 0, 0); 3846} 3847 3848SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3849 MVT VT, SDValue Op1) { 3850 SDVTList VTs = getVTList(VT); 3851 SDValue Ops[] = { Op1 }; 3852 return MorphNodeTo(N, Opc, VTs, Ops, 1); 3853} 3854 3855SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3856 MVT VT, SDValue Op1, 3857 SDValue Op2) { 3858 SDVTList VTs = getVTList(VT); 3859 SDValue Ops[] = { Op1, Op2 }; 3860 return MorphNodeTo(N, Opc, VTs, Ops, 2); 3861} 3862 3863SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3864 MVT VT, SDValue Op1, 3865 SDValue Op2, SDValue Op3) { 3866 SDVTList VTs = getVTList(VT); 3867 SDValue Ops[] = { Op1, Op2, Op3 }; 3868 return MorphNodeTo(N, Opc, VTs, Ops, 3); 3869} 3870 3871SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3872 MVT VT, const SDValue *Ops, 3873 unsigned NumOps) { 3874 SDVTList VTs = getVTList(VT); 3875 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 3876} 3877 3878SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3879 MVT VT1, MVT VT2, const SDValue *Ops, 3880 unsigned NumOps) { 3881 SDVTList VTs = getVTList(VT1, VT2); 3882 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 3883} 3884 3885SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3886 MVT VT1, MVT VT2) { 3887 SDVTList VTs = getVTList(VT1, VT2); 3888 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 3889} 3890 3891SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3892 MVT VT1, MVT VT2, MVT VT3, 3893 const SDValue *Ops, unsigned NumOps) { 3894 SDVTList VTs = getVTList(VT1, VT2, VT3); 3895 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 3896} 3897 3898SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3899 MVT VT1, MVT VT2, 3900 SDValue Op1) { 3901 SDVTList VTs = getVTList(VT1, VT2); 3902 SDValue Ops[] = { Op1 }; 3903 return MorphNodeTo(N, Opc, VTs, Ops, 1); 3904} 3905 3906SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3907 MVT VT1, MVT VT2, 3908 SDValue Op1, SDValue Op2) { 3909 SDVTList VTs = getVTList(VT1, VT2); 3910 SDValue Ops[] = { Op1, Op2 }; 3911 return MorphNodeTo(N, Opc, VTs, Ops, 2); 3912} 3913 3914SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3915 MVT VT1, MVT VT2, 3916 SDValue Op1, SDValue Op2, 3917 SDValue Op3) { 3918 SDVTList VTs = getVTList(VT1, VT2); 3919 SDValue Ops[] = { Op1, Op2, Op3 }; 3920 return MorphNodeTo(N, Opc, VTs, Ops, 3); 3921} 3922 3923/// MorphNodeTo - These *mutate* the specified node to have the specified 3924/// return type, opcode, and operands. 3925/// 3926/// Note that MorphNodeTo returns the resultant node. If there is already a 3927/// node of the specified opcode and operands, it returns that node instead of 3928/// the current one. 3929/// 3930/// Using MorphNodeTo is faster than creating a new node and swapping it in 3931/// with ReplaceAllUsesWith both because it often avoids allocating a new 3932/// node, and because it doesn't require CSE recalulation for any of 3933/// the node's users. 3934/// 3935SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 3936 SDVTList VTs, const SDValue *Ops, 3937 unsigned NumOps) { 3938 // If an identical node already exists, use it. 3939 void *IP = 0; 3940 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 3941 FoldingSetNodeID ID; 3942 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 3943 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 3944 return ON; 3945 } 3946 3947 RemoveNodeFromCSEMaps(N); 3948 3949 // Start the morphing. 3950 N->NodeType = Opc; 3951 N->ValueList = VTs.VTs; 3952 N->NumValues = VTs.NumVTs; 3953 3954 // Clear the operands list, updating used nodes to remove this from their 3955 // use list. Keep track of any operands that become dead as a result. 3956 SmallPtrSet<SDNode*, 16> DeadNodeSet; 3957 for (SDNode::op_iterator B = N->op_begin(), I = B, E = N->op_end(); 3958 I != E; ++I) { 3959 SDNode *Used = I->getVal(); 3960 Used->removeUser(std::distance(B, I), N); 3961 if (Used->use_empty()) 3962 DeadNodeSet.insert(Used); 3963 } 3964 3965 // If NumOps is larger than the # of operands we currently have, reallocate 3966 // the operand list. 3967 if (NumOps > N->NumOperands) { 3968 if (N->OperandsNeedDelete) 3969 delete[] N->OperandList; 3970 if (N->isMachineOpcode()) { 3971 // We're creating a final node that will live unmorphed for the 3972 // remainder of this SelectionDAG's duration, so we can allocate the 3973 // operands directly out of the pool with no recycling metadata. 3974 N->OperandList = Allocator.Allocate<SDUse>(NumOps); 3975 N->OperandsNeedDelete = false; 3976 } else { 3977 N->OperandList = new SDUse[NumOps]; 3978 N->OperandsNeedDelete = true; 3979 } 3980 } 3981 3982 // Assign the new operands. 3983 N->NumOperands = NumOps; 3984 for (unsigned i = 0, e = NumOps; i != e; ++i) { 3985 N->OperandList[i] = Ops[i]; 3986 N->OperandList[i].setUser(N); 3987 SDNode *ToUse = N->OperandList[i].getVal(); 3988 ToUse->addUser(i, N); 3989 DeadNodeSet.erase(ToUse); 3990 } 3991 3992 // Delete any nodes that are still dead after adding the uses for the 3993 // new operands. 3994 SmallVector<SDNode *, 16> DeadNodes; 3995 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 3996 E = DeadNodeSet.end(); I != E; ++I) 3997 if ((*I)->use_empty()) 3998 DeadNodes.push_back(*I); 3999 RemoveDeadNodes(DeadNodes); 4000 4001 if (IP) 4002 CSEMap.InsertNode(N, IP); // Memoize the new node. 4003 return N; 4004} 4005 4006 4007/// getTargetNode - These are used for target selectors to create a new node 4008/// with specified return type(s), target opcode, and operands. 4009/// 4010/// Note that getTargetNode returns the resultant node. If there is already a 4011/// node of the specified opcode and operands, it returns that node instead of 4012/// the current one. 4013SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { 4014 return getNode(~Opcode, VT).Val; 4015} 4016SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) { 4017 return getNode(~Opcode, VT, Op1).Val; 4018} 4019SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4020 SDValue Op1, SDValue Op2) { 4021 return getNode(~Opcode, VT, Op1, Op2).Val; 4022} 4023SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4024 SDValue Op1, SDValue Op2, 4025 SDValue Op3) { 4026 return getNode(~Opcode, VT, Op1, Op2, Op3).Val; 4027} 4028SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4029 const SDValue *Ops, unsigned NumOps) { 4030 return getNode(~Opcode, VT, Ops, NumOps).Val; 4031} 4032SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { 4033 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4034 SDValue Op; 4035 return getNode(~Opcode, VTs, 2, &Op, 0).Val; 4036} 4037SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4038 MVT VT2, SDValue Op1) { 4039 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4040 return getNode(~Opcode, VTs, 2, &Op1, 1).Val; 4041} 4042SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4043 MVT VT2, SDValue Op1, 4044 SDValue Op2) { 4045 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4046 SDValue Ops[] = { Op1, Op2 }; 4047 return getNode(~Opcode, VTs, 2, Ops, 2).Val; 4048} 4049SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4050 MVT VT2, SDValue Op1, 4051 SDValue Op2, SDValue Op3) { 4052 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4053 SDValue Ops[] = { Op1, Op2, Op3 }; 4054 return getNode(~Opcode, VTs, 2, Ops, 3).Val; 4055} 4056SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, 4057 const SDValue *Ops, unsigned NumOps) { 4058 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4059 return getNode(~Opcode, VTs, 2, Ops, NumOps).Val; 4060} 4061SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4062 SDValue Op1, SDValue Op2) { 4063 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4064 SDValue Ops[] = { Op1, Op2 }; 4065 return getNode(~Opcode, VTs, 3, Ops, 2).Val; 4066} 4067SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4068 SDValue Op1, SDValue Op2, 4069 SDValue Op3) { 4070 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4071 SDValue Ops[] = { Op1, Op2, Op3 }; 4072 return getNode(~Opcode, VTs, 3, Ops, 3).Val; 4073} 4074SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4075 const SDValue *Ops, unsigned NumOps) { 4076 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4077 return getNode(~Opcode, VTs, 3, Ops, NumOps).Val; 4078} 4079SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4080 MVT VT2, MVT VT3, MVT VT4, 4081 const SDValue *Ops, unsigned NumOps) { 4082 std::vector<MVT> VTList; 4083 VTList.push_back(VT1); 4084 VTList.push_back(VT2); 4085 VTList.push_back(VT3); 4086 VTList.push_back(VT4); 4087 const MVT *VTs = getNodeValueTypes(VTList); 4088 return getNode(~Opcode, VTs, 4, Ops, NumOps).Val; 4089} 4090SDNode *SelectionDAG::getTargetNode(unsigned Opcode, 4091 const std::vector<MVT> &ResultTys, 4092 const SDValue *Ops, unsigned NumOps) { 4093 const MVT *VTs = getNodeValueTypes(ResultTys); 4094 return getNode(~Opcode, VTs, ResultTys.size(), 4095 Ops, NumOps).Val; 4096} 4097 4098/// getNodeIfExists - Get the specified node if it's already available, or 4099/// else return NULL. 4100SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4101 const SDValue *Ops, unsigned NumOps) { 4102 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4103 FoldingSetNodeID ID; 4104 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4105 void *IP = 0; 4106 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4107 return E; 4108 } 4109 return NULL; 4110} 4111 4112 4113/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4114/// This can cause recursive merging of nodes in the DAG. 4115/// 4116/// This version assumes From has a single result value. 4117/// 4118void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4119 DAGUpdateListener *UpdateListener) { 4120 SDNode *From = FromN.Val; 4121 assert(From->getNumValues() == 1 && FromN.ResNo == 0 && 4122 "Cannot replace with this method!"); 4123 assert(From != To.Val && "Cannot replace uses of with self"); 4124 4125 while (!From->use_empty()) { 4126 SDNode::use_iterator UI = From->use_begin(); 4127 SDNode *U = *UI; 4128 4129 // This node is about to morph, remove its old self from the CSE maps. 4130 RemoveNodeFromCSEMaps(U); 4131 int operandNum = 0; 4132 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4133 I != E; ++I, ++operandNum) 4134 if (I->getVal() == From) { 4135 From->removeUser(operandNum, U); 4136 *I = To; 4137 I->setUser(U); 4138 To.Val->addUser(operandNum, U); 4139 } 4140 4141 // Now that we have modified U, add it back to the CSE maps. If it already 4142 // exists there, recursively merge the results together. 4143 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4144 ReplaceAllUsesWith(U, Existing, UpdateListener); 4145 // U is now dead. Inform the listener if it exists and delete it. 4146 if (UpdateListener) 4147 UpdateListener->NodeDeleted(U, Existing); 4148 DeleteNodeNotInCSEMaps(U); 4149 } else { 4150 // If the node doesn't already exist, we updated it. Inform a listener if 4151 // it exists. 4152 if (UpdateListener) 4153 UpdateListener->NodeUpdated(U); 4154 } 4155 } 4156} 4157 4158/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4159/// This can cause recursive merging of nodes in the DAG. 4160/// 4161/// This version assumes From/To have matching types and numbers of result 4162/// values. 4163/// 4164void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4165 DAGUpdateListener *UpdateListener) { 4166 assert(From->getVTList().VTs == To->getVTList().VTs && 4167 From->getNumValues() == To->getNumValues() && 4168 "Cannot use this version of ReplaceAllUsesWith!"); 4169 4170 // Handle the trivial case. 4171 if (From == To) 4172 return; 4173 4174 while (!From->use_empty()) { 4175 SDNode::use_iterator UI = From->use_begin(); 4176 SDNode *U = *UI; 4177 4178 // This node is about to morph, remove its old self from the CSE maps. 4179 RemoveNodeFromCSEMaps(U); 4180 int operandNum = 0; 4181 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4182 I != E; ++I, ++operandNum) 4183 if (I->getVal() == From) { 4184 From->removeUser(operandNum, U); 4185 I->getVal() = To; 4186 To->addUser(operandNum, U); 4187 } 4188 4189 // Now that we have modified U, add it back to the CSE maps. If it already 4190 // exists there, recursively merge the results together. 4191 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4192 ReplaceAllUsesWith(U, Existing, UpdateListener); 4193 // U is now dead. Inform the listener if it exists and delete it. 4194 if (UpdateListener) 4195 UpdateListener->NodeDeleted(U, Existing); 4196 DeleteNodeNotInCSEMaps(U); 4197 } else { 4198 // If the node doesn't already exist, we updated it. Inform a listener if 4199 // it exists. 4200 if (UpdateListener) 4201 UpdateListener->NodeUpdated(U); 4202 } 4203 } 4204} 4205 4206/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4207/// This can cause recursive merging of nodes in the DAG. 4208/// 4209/// This version can replace From with any result values. To must match the 4210/// number and types of values returned by From. 4211void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4212 const SDValue *To, 4213 DAGUpdateListener *UpdateListener) { 4214 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4215 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4216 4217 while (!From->use_empty()) { 4218 SDNode::use_iterator UI = From->use_begin(); 4219 SDNode *U = *UI; 4220 4221 // This node is about to morph, remove its old self from the CSE maps. 4222 RemoveNodeFromCSEMaps(U); 4223 int operandNum = 0; 4224 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4225 I != E; ++I, ++operandNum) 4226 if (I->getVal() == From) { 4227 const SDValue &ToOp = To[I->getSDValue().ResNo]; 4228 From->removeUser(operandNum, U); 4229 *I = ToOp; 4230 I->setUser(U); 4231 ToOp.Val->addUser(operandNum, U); 4232 } 4233 4234 // Now that we have modified U, add it back to the CSE maps. If it already 4235 // exists there, recursively merge the results together. 4236 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4237 ReplaceAllUsesWith(U, Existing, UpdateListener); 4238 // U is now dead. Inform the listener if it exists and delete it. 4239 if (UpdateListener) 4240 UpdateListener->NodeDeleted(U, Existing); 4241 DeleteNodeNotInCSEMaps(U); 4242 } else { 4243 // If the node doesn't already exist, we updated it. Inform a listener if 4244 // it exists. 4245 if (UpdateListener) 4246 UpdateListener->NodeUpdated(U); 4247 } 4248 } 4249} 4250 4251/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4252/// uses of other values produced by From.Val alone. The Deleted vector is 4253/// handled the same way as for ReplaceAllUsesWith. 4254void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4255 DAGUpdateListener *UpdateListener){ 4256 // Handle the really simple, really trivial case efficiently. 4257 if (From == To) return; 4258 4259 // Handle the simple, trivial, case efficiently. 4260 if (From.Val->getNumValues() == 1) { 4261 ReplaceAllUsesWith(From, To, UpdateListener); 4262 return; 4263 } 4264 4265 // Get all of the users of From.Val. We want these in a nice, 4266 // deterministically ordered and uniqued set, so we use a SmallSetVector. 4267 SmallSetVector<SDNode*, 16> Users(From.Val->use_begin(), From.Val->use_end()); 4268 4269 while (!Users.empty()) { 4270 // We know that this user uses some value of From. If it is the right 4271 // value, update it. 4272 SDNode *User = Users.back(); 4273 Users.pop_back(); 4274 4275 // Scan for an operand that matches From. 4276 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4277 for (; Op != E; ++Op) 4278 if (*Op == From) break; 4279 4280 // If there are no matches, the user must use some other result of From. 4281 if (Op == E) continue; 4282 4283 // Okay, we know this user needs to be updated. Remove its old self 4284 // from the CSE maps. 4285 RemoveNodeFromCSEMaps(User); 4286 4287 // Update all operands that match "From" in case there are multiple uses. 4288 for (; Op != E; ++Op) { 4289 if (*Op == From) { 4290 From.Val->removeUser(Op-User->op_begin(), User); 4291 *Op = To; 4292 Op->setUser(User); 4293 To.Val->addUser(Op-User->op_begin(), User); 4294 } 4295 } 4296 4297 // Now that we have modified User, add it back to the CSE maps. If it 4298 // already exists there, recursively merge the results together. 4299 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4300 if (!Existing) { 4301 if (UpdateListener) UpdateListener->NodeUpdated(User); 4302 continue; // Continue on to next user. 4303 } 4304 4305 // If there was already an existing matching node, use ReplaceAllUsesWith 4306 // to replace the dead one with the existing one. This can cause 4307 // recursive merging of other unrelated nodes down the line. 4308 ReplaceAllUsesWith(User, Existing, UpdateListener); 4309 4310 // User is now dead. Notify a listener if present. 4311 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4312 DeleteNodeNotInCSEMaps(User); 4313 } 4314} 4315 4316/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4317/// uses of other values produced by From.Val alone. The same value may 4318/// appear in both the From and To list. The Deleted vector is 4319/// handled the same way as for ReplaceAllUsesWith. 4320void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4321 const SDValue *To, 4322 unsigned Num, 4323 DAGUpdateListener *UpdateListener){ 4324 // Handle the simple, trivial case efficiently. 4325 if (Num == 1) 4326 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4327 4328 SmallVector<std::pair<SDNode *, unsigned>, 16> Users; 4329 for (unsigned i = 0; i != Num; ++i) 4330 for (SDNode::use_iterator UI = From[i].Val->use_begin(), 4331 E = From[i].Val->use_end(); UI != E; ++UI) 4332 Users.push_back(std::make_pair(*UI, i)); 4333 4334 while (!Users.empty()) { 4335 // We know that this user uses some value of From. If it is the right 4336 // value, update it. 4337 SDNode *User = Users.back().first; 4338 unsigned i = Users.back().second; 4339 Users.pop_back(); 4340 4341 // Scan for an operand that matches From. 4342 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4343 for (; Op != E; ++Op) 4344 if (*Op == From[i]) break; 4345 4346 // If there are no matches, the user must use some other result of From. 4347 if (Op == E) continue; 4348 4349 // Okay, we know this user needs to be updated. Remove its old self 4350 // from the CSE maps. 4351 RemoveNodeFromCSEMaps(User); 4352 4353 // Update all operands that match "From" in case there are multiple uses. 4354 for (; Op != E; ++Op) { 4355 if (*Op == From[i]) { 4356 From[i].Val->removeUser(Op-User->op_begin(), User); 4357 *Op = To[i]; 4358 Op->setUser(User); 4359 To[i].Val->addUser(Op-User->op_begin(), User); 4360 } 4361 } 4362 4363 // Now that we have modified User, add it back to the CSE maps. If it 4364 // already exists there, recursively merge the results together. 4365 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4366 if (!Existing) { 4367 if (UpdateListener) UpdateListener->NodeUpdated(User); 4368 continue; // Continue on to next user. 4369 } 4370 4371 // If there was already an existing matching node, use ReplaceAllUsesWith 4372 // to replace the dead one with the existing one. This can cause 4373 // recursive merging of other unrelated nodes down the line. 4374 ReplaceAllUsesWith(User, Existing, UpdateListener); 4375 4376 // User is now dead. Notify a listener if present. 4377 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4378 DeleteNodeNotInCSEMaps(User); 4379 } 4380} 4381 4382/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4383/// based on their topological order. It returns the maximum id and a vector 4384/// of the SDNodes* in assigned order by reference. 4385unsigned SelectionDAG::AssignTopologicalOrder(std::vector<SDNode*> &TopOrder) { 4386 unsigned DAGSize = AllNodes.size(); 4387 std::vector<unsigned> InDegree(DAGSize); 4388 std::vector<SDNode*> Sources; 4389 4390 // Use a two pass approach to avoid using a std::map which is slow. 4391 unsigned Id = 0; 4392 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I){ 4393 SDNode *N = I; 4394 N->setNodeId(Id++); 4395 unsigned Degree = N->use_size(); 4396 InDegree[N->getNodeId()] = Degree; 4397 if (Degree == 0) 4398 Sources.push_back(N); 4399 } 4400 4401 TopOrder.clear(); 4402 TopOrder.reserve(DAGSize); 4403 while (!Sources.empty()) { 4404 SDNode *N = Sources.back(); 4405 Sources.pop_back(); 4406 TopOrder.push_back(N); 4407 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) { 4408 SDNode *P = I->getVal(); 4409 unsigned Degree = --InDegree[P->getNodeId()]; 4410 if (Degree == 0) 4411 Sources.push_back(P); 4412 } 4413 } 4414 4415 // Second pass, assign the actual topological order as node ids. 4416 Id = 0; 4417 for (std::vector<SDNode*>::iterator TI = TopOrder.begin(),TE = TopOrder.end(); 4418 TI != TE; ++TI) 4419 (*TI)->setNodeId(Id++); 4420 4421 return Id; 4422} 4423 4424 4425 4426//===----------------------------------------------------------------------===// 4427// SDNode Class 4428//===----------------------------------------------------------------------===// 4429 4430// Out-of-line virtual method to give class a home. 4431void SDNode::ANCHOR() {} 4432void UnarySDNode::ANCHOR() {} 4433void BinarySDNode::ANCHOR() {} 4434void TernarySDNode::ANCHOR() {} 4435void HandleSDNode::ANCHOR() {} 4436void ConstantSDNode::ANCHOR() {} 4437void ConstantFPSDNode::ANCHOR() {} 4438void GlobalAddressSDNode::ANCHOR() {} 4439void FrameIndexSDNode::ANCHOR() {} 4440void JumpTableSDNode::ANCHOR() {} 4441void ConstantPoolSDNode::ANCHOR() {} 4442void BasicBlockSDNode::ANCHOR() {} 4443void SrcValueSDNode::ANCHOR() {} 4444void MemOperandSDNode::ANCHOR() {} 4445void RegisterSDNode::ANCHOR() {} 4446void DbgStopPointSDNode::ANCHOR() {} 4447void LabelSDNode::ANCHOR() {} 4448void ExternalSymbolSDNode::ANCHOR() {} 4449void CondCodeSDNode::ANCHOR() {} 4450void ARG_FLAGSSDNode::ANCHOR() {} 4451void VTSDNode::ANCHOR() {} 4452void MemSDNode::ANCHOR() {} 4453void LoadSDNode::ANCHOR() {} 4454void StoreSDNode::ANCHOR() {} 4455void AtomicSDNode::ANCHOR() {} 4456 4457HandleSDNode::~HandleSDNode() { 4458 DropOperands(); 4459} 4460 4461GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4462 MVT VT, int o) 4463 : SDNode(isa<GlobalVariable>(GA) && 4464 cast<GlobalVariable>(GA)->isThreadLocal() ? 4465 // Thread Local 4466 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4467 // Non Thread Local 4468 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4469 getSDVTList(VT)), Offset(o) { 4470 TheGlobal = const_cast<GlobalValue*>(GA); 4471} 4472 4473MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt, 4474 const Value *srcValue, int SVO, 4475 unsigned alignment, bool vol) 4476 : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4477 Flags(vol | ((Log2_32(alignment) + 1) << 1)) { 4478 4479 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4480 assert(getAlignment() == alignment && "Alignment representation error!"); 4481 assert(isVolatile() == vol && "Volatile representation error!"); 4482} 4483 4484/// getMemOperand - Return a MachineMemOperand object describing the memory 4485/// reference performed by this memory reference. 4486MachineMemOperand MemSDNode::getMemOperand() const { 4487 int Flags; 4488 if (isa<LoadSDNode>(this)) 4489 Flags = MachineMemOperand::MOLoad; 4490 else if (isa<StoreSDNode>(this)) 4491 Flags = MachineMemOperand::MOStore; 4492 else { 4493 assert(isa<AtomicSDNode>(this) && "Unknown MemSDNode opcode!"); 4494 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4495 } 4496 4497 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4498 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4499 4500 // Check if the memory reference references a frame index 4501 const FrameIndexSDNode *FI = 4502 dyn_cast<const FrameIndexSDNode>(getBasePtr().Val); 4503 if (!getSrcValue() && FI) 4504 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4505 Flags, 0, Size, getAlignment()); 4506 else 4507 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4508 Size, getAlignment()); 4509} 4510 4511/// Profile - Gather unique data for the node. 4512/// 4513void SDNode::Profile(FoldingSetNodeID &ID) { 4514 AddNodeIDNode(ID, this); 4515} 4516 4517/// getValueTypeList - Return a pointer to the specified value type. 4518/// 4519const MVT *SDNode::getValueTypeList(MVT VT) { 4520 if (VT.isExtended()) { 4521 static std::set<MVT, MVT::compareRawBits> EVTs; 4522 return &(*EVTs.insert(VT).first); 4523 } else { 4524 static MVT VTs[MVT::LAST_VALUETYPE]; 4525 VTs[VT.getSimpleVT()] = VT; 4526 return &VTs[VT.getSimpleVT()]; 4527 } 4528} 4529 4530/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4531/// indicated value. This method ignores uses of other values defined by this 4532/// operation. 4533bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4534 assert(Value < getNumValues() && "Bad value!"); 4535 4536 // TODO: Only iterate over uses of a given value of the node 4537 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4538 if (UI.getUse().getSDValue().ResNo == Value) { 4539 if (NUses == 0) 4540 return false; 4541 --NUses; 4542 } 4543 } 4544 4545 // Found exactly the right number of uses? 4546 return NUses == 0; 4547} 4548 4549 4550/// hasAnyUseOfValue - Return true if there are any use of the indicated 4551/// value. This method ignores uses of other values defined by this operation. 4552bool SDNode::hasAnyUseOfValue(unsigned Value) const { 4553 assert(Value < getNumValues() && "Bad value!"); 4554 4555 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 4556 if (UI.getUse().getSDValue().ResNo == Value) 4557 return true; 4558 4559 return false; 4560} 4561 4562 4563/// isOnlyUserOf - Return true if this node is the only use of N. 4564/// 4565bool SDNode::isOnlyUserOf(SDNode *N) const { 4566 bool Seen = false; 4567 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 4568 SDNode *User = *I; 4569 if (User == this) 4570 Seen = true; 4571 else 4572 return false; 4573 } 4574 4575 return Seen; 4576} 4577 4578/// isOperand - Return true if this node is an operand of N. 4579/// 4580bool SDValue::isOperandOf(SDNode *N) const { 4581 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4582 if (*this == N->getOperand(i)) 4583 return true; 4584 return false; 4585} 4586 4587bool SDNode::isOperandOf(SDNode *N) const { 4588 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 4589 if (this == N->OperandList[i].getVal()) 4590 return true; 4591 return false; 4592} 4593 4594/// reachesChainWithoutSideEffects - Return true if this operand (which must 4595/// be a chain) reaches the specified operand without crossing any 4596/// side-effecting instructions. In practice, this looks through token 4597/// factors and non-volatile loads. In order to remain efficient, this only 4598/// looks a couple of nodes in, it does not do an exhaustive search. 4599bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 4600 unsigned Depth) const { 4601 if (*this == Dest) return true; 4602 4603 // Don't search too deeply, we just want to be able to see through 4604 // TokenFactor's etc. 4605 if (Depth == 0) return false; 4606 4607 // If this is a token factor, all inputs to the TF happen in parallel. If any 4608 // of the operands of the TF reach dest, then we can do the xform. 4609 if (getOpcode() == ISD::TokenFactor) { 4610 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 4611 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 4612 return true; 4613 return false; 4614 } 4615 4616 // Loads don't have side effects, look through them. 4617 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 4618 if (!Ld->isVolatile()) 4619 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 4620 } 4621 return false; 4622} 4623 4624 4625static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 4626 SmallPtrSet<SDNode *, 32> &Visited) { 4627 if (found || !Visited.insert(N)) 4628 return; 4629 4630 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 4631 SDNode *Op = N->getOperand(i).Val; 4632 if (Op == P) { 4633 found = true; 4634 return; 4635 } 4636 findPredecessor(Op, P, found, Visited); 4637 } 4638} 4639 4640/// isPredecessorOf - Return true if this node is a predecessor of N. This node 4641/// is either an operand of N or it can be reached by recursively traversing 4642/// up the operands. 4643/// NOTE: this is an expensive method. Use it carefully. 4644bool SDNode::isPredecessorOf(SDNode *N) const { 4645 SmallPtrSet<SDNode *, 32> Visited; 4646 bool found = false; 4647 findPredecessor(N, this, found, Visited); 4648 return found; 4649} 4650 4651uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 4652 assert(Num < NumOperands && "Invalid child # of SDNode!"); 4653 return cast<ConstantSDNode>(OperandList[Num])->getValue(); 4654} 4655 4656std::string SDNode::getOperationName(const SelectionDAG *G) const { 4657 switch (getOpcode()) { 4658 default: 4659 if (getOpcode() < ISD::BUILTIN_OP_END) 4660 return "<<Unknown DAG Node>>"; 4661 if (isMachineOpcode()) { 4662 if (G) 4663 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 4664 if (getMachineOpcode() < TII->getNumOpcodes()) 4665 return TII->get(getMachineOpcode()).getName(); 4666 return "<<Unknown Machine Node>>"; 4667 } 4668 if (G) { 4669 TargetLowering &TLI = G->getTargetLoweringInfo(); 4670 const char *Name = TLI.getTargetNodeName(getOpcode()); 4671 if (Name) return Name; 4672 return "<<Unknown Target Node>>"; 4673 } 4674 return "<<Unknown Node>>"; 4675 4676#ifndef NDEBUG 4677 case ISD::DELETED_NODE: 4678 return "<<Deleted Node!>>"; 4679#endif 4680 case ISD::PREFETCH: return "Prefetch"; 4681 case ISD::MEMBARRIER: return "MemBarrier"; 4682 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 4683 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 4684 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 4685 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; 4686 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; 4687 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor"; 4688 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand"; 4689 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin"; 4690 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; 4691 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; 4692 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; 4693 case ISD::ATOMIC_SWAP: return "AtomicSWAP"; 4694 case ISD::PCMARKER: return "PCMarker"; 4695 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 4696 case ISD::SRCVALUE: return "SrcValue"; 4697 case ISD::MEMOPERAND: return "MemOperand"; 4698 case ISD::EntryToken: return "EntryToken"; 4699 case ISD::TokenFactor: return "TokenFactor"; 4700 case ISD::AssertSext: return "AssertSext"; 4701 case ISD::AssertZext: return "AssertZext"; 4702 4703 case ISD::BasicBlock: return "BasicBlock"; 4704 case ISD::ARG_FLAGS: return "ArgFlags"; 4705 case ISD::VALUETYPE: return "ValueType"; 4706 case ISD::Register: return "Register"; 4707 4708 case ISD::Constant: return "Constant"; 4709 case ISD::ConstantFP: return "ConstantFP"; 4710 case ISD::GlobalAddress: return "GlobalAddress"; 4711 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 4712 case ISD::FrameIndex: return "FrameIndex"; 4713 case ISD::JumpTable: return "JumpTable"; 4714 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 4715 case ISD::RETURNADDR: return "RETURNADDR"; 4716 case ISD::FRAMEADDR: return "FRAMEADDR"; 4717 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 4718 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 4719 case ISD::EHSELECTION: return "EHSELECTION"; 4720 case ISD::EH_RETURN: return "EH_RETURN"; 4721 case ISD::ConstantPool: return "ConstantPool"; 4722 case ISD::ExternalSymbol: return "ExternalSymbol"; 4723 case ISD::INTRINSIC_WO_CHAIN: { 4724 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getValue(); 4725 return Intrinsic::getName((Intrinsic::ID)IID); 4726 } 4727 case ISD::INTRINSIC_VOID: 4728 case ISD::INTRINSIC_W_CHAIN: { 4729 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getValue(); 4730 return Intrinsic::getName((Intrinsic::ID)IID); 4731 } 4732 4733 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 4734 case ISD::TargetConstant: return "TargetConstant"; 4735 case ISD::TargetConstantFP:return "TargetConstantFP"; 4736 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 4737 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 4738 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 4739 case ISD::TargetJumpTable: return "TargetJumpTable"; 4740 case ISD::TargetConstantPool: return "TargetConstantPool"; 4741 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 4742 4743 case ISD::CopyToReg: return "CopyToReg"; 4744 case ISD::CopyFromReg: return "CopyFromReg"; 4745 case ISD::UNDEF: return "undef"; 4746 case ISD::MERGE_VALUES: return "merge_values"; 4747 case ISD::INLINEASM: return "inlineasm"; 4748 case ISD::DBG_LABEL: return "dbg_label"; 4749 case ISD::EH_LABEL: return "eh_label"; 4750 case ISD::DECLARE: return "declare"; 4751 case ISD::HANDLENODE: return "handlenode"; 4752 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 4753 case ISD::CALL: return "call"; 4754 4755 // Unary operators 4756 case ISD::FABS: return "fabs"; 4757 case ISD::FNEG: return "fneg"; 4758 case ISD::FSQRT: return "fsqrt"; 4759 case ISD::FSIN: return "fsin"; 4760 case ISD::FCOS: return "fcos"; 4761 case ISD::FPOWI: return "fpowi"; 4762 case ISD::FPOW: return "fpow"; 4763 4764 // Binary operators 4765 case ISD::ADD: return "add"; 4766 case ISD::SUB: return "sub"; 4767 case ISD::MUL: return "mul"; 4768 case ISD::MULHU: return "mulhu"; 4769 case ISD::MULHS: return "mulhs"; 4770 case ISD::SDIV: return "sdiv"; 4771 case ISD::UDIV: return "udiv"; 4772 case ISD::SREM: return "srem"; 4773 case ISD::UREM: return "urem"; 4774 case ISD::SMUL_LOHI: return "smul_lohi"; 4775 case ISD::UMUL_LOHI: return "umul_lohi"; 4776 case ISD::SDIVREM: return "sdivrem"; 4777 case ISD::UDIVREM: return "divrem"; 4778 case ISD::AND: return "and"; 4779 case ISD::OR: return "or"; 4780 case ISD::XOR: return "xor"; 4781 case ISD::SHL: return "shl"; 4782 case ISD::SRA: return "sra"; 4783 case ISD::SRL: return "srl"; 4784 case ISD::ROTL: return "rotl"; 4785 case ISD::ROTR: return "rotr"; 4786 case ISD::FADD: return "fadd"; 4787 case ISD::FSUB: return "fsub"; 4788 case ISD::FMUL: return "fmul"; 4789 case ISD::FDIV: return "fdiv"; 4790 case ISD::FREM: return "frem"; 4791 case ISD::FCOPYSIGN: return "fcopysign"; 4792 case ISD::FGETSIGN: return "fgetsign"; 4793 4794 case ISD::SETCC: return "setcc"; 4795 case ISD::VSETCC: return "vsetcc"; 4796 case ISD::SELECT: return "select"; 4797 case ISD::SELECT_CC: return "select_cc"; 4798 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 4799 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 4800 case ISD::CONCAT_VECTORS: return "concat_vectors"; 4801 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 4802 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 4803 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 4804 case ISD::CARRY_FALSE: return "carry_false"; 4805 case ISD::ADDC: return "addc"; 4806 case ISD::ADDE: return "adde"; 4807 case ISD::SUBC: return "subc"; 4808 case ISD::SUBE: return "sube"; 4809 case ISD::SHL_PARTS: return "shl_parts"; 4810 case ISD::SRA_PARTS: return "sra_parts"; 4811 case ISD::SRL_PARTS: return "srl_parts"; 4812 4813 case ISD::EXTRACT_SUBREG: return "extract_subreg"; 4814 case ISD::INSERT_SUBREG: return "insert_subreg"; 4815 4816 // Conversion operators. 4817 case ISD::SIGN_EXTEND: return "sign_extend"; 4818 case ISD::ZERO_EXTEND: return "zero_extend"; 4819 case ISD::ANY_EXTEND: return "any_extend"; 4820 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 4821 case ISD::TRUNCATE: return "truncate"; 4822 case ISD::FP_ROUND: return "fp_round"; 4823 case ISD::FLT_ROUNDS_: return "flt_rounds"; 4824 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 4825 case ISD::FP_EXTEND: return "fp_extend"; 4826 4827 case ISD::SINT_TO_FP: return "sint_to_fp"; 4828 case ISD::UINT_TO_FP: return "uint_to_fp"; 4829 case ISD::FP_TO_SINT: return "fp_to_sint"; 4830 case ISD::FP_TO_UINT: return "fp_to_uint"; 4831 case ISD::BIT_CONVERT: return "bit_convert"; 4832 4833 // Control flow instructions 4834 case ISD::BR: return "br"; 4835 case ISD::BRIND: return "brind"; 4836 case ISD::BR_JT: return "br_jt"; 4837 case ISD::BRCOND: return "brcond"; 4838 case ISD::BR_CC: return "br_cc"; 4839 case ISD::RET: return "ret"; 4840 case ISD::CALLSEQ_START: return "callseq_start"; 4841 case ISD::CALLSEQ_END: return "callseq_end"; 4842 4843 // Other operators 4844 case ISD::LOAD: return "load"; 4845 case ISD::STORE: return "store"; 4846 case ISD::VAARG: return "vaarg"; 4847 case ISD::VACOPY: return "vacopy"; 4848 case ISD::VAEND: return "vaend"; 4849 case ISD::VASTART: return "vastart"; 4850 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 4851 case ISD::EXTRACT_ELEMENT: return "extract_element"; 4852 case ISD::BUILD_PAIR: return "build_pair"; 4853 case ISD::STACKSAVE: return "stacksave"; 4854 case ISD::STACKRESTORE: return "stackrestore"; 4855 case ISD::TRAP: return "trap"; 4856 4857 // Bit manipulation 4858 case ISD::BSWAP: return "bswap"; 4859 case ISD::CTPOP: return "ctpop"; 4860 case ISD::CTTZ: return "cttz"; 4861 case ISD::CTLZ: return "ctlz"; 4862 4863 // Debug info 4864 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 4865 case ISD::DEBUG_LOC: return "debug_loc"; 4866 4867 // Trampolines 4868 case ISD::TRAMPOLINE: return "trampoline"; 4869 4870 case ISD::CONDCODE: 4871 switch (cast<CondCodeSDNode>(this)->get()) { 4872 default: assert(0 && "Unknown setcc condition!"); 4873 case ISD::SETOEQ: return "setoeq"; 4874 case ISD::SETOGT: return "setogt"; 4875 case ISD::SETOGE: return "setoge"; 4876 case ISD::SETOLT: return "setolt"; 4877 case ISD::SETOLE: return "setole"; 4878 case ISD::SETONE: return "setone"; 4879 4880 case ISD::SETO: return "seto"; 4881 case ISD::SETUO: return "setuo"; 4882 case ISD::SETUEQ: return "setue"; 4883 case ISD::SETUGT: return "setugt"; 4884 case ISD::SETUGE: return "setuge"; 4885 case ISD::SETULT: return "setult"; 4886 case ISD::SETULE: return "setule"; 4887 case ISD::SETUNE: return "setune"; 4888 4889 case ISD::SETEQ: return "seteq"; 4890 case ISD::SETGT: return "setgt"; 4891 case ISD::SETGE: return "setge"; 4892 case ISD::SETLT: return "setlt"; 4893 case ISD::SETLE: return "setle"; 4894 case ISD::SETNE: return "setne"; 4895 } 4896 } 4897} 4898 4899const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 4900 switch (AM) { 4901 default: 4902 return ""; 4903 case ISD::PRE_INC: 4904 return "<pre-inc>"; 4905 case ISD::PRE_DEC: 4906 return "<pre-dec>"; 4907 case ISD::POST_INC: 4908 return "<post-inc>"; 4909 case ISD::POST_DEC: 4910 return "<post-dec>"; 4911 } 4912} 4913 4914std::string ISD::ArgFlagsTy::getArgFlagsString() { 4915 std::string S = "< "; 4916 4917 if (isZExt()) 4918 S += "zext "; 4919 if (isSExt()) 4920 S += "sext "; 4921 if (isInReg()) 4922 S += "inreg "; 4923 if (isSRet()) 4924 S += "sret "; 4925 if (isByVal()) 4926 S += "byval "; 4927 if (isNest()) 4928 S += "nest "; 4929 if (getByValAlign()) 4930 S += "byval-align:" + utostr(getByValAlign()) + " "; 4931 if (getOrigAlign()) 4932 S += "orig-align:" + utostr(getOrigAlign()) + " "; 4933 if (getByValSize()) 4934 S += "byval-size:" + utostr(getByValSize()) + " "; 4935 return S + ">"; 4936} 4937 4938void SDNode::dump() const { dump(0); } 4939void SDNode::dump(const SelectionDAG *G) const { 4940 cerr << (void*)this << ": "; 4941 4942 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 4943 if (i) cerr << ","; 4944 if (getValueType(i) == MVT::Other) 4945 cerr << "ch"; 4946 else 4947 cerr << getValueType(i).getMVTString(); 4948 } 4949 cerr << " = " << getOperationName(G); 4950 4951 cerr << " "; 4952 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 4953 if (i) cerr << ", "; 4954 cerr << (void*)getOperand(i).Val; 4955 if (unsigned RN = getOperand(i).ResNo) 4956 cerr << ":" << RN; 4957 } 4958 4959 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 4960 SDNode *Mask = getOperand(2).Val; 4961 cerr << "<"; 4962 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 4963 if (i) cerr << ","; 4964 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 4965 cerr << "u"; 4966 else 4967 cerr << cast<ConstantSDNode>(Mask->getOperand(i))->getValue(); 4968 } 4969 cerr << ">"; 4970 } 4971 4972 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 4973 cerr << "<" << CSDN->getAPIntValue().toStringUnsigned() << ">"; 4974 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 4975 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 4976 cerr << "<" << CSDN->getValueAPF().convertToFloat() << ">"; 4977 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 4978 cerr << "<" << CSDN->getValueAPF().convertToDouble() << ">"; 4979 else { 4980 cerr << "<APFloat("; 4981 CSDN->getValueAPF().convertToAPInt().dump(); 4982 cerr << ")>"; 4983 } 4984 } else if (const GlobalAddressSDNode *GADN = 4985 dyn_cast<GlobalAddressSDNode>(this)) { 4986 int offset = GADN->getOffset(); 4987 cerr << "<"; 4988 WriteAsOperand(*cerr.stream(), GADN->getGlobal()) << ">"; 4989 if (offset > 0) 4990 cerr << " + " << offset; 4991 else 4992 cerr << " " << offset; 4993 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 4994 cerr << "<" << FIDN->getIndex() << ">"; 4995 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 4996 cerr << "<" << JTDN->getIndex() << ">"; 4997 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 4998 int offset = CP->getOffset(); 4999 if (CP->isMachineConstantPoolEntry()) 5000 cerr << "<" << *CP->getMachineCPVal() << ">"; 5001 else 5002 cerr << "<" << *CP->getConstVal() << ">"; 5003 if (offset > 0) 5004 cerr << " + " << offset; 5005 else 5006 cerr << " " << offset; 5007 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5008 cerr << "<"; 5009 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5010 if (LBB) 5011 cerr << LBB->getName() << " "; 5012 cerr << (const void*)BBDN->getBasicBlock() << ">"; 5013 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5014 if (G && R->getReg() && 5015 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5016 cerr << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5017 } else { 5018 cerr << " #" << R->getReg(); 5019 } 5020 } else if (const ExternalSymbolSDNode *ES = 5021 dyn_cast<ExternalSymbolSDNode>(this)) { 5022 cerr << "'" << ES->getSymbol() << "'"; 5023 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5024 if (M->getValue()) 5025 cerr << "<" << M->getValue() << ">"; 5026 else 5027 cerr << "<null>"; 5028 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5029 if (M->MO.getValue()) 5030 cerr << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5031 else 5032 cerr << "<null:" << M->MO.getOffset() << ">"; 5033 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5034 cerr << N->getArgFlags().getArgFlagsString(); 5035 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5036 cerr << ":" << N->getVT().getMVTString(); 5037 } 5038 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5039 const Value *SrcValue = LD->getSrcValue(); 5040 int SrcOffset = LD->getSrcValueOffset(); 5041 cerr << " <"; 5042 if (SrcValue) 5043 cerr << SrcValue; 5044 else 5045 cerr << "null"; 5046 cerr << ":" << SrcOffset << ">"; 5047 5048 bool doExt = true; 5049 switch (LD->getExtensionType()) { 5050 default: doExt = false; break; 5051 case ISD::EXTLOAD: 5052 cerr << " <anyext "; 5053 break; 5054 case ISD::SEXTLOAD: 5055 cerr << " <sext "; 5056 break; 5057 case ISD::ZEXTLOAD: 5058 cerr << " <zext "; 5059 break; 5060 } 5061 if (doExt) 5062 cerr << LD->getMemoryVT().getMVTString() << ">"; 5063 5064 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5065 if (*AM) 5066 cerr << " " << AM; 5067 if (LD->isVolatile()) 5068 cerr << " <volatile>"; 5069 cerr << " alignment=" << LD->getAlignment(); 5070 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5071 const Value *SrcValue = ST->getSrcValue(); 5072 int SrcOffset = ST->getSrcValueOffset(); 5073 cerr << " <"; 5074 if (SrcValue) 5075 cerr << SrcValue; 5076 else 5077 cerr << "null"; 5078 cerr << ":" << SrcOffset << ">"; 5079 5080 if (ST->isTruncatingStore()) 5081 cerr << " <trunc " 5082 << ST->getMemoryVT().getMVTString() << ">"; 5083 5084 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5085 if (*AM) 5086 cerr << " " << AM; 5087 if (ST->isVolatile()) 5088 cerr << " <volatile>"; 5089 cerr << " alignment=" << ST->getAlignment(); 5090 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5091 const Value *SrcValue = AT->getSrcValue(); 5092 int SrcOffset = AT->getSrcValueOffset(); 5093 cerr << " <"; 5094 if (SrcValue) 5095 cerr << SrcValue; 5096 else 5097 cerr << "null"; 5098 cerr << ":" << SrcOffset << ">"; 5099 if (AT->isVolatile()) 5100 cerr << " <volatile>"; 5101 cerr << " alignment=" << AT->getAlignment(); 5102 } 5103} 5104 5105static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5106 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5107 if (N->getOperand(i).Val->hasOneUse()) 5108 DumpNodes(N->getOperand(i).Val, indent+2, G); 5109 else 5110 cerr << "\n" << std::string(indent+2, ' ') 5111 << (void*)N->getOperand(i).Val << ": <multiple use>"; 5112 5113 5114 cerr << "\n" << std::string(indent, ' '); 5115 N->dump(G); 5116} 5117 5118void SelectionDAG::dump() const { 5119 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5120 5121 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5122 I != E; ++I) { 5123 const SDNode *N = I; 5124 if (!N->hasOneUse() && N != getRoot().Val) 5125 DumpNodes(N, 2, this); 5126 } 5127 5128 if (getRoot().Val) DumpNodes(getRoot().Val, 2, this); 5129 5130 cerr << "\n\n"; 5131} 5132 5133const Type *ConstantPoolSDNode::getType() const { 5134 if (isMachineConstantPoolEntry()) 5135 return Val.MachineCPVal->getType(); 5136 return Val.ConstVal->getType(); 5137} 5138