SelectionDAG.cpp revision 6b61cd185eeb90bec93f042535594132ae1f0f41
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/ManagedStatic.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/System/Mutex.h" 38#include "llvm/ADT/SetVector.h" 39#include "llvm/ADT/SmallPtrSet.h" 40#include "llvm/ADT/SmallSet.h" 41#include "llvm/ADT/SmallVector.h" 42#include "llvm/ADT/StringExtras.h" 43#include <algorithm> 44#include <cmath> 45using namespace llvm; 46 47/// makeVTList - Return an instance of the SDVTList struct initialized with the 48/// specified members. 49static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 50 SDVTList Res = {VTs, NumVTs}; 51 return Res; 52} 53 54static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 55 switch (VT.getSimpleVT()) { 56 default: assert(0 && "Unknown FP format"); 57 case MVT::f32: return &APFloat::IEEEsingle; 58 case MVT::f64: return &APFloat::IEEEdouble; 59 case MVT::f80: return &APFloat::x87DoubleExtended; 60 case MVT::f128: return &APFloat::IEEEquad; 61 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 62 } 63} 64 65SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 66 67//===----------------------------------------------------------------------===// 68// ConstantFPSDNode Class 69//===----------------------------------------------------------------------===// 70 71/// isExactlyValue - We don't rely on operator== working on double values, as 72/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 73/// As such, this method can be used to do an exact bit-for-bit comparison of 74/// two floating point values. 75bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 76 return getValueAPF().bitwiseIsEqual(V); 77} 78 79bool ConstantFPSDNode::isValueValidForType(MVT VT, 80 const APFloat& Val) { 81 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 82 83 // PPC long double cannot be converted to any other type. 84 if (VT == MVT::ppcf128 || 85 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 86 return false; 87 88 // convert modifies in place, so make a copy. 89 APFloat Val2 = APFloat(Val); 90 bool losesInfo; 91 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 92 &losesInfo); 93 return !losesInfo; 94} 95 96//===----------------------------------------------------------------------===// 97// ISD Namespace 98//===----------------------------------------------------------------------===// 99 100/// isBuildVectorAllOnes - Return true if the specified node is a 101/// BUILD_VECTOR where all of the elements are ~0 or undef. 102bool ISD::isBuildVectorAllOnes(const SDNode *N) { 103 // Look through a bit convert. 104 if (N->getOpcode() == ISD::BIT_CONVERT) 105 N = N->getOperand(0).getNode(); 106 107 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 108 109 unsigned i = 0, e = N->getNumOperands(); 110 111 // Skip over all of the undef values. 112 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 113 ++i; 114 115 // Do not accept an all-undef vector. 116 if (i == e) return false; 117 118 // Do not accept build_vectors that aren't all constants or which have non-~0 119 // elements. 120 SDValue NotZero = N->getOperand(i); 121 if (isa<ConstantSDNode>(NotZero)) { 122 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 123 return false; 124 } else if (isa<ConstantFPSDNode>(NotZero)) { 125 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 126 bitcastToAPInt().isAllOnesValue()) 127 return false; 128 } else 129 return false; 130 131 // Okay, we have at least one ~0 value, check to see if the rest match or are 132 // undefs. 133 for (++i; i != e; ++i) 134 if (N->getOperand(i) != NotZero && 135 N->getOperand(i).getOpcode() != ISD::UNDEF) 136 return false; 137 return true; 138} 139 140 141/// isBuildVectorAllZeros - Return true if the specified node is a 142/// BUILD_VECTOR where all of the elements are 0 or undef. 143bool ISD::isBuildVectorAllZeros(const SDNode *N) { 144 // Look through a bit convert. 145 if (N->getOpcode() == ISD::BIT_CONVERT) 146 N = N->getOperand(0).getNode(); 147 148 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 149 150 unsigned i = 0, e = N->getNumOperands(); 151 152 // Skip over all of the undef values. 153 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 154 ++i; 155 156 // Do not accept an all-undef vector. 157 if (i == e) return false; 158 159 // Do not accept build_vectors that aren't all constants or which have non-0 160 // elements. 161 SDValue Zero = N->getOperand(i); 162 if (isa<ConstantSDNode>(Zero)) { 163 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 164 return false; 165 } else if (isa<ConstantFPSDNode>(Zero)) { 166 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 167 return false; 168 } else 169 return false; 170 171 // Okay, we have at least one 0 value, check to see if the rest match or are 172 // undefs. 173 for (++i; i != e; ++i) 174 if (N->getOperand(i) != Zero && 175 N->getOperand(i).getOpcode() != ISD::UNDEF) 176 return false; 177 return true; 178} 179 180/// isScalarToVector - Return true if the specified node is a 181/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 182/// element is not an undef. 183bool ISD::isScalarToVector(const SDNode *N) { 184 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 185 return true; 186 187 if (N->getOpcode() != ISD::BUILD_VECTOR) 188 return false; 189 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 190 return false; 191 unsigned NumElems = N->getNumOperands(); 192 for (unsigned i = 1; i < NumElems; ++i) { 193 SDValue V = N->getOperand(i); 194 if (V.getOpcode() != ISD::UNDEF) 195 return false; 196 } 197 return true; 198} 199 200 201/// isDebugLabel - Return true if the specified node represents a debug 202/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 203bool ISD::isDebugLabel(const SDNode *N) { 204 SDValue Zero; 205 if (N->getOpcode() == ISD::DBG_LABEL) 206 return true; 207 if (N->isMachineOpcode() && 208 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 209 return true; 210 return false; 211} 212 213/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 214/// when given the operation for (X op Y). 215ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 216 // To perform this operation, we just need to swap the L and G bits of the 217 // operation. 218 unsigned OldL = (Operation >> 2) & 1; 219 unsigned OldG = (Operation >> 1) & 1; 220 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 221 (OldL << 1) | // New G bit 222 (OldG << 2)); // New L bit. 223} 224 225/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 226/// 'op' is a valid SetCC operation. 227ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 228 unsigned Operation = Op; 229 if (isInteger) 230 Operation ^= 7; // Flip L, G, E bits, but not U. 231 else 232 Operation ^= 15; // Flip all of the condition bits. 233 234 if (Operation > ISD::SETTRUE2) 235 Operation &= ~8; // Don't let N and U bits get set. 236 237 return ISD::CondCode(Operation); 238} 239 240 241/// isSignedOp - For an integer comparison, return 1 if the comparison is a 242/// signed operation and 2 if the result is an unsigned comparison. Return zero 243/// if the operation does not depend on the sign of the input (setne and seteq). 244static int isSignedOp(ISD::CondCode Opcode) { 245 switch (Opcode) { 246 default: assert(0 && "Illegal integer setcc operation!"); 247 case ISD::SETEQ: 248 case ISD::SETNE: return 0; 249 case ISD::SETLT: 250 case ISD::SETLE: 251 case ISD::SETGT: 252 case ISD::SETGE: return 1; 253 case ISD::SETULT: 254 case ISD::SETULE: 255 case ISD::SETUGT: 256 case ISD::SETUGE: return 2; 257 } 258} 259 260/// getSetCCOrOperation - Return the result of a logical OR between different 261/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 262/// returns SETCC_INVALID if it is not possible to represent the resultant 263/// comparison. 264ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 265 bool isInteger) { 266 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 267 // Cannot fold a signed integer setcc with an unsigned integer setcc. 268 return ISD::SETCC_INVALID; 269 270 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 271 272 // If the N and U bits get set then the resultant comparison DOES suddenly 273 // care about orderedness, and is true when ordered. 274 if (Op > ISD::SETTRUE2) 275 Op &= ~16; // Clear the U bit if the N bit is set. 276 277 // Canonicalize illegal integer setcc's. 278 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 279 Op = ISD::SETNE; 280 281 return ISD::CondCode(Op); 282} 283 284/// getSetCCAndOperation - Return the result of a logical AND between different 285/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 286/// function returns zero if it is not possible to represent the resultant 287/// comparison. 288ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 289 bool isInteger) { 290 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 291 // Cannot fold a signed setcc with an unsigned setcc. 292 return ISD::SETCC_INVALID; 293 294 // Combine all of the condition bits. 295 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 296 297 // Canonicalize illegal integer setcc's. 298 if (isInteger) { 299 switch (Result) { 300 default: break; 301 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 302 case ISD::SETOEQ: // SETEQ & SETU[LG]E 303 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 304 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 305 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 306 } 307 } 308 309 return Result; 310} 311 312const TargetMachine &SelectionDAG::getTarget() const { 313 return MF->getTarget(); 314} 315 316//===----------------------------------------------------------------------===// 317// SDNode Profile Support 318//===----------------------------------------------------------------------===// 319 320/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 321/// 322static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 323 ID.AddInteger(OpC); 324} 325 326/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 327/// solely with their pointer. 328static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 329 ID.AddPointer(VTList.VTs); 330} 331 332/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 333/// 334static void AddNodeIDOperands(FoldingSetNodeID &ID, 335 const SDValue *Ops, unsigned NumOps) { 336 for (; NumOps; --NumOps, ++Ops) { 337 ID.AddPointer(Ops->getNode()); 338 ID.AddInteger(Ops->getResNo()); 339 } 340} 341 342/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 343/// 344static void AddNodeIDOperands(FoldingSetNodeID &ID, 345 const SDUse *Ops, unsigned NumOps) { 346 for (; NumOps; --NumOps, ++Ops) { 347 ID.AddPointer(Ops->getNode()); 348 ID.AddInteger(Ops->getResNo()); 349 } 350} 351 352static void AddNodeIDNode(FoldingSetNodeID &ID, 353 unsigned short OpC, SDVTList VTList, 354 const SDValue *OpList, unsigned N) { 355 AddNodeIDOpcode(ID, OpC); 356 AddNodeIDValueTypes(ID, VTList); 357 AddNodeIDOperands(ID, OpList, N); 358} 359 360/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 361/// the NodeID data. 362static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 363 switch (N->getOpcode()) { 364 case ISD::TargetExternalSymbol: 365 case ISD::ExternalSymbol: 366 assert(0 && "Should only be used on nodes with operands"); 367 default: break; // Normal nodes don't need extra info. 368 case ISD::ARG_FLAGS: 369 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 370 break; 371 case ISD::TargetConstant: 372 case ISD::Constant: 373 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 374 break; 375 case ISD::TargetConstantFP: 376 case ISD::ConstantFP: { 377 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 378 break; 379 } 380 case ISD::TargetGlobalAddress: 381 case ISD::GlobalAddress: 382 case ISD::TargetGlobalTLSAddress: 383 case ISD::GlobalTLSAddress: { 384 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 385 ID.AddPointer(GA->getGlobal()); 386 ID.AddInteger(GA->getOffset()); 387 ID.AddInteger(GA->getTargetFlags()); 388 break; 389 } 390 case ISD::BasicBlock: 391 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 392 break; 393 case ISD::Register: 394 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 395 break; 396 case ISD::DBG_STOPPOINT: { 397 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 398 ID.AddInteger(DSP->getLine()); 399 ID.AddInteger(DSP->getColumn()); 400 ID.AddPointer(DSP->getCompileUnit()); 401 break; 402 } 403 case ISD::SRCVALUE: 404 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 405 break; 406 case ISD::MEMOPERAND: { 407 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 408 MO.Profile(ID); 409 break; 410 } 411 case ISD::FrameIndex: 412 case ISD::TargetFrameIndex: 413 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 414 break; 415 case ISD::JumpTable: 416 case ISD::TargetJumpTable: 417 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 418 ID.AddInteger(cast<JumpTableSDNode>(N)->getTargetFlags()); 419 break; 420 case ISD::ConstantPool: 421 case ISD::TargetConstantPool: { 422 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 423 ID.AddInteger(CP->getAlignment()); 424 ID.AddInteger(CP->getOffset()); 425 if (CP->isMachineConstantPoolEntry()) 426 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 427 else 428 ID.AddPointer(CP->getConstVal()); 429 ID.AddInteger(CP->getTargetFlags()); 430 break; 431 } 432 case ISD::CALL: { 433 const CallSDNode *Call = cast<CallSDNode>(N); 434 ID.AddInteger(Call->getCallingConv()); 435 ID.AddInteger(Call->isVarArg()); 436 break; 437 } 438 case ISD::LOAD: { 439 const LoadSDNode *LD = cast<LoadSDNode>(N); 440 ID.AddInteger(LD->getMemoryVT().getRawBits()); 441 ID.AddInteger(LD->getRawSubclassData()); 442 break; 443 } 444 case ISD::STORE: { 445 const StoreSDNode *ST = cast<StoreSDNode>(N); 446 ID.AddInteger(ST->getMemoryVT().getRawBits()); 447 ID.AddInteger(ST->getRawSubclassData()); 448 break; 449 } 450 case ISD::ATOMIC_CMP_SWAP: 451 case ISD::ATOMIC_SWAP: 452 case ISD::ATOMIC_LOAD_ADD: 453 case ISD::ATOMIC_LOAD_SUB: 454 case ISD::ATOMIC_LOAD_AND: 455 case ISD::ATOMIC_LOAD_OR: 456 case ISD::ATOMIC_LOAD_XOR: 457 case ISD::ATOMIC_LOAD_NAND: 458 case ISD::ATOMIC_LOAD_MIN: 459 case ISD::ATOMIC_LOAD_MAX: 460 case ISD::ATOMIC_LOAD_UMIN: 461 case ISD::ATOMIC_LOAD_UMAX: { 462 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 463 ID.AddInteger(AT->getMemoryVT().getRawBits()); 464 ID.AddInteger(AT->getRawSubclassData()); 465 break; 466 } 467 case ISD::VECTOR_SHUFFLE: { 468 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 469 for (unsigned i = 0, e = N->getValueType(0).getVectorNumElements(); 470 i != e; ++i) 471 ID.AddInteger(SVN->getMaskElt(i)); 472 break; 473 } 474 } // end switch (N->getOpcode()) 475} 476 477/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 478/// data. 479static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 480 AddNodeIDOpcode(ID, N->getOpcode()); 481 // Add the return value info. 482 AddNodeIDValueTypes(ID, N->getVTList()); 483 // Add the operand info. 484 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 485 486 // Handle SDNode leafs with special info. 487 AddNodeIDCustom(ID, N); 488} 489 490/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 491/// the CSE map that carries alignment, volatility, indexing mode, and 492/// extension/truncation information. 493/// 494static inline unsigned 495encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, 496 bool isVolatile, unsigned Alignment) { 497 assert((ConvType & 3) == ConvType && 498 "ConvType may not require more than 2 bits!"); 499 assert((AM & 7) == AM && 500 "AM may not require more than 3 bits!"); 501 return ConvType | 502 (AM << 2) | 503 (isVolatile << 5) | 504 ((Log2_32(Alignment) + 1) << 6); 505} 506 507//===----------------------------------------------------------------------===// 508// SelectionDAG Class 509//===----------------------------------------------------------------------===// 510 511/// doNotCSE - Return true if CSE should not be performed for this node. 512static bool doNotCSE(SDNode *N) { 513 if (N->getValueType(0) == MVT::Flag) 514 return true; // Never CSE anything that produces a flag. 515 516 switch (N->getOpcode()) { 517 default: break; 518 case ISD::HANDLENODE: 519 case ISD::DBG_LABEL: 520 case ISD::DBG_STOPPOINT: 521 case ISD::EH_LABEL: 522 case ISD::DECLARE: 523 return true; // Never CSE these nodes. 524 } 525 526 // Check that remaining values produced are not flags. 527 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 528 if (N->getValueType(i) == MVT::Flag) 529 return true; // Never CSE anything that produces a flag. 530 531 return false; 532} 533 534/// RemoveDeadNodes - This method deletes all unreachable nodes in the 535/// SelectionDAG. 536void SelectionDAG::RemoveDeadNodes() { 537 // Create a dummy node (which is not added to allnodes), that adds a reference 538 // to the root node, preventing it from being deleted. 539 HandleSDNode Dummy(getRoot()); 540 541 SmallVector<SDNode*, 128> DeadNodes; 542 543 // Add all obviously-dead nodes to the DeadNodes worklist. 544 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 545 if (I->use_empty()) 546 DeadNodes.push_back(I); 547 548 RemoveDeadNodes(DeadNodes); 549 550 // If the root changed (e.g. it was a dead load, update the root). 551 setRoot(Dummy.getValue()); 552} 553 554/// RemoveDeadNodes - This method deletes the unreachable nodes in the 555/// given list, and any nodes that become unreachable as a result. 556void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 557 DAGUpdateListener *UpdateListener) { 558 559 // Process the worklist, deleting the nodes and adding their uses to the 560 // worklist. 561 while (!DeadNodes.empty()) { 562 SDNode *N = DeadNodes.pop_back_val(); 563 564 if (UpdateListener) 565 UpdateListener->NodeDeleted(N, 0); 566 567 // Take the node out of the appropriate CSE map. 568 RemoveNodeFromCSEMaps(N); 569 570 // Next, brutally remove the operand list. This is safe to do, as there are 571 // no cycles in the graph. 572 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 573 SDUse &Use = *I++; 574 SDNode *Operand = Use.getNode(); 575 Use.set(SDValue()); 576 577 // Now that we removed this operand, see if there are no uses of it left. 578 if (Operand->use_empty()) 579 DeadNodes.push_back(Operand); 580 } 581 582 DeallocateNode(N); 583 } 584} 585 586void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 587 SmallVector<SDNode*, 16> DeadNodes(1, N); 588 RemoveDeadNodes(DeadNodes, UpdateListener); 589} 590 591void SelectionDAG::DeleteNode(SDNode *N) { 592 // First take this out of the appropriate CSE map. 593 RemoveNodeFromCSEMaps(N); 594 595 // Finally, remove uses due to operands of this node, remove from the 596 // AllNodes list, and delete the node. 597 DeleteNodeNotInCSEMaps(N); 598} 599 600void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 601 assert(N != AllNodes.begin() && "Cannot delete the entry node!"); 602 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 603 604 // Drop all of the operands and decrement used node's use counts. 605 N->DropOperands(); 606 607 DeallocateNode(N); 608} 609 610void SelectionDAG::DeallocateNode(SDNode *N) { 611 if (N->OperandsNeedDelete) 612 delete[] N->OperandList; 613 614 // Set the opcode to DELETED_NODE to help catch bugs when node 615 // memory is reallocated. 616 N->NodeType = ISD::DELETED_NODE; 617 618 NodeAllocator.Deallocate(AllNodes.remove(N)); 619} 620 621/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 622/// correspond to it. This is useful when we're about to delete or repurpose 623/// the node. We don't want future request for structurally identical nodes 624/// to return N anymore. 625bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 626 bool Erased = false; 627 switch (N->getOpcode()) { 628 case ISD::EntryToken: 629 assert(0 && "EntryToken should not be in CSEMaps!"); 630 return false; 631 case ISD::HANDLENODE: return false; // noop. 632 case ISD::CONDCODE: 633 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 634 "Cond code doesn't exist!"); 635 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 636 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 637 break; 638 case ISD::ExternalSymbol: 639 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 640 break; 641 case ISD::TargetExternalSymbol: { 642 ExternalSymbolSDNode *ESN = cast<ExternalSymbolSDNode>(N); 643 Erased = TargetExternalSymbols.erase( 644 std::pair<std::string,unsigned char>(ESN->getSymbol(), 645 ESN->getTargetFlags())); 646 break; 647 } 648 case ISD::VALUETYPE: { 649 MVT VT = cast<VTSDNode>(N)->getVT(); 650 if (VT.isExtended()) { 651 Erased = ExtendedValueTypeNodes.erase(VT); 652 } else { 653 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 654 ValueTypeNodes[VT.getSimpleVT()] = 0; 655 } 656 break; 657 } 658 default: 659 // Remove it from the CSE Map. 660 Erased = CSEMap.RemoveNode(N); 661 break; 662 } 663#ifndef NDEBUG 664 // Verify that the node was actually in one of the CSE maps, unless it has a 665 // flag result (which cannot be CSE'd) or is one of the special cases that are 666 // not subject to CSE. 667 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 668 !N->isMachineOpcode() && !doNotCSE(N)) { 669 N->dump(this); 670 cerr << "\n"; 671 assert(0 && "Node is not in map!"); 672 } 673#endif 674 return Erased; 675} 676 677/// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE 678/// maps and modified in place. Add it back to the CSE maps, unless an identical 679/// node already exists, in which case transfer all its users to the existing 680/// node. This transfer can potentially trigger recursive merging. 681/// 682void 683SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N, 684 DAGUpdateListener *UpdateListener) { 685 // For node types that aren't CSE'd, just act as if no identical node 686 // already exists. 687 if (!doNotCSE(N)) { 688 SDNode *Existing = CSEMap.GetOrInsertNode(N); 689 if (Existing != N) { 690 // If there was already an existing matching node, use ReplaceAllUsesWith 691 // to replace the dead one with the existing one. This can cause 692 // recursive merging of other unrelated nodes down the line. 693 ReplaceAllUsesWith(N, Existing, UpdateListener); 694 695 // N is now dead. Inform the listener if it exists and delete it. 696 if (UpdateListener) 697 UpdateListener->NodeDeleted(N, Existing); 698 DeleteNodeNotInCSEMaps(N); 699 return; 700 } 701 } 702 703 // If the node doesn't already exist, we updated it. Inform a listener if 704 // it exists. 705 if (UpdateListener) 706 UpdateListener->NodeUpdated(N); 707} 708 709/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 710/// were replaced with those specified. If this node is never memoized, 711/// return null, otherwise return a pointer to the slot it would take. If a 712/// node already exists with these operands, the slot will be non-null. 713SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 714 void *&InsertPos) { 715 if (doNotCSE(N)) 716 return 0; 717 718 SDValue Ops[] = { Op }; 719 FoldingSetNodeID ID; 720 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 721 AddNodeIDCustom(ID, N); 722 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 723} 724 725/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 726/// were replaced with those specified. If this node is never memoized, 727/// return null, otherwise return a pointer to the slot it would take. If a 728/// node already exists with these operands, the slot will be non-null. 729SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 730 SDValue Op1, SDValue Op2, 731 void *&InsertPos) { 732 if (doNotCSE(N)) 733 return 0; 734 735 SDValue Ops[] = { Op1, Op2 }; 736 FoldingSetNodeID ID; 737 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 738 AddNodeIDCustom(ID, N); 739 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 740} 741 742 743/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 744/// were replaced with those specified. If this node is never memoized, 745/// return null, otherwise return a pointer to the slot it would take. If a 746/// node already exists with these operands, the slot will be non-null. 747SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 748 const SDValue *Ops,unsigned NumOps, 749 void *&InsertPos) { 750 if (doNotCSE(N)) 751 return 0; 752 753 FoldingSetNodeID ID; 754 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 755 AddNodeIDCustom(ID, N); 756 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 757} 758 759/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 760void SelectionDAG::VerifyNode(SDNode *N) { 761 switch (N->getOpcode()) { 762 default: 763 break; 764 case ISD::BUILD_PAIR: { 765 MVT VT = N->getValueType(0); 766 assert(N->getNumValues() == 1 && "Too many results!"); 767 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 768 "Wrong return type!"); 769 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 770 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 771 "Mismatched operand types!"); 772 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 773 "Wrong operand type!"); 774 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 775 "Wrong return type size"); 776 break; 777 } 778 case ISD::BUILD_VECTOR: { 779 assert(N->getNumValues() == 1 && "Too many results!"); 780 assert(N->getValueType(0).isVector() && "Wrong return type!"); 781 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 782 "Wrong number of operands!"); 783 MVT EltVT = N->getValueType(0).getVectorElementType(); 784 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 785 assert((I->getValueType() == EltVT || 786 (EltVT.isInteger() && I->getValueType().isInteger() && 787 EltVT.bitsLE(I->getValueType()))) && 788 "Wrong operand type!"); 789 break; 790 } 791 } 792} 793 794/// getMVTAlignment - Compute the default alignment value for the 795/// given type. 796/// 797unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 798 const Type *Ty = VT == MVT::iPTR ? 799 PointerType::get(Type::Int8Ty, 0) : 800 VT.getTypeForMVT(); 801 802 return TLI.getTargetData()->getABITypeAlignment(Ty); 803} 804 805// EntryNode could meaningfully have debug info if we can find it... 806SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 807 : TLI(tli), FLI(fli), DW(0), 808 EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(), 809 getVTList(MVT::Other)), Root(getEntryNode()) { 810 AllNodes.push_back(&EntryNode); 811} 812 813void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi, 814 DwarfWriter *dw) { 815 MF = &mf; 816 MMI = mmi; 817 DW = dw; 818} 819 820SelectionDAG::~SelectionDAG() { 821 allnodes_clear(); 822} 823 824void SelectionDAG::allnodes_clear() { 825 assert(&*AllNodes.begin() == &EntryNode); 826 AllNodes.remove(AllNodes.begin()); 827 while (!AllNodes.empty()) 828 DeallocateNode(AllNodes.begin()); 829} 830 831void SelectionDAG::clear() { 832 allnodes_clear(); 833 OperandAllocator.Reset(); 834 CSEMap.clear(); 835 836 ExtendedValueTypeNodes.clear(); 837 ExternalSymbols.clear(); 838 TargetExternalSymbols.clear(); 839 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 840 static_cast<CondCodeSDNode*>(0)); 841 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 842 static_cast<SDNode*>(0)); 843 844 EntryNode.UseList = 0; 845 AllNodes.push_back(&EntryNode); 846 Root = getEntryNode(); 847} 848 849SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { 850 if (Op.getValueType() == VT) return Op; 851 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 852 VT.getSizeInBits()); 853 return getNode(ISD::AND, DL, Op.getValueType(), Op, 854 getConstant(Imm, Op.getValueType())); 855} 856 857/// getNOT - Create a bitwise NOT operation as (XOR Val, -1). 858/// 859SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) { 860 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 861 SDValue NegOne = 862 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 863 return getNode(ISD::XOR, DL, VT, Val, NegOne); 864} 865 866SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 867 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 868 assert((EltVT.getSizeInBits() >= 64 || 869 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) && 870 "getConstant with a uint64_t value that doesn't fit in the type!"); 871 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 872} 873 874SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 875 return getConstant(*ConstantInt::get(Val), VT, isT); 876} 877 878SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 879 assert(VT.isInteger() && "Cannot create FP integer constant!"); 880 881 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 882 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 883 "APInt size does not match type size!"); 884 885 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 886 FoldingSetNodeID ID; 887 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 888 ID.AddPointer(&Val); 889 void *IP = 0; 890 SDNode *N = NULL; 891 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 892 if (!VT.isVector()) 893 return SDValue(N, 0); 894 if (!N) { 895 N = NodeAllocator.Allocate<ConstantSDNode>(); 896 new (N) ConstantSDNode(isT, &Val, EltVT); 897 CSEMap.InsertNode(N, IP); 898 AllNodes.push_back(N); 899 } 900 901 SDValue Result(N, 0); 902 if (VT.isVector()) { 903 SmallVector<SDValue, 8> Ops; 904 Ops.assign(VT.getVectorNumElements(), Result); 905 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 906 VT, &Ops[0], Ops.size()); 907 } 908 return Result; 909} 910 911SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 912 return getConstant(Val, TLI.getPointerTy(), isTarget); 913} 914 915 916SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 917 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 918} 919 920SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 921 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 922 923 MVT EltVT = 924 VT.isVector() ? VT.getVectorElementType() : VT; 925 926 // Do the map lookup using the actual bit pattern for the floating point 927 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 928 // we don't have issues with SNANs. 929 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 930 FoldingSetNodeID ID; 931 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 932 ID.AddPointer(&V); 933 void *IP = 0; 934 SDNode *N = NULL; 935 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 936 if (!VT.isVector()) 937 return SDValue(N, 0); 938 if (!N) { 939 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 940 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 941 CSEMap.InsertNode(N, IP); 942 AllNodes.push_back(N); 943 } 944 945 SDValue Result(N, 0); 946 if (VT.isVector()) { 947 SmallVector<SDValue, 8> Ops; 948 Ops.assign(VT.getVectorNumElements(), Result); 949 // FIXME DebugLoc info might be appropriate here 950 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 951 VT, &Ops[0], Ops.size()); 952 } 953 return Result; 954} 955 956SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 957 MVT EltVT = 958 VT.isVector() ? VT.getVectorElementType() : VT; 959 if (EltVT==MVT::f32) 960 return getConstantFP(APFloat((float)Val), VT, isTarget); 961 else 962 return getConstantFP(APFloat(Val), VT, isTarget); 963} 964 965SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 966 MVT VT, int64_t Offset, 967 bool isTargetGA, 968 unsigned char TargetFlags) { 969 assert((TargetFlags == 0 || isTargetGA) && 970 "Cannot set target flags on target-independent globals"); 971 972 // Truncate (with sign-extension) the offset value to the pointer size. 973 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 974 if (BitWidth < 64) 975 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 976 977 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 978 if (!GVar) { 979 // If GV is an alias then use the aliasee for determining thread-localness. 980 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 981 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 982 } 983 984 unsigned Opc; 985 if (GVar && GVar->isThreadLocal()) 986 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 987 else 988 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 989 990 FoldingSetNodeID ID; 991 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 992 ID.AddPointer(GV); 993 ID.AddInteger(Offset); 994 ID.AddInteger(TargetFlags); 995 void *IP = 0; 996 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 997 return SDValue(E, 0); 998 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 999 new (N) GlobalAddressSDNode(Opc, GV, VT, Offset, TargetFlags); 1000 CSEMap.InsertNode(N, IP); 1001 AllNodes.push_back(N); 1002 return SDValue(N, 0); 1003} 1004 1005SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 1006 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 1007 FoldingSetNodeID ID; 1008 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1009 ID.AddInteger(FI); 1010 void *IP = 0; 1011 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1012 return SDValue(E, 0); 1013 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 1014 new (N) FrameIndexSDNode(FI, VT, isTarget); 1015 CSEMap.InsertNode(N, IP); 1016 AllNodes.push_back(N); 1017 return SDValue(N, 0); 1018} 1019 1020SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget, 1021 unsigned char TargetFlags) { 1022 assert((TargetFlags == 0 || isTarget) && 1023 "Cannot set target flags on target-independent jump tables"); 1024 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1025 FoldingSetNodeID ID; 1026 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1027 ID.AddInteger(JTI); 1028 ID.AddInteger(TargetFlags); 1029 void *IP = 0; 1030 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1031 return SDValue(E, 0); 1032 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1033 new (N) JumpTableSDNode(JTI, VT, isTarget, TargetFlags); 1034 CSEMap.InsertNode(N, IP); 1035 AllNodes.push_back(N); 1036 return SDValue(N, 0); 1037} 1038 1039SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1040 unsigned Alignment, int Offset, 1041 bool isTarget, 1042 unsigned char TargetFlags) { 1043 assert((TargetFlags == 0 || isTarget) && 1044 "Cannot set target flags on target-independent globals"); 1045 if (Alignment == 0) 1046 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1047 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1048 FoldingSetNodeID ID; 1049 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1050 ID.AddInteger(Alignment); 1051 ID.AddInteger(Offset); 1052 ID.AddPointer(C); 1053 ID.AddInteger(TargetFlags); 1054 void *IP = 0; 1055 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1056 return SDValue(E, 0); 1057 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1058 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment, TargetFlags); 1059 CSEMap.InsertNode(N, IP); 1060 AllNodes.push_back(N); 1061 return SDValue(N, 0); 1062} 1063 1064 1065SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1066 unsigned Alignment, int Offset, 1067 bool isTarget, 1068 unsigned char TargetFlags) { 1069 assert((TargetFlags == 0 || isTarget) && 1070 "Cannot set target flags on target-independent globals"); 1071 if (Alignment == 0) 1072 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1073 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1074 FoldingSetNodeID ID; 1075 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1076 ID.AddInteger(Alignment); 1077 ID.AddInteger(Offset); 1078 C->AddSelectionDAGCSEId(ID); 1079 ID.AddInteger(TargetFlags); 1080 void *IP = 0; 1081 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1082 return SDValue(E, 0); 1083 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1084 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment, TargetFlags); 1085 CSEMap.InsertNode(N, IP); 1086 AllNodes.push_back(N); 1087 return SDValue(N, 0); 1088} 1089 1090SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1091 FoldingSetNodeID ID; 1092 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1093 ID.AddPointer(MBB); 1094 void *IP = 0; 1095 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1096 return SDValue(E, 0); 1097 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1098 new (N) BasicBlockSDNode(MBB); 1099 CSEMap.InsertNode(N, IP); 1100 AllNodes.push_back(N); 1101 return SDValue(N, 0); 1102} 1103 1104SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1105 FoldingSetNodeID ID; 1106 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1107 ID.AddInteger(Flags.getRawBits()); 1108 void *IP = 0; 1109 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1110 return SDValue(E, 0); 1111 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1112 new (N) ARG_FLAGSSDNode(Flags); 1113 CSEMap.InsertNode(N, IP); 1114 AllNodes.push_back(N); 1115 return SDValue(N, 0); 1116} 1117 1118SDValue SelectionDAG::getValueType(MVT VT) { 1119 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1120 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1121 1122 SDNode *&N = VT.isExtended() ? 1123 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1124 1125 if (N) return SDValue(N, 0); 1126 N = NodeAllocator.Allocate<VTSDNode>(); 1127 new (N) VTSDNode(VT); 1128 AllNodes.push_back(N); 1129 return SDValue(N, 0); 1130} 1131 1132SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1133 SDNode *&N = ExternalSymbols[Sym]; 1134 if (N) return SDValue(N, 0); 1135 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1136 new (N) ExternalSymbolSDNode(false, Sym, 0, VT); 1137 AllNodes.push_back(N); 1138 return SDValue(N, 0); 1139} 1140 1141SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT, 1142 unsigned char TargetFlags) { 1143 SDNode *&N = 1144 TargetExternalSymbols[std::pair<std::string,unsigned char>(Sym, 1145 TargetFlags)]; 1146 if (N) return SDValue(N, 0); 1147 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1148 new (N) ExternalSymbolSDNode(true, Sym, TargetFlags, VT); 1149 AllNodes.push_back(N); 1150 return SDValue(N, 0); 1151} 1152 1153SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1154 if ((unsigned)Cond >= CondCodeNodes.size()) 1155 CondCodeNodes.resize(Cond+1); 1156 1157 if (CondCodeNodes[Cond] == 0) { 1158 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1159 new (N) CondCodeSDNode(Cond); 1160 CondCodeNodes[Cond] = N; 1161 AllNodes.push_back(N); 1162 } 1163 return SDValue(CondCodeNodes[Cond], 0); 1164} 1165 1166// commuteShuffle - swaps the values of N1 and N2, and swaps all indices in 1167// the shuffle mask M that point at N1 to point at N2, and indices that point 1168// N2 to point at N1. 1169static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) { 1170 std::swap(N1, N2); 1171 int NElts = M.size(); 1172 for (int i = 0; i != NElts; ++i) { 1173 if (M[i] >= NElts) 1174 M[i] -= NElts; 1175 else if (M[i] >= 0) 1176 M[i] += NElts; 1177 } 1178} 1179 1180SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1, 1181 SDValue N2, const int *Mask) { 1182 assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE"); 1183 assert(VT.isVector() && N1.getValueType().isVector() && 1184 "Vector Shuffle VTs must be a vectors"); 1185 assert(VT.getVectorElementType() == N1.getValueType().getVectorElementType() 1186 && "Vector Shuffle VTs must have same element type"); 1187 1188 // Canonicalize shuffle undef, undef -> undef 1189 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF) 1190 return N1; 1191 1192 // Validate that all indices in Mask are within the range of the elements 1193 // input to the shuffle. 1194 unsigned NElts = VT.getVectorNumElements(); 1195 SmallVector<int, 8> MaskVec; 1196 for (unsigned i = 0; i != NElts; ++i) { 1197 assert(Mask[i] < (int)(NElts * 2) && "Index out of range"); 1198 MaskVec.push_back(Mask[i]); 1199 } 1200 1201 // Canonicalize shuffle v, v -> v, undef 1202 if (N1 == N2) { 1203 N2 = getUNDEF(VT); 1204 for (unsigned i = 0; i != NElts; ++i) 1205 if (MaskVec[i] >= (int)NElts) MaskVec[i] -= NElts; 1206 } 1207 1208 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 1209 if (N1.getOpcode() == ISD::UNDEF) 1210 commuteShuffle(N1, N2, MaskVec); 1211 1212 // Canonicalize all index into lhs, -> shuffle lhs, undef 1213 // Canonicalize all index into rhs, -> shuffle rhs, undef 1214 bool AllLHS = true, AllRHS = true; 1215 bool N2Undef = N2.getOpcode() == ISD::UNDEF; 1216 for (unsigned i = 0; i != NElts; ++i) { 1217 if (MaskVec[i] >= (int)NElts) { 1218 if (N2Undef) 1219 MaskVec[i] = -1; 1220 else 1221 AllLHS = false; 1222 } else if (MaskVec[i] >= 0) { 1223 AllRHS = false; 1224 } 1225 } 1226 if (AllLHS && AllRHS) 1227 return getUNDEF(VT); 1228 if (AllLHS && !N2Undef) 1229 N2 = getUNDEF(VT); 1230 if (AllRHS) { 1231 N1 = getUNDEF(VT); 1232 commuteShuffle(N1, N2, MaskVec); 1233 } 1234 1235 // If Identity shuffle, or all shuffle in to undef, return that node. 1236 bool AllUndef = true; 1237 bool Identity = true; 1238 for (unsigned i = 0; i != NElts; ++i) { 1239 if (MaskVec[i] >= 0 && MaskVec[i] != (int)i) Identity = false; 1240 if (MaskVec[i] >= 0) AllUndef = false; 1241 } 1242 if (Identity) 1243 return N1; 1244 if (AllUndef) 1245 return getUNDEF(VT); 1246 1247 FoldingSetNodeID ID; 1248 SDValue Ops[2] = { N1, N2 }; 1249 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2); 1250 for (unsigned i = 0; i != NElts; ++i) 1251 ID.AddInteger(MaskVec[i]); 1252 1253 void* IP = 0; 1254 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1255 return SDValue(E, 0); 1256 1257 // Allocate the mask array for the node out of the BumpPtrAllocator, since 1258 // SDNode doesn't have access to it. This memory will be "leaked" when 1259 // the node is deallocated, but recovered when the NodeAllocator is released. 1260 int *MaskAlloc = OperandAllocator.Allocate<int>(NElts); 1261 memcpy(MaskAlloc, &MaskVec[0], NElts * sizeof(int)); 1262 1263 ShuffleVectorSDNode *N = NodeAllocator.Allocate<ShuffleVectorSDNode>(); 1264 new (N) ShuffleVectorSDNode(VT, dl, N1, N2, MaskAlloc); 1265 CSEMap.InsertNode(N, IP); 1266 AllNodes.push_back(N); 1267 return SDValue(N, 0); 1268} 1269 1270SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl, 1271 SDValue Val, SDValue DTy, 1272 SDValue STy, SDValue Rnd, SDValue Sat, 1273 ISD::CvtCode Code) { 1274 // If the src and dest types are the same and the conversion is between 1275 // integer types of the same sign or two floats, no conversion is necessary. 1276 if (DTy == STy && 1277 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF)) 1278 return Val; 1279 1280 FoldingSetNodeID ID; 1281 void* IP = 0; 1282 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1283 return SDValue(E, 0); 1284 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1285 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1286 new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code); 1287 CSEMap.InsertNode(N, IP); 1288 AllNodes.push_back(N); 1289 return SDValue(N, 0); 1290} 1291 1292SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1293 FoldingSetNodeID ID; 1294 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1295 ID.AddInteger(RegNo); 1296 void *IP = 0; 1297 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1298 return SDValue(E, 0); 1299 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1300 new (N) RegisterSDNode(RegNo, VT); 1301 CSEMap.InsertNode(N, IP); 1302 AllNodes.push_back(N); 1303 return SDValue(N, 0); 1304} 1305 1306SDValue SelectionDAG::getDbgStopPoint(DebugLoc DL, SDValue Root, 1307 unsigned Line, unsigned Col, 1308 Value *CU) { 1309 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1310 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1311 N->setDebugLoc(DL); 1312 AllNodes.push_back(N); 1313 return SDValue(N, 0); 1314} 1315 1316SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, 1317 SDValue Root, 1318 unsigned LabelID) { 1319 FoldingSetNodeID ID; 1320 SDValue Ops[] = { Root }; 1321 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1322 ID.AddInteger(LabelID); 1323 void *IP = 0; 1324 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1325 return SDValue(E, 0); 1326 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1327 new (N) LabelSDNode(Opcode, dl, Root, LabelID); 1328 CSEMap.InsertNode(N, IP); 1329 AllNodes.push_back(N); 1330 return SDValue(N, 0); 1331} 1332 1333SDValue SelectionDAG::getSrcValue(const Value *V) { 1334 assert((!V || isa<PointerType>(V->getType())) && 1335 "SrcValue is not a pointer?"); 1336 1337 FoldingSetNodeID ID; 1338 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1339 ID.AddPointer(V); 1340 1341 void *IP = 0; 1342 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1343 return SDValue(E, 0); 1344 1345 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1346 new (N) SrcValueSDNode(V); 1347 CSEMap.InsertNode(N, IP); 1348 AllNodes.push_back(N); 1349 return SDValue(N, 0); 1350} 1351 1352SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1353#ifndef NDEBUG 1354 const Value *v = MO.getValue(); 1355 assert((!v || isa<PointerType>(v->getType())) && 1356 "SrcValue is not a pointer?"); 1357#endif 1358 1359 FoldingSetNodeID ID; 1360 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1361 MO.Profile(ID); 1362 1363 void *IP = 0; 1364 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1365 return SDValue(E, 0); 1366 1367 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1368 new (N) MemOperandSDNode(MO); 1369 CSEMap.InsertNode(N, IP); 1370 AllNodes.push_back(N); 1371 return SDValue(N, 0); 1372} 1373 1374/// getShiftAmountOperand - Return the specified value casted to 1375/// the target's desired shift amount type. 1376SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { 1377 MVT OpTy = Op.getValueType(); 1378 MVT ShTy = TLI.getShiftAmountTy(); 1379 if (OpTy == ShTy || OpTy.isVector()) return Op; 1380 1381 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1382 return getNode(Opcode, Op.getDebugLoc(), ShTy, Op); 1383} 1384 1385/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1386/// specified value type. 1387SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1388 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1389 unsigned ByteSize = VT.getStoreSizeInBits()/8; 1390 const Type *Ty = VT.getTypeForMVT(); 1391 unsigned StackAlign = 1392 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1393 1394 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1395 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1396} 1397 1398/// CreateStackTemporary - Create a stack temporary suitable for holding 1399/// either of the specified value types. 1400SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) { 1401 unsigned Bytes = std::max(VT1.getStoreSizeInBits(), 1402 VT2.getStoreSizeInBits())/8; 1403 const Type *Ty1 = VT1.getTypeForMVT(); 1404 const Type *Ty2 = VT2.getTypeForMVT(); 1405 const TargetData *TD = TLI.getTargetData(); 1406 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1), 1407 TD->getPrefTypeAlignment(Ty2)); 1408 1409 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1410 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align); 1411 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1412} 1413 1414SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1415 SDValue N2, ISD::CondCode Cond, DebugLoc dl) { 1416 // These setcc operations always fold. 1417 switch (Cond) { 1418 default: break; 1419 case ISD::SETFALSE: 1420 case ISD::SETFALSE2: return getConstant(0, VT); 1421 case ISD::SETTRUE: 1422 case ISD::SETTRUE2: return getConstant(1, VT); 1423 1424 case ISD::SETOEQ: 1425 case ISD::SETOGT: 1426 case ISD::SETOGE: 1427 case ISD::SETOLT: 1428 case ISD::SETOLE: 1429 case ISD::SETONE: 1430 case ISD::SETO: 1431 case ISD::SETUO: 1432 case ISD::SETUEQ: 1433 case ISD::SETUNE: 1434 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1435 break; 1436 } 1437 1438 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1439 const APInt &C2 = N2C->getAPIntValue(); 1440 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1441 const APInt &C1 = N1C->getAPIntValue(); 1442 1443 switch (Cond) { 1444 default: assert(0 && "Unknown integer setcc!"); 1445 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1446 case ISD::SETNE: return getConstant(C1 != C2, VT); 1447 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1448 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1449 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1450 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1451 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1452 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1453 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1454 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1455 } 1456 } 1457 } 1458 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1459 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1460 // No compile time operations on this type yet. 1461 if (N1C->getValueType(0) == MVT::ppcf128) 1462 return SDValue(); 1463 1464 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1465 switch (Cond) { 1466 default: break; 1467 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1468 return getUNDEF(VT); 1469 // fall through 1470 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1471 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1472 return getUNDEF(VT); 1473 // fall through 1474 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1475 R==APFloat::cmpLessThan, VT); 1476 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1477 return getUNDEF(VT); 1478 // fall through 1479 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1480 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1481 return getUNDEF(VT); 1482 // fall through 1483 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1484 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1485 return getUNDEF(VT); 1486 // fall through 1487 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1488 R==APFloat::cmpEqual, VT); 1489 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1490 return getUNDEF(VT); 1491 // fall through 1492 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1493 R==APFloat::cmpEqual, VT); 1494 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1495 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1496 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1497 R==APFloat::cmpEqual, VT); 1498 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1499 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1500 R==APFloat::cmpLessThan, VT); 1501 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1502 R==APFloat::cmpUnordered, VT); 1503 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1504 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1505 } 1506 } else { 1507 // Ensure that the constant occurs on the RHS. 1508 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1509 } 1510 } 1511 1512 // Could not fold it. 1513 return SDValue(); 1514} 1515 1516/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1517/// use this predicate to simplify operations downstream. 1518bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1519 unsigned BitWidth = Op.getValueSizeInBits(); 1520 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1521} 1522 1523/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1524/// this predicate to simplify operations downstream. Mask is known to be zero 1525/// for bits that V cannot have. 1526bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1527 unsigned Depth) const { 1528 APInt KnownZero, KnownOne; 1529 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1530 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1531 return (KnownZero & Mask) == Mask; 1532} 1533 1534/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1535/// known to be either zero or one and return them in the KnownZero/KnownOne 1536/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1537/// processing. 1538void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1539 APInt &KnownZero, APInt &KnownOne, 1540 unsigned Depth) const { 1541 unsigned BitWidth = Mask.getBitWidth(); 1542 assert(BitWidth == Op.getValueType().getSizeInBits() && 1543 "Mask size mismatches value type size!"); 1544 1545 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1546 if (Depth == 6 || Mask == 0) 1547 return; // Limit search depth. 1548 1549 APInt KnownZero2, KnownOne2; 1550 1551 switch (Op.getOpcode()) { 1552 case ISD::Constant: 1553 // We know all of the bits for a constant! 1554 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1555 KnownZero = ~KnownOne & Mask; 1556 return; 1557 case ISD::AND: 1558 // If either the LHS or the RHS are Zero, the result is zero. 1559 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1560 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1561 KnownZero2, KnownOne2, Depth+1); 1562 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1563 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1564 1565 // Output known-1 bits are only known if set in both the LHS & RHS. 1566 KnownOne &= KnownOne2; 1567 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1568 KnownZero |= KnownZero2; 1569 return; 1570 case ISD::OR: 1571 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1572 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1573 KnownZero2, KnownOne2, Depth+1); 1574 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1575 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1576 1577 // Output known-0 bits are only known if clear in both the LHS & RHS. 1578 KnownZero &= KnownZero2; 1579 // Output known-1 are known to be set if set in either the LHS | RHS. 1580 KnownOne |= KnownOne2; 1581 return; 1582 case ISD::XOR: { 1583 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1584 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1585 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1586 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1587 1588 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1589 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1590 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1591 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1592 KnownZero = KnownZeroOut; 1593 return; 1594 } 1595 case ISD::MUL: { 1596 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1597 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1598 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1599 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1600 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1601 1602 // If low bits are zero in either operand, output low known-0 bits. 1603 // Also compute a conserative estimate for high known-0 bits. 1604 // More trickiness is possible, but this is sufficient for the 1605 // interesting case of alignment computation. 1606 KnownOne.clear(); 1607 unsigned TrailZ = KnownZero.countTrailingOnes() + 1608 KnownZero2.countTrailingOnes(); 1609 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1610 KnownZero2.countLeadingOnes(), 1611 BitWidth) - BitWidth; 1612 1613 TrailZ = std::min(TrailZ, BitWidth); 1614 LeadZ = std::min(LeadZ, BitWidth); 1615 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1616 APInt::getHighBitsSet(BitWidth, LeadZ); 1617 KnownZero &= Mask; 1618 return; 1619 } 1620 case ISD::UDIV: { 1621 // For the purposes of computing leading zeros we can conservatively 1622 // treat a udiv as a logical right shift by the power of 2 known to 1623 // be less than the denominator. 1624 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1625 ComputeMaskedBits(Op.getOperand(0), 1626 AllOnes, KnownZero2, KnownOne2, Depth+1); 1627 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1628 1629 KnownOne2.clear(); 1630 KnownZero2.clear(); 1631 ComputeMaskedBits(Op.getOperand(1), 1632 AllOnes, KnownZero2, KnownOne2, Depth+1); 1633 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1634 if (RHSUnknownLeadingOnes != BitWidth) 1635 LeadZ = std::min(BitWidth, 1636 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1637 1638 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1639 return; 1640 } 1641 case ISD::SELECT: 1642 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1643 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1644 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1645 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1646 1647 // Only known if known in both the LHS and RHS. 1648 KnownOne &= KnownOne2; 1649 KnownZero &= KnownZero2; 1650 return; 1651 case ISD::SELECT_CC: 1652 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1653 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1654 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1655 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1656 1657 // Only known if known in both the LHS and RHS. 1658 KnownOne &= KnownOne2; 1659 KnownZero &= KnownZero2; 1660 return; 1661 case ISD::SADDO: 1662 case ISD::UADDO: 1663 case ISD::SSUBO: 1664 case ISD::USUBO: 1665 case ISD::SMULO: 1666 case ISD::UMULO: 1667 if (Op.getResNo() != 1) 1668 return; 1669 // The boolean result conforms to getBooleanContents. Fall through. 1670 case ISD::SETCC: 1671 // If we know the result of a setcc has the top bits zero, use this info. 1672 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1673 BitWidth > 1) 1674 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1675 return; 1676 case ISD::SHL: 1677 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1678 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1679 unsigned ShAmt = SA->getZExtValue(); 1680 1681 // If the shift count is an invalid immediate, don't do anything. 1682 if (ShAmt >= BitWidth) 1683 return; 1684 1685 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1686 KnownZero, KnownOne, Depth+1); 1687 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1688 KnownZero <<= ShAmt; 1689 KnownOne <<= ShAmt; 1690 // low bits known zero. 1691 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1692 } 1693 return; 1694 case ISD::SRL: 1695 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1696 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1697 unsigned ShAmt = SA->getZExtValue(); 1698 1699 // If the shift count is an invalid immediate, don't do anything. 1700 if (ShAmt >= BitWidth) 1701 return; 1702 1703 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1704 KnownZero, KnownOne, Depth+1); 1705 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1706 KnownZero = KnownZero.lshr(ShAmt); 1707 KnownOne = KnownOne.lshr(ShAmt); 1708 1709 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1710 KnownZero |= HighBits; // High bits known zero. 1711 } 1712 return; 1713 case ISD::SRA: 1714 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1715 unsigned ShAmt = SA->getZExtValue(); 1716 1717 // If the shift count is an invalid immediate, don't do anything. 1718 if (ShAmt >= BitWidth) 1719 return; 1720 1721 APInt InDemandedMask = (Mask << ShAmt); 1722 // If any of the demanded bits are produced by the sign extension, we also 1723 // demand the input sign bit. 1724 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1725 if (HighBits.getBoolValue()) 1726 InDemandedMask |= APInt::getSignBit(BitWidth); 1727 1728 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1729 Depth+1); 1730 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1731 KnownZero = KnownZero.lshr(ShAmt); 1732 KnownOne = KnownOne.lshr(ShAmt); 1733 1734 // Handle the sign bits. 1735 APInt SignBit = APInt::getSignBit(BitWidth); 1736 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1737 1738 if (KnownZero.intersects(SignBit)) { 1739 KnownZero |= HighBits; // New bits are known zero. 1740 } else if (KnownOne.intersects(SignBit)) { 1741 KnownOne |= HighBits; // New bits are known one. 1742 } 1743 } 1744 return; 1745 case ISD::SIGN_EXTEND_INREG: { 1746 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1747 unsigned EBits = EVT.getSizeInBits(); 1748 1749 // Sign extension. Compute the demanded bits in the result that are not 1750 // present in the input. 1751 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1752 1753 APInt InSignBit = APInt::getSignBit(EBits); 1754 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1755 1756 // If the sign extended bits are demanded, we know that the sign 1757 // bit is demanded. 1758 InSignBit.zext(BitWidth); 1759 if (NewBits.getBoolValue()) 1760 InputDemandedBits |= InSignBit; 1761 1762 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1763 KnownZero, KnownOne, Depth+1); 1764 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1765 1766 // If the sign bit of the input is known set or clear, then we know the 1767 // top bits of the result. 1768 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1769 KnownZero |= NewBits; 1770 KnownOne &= ~NewBits; 1771 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1772 KnownOne |= NewBits; 1773 KnownZero &= ~NewBits; 1774 } else { // Input sign bit unknown 1775 KnownZero &= ~NewBits; 1776 KnownOne &= ~NewBits; 1777 } 1778 return; 1779 } 1780 case ISD::CTTZ: 1781 case ISD::CTLZ: 1782 case ISD::CTPOP: { 1783 unsigned LowBits = Log2_32(BitWidth)+1; 1784 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1785 KnownOne.clear(); 1786 return; 1787 } 1788 case ISD::LOAD: { 1789 if (ISD::isZEXTLoad(Op.getNode())) { 1790 LoadSDNode *LD = cast<LoadSDNode>(Op); 1791 MVT VT = LD->getMemoryVT(); 1792 unsigned MemBits = VT.getSizeInBits(); 1793 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1794 } 1795 return; 1796 } 1797 case ISD::ZERO_EXTEND: { 1798 MVT InVT = Op.getOperand(0).getValueType(); 1799 unsigned InBits = InVT.getSizeInBits(); 1800 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1801 APInt InMask = Mask; 1802 InMask.trunc(InBits); 1803 KnownZero.trunc(InBits); 1804 KnownOne.trunc(InBits); 1805 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1806 KnownZero.zext(BitWidth); 1807 KnownOne.zext(BitWidth); 1808 KnownZero |= NewBits; 1809 return; 1810 } 1811 case ISD::SIGN_EXTEND: { 1812 MVT InVT = Op.getOperand(0).getValueType(); 1813 unsigned InBits = InVT.getSizeInBits(); 1814 APInt InSignBit = APInt::getSignBit(InBits); 1815 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1816 APInt InMask = Mask; 1817 InMask.trunc(InBits); 1818 1819 // If any of the sign extended bits are demanded, we know that the sign 1820 // bit is demanded. Temporarily set this bit in the mask for our callee. 1821 if (NewBits.getBoolValue()) 1822 InMask |= InSignBit; 1823 1824 KnownZero.trunc(InBits); 1825 KnownOne.trunc(InBits); 1826 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1827 1828 // Note if the sign bit is known to be zero or one. 1829 bool SignBitKnownZero = KnownZero.isNegative(); 1830 bool SignBitKnownOne = KnownOne.isNegative(); 1831 assert(!(SignBitKnownZero && SignBitKnownOne) && 1832 "Sign bit can't be known to be both zero and one!"); 1833 1834 // If the sign bit wasn't actually demanded by our caller, we don't 1835 // want it set in the KnownZero and KnownOne result values. Reset the 1836 // mask and reapply it to the result values. 1837 InMask = Mask; 1838 InMask.trunc(InBits); 1839 KnownZero &= InMask; 1840 KnownOne &= InMask; 1841 1842 KnownZero.zext(BitWidth); 1843 KnownOne.zext(BitWidth); 1844 1845 // If the sign bit is known zero or one, the top bits match. 1846 if (SignBitKnownZero) 1847 KnownZero |= NewBits; 1848 else if (SignBitKnownOne) 1849 KnownOne |= NewBits; 1850 return; 1851 } 1852 case ISD::ANY_EXTEND: { 1853 MVT InVT = Op.getOperand(0).getValueType(); 1854 unsigned InBits = InVT.getSizeInBits(); 1855 APInt InMask = Mask; 1856 InMask.trunc(InBits); 1857 KnownZero.trunc(InBits); 1858 KnownOne.trunc(InBits); 1859 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1860 KnownZero.zext(BitWidth); 1861 KnownOne.zext(BitWidth); 1862 return; 1863 } 1864 case ISD::TRUNCATE: { 1865 MVT InVT = Op.getOperand(0).getValueType(); 1866 unsigned InBits = InVT.getSizeInBits(); 1867 APInt InMask = Mask; 1868 InMask.zext(InBits); 1869 KnownZero.zext(InBits); 1870 KnownOne.zext(InBits); 1871 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1872 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1873 KnownZero.trunc(BitWidth); 1874 KnownOne.trunc(BitWidth); 1875 break; 1876 } 1877 case ISD::AssertZext: { 1878 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1879 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1880 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1881 KnownOne, Depth+1); 1882 KnownZero |= (~InMask) & Mask; 1883 return; 1884 } 1885 case ISD::FGETSIGN: 1886 // All bits are zero except the low bit. 1887 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1888 return; 1889 1890 case ISD::SUB: { 1891 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1892 // We know that the top bits of C-X are clear if X contains less bits 1893 // than C (i.e. no wrap-around can happen). For example, 20-X is 1894 // positive if we can prove that X is >= 0 and < 16. 1895 if (CLHS->getAPIntValue().isNonNegative()) { 1896 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1897 // NLZ can't be BitWidth with no sign bit 1898 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1899 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1900 Depth+1); 1901 1902 // If all of the MaskV bits are known to be zero, then we know the 1903 // output top bits are zero, because we now know that the output is 1904 // from [0-C]. 1905 if ((KnownZero2 & MaskV) == MaskV) { 1906 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1907 // Top bits known zero. 1908 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1909 } 1910 } 1911 } 1912 } 1913 // fall through 1914 case ISD::ADD: { 1915 // Output known-0 bits are known if clear or set in both the low clear bits 1916 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1917 // low 3 bits clear. 1918 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1919 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1920 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1921 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1922 1923 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1924 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1925 KnownZeroOut = std::min(KnownZeroOut, 1926 KnownZero2.countTrailingOnes()); 1927 1928 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1929 return; 1930 } 1931 case ISD::SREM: 1932 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1933 const APInt &RA = Rem->getAPIntValue(); 1934 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1935 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1936 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1937 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1938 1939 // If the sign bit of the first operand is zero, the sign bit of 1940 // the result is zero. If the first operand has no one bits below 1941 // the second operand's single 1 bit, its sign will be zero. 1942 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1943 KnownZero2 |= ~LowBits; 1944 1945 KnownZero |= KnownZero2 & Mask; 1946 1947 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1948 } 1949 } 1950 return; 1951 case ISD::UREM: { 1952 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1953 const APInt &RA = Rem->getAPIntValue(); 1954 if (RA.isPowerOf2()) { 1955 APInt LowBits = (RA - 1); 1956 APInt Mask2 = LowBits & Mask; 1957 KnownZero |= ~LowBits & Mask; 1958 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1959 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1960 break; 1961 } 1962 } 1963 1964 // Since the result is less than or equal to either operand, any leading 1965 // zero bits in either operand must also exist in the result. 1966 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1967 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1968 Depth+1); 1969 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1970 Depth+1); 1971 1972 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1973 KnownZero2.countLeadingOnes()); 1974 KnownOne.clear(); 1975 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1976 return; 1977 } 1978 default: 1979 // Allow the target to implement this method for its nodes. 1980 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1981 case ISD::INTRINSIC_WO_CHAIN: 1982 case ISD::INTRINSIC_W_CHAIN: 1983 case ISD::INTRINSIC_VOID: 1984 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1985 } 1986 return; 1987 } 1988} 1989 1990/// ComputeNumSignBits - Return the number of times the sign bit of the 1991/// register is replicated into the other bits. We know that at least 1 bit 1992/// is always equal to the sign bit (itself), but other cases can give us 1993/// information. For example, immediately after an "SRA X, 2", we know that 1994/// the top 3 bits are all equal to each other, so we return 3. 1995unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1996 MVT VT = Op.getValueType(); 1997 assert(VT.isInteger() && "Invalid VT!"); 1998 unsigned VTBits = VT.getSizeInBits(); 1999 unsigned Tmp, Tmp2; 2000 unsigned FirstAnswer = 1; 2001 2002 if (Depth == 6) 2003 return 1; // Limit search depth. 2004 2005 switch (Op.getOpcode()) { 2006 default: break; 2007 case ISD::AssertSext: 2008 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 2009 return VTBits-Tmp+1; 2010 case ISD::AssertZext: 2011 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 2012 return VTBits-Tmp; 2013 2014 case ISD::Constant: { 2015 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 2016 // If negative, return # leading ones. 2017 if (Val.isNegative()) 2018 return Val.countLeadingOnes(); 2019 2020 // Return # leading zeros. 2021 return Val.countLeadingZeros(); 2022 } 2023 2024 case ISD::SIGN_EXTEND: 2025 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 2026 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 2027 2028 case ISD::SIGN_EXTEND_INREG: 2029 // Max of the input and what this extends. 2030 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 2031 Tmp = VTBits-Tmp+1; 2032 2033 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2034 return std::max(Tmp, Tmp2); 2035 2036 case ISD::SRA: 2037 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2038 // SRA X, C -> adds C sign bits. 2039 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2040 Tmp += C->getZExtValue(); 2041 if (Tmp > VTBits) Tmp = VTBits; 2042 } 2043 return Tmp; 2044 case ISD::SHL: 2045 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2046 // shl destroys sign bits. 2047 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2048 if (C->getZExtValue() >= VTBits || // Bad shift. 2049 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 2050 return Tmp - C->getZExtValue(); 2051 } 2052 break; 2053 case ISD::AND: 2054 case ISD::OR: 2055 case ISD::XOR: // NOT is handled here. 2056 // Logical binary ops preserve the number of sign bits at the worst. 2057 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2058 if (Tmp != 1) { 2059 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2060 FirstAnswer = std::min(Tmp, Tmp2); 2061 // We computed what we know about the sign bits as our first 2062 // answer. Now proceed to the generic code that uses 2063 // ComputeMaskedBits, and pick whichever answer is better. 2064 } 2065 break; 2066 2067 case ISD::SELECT: 2068 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2069 if (Tmp == 1) return 1; // Early out. 2070 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 2071 return std::min(Tmp, Tmp2); 2072 2073 case ISD::SADDO: 2074 case ISD::UADDO: 2075 case ISD::SSUBO: 2076 case ISD::USUBO: 2077 case ISD::SMULO: 2078 case ISD::UMULO: 2079 if (Op.getResNo() != 1) 2080 break; 2081 // The boolean result conforms to getBooleanContents. Fall through. 2082 case ISD::SETCC: 2083 // If setcc returns 0/-1, all bits are sign bits. 2084 if (TLI.getBooleanContents() == 2085 TargetLowering::ZeroOrNegativeOneBooleanContent) 2086 return VTBits; 2087 break; 2088 case ISD::ROTL: 2089 case ISD::ROTR: 2090 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2091 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 2092 2093 // Handle rotate right by N like a rotate left by 32-N. 2094 if (Op.getOpcode() == ISD::ROTR) 2095 RotAmt = (VTBits-RotAmt) & (VTBits-1); 2096 2097 // If we aren't rotating out all of the known-in sign bits, return the 2098 // number that are left. This handles rotl(sext(x), 1) for example. 2099 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2100 if (Tmp > RotAmt+1) return Tmp-RotAmt; 2101 } 2102 break; 2103 case ISD::ADD: 2104 // Add can have at most one carry bit. Thus we know that the output 2105 // is, at worst, one more bit than the inputs. 2106 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2107 if (Tmp == 1) return 1; // Early out. 2108 2109 // Special case decrementing a value (ADD X, -1): 2110 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 2111 if (CRHS->isAllOnesValue()) { 2112 APInt KnownZero, KnownOne; 2113 APInt Mask = APInt::getAllOnesValue(VTBits); 2114 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 2115 2116 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2117 // sign bits set. 2118 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2119 return VTBits; 2120 2121 // If we are subtracting one from a positive number, there is no carry 2122 // out of the result. 2123 if (KnownZero.isNegative()) 2124 return Tmp; 2125 } 2126 2127 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2128 if (Tmp2 == 1) return 1; 2129 return std::min(Tmp, Tmp2)-1; 2130 break; 2131 2132 case ISD::SUB: 2133 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2134 if (Tmp2 == 1) return 1; 2135 2136 // Handle NEG. 2137 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 2138 if (CLHS->isNullValue()) { 2139 APInt KnownZero, KnownOne; 2140 APInt Mask = APInt::getAllOnesValue(VTBits); 2141 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 2142 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2143 // sign bits set. 2144 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2145 return VTBits; 2146 2147 // If the input is known to be positive (the sign bit is known clear), 2148 // the output of the NEG has the same number of sign bits as the input. 2149 if (KnownZero.isNegative()) 2150 return Tmp2; 2151 2152 // Otherwise, we treat this like a SUB. 2153 } 2154 2155 // Sub can have at most one carry bit. Thus we know that the output 2156 // is, at worst, one more bit than the inputs. 2157 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2158 if (Tmp == 1) return 1; // Early out. 2159 return std::min(Tmp, Tmp2)-1; 2160 break; 2161 case ISD::TRUNCATE: 2162 // FIXME: it's tricky to do anything useful for this, but it is an important 2163 // case for targets like X86. 2164 break; 2165 } 2166 2167 // Handle LOADX separately here. EXTLOAD case will fallthrough. 2168 if (Op.getOpcode() == ISD::LOAD) { 2169 LoadSDNode *LD = cast<LoadSDNode>(Op); 2170 unsigned ExtType = LD->getExtensionType(); 2171 switch (ExtType) { 2172 default: break; 2173 case ISD::SEXTLOAD: // '17' bits known 2174 Tmp = LD->getMemoryVT().getSizeInBits(); 2175 return VTBits-Tmp+1; 2176 case ISD::ZEXTLOAD: // '16' bits known 2177 Tmp = LD->getMemoryVT().getSizeInBits(); 2178 return VTBits-Tmp; 2179 } 2180 } 2181 2182 // Allow the target to implement this method for its nodes. 2183 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2184 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2185 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2186 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2187 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2188 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2189 } 2190 2191 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2192 // use this information. 2193 APInt KnownZero, KnownOne; 2194 APInt Mask = APInt::getAllOnesValue(VTBits); 2195 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2196 2197 if (KnownZero.isNegative()) { // sign bit is 0 2198 Mask = KnownZero; 2199 } else if (KnownOne.isNegative()) { // sign bit is 1; 2200 Mask = KnownOne; 2201 } else { 2202 // Nothing known. 2203 return FirstAnswer; 2204 } 2205 2206 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2207 // the number of identical bits in the top of the input value. 2208 Mask = ~Mask; 2209 Mask <<= Mask.getBitWidth()-VTBits; 2210 // Return # leading zeros. We use 'min' here in case Val was zero before 2211 // shifting. We don't want to return '64' as for an i32 "0". 2212 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2213} 2214 2215 2216bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2217 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2218 if (!GA) return false; 2219 if (GA->getOffset() != 0) return false; 2220 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2221 if (!GV) return false; 2222 MachineModuleInfo *MMI = getMachineModuleInfo(); 2223 return MMI && MMI->hasDebugInfo(); 2224} 2225 2226 2227/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2228/// element of the result of the vector shuffle. 2229SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N, 2230 unsigned i) { 2231 MVT VT = N->getValueType(0); 2232 DebugLoc dl = N->getDebugLoc(); 2233 if (N->getMaskElt(i) < 0) 2234 return getUNDEF(VT.getVectorElementType()); 2235 unsigned Index = N->getMaskElt(i); 2236 unsigned NumElems = VT.getVectorNumElements(); 2237 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2238 Index %= NumElems; 2239 2240 if (V.getOpcode() == ISD::BIT_CONVERT) { 2241 V = V.getOperand(0); 2242 MVT VVT = V.getValueType(); 2243 if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems) 2244 return SDValue(); 2245 } 2246 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2247 return (Index == 0) ? V.getOperand(0) 2248 : getUNDEF(VT.getVectorElementType()); 2249 if (V.getOpcode() == ISD::BUILD_VECTOR) 2250 return V.getOperand(Index); 2251 if (const ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(V)) 2252 return getShuffleScalarElt(SVN, Index); 2253 return SDValue(); 2254} 2255 2256 2257/// getNode - Gets or creates the specified node. 2258/// 2259SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) { 2260 FoldingSetNodeID ID; 2261 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2262 void *IP = 0; 2263 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2264 return SDValue(E, 0); 2265 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2266 new (N) SDNode(Opcode, DL, getVTList(VT)); 2267 CSEMap.InsertNode(N, IP); 2268 2269 AllNodes.push_back(N); 2270#ifndef NDEBUG 2271 VerifyNode(N); 2272#endif 2273 return SDValue(N, 0); 2274} 2275 2276SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 2277 MVT VT, SDValue Operand) { 2278 // Constant fold unary operations with an integer constant operand. 2279 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2280 const APInt &Val = C->getAPIntValue(); 2281 unsigned BitWidth = VT.getSizeInBits(); 2282 switch (Opcode) { 2283 default: break; 2284 case ISD::SIGN_EXTEND: 2285 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2286 case ISD::ANY_EXTEND: 2287 case ISD::ZERO_EXTEND: 2288 case ISD::TRUNCATE: 2289 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2290 case ISD::UINT_TO_FP: 2291 case ISD::SINT_TO_FP: { 2292 const uint64_t zero[] = {0, 0}; 2293 // No compile time operations on this type. 2294 if (VT==MVT::ppcf128) 2295 break; 2296 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2297 (void)apf.convertFromAPInt(Val, 2298 Opcode==ISD::SINT_TO_FP, 2299 APFloat::rmNearestTiesToEven); 2300 return getConstantFP(apf, VT); 2301 } 2302 case ISD::BIT_CONVERT: 2303 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2304 return getConstantFP(Val.bitsToFloat(), VT); 2305 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2306 return getConstantFP(Val.bitsToDouble(), VT); 2307 break; 2308 case ISD::BSWAP: 2309 return getConstant(Val.byteSwap(), VT); 2310 case ISD::CTPOP: 2311 return getConstant(Val.countPopulation(), VT); 2312 case ISD::CTLZ: 2313 return getConstant(Val.countLeadingZeros(), VT); 2314 case ISD::CTTZ: 2315 return getConstant(Val.countTrailingZeros(), VT); 2316 } 2317 } 2318 2319 // Constant fold unary operations with a floating point constant operand. 2320 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2321 APFloat V = C->getValueAPF(); // make copy 2322 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2323 switch (Opcode) { 2324 case ISD::FNEG: 2325 V.changeSign(); 2326 return getConstantFP(V, VT); 2327 case ISD::FABS: 2328 V.clearSign(); 2329 return getConstantFP(V, VT); 2330 case ISD::FP_ROUND: 2331 case ISD::FP_EXTEND: { 2332 bool ignored; 2333 // This can return overflow, underflow, or inexact; we don't care. 2334 // FIXME need to be more flexible about rounding mode. 2335 (void)V.convert(*MVTToAPFloatSemantics(VT), 2336 APFloat::rmNearestTiesToEven, &ignored); 2337 return getConstantFP(V, VT); 2338 } 2339 case ISD::FP_TO_SINT: 2340 case ISD::FP_TO_UINT: { 2341 integerPart x[2]; 2342 bool ignored; 2343 assert(integerPartWidth >= 64); 2344 // FIXME need to be more flexible about rounding mode. 2345 APFloat::opStatus s = V.convertToInteger(x, VT.getSizeInBits(), 2346 Opcode==ISD::FP_TO_SINT, 2347 APFloat::rmTowardZero, &ignored); 2348 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2349 break; 2350 APInt api(VT.getSizeInBits(), 2, x); 2351 return getConstant(api, VT); 2352 } 2353 case ISD::BIT_CONVERT: 2354 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2355 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2356 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2357 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2358 break; 2359 } 2360 } 2361 } 2362 2363 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2364 switch (Opcode) { 2365 case ISD::TokenFactor: 2366 case ISD::MERGE_VALUES: 2367 case ISD::CONCAT_VECTORS: 2368 return Operand; // Factor, merge or concat of one node? No need. 2369 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2370 case ISD::FP_EXTEND: 2371 assert(VT.isFloatingPoint() && 2372 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2373 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2374 if (Operand.getOpcode() == ISD::UNDEF) 2375 return getUNDEF(VT); 2376 break; 2377 case ISD::SIGN_EXTEND: 2378 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2379 "Invalid SIGN_EXTEND!"); 2380 if (Operand.getValueType() == VT) return Operand; // noop extension 2381 assert(Operand.getValueType().bitsLT(VT) 2382 && "Invalid sext node, dst < src!"); 2383 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2384 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2385 break; 2386 case ISD::ZERO_EXTEND: 2387 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2388 "Invalid ZERO_EXTEND!"); 2389 if (Operand.getValueType() == VT) return Operand; // noop extension 2390 assert(Operand.getValueType().bitsLT(VT) 2391 && "Invalid zext node, dst < src!"); 2392 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2393 return getNode(ISD::ZERO_EXTEND, DL, VT, 2394 Operand.getNode()->getOperand(0)); 2395 break; 2396 case ISD::ANY_EXTEND: 2397 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2398 "Invalid ANY_EXTEND!"); 2399 if (Operand.getValueType() == VT) return Operand; // noop extension 2400 assert(Operand.getValueType().bitsLT(VT) 2401 && "Invalid anyext node, dst < src!"); 2402 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2403 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2404 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2405 break; 2406 case ISD::TRUNCATE: 2407 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2408 "Invalid TRUNCATE!"); 2409 if (Operand.getValueType() == VT) return Operand; // noop truncate 2410 assert(Operand.getValueType().bitsGT(VT) 2411 && "Invalid truncate node, src < dst!"); 2412 if (OpOpcode == ISD::TRUNCATE) 2413 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2414 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2415 OpOpcode == ISD::ANY_EXTEND) { 2416 // If the source is smaller than the dest, we still need an extend. 2417 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2418 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2419 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2420 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2421 else 2422 return Operand.getNode()->getOperand(0); 2423 } 2424 break; 2425 case ISD::BIT_CONVERT: 2426 // Basic sanity checking. 2427 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2428 && "Cannot BIT_CONVERT between types of different sizes!"); 2429 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2430 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2431 return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0)); 2432 if (OpOpcode == ISD::UNDEF) 2433 return getUNDEF(VT); 2434 break; 2435 case ISD::SCALAR_TO_VECTOR: 2436 assert(VT.isVector() && !Operand.getValueType().isVector() && 2437 (VT.getVectorElementType() == Operand.getValueType() || 2438 (VT.getVectorElementType().isInteger() && 2439 Operand.getValueType().isInteger() && 2440 VT.getVectorElementType().bitsLE(Operand.getValueType()))) && 2441 "Illegal SCALAR_TO_VECTOR node!"); 2442 if (OpOpcode == ISD::UNDEF) 2443 return getUNDEF(VT); 2444 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2445 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2446 isa<ConstantSDNode>(Operand.getOperand(1)) && 2447 Operand.getConstantOperandVal(1) == 0 && 2448 Operand.getOperand(0).getValueType() == VT) 2449 return Operand.getOperand(0); 2450 break; 2451 case ISD::FNEG: 2452 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 2453 if (UnsafeFPMath && OpOpcode == ISD::FSUB) 2454 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1), 2455 Operand.getNode()->getOperand(0)); 2456 if (OpOpcode == ISD::FNEG) // --X -> X 2457 return Operand.getNode()->getOperand(0); 2458 break; 2459 case ISD::FABS: 2460 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2461 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0)); 2462 break; 2463 } 2464 2465 SDNode *N; 2466 SDVTList VTs = getVTList(VT); 2467 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2468 FoldingSetNodeID ID; 2469 SDValue Ops[1] = { Operand }; 2470 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2471 void *IP = 0; 2472 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2473 return SDValue(E, 0); 2474 N = NodeAllocator.Allocate<UnarySDNode>(); 2475 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2476 CSEMap.InsertNode(N, IP); 2477 } else { 2478 N = NodeAllocator.Allocate<UnarySDNode>(); 2479 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2480 } 2481 2482 AllNodes.push_back(N); 2483#ifndef NDEBUG 2484 VerifyNode(N); 2485#endif 2486 return SDValue(N, 0); 2487} 2488 2489SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2490 MVT VT, 2491 ConstantSDNode *Cst1, 2492 ConstantSDNode *Cst2) { 2493 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2494 2495 switch (Opcode) { 2496 case ISD::ADD: return getConstant(C1 + C2, VT); 2497 case ISD::SUB: return getConstant(C1 - C2, VT); 2498 case ISD::MUL: return getConstant(C1 * C2, VT); 2499 case ISD::UDIV: 2500 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2501 break; 2502 case ISD::UREM: 2503 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2504 break; 2505 case ISD::SDIV: 2506 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2507 break; 2508 case ISD::SREM: 2509 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2510 break; 2511 case ISD::AND: return getConstant(C1 & C2, VT); 2512 case ISD::OR: return getConstant(C1 | C2, VT); 2513 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2514 case ISD::SHL: return getConstant(C1 << C2, VT); 2515 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2516 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2517 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2518 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2519 default: break; 2520 } 2521 2522 return SDValue(); 2523} 2524 2525SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2526 SDValue N1, SDValue N2) { 2527 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2528 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2529 switch (Opcode) { 2530 default: break; 2531 case ISD::TokenFactor: 2532 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2533 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2534 // Fold trivial token factors. 2535 if (N1.getOpcode() == ISD::EntryToken) return N2; 2536 if (N2.getOpcode() == ISD::EntryToken) return N1; 2537 if (N1 == N2) return N1; 2538 break; 2539 case ISD::CONCAT_VECTORS: 2540 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2541 // one big BUILD_VECTOR. 2542 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2543 N2.getOpcode() == ISD::BUILD_VECTOR) { 2544 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2545 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2546 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2547 } 2548 break; 2549 case ISD::AND: 2550 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2551 N1.getValueType() == VT && "Binary operator types must match!"); 2552 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2553 // worth handling here. 2554 if (N2C && N2C->isNullValue()) 2555 return N2; 2556 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2557 return N1; 2558 break; 2559 case ISD::OR: 2560 case ISD::XOR: 2561 case ISD::ADD: 2562 case ISD::SUB: 2563 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2564 N1.getValueType() == VT && "Binary operator types must match!"); 2565 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2566 // it's worth handling here. 2567 if (N2C && N2C->isNullValue()) 2568 return N1; 2569 break; 2570 case ISD::UDIV: 2571 case ISD::UREM: 2572 case ISD::MULHU: 2573 case ISD::MULHS: 2574 case ISD::MUL: 2575 case ISD::SDIV: 2576 case ISD::SREM: 2577 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2578 // fall through 2579 case ISD::FADD: 2580 case ISD::FSUB: 2581 case ISD::FMUL: 2582 case ISD::FDIV: 2583 case ISD::FREM: 2584 if (UnsafeFPMath) { 2585 if (Opcode == ISD::FADD) { 2586 // 0+x --> x 2587 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) 2588 if (CFP->getValueAPF().isZero()) 2589 return N2; 2590 // x+0 --> x 2591 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2592 if (CFP->getValueAPF().isZero()) 2593 return N1; 2594 } else if (Opcode == ISD::FSUB) { 2595 // x-0 --> x 2596 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2597 if (CFP->getValueAPF().isZero()) 2598 return N1; 2599 } 2600 } 2601 assert(N1.getValueType() == N2.getValueType() && 2602 N1.getValueType() == VT && "Binary operator types must match!"); 2603 break; 2604 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2605 assert(N1.getValueType() == VT && 2606 N1.getValueType().isFloatingPoint() && 2607 N2.getValueType().isFloatingPoint() && 2608 "Invalid FCOPYSIGN!"); 2609 break; 2610 case ISD::SHL: 2611 case ISD::SRA: 2612 case ISD::SRL: 2613 case ISD::ROTL: 2614 case ISD::ROTR: 2615 assert(VT == N1.getValueType() && 2616 "Shift operators return type must be the same as their first arg"); 2617 assert(VT.isInteger() && N2.getValueType().isInteger() && 2618 "Shifts only work on integers"); 2619 2620 // Always fold shifts of i1 values so the code generator doesn't need to 2621 // handle them. Since we know the size of the shift has to be less than the 2622 // size of the value, the shift/rotate count is guaranteed to be zero. 2623 if (VT == MVT::i1) 2624 return N1; 2625 break; 2626 case ISD::FP_ROUND_INREG: { 2627 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2628 assert(VT == N1.getValueType() && "Not an inreg round!"); 2629 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2630 "Cannot FP_ROUND_INREG integer types"); 2631 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2632 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2633 break; 2634 } 2635 case ISD::FP_ROUND: 2636 assert(VT.isFloatingPoint() && 2637 N1.getValueType().isFloatingPoint() && 2638 VT.bitsLE(N1.getValueType()) && 2639 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2640 if (N1.getValueType() == VT) return N1; // noop conversion. 2641 break; 2642 case ISD::AssertSext: 2643 case ISD::AssertZext: { 2644 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2645 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2646 assert(VT.isInteger() && EVT.isInteger() && 2647 "Cannot *_EXTEND_INREG FP types"); 2648 assert(EVT.bitsLE(VT) && "Not extending!"); 2649 if (VT == EVT) return N1; // noop assertion. 2650 break; 2651 } 2652 case ISD::SIGN_EXTEND_INREG: { 2653 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2654 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2655 assert(VT.isInteger() && EVT.isInteger() && 2656 "Cannot *_EXTEND_INREG FP types"); 2657 assert(EVT.bitsLE(VT) && "Not extending!"); 2658 if (EVT == VT) return N1; // Not actually extending 2659 2660 if (N1C) { 2661 APInt Val = N1C->getAPIntValue(); 2662 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2663 Val <<= Val.getBitWidth()-FromBits; 2664 Val = Val.ashr(Val.getBitWidth()-FromBits); 2665 return getConstant(Val, VT); 2666 } 2667 break; 2668 } 2669 case ISD::EXTRACT_VECTOR_ELT: 2670 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2671 if (N1.getOpcode() == ISD::UNDEF) 2672 return getUNDEF(VT); 2673 2674 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2675 // expanding copies of large vectors from registers. 2676 if (N2C && 2677 N1.getOpcode() == ISD::CONCAT_VECTORS && 2678 N1.getNumOperands() > 0) { 2679 unsigned Factor = 2680 N1.getOperand(0).getValueType().getVectorNumElements(); 2681 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, 2682 N1.getOperand(N2C->getZExtValue() / Factor), 2683 getConstant(N2C->getZExtValue() % Factor, 2684 N2.getValueType())); 2685 } 2686 2687 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2688 // expanding large vector constants. 2689 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) { 2690 SDValue Elt = N1.getOperand(N2C->getZExtValue()); 2691 if (Elt.getValueType() != VT) { 2692 // If the vector element type is not legal, the BUILD_VECTOR operands 2693 // are promoted and implicitly truncated. Make that explicit here. 2694 assert(VT.isInteger() && Elt.getValueType().isInteger() && 2695 VT.bitsLE(Elt.getValueType()) && 2696 "Bad type for BUILD_VECTOR operand"); 2697 Elt = getNode(ISD::TRUNCATE, DL, VT, Elt); 2698 } 2699 return Elt; 2700 } 2701 2702 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2703 // operations are lowered to scalars. 2704 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2705 // If the indices are the same, return the inserted element. 2706 if (N1.getOperand(2) == N2) 2707 return N1.getOperand(1); 2708 // If the indices are known different, extract the element from 2709 // the original vector. 2710 else if (isa<ConstantSDNode>(N1.getOperand(2)) && 2711 isa<ConstantSDNode>(N2)) 2712 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2); 2713 } 2714 break; 2715 case ISD::EXTRACT_ELEMENT: 2716 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2717 assert(!N1.getValueType().isVector() && !VT.isVector() && 2718 (N1.getValueType().isInteger() == VT.isInteger()) && 2719 "Wrong types for EXTRACT_ELEMENT!"); 2720 2721 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2722 // 64-bit integers into 32-bit parts. Instead of building the extract of 2723 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2724 if (N1.getOpcode() == ISD::BUILD_PAIR) 2725 return N1.getOperand(N2C->getZExtValue()); 2726 2727 // EXTRACT_ELEMENT of a constant int is also very common. 2728 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2729 unsigned ElementSize = VT.getSizeInBits(); 2730 unsigned Shift = ElementSize * N2C->getZExtValue(); 2731 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2732 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2733 } 2734 break; 2735 case ISD::EXTRACT_SUBVECTOR: 2736 if (N1.getValueType() == VT) // Trivial extraction. 2737 return N1; 2738 break; 2739 } 2740 2741 if (N1C) { 2742 if (N2C) { 2743 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2744 if (SV.getNode()) return SV; 2745 } else { // Cannonicalize constant to RHS if commutative 2746 if (isCommutativeBinOp(Opcode)) { 2747 std::swap(N1C, N2C); 2748 std::swap(N1, N2); 2749 } 2750 } 2751 } 2752 2753 // Constant fold FP operations. 2754 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2755 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2756 if (N1CFP) { 2757 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2758 // Cannonicalize constant to RHS if commutative 2759 std::swap(N1CFP, N2CFP); 2760 std::swap(N1, N2); 2761 } else if (N2CFP && VT != MVT::ppcf128) { 2762 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2763 APFloat::opStatus s; 2764 switch (Opcode) { 2765 case ISD::FADD: 2766 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2767 if (s != APFloat::opInvalidOp) 2768 return getConstantFP(V1, VT); 2769 break; 2770 case ISD::FSUB: 2771 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2772 if (s!=APFloat::opInvalidOp) 2773 return getConstantFP(V1, VT); 2774 break; 2775 case ISD::FMUL: 2776 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2777 if (s!=APFloat::opInvalidOp) 2778 return getConstantFP(V1, VT); 2779 break; 2780 case ISD::FDIV: 2781 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2782 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2783 return getConstantFP(V1, VT); 2784 break; 2785 case ISD::FREM : 2786 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2787 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2788 return getConstantFP(V1, VT); 2789 break; 2790 case ISD::FCOPYSIGN: 2791 V1.copySign(V2); 2792 return getConstantFP(V1, VT); 2793 default: break; 2794 } 2795 } 2796 } 2797 2798 // Canonicalize an UNDEF to the RHS, even over a constant. 2799 if (N1.getOpcode() == ISD::UNDEF) { 2800 if (isCommutativeBinOp(Opcode)) { 2801 std::swap(N1, N2); 2802 } else { 2803 switch (Opcode) { 2804 case ISD::FP_ROUND_INREG: 2805 case ISD::SIGN_EXTEND_INREG: 2806 case ISD::SUB: 2807 case ISD::FSUB: 2808 case ISD::FDIV: 2809 case ISD::FREM: 2810 case ISD::SRA: 2811 return N1; // fold op(undef, arg2) -> undef 2812 case ISD::UDIV: 2813 case ISD::SDIV: 2814 case ISD::UREM: 2815 case ISD::SREM: 2816 case ISD::SRL: 2817 case ISD::SHL: 2818 if (!VT.isVector()) 2819 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2820 // For vectors, we can't easily build an all zero vector, just return 2821 // the LHS. 2822 return N2; 2823 } 2824 } 2825 } 2826 2827 // Fold a bunch of operators when the RHS is undef. 2828 if (N2.getOpcode() == ISD::UNDEF) { 2829 switch (Opcode) { 2830 case ISD::XOR: 2831 if (N1.getOpcode() == ISD::UNDEF) 2832 // Handle undef ^ undef -> 0 special case. This is a common 2833 // idiom (misuse). 2834 return getConstant(0, VT); 2835 // fallthrough 2836 case ISD::ADD: 2837 case ISD::ADDC: 2838 case ISD::ADDE: 2839 case ISD::SUB: 2840 case ISD::UDIV: 2841 case ISD::SDIV: 2842 case ISD::UREM: 2843 case ISD::SREM: 2844 return N2; // fold op(arg1, undef) -> undef 2845 case ISD::FADD: 2846 case ISD::FSUB: 2847 case ISD::FMUL: 2848 case ISD::FDIV: 2849 case ISD::FREM: 2850 if (UnsafeFPMath) 2851 return N2; 2852 break; 2853 case ISD::MUL: 2854 case ISD::AND: 2855 case ISD::SRL: 2856 case ISD::SHL: 2857 if (!VT.isVector()) 2858 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2859 // For vectors, we can't easily build an all zero vector, just return 2860 // the LHS. 2861 return N1; 2862 case ISD::OR: 2863 if (!VT.isVector()) 2864 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 2865 // For vectors, we can't easily build an all one vector, just return 2866 // the LHS. 2867 return N1; 2868 case ISD::SRA: 2869 return N1; 2870 } 2871 } 2872 2873 // Memoize this node if possible. 2874 SDNode *N; 2875 SDVTList VTs = getVTList(VT); 2876 if (VT != MVT::Flag) { 2877 SDValue Ops[] = { N1, N2 }; 2878 FoldingSetNodeID ID; 2879 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2880 void *IP = 0; 2881 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2882 return SDValue(E, 0); 2883 N = NodeAllocator.Allocate<BinarySDNode>(); 2884 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2885 CSEMap.InsertNode(N, IP); 2886 } else { 2887 N = NodeAllocator.Allocate<BinarySDNode>(); 2888 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2889 } 2890 2891 AllNodes.push_back(N); 2892#ifndef NDEBUG 2893 VerifyNode(N); 2894#endif 2895 return SDValue(N, 0); 2896} 2897 2898SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2899 SDValue N1, SDValue N2, SDValue N3) { 2900 // Perform various simplifications. 2901 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2902 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2903 switch (Opcode) { 2904 case ISD::CONCAT_VECTORS: 2905 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2906 // one big BUILD_VECTOR. 2907 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2908 N2.getOpcode() == ISD::BUILD_VECTOR && 2909 N3.getOpcode() == ISD::BUILD_VECTOR) { 2910 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2911 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2912 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2913 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2914 } 2915 break; 2916 case ISD::SETCC: { 2917 // Use FoldSetCC to simplify SETCC's. 2918 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL); 2919 if (Simp.getNode()) return Simp; 2920 break; 2921 } 2922 case ISD::SELECT: 2923 if (N1C) { 2924 if (N1C->getZExtValue()) 2925 return N2; // select true, X, Y -> X 2926 else 2927 return N3; // select false, X, Y -> Y 2928 } 2929 2930 if (N2 == N3) return N2; // select C, X, X -> X 2931 break; 2932 case ISD::BRCOND: 2933 if (N2C) { 2934 if (N2C->getZExtValue()) // Unconditional branch 2935 return getNode(ISD::BR, DL, MVT::Other, N1, N3); 2936 else 2937 return N1; // Never-taken branch 2938 } 2939 break; 2940 case ISD::VECTOR_SHUFFLE: 2941 assert(0 && "should use getVectorShuffle constructor!"); 2942 break; 2943 case ISD::BIT_CONVERT: 2944 // Fold bit_convert nodes from a type to themselves. 2945 if (N1.getValueType() == VT) 2946 return N1; 2947 break; 2948 } 2949 2950 // Memoize node if it doesn't produce a flag. 2951 SDNode *N; 2952 SDVTList VTs = getVTList(VT); 2953 if (VT != MVT::Flag) { 2954 SDValue Ops[] = { N1, N2, N3 }; 2955 FoldingSetNodeID ID; 2956 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2957 void *IP = 0; 2958 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2959 return SDValue(E, 0); 2960 N = NodeAllocator.Allocate<TernarySDNode>(); 2961 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2962 CSEMap.InsertNode(N, IP); 2963 } else { 2964 N = NodeAllocator.Allocate<TernarySDNode>(); 2965 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2966 } 2967 AllNodes.push_back(N); 2968#ifndef NDEBUG 2969 VerifyNode(N); 2970#endif 2971 return SDValue(N, 0); 2972} 2973 2974SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2975 SDValue N1, SDValue N2, SDValue N3, 2976 SDValue N4) { 2977 SDValue Ops[] = { N1, N2, N3, N4 }; 2978 return getNode(Opcode, DL, VT, Ops, 4); 2979} 2980 2981SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2982 SDValue N1, SDValue N2, SDValue N3, 2983 SDValue N4, SDValue N5) { 2984 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2985 return getNode(Opcode, DL, VT, Ops, 5); 2986} 2987 2988/// getMemsetValue - Vectorized representation of the memset value 2989/// operand. 2990static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG, 2991 DebugLoc dl) { 2992 unsigned NumBits = VT.isVector() ? 2993 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2994 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2995 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2996 unsigned Shift = 8; 2997 for (unsigned i = NumBits; i > 8; i >>= 1) { 2998 Val = (Val << Shift) | Val; 2999 Shift <<= 1; 3000 } 3001 if (VT.isInteger()) 3002 return DAG.getConstant(Val, VT); 3003 return DAG.getConstantFP(APFloat(Val), VT); 3004 } 3005 3006 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3007 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); 3008 unsigned Shift = 8; 3009 for (unsigned i = NumBits; i > 8; i >>= 1) { 3010 Value = DAG.getNode(ISD::OR, dl, VT, 3011 DAG.getNode(ISD::SHL, dl, VT, Value, 3012 DAG.getConstant(Shift, 3013 TLI.getShiftAmountTy())), 3014 Value); 3015 Shift <<= 1; 3016 } 3017 3018 return Value; 3019} 3020 3021/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 3022/// used when a memcpy is turned into a memset when the source is a constant 3023/// string ptr. 3024static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, 3025 const TargetLowering &TLI, 3026 std::string &Str, unsigned Offset) { 3027 // Handle vector with all elements zero. 3028 if (Str.empty()) { 3029 if (VT.isInteger()) 3030 return DAG.getConstant(0, VT); 3031 unsigned NumElts = VT.getVectorNumElements(); 3032 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 3033 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3034 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 3035 } 3036 3037 assert(!VT.isVector() && "Can't handle vector type here!"); 3038 unsigned NumBits = VT.getSizeInBits(); 3039 unsigned MSB = NumBits / 8; 3040 uint64_t Val = 0; 3041 if (TLI.isLittleEndian()) 3042 Offset = Offset + MSB - 1; 3043 for (unsigned i = 0; i != MSB; ++i) { 3044 Val = (Val << 8) | (unsigned char)Str[Offset]; 3045 Offset += TLI.isLittleEndian() ? -1 : 1; 3046 } 3047 return DAG.getConstant(Val, VT); 3048} 3049 3050/// getMemBasePlusOffset - Returns base and offset node for the 3051/// 3052static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 3053 SelectionDAG &DAG) { 3054 MVT VT = Base.getValueType(); 3055 return DAG.getNode(ISD::ADD, Base.getDebugLoc(), 3056 VT, Base, DAG.getConstant(Offset, VT)); 3057} 3058 3059/// isMemSrcFromString - Returns true if memcpy source is a string constant. 3060/// 3061static bool isMemSrcFromString(SDValue Src, std::string &Str) { 3062 unsigned SrcDelta = 0; 3063 GlobalAddressSDNode *G = NULL; 3064 if (Src.getOpcode() == ISD::GlobalAddress) 3065 G = cast<GlobalAddressSDNode>(Src); 3066 else if (Src.getOpcode() == ISD::ADD && 3067 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 3068 Src.getOperand(1).getOpcode() == ISD::Constant) { 3069 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 3070 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 3071 } 3072 if (!G) 3073 return false; 3074 3075 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 3076 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 3077 return true; 3078 3079 return false; 3080} 3081 3082/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 3083/// to replace the memset / memcpy is below the threshold. It also returns the 3084/// types of the sequence of memory ops to perform memset / memcpy. 3085static 3086bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 3087 SDValue Dst, SDValue Src, 3088 unsigned Limit, uint64_t Size, unsigned &Align, 3089 std::string &Str, bool &isSrcStr, 3090 SelectionDAG &DAG, 3091 const TargetLowering &TLI) { 3092 isSrcStr = isMemSrcFromString(Src, Str); 3093 bool isSrcConst = isa<ConstantSDNode>(Src); 3094 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 3095 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG); 3096 if (VT != MVT::iAny) { 3097 unsigned NewAlign = (unsigned) 3098 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 3099 // If source is a string constant, this will require an unaligned load. 3100 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 3101 if (Dst.getOpcode() != ISD::FrameIndex) { 3102 // Can't change destination alignment. It requires a unaligned store. 3103 if (AllowUnalign) 3104 VT = MVT::iAny; 3105 } else { 3106 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 3107 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3108 if (MFI->isFixedObjectIndex(FI)) { 3109 // Can't change destination alignment. It requires a unaligned store. 3110 if (AllowUnalign) 3111 VT = MVT::iAny; 3112 } else { 3113 // Give the stack frame object a larger alignment if needed. 3114 if (MFI->getObjectAlignment(FI) < NewAlign) 3115 MFI->setObjectAlignment(FI, NewAlign); 3116 Align = NewAlign; 3117 } 3118 } 3119 } 3120 } 3121 3122 if (VT == MVT::iAny) { 3123 if (AllowUnalign) { 3124 VT = MVT::i64; 3125 } else { 3126 switch (Align & 7) { 3127 case 0: VT = MVT::i64; break; 3128 case 4: VT = MVT::i32; break; 3129 case 2: VT = MVT::i16; break; 3130 default: VT = MVT::i8; break; 3131 } 3132 } 3133 3134 MVT LVT = MVT::i64; 3135 while (!TLI.isTypeLegal(LVT)) 3136 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 3137 assert(LVT.isInteger()); 3138 3139 if (VT.bitsGT(LVT)) 3140 VT = LVT; 3141 } 3142 3143 unsigned NumMemOps = 0; 3144 while (Size != 0) { 3145 unsigned VTSize = VT.getSizeInBits() / 8; 3146 while (VTSize > Size) { 3147 // For now, only use non-vector load / store's for the left-over pieces. 3148 if (VT.isVector()) { 3149 VT = MVT::i64; 3150 while (!TLI.isTypeLegal(VT)) 3151 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3152 VTSize = VT.getSizeInBits() / 8; 3153 } else { 3154 // This can result in a type that is not legal on the target, e.g. 3155 // 1 or 2 bytes on PPC. 3156 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3157 VTSize >>= 1; 3158 } 3159 } 3160 3161 if (++NumMemOps > Limit) 3162 return false; 3163 MemOps.push_back(VT); 3164 Size -= VTSize; 3165 } 3166 3167 return true; 3168} 3169 3170static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3171 SDValue Chain, SDValue Dst, 3172 SDValue Src, uint64_t Size, 3173 unsigned Align, bool AlwaysInline, 3174 const Value *DstSV, uint64_t DstSVOff, 3175 const Value *SrcSV, uint64_t SrcSVOff){ 3176 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3177 3178 // Expand memcpy to a series of load and store ops if the size operand falls 3179 // below a certain threshold. 3180 std::vector<MVT> MemOps; 3181 uint64_t Limit = -1ULL; 3182 if (!AlwaysInline) 3183 Limit = TLI.getMaxStoresPerMemcpy(); 3184 unsigned DstAlign = Align; // Destination alignment can change. 3185 std::string Str; 3186 bool CopyFromStr; 3187 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3188 Str, CopyFromStr, DAG, TLI)) 3189 return SDValue(); 3190 3191 3192 bool isZeroStr = CopyFromStr && Str.empty(); 3193 SmallVector<SDValue, 8> OutChains; 3194 unsigned NumMemOps = MemOps.size(); 3195 uint64_t SrcOff = 0, DstOff = 0; 3196 for (unsigned i = 0; i < NumMemOps; i++) { 3197 MVT VT = MemOps[i]; 3198 unsigned VTSize = VT.getSizeInBits() / 8; 3199 SDValue Value, Store; 3200 3201 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 3202 // It's unlikely a store of a vector immediate can be done in a single 3203 // instruction. It would require a load from a constantpool first. 3204 // We also handle store a vector with all zero's. 3205 // FIXME: Handle other cases where store of vector immediate is done in 3206 // a single instruction. 3207 Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff); 3208 Store = DAG.getStore(Chain, dl, Value, 3209 getMemBasePlusOffset(Dst, DstOff, DAG), 3210 DstSV, DstSVOff + DstOff, false, DstAlign); 3211 } else { 3212 // The type might not be legal for the target. This should only happen 3213 // if the type is smaller than a legal type, as on PPC, so the right 3214 // thing to do is generate a LoadExt/StoreTrunc pair. These simplify 3215 // to Load/Store if NVT==VT. 3216 // FIXME does the case above also need this? 3217 MVT NVT = TLI.getTypeToTransformTo(VT); 3218 assert(NVT.bitsGE(VT)); 3219 Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain, 3220 getMemBasePlusOffset(Src, SrcOff, DAG), 3221 SrcSV, SrcSVOff + SrcOff, VT, false, Align); 3222 Store = DAG.getTruncStore(Chain, dl, Value, 3223 getMemBasePlusOffset(Dst, DstOff, DAG), 3224 DstSV, DstSVOff + DstOff, VT, false, DstAlign); 3225 } 3226 OutChains.push_back(Store); 3227 SrcOff += VTSize; 3228 DstOff += VTSize; 3229 } 3230 3231 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3232 &OutChains[0], OutChains.size()); 3233} 3234 3235static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3236 SDValue Chain, SDValue Dst, 3237 SDValue Src, uint64_t Size, 3238 unsigned Align, bool AlwaysInline, 3239 const Value *DstSV, uint64_t DstSVOff, 3240 const Value *SrcSV, uint64_t SrcSVOff){ 3241 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3242 3243 // Expand memmove to a series of load and store ops if the size operand falls 3244 // below a certain threshold. 3245 std::vector<MVT> MemOps; 3246 uint64_t Limit = -1ULL; 3247 if (!AlwaysInline) 3248 Limit = TLI.getMaxStoresPerMemmove(); 3249 unsigned DstAlign = Align; // Destination alignment can change. 3250 std::string Str; 3251 bool CopyFromStr; 3252 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3253 Str, CopyFromStr, DAG, TLI)) 3254 return SDValue(); 3255 3256 uint64_t SrcOff = 0, DstOff = 0; 3257 3258 SmallVector<SDValue, 8> LoadValues; 3259 SmallVector<SDValue, 8> LoadChains; 3260 SmallVector<SDValue, 8> OutChains; 3261 unsigned NumMemOps = MemOps.size(); 3262 for (unsigned i = 0; i < NumMemOps; i++) { 3263 MVT VT = MemOps[i]; 3264 unsigned VTSize = VT.getSizeInBits() / 8; 3265 SDValue Value, Store; 3266 3267 Value = DAG.getLoad(VT, dl, Chain, 3268 getMemBasePlusOffset(Src, SrcOff, DAG), 3269 SrcSV, SrcSVOff + SrcOff, false, Align); 3270 LoadValues.push_back(Value); 3271 LoadChains.push_back(Value.getValue(1)); 3272 SrcOff += VTSize; 3273 } 3274 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3275 &LoadChains[0], LoadChains.size()); 3276 OutChains.clear(); 3277 for (unsigned i = 0; i < NumMemOps; i++) { 3278 MVT VT = MemOps[i]; 3279 unsigned VTSize = VT.getSizeInBits() / 8; 3280 SDValue Value, Store; 3281 3282 Store = DAG.getStore(Chain, dl, LoadValues[i], 3283 getMemBasePlusOffset(Dst, DstOff, DAG), 3284 DstSV, DstSVOff + DstOff, false, DstAlign); 3285 OutChains.push_back(Store); 3286 DstOff += VTSize; 3287 } 3288 3289 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3290 &OutChains[0], OutChains.size()); 3291} 3292 3293static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, 3294 SDValue Chain, SDValue Dst, 3295 SDValue Src, uint64_t Size, 3296 unsigned Align, 3297 const Value *DstSV, uint64_t DstSVOff) { 3298 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3299 3300 // Expand memset to a series of load/store ops if the size operand 3301 // falls below a certain threshold. 3302 std::vector<MVT> MemOps; 3303 std::string Str; 3304 bool CopyFromStr; 3305 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3306 Size, Align, Str, CopyFromStr, DAG, TLI)) 3307 return SDValue(); 3308 3309 SmallVector<SDValue, 8> OutChains; 3310 uint64_t DstOff = 0; 3311 3312 unsigned NumMemOps = MemOps.size(); 3313 for (unsigned i = 0; i < NumMemOps; i++) { 3314 MVT VT = MemOps[i]; 3315 unsigned VTSize = VT.getSizeInBits() / 8; 3316 SDValue Value = getMemsetValue(Src, VT, DAG, dl); 3317 SDValue Store = DAG.getStore(Chain, dl, Value, 3318 getMemBasePlusOffset(Dst, DstOff, DAG), 3319 DstSV, DstSVOff + DstOff); 3320 OutChains.push_back(Store); 3321 DstOff += VTSize; 3322 } 3323 3324 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3325 &OutChains[0], OutChains.size()); 3326} 3327 3328SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, 3329 SDValue Src, SDValue Size, 3330 unsigned Align, bool AlwaysInline, 3331 const Value *DstSV, uint64_t DstSVOff, 3332 const Value *SrcSV, uint64_t SrcSVOff) { 3333 3334 // Check to see if we should lower the memcpy to loads and stores first. 3335 // For cases within the target-specified limits, this is the best choice. 3336 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3337 if (ConstantSize) { 3338 // Memcpy with size zero? Just return the original chain. 3339 if (ConstantSize->isNullValue()) 3340 return Chain; 3341 3342 SDValue Result = 3343 getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3344 ConstantSize->getZExtValue(), 3345 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3346 if (Result.getNode()) 3347 return Result; 3348 } 3349 3350 // Then check to see if we should lower the memcpy with target-specific 3351 // code. If the target chooses to do this, this is the next best. 3352 SDValue Result = 3353 TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align, 3354 AlwaysInline, 3355 DstSV, DstSVOff, SrcSV, SrcSVOff); 3356 if (Result.getNode()) 3357 return Result; 3358 3359 // If we really need inline code and the target declined to provide it, 3360 // use a (potentially long) sequence of loads and stores. 3361 if (AlwaysInline) { 3362 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3363 return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3364 ConstantSize->getZExtValue(), Align, true, 3365 DstSV, DstSVOff, SrcSV, SrcSVOff); 3366 } 3367 3368 // Emit a library call. 3369 TargetLowering::ArgListTy Args; 3370 TargetLowering::ArgListEntry Entry; 3371 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3372 Entry.Node = Dst; Args.push_back(Entry); 3373 Entry.Node = Src; Args.push_back(Entry); 3374 Entry.Node = Size; Args.push_back(Entry); 3375 // FIXME: pass in DebugLoc 3376 std::pair<SDValue,SDValue> CallResult = 3377 TLI.LowerCallTo(Chain, Type::VoidTy, 3378 false, false, false, false, 0, CallingConv::C, false, 3379 getExternalSymbol("memcpy", TLI.getPointerTy()), 3380 Args, *this, dl); 3381 return CallResult.second; 3382} 3383 3384SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, 3385 SDValue Src, SDValue Size, 3386 unsigned Align, 3387 const Value *DstSV, uint64_t DstSVOff, 3388 const Value *SrcSV, uint64_t SrcSVOff) { 3389 3390 // Check to see if we should lower the memmove to loads and stores first. 3391 // For cases within the target-specified limits, this is the best choice. 3392 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3393 if (ConstantSize) { 3394 // Memmove with size zero? Just return the original chain. 3395 if (ConstantSize->isNullValue()) 3396 return Chain; 3397 3398 SDValue Result = 3399 getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src, 3400 ConstantSize->getZExtValue(), 3401 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3402 if (Result.getNode()) 3403 return Result; 3404 } 3405 3406 // Then check to see if we should lower the memmove with target-specific 3407 // code. If the target chooses to do this, this is the next best. 3408 SDValue Result = 3409 TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align, 3410 DstSV, DstSVOff, SrcSV, SrcSVOff); 3411 if (Result.getNode()) 3412 return Result; 3413 3414 // Emit a library call. 3415 TargetLowering::ArgListTy Args; 3416 TargetLowering::ArgListEntry Entry; 3417 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3418 Entry.Node = Dst; Args.push_back(Entry); 3419 Entry.Node = Src; Args.push_back(Entry); 3420 Entry.Node = Size; Args.push_back(Entry); 3421 // FIXME: pass in DebugLoc 3422 std::pair<SDValue,SDValue> CallResult = 3423 TLI.LowerCallTo(Chain, Type::VoidTy, 3424 false, false, false, false, 0, CallingConv::C, false, 3425 getExternalSymbol("memmove", TLI.getPointerTy()), 3426 Args, *this, dl); 3427 return CallResult.second; 3428} 3429 3430SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, 3431 SDValue Src, SDValue Size, 3432 unsigned Align, 3433 const Value *DstSV, uint64_t DstSVOff) { 3434 3435 // Check to see if we should lower the memset to stores first. 3436 // For cases within the target-specified limits, this is the best choice. 3437 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3438 if (ConstantSize) { 3439 // Memset with size zero? Just return the original chain. 3440 if (ConstantSize->isNullValue()) 3441 return Chain; 3442 3443 SDValue Result = 3444 getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), 3445 Align, DstSV, DstSVOff); 3446 if (Result.getNode()) 3447 return Result; 3448 } 3449 3450 // Then check to see if we should lower the memset with target-specific 3451 // code. If the target chooses to do this, this is the next best. 3452 SDValue Result = 3453 TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align, 3454 DstSV, DstSVOff); 3455 if (Result.getNode()) 3456 return Result; 3457 3458 // Emit a library call. 3459 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3460 TargetLowering::ArgListTy Args; 3461 TargetLowering::ArgListEntry Entry; 3462 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3463 Args.push_back(Entry); 3464 // Extend or truncate the argument to be an i32 value for the call. 3465 if (Src.getValueType().bitsGT(MVT::i32)) 3466 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src); 3467 else 3468 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); 3469 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3470 Args.push_back(Entry); 3471 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3472 Args.push_back(Entry); 3473 // FIXME: pass in DebugLoc 3474 std::pair<SDValue,SDValue> CallResult = 3475 TLI.LowerCallTo(Chain, Type::VoidTy, 3476 false, false, false, false, 0, CallingConv::C, false, 3477 getExternalSymbol("memset", TLI.getPointerTy()), 3478 Args, *this, dl); 3479 return CallResult.second; 3480} 3481 3482SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3483 SDValue Chain, 3484 SDValue Ptr, SDValue Cmp, 3485 SDValue Swp, const Value* PtrVal, 3486 unsigned Alignment) { 3487 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); 3488 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3489 3490 MVT VT = Cmp.getValueType(); 3491 3492 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3493 Alignment = getMVTAlignment(MemVT); 3494 3495 SDVTList VTs = getVTList(VT, MVT::Other); 3496 FoldingSetNodeID ID; 3497 ID.AddInteger(MemVT.getRawBits()); 3498 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3499 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3500 void* IP = 0; 3501 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3502 return SDValue(E, 0); 3503 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3504 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3505 Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3506 CSEMap.InsertNode(N, IP); 3507 AllNodes.push_back(N); 3508 return SDValue(N, 0); 3509} 3510 3511SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3512 SDValue Chain, 3513 SDValue Ptr, SDValue Val, 3514 const Value* PtrVal, 3515 unsigned Alignment) { 3516 assert((Opcode == ISD::ATOMIC_LOAD_ADD || 3517 Opcode == ISD::ATOMIC_LOAD_SUB || 3518 Opcode == ISD::ATOMIC_LOAD_AND || 3519 Opcode == ISD::ATOMIC_LOAD_OR || 3520 Opcode == ISD::ATOMIC_LOAD_XOR || 3521 Opcode == ISD::ATOMIC_LOAD_NAND || 3522 Opcode == ISD::ATOMIC_LOAD_MIN || 3523 Opcode == ISD::ATOMIC_LOAD_MAX || 3524 Opcode == ISD::ATOMIC_LOAD_UMIN || 3525 Opcode == ISD::ATOMIC_LOAD_UMAX || 3526 Opcode == ISD::ATOMIC_SWAP) && 3527 "Invalid Atomic Op"); 3528 3529 MVT VT = Val.getValueType(); 3530 3531 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3532 Alignment = getMVTAlignment(MemVT); 3533 3534 SDVTList VTs = getVTList(VT, MVT::Other); 3535 FoldingSetNodeID ID; 3536 ID.AddInteger(MemVT.getRawBits()); 3537 SDValue Ops[] = {Chain, Ptr, Val}; 3538 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3539 void* IP = 0; 3540 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3541 return SDValue(E, 0); 3542 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3543 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3544 Chain, Ptr, Val, PtrVal, Alignment); 3545 CSEMap.InsertNode(N, IP); 3546 AllNodes.push_back(N); 3547 return SDValue(N, 0); 3548} 3549 3550/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3551/// Allowed to return something different (and simpler) if Simplify is true. 3552SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3553 DebugLoc dl) { 3554 if (NumOps == 1) 3555 return Ops[0]; 3556 3557 SmallVector<MVT, 4> VTs; 3558 VTs.reserve(NumOps); 3559 for (unsigned i = 0; i < NumOps; ++i) 3560 VTs.push_back(Ops[i].getValueType()); 3561 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps), 3562 Ops, NumOps); 3563} 3564 3565SDValue 3566SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, 3567 const MVT *VTs, unsigned NumVTs, 3568 const SDValue *Ops, unsigned NumOps, 3569 MVT MemVT, const Value *srcValue, int SVOff, 3570 unsigned Align, bool Vol, 3571 bool ReadMem, bool WriteMem) { 3572 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps, 3573 MemVT, srcValue, SVOff, Align, Vol, 3574 ReadMem, WriteMem); 3575} 3576 3577SDValue 3578SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, 3579 const SDValue *Ops, unsigned NumOps, 3580 MVT MemVT, const Value *srcValue, int SVOff, 3581 unsigned Align, bool Vol, 3582 bool ReadMem, bool WriteMem) { 3583 // Memoize the node unless it returns a flag. 3584 MemIntrinsicSDNode *N; 3585 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3586 FoldingSetNodeID ID; 3587 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3588 void *IP = 0; 3589 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3590 return SDValue(E, 0); 3591 3592 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3593 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3594 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3595 CSEMap.InsertNode(N, IP); 3596 } else { 3597 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3598 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3599 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3600 } 3601 AllNodes.push_back(N); 3602 return SDValue(N, 0); 3603} 3604 3605SDValue 3606SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, 3607 bool IsTailCall, bool IsInreg, SDVTList VTs, 3608 const SDValue *Operands, unsigned NumOperands, 3609 unsigned NumFixedArgs) { 3610 // Do not include isTailCall in the folding set profile. 3611 FoldingSetNodeID ID; 3612 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3613 ID.AddInteger(CallingConv); 3614 ID.AddInteger(IsVarArgs); 3615 void *IP = 0; 3616 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3617 // Instead of including isTailCall in the folding set, we just 3618 // set the flag of the existing node. 3619 if (!IsTailCall) 3620 cast<CallSDNode>(E)->setNotTailCall(); 3621 return SDValue(E, 0); 3622 } 3623 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3624 new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg, 3625 VTs, Operands, NumOperands, NumFixedArgs); 3626 CSEMap.InsertNode(N, IP); 3627 AllNodes.push_back(N); 3628 return SDValue(N, 0); 3629} 3630 3631SDValue 3632SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, 3633 ISD::LoadExtType ExtType, MVT VT, SDValue Chain, 3634 SDValue Ptr, SDValue Offset, 3635 const Value *SV, int SVOffset, MVT EVT, 3636 bool isVolatile, unsigned Alignment) { 3637 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3638 Alignment = getMVTAlignment(VT); 3639 3640 if (VT == EVT) { 3641 ExtType = ISD::NON_EXTLOAD; 3642 } else if (ExtType == ISD::NON_EXTLOAD) { 3643 assert(VT == EVT && "Non-extending load from different memory type!"); 3644 } else { 3645 // Extending load. 3646 if (VT.isVector()) 3647 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3648 "Invalid vector extload!"); 3649 else 3650 assert(EVT.bitsLT(VT) && 3651 "Should only be an extending load, not truncating!"); 3652 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3653 "Cannot sign/zero extend a FP/Vector load!"); 3654 assert(VT.isInteger() == EVT.isInteger() && 3655 "Cannot convert from FP to Int or Int -> FP!"); 3656 } 3657 3658 bool Indexed = AM != ISD::UNINDEXED; 3659 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3660 "Unindexed load with an offset!"); 3661 3662 SDVTList VTs = Indexed ? 3663 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3664 SDValue Ops[] = { Chain, Ptr, Offset }; 3665 FoldingSetNodeID ID; 3666 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3667 ID.AddInteger(EVT.getRawBits()); 3668 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); 3669 void *IP = 0; 3670 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3671 return SDValue(E, 0); 3672 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3673 new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset, 3674 Alignment, isVolatile); 3675 CSEMap.InsertNode(N, IP); 3676 AllNodes.push_back(N); 3677 return SDValue(N, 0); 3678} 3679 3680SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, 3681 SDValue Chain, SDValue Ptr, 3682 const Value *SV, int SVOffset, 3683 bool isVolatile, unsigned Alignment) { 3684 SDValue Undef = getUNDEF(Ptr.getValueType()); 3685 return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3686 SV, SVOffset, VT, isVolatile, Alignment); 3687} 3688 3689SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, 3690 SDValue Chain, SDValue Ptr, 3691 const Value *SV, 3692 int SVOffset, MVT EVT, 3693 bool isVolatile, unsigned Alignment) { 3694 SDValue Undef = getUNDEF(Ptr.getValueType()); 3695 return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef, 3696 SV, SVOffset, EVT, isVolatile, Alignment); 3697} 3698 3699SDValue 3700SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, 3701 SDValue Offset, ISD::MemIndexedMode AM) { 3702 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3703 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3704 "Load is already a indexed load!"); 3705 return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(), 3706 LD->getChain(), Base, Offset, LD->getSrcValue(), 3707 LD->getSrcValueOffset(), LD->getMemoryVT(), 3708 LD->isVolatile(), LD->getAlignment()); 3709} 3710 3711SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, 3712 SDValue Ptr, const Value *SV, int SVOffset, 3713 bool isVolatile, unsigned Alignment) { 3714 MVT VT = Val.getValueType(); 3715 3716 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3717 Alignment = getMVTAlignment(VT); 3718 3719 SDVTList VTs = getVTList(MVT::Other); 3720 SDValue Undef = getUNDEF(Ptr.getValueType()); 3721 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3722 FoldingSetNodeID ID; 3723 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3724 ID.AddInteger(VT.getRawBits()); 3725 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, 3726 isVolatile, Alignment)); 3727 void *IP = 0; 3728 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3729 return SDValue(E, 0); 3730 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3731 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false, 3732 VT, SV, SVOffset, Alignment, isVolatile); 3733 CSEMap.InsertNode(N, IP); 3734 AllNodes.push_back(N); 3735 return SDValue(N, 0); 3736} 3737 3738SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, 3739 SDValue Ptr, const Value *SV, 3740 int SVOffset, MVT SVT, 3741 bool isVolatile, unsigned Alignment) { 3742 MVT VT = Val.getValueType(); 3743 3744 if (VT == SVT) 3745 return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3746 3747 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3748 assert(VT.isInteger() == SVT.isInteger() && 3749 "Can't do FP-INT conversion!"); 3750 3751 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3752 Alignment = getMVTAlignment(VT); 3753 3754 SDVTList VTs = getVTList(MVT::Other); 3755 SDValue Undef = getUNDEF(Ptr.getValueType()); 3756 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3757 FoldingSetNodeID ID; 3758 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3759 ID.AddInteger(SVT.getRawBits()); 3760 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, 3761 isVolatile, Alignment)); 3762 void *IP = 0; 3763 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3764 return SDValue(E, 0); 3765 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3766 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true, 3767 SVT, SV, SVOffset, Alignment, isVolatile); 3768 CSEMap.InsertNode(N, IP); 3769 AllNodes.push_back(N); 3770 return SDValue(N, 0); 3771} 3772 3773SDValue 3774SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, 3775 SDValue Offset, ISD::MemIndexedMode AM) { 3776 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3777 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3778 "Store is already a indexed store!"); 3779 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3780 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3781 FoldingSetNodeID ID; 3782 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3783 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3784 ID.AddInteger(ST->getRawSubclassData()); 3785 void *IP = 0; 3786 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3787 return SDValue(E, 0); 3788 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3789 new (N) StoreSDNode(Ops, dl, VTs, AM, 3790 ST->isTruncatingStore(), ST->getMemoryVT(), 3791 ST->getSrcValue(), ST->getSrcValueOffset(), 3792 ST->getAlignment(), ST->isVolatile()); 3793 CSEMap.InsertNode(N, IP); 3794 AllNodes.push_back(N); 3795 return SDValue(N, 0); 3796} 3797 3798SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl, 3799 SDValue Chain, SDValue Ptr, 3800 SDValue SV) { 3801 SDValue Ops[] = { Chain, Ptr, SV }; 3802 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3); 3803} 3804 3805SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3806 const SDUse *Ops, unsigned NumOps) { 3807 switch (NumOps) { 3808 case 0: return getNode(Opcode, DL, VT); 3809 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3810 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3811 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3812 default: break; 3813 } 3814 3815 // Copy from an SDUse array into an SDValue array for use with 3816 // the regular getNode logic. 3817 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3818 return getNode(Opcode, DL, VT, &NewOps[0], NumOps); 3819} 3820 3821SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3822 const SDValue *Ops, unsigned NumOps) { 3823 switch (NumOps) { 3824 case 0: return getNode(Opcode, DL, VT); 3825 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3826 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3827 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3828 default: break; 3829 } 3830 3831 switch (Opcode) { 3832 default: break; 3833 case ISD::SELECT_CC: { 3834 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3835 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3836 "LHS and RHS of condition must have same type!"); 3837 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3838 "True and False arms of SelectCC must have same type!"); 3839 assert(Ops[2].getValueType() == VT && 3840 "select_cc node must be of same type as true and false value!"); 3841 break; 3842 } 3843 case ISD::BR_CC: { 3844 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3845 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3846 "LHS/RHS of comparison should match types!"); 3847 break; 3848 } 3849 } 3850 3851 // Memoize nodes. 3852 SDNode *N; 3853 SDVTList VTs = getVTList(VT); 3854 3855 if (VT != MVT::Flag) { 3856 FoldingSetNodeID ID; 3857 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3858 void *IP = 0; 3859 3860 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3861 return SDValue(E, 0); 3862 3863 N = NodeAllocator.Allocate<SDNode>(); 3864 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3865 CSEMap.InsertNode(N, IP); 3866 } else { 3867 N = NodeAllocator.Allocate<SDNode>(); 3868 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3869 } 3870 3871 AllNodes.push_back(N); 3872#ifndef NDEBUG 3873 VerifyNode(N); 3874#endif 3875 return SDValue(N, 0); 3876} 3877 3878SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3879 const std::vector<MVT> &ResultTys, 3880 const SDValue *Ops, unsigned NumOps) { 3881 return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()), 3882 Ops, NumOps); 3883} 3884 3885SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3886 const MVT *VTs, unsigned NumVTs, 3887 const SDValue *Ops, unsigned NumOps) { 3888 if (NumVTs == 1) 3889 return getNode(Opcode, DL, VTs[0], Ops, NumOps); 3890 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps); 3891} 3892 3893SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3894 const SDValue *Ops, unsigned NumOps) { 3895 if (VTList.NumVTs == 1) 3896 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps); 3897 3898 switch (Opcode) { 3899 // FIXME: figure out how to safely handle things like 3900 // int foo(int x) { return 1 << (x & 255); } 3901 // int bar() { return foo(256); } 3902#if 0 3903 case ISD::SRA_PARTS: 3904 case ISD::SRL_PARTS: 3905 case ISD::SHL_PARTS: 3906 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3907 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3908 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3909 else if (N3.getOpcode() == ISD::AND) 3910 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3911 // If the and is only masking out bits that cannot effect the shift, 3912 // eliminate the and. 3913 unsigned NumBits = VT.getSizeInBits()*2; 3914 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3915 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3916 } 3917 break; 3918#endif 3919 } 3920 3921 // Memoize the node unless it returns a flag. 3922 SDNode *N; 3923 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3924 FoldingSetNodeID ID; 3925 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3926 void *IP = 0; 3927 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3928 return SDValue(E, 0); 3929 if (NumOps == 1) { 3930 N = NodeAllocator.Allocate<UnarySDNode>(); 3931 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3932 } else if (NumOps == 2) { 3933 N = NodeAllocator.Allocate<BinarySDNode>(); 3934 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3935 } else if (NumOps == 3) { 3936 N = NodeAllocator.Allocate<TernarySDNode>(); 3937 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3938 } else { 3939 N = NodeAllocator.Allocate<SDNode>(); 3940 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3941 } 3942 CSEMap.InsertNode(N, IP); 3943 } else { 3944 if (NumOps == 1) { 3945 N = NodeAllocator.Allocate<UnarySDNode>(); 3946 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3947 } else if (NumOps == 2) { 3948 N = NodeAllocator.Allocate<BinarySDNode>(); 3949 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3950 } else if (NumOps == 3) { 3951 N = NodeAllocator.Allocate<TernarySDNode>(); 3952 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3953 } else { 3954 N = NodeAllocator.Allocate<SDNode>(); 3955 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3956 } 3957 } 3958 AllNodes.push_back(N); 3959#ifndef NDEBUG 3960 VerifyNode(N); 3961#endif 3962 return SDValue(N, 0); 3963} 3964 3965SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) { 3966 return getNode(Opcode, DL, VTList, 0, 0); 3967} 3968 3969SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3970 SDValue N1) { 3971 SDValue Ops[] = { N1 }; 3972 return getNode(Opcode, DL, VTList, Ops, 1); 3973} 3974 3975SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3976 SDValue N1, SDValue N2) { 3977 SDValue Ops[] = { N1, N2 }; 3978 return getNode(Opcode, DL, VTList, Ops, 2); 3979} 3980 3981SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3982 SDValue N1, SDValue N2, SDValue N3) { 3983 SDValue Ops[] = { N1, N2, N3 }; 3984 return getNode(Opcode, DL, VTList, Ops, 3); 3985} 3986 3987SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3988 SDValue N1, SDValue N2, SDValue N3, 3989 SDValue N4) { 3990 SDValue Ops[] = { N1, N2, N3, N4 }; 3991 return getNode(Opcode, DL, VTList, Ops, 4); 3992} 3993 3994SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3995 SDValue N1, SDValue N2, SDValue N3, 3996 SDValue N4, SDValue N5) { 3997 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3998 return getNode(Opcode, DL, VTList, Ops, 5); 3999} 4000 4001SDVTList SelectionDAG::getVTList(MVT VT) { 4002 return makeVTList(SDNode::getValueTypeList(VT), 1); 4003} 4004 4005SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 4006 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4007 E = VTList.rend(); I != E; ++I) 4008 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 4009 return *I; 4010 4011 MVT *Array = Allocator.Allocate<MVT>(2); 4012 Array[0] = VT1; 4013 Array[1] = VT2; 4014 SDVTList Result = makeVTList(Array, 2); 4015 VTList.push_back(Result); 4016 return Result; 4017} 4018 4019SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 4020 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4021 E = VTList.rend(); I != E; ++I) 4022 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 4023 I->VTs[2] == VT3) 4024 return *I; 4025 4026 MVT *Array = Allocator.Allocate<MVT>(3); 4027 Array[0] = VT1; 4028 Array[1] = VT2; 4029 Array[2] = VT3; 4030 SDVTList Result = makeVTList(Array, 3); 4031 VTList.push_back(Result); 4032 return Result; 4033} 4034 4035SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { 4036 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4037 E = VTList.rend(); I != E; ++I) 4038 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 4039 I->VTs[2] == VT3 && I->VTs[3] == VT4) 4040 return *I; 4041 4042 MVT *Array = Allocator.Allocate<MVT>(3); 4043 Array[0] = VT1; 4044 Array[1] = VT2; 4045 Array[2] = VT3; 4046 Array[3] = VT4; 4047 SDVTList Result = makeVTList(Array, 4); 4048 VTList.push_back(Result); 4049 return Result; 4050} 4051 4052SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 4053 switch (NumVTs) { 4054 case 0: assert(0 && "Cannot have nodes without results!"); 4055 case 1: return getVTList(VTs[0]); 4056 case 2: return getVTList(VTs[0], VTs[1]); 4057 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 4058 default: break; 4059 } 4060 4061 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4062 E = VTList.rend(); I != E; ++I) { 4063 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 4064 continue; 4065 4066 bool NoMatch = false; 4067 for (unsigned i = 2; i != NumVTs; ++i) 4068 if (VTs[i] != I->VTs[i]) { 4069 NoMatch = true; 4070 break; 4071 } 4072 if (!NoMatch) 4073 return *I; 4074 } 4075 4076 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 4077 std::copy(VTs, VTs+NumVTs, Array); 4078 SDVTList Result = makeVTList(Array, NumVTs); 4079 VTList.push_back(Result); 4080 return Result; 4081} 4082 4083 4084/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 4085/// specified operands. If the resultant node already exists in the DAG, 4086/// this does not modify the specified node, instead it returns the node that 4087/// already exists. If the resultant node does not exist in the DAG, the 4088/// input node is returned. As a degenerate case, if you specify the same 4089/// input operands as the node already has, the input node is returned. 4090SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 4091 SDNode *N = InN.getNode(); 4092 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 4093 4094 // Check to see if there is no change. 4095 if (Op == N->getOperand(0)) return InN; 4096 4097 // See if the modified node already exists. 4098 void *InsertPos = 0; 4099 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 4100 return SDValue(Existing, InN.getResNo()); 4101 4102 // Nope it doesn't. Remove the node from its current place in the maps. 4103 if (InsertPos) 4104 if (!RemoveNodeFromCSEMaps(N)) 4105 InsertPos = 0; 4106 4107 // Now we update the operands. 4108 N->OperandList[0].set(Op); 4109 4110 // If this gets put into a CSE map, add it. 4111 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4112 return InN; 4113} 4114 4115SDValue SelectionDAG:: 4116UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 4117 SDNode *N = InN.getNode(); 4118 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 4119 4120 // Check to see if there is no change. 4121 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 4122 return InN; // No operands changed, just return the input node. 4123 4124 // See if the modified node already exists. 4125 void *InsertPos = 0; 4126 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 4127 return SDValue(Existing, InN.getResNo()); 4128 4129 // Nope it doesn't. Remove the node from its current place in the maps. 4130 if (InsertPos) 4131 if (!RemoveNodeFromCSEMaps(N)) 4132 InsertPos = 0; 4133 4134 // Now we update the operands. 4135 if (N->OperandList[0] != Op1) 4136 N->OperandList[0].set(Op1); 4137 if (N->OperandList[1] != Op2) 4138 N->OperandList[1].set(Op2); 4139 4140 // If this gets put into a CSE map, add it. 4141 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4142 return InN; 4143} 4144 4145SDValue SelectionDAG:: 4146UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 4147 SDValue Ops[] = { Op1, Op2, Op3 }; 4148 return UpdateNodeOperands(N, Ops, 3); 4149} 4150 4151SDValue SelectionDAG:: 4152UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4153 SDValue Op3, SDValue Op4) { 4154 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 4155 return UpdateNodeOperands(N, Ops, 4); 4156} 4157 4158SDValue SelectionDAG:: 4159UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4160 SDValue Op3, SDValue Op4, SDValue Op5) { 4161 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 4162 return UpdateNodeOperands(N, Ops, 5); 4163} 4164 4165SDValue SelectionDAG:: 4166UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 4167 SDNode *N = InN.getNode(); 4168 assert(N->getNumOperands() == NumOps && 4169 "Update with wrong number of operands"); 4170 4171 // Check to see if there is no change. 4172 bool AnyChange = false; 4173 for (unsigned i = 0; i != NumOps; ++i) { 4174 if (Ops[i] != N->getOperand(i)) { 4175 AnyChange = true; 4176 break; 4177 } 4178 } 4179 4180 // No operands changed, just return the input node. 4181 if (!AnyChange) return InN; 4182 4183 // See if the modified node already exists. 4184 void *InsertPos = 0; 4185 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 4186 return SDValue(Existing, InN.getResNo()); 4187 4188 // Nope it doesn't. Remove the node from its current place in the maps. 4189 if (InsertPos) 4190 if (!RemoveNodeFromCSEMaps(N)) 4191 InsertPos = 0; 4192 4193 // Now we update the operands. 4194 for (unsigned i = 0; i != NumOps; ++i) 4195 if (N->OperandList[i] != Ops[i]) 4196 N->OperandList[i].set(Ops[i]); 4197 4198 // If this gets put into a CSE map, add it. 4199 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4200 return InN; 4201} 4202 4203/// DropOperands - Release the operands and set this node to have 4204/// zero operands. 4205void SDNode::DropOperands() { 4206 // Unlike the code in MorphNodeTo that does this, we don't need to 4207 // watch for dead nodes here. 4208 for (op_iterator I = op_begin(), E = op_end(); I != E; ) { 4209 SDUse &Use = *I++; 4210 Use.set(SDValue()); 4211 } 4212} 4213 4214/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4215/// machine opcode. 4216/// 4217SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4218 MVT VT) { 4219 SDVTList VTs = getVTList(VT); 4220 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4221} 4222 4223SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4224 MVT VT, SDValue Op1) { 4225 SDVTList VTs = getVTList(VT); 4226 SDValue Ops[] = { Op1 }; 4227 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4228} 4229 4230SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4231 MVT VT, SDValue Op1, 4232 SDValue Op2) { 4233 SDVTList VTs = getVTList(VT); 4234 SDValue Ops[] = { Op1, Op2 }; 4235 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4236} 4237 4238SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4239 MVT VT, SDValue Op1, 4240 SDValue Op2, SDValue Op3) { 4241 SDVTList VTs = getVTList(VT); 4242 SDValue Ops[] = { Op1, Op2, Op3 }; 4243 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4244} 4245 4246SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4247 MVT VT, const SDValue *Ops, 4248 unsigned NumOps) { 4249 SDVTList VTs = getVTList(VT); 4250 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4251} 4252 4253SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4254 MVT VT1, MVT VT2, const SDValue *Ops, 4255 unsigned NumOps) { 4256 SDVTList VTs = getVTList(VT1, VT2); 4257 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4258} 4259 4260SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4261 MVT VT1, MVT VT2) { 4262 SDVTList VTs = getVTList(VT1, VT2); 4263 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4264} 4265 4266SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4267 MVT VT1, MVT VT2, MVT VT3, 4268 const SDValue *Ops, unsigned NumOps) { 4269 SDVTList VTs = getVTList(VT1, VT2, VT3); 4270 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4271} 4272 4273SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4274 MVT VT1, MVT VT2, MVT VT3, MVT VT4, 4275 const SDValue *Ops, unsigned NumOps) { 4276 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4277 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4278} 4279 4280SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4281 MVT VT1, MVT VT2, 4282 SDValue Op1) { 4283 SDVTList VTs = getVTList(VT1, VT2); 4284 SDValue Ops[] = { Op1 }; 4285 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4286} 4287 4288SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4289 MVT VT1, MVT VT2, 4290 SDValue Op1, SDValue Op2) { 4291 SDVTList VTs = getVTList(VT1, VT2); 4292 SDValue Ops[] = { Op1, Op2 }; 4293 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4294} 4295 4296SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4297 MVT VT1, MVT VT2, 4298 SDValue Op1, SDValue Op2, 4299 SDValue Op3) { 4300 SDVTList VTs = getVTList(VT1, VT2); 4301 SDValue Ops[] = { Op1, Op2, Op3 }; 4302 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4303} 4304 4305SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4306 MVT VT1, MVT VT2, MVT VT3, 4307 SDValue Op1, SDValue Op2, 4308 SDValue Op3) { 4309 SDVTList VTs = getVTList(VT1, VT2, VT3); 4310 SDValue Ops[] = { Op1, Op2, Op3 }; 4311 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4312} 4313 4314SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4315 SDVTList VTs, const SDValue *Ops, 4316 unsigned NumOps) { 4317 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4318} 4319 4320SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4321 MVT VT) { 4322 SDVTList VTs = getVTList(VT); 4323 return MorphNodeTo(N, Opc, VTs, 0, 0); 4324} 4325 4326SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4327 MVT VT, SDValue Op1) { 4328 SDVTList VTs = getVTList(VT); 4329 SDValue Ops[] = { Op1 }; 4330 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4331} 4332 4333SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4334 MVT VT, SDValue Op1, 4335 SDValue Op2) { 4336 SDVTList VTs = getVTList(VT); 4337 SDValue Ops[] = { Op1, Op2 }; 4338 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4339} 4340 4341SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4342 MVT VT, SDValue Op1, 4343 SDValue Op2, SDValue Op3) { 4344 SDVTList VTs = getVTList(VT); 4345 SDValue Ops[] = { Op1, Op2, Op3 }; 4346 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4347} 4348 4349SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4350 MVT VT, const SDValue *Ops, 4351 unsigned NumOps) { 4352 SDVTList VTs = getVTList(VT); 4353 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4354} 4355 4356SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4357 MVT VT1, MVT VT2, const SDValue *Ops, 4358 unsigned NumOps) { 4359 SDVTList VTs = getVTList(VT1, VT2); 4360 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4361} 4362 4363SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4364 MVT VT1, MVT VT2) { 4365 SDVTList VTs = getVTList(VT1, VT2); 4366 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4367} 4368 4369SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4370 MVT VT1, MVT VT2, MVT VT3, 4371 const SDValue *Ops, unsigned NumOps) { 4372 SDVTList VTs = getVTList(VT1, VT2, VT3); 4373 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4374} 4375 4376SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4377 MVT VT1, MVT VT2, 4378 SDValue Op1) { 4379 SDVTList VTs = getVTList(VT1, VT2); 4380 SDValue Ops[] = { Op1 }; 4381 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4382} 4383 4384SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4385 MVT VT1, MVT VT2, 4386 SDValue Op1, SDValue Op2) { 4387 SDVTList VTs = getVTList(VT1, VT2); 4388 SDValue Ops[] = { Op1, Op2 }; 4389 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4390} 4391 4392SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4393 MVT VT1, MVT VT2, 4394 SDValue Op1, SDValue Op2, 4395 SDValue Op3) { 4396 SDVTList VTs = getVTList(VT1, VT2); 4397 SDValue Ops[] = { Op1, Op2, Op3 }; 4398 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4399} 4400 4401/// MorphNodeTo - These *mutate* the specified node to have the specified 4402/// return type, opcode, and operands. 4403/// 4404/// Note that MorphNodeTo returns the resultant node. If there is already a 4405/// node of the specified opcode and operands, it returns that node instead of 4406/// the current one. Note that the DebugLoc need not be the same. 4407/// 4408/// Using MorphNodeTo is faster than creating a new node and swapping it in 4409/// with ReplaceAllUsesWith both because it often avoids allocating a new 4410/// node, and because it doesn't require CSE recalculation for any of 4411/// the node's users. 4412/// 4413SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4414 SDVTList VTs, const SDValue *Ops, 4415 unsigned NumOps) { 4416 // If an identical node already exists, use it. 4417 void *IP = 0; 4418 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4419 FoldingSetNodeID ID; 4420 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4421 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4422 return ON; 4423 } 4424 4425 if (!RemoveNodeFromCSEMaps(N)) 4426 IP = 0; 4427 4428 // Start the morphing. 4429 N->NodeType = Opc; 4430 N->ValueList = VTs.VTs; 4431 N->NumValues = VTs.NumVTs; 4432 4433 // Clear the operands list, updating used nodes to remove this from their 4434 // use list. Keep track of any operands that become dead as a result. 4435 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4436 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 4437 SDUse &Use = *I++; 4438 SDNode *Used = Use.getNode(); 4439 Use.set(SDValue()); 4440 if (Used->use_empty()) 4441 DeadNodeSet.insert(Used); 4442 } 4443 4444 // If NumOps is larger than the # of operands we currently have, reallocate 4445 // the operand list. 4446 if (NumOps > N->NumOperands) { 4447 if (N->OperandsNeedDelete) 4448 delete[] N->OperandList; 4449 4450 if (N->isMachineOpcode()) { 4451 // We're creating a final node that will live unmorphed for the 4452 // remainder of the current SelectionDAG iteration, so we can allocate 4453 // the operands directly out of a pool with no recycling metadata. 4454 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4455 N->OperandsNeedDelete = false; 4456 } else { 4457 N->OperandList = new SDUse[NumOps]; 4458 N->OperandsNeedDelete = true; 4459 } 4460 } 4461 4462 // Assign the new operands. 4463 N->NumOperands = NumOps; 4464 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4465 N->OperandList[i].setUser(N); 4466 N->OperandList[i].setInitial(Ops[i]); 4467 } 4468 4469 // Delete any nodes that are still dead after adding the uses for the 4470 // new operands. 4471 SmallVector<SDNode *, 16> DeadNodes; 4472 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4473 E = DeadNodeSet.end(); I != E; ++I) 4474 if ((*I)->use_empty()) 4475 DeadNodes.push_back(*I); 4476 RemoveDeadNodes(DeadNodes); 4477 4478 if (IP) 4479 CSEMap.InsertNode(N, IP); // Memoize the new node. 4480 return N; 4481} 4482 4483 4484/// getTargetNode - These are used for target selectors to create a new node 4485/// with specified return type(s), target opcode, and operands. 4486/// 4487/// Note that getTargetNode returns the resultant node. If there is already a 4488/// node of the specified opcode and operands, it returns that node instead of 4489/// the current one. 4490SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) { 4491 return getNode(~Opcode, dl, VT).getNode(); 4492} 4493 4494SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4495 SDValue Op1) { 4496 return getNode(~Opcode, dl, VT, Op1).getNode(); 4497} 4498 4499SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4500 SDValue Op1, SDValue Op2) { 4501 return getNode(~Opcode, dl, VT, Op1, Op2).getNode(); 4502} 4503 4504SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4505 SDValue Op1, SDValue Op2, 4506 SDValue Op3) { 4507 return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode(); 4508} 4509 4510SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4511 const SDValue *Ops, unsigned NumOps) { 4512 return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); 4513} 4514 4515SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4516 MVT VT1, MVT VT2) { 4517 SDVTList VTs = getVTList(VT1, VT2); 4518 SDValue Op; 4519 return getNode(~Opcode, dl, VTs, &Op, 0).getNode(); 4520} 4521 4522SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4523 MVT VT2, SDValue Op1) { 4524 SDVTList VTs = getVTList(VT1, VT2); 4525 return getNode(~Opcode, dl, VTs, &Op1, 1).getNode(); 4526} 4527 4528SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4529 MVT VT2, SDValue Op1, 4530 SDValue Op2) { 4531 SDVTList VTs = getVTList(VT1, VT2); 4532 SDValue Ops[] = { Op1, Op2 }; 4533 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4534} 4535 4536SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4537 MVT VT2, SDValue Op1, 4538 SDValue Op2, SDValue Op3) { 4539 SDVTList VTs = getVTList(VT1, VT2); 4540 SDValue Ops[] = { Op1, Op2, Op3 }; 4541 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4542} 4543 4544SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4545 MVT VT1, MVT VT2, 4546 const SDValue *Ops, unsigned NumOps) { 4547 SDVTList VTs = getVTList(VT1, VT2); 4548 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4549} 4550 4551SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4552 MVT VT1, MVT VT2, MVT VT3, 4553 SDValue Op1, SDValue Op2) { 4554 SDVTList VTs = getVTList(VT1, VT2, VT3); 4555 SDValue Ops[] = { Op1, Op2 }; 4556 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4557} 4558 4559SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4560 MVT VT1, MVT VT2, MVT VT3, 4561 SDValue Op1, SDValue Op2, 4562 SDValue Op3) { 4563 SDVTList VTs = getVTList(VT1, VT2, VT3); 4564 SDValue Ops[] = { Op1, Op2, Op3 }; 4565 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4566} 4567 4568SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4569 MVT VT1, MVT VT2, MVT VT3, 4570 const SDValue *Ops, unsigned NumOps) { 4571 SDVTList VTs = getVTList(VT1, VT2, VT3); 4572 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4573} 4574 4575SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4576 MVT VT2, MVT VT3, MVT VT4, 4577 const SDValue *Ops, unsigned NumOps) { 4578 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4579 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4580} 4581 4582SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4583 const std::vector<MVT> &ResultTys, 4584 const SDValue *Ops, unsigned NumOps) { 4585 return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode(); 4586} 4587 4588/// getNodeIfExists - Get the specified node if it's already available, or 4589/// else return NULL. 4590SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4591 const SDValue *Ops, unsigned NumOps) { 4592 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4593 FoldingSetNodeID ID; 4594 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4595 void *IP = 0; 4596 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4597 return E; 4598 } 4599 return NULL; 4600} 4601 4602/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4603/// This can cause recursive merging of nodes in the DAG. 4604/// 4605/// This version assumes From has a single result value. 4606/// 4607void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4608 DAGUpdateListener *UpdateListener) { 4609 SDNode *From = FromN.getNode(); 4610 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4611 "Cannot replace with this method!"); 4612 assert(From != To.getNode() && "Cannot replace uses of with self"); 4613 4614 // Iterate over all the existing uses of From. New uses will be added 4615 // to the beginning of the use list, which we avoid visiting. 4616 // This specifically avoids visiting uses of From that arise while the 4617 // replacement is happening, because any such uses would be the result 4618 // of CSE: If an existing node looks like From after one of its operands 4619 // is replaced by To, we don't want to replace of all its users with To 4620 // too. See PR3018 for more info. 4621 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4622 while (UI != UE) { 4623 SDNode *User = *UI; 4624 4625 // This node is about to morph, remove its old self from the CSE maps. 4626 RemoveNodeFromCSEMaps(User); 4627 4628 // A user can appear in a use list multiple times, and when this 4629 // happens the uses are usually next to each other in the list. 4630 // To help reduce the number of CSE recomputations, process all 4631 // the uses of this user that we can find this way. 4632 do { 4633 SDUse &Use = UI.getUse(); 4634 ++UI; 4635 Use.set(To); 4636 } while (UI != UE && *UI == User); 4637 4638 // Now that we have modified User, add it back to the CSE maps. If it 4639 // already exists there, recursively merge the results together. 4640 AddModifiedNodeToCSEMaps(User, UpdateListener); 4641 } 4642} 4643 4644/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4645/// This can cause recursive merging of nodes in the DAG. 4646/// 4647/// This version assumes that for each value of From, there is a 4648/// corresponding value in To in the same position with the same type. 4649/// 4650void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4651 DAGUpdateListener *UpdateListener) { 4652#ifndef NDEBUG 4653 for (unsigned i = 0, e = From->getNumValues(); i != e; ++i) 4654 assert((!From->hasAnyUseOfValue(i) || 4655 From->getValueType(i) == To->getValueType(i)) && 4656 "Cannot use this version of ReplaceAllUsesWith!"); 4657#endif 4658 4659 // Handle the trivial case. 4660 if (From == To) 4661 return; 4662 4663 // Iterate over just the existing users of From. See the comments in 4664 // the ReplaceAllUsesWith above. 4665 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4666 while (UI != UE) { 4667 SDNode *User = *UI; 4668 4669 // This node is about to morph, remove its old self from the CSE maps. 4670 RemoveNodeFromCSEMaps(User); 4671 4672 // A user can appear in a use list multiple times, and when this 4673 // happens the uses are usually next to each other in the list. 4674 // To help reduce the number of CSE recomputations, process all 4675 // the uses of this user that we can find this way. 4676 do { 4677 SDUse &Use = UI.getUse(); 4678 ++UI; 4679 Use.setNode(To); 4680 } while (UI != UE && *UI == User); 4681 4682 // Now that we have modified User, add it back to the CSE maps. If it 4683 // already exists there, recursively merge the results together. 4684 AddModifiedNodeToCSEMaps(User, UpdateListener); 4685 } 4686} 4687 4688/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4689/// This can cause recursive merging of nodes in the DAG. 4690/// 4691/// This version can replace From with any result values. To must match the 4692/// number and types of values returned by From. 4693void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4694 const SDValue *To, 4695 DAGUpdateListener *UpdateListener) { 4696 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4697 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4698 4699 // Iterate over just the existing users of From. See the comments in 4700 // the ReplaceAllUsesWith above. 4701 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4702 while (UI != UE) { 4703 SDNode *User = *UI; 4704 4705 // This node is about to morph, remove its old self from the CSE maps. 4706 RemoveNodeFromCSEMaps(User); 4707 4708 // A user can appear in a use list multiple times, and when this 4709 // happens the uses are usually next to each other in the list. 4710 // To help reduce the number of CSE recomputations, process all 4711 // the uses of this user that we can find this way. 4712 do { 4713 SDUse &Use = UI.getUse(); 4714 const SDValue &ToOp = To[Use.getResNo()]; 4715 ++UI; 4716 Use.set(ToOp); 4717 } while (UI != UE && *UI == User); 4718 4719 // Now that we have modified User, add it back to the CSE maps. If it 4720 // already exists there, recursively merge the results together. 4721 AddModifiedNodeToCSEMaps(User, UpdateListener); 4722 } 4723} 4724 4725/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4726/// uses of other values produced by From.getNode() alone. The Deleted 4727/// vector is handled the same way as for ReplaceAllUsesWith. 4728void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4729 DAGUpdateListener *UpdateListener){ 4730 // Handle the really simple, really trivial case efficiently. 4731 if (From == To) return; 4732 4733 // Handle the simple, trivial, case efficiently. 4734 if (From.getNode()->getNumValues() == 1) { 4735 ReplaceAllUsesWith(From, To, UpdateListener); 4736 return; 4737 } 4738 4739 // Iterate over just the existing users of From. See the comments in 4740 // the ReplaceAllUsesWith above. 4741 SDNode::use_iterator UI = From.getNode()->use_begin(), 4742 UE = From.getNode()->use_end(); 4743 while (UI != UE) { 4744 SDNode *User = *UI; 4745 bool UserRemovedFromCSEMaps = false; 4746 4747 // A user can appear in a use list multiple times, and when this 4748 // happens the uses are usually next to each other in the list. 4749 // To help reduce the number of CSE recomputations, process all 4750 // the uses of this user that we can find this way. 4751 do { 4752 SDUse &Use = UI.getUse(); 4753 4754 // Skip uses of different values from the same node. 4755 if (Use.getResNo() != From.getResNo()) { 4756 ++UI; 4757 continue; 4758 } 4759 4760 // If this node hasn't been modified yet, it's still in the CSE maps, 4761 // so remove its old self from the CSE maps. 4762 if (!UserRemovedFromCSEMaps) { 4763 RemoveNodeFromCSEMaps(User); 4764 UserRemovedFromCSEMaps = true; 4765 } 4766 4767 ++UI; 4768 Use.set(To); 4769 } while (UI != UE && *UI == User); 4770 4771 // We are iterating over all uses of the From node, so if a use 4772 // doesn't use the specific value, no changes are made. 4773 if (!UserRemovedFromCSEMaps) 4774 continue; 4775 4776 // Now that we have modified User, add it back to the CSE maps. If it 4777 // already exists there, recursively merge the results together. 4778 AddModifiedNodeToCSEMaps(User, UpdateListener); 4779 } 4780} 4781 4782namespace { 4783 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith 4784 /// to record information about a use. 4785 struct UseMemo { 4786 SDNode *User; 4787 unsigned Index; 4788 SDUse *Use; 4789 }; 4790 4791 /// operator< - Sort Memos by User. 4792 bool operator<(const UseMemo &L, const UseMemo &R) { 4793 return (intptr_t)L.User < (intptr_t)R.User; 4794 } 4795} 4796 4797/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4798/// uses of other values produced by From.getNode() alone. The same value 4799/// may appear in both the From and To list. The Deleted vector is 4800/// handled the same way as for ReplaceAllUsesWith. 4801void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4802 const SDValue *To, 4803 unsigned Num, 4804 DAGUpdateListener *UpdateListener){ 4805 // Handle the simple, trivial case efficiently. 4806 if (Num == 1) 4807 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4808 4809 // Read up all the uses and make records of them. This helps 4810 // processing new uses that are introduced during the 4811 // replacement process. 4812 SmallVector<UseMemo, 4> Uses; 4813 for (unsigned i = 0; i != Num; ++i) { 4814 unsigned FromResNo = From[i].getResNo(); 4815 SDNode *FromNode = From[i].getNode(); 4816 for (SDNode::use_iterator UI = FromNode->use_begin(), 4817 E = FromNode->use_end(); UI != E; ++UI) { 4818 SDUse &Use = UI.getUse(); 4819 if (Use.getResNo() == FromResNo) { 4820 UseMemo Memo = { *UI, i, &Use }; 4821 Uses.push_back(Memo); 4822 } 4823 } 4824 } 4825 4826 // Sort the uses, so that all the uses from a given User are together. 4827 std::sort(Uses.begin(), Uses.end()); 4828 4829 for (unsigned UseIndex = 0, UseIndexEnd = Uses.size(); 4830 UseIndex != UseIndexEnd; ) { 4831 // We know that this user uses some value of From. If it is the right 4832 // value, update it. 4833 SDNode *User = Uses[UseIndex].User; 4834 4835 // This node is about to morph, remove its old self from the CSE maps. 4836 RemoveNodeFromCSEMaps(User); 4837 4838 // The Uses array is sorted, so all the uses for a given User 4839 // are next to each other in the list. 4840 // To help reduce the number of CSE recomputations, process all 4841 // the uses of this user that we can find this way. 4842 do { 4843 unsigned i = Uses[UseIndex].Index; 4844 SDUse &Use = *Uses[UseIndex].Use; 4845 ++UseIndex; 4846 4847 Use.set(To[i]); 4848 } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User); 4849 4850 // Now that we have modified User, add it back to the CSE maps. If it 4851 // already exists there, recursively merge the results together. 4852 AddModifiedNodeToCSEMaps(User, UpdateListener); 4853 } 4854} 4855 4856/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4857/// based on their topological order. It returns the maximum id and a vector 4858/// of the SDNodes* in assigned order by reference. 4859unsigned SelectionDAG::AssignTopologicalOrder() { 4860 4861 unsigned DAGSize = 0; 4862 4863 // SortedPos tracks the progress of the algorithm. Nodes before it are 4864 // sorted, nodes after it are unsorted. When the algorithm completes 4865 // it is at the end of the list. 4866 allnodes_iterator SortedPos = allnodes_begin(); 4867 4868 // Visit all the nodes. Move nodes with no operands to the front of 4869 // the list immediately. Annotate nodes that do have operands with their 4870 // operand count. Before we do this, the Node Id fields of the nodes 4871 // may contain arbitrary values. After, the Node Id fields for nodes 4872 // before SortedPos will contain the topological sort index, and the 4873 // Node Id fields for nodes At SortedPos and after will contain the 4874 // count of outstanding operands. 4875 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4876 SDNode *N = I++; 4877 unsigned Degree = N->getNumOperands(); 4878 if (Degree == 0) { 4879 // A node with no uses, add it to the result array immediately. 4880 N->setNodeId(DAGSize++); 4881 allnodes_iterator Q = N; 4882 if (Q != SortedPos) 4883 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4884 ++SortedPos; 4885 } else { 4886 // Temporarily use the Node Id as scratch space for the degree count. 4887 N->setNodeId(Degree); 4888 } 4889 } 4890 4891 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4892 // such that by the time the end is reached all nodes will be sorted. 4893 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4894 SDNode *N = I; 4895 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4896 UI != UE; ++UI) { 4897 SDNode *P = *UI; 4898 unsigned Degree = P->getNodeId(); 4899 --Degree; 4900 if (Degree == 0) { 4901 // All of P's operands are sorted, so P may sorted now. 4902 P->setNodeId(DAGSize++); 4903 if (P != SortedPos) 4904 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4905 ++SortedPos; 4906 } else { 4907 // Update P's outstanding operand count. 4908 P->setNodeId(Degree); 4909 } 4910 } 4911 } 4912 4913 assert(SortedPos == AllNodes.end() && 4914 "Topological sort incomplete!"); 4915 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4916 "First node in topological sort is not the entry token!"); 4917 assert(AllNodes.front().getNodeId() == 0 && 4918 "First node in topological sort has non-zero id!"); 4919 assert(AllNodes.front().getNumOperands() == 0 && 4920 "First node in topological sort has operands!"); 4921 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4922 "Last node in topologic sort has unexpected id!"); 4923 assert(AllNodes.back().use_empty() && 4924 "Last node in topologic sort has users!"); 4925 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 4926 return DAGSize; 4927} 4928 4929 4930 4931//===----------------------------------------------------------------------===// 4932// SDNode Class 4933//===----------------------------------------------------------------------===// 4934 4935HandleSDNode::~HandleSDNode() { 4936 DropOperands(); 4937} 4938 4939GlobalAddressSDNode::GlobalAddressSDNode(unsigned Opc, const GlobalValue *GA, 4940 MVT VT, int64_t o, unsigned char TF) 4941 : SDNode(Opc, DebugLoc::getUnknownLoc(), getSDVTList(VT)), 4942 Offset(o), TargetFlags(TF) { 4943 TheGlobal = const_cast<GlobalValue*>(GA); 4944} 4945 4946MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt, 4947 const Value *srcValue, int SVO, 4948 unsigned alignment, bool vol) 4949 : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4950 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4951 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4952 assert(getAlignment() == alignment && "Alignment representation error!"); 4953 assert(isVolatile() == vol && "Volatile representation error!"); 4954} 4955 4956MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, 4957 const SDValue *Ops, 4958 unsigned NumOps, MVT memvt, const Value *srcValue, 4959 int SVO, unsigned alignment, bool vol) 4960 : SDNode(Opc, dl, VTs, Ops, NumOps), 4961 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4962 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4963 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4964 assert(getAlignment() == alignment && "Alignment representation error!"); 4965 assert(isVolatile() == vol && "Volatile representation error!"); 4966} 4967 4968/// getMemOperand - Return a MachineMemOperand object describing the memory 4969/// reference performed by this memory reference. 4970MachineMemOperand MemSDNode::getMemOperand() const { 4971 int Flags = 0; 4972 if (isa<LoadSDNode>(this)) 4973 Flags = MachineMemOperand::MOLoad; 4974 else if (isa<StoreSDNode>(this)) 4975 Flags = MachineMemOperand::MOStore; 4976 else if (isa<AtomicSDNode>(this)) { 4977 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4978 } 4979 else { 4980 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4981 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4982 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4983 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4984 } 4985 4986 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4987 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4988 4989 // Check if the memory reference references a frame index 4990 const FrameIndexSDNode *FI = 4991 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4992 if (!getSrcValue() && FI) 4993 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4994 Flags, 0, Size, getAlignment()); 4995 else 4996 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4997 Size, getAlignment()); 4998} 4999 5000/// Profile - Gather unique data for the node. 5001/// 5002void SDNode::Profile(FoldingSetNodeID &ID) const { 5003 AddNodeIDNode(ID, this); 5004} 5005 5006static ManagedStatic<std::set<MVT, MVT::compareRawBits> > EVTs; 5007static MVT VTs[MVT::LAST_VALUETYPE]; 5008static ManagedStatic<sys::SmartMutex<true> > VTMutex; 5009 5010/// getValueTypeList - Return a pointer to the specified value type. 5011/// 5012const MVT *SDNode::getValueTypeList(MVT VT) { 5013 sys::SmartScopedLock<true> Lock(&*VTMutex); 5014 if (VT.isExtended()) { 5015 return &(*EVTs->insert(VT).first); 5016 } else { 5017 VTs[VT.getSimpleVT()] = VT; 5018 return &VTs[VT.getSimpleVT()]; 5019 } 5020} 5021 5022/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 5023/// indicated value. This method ignores uses of other values defined by this 5024/// operation. 5025bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 5026 assert(Value < getNumValues() && "Bad value!"); 5027 5028 // TODO: Only iterate over uses of a given value of the node 5029 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 5030 if (UI.getUse().getResNo() == Value) { 5031 if (NUses == 0) 5032 return false; 5033 --NUses; 5034 } 5035 } 5036 5037 // Found exactly the right number of uses? 5038 return NUses == 0; 5039} 5040 5041 5042/// hasAnyUseOfValue - Return true if there are any use of the indicated 5043/// value. This method ignores uses of other values defined by this operation. 5044bool SDNode::hasAnyUseOfValue(unsigned Value) const { 5045 assert(Value < getNumValues() && "Bad value!"); 5046 5047 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 5048 if (UI.getUse().getResNo() == Value) 5049 return true; 5050 5051 return false; 5052} 5053 5054 5055/// isOnlyUserOf - Return true if this node is the only use of N. 5056/// 5057bool SDNode::isOnlyUserOf(SDNode *N) const { 5058 bool Seen = false; 5059 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 5060 SDNode *User = *I; 5061 if (User == this) 5062 Seen = true; 5063 else 5064 return false; 5065 } 5066 5067 return Seen; 5068} 5069 5070/// isOperand - Return true if this node is an operand of N. 5071/// 5072bool SDValue::isOperandOf(SDNode *N) const { 5073 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5074 if (*this == N->getOperand(i)) 5075 return true; 5076 return false; 5077} 5078 5079bool SDNode::isOperandOf(SDNode *N) const { 5080 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 5081 if (this == N->OperandList[i].getNode()) 5082 return true; 5083 return false; 5084} 5085 5086/// reachesChainWithoutSideEffects - Return true if this operand (which must 5087/// be a chain) reaches the specified operand without crossing any 5088/// side-effecting instructions. In practice, this looks through token 5089/// factors and non-volatile loads. In order to remain efficient, this only 5090/// looks a couple of nodes in, it does not do an exhaustive search. 5091bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 5092 unsigned Depth) const { 5093 if (*this == Dest) return true; 5094 5095 // Don't search too deeply, we just want to be able to see through 5096 // TokenFactor's etc. 5097 if (Depth == 0) return false; 5098 5099 // If this is a token factor, all inputs to the TF happen in parallel. If any 5100 // of the operands of the TF reach dest, then we can do the xform. 5101 if (getOpcode() == ISD::TokenFactor) { 5102 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 5103 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 5104 return true; 5105 return false; 5106 } 5107 5108 // Loads don't have side effects, look through them. 5109 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 5110 if (!Ld->isVolatile()) 5111 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 5112 } 5113 return false; 5114} 5115 5116 5117static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 5118 SmallPtrSet<SDNode *, 32> &Visited) { 5119 if (found || !Visited.insert(N)) 5120 return; 5121 5122 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 5123 SDNode *Op = N->getOperand(i).getNode(); 5124 if (Op == P) { 5125 found = true; 5126 return; 5127 } 5128 findPredecessor(Op, P, found, Visited); 5129 } 5130} 5131 5132/// isPredecessorOf - Return true if this node is a predecessor of N. This node 5133/// is either an operand of N or it can be reached by recursively traversing 5134/// up the operands. 5135/// NOTE: this is an expensive method. Use it carefully. 5136bool SDNode::isPredecessorOf(SDNode *N) const { 5137 SmallPtrSet<SDNode *, 32> Visited; 5138 bool found = false; 5139 findPredecessor(N, this, found, Visited); 5140 return found; 5141} 5142 5143uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 5144 assert(Num < NumOperands && "Invalid child # of SDNode!"); 5145 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 5146} 5147 5148std::string SDNode::getOperationName(const SelectionDAG *G) const { 5149 switch (getOpcode()) { 5150 default: 5151 if (getOpcode() < ISD::BUILTIN_OP_END) 5152 return "<<Unknown DAG Node>>"; 5153 if (isMachineOpcode()) { 5154 if (G) 5155 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 5156 if (getMachineOpcode() < TII->getNumOpcodes()) 5157 return TII->get(getMachineOpcode()).getName(); 5158 return "<<Unknown Machine Node>>"; 5159 } 5160 if (G) { 5161 const TargetLowering &TLI = G->getTargetLoweringInfo(); 5162 const char *Name = TLI.getTargetNodeName(getOpcode()); 5163 if (Name) return Name; 5164 return "<<Unknown Target Node>>"; 5165 } 5166 return "<<Unknown Node>>"; 5167 5168#ifndef NDEBUG 5169 case ISD::DELETED_NODE: 5170 return "<<Deleted Node!>>"; 5171#endif 5172 case ISD::PREFETCH: return "Prefetch"; 5173 case ISD::MEMBARRIER: return "MemBarrier"; 5174 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 5175 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 5176 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 5177 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 5178 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; 5179 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; 5180 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor"; 5181 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand"; 5182 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin"; 5183 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; 5184 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; 5185 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; 5186 case ISD::PCMARKER: return "PCMarker"; 5187 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5188 case ISD::SRCVALUE: return "SrcValue"; 5189 case ISD::MEMOPERAND: return "MemOperand"; 5190 case ISD::EntryToken: return "EntryToken"; 5191 case ISD::TokenFactor: return "TokenFactor"; 5192 case ISD::AssertSext: return "AssertSext"; 5193 case ISD::AssertZext: return "AssertZext"; 5194 5195 case ISD::BasicBlock: return "BasicBlock"; 5196 case ISD::ARG_FLAGS: return "ArgFlags"; 5197 case ISD::VALUETYPE: return "ValueType"; 5198 case ISD::Register: return "Register"; 5199 5200 case ISD::Constant: return "Constant"; 5201 case ISD::ConstantFP: return "ConstantFP"; 5202 case ISD::GlobalAddress: return "GlobalAddress"; 5203 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5204 case ISD::FrameIndex: return "FrameIndex"; 5205 case ISD::JumpTable: return "JumpTable"; 5206 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5207 case ISD::RETURNADDR: return "RETURNADDR"; 5208 case ISD::FRAMEADDR: return "FRAMEADDR"; 5209 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5210 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5211 case ISD::EHSELECTION: return "EHSELECTION"; 5212 case ISD::EH_RETURN: return "EH_RETURN"; 5213 case ISD::ConstantPool: return "ConstantPool"; 5214 case ISD::ExternalSymbol: return "ExternalSymbol"; 5215 case ISD::INTRINSIC_WO_CHAIN: { 5216 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5217 return Intrinsic::getName((Intrinsic::ID)IID); 5218 } 5219 case ISD::INTRINSIC_VOID: 5220 case ISD::INTRINSIC_W_CHAIN: { 5221 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5222 return Intrinsic::getName((Intrinsic::ID)IID); 5223 } 5224 5225 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5226 case ISD::TargetConstant: return "TargetConstant"; 5227 case ISD::TargetConstantFP:return "TargetConstantFP"; 5228 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5229 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5230 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5231 case ISD::TargetJumpTable: return "TargetJumpTable"; 5232 case ISD::TargetConstantPool: return "TargetConstantPool"; 5233 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5234 5235 case ISD::CopyToReg: return "CopyToReg"; 5236 case ISD::CopyFromReg: return "CopyFromReg"; 5237 case ISD::UNDEF: return "undef"; 5238 case ISD::MERGE_VALUES: return "merge_values"; 5239 case ISD::INLINEASM: return "inlineasm"; 5240 case ISD::DBG_LABEL: return "dbg_label"; 5241 case ISD::EH_LABEL: return "eh_label"; 5242 case ISD::DECLARE: return "declare"; 5243 case ISD::HANDLENODE: return "handlenode"; 5244 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5245 case ISD::CALL: return "call"; 5246 5247 // Unary operators 5248 case ISD::FABS: return "fabs"; 5249 case ISD::FNEG: return "fneg"; 5250 case ISD::FSQRT: return "fsqrt"; 5251 case ISD::FSIN: return "fsin"; 5252 case ISD::FCOS: return "fcos"; 5253 case ISD::FPOWI: return "fpowi"; 5254 case ISD::FPOW: return "fpow"; 5255 case ISD::FTRUNC: return "ftrunc"; 5256 case ISD::FFLOOR: return "ffloor"; 5257 case ISD::FCEIL: return "fceil"; 5258 case ISD::FRINT: return "frint"; 5259 case ISD::FNEARBYINT: return "fnearbyint"; 5260 5261 // Binary operators 5262 case ISD::ADD: return "add"; 5263 case ISD::SUB: return "sub"; 5264 case ISD::MUL: return "mul"; 5265 case ISD::MULHU: return "mulhu"; 5266 case ISD::MULHS: return "mulhs"; 5267 case ISD::SDIV: return "sdiv"; 5268 case ISD::UDIV: return "udiv"; 5269 case ISD::SREM: return "srem"; 5270 case ISD::UREM: return "urem"; 5271 case ISD::SMUL_LOHI: return "smul_lohi"; 5272 case ISD::UMUL_LOHI: return "umul_lohi"; 5273 case ISD::SDIVREM: return "sdivrem"; 5274 case ISD::UDIVREM: return "udivrem"; 5275 case ISD::AND: return "and"; 5276 case ISD::OR: return "or"; 5277 case ISD::XOR: return "xor"; 5278 case ISD::SHL: return "shl"; 5279 case ISD::SRA: return "sra"; 5280 case ISD::SRL: return "srl"; 5281 case ISD::ROTL: return "rotl"; 5282 case ISD::ROTR: return "rotr"; 5283 case ISD::FADD: return "fadd"; 5284 case ISD::FSUB: return "fsub"; 5285 case ISD::FMUL: return "fmul"; 5286 case ISD::FDIV: return "fdiv"; 5287 case ISD::FREM: return "frem"; 5288 case ISD::FCOPYSIGN: return "fcopysign"; 5289 case ISD::FGETSIGN: return "fgetsign"; 5290 5291 case ISD::SETCC: return "setcc"; 5292 case ISD::VSETCC: return "vsetcc"; 5293 case ISD::SELECT: return "select"; 5294 case ISD::SELECT_CC: return "select_cc"; 5295 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5296 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5297 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5298 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5299 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5300 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5301 case ISD::CARRY_FALSE: return "carry_false"; 5302 case ISD::ADDC: return "addc"; 5303 case ISD::ADDE: return "adde"; 5304 case ISD::SADDO: return "saddo"; 5305 case ISD::UADDO: return "uaddo"; 5306 case ISD::SSUBO: return "ssubo"; 5307 case ISD::USUBO: return "usubo"; 5308 case ISD::SMULO: return "smulo"; 5309 case ISD::UMULO: return "umulo"; 5310 case ISD::SUBC: return "subc"; 5311 case ISD::SUBE: return "sube"; 5312 case ISD::SHL_PARTS: return "shl_parts"; 5313 case ISD::SRA_PARTS: return "sra_parts"; 5314 case ISD::SRL_PARTS: return "srl_parts"; 5315 5316 // Conversion operators. 5317 case ISD::SIGN_EXTEND: return "sign_extend"; 5318 case ISD::ZERO_EXTEND: return "zero_extend"; 5319 case ISD::ANY_EXTEND: return "any_extend"; 5320 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5321 case ISD::TRUNCATE: return "truncate"; 5322 case ISD::FP_ROUND: return "fp_round"; 5323 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5324 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5325 case ISD::FP_EXTEND: return "fp_extend"; 5326 5327 case ISD::SINT_TO_FP: return "sint_to_fp"; 5328 case ISD::UINT_TO_FP: return "uint_to_fp"; 5329 case ISD::FP_TO_SINT: return "fp_to_sint"; 5330 case ISD::FP_TO_UINT: return "fp_to_uint"; 5331 case ISD::BIT_CONVERT: return "bit_convert"; 5332 5333 case ISD::CONVERT_RNDSAT: { 5334 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5335 default: assert(0 && "Unknown cvt code!"); 5336 case ISD::CVT_FF: return "cvt_ff"; 5337 case ISD::CVT_FS: return "cvt_fs"; 5338 case ISD::CVT_FU: return "cvt_fu"; 5339 case ISD::CVT_SF: return "cvt_sf"; 5340 case ISD::CVT_UF: return "cvt_uf"; 5341 case ISD::CVT_SS: return "cvt_ss"; 5342 case ISD::CVT_SU: return "cvt_su"; 5343 case ISD::CVT_US: return "cvt_us"; 5344 case ISD::CVT_UU: return "cvt_uu"; 5345 } 5346 } 5347 5348 // Control flow instructions 5349 case ISD::BR: return "br"; 5350 case ISD::BRIND: return "brind"; 5351 case ISD::BR_JT: return "br_jt"; 5352 case ISD::BRCOND: return "brcond"; 5353 case ISD::BR_CC: return "br_cc"; 5354 case ISD::RET: return "ret"; 5355 case ISD::CALLSEQ_START: return "callseq_start"; 5356 case ISD::CALLSEQ_END: return "callseq_end"; 5357 5358 // Other operators 5359 case ISD::LOAD: return "load"; 5360 case ISD::STORE: return "store"; 5361 case ISD::VAARG: return "vaarg"; 5362 case ISD::VACOPY: return "vacopy"; 5363 case ISD::VAEND: return "vaend"; 5364 case ISD::VASTART: return "vastart"; 5365 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5366 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5367 case ISD::BUILD_PAIR: return "build_pair"; 5368 case ISD::STACKSAVE: return "stacksave"; 5369 case ISD::STACKRESTORE: return "stackrestore"; 5370 case ISD::TRAP: return "trap"; 5371 5372 // Bit manipulation 5373 case ISD::BSWAP: return "bswap"; 5374 case ISD::CTPOP: return "ctpop"; 5375 case ISD::CTTZ: return "cttz"; 5376 case ISD::CTLZ: return "ctlz"; 5377 5378 // Debug info 5379 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5380 case ISD::DEBUG_LOC: return "debug_loc"; 5381 5382 // Trampolines 5383 case ISD::TRAMPOLINE: return "trampoline"; 5384 5385 case ISD::CONDCODE: 5386 switch (cast<CondCodeSDNode>(this)->get()) { 5387 default: assert(0 && "Unknown setcc condition!"); 5388 case ISD::SETOEQ: return "setoeq"; 5389 case ISD::SETOGT: return "setogt"; 5390 case ISD::SETOGE: return "setoge"; 5391 case ISD::SETOLT: return "setolt"; 5392 case ISD::SETOLE: return "setole"; 5393 case ISD::SETONE: return "setone"; 5394 5395 case ISD::SETO: return "seto"; 5396 case ISD::SETUO: return "setuo"; 5397 case ISD::SETUEQ: return "setue"; 5398 case ISD::SETUGT: return "setugt"; 5399 case ISD::SETUGE: return "setuge"; 5400 case ISD::SETULT: return "setult"; 5401 case ISD::SETULE: return "setule"; 5402 case ISD::SETUNE: return "setune"; 5403 5404 case ISD::SETEQ: return "seteq"; 5405 case ISD::SETGT: return "setgt"; 5406 case ISD::SETGE: return "setge"; 5407 case ISD::SETLT: return "setlt"; 5408 case ISD::SETLE: return "setle"; 5409 case ISD::SETNE: return "setne"; 5410 } 5411 } 5412} 5413 5414const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5415 switch (AM) { 5416 default: 5417 return ""; 5418 case ISD::PRE_INC: 5419 return "<pre-inc>"; 5420 case ISD::PRE_DEC: 5421 return "<pre-dec>"; 5422 case ISD::POST_INC: 5423 return "<post-inc>"; 5424 case ISD::POST_DEC: 5425 return "<post-dec>"; 5426 } 5427} 5428 5429std::string ISD::ArgFlagsTy::getArgFlagsString() { 5430 std::string S = "< "; 5431 5432 if (isZExt()) 5433 S += "zext "; 5434 if (isSExt()) 5435 S += "sext "; 5436 if (isInReg()) 5437 S += "inreg "; 5438 if (isSRet()) 5439 S += "sret "; 5440 if (isByVal()) 5441 S += "byval "; 5442 if (isNest()) 5443 S += "nest "; 5444 if (getByValAlign()) 5445 S += "byval-align:" + utostr(getByValAlign()) + " "; 5446 if (getOrigAlign()) 5447 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5448 if (getByValSize()) 5449 S += "byval-size:" + utostr(getByValSize()) + " "; 5450 return S + ">"; 5451} 5452 5453void SDNode::dump() const { dump(0); } 5454void SDNode::dump(const SelectionDAG *G) const { 5455 print(errs(), G); 5456} 5457 5458void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const { 5459 OS << (void*)this << ": "; 5460 5461 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5462 if (i) OS << ","; 5463 if (getValueType(i) == MVT::Other) 5464 OS << "ch"; 5465 else 5466 OS << getValueType(i).getMVTString(); 5467 } 5468 OS << " = " << getOperationName(G); 5469} 5470 5471void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { 5472 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5473 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(this); 5474 OS << "<"; 5475 for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) { 5476 int Idx = SVN->getMaskElt(i); 5477 if (i) OS << ","; 5478 if (Idx < 0) 5479 OS << "u"; 5480 else 5481 OS << Idx; 5482 } 5483 OS << ">"; 5484 } 5485 5486 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5487 OS << '<' << CSDN->getAPIntValue() << '>'; 5488 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5489 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5490 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5491 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5492 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5493 else { 5494 OS << "<APFloat("; 5495 CSDN->getValueAPF().bitcastToAPInt().dump(); 5496 OS << ")>"; 5497 } 5498 } else if (const GlobalAddressSDNode *GADN = 5499 dyn_cast<GlobalAddressSDNode>(this)) { 5500 int64_t offset = GADN->getOffset(); 5501 OS << '<'; 5502 WriteAsOperand(OS, GADN->getGlobal()); 5503 OS << '>'; 5504 if (offset > 0) 5505 OS << " + " << offset; 5506 else 5507 OS << " " << offset; 5508 if (unsigned char TF = GADN->getTargetFlags()) 5509 OS << " [TF=" << TF << ']'; 5510 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5511 OS << "<" << FIDN->getIndex() << ">"; 5512 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5513 OS << "<" << JTDN->getIndex() << ">"; 5514 if (unsigned char TF = JTDN->getTargetFlags()) 5515 OS << " [TF=" << TF << ']'; 5516 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5517 int offset = CP->getOffset(); 5518 if (CP->isMachineConstantPoolEntry()) 5519 OS << "<" << *CP->getMachineCPVal() << ">"; 5520 else 5521 OS << "<" << *CP->getConstVal() << ">"; 5522 if (offset > 0) 5523 OS << " + " << offset; 5524 else 5525 OS << " " << offset; 5526 if (unsigned char TF = CP->getTargetFlags()) 5527 OS << " [TF=" << TF << ']'; 5528 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5529 OS << "<"; 5530 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5531 if (LBB) 5532 OS << LBB->getName() << " "; 5533 OS << (const void*)BBDN->getBasicBlock() << ">"; 5534 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5535 if (G && R->getReg() && 5536 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5537 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5538 } else { 5539 OS << " #" << R->getReg(); 5540 } 5541 } else if (const ExternalSymbolSDNode *ES = 5542 dyn_cast<ExternalSymbolSDNode>(this)) { 5543 OS << "'" << ES->getSymbol() << "'"; 5544 if (unsigned char TF = ES->getTargetFlags()) 5545 OS << " [TF=" << TF << ']'; 5546 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5547 if (M->getValue()) 5548 OS << "<" << M->getValue() << ">"; 5549 else 5550 OS << "<null>"; 5551 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5552 if (M->MO.getValue()) 5553 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5554 else 5555 OS << "<null:" << M->MO.getOffset() << ">"; 5556 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5557 OS << N->getArgFlags().getArgFlagsString(); 5558 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5559 OS << ":" << N->getVT().getMVTString(); 5560 } 5561 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5562 const Value *SrcValue = LD->getSrcValue(); 5563 int SrcOffset = LD->getSrcValueOffset(); 5564 OS << " <"; 5565 if (SrcValue) 5566 OS << SrcValue; 5567 else 5568 OS << "null"; 5569 OS << ":" << SrcOffset << ">"; 5570 5571 bool doExt = true; 5572 switch (LD->getExtensionType()) { 5573 default: doExt = false; break; 5574 case ISD::EXTLOAD: OS << " <anyext "; break; 5575 case ISD::SEXTLOAD: OS << " <sext "; break; 5576 case ISD::ZEXTLOAD: OS << " <zext "; break; 5577 } 5578 if (doExt) 5579 OS << LD->getMemoryVT().getMVTString() << ">"; 5580 5581 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5582 if (*AM) 5583 OS << " " << AM; 5584 if (LD->isVolatile()) 5585 OS << " <volatile>"; 5586 OS << " alignment=" << LD->getAlignment(); 5587 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5588 const Value *SrcValue = ST->getSrcValue(); 5589 int SrcOffset = ST->getSrcValueOffset(); 5590 OS << " <"; 5591 if (SrcValue) 5592 OS << SrcValue; 5593 else 5594 OS << "null"; 5595 OS << ":" << SrcOffset << ">"; 5596 5597 if (ST->isTruncatingStore()) 5598 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5599 5600 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5601 if (*AM) 5602 OS << " " << AM; 5603 if (ST->isVolatile()) 5604 OS << " <volatile>"; 5605 OS << " alignment=" << ST->getAlignment(); 5606 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5607 const Value *SrcValue = AT->getSrcValue(); 5608 int SrcOffset = AT->getSrcValueOffset(); 5609 OS << " <"; 5610 if (SrcValue) 5611 OS << SrcValue; 5612 else 5613 OS << "null"; 5614 OS << ":" << SrcOffset << ">"; 5615 if (AT->isVolatile()) 5616 OS << " <volatile>"; 5617 OS << " alignment=" << AT->getAlignment(); 5618 } 5619} 5620 5621void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5622 print_types(OS, G); 5623 OS << " "; 5624 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5625 if (i) OS << ", "; 5626 OS << (void*)getOperand(i).getNode(); 5627 if (unsigned RN = getOperand(i).getResNo()) 5628 OS << ":" << RN; 5629 } 5630 print_details(OS, G); 5631} 5632 5633static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5634 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5635 if (N->getOperand(i).getNode()->hasOneUse()) 5636 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5637 else 5638 cerr << "\n" << std::string(indent+2, ' ') 5639 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5640 5641 5642 cerr << "\n" << std::string(indent, ' '); 5643 N->dump(G); 5644} 5645 5646void SelectionDAG::dump() const { 5647 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5648 5649 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5650 I != E; ++I) { 5651 const SDNode *N = I; 5652 if (!N->hasOneUse() && N != getRoot().getNode()) 5653 DumpNodes(N, 2, this); 5654 } 5655 5656 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5657 5658 cerr << "\n\n"; 5659} 5660 5661void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const { 5662 print_types(OS, G); 5663 print_details(OS, G); 5664} 5665 5666typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet; 5667static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, 5668 const SelectionDAG *G, VisitedSDNodeSet &once) { 5669 if (!once.insert(N)) // If we've been here before, return now. 5670 return; 5671 // Dump the current SDNode, but don't end the line yet. 5672 OS << std::string(indent, ' '); 5673 N->printr(OS, G); 5674 // Having printed this SDNode, walk the children: 5675 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5676 const SDNode *child = N->getOperand(i).getNode(); 5677 if (i) OS << ","; 5678 OS << " "; 5679 if (child->getNumOperands() == 0) { 5680 // This child has no grandchildren; print it inline right here. 5681 child->printr(OS, G); 5682 once.insert(child); 5683 } else { // Just the address. FIXME: also print the child's opcode 5684 OS << (void*)child; 5685 if (unsigned RN = N->getOperand(i).getResNo()) 5686 OS << ":" << RN; 5687 } 5688 } 5689 OS << "\n"; 5690 // Dump children that have grandchildren on their own line(s). 5691 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5692 const SDNode *child = N->getOperand(i).getNode(); 5693 DumpNodesr(OS, child, indent+2, G, once); 5694 } 5695} 5696 5697void SDNode::dumpr() const { 5698 VisitedSDNodeSet once; 5699 DumpNodesr(errs(), this, 0, 0, once); 5700} 5701 5702 5703// getAddressSpace - Return the address space this GlobalAddress belongs to. 5704unsigned GlobalAddressSDNode::getAddressSpace() const { 5705 return getGlobal()->getType()->getAddressSpace(); 5706} 5707 5708 5709const Type *ConstantPoolSDNode::getType() const { 5710 if (isMachineConstantPoolEntry()) 5711 return Val.MachineCPVal->getType(); 5712 return Val.ConstVal->getType(); 5713} 5714 5715bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue, 5716 APInt &SplatUndef, 5717 unsigned &SplatBitSize, 5718 bool &HasAnyUndefs, 5719 unsigned MinSplatBits) { 5720 MVT VT = getValueType(0); 5721 assert(VT.isVector() && "Expected a vector type"); 5722 unsigned sz = VT.getSizeInBits(); 5723 if (MinSplatBits > sz) 5724 return false; 5725 5726 SplatValue = APInt(sz, 0); 5727 SplatUndef = APInt(sz, 0); 5728 5729 // Get the bits. Bits with undefined values (when the corresponding element 5730 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared 5731 // in SplatValue. If any of the values are not constant, give up and return 5732 // false. 5733 unsigned int nOps = getNumOperands(); 5734 assert(nOps > 0 && "isConstantSplat has 0-size build vector"); 5735 unsigned EltBitSize = VT.getVectorElementType().getSizeInBits(); 5736 for (unsigned i = 0; i < nOps; ++i) { 5737 SDValue OpVal = getOperand(i); 5738 unsigned BitPos = i * EltBitSize; 5739 5740 if (OpVal.getOpcode() == ISD::UNDEF) 5741 SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos +EltBitSize); 5742 else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) 5743 SplatValue |= (APInt(CN->getAPIntValue()).zextOrTrunc(EltBitSize). 5744 zextOrTrunc(sz) << BitPos); 5745 else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) 5746 SplatValue |= CN->getValueAPF().bitcastToAPInt().zextOrTrunc(sz) <<BitPos; 5747 else 5748 return false; 5749 } 5750 5751 // The build_vector is all constants or undefs. Find the smallest element 5752 // size that splats the vector. 5753 5754 HasAnyUndefs = (SplatUndef != 0); 5755 while (sz > 8) { 5756 5757 unsigned HalfSize = sz / 2; 5758 APInt HighValue = APInt(SplatValue).lshr(HalfSize).trunc(HalfSize); 5759 APInt LowValue = APInt(SplatValue).trunc(HalfSize); 5760 APInt HighUndef = APInt(SplatUndef).lshr(HalfSize).trunc(HalfSize); 5761 APInt LowUndef = APInt(SplatUndef).trunc(HalfSize); 5762 5763 // If the two halves do not match (ignoring undef bits), stop here. 5764 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) || 5765 MinSplatBits > HalfSize) 5766 break; 5767 5768 SplatValue = HighValue | LowValue; 5769 SplatUndef = HighUndef & LowUndef; 5770 5771 sz = HalfSize; 5772 } 5773 5774 SplatBitSize = sz; 5775 return true; 5776} 5777 5778bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) { 5779 // Find the first non-undef value in the shuffle mask. 5780 unsigned i, e; 5781 for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i) 5782 /* search */; 5783 5784 assert(i != e && "VECTOR_SHUFFLE node with all undef indices!"); 5785 5786 // Make sure all remaining elements are either undef or the same as the first 5787 // non-undef value. 5788 for (int Idx = Mask[i]; i != e; ++i) 5789 if (Mask[i] >= 0 && Mask[i] != Idx) 5790 return false; 5791 return true; 5792} 5793