SelectionDAG.cpp revision 74c376529101acbe141a256d0bf23a44eb454c84
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetInstrInfo.h" 31#include "llvm/Target/TargetMachine.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/ADT/SetVector.h" 36#include "llvm/ADT/SmallPtrSet.h" 37#include "llvm/ADT/SmallSet.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/ADT/StringExtras.h" 40#include <algorithm> 41#include <cmath> 42using namespace llvm; 43 44/// makeVTList - Return an instance of the SDVTList struct initialized with the 45/// specified members. 46static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 47 SDVTList Res = {VTs, NumVTs}; 48 return Res; 49} 50 51static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 52 switch (VT.getSimpleVT()) { 53 default: assert(0 && "Unknown FP format"); 54 case MVT::f32: return &APFloat::IEEEsingle; 55 case MVT::f64: return &APFloat::IEEEdouble; 56 case MVT::f80: return &APFloat::x87DoubleExtended; 57 case MVT::f128: return &APFloat::IEEEquad; 58 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 59 } 60} 61 62SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 63 64//===----------------------------------------------------------------------===// 65// ConstantFPSDNode Class 66//===----------------------------------------------------------------------===// 67 68/// isExactlyValue - We don't rely on operator== working on double values, as 69/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 70/// As such, this method can be used to do an exact bit-for-bit comparison of 71/// two floating point values. 72bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 73 return getValueAPF().bitwiseIsEqual(V); 74} 75 76bool ConstantFPSDNode::isValueValidForType(MVT VT, 77 const APFloat& Val) { 78 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 79 80 // PPC long double cannot be converted to any other type. 81 if (VT == MVT::ppcf128 || 82 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 83 return false; 84 85 // convert modifies in place, so make a copy. 86 APFloat Val2 = APFloat(Val); 87 bool losesInfo; 88 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 89 &losesInfo); 90 return !losesInfo; 91} 92 93//===----------------------------------------------------------------------===// 94// ISD Namespace 95//===----------------------------------------------------------------------===// 96 97/// isBuildVectorAllOnes - Return true if the specified node is a 98/// BUILD_VECTOR where all of the elements are ~0 or undef. 99bool ISD::isBuildVectorAllOnes(const SDNode *N) { 100 // Look through a bit convert. 101 if (N->getOpcode() == ISD::BIT_CONVERT) 102 N = N->getOperand(0).getNode(); 103 104 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 105 106 unsigned i = 0, e = N->getNumOperands(); 107 108 // Skip over all of the undef values. 109 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 110 ++i; 111 112 // Do not accept an all-undef vector. 113 if (i == e) return false; 114 115 // Do not accept build_vectors that aren't all constants or which have non-~0 116 // elements. 117 SDValue NotZero = N->getOperand(i); 118 if (isa<ConstantSDNode>(NotZero)) { 119 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 120 return false; 121 } else if (isa<ConstantFPSDNode>(NotZero)) { 122 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 123 bitcastToAPInt().isAllOnesValue()) 124 return false; 125 } else 126 return false; 127 128 // Okay, we have at least one ~0 value, check to see if the rest match or are 129 // undefs. 130 for (++i; i != e; ++i) 131 if (N->getOperand(i) != NotZero && 132 N->getOperand(i).getOpcode() != ISD::UNDEF) 133 return false; 134 return true; 135} 136 137 138/// isBuildVectorAllZeros - Return true if the specified node is a 139/// BUILD_VECTOR where all of the elements are 0 or undef. 140bool ISD::isBuildVectorAllZeros(const SDNode *N) { 141 // Look through a bit convert. 142 if (N->getOpcode() == ISD::BIT_CONVERT) 143 N = N->getOperand(0).getNode(); 144 145 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 146 147 unsigned i = 0, e = N->getNumOperands(); 148 149 // Skip over all of the undef values. 150 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 151 ++i; 152 153 // Do not accept an all-undef vector. 154 if (i == e) return false; 155 156 // Do not accept build_vectors that aren't all constants or which have non-~0 157 // elements. 158 SDValue Zero = N->getOperand(i); 159 if (isa<ConstantSDNode>(Zero)) { 160 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 161 return false; 162 } else if (isa<ConstantFPSDNode>(Zero)) { 163 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 164 return false; 165 } else 166 return false; 167 168 // Okay, we have at least one ~0 value, check to see if the rest match or are 169 // undefs. 170 for (++i; i != e; ++i) 171 if (N->getOperand(i) != Zero && 172 N->getOperand(i).getOpcode() != ISD::UNDEF) 173 return false; 174 return true; 175} 176 177/// isScalarToVector - Return true if the specified node is a 178/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 179/// element is not an undef. 180bool ISD::isScalarToVector(const SDNode *N) { 181 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 182 return true; 183 184 if (N->getOpcode() != ISD::BUILD_VECTOR) 185 return false; 186 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 187 return false; 188 unsigned NumElems = N->getNumOperands(); 189 for (unsigned i = 1; i < NumElems; ++i) { 190 SDValue V = N->getOperand(i); 191 if (V.getOpcode() != ISD::UNDEF) 192 return false; 193 } 194 return true; 195} 196 197 198/// isDebugLabel - Return true if the specified node represents a debug 199/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 200bool ISD::isDebugLabel(const SDNode *N) { 201 SDValue Zero; 202 if (N->getOpcode() == ISD::DBG_LABEL) 203 return true; 204 if (N->isMachineOpcode() && 205 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 206 return true; 207 return false; 208} 209 210/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 211/// when given the operation for (X op Y). 212ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 213 // To perform this operation, we just need to swap the L and G bits of the 214 // operation. 215 unsigned OldL = (Operation >> 2) & 1; 216 unsigned OldG = (Operation >> 1) & 1; 217 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 218 (OldL << 1) | // New G bit 219 (OldG << 2)); // New L bit. 220} 221 222/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 223/// 'op' is a valid SetCC operation. 224ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 225 unsigned Operation = Op; 226 if (isInteger) 227 Operation ^= 7; // Flip L, G, E bits, but not U. 228 else 229 Operation ^= 15; // Flip all of the condition bits. 230 231 if (Operation > ISD::SETTRUE2) 232 Operation &= ~8; // Don't let N and U bits get set. 233 234 return ISD::CondCode(Operation); 235} 236 237 238/// isSignedOp - For an integer comparison, return 1 if the comparison is a 239/// signed operation and 2 if the result is an unsigned comparison. Return zero 240/// if the operation does not depend on the sign of the input (setne and seteq). 241static int isSignedOp(ISD::CondCode Opcode) { 242 switch (Opcode) { 243 default: assert(0 && "Illegal integer setcc operation!"); 244 case ISD::SETEQ: 245 case ISD::SETNE: return 0; 246 case ISD::SETLT: 247 case ISD::SETLE: 248 case ISD::SETGT: 249 case ISD::SETGE: return 1; 250 case ISD::SETULT: 251 case ISD::SETULE: 252 case ISD::SETUGT: 253 case ISD::SETUGE: return 2; 254 } 255} 256 257/// getSetCCOrOperation - Return the result of a logical OR between different 258/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 259/// returns SETCC_INVALID if it is not possible to represent the resultant 260/// comparison. 261ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 262 bool isInteger) { 263 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 264 // Cannot fold a signed integer setcc with an unsigned integer setcc. 265 return ISD::SETCC_INVALID; 266 267 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 268 269 // If the N and U bits get set then the resultant comparison DOES suddenly 270 // care about orderedness, and is true when ordered. 271 if (Op > ISD::SETTRUE2) 272 Op &= ~16; // Clear the U bit if the N bit is set. 273 274 // Canonicalize illegal integer setcc's. 275 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 276 Op = ISD::SETNE; 277 278 return ISD::CondCode(Op); 279} 280 281/// getSetCCAndOperation - Return the result of a logical AND between different 282/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 283/// function returns zero if it is not possible to represent the resultant 284/// comparison. 285ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 286 bool isInteger) { 287 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 288 // Cannot fold a signed setcc with an unsigned setcc. 289 return ISD::SETCC_INVALID; 290 291 // Combine all of the condition bits. 292 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 293 294 // Canonicalize illegal integer setcc's. 295 if (isInteger) { 296 switch (Result) { 297 default: break; 298 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 299 case ISD::SETOEQ: // SETEQ & SETU[LG]E 300 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 301 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 302 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 303 } 304 } 305 306 return Result; 307} 308 309const TargetMachine &SelectionDAG::getTarget() const { 310 return MF->getTarget(); 311} 312 313//===----------------------------------------------------------------------===// 314// SDNode Profile Support 315//===----------------------------------------------------------------------===// 316 317/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 318/// 319static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 320 ID.AddInteger(OpC); 321} 322 323/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 324/// solely with their pointer. 325static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 326 ID.AddPointer(VTList.VTs); 327} 328 329/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 330/// 331static void AddNodeIDOperands(FoldingSetNodeID &ID, 332 const SDValue *Ops, unsigned NumOps) { 333 for (; NumOps; --NumOps, ++Ops) { 334 ID.AddPointer(Ops->getNode()); 335 ID.AddInteger(Ops->getResNo()); 336 } 337} 338 339/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 340/// 341static void AddNodeIDOperands(FoldingSetNodeID &ID, 342 const SDUse *Ops, unsigned NumOps) { 343 for (; NumOps; --NumOps, ++Ops) { 344 ID.AddPointer(Ops->getVal()); 345 ID.AddInteger(Ops->getSDValue().getResNo()); 346 } 347} 348 349static void AddNodeIDNode(FoldingSetNodeID &ID, 350 unsigned short OpC, SDVTList VTList, 351 const SDValue *OpList, unsigned N) { 352 AddNodeIDOpcode(ID, OpC); 353 AddNodeIDValueTypes(ID, VTList); 354 AddNodeIDOperands(ID, OpList, N); 355} 356 357/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 358/// the NodeID data. 359static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 360 switch (N->getOpcode()) { 361 default: break; // Normal nodes don't need extra info. 362 case ISD::ARG_FLAGS: 363 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 364 break; 365 case ISD::TargetConstant: 366 case ISD::Constant: 367 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 368 break; 369 case ISD::TargetConstantFP: 370 case ISD::ConstantFP: { 371 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 372 break; 373 } 374 case ISD::TargetGlobalAddress: 375 case ISD::GlobalAddress: 376 case ISD::TargetGlobalTLSAddress: 377 case ISD::GlobalTLSAddress: { 378 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 379 ID.AddPointer(GA->getGlobal()); 380 ID.AddInteger(GA->getOffset()); 381 break; 382 } 383 case ISD::BasicBlock: 384 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 385 break; 386 case ISD::Register: 387 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 388 break; 389 case ISD::DBG_STOPPOINT: { 390 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 391 ID.AddInteger(DSP->getLine()); 392 ID.AddInteger(DSP->getColumn()); 393 ID.AddPointer(DSP->getCompileUnit()); 394 break; 395 } 396 case ISD::SRCVALUE: 397 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 398 break; 399 case ISD::MEMOPERAND: { 400 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 401 MO.Profile(ID); 402 break; 403 } 404 case ISD::FrameIndex: 405 case ISD::TargetFrameIndex: 406 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 407 break; 408 case ISD::JumpTable: 409 case ISD::TargetJumpTable: 410 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 411 break; 412 case ISD::ConstantPool: 413 case ISD::TargetConstantPool: { 414 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 415 ID.AddInteger(CP->getAlignment()); 416 ID.AddInteger(CP->getOffset()); 417 if (CP->isMachineConstantPoolEntry()) 418 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 419 else 420 ID.AddPointer(CP->getConstVal()); 421 break; 422 } 423 case ISD::CALL: { 424 const CallSDNode *Call = cast<CallSDNode>(N); 425 ID.AddInteger(Call->getCallingConv()); 426 ID.AddInteger(Call->isVarArg()); 427 break; 428 } 429 case ISD::LOAD: { 430 const LoadSDNode *LD = cast<LoadSDNode>(N); 431 ID.AddInteger(LD->getAddressingMode()); 432 ID.AddInteger(LD->getExtensionType()); 433 ID.AddInteger(LD->getMemoryVT().getRawBits()); 434 ID.AddInteger(LD->getRawFlags()); 435 break; 436 } 437 case ISD::STORE: { 438 const StoreSDNode *ST = cast<StoreSDNode>(N); 439 ID.AddInteger(ST->getAddressingMode()); 440 ID.AddInteger(ST->isTruncatingStore()); 441 ID.AddInteger(ST->getMemoryVT().getRawBits()); 442 ID.AddInteger(ST->getRawFlags()); 443 break; 444 } 445 case ISD::ATOMIC_CMP_SWAP_8: 446 case ISD::ATOMIC_SWAP_8: 447 case ISD::ATOMIC_LOAD_ADD_8: 448 case ISD::ATOMIC_LOAD_SUB_8: 449 case ISD::ATOMIC_LOAD_AND_8: 450 case ISD::ATOMIC_LOAD_OR_8: 451 case ISD::ATOMIC_LOAD_XOR_8: 452 case ISD::ATOMIC_LOAD_NAND_8: 453 case ISD::ATOMIC_LOAD_MIN_8: 454 case ISD::ATOMIC_LOAD_MAX_8: 455 case ISD::ATOMIC_LOAD_UMIN_8: 456 case ISD::ATOMIC_LOAD_UMAX_8: 457 case ISD::ATOMIC_CMP_SWAP_16: 458 case ISD::ATOMIC_SWAP_16: 459 case ISD::ATOMIC_LOAD_ADD_16: 460 case ISD::ATOMIC_LOAD_SUB_16: 461 case ISD::ATOMIC_LOAD_AND_16: 462 case ISD::ATOMIC_LOAD_OR_16: 463 case ISD::ATOMIC_LOAD_XOR_16: 464 case ISD::ATOMIC_LOAD_NAND_16: 465 case ISD::ATOMIC_LOAD_MIN_16: 466 case ISD::ATOMIC_LOAD_MAX_16: 467 case ISD::ATOMIC_LOAD_UMIN_16: 468 case ISD::ATOMIC_LOAD_UMAX_16: 469 case ISD::ATOMIC_CMP_SWAP_32: 470 case ISD::ATOMIC_SWAP_32: 471 case ISD::ATOMIC_LOAD_ADD_32: 472 case ISD::ATOMIC_LOAD_SUB_32: 473 case ISD::ATOMIC_LOAD_AND_32: 474 case ISD::ATOMIC_LOAD_OR_32: 475 case ISD::ATOMIC_LOAD_XOR_32: 476 case ISD::ATOMIC_LOAD_NAND_32: 477 case ISD::ATOMIC_LOAD_MIN_32: 478 case ISD::ATOMIC_LOAD_MAX_32: 479 case ISD::ATOMIC_LOAD_UMIN_32: 480 case ISD::ATOMIC_LOAD_UMAX_32: 481 case ISD::ATOMIC_CMP_SWAP_64: 482 case ISD::ATOMIC_SWAP_64: 483 case ISD::ATOMIC_LOAD_ADD_64: 484 case ISD::ATOMIC_LOAD_SUB_64: 485 case ISD::ATOMIC_LOAD_AND_64: 486 case ISD::ATOMIC_LOAD_OR_64: 487 case ISD::ATOMIC_LOAD_XOR_64: 488 case ISD::ATOMIC_LOAD_NAND_64: 489 case ISD::ATOMIC_LOAD_MIN_64: 490 case ISD::ATOMIC_LOAD_MAX_64: 491 case ISD::ATOMIC_LOAD_UMIN_64: 492 case ISD::ATOMIC_LOAD_UMAX_64: { 493 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 494 ID.AddInteger(AT->getRawFlags()); 495 break; 496 } 497 } // end switch (N->getOpcode()) 498} 499 500/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 501/// data. 502static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 503 AddNodeIDOpcode(ID, N->getOpcode()); 504 // Add the return value info. 505 AddNodeIDValueTypes(ID, N->getVTList()); 506 // Add the operand info. 507 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 508 509 // Handle SDNode leafs with special info. 510 AddNodeIDCustom(ID, N); 511} 512 513/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 514/// the CSE map that carries both alignment and volatility information. 515/// 516static inline unsigned 517encodeMemSDNodeFlags(bool isVolatile, unsigned Alignment) { 518 return isVolatile | ((Log2_32(Alignment) + 1) << 1); 519} 520 521//===----------------------------------------------------------------------===// 522// SelectionDAG Class 523//===----------------------------------------------------------------------===// 524 525/// doNotCSE - Return true if CSE should not be performed for this node. 526static bool doNotCSE(SDNode *N) { 527 if (N->getValueType(0) == MVT::Flag) 528 return true; // Never CSE anything that produces a flag. 529 530 switch (N->getOpcode()) { 531 default: break; 532 case ISD::HANDLENODE: 533 case ISD::DBG_LABEL: 534 case ISD::DBG_STOPPOINT: 535 case ISD::EH_LABEL: 536 case ISD::DECLARE: 537 return true; // Never CSE these nodes. 538 } 539 540 // Check that remaining values produced are not flags. 541 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 542 if (N->getValueType(i) == MVT::Flag) 543 return true; // Never CSE anything that produces a flag. 544 545 return false; 546} 547 548/// RemoveDeadNodes - This method deletes all unreachable nodes in the 549/// SelectionDAG. 550void SelectionDAG::RemoveDeadNodes() { 551 // Create a dummy node (which is not added to allnodes), that adds a reference 552 // to the root node, preventing it from being deleted. 553 HandleSDNode Dummy(getRoot()); 554 555 SmallVector<SDNode*, 128> DeadNodes; 556 557 // Add all obviously-dead nodes to the DeadNodes worklist. 558 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 559 if (I->use_empty()) 560 DeadNodes.push_back(I); 561 562 RemoveDeadNodes(DeadNodes); 563 564 // If the root changed (e.g. it was a dead load, update the root). 565 setRoot(Dummy.getValue()); 566} 567 568/// RemoveDeadNodes - This method deletes the unreachable nodes in the 569/// given list, and any nodes that become unreachable as a result. 570void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 571 DAGUpdateListener *UpdateListener) { 572 573 // Process the worklist, deleting the nodes and adding their uses to the 574 // worklist. 575 while (!DeadNodes.empty()) { 576 SDNode *N = DeadNodes.back(); 577 DeadNodes.pop_back(); 578 579 if (UpdateListener) 580 UpdateListener->NodeDeleted(N, 0); 581 582 // Take the node out of the appropriate CSE map. 583 RemoveNodeFromCSEMaps(N); 584 585 // Next, brutally remove the operand list. This is safe to do, as there are 586 // no cycles in the graph. 587 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) { 588 SDNode *Operand = I->getVal(); 589 Operand->removeUser(std::distance(N->op_begin(), I), N); 590 591 // Now that we removed this operand, see if there are no uses of it left. 592 if (Operand->use_empty()) 593 DeadNodes.push_back(Operand); 594 } 595 596 if (N->OperandsNeedDelete) 597 delete[] N->OperandList; 598 599 N->OperandList = 0; 600 N->NumOperands = 0; 601 602 // Finally, remove N itself. 603 NodeAllocator.Deallocate(AllNodes.remove(N)); 604 } 605} 606 607void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 608 SmallVector<SDNode*, 16> DeadNodes(1, N); 609 RemoveDeadNodes(DeadNodes, UpdateListener); 610} 611 612void SelectionDAG::DeleteNode(SDNode *N) { 613 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 614 615 // First take this out of the appropriate CSE map. 616 RemoveNodeFromCSEMaps(N); 617 618 // Finally, remove uses due to operands of this node, remove from the 619 // AllNodes list, and delete the node. 620 DeleteNodeNotInCSEMaps(N); 621} 622 623void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 624 // Drop all of the operands and decrement used node's use counts. 625 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 626 I->getVal()->removeUser(std::distance(N->op_begin(), I), N); 627 628 if (N->OperandsNeedDelete) { 629 delete[] N->OperandList; 630 N->OperandList = 0; 631 } 632 633 assert(N != AllNodes.begin()); 634 NodeAllocator.Deallocate(AllNodes.remove(N)); 635} 636 637/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 638/// correspond to it. This is useful when we're about to delete or repurpose 639/// the node. We don't want future request for structurally identical nodes 640/// to return N anymore. 641bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 642 bool Erased = false; 643 switch (N->getOpcode()) { 644 case ISD::EntryToken: 645 assert(0 && "EntryToken should not be in CSEMaps!"); 646 return false; 647 case ISD::HANDLENODE: return false; // noop. 648 case ISD::CONDCODE: 649 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 650 "Cond code doesn't exist!"); 651 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 652 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 653 break; 654 case ISD::ExternalSymbol: 655 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 656 break; 657 case ISD::TargetExternalSymbol: 658 Erased = 659 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 660 break; 661 case ISD::VALUETYPE: { 662 MVT VT = cast<VTSDNode>(N)->getVT(); 663 if (VT.isExtended()) { 664 Erased = ExtendedValueTypeNodes.erase(VT); 665 } else { 666 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 667 ValueTypeNodes[VT.getSimpleVT()] = 0; 668 } 669 break; 670 } 671 default: 672 // Remove it from the CSE Map. 673 Erased = CSEMap.RemoveNode(N); 674 break; 675 } 676#ifndef NDEBUG 677 // Verify that the node was actually in one of the CSE maps, unless it has a 678 // flag result (which cannot be CSE'd) or is one of the special cases that are 679 // not subject to CSE. 680 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 681 !N->isMachineOpcode() && !doNotCSE(N)) { 682 N->dump(this); 683 cerr << "\n"; 684 assert(0 && "Node is not in map!"); 685 } 686#endif 687 return Erased; 688} 689 690/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 691/// has been taken out and modified in some way. If the specified node already 692/// exists in the CSE maps, do not modify the maps, but return the existing node 693/// instead. If it doesn't exist, add it and return null. 694/// 695SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 696 assert(N->getNumOperands() && "This is a leaf node!"); 697 698 if (doNotCSE(N)) 699 return 0; 700 701 SDNode *New = CSEMap.GetOrInsertNode(N); 702 if (New != N) return New; // Node already existed. 703 return 0; 704} 705 706/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 707/// were replaced with those specified. If this node is never memoized, 708/// return null, otherwise return a pointer to the slot it would take. If a 709/// node already exists with these operands, the slot will be non-null. 710SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 711 void *&InsertPos) { 712 if (doNotCSE(N)) 713 return 0; 714 715 SDValue Ops[] = { Op }; 716 FoldingSetNodeID ID; 717 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 718 AddNodeIDCustom(ID, N); 719 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 720} 721 722/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 723/// were replaced with those specified. If this node is never memoized, 724/// return null, otherwise return a pointer to the slot it would take. If a 725/// node already exists with these operands, the slot will be non-null. 726SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 727 SDValue Op1, SDValue Op2, 728 void *&InsertPos) { 729 if (doNotCSE(N)) 730 return 0; 731 732 SDValue Ops[] = { Op1, Op2 }; 733 FoldingSetNodeID ID; 734 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 735 AddNodeIDCustom(ID, N); 736 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 737} 738 739 740/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 741/// were replaced with those specified. If this node is never memoized, 742/// return null, otherwise return a pointer to the slot it would take. If a 743/// node already exists with these operands, the slot will be non-null. 744SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 745 const SDValue *Ops,unsigned NumOps, 746 void *&InsertPos) { 747 if (doNotCSE(N)) 748 return 0; 749 750 FoldingSetNodeID ID; 751 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 752 AddNodeIDCustom(ID, N); 753 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 754} 755 756/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 757void SelectionDAG::VerifyNode(SDNode *N) { 758 switch (N->getOpcode()) { 759 default: 760 break; 761 case ISD::BUILD_PAIR: { 762 MVT VT = N->getValueType(0); 763 assert(N->getNumValues() == 1 && "Too many results!"); 764 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 765 "Wrong return type!"); 766 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 767 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 768 "Mismatched operand types!"); 769 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 770 "Wrong operand type!"); 771 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 772 "Wrong return type size"); 773 break; 774 } 775 case ISD::BUILD_VECTOR: { 776 assert(N->getNumValues() == 1 && "Too many results!"); 777 assert(N->getValueType(0).isVector() && "Wrong return type!"); 778 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 779 "Wrong number of operands!"); 780 // FIXME: Change vector_shuffle to a variadic node with mask elements being 781 // operands of the node. Currently the mask is a BUILD_VECTOR passed as an 782 // operand, and it is not always possible to legalize it. Turning off the 783 // following checks at least makes it possible to legalize most of the time. 784// MVT EltVT = N->getValueType(0).getVectorElementType(); 785// for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 786// assert(I->getSDValue().getValueType() == EltVT && 787// "Wrong operand type!"); 788 break; 789 } 790 } 791} 792 793/// getMVTAlignment - Compute the default alignment value for the 794/// given type. 795/// 796unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 797 const Type *Ty = VT == MVT::iPTR ? 798 PointerType::get(Type::Int8Ty, 0) : 799 VT.getTypeForMVT(); 800 801 return TLI.getTargetData()->getABITypeAlignment(Ty); 802} 803 804SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 805 : TLI(tli), FLI(fli), 806 EntryNode(ISD::EntryToken, getVTList(MVT::Other)), 807 Root(getEntryNode()) { 808 AllNodes.push_back(&EntryNode); 809} 810 811void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi) { 812 MF = &mf; 813 MMI = mmi; 814} 815 816SelectionDAG::~SelectionDAG() { 817 allnodes_clear(); 818} 819 820void SelectionDAG::allnodes_clear() { 821 assert(&*AllNodes.begin() == &EntryNode); 822 AllNodes.remove(AllNodes.begin()); 823 while (!AllNodes.empty()) { 824 SDNode *N = AllNodes.remove(AllNodes.begin()); 825 N->SetNextInBucket(0); 826 827 if (N->OperandsNeedDelete) { 828 delete [] N->OperandList; 829 N->OperandList = 0; 830 } 831 832 NodeAllocator.Deallocate(N); 833 } 834} 835 836void SelectionDAG::clear() { 837 allnodes_clear(); 838 OperandAllocator.Reset(); 839 CSEMap.clear(); 840 841 ExtendedValueTypeNodes.clear(); 842 ExternalSymbols.clear(); 843 TargetExternalSymbols.clear(); 844 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 845 static_cast<CondCodeSDNode*>(0)); 846 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 847 static_cast<SDNode*>(0)); 848 849 EntryNode.Uses = 0; 850 AllNodes.push_back(&EntryNode); 851 Root = getEntryNode(); 852} 853 854SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) { 855 if (Op.getValueType() == VT) return Op; 856 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 857 VT.getSizeInBits()); 858 return getNode(ISD::AND, Op.getValueType(), Op, 859 getConstant(Imm, Op.getValueType())); 860} 861 862SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 863 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 864 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 865} 866 867SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 868 return getConstant(*ConstantInt::get(Val), VT, isT); 869} 870 871SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 872 assert(VT.isInteger() && "Cannot create FP integer constant!"); 873 874 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 875 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 876 "APInt size does not match type size!"); 877 878 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 879 FoldingSetNodeID ID; 880 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 881 ID.AddPointer(&Val); 882 void *IP = 0; 883 SDNode *N = NULL; 884 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 885 if (!VT.isVector()) 886 return SDValue(N, 0); 887 if (!N) { 888 N = NodeAllocator.Allocate<ConstantSDNode>(); 889 new (N) ConstantSDNode(isT, &Val, EltVT); 890 CSEMap.InsertNode(N, IP); 891 AllNodes.push_back(N); 892 } 893 894 SDValue Result(N, 0); 895 if (VT.isVector()) { 896 SmallVector<SDValue, 8> Ops; 897 Ops.assign(VT.getVectorNumElements(), Result); 898 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 899 } 900 return Result; 901} 902 903SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 904 return getConstant(Val, TLI.getPointerTy(), isTarget); 905} 906 907 908SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 909 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 910} 911 912SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 913 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 914 915 MVT EltVT = 916 VT.isVector() ? VT.getVectorElementType() : VT; 917 918 // Do the map lookup using the actual bit pattern for the floating point 919 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 920 // we don't have issues with SNANs. 921 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 922 FoldingSetNodeID ID; 923 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 924 ID.AddPointer(&V); 925 void *IP = 0; 926 SDNode *N = NULL; 927 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 928 if (!VT.isVector()) 929 return SDValue(N, 0); 930 if (!N) { 931 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 932 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 933 CSEMap.InsertNode(N, IP); 934 AllNodes.push_back(N); 935 } 936 937 SDValue Result(N, 0); 938 if (VT.isVector()) { 939 SmallVector<SDValue, 8> Ops; 940 Ops.assign(VT.getVectorNumElements(), Result); 941 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 942 } 943 return Result; 944} 945 946SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 947 MVT EltVT = 948 VT.isVector() ? VT.getVectorElementType() : VT; 949 if (EltVT==MVT::f32) 950 return getConstantFP(APFloat((float)Val), VT, isTarget); 951 else 952 return getConstantFP(APFloat(Val), VT, isTarget); 953} 954 955SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 956 MVT VT, int64_t Offset, 957 bool isTargetGA) { 958 unsigned Opc; 959 960 // Truncate (with sign-extension) the offset value to the pointer size. 961 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 962 if (BitWidth < 64) 963 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 964 965 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 966 if (!GVar) { 967 // If GV is an alias then use the aliasee for determining thread-localness. 968 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 969 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 970 } 971 972 if (GVar && GVar->isThreadLocal()) 973 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 974 else 975 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 976 977 FoldingSetNodeID ID; 978 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 979 ID.AddPointer(GV); 980 ID.AddInteger(Offset); 981 void *IP = 0; 982 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 983 return SDValue(E, 0); 984 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 985 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 986 CSEMap.InsertNode(N, IP); 987 AllNodes.push_back(N); 988 return SDValue(N, 0); 989} 990 991SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 992 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 993 FoldingSetNodeID ID; 994 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 995 ID.AddInteger(FI); 996 void *IP = 0; 997 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 998 return SDValue(E, 0); 999 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 1000 new (N) FrameIndexSDNode(FI, VT, isTarget); 1001 CSEMap.InsertNode(N, IP); 1002 AllNodes.push_back(N); 1003 return SDValue(N, 0); 1004} 1005 1006SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 1007 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1008 FoldingSetNodeID ID; 1009 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1010 ID.AddInteger(JTI); 1011 void *IP = 0; 1012 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1013 return SDValue(E, 0); 1014 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1015 new (N) JumpTableSDNode(JTI, VT, isTarget); 1016 CSEMap.InsertNode(N, IP); 1017 AllNodes.push_back(N); 1018 return SDValue(N, 0); 1019} 1020 1021SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1022 unsigned Alignment, int Offset, 1023 bool isTarget) { 1024 if (Alignment == 0) 1025 Alignment = 1026 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1027 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1028 FoldingSetNodeID ID; 1029 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1030 ID.AddInteger(Alignment); 1031 ID.AddInteger(Offset); 1032 ID.AddPointer(C); 1033 void *IP = 0; 1034 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1035 return SDValue(E, 0); 1036 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1037 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1038 CSEMap.InsertNode(N, IP); 1039 AllNodes.push_back(N); 1040 return SDValue(N, 0); 1041} 1042 1043 1044SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1045 unsigned Alignment, int Offset, 1046 bool isTarget) { 1047 if (Alignment == 0) 1048 Alignment = 1049 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1050 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1051 FoldingSetNodeID ID; 1052 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1053 ID.AddInteger(Alignment); 1054 ID.AddInteger(Offset); 1055 C->AddSelectionDAGCSEId(ID); 1056 void *IP = 0; 1057 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1058 return SDValue(E, 0); 1059 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1060 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1061 CSEMap.InsertNode(N, IP); 1062 AllNodes.push_back(N); 1063 return SDValue(N, 0); 1064} 1065 1066 1067SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1068 FoldingSetNodeID ID; 1069 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1070 ID.AddPointer(MBB); 1071 void *IP = 0; 1072 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1073 return SDValue(E, 0); 1074 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1075 new (N) BasicBlockSDNode(MBB); 1076 CSEMap.InsertNode(N, IP); 1077 AllNodes.push_back(N); 1078 return SDValue(N, 0); 1079} 1080 1081SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1082 FoldingSetNodeID ID; 1083 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1084 ID.AddInteger(Flags.getRawBits()); 1085 void *IP = 0; 1086 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1087 return SDValue(E, 0); 1088 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1089 new (N) ARG_FLAGSSDNode(Flags); 1090 CSEMap.InsertNode(N, IP); 1091 AllNodes.push_back(N); 1092 return SDValue(N, 0); 1093} 1094 1095SDValue SelectionDAG::getValueType(MVT VT) { 1096 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1097 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1098 1099 SDNode *&N = VT.isExtended() ? 1100 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1101 1102 if (N) return SDValue(N, 0); 1103 N = NodeAllocator.Allocate<VTSDNode>(); 1104 new (N) VTSDNode(VT); 1105 AllNodes.push_back(N); 1106 return SDValue(N, 0); 1107} 1108 1109SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1110 SDNode *&N = ExternalSymbols[Sym]; 1111 if (N) return SDValue(N, 0); 1112 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1113 new (N) ExternalSymbolSDNode(false, Sym, VT); 1114 AllNodes.push_back(N); 1115 return SDValue(N, 0); 1116} 1117 1118SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1119 SDNode *&N = TargetExternalSymbols[Sym]; 1120 if (N) return SDValue(N, 0); 1121 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1122 new (N) ExternalSymbolSDNode(true, Sym, VT); 1123 AllNodes.push_back(N); 1124 return SDValue(N, 0); 1125} 1126 1127SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1128 if ((unsigned)Cond >= CondCodeNodes.size()) 1129 CondCodeNodes.resize(Cond+1); 1130 1131 if (CondCodeNodes[Cond] == 0) { 1132 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1133 new (N) CondCodeSDNode(Cond); 1134 CondCodeNodes[Cond] = N; 1135 AllNodes.push_back(N); 1136 } 1137 return SDValue(CondCodeNodes[Cond], 0); 1138} 1139 1140SDValue SelectionDAG::getConvertRndSat(MVT VT, SDValue Val, SDValue DTy, 1141 SDValue STy, SDValue Rnd, SDValue Sat, 1142 ISD::CvtCode Code) { 1143 FoldingSetNodeID ID; 1144 void* IP = 0; 1145 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1146 return SDValue(E, 0); 1147 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1148 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1149 new (N) CvtRndSatSDNode(VT, Ops, 5, Code); 1150 CSEMap.InsertNode(N, IP); 1151 AllNodes.push_back(N); 1152 return SDValue(N, 0); 1153} 1154 1155SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1156 FoldingSetNodeID ID; 1157 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1158 ID.AddInteger(RegNo); 1159 void *IP = 0; 1160 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1161 return SDValue(E, 0); 1162 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1163 new (N) RegisterSDNode(RegNo, VT); 1164 CSEMap.InsertNode(N, IP); 1165 AllNodes.push_back(N); 1166 return SDValue(N, 0); 1167} 1168 1169SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1170 unsigned Line, unsigned Col, 1171 const CompileUnitDesc *CU) { 1172 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1173 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1174 AllNodes.push_back(N); 1175 return SDValue(N, 0); 1176} 1177 1178SDValue SelectionDAG::getLabel(unsigned Opcode, 1179 SDValue Root, 1180 unsigned LabelID) { 1181 FoldingSetNodeID ID; 1182 SDValue Ops[] = { Root }; 1183 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1184 ID.AddInteger(LabelID); 1185 void *IP = 0; 1186 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1187 return SDValue(E, 0); 1188 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1189 new (N) LabelSDNode(Opcode, Root, LabelID); 1190 CSEMap.InsertNode(N, IP); 1191 AllNodes.push_back(N); 1192 return SDValue(N, 0); 1193} 1194 1195SDValue SelectionDAG::getSrcValue(const Value *V) { 1196 assert((!V || isa<PointerType>(V->getType())) && 1197 "SrcValue is not a pointer?"); 1198 1199 FoldingSetNodeID ID; 1200 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1201 ID.AddPointer(V); 1202 1203 void *IP = 0; 1204 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1205 return SDValue(E, 0); 1206 1207 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1208 new (N) SrcValueSDNode(V); 1209 CSEMap.InsertNode(N, IP); 1210 AllNodes.push_back(N); 1211 return SDValue(N, 0); 1212} 1213 1214SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1215#ifndef NDEBUG 1216 const Value *v = MO.getValue(); 1217 assert((!v || isa<PointerType>(v->getType())) && 1218 "SrcValue is not a pointer?"); 1219#endif 1220 1221 FoldingSetNodeID ID; 1222 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1223 MO.Profile(ID); 1224 1225 void *IP = 0; 1226 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1227 return SDValue(E, 0); 1228 1229 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1230 new (N) MemOperandSDNode(MO); 1231 CSEMap.InsertNode(N, IP); 1232 AllNodes.push_back(N); 1233 return SDValue(N, 0); 1234} 1235 1236/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1237/// specified value type. 1238SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1239 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1240 unsigned ByteSize = VT.getStoreSizeInBits()/8; 1241 const Type *Ty = VT.getTypeForMVT(); 1242 unsigned StackAlign = 1243 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1244 1245 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1246 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1247} 1248 1249/// CreateStackTemporary - Create a stack temporary suitable for holding 1250/// either of the specified value types. 1251SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) { 1252 unsigned Bytes = std::max(VT1.getStoreSizeInBits(), 1253 VT2.getStoreSizeInBits())/8; 1254 const Type *Ty1 = VT1.getTypeForMVT(); 1255 const Type *Ty2 = VT2.getTypeForMVT(); 1256 const TargetData *TD = TLI.getTargetData(); 1257 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1), 1258 TD->getPrefTypeAlignment(Ty2)); 1259 1260 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1261 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align); 1262 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1263} 1264 1265SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1266 SDValue N2, ISD::CondCode Cond) { 1267 // These setcc operations always fold. 1268 switch (Cond) { 1269 default: break; 1270 case ISD::SETFALSE: 1271 case ISD::SETFALSE2: return getConstant(0, VT); 1272 case ISD::SETTRUE: 1273 case ISD::SETTRUE2: return getConstant(1, VT); 1274 1275 case ISD::SETOEQ: 1276 case ISD::SETOGT: 1277 case ISD::SETOGE: 1278 case ISD::SETOLT: 1279 case ISD::SETOLE: 1280 case ISD::SETONE: 1281 case ISD::SETO: 1282 case ISD::SETUO: 1283 case ISD::SETUEQ: 1284 case ISD::SETUNE: 1285 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1286 break; 1287 } 1288 1289 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1290 const APInt &C2 = N2C->getAPIntValue(); 1291 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1292 const APInt &C1 = N1C->getAPIntValue(); 1293 1294 switch (Cond) { 1295 default: assert(0 && "Unknown integer setcc!"); 1296 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1297 case ISD::SETNE: return getConstant(C1 != C2, VT); 1298 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1299 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1300 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1301 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1302 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1303 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1304 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1305 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1306 } 1307 } 1308 } 1309 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1310 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1311 // No compile time operations on this type yet. 1312 if (N1C->getValueType(0) == MVT::ppcf128) 1313 return SDValue(); 1314 1315 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1316 switch (Cond) { 1317 default: break; 1318 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1319 return getNode(ISD::UNDEF, VT); 1320 // fall through 1321 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1322 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1323 return getNode(ISD::UNDEF, VT); 1324 // fall through 1325 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1326 R==APFloat::cmpLessThan, VT); 1327 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1328 return getNode(ISD::UNDEF, VT); 1329 // fall through 1330 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1331 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1332 return getNode(ISD::UNDEF, VT); 1333 // fall through 1334 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1335 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1336 return getNode(ISD::UNDEF, VT); 1337 // fall through 1338 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1339 R==APFloat::cmpEqual, VT); 1340 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1341 return getNode(ISD::UNDEF, VT); 1342 // fall through 1343 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1344 R==APFloat::cmpEqual, VT); 1345 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1346 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1347 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1348 R==APFloat::cmpEqual, VT); 1349 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1350 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1351 R==APFloat::cmpLessThan, VT); 1352 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1353 R==APFloat::cmpUnordered, VT); 1354 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1355 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1356 } 1357 } else { 1358 // Ensure that the constant occurs on the RHS. 1359 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1360 } 1361 } 1362 1363 // Could not fold it. 1364 return SDValue(); 1365} 1366 1367/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1368/// use this predicate to simplify operations downstream. 1369bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1370 unsigned BitWidth = Op.getValueSizeInBits(); 1371 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1372} 1373 1374/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1375/// this predicate to simplify operations downstream. Mask is known to be zero 1376/// for bits that V cannot have. 1377bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1378 unsigned Depth) const { 1379 APInt KnownZero, KnownOne; 1380 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1381 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1382 return (KnownZero & Mask) == Mask; 1383} 1384 1385/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1386/// known to be either zero or one and return them in the KnownZero/KnownOne 1387/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1388/// processing. 1389void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1390 APInt &KnownZero, APInt &KnownOne, 1391 unsigned Depth) const { 1392 unsigned BitWidth = Mask.getBitWidth(); 1393 assert(BitWidth == Op.getValueType().getSizeInBits() && 1394 "Mask size mismatches value type size!"); 1395 1396 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1397 if (Depth == 6 || Mask == 0) 1398 return; // Limit search depth. 1399 1400 APInt KnownZero2, KnownOne2; 1401 1402 switch (Op.getOpcode()) { 1403 case ISD::Constant: 1404 // We know all of the bits for a constant! 1405 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1406 KnownZero = ~KnownOne & Mask; 1407 return; 1408 case ISD::AND: 1409 // If either the LHS or the RHS are Zero, the result is zero. 1410 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1411 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1412 KnownZero2, KnownOne2, Depth+1); 1413 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1414 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1415 1416 // Output known-1 bits are only known if set in both the LHS & RHS. 1417 KnownOne &= KnownOne2; 1418 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1419 KnownZero |= KnownZero2; 1420 return; 1421 case ISD::OR: 1422 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1423 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1424 KnownZero2, KnownOne2, Depth+1); 1425 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1426 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1427 1428 // Output known-0 bits are only known if clear in both the LHS & RHS. 1429 KnownZero &= KnownZero2; 1430 // Output known-1 are known to be set if set in either the LHS | RHS. 1431 KnownOne |= KnownOne2; 1432 return; 1433 case ISD::XOR: { 1434 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1435 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1436 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1437 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1438 1439 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1440 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1441 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1442 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1443 KnownZero = KnownZeroOut; 1444 return; 1445 } 1446 case ISD::MUL: { 1447 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1448 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1449 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1450 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1451 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1452 1453 // If low bits are zero in either operand, output low known-0 bits. 1454 // Also compute a conserative estimate for high known-0 bits. 1455 // More trickiness is possible, but this is sufficient for the 1456 // interesting case of alignment computation. 1457 KnownOne.clear(); 1458 unsigned TrailZ = KnownZero.countTrailingOnes() + 1459 KnownZero2.countTrailingOnes(); 1460 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1461 KnownZero2.countLeadingOnes(), 1462 BitWidth) - BitWidth; 1463 1464 TrailZ = std::min(TrailZ, BitWidth); 1465 LeadZ = std::min(LeadZ, BitWidth); 1466 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1467 APInt::getHighBitsSet(BitWidth, LeadZ); 1468 KnownZero &= Mask; 1469 return; 1470 } 1471 case ISD::UDIV: { 1472 // For the purposes of computing leading zeros we can conservatively 1473 // treat a udiv as a logical right shift by the power of 2 known to 1474 // be less than the denominator. 1475 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1476 ComputeMaskedBits(Op.getOperand(0), 1477 AllOnes, KnownZero2, KnownOne2, Depth+1); 1478 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1479 1480 KnownOne2.clear(); 1481 KnownZero2.clear(); 1482 ComputeMaskedBits(Op.getOperand(1), 1483 AllOnes, KnownZero2, KnownOne2, Depth+1); 1484 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1485 if (RHSUnknownLeadingOnes != BitWidth) 1486 LeadZ = std::min(BitWidth, 1487 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1488 1489 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1490 return; 1491 } 1492 case ISD::SELECT: 1493 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1494 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1495 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1496 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1497 1498 // Only known if known in both the LHS and RHS. 1499 KnownOne &= KnownOne2; 1500 KnownZero &= KnownZero2; 1501 return; 1502 case ISD::SELECT_CC: 1503 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1504 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1505 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1506 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1507 1508 // Only known if known in both the LHS and RHS. 1509 KnownOne &= KnownOne2; 1510 KnownZero &= KnownZero2; 1511 return; 1512 case ISD::SADDO: 1513 case ISD::UADDO: 1514 case ISD::SSUBO: 1515 case ISD::USUBO: 1516 case ISD::SMULO: 1517 case ISD::UMULO: 1518 if (Op.getResNo() != 1) 1519 return; 1520 // The boolean result conforms to getBooleanContents. Fall through. 1521 case ISD::SETCC: 1522 // If we know the result of a setcc has the top bits zero, use this info. 1523 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1524 BitWidth > 1) 1525 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1526 return; 1527 case ISD::SHL: 1528 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1529 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1530 unsigned ShAmt = SA->getZExtValue(); 1531 1532 // If the shift count is an invalid immediate, don't do anything. 1533 if (ShAmt >= BitWidth) 1534 return; 1535 1536 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1537 KnownZero, KnownOne, Depth+1); 1538 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1539 KnownZero <<= ShAmt; 1540 KnownOne <<= ShAmt; 1541 // low bits known zero. 1542 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1543 } 1544 return; 1545 case ISD::SRL: 1546 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1547 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1548 unsigned ShAmt = SA->getZExtValue(); 1549 1550 // If the shift count is an invalid immediate, don't do anything. 1551 if (ShAmt >= BitWidth) 1552 return; 1553 1554 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1555 KnownZero, KnownOne, Depth+1); 1556 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1557 KnownZero = KnownZero.lshr(ShAmt); 1558 KnownOne = KnownOne.lshr(ShAmt); 1559 1560 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1561 KnownZero |= HighBits; // High bits known zero. 1562 } 1563 return; 1564 case ISD::SRA: 1565 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1566 unsigned ShAmt = SA->getZExtValue(); 1567 1568 // If the shift count is an invalid immediate, don't do anything. 1569 if (ShAmt >= BitWidth) 1570 return; 1571 1572 APInt InDemandedMask = (Mask << ShAmt); 1573 // If any of the demanded bits are produced by the sign extension, we also 1574 // demand the input sign bit. 1575 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1576 if (HighBits.getBoolValue()) 1577 InDemandedMask |= APInt::getSignBit(BitWidth); 1578 1579 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1580 Depth+1); 1581 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1582 KnownZero = KnownZero.lshr(ShAmt); 1583 KnownOne = KnownOne.lshr(ShAmt); 1584 1585 // Handle the sign bits. 1586 APInt SignBit = APInt::getSignBit(BitWidth); 1587 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1588 1589 if (KnownZero.intersects(SignBit)) { 1590 KnownZero |= HighBits; // New bits are known zero. 1591 } else if (KnownOne.intersects(SignBit)) { 1592 KnownOne |= HighBits; // New bits are known one. 1593 } 1594 } 1595 return; 1596 case ISD::SIGN_EXTEND_INREG: { 1597 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1598 unsigned EBits = EVT.getSizeInBits(); 1599 1600 // Sign extension. Compute the demanded bits in the result that are not 1601 // present in the input. 1602 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1603 1604 APInt InSignBit = APInt::getSignBit(EBits); 1605 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1606 1607 // If the sign extended bits are demanded, we know that the sign 1608 // bit is demanded. 1609 InSignBit.zext(BitWidth); 1610 if (NewBits.getBoolValue()) 1611 InputDemandedBits |= InSignBit; 1612 1613 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1614 KnownZero, KnownOne, Depth+1); 1615 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1616 1617 // If the sign bit of the input is known set or clear, then we know the 1618 // top bits of the result. 1619 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1620 KnownZero |= NewBits; 1621 KnownOne &= ~NewBits; 1622 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1623 KnownOne |= NewBits; 1624 KnownZero &= ~NewBits; 1625 } else { // Input sign bit unknown 1626 KnownZero &= ~NewBits; 1627 KnownOne &= ~NewBits; 1628 } 1629 return; 1630 } 1631 case ISD::CTTZ: 1632 case ISD::CTLZ: 1633 case ISD::CTPOP: { 1634 unsigned LowBits = Log2_32(BitWidth)+1; 1635 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1636 KnownOne.clear(); 1637 return; 1638 } 1639 case ISD::LOAD: { 1640 if (ISD::isZEXTLoad(Op.getNode())) { 1641 LoadSDNode *LD = cast<LoadSDNode>(Op); 1642 MVT VT = LD->getMemoryVT(); 1643 unsigned MemBits = VT.getSizeInBits(); 1644 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1645 } 1646 return; 1647 } 1648 case ISD::ZERO_EXTEND: { 1649 MVT InVT = Op.getOperand(0).getValueType(); 1650 unsigned InBits = InVT.getSizeInBits(); 1651 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1652 APInt InMask = Mask; 1653 InMask.trunc(InBits); 1654 KnownZero.trunc(InBits); 1655 KnownOne.trunc(InBits); 1656 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1657 KnownZero.zext(BitWidth); 1658 KnownOne.zext(BitWidth); 1659 KnownZero |= NewBits; 1660 return; 1661 } 1662 case ISD::SIGN_EXTEND: { 1663 MVT InVT = Op.getOperand(0).getValueType(); 1664 unsigned InBits = InVT.getSizeInBits(); 1665 APInt InSignBit = APInt::getSignBit(InBits); 1666 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1667 APInt InMask = Mask; 1668 InMask.trunc(InBits); 1669 1670 // If any of the sign extended bits are demanded, we know that the sign 1671 // bit is demanded. Temporarily set this bit in the mask for our callee. 1672 if (NewBits.getBoolValue()) 1673 InMask |= InSignBit; 1674 1675 KnownZero.trunc(InBits); 1676 KnownOne.trunc(InBits); 1677 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1678 1679 // Note if the sign bit is known to be zero or one. 1680 bool SignBitKnownZero = KnownZero.isNegative(); 1681 bool SignBitKnownOne = KnownOne.isNegative(); 1682 assert(!(SignBitKnownZero && SignBitKnownOne) && 1683 "Sign bit can't be known to be both zero and one!"); 1684 1685 // If the sign bit wasn't actually demanded by our caller, we don't 1686 // want it set in the KnownZero and KnownOne result values. Reset the 1687 // mask and reapply it to the result values. 1688 InMask = Mask; 1689 InMask.trunc(InBits); 1690 KnownZero &= InMask; 1691 KnownOne &= InMask; 1692 1693 KnownZero.zext(BitWidth); 1694 KnownOne.zext(BitWidth); 1695 1696 // If the sign bit is known zero or one, the top bits match. 1697 if (SignBitKnownZero) 1698 KnownZero |= NewBits; 1699 else if (SignBitKnownOne) 1700 KnownOne |= NewBits; 1701 return; 1702 } 1703 case ISD::ANY_EXTEND: { 1704 MVT InVT = Op.getOperand(0).getValueType(); 1705 unsigned InBits = InVT.getSizeInBits(); 1706 APInt InMask = Mask; 1707 InMask.trunc(InBits); 1708 KnownZero.trunc(InBits); 1709 KnownOne.trunc(InBits); 1710 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1711 KnownZero.zext(BitWidth); 1712 KnownOne.zext(BitWidth); 1713 return; 1714 } 1715 case ISD::TRUNCATE: { 1716 MVT InVT = Op.getOperand(0).getValueType(); 1717 unsigned InBits = InVT.getSizeInBits(); 1718 APInt InMask = Mask; 1719 InMask.zext(InBits); 1720 KnownZero.zext(InBits); 1721 KnownOne.zext(InBits); 1722 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1723 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1724 KnownZero.trunc(BitWidth); 1725 KnownOne.trunc(BitWidth); 1726 break; 1727 } 1728 case ISD::AssertZext: { 1729 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1730 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1731 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1732 KnownOne, Depth+1); 1733 KnownZero |= (~InMask) & Mask; 1734 return; 1735 } 1736 case ISD::FGETSIGN: 1737 // All bits are zero except the low bit. 1738 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1739 return; 1740 1741 case ISD::SUB: { 1742 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1743 // We know that the top bits of C-X are clear if X contains less bits 1744 // than C (i.e. no wrap-around can happen). For example, 20-X is 1745 // positive if we can prove that X is >= 0 and < 16. 1746 if (CLHS->getAPIntValue().isNonNegative()) { 1747 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1748 // NLZ can't be BitWidth with no sign bit 1749 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1750 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1751 Depth+1); 1752 1753 // If all of the MaskV bits are known to be zero, then we know the 1754 // output top bits are zero, because we now know that the output is 1755 // from [0-C]. 1756 if ((KnownZero2 & MaskV) == MaskV) { 1757 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1758 // Top bits known zero. 1759 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1760 } 1761 } 1762 } 1763 } 1764 // fall through 1765 case ISD::ADD: { 1766 // Output known-0 bits are known if clear or set in both the low clear bits 1767 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1768 // low 3 bits clear. 1769 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1770 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1771 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1772 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1773 1774 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1775 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1776 KnownZeroOut = std::min(KnownZeroOut, 1777 KnownZero2.countTrailingOnes()); 1778 1779 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1780 return; 1781 } 1782 case ISD::SREM: 1783 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1784 const APInt &RA = Rem->getAPIntValue(); 1785 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1786 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1787 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1788 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1789 1790 // If the sign bit of the first operand is zero, the sign bit of 1791 // the result is zero. If the first operand has no one bits below 1792 // the second operand's single 1 bit, its sign will be zero. 1793 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1794 KnownZero2 |= ~LowBits; 1795 1796 KnownZero |= KnownZero2 & Mask; 1797 1798 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1799 } 1800 } 1801 return; 1802 case ISD::UREM: { 1803 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1804 const APInt &RA = Rem->getAPIntValue(); 1805 if (RA.isPowerOf2()) { 1806 APInt LowBits = (RA - 1); 1807 APInt Mask2 = LowBits & Mask; 1808 KnownZero |= ~LowBits & Mask; 1809 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1810 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1811 break; 1812 } 1813 } 1814 1815 // Since the result is less than or equal to either operand, any leading 1816 // zero bits in either operand must also exist in the result. 1817 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1818 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1819 Depth+1); 1820 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1821 Depth+1); 1822 1823 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1824 KnownZero2.countLeadingOnes()); 1825 KnownOne.clear(); 1826 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1827 return; 1828 } 1829 default: 1830 // Allow the target to implement this method for its nodes. 1831 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1832 case ISD::INTRINSIC_WO_CHAIN: 1833 case ISD::INTRINSIC_W_CHAIN: 1834 case ISD::INTRINSIC_VOID: 1835 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1836 } 1837 return; 1838 } 1839} 1840 1841/// ComputeNumSignBits - Return the number of times the sign bit of the 1842/// register is replicated into the other bits. We know that at least 1 bit 1843/// is always equal to the sign bit (itself), but other cases can give us 1844/// information. For example, immediately after an "SRA X, 2", we know that 1845/// the top 3 bits are all equal to each other, so we return 3. 1846unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1847 MVT VT = Op.getValueType(); 1848 assert(VT.isInteger() && "Invalid VT!"); 1849 unsigned VTBits = VT.getSizeInBits(); 1850 unsigned Tmp, Tmp2; 1851 unsigned FirstAnswer = 1; 1852 1853 if (Depth == 6) 1854 return 1; // Limit search depth. 1855 1856 switch (Op.getOpcode()) { 1857 default: break; 1858 case ISD::AssertSext: 1859 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1860 return VTBits-Tmp+1; 1861 case ISD::AssertZext: 1862 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1863 return VTBits-Tmp; 1864 1865 case ISD::Constant: { 1866 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1867 // If negative, return # leading ones. 1868 if (Val.isNegative()) 1869 return Val.countLeadingOnes(); 1870 1871 // Return # leading zeros. 1872 return Val.countLeadingZeros(); 1873 } 1874 1875 case ISD::SIGN_EXTEND: 1876 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1877 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1878 1879 case ISD::SIGN_EXTEND_INREG: 1880 // Max of the input and what this extends. 1881 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1882 Tmp = VTBits-Tmp+1; 1883 1884 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1885 return std::max(Tmp, Tmp2); 1886 1887 case ISD::SRA: 1888 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1889 // SRA X, C -> adds C sign bits. 1890 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1891 Tmp += C->getZExtValue(); 1892 if (Tmp > VTBits) Tmp = VTBits; 1893 } 1894 return Tmp; 1895 case ISD::SHL: 1896 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1897 // shl destroys sign bits. 1898 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1899 if (C->getZExtValue() >= VTBits || // Bad shift. 1900 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 1901 return Tmp - C->getZExtValue(); 1902 } 1903 break; 1904 case ISD::AND: 1905 case ISD::OR: 1906 case ISD::XOR: // NOT is handled here. 1907 // Logical binary ops preserve the number of sign bits at the worst. 1908 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1909 if (Tmp != 1) { 1910 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1911 FirstAnswer = std::min(Tmp, Tmp2); 1912 // We computed what we know about the sign bits as our first 1913 // answer. Now proceed to the generic code that uses 1914 // ComputeMaskedBits, and pick whichever answer is better. 1915 } 1916 break; 1917 1918 case ISD::SELECT: 1919 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1920 if (Tmp == 1) return 1; // Early out. 1921 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1922 return std::min(Tmp, Tmp2); 1923 1924 case ISD::SADDO: 1925 case ISD::UADDO: 1926 case ISD::SSUBO: 1927 case ISD::USUBO: 1928 case ISD::SMULO: 1929 case ISD::UMULO: 1930 if (Op.getResNo() != 1) 1931 break; 1932 // The boolean result conforms to getBooleanContents. Fall through. 1933 case ISD::SETCC: 1934 // If setcc returns 0/-1, all bits are sign bits. 1935 if (TLI.getBooleanContents() == 1936 TargetLowering::ZeroOrNegativeOneBooleanContent) 1937 return VTBits; 1938 break; 1939 case ISD::ROTL: 1940 case ISD::ROTR: 1941 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1942 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 1943 1944 // Handle rotate right by N like a rotate left by 32-N. 1945 if (Op.getOpcode() == ISD::ROTR) 1946 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1947 1948 // If we aren't rotating out all of the known-in sign bits, return the 1949 // number that are left. This handles rotl(sext(x), 1) for example. 1950 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1951 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1952 } 1953 break; 1954 case ISD::ADD: 1955 // Add can have at most one carry bit. Thus we know that the output 1956 // is, at worst, one more bit than the inputs. 1957 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1958 if (Tmp == 1) return 1; // Early out. 1959 1960 // Special case decrementing a value (ADD X, -1): 1961 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1962 if (CRHS->isAllOnesValue()) { 1963 APInt KnownZero, KnownOne; 1964 APInt Mask = APInt::getAllOnesValue(VTBits); 1965 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1966 1967 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1968 // sign bits set. 1969 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1970 return VTBits; 1971 1972 // If we are subtracting one from a positive number, there is no carry 1973 // out of the result. 1974 if (KnownZero.isNegative()) 1975 return Tmp; 1976 } 1977 1978 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1979 if (Tmp2 == 1) return 1; 1980 return std::min(Tmp, Tmp2)-1; 1981 break; 1982 1983 case ISD::SUB: 1984 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1985 if (Tmp2 == 1) return 1; 1986 1987 // Handle NEG. 1988 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1989 if (CLHS->isNullValue()) { 1990 APInt KnownZero, KnownOne; 1991 APInt Mask = APInt::getAllOnesValue(VTBits); 1992 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1993 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1994 // sign bits set. 1995 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1996 return VTBits; 1997 1998 // If the input is known to be positive (the sign bit is known clear), 1999 // the output of the NEG has the same number of sign bits as the input. 2000 if (KnownZero.isNegative()) 2001 return Tmp2; 2002 2003 // Otherwise, we treat this like a SUB. 2004 } 2005 2006 // Sub can have at most one carry bit. Thus we know that the output 2007 // is, at worst, one more bit than the inputs. 2008 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2009 if (Tmp == 1) return 1; // Early out. 2010 return std::min(Tmp, Tmp2)-1; 2011 break; 2012 case ISD::TRUNCATE: 2013 // FIXME: it's tricky to do anything useful for this, but it is an important 2014 // case for targets like X86. 2015 break; 2016 } 2017 2018 // Handle LOADX separately here. EXTLOAD case will fallthrough. 2019 if (Op.getOpcode() == ISD::LOAD) { 2020 LoadSDNode *LD = cast<LoadSDNode>(Op); 2021 unsigned ExtType = LD->getExtensionType(); 2022 switch (ExtType) { 2023 default: break; 2024 case ISD::SEXTLOAD: // '17' bits known 2025 Tmp = LD->getMemoryVT().getSizeInBits(); 2026 return VTBits-Tmp+1; 2027 case ISD::ZEXTLOAD: // '16' bits known 2028 Tmp = LD->getMemoryVT().getSizeInBits(); 2029 return VTBits-Tmp; 2030 } 2031 } 2032 2033 // Allow the target to implement this method for its nodes. 2034 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2035 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2036 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2037 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2038 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2039 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2040 } 2041 2042 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2043 // use this information. 2044 APInt KnownZero, KnownOne; 2045 APInt Mask = APInt::getAllOnesValue(VTBits); 2046 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2047 2048 if (KnownZero.isNegative()) { // sign bit is 0 2049 Mask = KnownZero; 2050 } else if (KnownOne.isNegative()) { // sign bit is 1; 2051 Mask = KnownOne; 2052 } else { 2053 // Nothing known. 2054 return FirstAnswer; 2055 } 2056 2057 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2058 // the number of identical bits in the top of the input value. 2059 Mask = ~Mask; 2060 Mask <<= Mask.getBitWidth()-VTBits; 2061 // Return # leading zeros. We use 'min' here in case Val was zero before 2062 // shifting. We don't want to return '64' as for an i32 "0". 2063 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2064} 2065 2066 2067bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2068 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2069 if (!GA) return false; 2070 if (GA->getOffset() != 0) return false; 2071 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2072 if (!GV) return false; 2073 MachineModuleInfo *MMI = getMachineModuleInfo(); 2074 return MMI && MMI->hasDebugInfo() && MMI->isVerified(GV); 2075} 2076 2077 2078/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2079/// element of the result of the vector shuffle. 2080SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 2081 MVT VT = N->getValueType(0); 2082 SDValue PermMask = N->getOperand(2); 2083 SDValue Idx = PermMask.getOperand(i); 2084 if (Idx.getOpcode() == ISD::UNDEF) 2085 return getNode(ISD::UNDEF, VT.getVectorElementType()); 2086 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 2087 unsigned NumElems = PermMask.getNumOperands(); 2088 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2089 Index %= NumElems; 2090 2091 if (V.getOpcode() == ISD::BIT_CONVERT) { 2092 V = V.getOperand(0); 2093 MVT VVT = V.getValueType(); 2094 if (!VVT.isVector() || VVT.getVectorNumElements() != NumElems) 2095 return SDValue(); 2096 } 2097 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2098 return (Index == 0) ? V.getOperand(0) 2099 : getNode(ISD::UNDEF, VT.getVectorElementType()); 2100 if (V.getOpcode() == ISD::BUILD_VECTOR) 2101 return V.getOperand(Index); 2102 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 2103 return getShuffleScalarElt(V.getNode(), Index); 2104 return SDValue(); 2105} 2106 2107 2108/// getNode - Gets or creates the specified node. 2109/// 2110SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) { 2111 FoldingSetNodeID ID; 2112 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2113 void *IP = 0; 2114 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2115 return SDValue(E, 0); 2116 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2117 new (N) SDNode(Opcode, SDNode::getSDVTList(VT)); 2118 CSEMap.InsertNode(N, IP); 2119 2120 AllNodes.push_back(N); 2121#ifndef NDEBUG 2122 VerifyNode(N); 2123#endif 2124 return SDValue(N, 0); 2125} 2126 2127SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) { 2128 // Constant fold unary operations with an integer constant operand. 2129 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2130 const APInt &Val = C->getAPIntValue(); 2131 unsigned BitWidth = VT.getSizeInBits(); 2132 switch (Opcode) { 2133 default: break; 2134 case ISD::SIGN_EXTEND: 2135 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2136 case ISD::ANY_EXTEND: 2137 case ISD::ZERO_EXTEND: 2138 case ISD::TRUNCATE: 2139 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2140 case ISD::UINT_TO_FP: 2141 case ISD::SINT_TO_FP: { 2142 const uint64_t zero[] = {0, 0}; 2143 // No compile time operations on this type. 2144 if (VT==MVT::ppcf128) 2145 break; 2146 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2147 (void)apf.convertFromAPInt(Val, 2148 Opcode==ISD::SINT_TO_FP, 2149 APFloat::rmNearestTiesToEven); 2150 return getConstantFP(apf, VT); 2151 } 2152 case ISD::BIT_CONVERT: 2153 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2154 return getConstantFP(Val.bitsToFloat(), VT); 2155 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2156 return getConstantFP(Val.bitsToDouble(), VT); 2157 break; 2158 case ISD::BSWAP: 2159 return getConstant(Val.byteSwap(), VT); 2160 case ISD::CTPOP: 2161 return getConstant(Val.countPopulation(), VT); 2162 case ISD::CTLZ: 2163 return getConstant(Val.countLeadingZeros(), VT); 2164 case ISD::CTTZ: 2165 return getConstant(Val.countTrailingZeros(), VT); 2166 } 2167 } 2168 2169 // Constant fold unary operations with a floating point constant operand. 2170 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2171 APFloat V = C->getValueAPF(); // make copy 2172 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2173 switch (Opcode) { 2174 case ISD::FNEG: 2175 V.changeSign(); 2176 return getConstantFP(V, VT); 2177 case ISD::FABS: 2178 V.clearSign(); 2179 return getConstantFP(V, VT); 2180 case ISD::FP_ROUND: 2181 case ISD::FP_EXTEND: { 2182 bool ignored; 2183 // This can return overflow, underflow, or inexact; we don't care. 2184 // FIXME need to be more flexible about rounding mode. 2185 (void)V.convert(*MVTToAPFloatSemantics(VT), 2186 APFloat::rmNearestTiesToEven, &ignored); 2187 return getConstantFP(V, VT); 2188 } 2189 case ISD::FP_TO_SINT: 2190 case ISD::FP_TO_UINT: { 2191 integerPart x; 2192 bool ignored; 2193 assert(integerPartWidth >= 64); 2194 // FIXME need to be more flexible about rounding mode. 2195 APFloat::opStatus s = V.convertToInteger(&x, 64U, 2196 Opcode==ISD::FP_TO_SINT, 2197 APFloat::rmTowardZero, &ignored); 2198 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2199 break; 2200 return getConstant(x, VT); 2201 } 2202 case ISD::BIT_CONVERT: 2203 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2204 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2205 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2206 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2207 break; 2208 } 2209 } 2210 } 2211 2212 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2213 switch (Opcode) { 2214 case ISD::TokenFactor: 2215 case ISD::MERGE_VALUES: 2216 case ISD::CONCAT_VECTORS: 2217 return Operand; // Factor, merge or concat of one node? No need. 2218 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2219 case ISD::FP_EXTEND: 2220 assert(VT.isFloatingPoint() && 2221 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2222 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2223 if (Operand.getOpcode() == ISD::UNDEF) 2224 return getNode(ISD::UNDEF, VT); 2225 break; 2226 case ISD::SIGN_EXTEND: 2227 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2228 "Invalid SIGN_EXTEND!"); 2229 if (Operand.getValueType() == VT) return Operand; // noop extension 2230 assert(Operand.getValueType().bitsLT(VT) 2231 && "Invalid sext node, dst < src!"); 2232 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2233 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2234 break; 2235 case ISD::ZERO_EXTEND: 2236 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2237 "Invalid ZERO_EXTEND!"); 2238 if (Operand.getValueType() == VT) return Operand; // noop extension 2239 assert(Operand.getValueType().bitsLT(VT) 2240 && "Invalid zext node, dst < src!"); 2241 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2242 return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()->getOperand(0)); 2243 break; 2244 case ISD::ANY_EXTEND: 2245 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2246 "Invalid ANY_EXTEND!"); 2247 if (Operand.getValueType() == VT) return Operand; // noop extension 2248 assert(Operand.getValueType().bitsLT(VT) 2249 && "Invalid anyext node, dst < src!"); 2250 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2251 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2252 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2253 break; 2254 case ISD::TRUNCATE: 2255 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2256 "Invalid TRUNCATE!"); 2257 if (Operand.getValueType() == VT) return Operand; // noop truncate 2258 assert(Operand.getValueType().bitsGT(VT) 2259 && "Invalid truncate node, src < dst!"); 2260 if (OpOpcode == ISD::TRUNCATE) 2261 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2262 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2263 OpOpcode == ISD::ANY_EXTEND) { 2264 // If the source is smaller than the dest, we still need an extend. 2265 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2266 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2267 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2268 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2269 else 2270 return Operand.getNode()->getOperand(0); 2271 } 2272 break; 2273 case ISD::BIT_CONVERT: 2274 // Basic sanity checking. 2275 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2276 && "Cannot BIT_CONVERT between types of different sizes!"); 2277 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2278 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2279 return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0)); 2280 if (OpOpcode == ISD::UNDEF) 2281 return getNode(ISD::UNDEF, VT); 2282 break; 2283 case ISD::SCALAR_TO_VECTOR: 2284 assert(VT.isVector() && !Operand.getValueType().isVector() && 2285 VT.getVectorElementType() == Operand.getValueType() && 2286 "Illegal SCALAR_TO_VECTOR node!"); 2287 if (OpOpcode == ISD::UNDEF) 2288 return getNode(ISD::UNDEF, VT); 2289 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2290 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2291 isa<ConstantSDNode>(Operand.getOperand(1)) && 2292 Operand.getConstantOperandVal(1) == 0 && 2293 Operand.getOperand(0).getValueType() == VT) 2294 return Operand.getOperand(0); 2295 break; 2296 case ISD::FNEG: 2297 if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X) 2298 return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1), 2299 Operand.getNode()->getOperand(0)); 2300 if (OpOpcode == ISD::FNEG) // --X -> X 2301 return Operand.getNode()->getOperand(0); 2302 break; 2303 case ISD::FABS: 2304 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2305 return getNode(ISD::FABS, VT, Operand.getNode()->getOperand(0)); 2306 break; 2307 } 2308 2309 SDNode *N; 2310 SDVTList VTs = getVTList(VT); 2311 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2312 FoldingSetNodeID ID; 2313 SDValue Ops[1] = { Operand }; 2314 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2315 void *IP = 0; 2316 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2317 return SDValue(E, 0); 2318 N = NodeAllocator.Allocate<UnarySDNode>(); 2319 new (N) UnarySDNode(Opcode, VTs, Operand); 2320 CSEMap.InsertNode(N, IP); 2321 } else { 2322 N = NodeAllocator.Allocate<UnarySDNode>(); 2323 new (N) UnarySDNode(Opcode, VTs, Operand); 2324 } 2325 2326 AllNodes.push_back(N); 2327#ifndef NDEBUG 2328 VerifyNode(N); 2329#endif 2330 return SDValue(N, 0); 2331} 2332 2333SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2334 MVT VT, 2335 ConstantSDNode *Cst1, 2336 ConstantSDNode *Cst2) { 2337 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2338 2339 switch (Opcode) { 2340 case ISD::ADD: return getConstant(C1 + C2, VT); 2341 case ISD::SUB: return getConstant(C1 - C2, VT); 2342 case ISD::MUL: return getConstant(C1 * C2, VT); 2343 case ISD::UDIV: 2344 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2345 break; 2346 case ISD::UREM: 2347 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2348 break; 2349 case ISD::SDIV: 2350 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2351 break; 2352 case ISD::SREM: 2353 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2354 break; 2355 case ISD::AND: return getConstant(C1 & C2, VT); 2356 case ISD::OR: return getConstant(C1 | C2, VT); 2357 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2358 case ISD::SHL: return getConstant(C1 << C2, VT); 2359 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2360 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2361 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2362 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2363 default: break; 2364 } 2365 2366 return SDValue(); 2367} 2368 2369SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2370 SDValue N1, SDValue N2) { 2371 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2372 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2373 switch (Opcode) { 2374 default: break; 2375 case ISD::TokenFactor: 2376 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2377 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2378 // Fold trivial token factors. 2379 if (N1.getOpcode() == ISD::EntryToken) return N2; 2380 if (N2.getOpcode() == ISD::EntryToken) return N1; 2381 if (N1 == N2) return N1; 2382 break; 2383 case ISD::CONCAT_VECTORS: 2384 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2385 // one big BUILD_VECTOR. 2386 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2387 N2.getOpcode() == ISD::BUILD_VECTOR) { 2388 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2389 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2390 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2391 } 2392 break; 2393 case ISD::AND: 2394 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2395 N1.getValueType() == VT && "Binary operator types must match!"); 2396 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2397 // worth handling here. 2398 if (N2C && N2C->isNullValue()) 2399 return N2; 2400 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2401 return N1; 2402 break; 2403 case ISD::OR: 2404 case ISD::XOR: 2405 case ISD::ADD: 2406 case ISD::SUB: 2407 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2408 N1.getValueType() == VT && "Binary operator types must match!"); 2409 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2410 // it's worth handling here. 2411 if (N2C && N2C->isNullValue()) 2412 return N1; 2413 break; 2414 case ISD::UDIV: 2415 case ISD::UREM: 2416 case ISD::MULHU: 2417 case ISD::MULHS: 2418 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2419 // fall through 2420 case ISD::MUL: 2421 case ISD::SDIV: 2422 case ISD::SREM: 2423 case ISD::FADD: 2424 case ISD::FSUB: 2425 case ISD::FMUL: 2426 case ISD::FDIV: 2427 case ISD::FREM: 2428 assert(N1.getValueType() == N2.getValueType() && 2429 N1.getValueType() == VT && "Binary operator types must match!"); 2430 break; 2431 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2432 assert(N1.getValueType() == VT && 2433 N1.getValueType().isFloatingPoint() && 2434 N2.getValueType().isFloatingPoint() && 2435 "Invalid FCOPYSIGN!"); 2436 break; 2437 case ISD::SHL: 2438 case ISD::SRA: 2439 case ISD::SRL: 2440 case ISD::ROTL: 2441 case ISD::ROTR: 2442 assert(VT == N1.getValueType() && 2443 "Shift operators return type must be the same as their first arg"); 2444 assert(VT.isInteger() && N2.getValueType().isInteger() && 2445 "Shifts only work on integers"); 2446 assert((N2.getValueType() == TLI.getShiftAmountTy() || 2447 (N2.getValueType().isVector() && N2.getValueType().isInteger())) && 2448 "Wrong type for shift amount"); 2449 2450 // Always fold shifts of i1 values so the code generator doesn't need to 2451 // handle them. Since we know the size of the shift has to be less than the 2452 // size of the value, the shift/rotate count is guaranteed to be zero. 2453 if (VT == MVT::i1) 2454 return N1; 2455 break; 2456 case ISD::FP_ROUND_INREG: { 2457 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2458 assert(VT == N1.getValueType() && "Not an inreg round!"); 2459 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2460 "Cannot FP_ROUND_INREG integer types"); 2461 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2462 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2463 break; 2464 } 2465 case ISD::FP_ROUND: 2466 assert(VT.isFloatingPoint() && 2467 N1.getValueType().isFloatingPoint() && 2468 VT.bitsLE(N1.getValueType()) && 2469 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2470 if (N1.getValueType() == VT) return N1; // noop conversion. 2471 break; 2472 case ISD::AssertSext: 2473 case ISD::AssertZext: { 2474 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2475 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2476 assert(VT.isInteger() && EVT.isInteger() && 2477 "Cannot *_EXTEND_INREG FP types"); 2478 assert(EVT.bitsLE(VT) && "Not extending!"); 2479 if (VT == EVT) return N1; // noop assertion. 2480 break; 2481 } 2482 case ISD::SIGN_EXTEND_INREG: { 2483 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2484 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2485 assert(VT.isInteger() && EVT.isInteger() && 2486 "Cannot *_EXTEND_INREG FP types"); 2487 assert(EVT.bitsLE(VT) && "Not extending!"); 2488 if (EVT == VT) return N1; // Not actually extending 2489 2490 if (N1C) { 2491 APInt Val = N1C->getAPIntValue(); 2492 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2493 Val <<= Val.getBitWidth()-FromBits; 2494 Val = Val.ashr(Val.getBitWidth()-FromBits); 2495 return getConstant(Val, VT); 2496 } 2497 break; 2498 } 2499 case ISD::EXTRACT_VECTOR_ELT: 2500 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2501 if (N1.getOpcode() == ISD::UNDEF) 2502 return getNode(ISD::UNDEF, VT); 2503 2504 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2505 // expanding copies of large vectors from registers. 2506 if (N2C && 2507 N1.getOpcode() == ISD::CONCAT_VECTORS && 2508 N1.getNumOperands() > 0) { 2509 unsigned Factor = 2510 N1.getOperand(0).getValueType().getVectorNumElements(); 2511 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, 2512 N1.getOperand(N2C->getZExtValue() / Factor), 2513 getConstant(N2C->getZExtValue() % Factor, 2514 N2.getValueType())); 2515 } 2516 2517 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2518 // expanding large vector constants. 2519 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) 2520 return N1.getOperand(N2C->getZExtValue()); 2521 2522 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2523 // operations are lowered to scalars. 2524 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2525 if (N1.getOperand(2) == N2) 2526 return N1.getOperand(1); 2527 else 2528 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2); 2529 } 2530 break; 2531 case ISD::EXTRACT_ELEMENT: 2532 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2533 assert(!N1.getValueType().isVector() && !VT.isVector() && 2534 (N1.getValueType().isInteger() == VT.isInteger()) && 2535 "Wrong types for EXTRACT_ELEMENT!"); 2536 2537 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2538 // 64-bit integers into 32-bit parts. Instead of building the extract of 2539 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2540 if (N1.getOpcode() == ISD::BUILD_PAIR) 2541 return N1.getOperand(N2C->getZExtValue()); 2542 2543 // EXTRACT_ELEMENT of a constant int is also very common. 2544 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2545 unsigned ElementSize = VT.getSizeInBits(); 2546 unsigned Shift = ElementSize * N2C->getZExtValue(); 2547 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2548 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2549 } 2550 break; 2551 case ISD::EXTRACT_SUBVECTOR: 2552 if (N1.getValueType() == VT) // Trivial extraction. 2553 return N1; 2554 break; 2555 } 2556 2557 if (N1C) { 2558 if (N2C) { 2559 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2560 if (SV.getNode()) return SV; 2561 } else { // Cannonicalize constant to RHS if commutative 2562 if (isCommutativeBinOp(Opcode)) { 2563 std::swap(N1C, N2C); 2564 std::swap(N1, N2); 2565 } 2566 } 2567 } 2568 2569 // Constant fold FP operations. 2570 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2571 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2572 if (N1CFP) { 2573 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2574 // Cannonicalize constant to RHS if commutative 2575 std::swap(N1CFP, N2CFP); 2576 std::swap(N1, N2); 2577 } else if (N2CFP && VT != MVT::ppcf128) { 2578 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2579 APFloat::opStatus s; 2580 switch (Opcode) { 2581 case ISD::FADD: 2582 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2583 if (s != APFloat::opInvalidOp) 2584 return getConstantFP(V1, VT); 2585 break; 2586 case ISD::FSUB: 2587 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2588 if (s!=APFloat::opInvalidOp) 2589 return getConstantFP(V1, VT); 2590 break; 2591 case ISD::FMUL: 2592 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2593 if (s!=APFloat::opInvalidOp) 2594 return getConstantFP(V1, VT); 2595 break; 2596 case ISD::FDIV: 2597 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2598 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2599 return getConstantFP(V1, VT); 2600 break; 2601 case ISD::FREM : 2602 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2603 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2604 return getConstantFP(V1, VT); 2605 break; 2606 case ISD::FCOPYSIGN: 2607 V1.copySign(V2); 2608 return getConstantFP(V1, VT); 2609 default: break; 2610 } 2611 } 2612 } 2613 2614 // Canonicalize an UNDEF to the RHS, even over a constant. 2615 if (N1.getOpcode() == ISD::UNDEF) { 2616 if (isCommutativeBinOp(Opcode)) { 2617 std::swap(N1, N2); 2618 } else { 2619 switch (Opcode) { 2620 case ISD::FP_ROUND_INREG: 2621 case ISD::SIGN_EXTEND_INREG: 2622 case ISD::SUB: 2623 case ISD::FSUB: 2624 case ISD::FDIV: 2625 case ISD::FREM: 2626 case ISD::SRA: 2627 return N1; // fold op(undef, arg2) -> undef 2628 case ISD::UDIV: 2629 case ISD::SDIV: 2630 case ISD::UREM: 2631 case ISD::SREM: 2632 case ISD::SRL: 2633 case ISD::SHL: 2634 if (!VT.isVector()) 2635 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2636 // For vectors, we can't easily build an all zero vector, just return 2637 // the LHS. 2638 return N2; 2639 } 2640 } 2641 } 2642 2643 // Fold a bunch of operators when the RHS is undef. 2644 if (N2.getOpcode() == ISD::UNDEF) { 2645 switch (Opcode) { 2646 case ISD::XOR: 2647 if (N1.getOpcode() == ISD::UNDEF) 2648 // Handle undef ^ undef -> 0 special case. This is a common 2649 // idiom (misuse). 2650 return getConstant(0, VT); 2651 // fallthrough 2652 case ISD::ADD: 2653 case ISD::ADDC: 2654 case ISD::ADDE: 2655 case ISD::SUB: 2656 case ISD::FADD: 2657 case ISD::FSUB: 2658 case ISD::FMUL: 2659 case ISD::FDIV: 2660 case ISD::FREM: 2661 case ISD::UDIV: 2662 case ISD::SDIV: 2663 case ISD::UREM: 2664 case ISD::SREM: 2665 return N2; // fold op(arg1, undef) -> undef 2666 case ISD::MUL: 2667 case ISD::AND: 2668 case ISD::SRL: 2669 case ISD::SHL: 2670 if (!VT.isVector()) 2671 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2672 // For vectors, we can't easily build an all zero vector, just return 2673 // the LHS. 2674 return N1; 2675 case ISD::OR: 2676 if (!VT.isVector()) 2677 return getConstant(VT.getIntegerVTBitMask(), VT); 2678 // For vectors, we can't easily build an all one vector, just return 2679 // the LHS. 2680 return N1; 2681 case ISD::SRA: 2682 return N1; 2683 } 2684 } 2685 2686 // Memoize this node if possible. 2687 SDNode *N; 2688 SDVTList VTs = getVTList(VT); 2689 if (VT != MVT::Flag) { 2690 SDValue Ops[] = { N1, N2 }; 2691 FoldingSetNodeID ID; 2692 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2693 void *IP = 0; 2694 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2695 return SDValue(E, 0); 2696 N = NodeAllocator.Allocate<BinarySDNode>(); 2697 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2698 CSEMap.InsertNode(N, IP); 2699 } else { 2700 N = NodeAllocator.Allocate<BinarySDNode>(); 2701 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2702 } 2703 2704 AllNodes.push_back(N); 2705#ifndef NDEBUG 2706 VerifyNode(N); 2707#endif 2708 return SDValue(N, 0); 2709} 2710 2711SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2712 SDValue N1, SDValue N2, SDValue N3) { 2713 // Perform various simplifications. 2714 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2715 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2716 switch (Opcode) { 2717 case ISD::CONCAT_VECTORS: 2718 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2719 // one big BUILD_VECTOR. 2720 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2721 N2.getOpcode() == ISD::BUILD_VECTOR && 2722 N3.getOpcode() == ISD::BUILD_VECTOR) { 2723 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2724 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2725 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2726 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2727 } 2728 break; 2729 case ISD::SETCC: { 2730 // Use FoldSetCC to simplify SETCC's. 2731 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 2732 if (Simp.getNode()) return Simp; 2733 break; 2734 } 2735 case ISD::SELECT: 2736 if (N1C) { 2737 if (N1C->getZExtValue()) 2738 return N2; // select true, X, Y -> X 2739 else 2740 return N3; // select false, X, Y -> Y 2741 } 2742 2743 if (N2 == N3) return N2; // select C, X, X -> X 2744 break; 2745 case ISD::BRCOND: 2746 if (N2C) { 2747 if (N2C->getZExtValue()) // Unconditional branch 2748 return getNode(ISD::BR, MVT::Other, N1, N3); 2749 else 2750 return N1; // Never-taken branch 2751 } 2752 break; 2753 case ISD::VECTOR_SHUFFLE: 2754 assert(N1.getValueType() == N2.getValueType() && 2755 N1.getValueType().isVector() && 2756 VT.isVector() && N3.getValueType().isVector() && 2757 N3.getOpcode() == ISD::BUILD_VECTOR && 2758 VT.getVectorNumElements() == N3.getNumOperands() && 2759 "Illegal VECTOR_SHUFFLE node!"); 2760 break; 2761 case ISD::BIT_CONVERT: 2762 // Fold bit_convert nodes from a type to themselves. 2763 if (N1.getValueType() == VT) 2764 return N1; 2765 break; 2766 } 2767 2768 // Memoize node if it doesn't produce a flag. 2769 SDNode *N; 2770 SDVTList VTs = getVTList(VT); 2771 if (VT != MVT::Flag) { 2772 SDValue Ops[] = { N1, N2, N3 }; 2773 FoldingSetNodeID ID; 2774 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2775 void *IP = 0; 2776 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2777 return SDValue(E, 0); 2778 N = NodeAllocator.Allocate<TernarySDNode>(); 2779 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2780 CSEMap.InsertNode(N, IP); 2781 } else { 2782 N = NodeAllocator.Allocate<TernarySDNode>(); 2783 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2784 } 2785 AllNodes.push_back(N); 2786#ifndef NDEBUG 2787 VerifyNode(N); 2788#endif 2789 return SDValue(N, 0); 2790} 2791 2792SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2793 SDValue N1, SDValue N2, SDValue N3, 2794 SDValue N4) { 2795 SDValue Ops[] = { N1, N2, N3, N4 }; 2796 return getNode(Opcode, VT, Ops, 4); 2797} 2798 2799SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2800 SDValue N1, SDValue N2, SDValue N3, 2801 SDValue N4, SDValue N5) { 2802 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2803 return getNode(Opcode, VT, Ops, 5); 2804} 2805 2806/// getMemsetValue - Vectorized representation of the memset value 2807/// operand. 2808static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) { 2809 unsigned NumBits = VT.isVector() ? 2810 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2811 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2812 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2813 unsigned Shift = 8; 2814 for (unsigned i = NumBits; i > 8; i >>= 1) { 2815 Val = (Val << Shift) | Val; 2816 Shift <<= 1; 2817 } 2818 if (VT.isInteger()) 2819 return DAG.getConstant(Val, VT); 2820 return DAG.getConstantFP(APFloat(Val), VT); 2821 } 2822 2823 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2824 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 2825 unsigned Shift = 8; 2826 for (unsigned i = NumBits; i > 8; i >>= 1) { 2827 Value = DAG.getNode(ISD::OR, VT, 2828 DAG.getNode(ISD::SHL, VT, Value, 2829 DAG.getConstant(Shift, 2830 TLI.getShiftAmountTy())), 2831 Value); 2832 Shift <<= 1; 2833 } 2834 2835 return Value; 2836} 2837 2838/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2839/// used when a memcpy is turned into a memset when the source is a constant 2840/// string ptr. 2841static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG, 2842 const TargetLowering &TLI, 2843 std::string &Str, unsigned Offset) { 2844 // Handle vector with all elements zero. 2845 if (Str.empty()) { 2846 if (VT.isInteger()) 2847 return DAG.getConstant(0, VT); 2848 unsigned NumElts = VT.getVectorNumElements(); 2849 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2850 return DAG.getNode(ISD::BIT_CONVERT, VT, 2851 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2852 } 2853 2854 assert(!VT.isVector() && "Can't handle vector type here!"); 2855 unsigned NumBits = VT.getSizeInBits(); 2856 unsigned MSB = NumBits / 8; 2857 uint64_t Val = 0; 2858 if (TLI.isLittleEndian()) 2859 Offset = Offset + MSB - 1; 2860 for (unsigned i = 0; i != MSB; ++i) { 2861 Val = (Val << 8) | (unsigned char)Str[Offset]; 2862 Offset += TLI.isLittleEndian() ? -1 : 1; 2863 } 2864 return DAG.getConstant(Val, VT); 2865} 2866 2867/// getMemBasePlusOffset - Returns base and offset node for the 2868/// 2869static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2870 SelectionDAG &DAG) { 2871 MVT VT = Base.getValueType(); 2872 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 2873} 2874 2875/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2876/// 2877static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2878 unsigned SrcDelta = 0; 2879 GlobalAddressSDNode *G = NULL; 2880 if (Src.getOpcode() == ISD::GlobalAddress) 2881 G = cast<GlobalAddressSDNode>(Src); 2882 else if (Src.getOpcode() == ISD::ADD && 2883 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2884 Src.getOperand(1).getOpcode() == ISD::Constant) { 2885 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2886 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 2887 } 2888 if (!G) 2889 return false; 2890 2891 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2892 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 2893 return true; 2894 2895 return false; 2896} 2897 2898/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2899/// to replace the memset / memcpy is below the threshold. It also returns the 2900/// types of the sequence of memory ops to perform memset / memcpy. 2901static 2902bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 2903 SDValue Dst, SDValue Src, 2904 unsigned Limit, uint64_t Size, unsigned &Align, 2905 std::string &Str, bool &isSrcStr, 2906 SelectionDAG &DAG, 2907 const TargetLowering &TLI) { 2908 isSrcStr = isMemSrcFromString(Src, Str); 2909 bool isSrcConst = isa<ConstantSDNode>(Src); 2910 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 2911 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 2912 if (VT != MVT::iAny) { 2913 unsigned NewAlign = (unsigned) 2914 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 2915 // If source is a string constant, this will require an unaligned load. 2916 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 2917 if (Dst.getOpcode() != ISD::FrameIndex) { 2918 // Can't change destination alignment. It requires a unaligned store. 2919 if (AllowUnalign) 2920 VT = MVT::iAny; 2921 } else { 2922 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 2923 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2924 if (MFI->isFixedObjectIndex(FI)) { 2925 // Can't change destination alignment. It requires a unaligned store. 2926 if (AllowUnalign) 2927 VT = MVT::iAny; 2928 } else { 2929 // Give the stack frame object a larger alignment if needed. 2930 if (MFI->getObjectAlignment(FI) < NewAlign) 2931 MFI->setObjectAlignment(FI, NewAlign); 2932 Align = NewAlign; 2933 } 2934 } 2935 } 2936 } 2937 2938 if (VT == MVT::iAny) { 2939 if (AllowUnalign) { 2940 VT = MVT::i64; 2941 } else { 2942 switch (Align & 7) { 2943 case 0: VT = MVT::i64; break; 2944 case 4: VT = MVT::i32; break; 2945 case 2: VT = MVT::i16; break; 2946 default: VT = MVT::i8; break; 2947 } 2948 } 2949 2950 MVT LVT = MVT::i64; 2951 while (!TLI.isTypeLegal(LVT)) 2952 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 2953 assert(LVT.isInteger()); 2954 2955 if (VT.bitsGT(LVT)) 2956 VT = LVT; 2957 } 2958 2959 unsigned NumMemOps = 0; 2960 while (Size != 0) { 2961 unsigned VTSize = VT.getSizeInBits() / 8; 2962 while (VTSize > Size) { 2963 // For now, only use non-vector load / store's for the left-over pieces. 2964 if (VT.isVector()) { 2965 VT = MVT::i64; 2966 while (!TLI.isTypeLegal(VT)) 2967 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2968 VTSize = VT.getSizeInBits() / 8; 2969 } else { 2970 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2971 VTSize >>= 1; 2972 } 2973 } 2974 2975 if (++NumMemOps > Limit) 2976 return false; 2977 MemOps.push_back(VT); 2978 Size -= VTSize; 2979 } 2980 2981 return true; 2982} 2983 2984static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, 2985 SDValue Chain, SDValue Dst, 2986 SDValue Src, uint64_t Size, 2987 unsigned Align, bool AlwaysInline, 2988 const Value *DstSV, uint64_t DstSVOff, 2989 const Value *SrcSV, uint64_t SrcSVOff){ 2990 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2991 2992 // Expand memcpy to a series of load and store ops if the size operand falls 2993 // below a certain threshold. 2994 std::vector<MVT> MemOps; 2995 uint64_t Limit = -1ULL; 2996 if (!AlwaysInline) 2997 Limit = TLI.getMaxStoresPerMemcpy(); 2998 unsigned DstAlign = Align; // Destination alignment can change. 2999 std::string Str; 3000 bool CopyFromStr; 3001 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3002 Str, CopyFromStr, DAG, TLI)) 3003 return SDValue(); 3004 3005 3006 bool isZeroStr = CopyFromStr && Str.empty(); 3007 SmallVector<SDValue, 8> OutChains; 3008 unsigned NumMemOps = MemOps.size(); 3009 uint64_t SrcOff = 0, DstOff = 0; 3010 for (unsigned i = 0; i < NumMemOps; i++) { 3011 MVT VT = MemOps[i]; 3012 unsigned VTSize = VT.getSizeInBits() / 8; 3013 SDValue Value, Store; 3014 3015 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 3016 // It's unlikely a store of a vector immediate can be done in a single 3017 // instruction. It would require a load from a constantpool first. 3018 // We also handle store a vector with all zero's. 3019 // FIXME: Handle other cases where store of vector immediate is done in 3020 // a single instruction. 3021 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 3022 Store = DAG.getStore(Chain, Value, 3023 getMemBasePlusOffset(Dst, DstOff, DAG), 3024 DstSV, DstSVOff + DstOff, false, DstAlign); 3025 } else { 3026 Value = DAG.getLoad(VT, Chain, 3027 getMemBasePlusOffset(Src, SrcOff, DAG), 3028 SrcSV, SrcSVOff + SrcOff, false, Align); 3029 Store = DAG.getStore(Chain, Value, 3030 getMemBasePlusOffset(Dst, DstOff, DAG), 3031 DstSV, DstSVOff + DstOff, false, DstAlign); 3032 } 3033 OutChains.push_back(Store); 3034 SrcOff += VTSize; 3035 DstOff += VTSize; 3036 } 3037 3038 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3039 &OutChains[0], OutChains.size()); 3040} 3041 3042static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, 3043 SDValue Chain, SDValue Dst, 3044 SDValue Src, uint64_t Size, 3045 unsigned Align, bool AlwaysInline, 3046 const Value *DstSV, uint64_t DstSVOff, 3047 const Value *SrcSV, uint64_t SrcSVOff){ 3048 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3049 3050 // Expand memmove to a series of load and store ops if the size operand falls 3051 // below a certain threshold. 3052 std::vector<MVT> MemOps; 3053 uint64_t Limit = -1ULL; 3054 if (!AlwaysInline) 3055 Limit = TLI.getMaxStoresPerMemmove(); 3056 unsigned DstAlign = Align; // Destination alignment can change. 3057 std::string Str; 3058 bool CopyFromStr; 3059 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3060 Str, CopyFromStr, DAG, TLI)) 3061 return SDValue(); 3062 3063 uint64_t SrcOff = 0, DstOff = 0; 3064 3065 SmallVector<SDValue, 8> LoadValues; 3066 SmallVector<SDValue, 8> LoadChains; 3067 SmallVector<SDValue, 8> OutChains; 3068 unsigned NumMemOps = MemOps.size(); 3069 for (unsigned i = 0; i < NumMemOps; i++) { 3070 MVT VT = MemOps[i]; 3071 unsigned VTSize = VT.getSizeInBits() / 8; 3072 SDValue Value, Store; 3073 3074 Value = DAG.getLoad(VT, Chain, 3075 getMemBasePlusOffset(Src, SrcOff, DAG), 3076 SrcSV, SrcSVOff + SrcOff, false, Align); 3077 LoadValues.push_back(Value); 3078 LoadChains.push_back(Value.getValue(1)); 3079 SrcOff += VTSize; 3080 } 3081 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3082 &LoadChains[0], LoadChains.size()); 3083 OutChains.clear(); 3084 for (unsigned i = 0; i < NumMemOps; i++) { 3085 MVT VT = MemOps[i]; 3086 unsigned VTSize = VT.getSizeInBits() / 8; 3087 SDValue Value, Store; 3088 3089 Store = DAG.getStore(Chain, LoadValues[i], 3090 getMemBasePlusOffset(Dst, DstOff, DAG), 3091 DstSV, DstSVOff + DstOff, false, DstAlign); 3092 OutChains.push_back(Store); 3093 DstOff += VTSize; 3094 } 3095 3096 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3097 &OutChains[0], OutChains.size()); 3098} 3099 3100static SDValue getMemsetStores(SelectionDAG &DAG, 3101 SDValue Chain, SDValue Dst, 3102 SDValue Src, uint64_t Size, 3103 unsigned Align, 3104 const Value *DstSV, uint64_t DstSVOff) { 3105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3106 3107 // Expand memset to a series of load/store ops if the size operand 3108 // falls below a certain threshold. 3109 std::vector<MVT> MemOps; 3110 std::string Str; 3111 bool CopyFromStr; 3112 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3113 Size, Align, Str, CopyFromStr, DAG, TLI)) 3114 return SDValue(); 3115 3116 SmallVector<SDValue, 8> OutChains; 3117 uint64_t DstOff = 0; 3118 3119 unsigned NumMemOps = MemOps.size(); 3120 for (unsigned i = 0; i < NumMemOps; i++) { 3121 MVT VT = MemOps[i]; 3122 unsigned VTSize = VT.getSizeInBits() / 8; 3123 SDValue Value = getMemsetValue(Src, VT, DAG); 3124 SDValue Store = DAG.getStore(Chain, Value, 3125 getMemBasePlusOffset(Dst, DstOff, DAG), 3126 DstSV, DstSVOff + DstOff); 3127 OutChains.push_back(Store); 3128 DstOff += VTSize; 3129 } 3130 3131 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3132 &OutChains[0], OutChains.size()); 3133} 3134 3135SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst, 3136 SDValue Src, SDValue Size, 3137 unsigned Align, bool AlwaysInline, 3138 const Value *DstSV, uint64_t DstSVOff, 3139 const Value *SrcSV, uint64_t SrcSVOff) { 3140 3141 // Check to see if we should lower the memcpy to loads and stores first. 3142 // For cases within the target-specified limits, this is the best choice. 3143 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3144 if (ConstantSize) { 3145 // Memcpy with size zero? Just return the original chain. 3146 if (ConstantSize->isNullValue()) 3147 return Chain; 3148 3149 SDValue Result = 3150 getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3151 ConstantSize->getZExtValue(), 3152 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3153 if (Result.getNode()) 3154 return Result; 3155 } 3156 3157 // Then check to see if we should lower the memcpy with target-specific 3158 // code. If the target chooses to do this, this is the next best. 3159 SDValue Result = 3160 TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align, 3161 AlwaysInline, 3162 DstSV, DstSVOff, SrcSV, SrcSVOff); 3163 if (Result.getNode()) 3164 return Result; 3165 3166 // If we really need inline code and the target declined to provide it, 3167 // use a (potentially long) sequence of loads and stores. 3168 if (AlwaysInline) { 3169 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3170 return getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3171 ConstantSize->getZExtValue(), Align, true, 3172 DstSV, DstSVOff, SrcSV, SrcSVOff); 3173 } 3174 3175 // Emit a library call. 3176 TargetLowering::ArgListTy Args; 3177 TargetLowering::ArgListEntry Entry; 3178 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3179 Entry.Node = Dst; Args.push_back(Entry); 3180 Entry.Node = Src; Args.push_back(Entry); 3181 Entry.Node = Size; Args.push_back(Entry); 3182 std::pair<SDValue,SDValue> CallResult = 3183 TLI.LowerCallTo(Chain, Type::VoidTy, 3184 false, false, false, false, CallingConv::C, false, 3185 getExternalSymbol("memcpy", TLI.getPointerTy()), 3186 Args, *this); 3187 return CallResult.second; 3188} 3189 3190SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst, 3191 SDValue Src, SDValue Size, 3192 unsigned Align, 3193 const Value *DstSV, uint64_t DstSVOff, 3194 const Value *SrcSV, uint64_t SrcSVOff) { 3195 3196 // Check to see if we should lower the memmove to loads and stores first. 3197 // For cases within the target-specified limits, this is the best choice. 3198 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3199 if (ConstantSize) { 3200 // Memmove with size zero? Just return the original chain. 3201 if (ConstantSize->isNullValue()) 3202 return Chain; 3203 3204 SDValue Result = 3205 getMemmoveLoadsAndStores(*this, Chain, Dst, Src, 3206 ConstantSize->getZExtValue(), 3207 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3208 if (Result.getNode()) 3209 return Result; 3210 } 3211 3212 // Then check to see if we should lower the memmove with target-specific 3213 // code. If the target chooses to do this, this is the next best. 3214 SDValue Result = 3215 TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align, 3216 DstSV, DstSVOff, SrcSV, SrcSVOff); 3217 if (Result.getNode()) 3218 return Result; 3219 3220 // Emit a library call. 3221 TargetLowering::ArgListTy Args; 3222 TargetLowering::ArgListEntry Entry; 3223 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3224 Entry.Node = Dst; Args.push_back(Entry); 3225 Entry.Node = Src; Args.push_back(Entry); 3226 Entry.Node = Size; Args.push_back(Entry); 3227 std::pair<SDValue,SDValue> CallResult = 3228 TLI.LowerCallTo(Chain, Type::VoidTy, 3229 false, false, false, false, CallingConv::C, false, 3230 getExternalSymbol("memmove", TLI.getPointerTy()), 3231 Args, *this); 3232 return CallResult.second; 3233} 3234 3235SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst, 3236 SDValue Src, SDValue Size, 3237 unsigned Align, 3238 const Value *DstSV, uint64_t DstSVOff) { 3239 3240 // Check to see if we should lower the memset to stores first. 3241 // For cases within the target-specified limits, this is the best choice. 3242 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3243 if (ConstantSize) { 3244 // Memset with size zero? Just return the original chain. 3245 if (ConstantSize->isNullValue()) 3246 return Chain; 3247 3248 SDValue Result = 3249 getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getZExtValue(), 3250 Align, DstSV, DstSVOff); 3251 if (Result.getNode()) 3252 return Result; 3253 } 3254 3255 // Then check to see if we should lower the memset with target-specific 3256 // code. If the target chooses to do this, this is the next best. 3257 SDValue Result = 3258 TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align, 3259 DstSV, DstSVOff); 3260 if (Result.getNode()) 3261 return Result; 3262 3263 // Emit a library call. 3264 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3265 TargetLowering::ArgListTy Args; 3266 TargetLowering::ArgListEntry Entry; 3267 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3268 Args.push_back(Entry); 3269 // Extend or truncate the argument to be an i32 value for the call. 3270 if (Src.getValueType().bitsGT(MVT::i32)) 3271 Src = getNode(ISD::TRUNCATE, MVT::i32, Src); 3272 else 3273 Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src); 3274 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3275 Args.push_back(Entry); 3276 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3277 Args.push_back(Entry); 3278 std::pair<SDValue,SDValue> CallResult = 3279 TLI.LowerCallTo(Chain, Type::VoidTy, 3280 false, false, false, false, CallingConv::C, false, 3281 getExternalSymbol("memset", TLI.getPointerTy()), 3282 Args, *this); 3283 return CallResult.second; 3284} 3285 3286SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3287 SDValue Ptr, SDValue Cmp, 3288 SDValue Swp, const Value* PtrVal, 3289 unsigned Alignment) { 3290 assert((Opcode == ISD::ATOMIC_CMP_SWAP_8 || 3291 Opcode == ISD::ATOMIC_CMP_SWAP_16 || 3292 Opcode == ISD::ATOMIC_CMP_SWAP_32 || 3293 Opcode == ISD::ATOMIC_CMP_SWAP_64) && "Invalid Atomic Op"); 3294 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3295 3296 MVT VT = Cmp.getValueType(); 3297 3298 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3299 Alignment = getMVTAlignment(VT); 3300 3301 SDVTList VTs = getVTList(VT, MVT::Other); 3302 FoldingSetNodeID ID; 3303 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3304 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3305 void* IP = 0; 3306 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3307 return SDValue(E, 0); 3308 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3309 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3310 CSEMap.InsertNode(N, IP); 3311 AllNodes.push_back(N); 3312 return SDValue(N, 0); 3313} 3314 3315SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3316 SDValue Ptr, SDValue Val, 3317 const Value* PtrVal, 3318 unsigned Alignment) { 3319 assert((Opcode == ISD::ATOMIC_LOAD_ADD_8 || 3320 Opcode == ISD::ATOMIC_LOAD_SUB_8 || 3321 Opcode == ISD::ATOMIC_LOAD_AND_8 || 3322 Opcode == ISD::ATOMIC_LOAD_OR_8 || 3323 Opcode == ISD::ATOMIC_LOAD_XOR_8 || 3324 Opcode == ISD::ATOMIC_LOAD_NAND_8 || 3325 Opcode == ISD::ATOMIC_LOAD_MIN_8 || 3326 Opcode == ISD::ATOMIC_LOAD_MAX_8 || 3327 Opcode == ISD::ATOMIC_LOAD_UMIN_8 || 3328 Opcode == ISD::ATOMIC_LOAD_UMAX_8 || 3329 Opcode == ISD::ATOMIC_SWAP_8 || 3330 Opcode == ISD::ATOMIC_LOAD_ADD_16 || 3331 Opcode == ISD::ATOMIC_LOAD_SUB_16 || 3332 Opcode == ISD::ATOMIC_LOAD_AND_16 || 3333 Opcode == ISD::ATOMIC_LOAD_OR_16 || 3334 Opcode == ISD::ATOMIC_LOAD_XOR_16 || 3335 Opcode == ISD::ATOMIC_LOAD_NAND_16 || 3336 Opcode == ISD::ATOMIC_LOAD_MIN_16 || 3337 Opcode == ISD::ATOMIC_LOAD_MAX_16 || 3338 Opcode == ISD::ATOMIC_LOAD_UMIN_16 || 3339 Opcode == ISD::ATOMIC_LOAD_UMAX_16 || 3340 Opcode == ISD::ATOMIC_SWAP_16 || 3341 Opcode == ISD::ATOMIC_LOAD_ADD_32 || 3342 Opcode == ISD::ATOMIC_LOAD_SUB_32 || 3343 Opcode == ISD::ATOMIC_LOAD_AND_32 || 3344 Opcode == ISD::ATOMIC_LOAD_OR_32 || 3345 Opcode == ISD::ATOMIC_LOAD_XOR_32 || 3346 Opcode == ISD::ATOMIC_LOAD_NAND_32 || 3347 Opcode == ISD::ATOMIC_LOAD_MIN_32 || 3348 Opcode == ISD::ATOMIC_LOAD_MAX_32 || 3349 Opcode == ISD::ATOMIC_LOAD_UMIN_32 || 3350 Opcode == ISD::ATOMIC_LOAD_UMAX_32 || 3351 Opcode == ISD::ATOMIC_SWAP_32 || 3352 Opcode == ISD::ATOMIC_LOAD_ADD_64 || 3353 Opcode == ISD::ATOMIC_LOAD_SUB_64 || 3354 Opcode == ISD::ATOMIC_LOAD_AND_64 || 3355 Opcode == ISD::ATOMIC_LOAD_OR_64 || 3356 Opcode == ISD::ATOMIC_LOAD_XOR_64 || 3357 Opcode == ISD::ATOMIC_LOAD_NAND_64 || 3358 Opcode == ISD::ATOMIC_LOAD_MIN_64 || 3359 Opcode == ISD::ATOMIC_LOAD_MAX_64 || 3360 Opcode == ISD::ATOMIC_LOAD_UMIN_64 || 3361 Opcode == ISD::ATOMIC_LOAD_UMAX_64 || 3362 Opcode == ISD::ATOMIC_SWAP_64) && "Invalid Atomic Op"); 3363 3364 MVT VT = Val.getValueType(); 3365 3366 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3367 Alignment = getMVTAlignment(VT); 3368 3369 SDVTList VTs = getVTList(VT, MVT::Other); 3370 FoldingSetNodeID ID; 3371 SDValue Ops[] = {Chain, Ptr, Val}; 3372 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3373 void* IP = 0; 3374 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3375 return SDValue(E, 0); 3376 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3377 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Val, PtrVal, Alignment); 3378 CSEMap.InsertNode(N, IP); 3379 AllNodes.push_back(N); 3380 return SDValue(N, 0); 3381} 3382 3383/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3384/// Allowed to return something different (and simpler) if Simplify is true. 3385SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps) { 3386 if (NumOps == 1) 3387 return Ops[0]; 3388 3389 SmallVector<MVT, 4> VTs; 3390 VTs.reserve(NumOps); 3391 for (unsigned i = 0; i < NumOps; ++i) 3392 VTs.push_back(Ops[i].getValueType()); 3393 return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps); 3394} 3395 3396SDValue 3397SelectionDAG::getMemIntrinsicNode(unsigned Opcode, 3398 const MVT *VTs, unsigned NumVTs, 3399 const SDValue *Ops, unsigned NumOps, 3400 MVT MemVT, const Value *srcValue, int SVOff, 3401 unsigned Align, bool Vol, 3402 bool ReadMem, bool WriteMem) { 3403 return getMemIntrinsicNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps, 3404 MemVT, srcValue, SVOff, Align, Vol, 3405 ReadMem, WriteMem); 3406} 3407 3408SDValue 3409SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDVTList VTList, 3410 const SDValue *Ops, unsigned NumOps, 3411 MVT MemVT, const Value *srcValue, int SVOff, 3412 unsigned Align, bool Vol, 3413 bool ReadMem, bool WriteMem) { 3414 // Memoize the node unless it returns a flag. 3415 MemIntrinsicSDNode *N; 3416 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3417 FoldingSetNodeID ID; 3418 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3419 void *IP = 0; 3420 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3421 return SDValue(E, 0); 3422 3423 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3424 new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, 3425 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3426 CSEMap.InsertNode(N, IP); 3427 } else { 3428 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3429 new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, 3430 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3431 } 3432 AllNodes.push_back(N); 3433 return SDValue(N, 0); 3434} 3435 3436SDValue 3437SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall, 3438 bool IsInreg, SDVTList VTs, 3439 const SDValue *Operands, unsigned NumOperands) { 3440 // Do not include isTailCall in the folding set profile. 3441 FoldingSetNodeID ID; 3442 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3443 ID.AddInteger(CallingConv); 3444 ID.AddInteger(IsVarArgs); 3445 void *IP = 0; 3446 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3447 // Instead of including isTailCall in the folding set, we just 3448 // set the flag of the existing node. 3449 if (!IsTailCall) 3450 cast<CallSDNode>(E)->setNotTailCall(); 3451 return SDValue(E, 0); 3452 } 3453 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3454 new (N) CallSDNode(CallingConv, IsVarArgs, IsTailCall, IsInreg, 3455 VTs, Operands, NumOperands); 3456 CSEMap.InsertNode(N, IP); 3457 AllNodes.push_back(N); 3458 return SDValue(N, 0); 3459} 3460 3461SDValue 3462SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, 3463 MVT VT, SDValue Chain, 3464 SDValue Ptr, SDValue Offset, 3465 const Value *SV, int SVOffset, MVT EVT, 3466 bool isVolatile, unsigned Alignment) { 3467 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3468 Alignment = getMVTAlignment(VT); 3469 3470 if (VT == EVT) { 3471 ExtType = ISD::NON_EXTLOAD; 3472 } else if (ExtType == ISD::NON_EXTLOAD) { 3473 assert(VT == EVT && "Non-extending load from different memory type!"); 3474 } else { 3475 // Extending load. 3476 if (VT.isVector()) 3477 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3478 "Invalid vector extload!"); 3479 else 3480 assert(EVT.bitsLT(VT) && 3481 "Should only be an extending load, not truncating!"); 3482 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3483 "Cannot sign/zero extend a FP/Vector load!"); 3484 assert(VT.isInteger() == EVT.isInteger() && 3485 "Cannot convert from FP to Int or Int -> FP!"); 3486 } 3487 3488 bool Indexed = AM != ISD::UNINDEXED; 3489 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3490 "Unindexed load with an offset!"); 3491 3492 SDVTList VTs = Indexed ? 3493 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3494 SDValue Ops[] = { Chain, Ptr, Offset }; 3495 FoldingSetNodeID ID; 3496 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3497 ID.AddInteger(AM); 3498 ID.AddInteger(ExtType); 3499 ID.AddInteger(EVT.getRawBits()); 3500 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3501 void *IP = 0; 3502 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3503 return SDValue(E, 0); 3504 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3505 new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset, 3506 Alignment, isVolatile); 3507 CSEMap.InsertNode(N, IP); 3508 AllNodes.push_back(N); 3509 return SDValue(N, 0); 3510} 3511 3512SDValue SelectionDAG::getLoad(MVT VT, 3513 SDValue Chain, SDValue Ptr, 3514 const Value *SV, int SVOffset, 3515 bool isVolatile, unsigned Alignment) { 3516 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3517 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3518 SV, SVOffset, VT, isVolatile, Alignment); 3519} 3520 3521SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT, 3522 SDValue Chain, SDValue Ptr, 3523 const Value *SV, 3524 int SVOffset, MVT EVT, 3525 bool isVolatile, unsigned Alignment) { 3526 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3527 return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef, 3528 SV, SVOffset, EVT, isVolatile, Alignment); 3529} 3530 3531SDValue 3532SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base, 3533 SDValue Offset, ISD::MemIndexedMode AM) { 3534 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3535 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3536 "Load is already a indexed load!"); 3537 return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), 3538 LD->getChain(), Base, Offset, LD->getSrcValue(), 3539 LD->getSrcValueOffset(), LD->getMemoryVT(), 3540 LD->isVolatile(), LD->getAlignment()); 3541} 3542 3543SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val, 3544 SDValue Ptr, const Value *SV, int SVOffset, 3545 bool isVolatile, unsigned Alignment) { 3546 MVT VT = Val.getValueType(); 3547 3548 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3549 Alignment = getMVTAlignment(VT); 3550 3551 SDVTList VTs = getVTList(MVT::Other); 3552 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3553 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3554 FoldingSetNodeID ID; 3555 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3556 ID.AddInteger(ISD::UNINDEXED); 3557 ID.AddInteger(false); 3558 ID.AddInteger(VT.getRawBits()); 3559 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3560 void *IP = 0; 3561 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3562 return SDValue(E, 0); 3563 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3564 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false, 3565 VT, SV, SVOffset, Alignment, isVolatile); 3566 CSEMap.InsertNode(N, IP); 3567 AllNodes.push_back(N); 3568 return SDValue(N, 0); 3569} 3570 3571SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val, 3572 SDValue Ptr, const Value *SV, 3573 int SVOffset, MVT SVT, 3574 bool isVolatile, unsigned Alignment) { 3575 MVT VT = Val.getValueType(); 3576 3577 if (VT == SVT) 3578 return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3579 3580 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3581 assert(VT.isInteger() == SVT.isInteger() && 3582 "Can't do FP-INT conversion!"); 3583 3584 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3585 Alignment = getMVTAlignment(VT); 3586 3587 SDVTList VTs = getVTList(MVT::Other); 3588 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3589 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3590 FoldingSetNodeID ID; 3591 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3592 ID.AddInteger(ISD::UNINDEXED); 3593 ID.AddInteger(1); 3594 ID.AddInteger(SVT.getRawBits()); 3595 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3596 void *IP = 0; 3597 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3598 return SDValue(E, 0); 3599 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3600 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true, 3601 SVT, SV, SVOffset, Alignment, isVolatile); 3602 CSEMap.InsertNode(N, IP); 3603 AllNodes.push_back(N); 3604 return SDValue(N, 0); 3605} 3606 3607SDValue 3608SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base, 3609 SDValue Offset, ISD::MemIndexedMode AM) { 3610 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3611 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3612 "Store is already a indexed store!"); 3613 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3614 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3615 FoldingSetNodeID ID; 3616 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3617 ID.AddInteger(AM); 3618 ID.AddInteger(ST->isTruncatingStore()); 3619 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3620 ID.AddInteger(ST->getRawFlags()); 3621 void *IP = 0; 3622 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3623 return SDValue(E, 0); 3624 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3625 new (N) StoreSDNode(Ops, VTs, AM, 3626 ST->isTruncatingStore(), ST->getMemoryVT(), 3627 ST->getSrcValue(), ST->getSrcValueOffset(), 3628 ST->getAlignment(), ST->isVolatile()); 3629 CSEMap.InsertNode(N, IP); 3630 AllNodes.push_back(N); 3631 return SDValue(N, 0); 3632} 3633 3634SDValue SelectionDAG::getVAArg(MVT VT, 3635 SDValue Chain, SDValue Ptr, 3636 SDValue SV) { 3637 SDValue Ops[] = { Chain, Ptr, SV }; 3638 return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); 3639} 3640 3641SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3642 const SDUse *Ops, unsigned NumOps) { 3643 switch (NumOps) { 3644 case 0: return getNode(Opcode, VT); 3645 case 1: return getNode(Opcode, VT, Ops[0]); 3646 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3647 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3648 default: break; 3649 } 3650 3651 // Copy from an SDUse array into an SDValue array for use with 3652 // the regular getNode logic. 3653 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3654 return getNode(Opcode, VT, &NewOps[0], NumOps); 3655} 3656 3657SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3658 const SDValue *Ops, unsigned NumOps) { 3659 switch (NumOps) { 3660 case 0: return getNode(Opcode, VT); 3661 case 1: return getNode(Opcode, VT, Ops[0]); 3662 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3663 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3664 default: break; 3665 } 3666 3667 switch (Opcode) { 3668 default: break; 3669 case ISD::SELECT_CC: { 3670 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3671 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3672 "LHS and RHS of condition must have same type!"); 3673 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3674 "True and False arms of SelectCC must have same type!"); 3675 assert(Ops[2].getValueType() == VT && 3676 "select_cc node must be of same type as true and false value!"); 3677 break; 3678 } 3679 case ISD::BR_CC: { 3680 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3681 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3682 "LHS/RHS of comparison should match types!"); 3683 break; 3684 } 3685 } 3686 3687 // Memoize nodes. 3688 SDNode *N; 3689 SDVTList VTs = getVTList(VT); 3690 if (VT != MVT::Flag) { 3691 FoldingSetNodeID ID; 3692 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3693 void *IP = 0; 3694 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3695 return SDValue(E, 0); 3696 N = NodeAllocator.Allocate<SDNode>(); 3697 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3698 CSEMap.InsertNode(N, IP); 3699 } else { 3700 N = NodeAllocator.Allocate<SDNode>(); 3701 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3702 } 3703 AllNodes.push_back(N); 3704#ifndef NDEBUG 3705 VerifyNode(N); 3706#endif 3707 return SDValue(N, 0); 3708} 3709 3710SDValue SelectionDAG::getNode(unsigned Opcode, 3711 const std::vector<MVT> &ResultTys, 3712 const SDValue *Ops, unsigned NumOps) { 3713 return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(), 3714 Ops, NumOps); 3715} 3716 3717SDValue SelectionDAG::getNode(unsigned Opcode, 3718 const MVT *VTs, unsigned NumVTs, 3719 const SDValue *Ops, unsigned NumOps) { 3720 if (NumVTs == 1) 3721 return getNode(Opcode, VTs[0], Ops, NumOps); 3722 return getNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps); 3723} 3724 3725SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3726 const SDValue *Ops, unsigned NumOps) { 3727 if (VTList.NumVTs == 1) 3728 return getNode(Opcode, VTList.VTs[0], Ops, NumOps); 3729 3730 switch (Opcode) { 3731 // FIXME: figure out how to safely handle things like 3732 // int foo(int x) { return 1 << (x & 255); } 3733 // int bar() { return foo(256); } 3734#if 0 3735 case ISD::SRA_PARTS: 3736 case ISD::SRL_PARTS: 3737 case ISD::SHL_PARTS: 3738 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3739 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3740 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3741 else if (N3.getOpcode() == ISD::AND) 3742 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3743 // If the and is only masking out bits that cannot effect the shift, 3744 // eliminate the and. 3745 unsigned NumBits = VT.getSizeInBits()*2; 3746 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3747 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3748 } 3749 break; 3750#endif 3751 } 3752 3753 // Memoize the node unless it returns a flag. 3754 SDNode *N; 3755 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3756 FoldingSetNodeID ID; 3757 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3758 void *IP = 0; 3759 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3760 return SDValue(E, 0); 3761 if (NumOps == 1) { 3762 N = NodeAllocator.Allocate<UnarySDNode>(); 3763 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3764 } else if (NumOps == 2) { 3765 N = NodeAllocator.Allocate<BinarySDNode>(); 3766 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3767 } else if (NumOps == 3) { 3768 N = NodeAllocator.Allocate<TernarySDNode>(); 3769 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3770 } else { 3771 N = NodeAllocator.Allocate<SDNode>(); 3772 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3773 } 3774 CSEMap.InsertNode(N, IP); 3775 } else { 3776 if (NumOps == 1) { 3777 N = NodeAllocator.Allocate<UnarySDNode>(); 3778 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3779 } else if (NumOps == 2) { 3780 N = NodeAllocator.Allocate<BinarySDNode>(); 3781 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3782 } else if (NumOps == 3) { 3783 N = NodeAllocator.Allocate<TernarySDNode>(); 3784 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3785 } else { 3786 N = NodeAllocator.Allocate<SDNode>(); 3787 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3788 } 3789 } 3790 AllNodes.push_back(N); 3791#ifndef NDEBUG 3792 VerifyNode(N); 3793#endif 3794 return SDValue(N, 0); 3795} 3796 3797SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) { 3798 return getNode(Opcode, VTList, 0, 0); 3799} 3800 3801SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3802 SDValue N1) { 3803 SDValue Ops[] = { N1 }; 3804 return getNode(Opcode, VTList, Ops, 1); 3805} 3806 3807SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3808 SDValue N1, SDValue N2) { 3809 SDValue Ops[] = { N1, N2 }; 3810 return getNode(Opcode, VTList, Ops, 2); 3811} 3812 3813SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3814 SDValue N1, SDValue N2, SDValue N3) { 3815 SDValue Ops[] = { N1, N2, N3 }; 3816 return getNode(Opcode, VTList, Ops, 3); 3817} 3818 3819SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3820 SDValue N1, SDValue N2, SDValue N3, 3821 SDValue N4) { 3822 SDValue Ops[] = { N1, N2, N3, N4 }; 3823 return getNode(Opcode, VTList, Ops, 4); 3824} 3825 3826SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3827 SDValue N1, SDValue N2, SDValue N3, 3828 SDValue N4, SDValue N5) { 3829 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3830 return getNode(Opcode, VTList, Ops, 5); 3831} 3832 3833SDVTList SelectionDAG::getVTList(MVT VT) { 3834 return makeVTList(SDNode::getValueTypeList(VT), 1); 3835} 3836 3837SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3838 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3839 E = VTList.rend(); I != E; ++I) 3840 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3841 return *I; 3842 3843 MVT *Array = Allocator.Allocate<MVT>(2); 3844 Array[0] = VT1; 3845 Array[1] = VT2; 3846 SDVTList Result = makeVTList(Array, 2); 3847 VTList.push_back(Result); 3848 return Result; 3849} 3850 3851SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3852 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3853 E = VTList.rend(); I != E; ++I) 3854 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3855 I->VTs[2] == VT3) 3856 return *I; 3857 3858 MVT *Array = Allocator.Allocate<MVT>(3); 3859 Array[0] = VT1; 3860 Array[1] = VT2; 3861 Array[2] = VT3; 3862 SDVTList Result = makeVTList(Array, 3); 3863 VTList.push_back(Result); 3864 return Result; 3865} 3866 3867SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { 3868 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3869 E = VTList.rend(); I != E; ++I) 3870 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3871 I->VTs[2] == VT3 && I->VTs[3] == VT4) 3872 return *I; 3873 3874 MVT *Array = Allocator.Allocate<MVT>(3); 3875 Array[0] = VT1; 3876 Array[1] = VT2; 3877 Array[2] = VT3; 3878 Array[3] = VT4; 3879 SDVTList Result = makeVTList(Array, 4); 3880 VTList.push_back(Result); 3881 return Result; 3882} 3883 3884SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3885 switch (NumVTs) { 3886 case 0: assert(0 && "Cannot have nodes without results!"); 3887 case 1: return getVTList(VTs[0]); 3888 case 2: return getVTList(VTs[0], VTs[1]); 3889 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3890 default: break; 3891 } 3892 3893 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3894 E = VTList.rend(); I != E; ++I) { 3895 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3896 continue; 3897 3898 bool NoMatch = false; 3899 for (unsigned i = 2; i != NumVTs; ++i) 3900 if (VTs[i] != I->VTs[i]) { 3901 NoMatch = true; 3902 break; 3903 } 3904 if (!NoMatch) 3905 return *I; 3906 } 3907 3908 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 3909 std::copy(VTs, VTs+NumVTs, Array); 3910 SDVTList Result = makeVTList(Array, NumVTs); 3911 VTList.push_back(Result); 3912 return Result; 3913} 3914 3915 3916/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 3917/// specified operands. If the resultant node already exists in the DAG, 3918/// this does not modify the specified node, instead it returns the node that 3919/// already exists. If the resultant node does not exist in the DAG, the 3920/// input node is returned. As a degenerate case, if you specify the same 3921/// input operands as the node already has, the input node is returned. 3922SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 3923 SDNode *N = InN.getNode(); 3924 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 3925 3926 // Check to see if there is no change. 3927 if (Op == N->getOperand(0)) return InN; 3928 3929 // See if the modified node already exists. 3930 void *InsertPos = 0; 3931 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 3932 return SDValue(Existing, InN.getResNo()); 3933 3934 // Nope it doesn't. Remove the node from its current place in the maps. 3935 if (InsertPos) 3936 if (!RemoveNodeFromCSEMaps(N)) 3937 InsertPos = 0; 3938 3939 // Now we update the operands. 3940 N->OperandList[0].getVal()->removeUser(0, N); 3941 N->OperandList[0] = Op; 3942 N->OperandList[0].setUser(N); 3943 Op.getNode()->addUser(0, N); 3944 3945 // If this gets put into a CSE map, add it. 3946 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3947 return InN; 3948} 3949 3950SDValue SelectionDAG:: 3951UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 3952 SDNode *N = InN.getNode(); 3953 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 3954 3955 // Check to see if there is no change. 3956 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 3957 return InN; // No operands changed, just return the input node. 3958 3959 // See if the modified node already exists. 3960 void *InsertPos = 0; 3961 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 3962 return SDValue(Existing, InN.getResNo()); 3963 3964 // Nope it doesn't. Remove the node from its current place in the maps. 3965 if (InsertPos) 3966 if (!RemoveNodeFromCSEMaps(N)) 3967 InsertPos = 0; 3968 3969 // Now we update the operands. 3970 if (N->OperandList[0] != Op1) { 3971 N->OperandList[0].getVal()->removeUser(0, N); 3972 N->OperandList[0] = Op1; 3973 N->OperandList[0].setUser(N); 3974 Op1.getNode()->addUser(0, N); 3975 } 3976 if (N->OperandList[1] != Op2) { 3977 N->OperandList[1].getVal()->removeUser(1, N); 3978 N->OperandList[1] = Op2; 3979 N->OperandList[1].setUser(N); 3980 Op2.getNode()->addUser(1, N); 3981 } 3982 3983 // If this gets put into a CSE map, add it. 3984 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3985 return InN; 3986} 3987 3988SDValue SelectionDAG:: 3989UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 3990 SDValue Ops[] = { Op1, Op2, Op3 }; 3991 return UpdateNodeOperands(N, Ops, 3); 3992} 3993 3994SDValue SelectionDAG:: 3995UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3996 SDValue Op3, SDValue Op4) { 3997 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 3998 return UpdateNodeOperands(N, Ops, 4); 3999} 4000 4001SDValue SelectionDAG:: 4002UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4003 SDValue Op3, SDValue Op4, SDValue Op5) { 4004 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 4005 return UpdateNodeOperands(N, Ops, 5); 4006} 4007 4008SDValue SelectionDAG:: 4009UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 4010 SDNode *N = InN.getNode(); 4011 assert(N->getNumOperands() == NumOps && 4012 "Update with wrong number of operands"); 4013 4014 // Check to see if there is no change. 4015 bool AnyChange = false; 4016 for (unsigned i = 0; i != NumOps; ++i) { 4017 if (Ops[i] != N->getOperand(i)) { 4018 AnyChange = true; 4019 break; 4020 } 4021 } 4022 4023 // No operands changed, just return the input node. 4024 if (!AnyChange) return InN; 4025 4026 // See if the modified node already exists. 4027 void *InsertPos = 0; 4028 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 4029 return SDValue(Existing, InN.getResNo()); 4030 4031 // Nope it doesn't. Remove the node from its current place in the maps. 4032 if (InsertPos) 4033 if (!RemoveNodeFromCSEMaps(N)) 4034 InsertPos = 0; 4035 4036 // Now we update the operands. 4037 for (unsigned i = 0; i != NumOps; ++i) { 4038 if (N->OperandList[i] != Ops[i]) { 4039 N->OperandList[i].getVal()->removeUser(i, N); 4040 N->OperandList[i] = Ops[i]; 4041 N->OperandList[i].setUser(N); 4042 Ops[i].getNode()->addUser(i, N); 4043 } 4044 } 4045 4046 // If this gets put into a CSE map, add it. 4047 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4048 return InN; 4049} 4050 4051/// DropOperands - Release the operands and set this node to have 4052/// zero operands. 4053void SDNode::DropOperands() { 4054 // Unlike the code in MorphNodeTo that does this, we don't need to 4055 // watch for dead nodes here. 4056 for (op_iterator I = op_begin(), E = op_end(); I != E; ++I) 4057 I->getVal()->removeUser(std::distance(op_begin(), I), this); 4058 4059 NumOperands = 0; 4060} 4061 4062/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4063/// machine opcode. 4064/// 4065SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4066 MVT VT) { 4067 SDVTList VTs = getVTList(VT); 4068 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4069} 4070 4071SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4072 MVT VT, SDValue Op1) { 4073 SDVTList VTs = getVTList(VT); 4074 SDValue Ops[] = { Op1 }; 4075 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4076} 4077 4078SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4079 MVT VT, SDValue Op1, 4080 SDValue Op2) { 4081 SDVTList VTs = getVTList(VT); 4082 SDValue Ops[] = { Op1, Op2 }; 4083 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4084} 4085 4086SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4087 MVT VT, SDValue Op1, 4088 SDValue Op2, SDValue Op3) { 4089 SDVTList VTs = getVTList(VT); 4090 SDValue Ops[] = { Op1, Op2, Op3 }; 4091 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4092} 4093 4094SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4095 MVT VT, const SDValue *Ops, 4096 unsigned NumOps) { 4097 SDVTList VTs = getVTList(VT); 4098 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4099} 4100 4101SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4102 MVT VT1, MVT VT2, const SDValue *Ops, 4103 unsigned NumOps) { 4104 SDVTList VTs = getVTList(VT1, VT2); 4105 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4106} 4107 4108SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4109 MVT VT1, MVT VT2) { 4110 SDVTList VTs = getVTList(VT1, VT2); 4111 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4112} 4113 4114SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4115 MVT VT1, MVT VT2, MVT VT3, 4116 const SDValue *Ops, unsigned NumOps) { 4117 SDVTList VTs = getVTList(VT1, VT2, VT3); 4118 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4119} 4120 4121SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4122 MVT VT1, MVT VT2, MVT VT3, MVT VT4, 4123 const SDValue *Ops, unsigned NumOps) { 4124 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4125 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4126} 4127 4128SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4129 MVT VT1, MVT VT2, 4130 SDValue Op1) { 4131 SDVTList VTs = getVTList(VT1, VT2); 4132 SDValue Ops[] = { Op1 }; 4133 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4134} 4135 4136SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4137 MVT VT1, MVT VT2, 4138 SDValue Op1, SDValue Op2) { 4139 SDVTList VTs = getVTList(VT1, VT2); 4140 SDValue Ops[] = { Op1, Op2 }; 4141 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4142} 4143 4144SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4145 MVT VT1, MVT VT2, 4146 SDValue Op1, SDValue Op2, 4147 SDValue Op3) { 4148 SDVTList VTs = getVTList(VT1, VT2); 4149 SDValue Ops[] = { Op1, Op2, Op3 }; 4150 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4151} 4152 4153SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4154 MVT VT1, MVT VT2, MVT VT3, 4155 SDValue Op1, SDValue Op2, 4156 SDValue Op3) { 4157 SDVTList VTs = getVTList(VT1, VT2, VT3); 4158 SDValue Ops[] = { Op1, Op2, Op3 }; 4159 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4160} 4161 4162SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4163 SDVTList VTs, const SDValue *Ops, 4164 unsigned NumOps) { 4165 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4166} 4167 4168SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4169 MVT VT) { 4170 SDVTList VTs = getVTList(VT); 4171 return MorphNodeTo(N, Opc, VTs, 0, 0); 4172} 4173 4174SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4175 MVT VT, SDValue Op1) { 4176 SDVTList VTs = getVTList(VT); 4177 SDValue Ops[] = { Op1 }; 4178 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4179} 4180 4181SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4182 MVT VT, SDValue Op1, 4183 SDValue Op2) { 4184 SDVTList VTs = getVTList(VT); 4185 SDValue Ops[] = { Op1, Op2 }; 4186 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4187} 4188 4189SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4190 MVT VT, SDValue Op1, 4191 SDValue Op2, SDValue Op3) { 4192 SDVTList VTs = getVTList(VT); 4193 SDValue Ops[] = { Op1, Op2, Op3 }; 4194 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4195} 4196 4197SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4198 MVT VT, const SDValue *Ops, 4199 unsigned NumOps) { 4200 SDVTList VTs = getVTList(VT); 4201 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4202} 4203 4204SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4205 MVT VT1, MVT VT2, const SDValue *Ops, 4206 unsigned NumOps) { 4207 SDVTList VTs = getVTList(VT1, VT2); 4208 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4209} 4210 4211SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4212 MVT VT1, MVT VT2) { 4213 SDVTList VTs = getVTList(VT1, VT2); 4214 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4215} 4216 4217SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4218 MVT VT1, MVT VT2, MVT VT3, 4219 const SDValue *Ops, unsigned NumOps) { 4220 SDVTList VTs = getVTList(VT1, VT2, VT3); 4221 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4222} 4223 4224SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4225 MVT VT1, MVT VT2, 4226 SDValue Op1) { 4227 SDVTList VTs = getVTList(VT1, VT2); 4228 SDValue Ops[] = { Op1 }; 4229 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4230} 4231 4232SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4233 MVT VT1, MVT VT2, 4234 SDValue Op1, SDValue Op2) { 4235 SDVTList VTs = getVTList(VT1, VT2); 4236 SDValue Ops[] = { Op1, Op2 }; 4237 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4238} 4239 4240SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4241 MVT VT1, MVT VT2, 4242 SDValue Op1, SDValue Op2, 4243 SDValue Op3) { 4244 SDVTList VTs = getVTList(VT1, VT2); 4245 SDValue Ops[] = { Op1, Op2, Op3 }; 4246 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4247} 4248 4249/// MorphNodeTo - These *mutate* the specified node to have the specified 4250/// return type, opcode, and operands. 4251/// 4252/// Note that MorphNodeTo returns the resultant node. If there is already a 4253/// node of the specified opcode and operands, it returns that node instead of 4254/// the current one. 4255/// 4256/// Using MorphNodeTo is faster than creating a new node and swapping it in 4257/// with ReplaceAllUsesWith both because it often avoids allocating a new 4258/// node, and because it doesn't require CSE recalculation for any of 4259/// the node's users. 4260/// 4261SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4262 SDVTList VTs, const SDValue *Ops, 4263 unsigned NumOps) { 4264 // If an identical node already exists, use it. 4265 void *IP = 0; 4266 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4267 FoldingSetNodeID ID; 4268 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4269 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4270 return ON; 4271 } 4272 4273 if (!RemoveNodeFromCSEMaps(N)) 4274 IP = 0; 4275 4276 // Start the morphing. 4277 N->NodeType = Opc; 4278 N->ValueList = VTs.VTs; 4279 N->NumValues = VTs.NumVTs; 4280 4281 // Clear the operands list, updating used nodes to remove this from their 4282 // use list. Keep track of any operands that become dead as a result. 4283 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4284 for (SDNode::op_iterator B = N->op_begin(), I = B, E = N->op_end(); 4285 I != E; ++I) { 4286 SDNode *Used = I->getVal(); 4287 Used->removeUser(std::distance(B, I), N); 4288 if (Used->use_empty()) 4289 DeadNodeSet.insert(Used); 4290 } 4291 4292 // If NumOps is larger than the # of operands we currently have, reallocate 4293 // the operand list. 4294 if (NumOps > N->NumOperands) { 4295 if (N->OperandsNeedDelete) 4296 delete[] N->OperandList; 4297 4298 if (N->isMachineOpcode()) { 4299 // We're creating a final node that will live unmorphed for the 4300 // remainder of the current SelectionDAG iteration, so we can allocate 4301 // the operands directly out of a pool with no recycling metadata. 4302 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4303 N->OperandsNeedDelete = false; 4304 } else { 4305 N->OperandList = new SDUse[NumOps]; 4306 N->OperandsNeedDelete = true; 4307 } 4308 } 4309 4310 // Assign the new operands. 4311 N->NumOperands = NumOps; 4312 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4313 N->OperandList[i] = Ops[i]; 4314 N->OperandList[i].setUser(N); 4315 SDNode *ToUse = N->OperandList[i].getVal(); 4316 ToUse->addUser(i, N); 4317 } 4318 4319 // Delete any nodes that are still dead after adding the uses for the 4320 // new operands. 4321 SmallVector<SDNode *, 16> DeadNodes; 4322 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4323 E = DeadNodeSet.end(); I != E; ++I) 4324 if ((*I)->use_empty()) 4325 DeadNodes.push_back(*I); 4326 RemoveDeadNodes(DeadNodes); 4327 4328 if (IP) 4329 CSEMap.InsertNode(N, IP); // Memoize the new node. 4330 return N; 4331} 4332 4333 4334/// getTargetNode - These are used for target selectors to create a new node 4335/// with specified return type(s), target opcode, and operands. 4336/// 4337/// Note that getTargetNode returns the resultant node. If there is already a 4338/// node of the specified opcode and operands, it returns that node instead of 4339/// the current one. 4340SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { 4341 return getNode(~Opcode, VT).getNode(); 4342} 4343SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) { 4344 return getNode(~Opcode, VT, Op1).getNode(); 4345} 4346SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4347 SDValue Op1, SDValue Op2) { 4348 return getNode(~Opcode, VT, Op1, Op2).getNode(); 4349} 4350SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4351 SDValue Op1, SDValue Op2, 4352 SDValue Op3) { 4353 return getNode(~Opcode, VT, Op1, Op2, Op3).getNode(); 4354} 4355SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4356 const SDValue *Ops, unsigned NumOps) { 4357 return getNode(~Opcode, VT, Ops, NumOps).getNode(); 4358} 4359SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { 4360 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4361 SDValue Op; 4362 return getNode(~Opcode, VTs, 2, &Op, 0).getNode(); 4363} 4364SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4365 MVT VT2, SDValue Op1) { 4366 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4367 return getNode(~Opcode, VTs, 2, &Op1, 1).getNode(); 4368} 4369SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4370 MVT VT2, SDValue Op1, 4371 SDValue Op2) { 4372 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4373 SDValue Ops[] = { Op1, Op2 }; 4374 return getNode(~Opcode, VTs, 2, Ops, 2).getNode(); 4375} 4376SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4377 MVT VT2, SDValue Op1, 4378 SDValue Op2, SDValue Op3) { 4379 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4380 SDValue Ops[] = { Op1, Op2, Op3 }; 4381 return getNode(~Opcode, VTs, 2, Ops, 3).getNode(); 4382} 4383SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, 4384 const SDValue *Ops, unsigned NumOps) { 4385 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4386 return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode(); 4387} 4388SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4389 SDValue Op1, SDValue Op2) { 4390 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4391 SDValue Ops[] = { Op1, Op2 }; 4392 return getNode(~Opcode, VTs, 3, Ops, 2).getNode(); 4393} 4394SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4395 SDValue Op1, SDValue Op2, 4396 SDValue Op3) { 4397 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4398 SDValue Ops[] = { Op1, Op2, Op3 }; 4399 return getNode(~Opcode, VTs, 3, Ops, 3).getNode(); 4400} 4401SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4402 const SDValue *Ops, unsigned NumOps) { 4403 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4404 return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode(); 4405} 4406SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4407 MVT VT2, MVT VT3, MVT VT4, 4408 const SDValue *Ops, unsigned NumOps) { 4409 std::vector<MVT> VTList; 4410 VTList.push_back(VT1); 4411 VTList.push_back(VT2); 4412 VTList.push_back(VT3); 4413 VTList.push_back(VT4); 4414 const MVT *VTs = getNodeValueTypes(VTList); 4415 return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode(); 4416} 4417SDNode *SelectionDAG::getTargetNode(unsigned Opcode, 4418 const std::vector<MVT> &ResultTys, 4419 const SDValue *Ops, unsigned NumOps) { 4420 const MVT *VTs = getNodeValueTypes(ResultTys); 4421 return getNode(~Opcode, VTs, ResultTys.size(), 4422 Ops, NumOps).getNode(); 4423} 4424 4425/// getNodeIfExists - Get the specified node if it's already available, or 4426/// else return NULL. 4427SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4428 const SDValue *Ops, unsigned NumOps) { 4429 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4430 FoldingSetNodeID ID; 4431 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4432 void *IP = 0; 4433 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4434 return E; 4435 } 4436 return NULL; 4437} 4438 4439 4440/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4441/// This can cause recursive merging of nodes in the DAG. 4442/// 4443/// This version assumes From has a single result value. 4444/// 4445void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4446 DAGUpdateListener *UpdateListener) { 4447 SDNode *From = FromN.getNode(); 4448 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4449 "Cannot replace with this method!"); 4450 assert(From != To.getNode() && "Cannot replace uses of with self"); 4451 4452 while (!From->use_empty()) { 4453 SDNode::use_iterator UI = From->use_begin(); 4454 SDNode *U = *UI; 4455 4456 // This node is about to morph, remove its old self from the CSE maps. 4457 RemoveNodeFromCSEMaps(U); 4458 int operandNum = 0; 4459 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4460 I != E; ++I, ++operandNum) 4461 if (I->getVal() == From) { 4462 From->removeUser(operandNum, U); 4463 *I = To; 4464 I->setUser(U); 4465 To.getNode()->addUser(operandNum, U); 4466 } 4467 4468 // Now that we have modified U, add it back to the CSE maps. If it already 4469 // exists there, recursively merge the results together. 4470 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4471 ReplaceAllUsesWith(U, Existing, UpdateListener); 4472 // U is now dead. Inform the listener if it exists and delete it. 4473 if (UpdateListener) 4474 UpdateListener->NodeDeleted(U, Existing); 4475 DeleteNodeNotInCSEMaps(U); 4476 } else { 4477 // If the node doesn't already exist, we updated it. Inform a listener if 4478 // it exists. 4479 if (UpdateListener) 4480 UpdateListener->NodeUpdated(U); 4481 } 4482 } 4483} 4484 4485/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4486/// This can cause recursive merging of nodes in the DAG. 4487/// 4488/// This version assumes From/To have matching types and numbers of result 4489/// values. 4490/// 4491void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4492 DAGUpdateListener *UpdateListener) { 4493 assert(From->getVTList().VTs == To->getVTList().VTs && 4494 From->getNumValues() == To->getNumValues() && 4495 "Cannot use this version of ReplaceAllUsesWith!"); 4496 4497 // Handle the trivial case. 4498 if (From == To) 4499 return; 4500 4501 while (!From->use_empty()) { 4502 SDNode::use_iterator UI = From->use_begin(); 4503 SDNode *U = *UI; 4504 4505 // This node is about to morph, remove its old self from the CSE maps. 4506 RemoveNodeFromCSEMaps(U); 4507 int operandNum = 0; 4508 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4509 I != E; ++I, ++operandNum) 4510 if (I->getVal() == From) { 4511 From->removeUser(operandNum, U); 4512 I->getSDValue().setNode(To); 4513 To->addUser(operandNum, U); 4514 } 4515 4516 // Now that we have modified U, add it back to the CSE maps. If it already 4517 // exists there, recursively merge the results together. 4518 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4519 ReplaceAllUsesWith(U, Existing, UpdateListener); 4520 // U is now dead. Inform the listener if it exists and delete it. 4521 if (UpdateListener) 4522 UpdateListener->NodeDeleted(U, Existing); 4523 DeleteNodeNotInCSEMaps(U); 4524 } else { 4525 // If the node doesn't already exist, we updated it. Inform a listener if 4526 // it exists. 4527 if (UpdateListener) 4528 UpdateListener->NodeUpdated(U); 4529 } 4530 } 4531} 4532 4533/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4534/// This can cause recursive merging of nodes in the DAG. 4535/// 4536/// This version can replace From with any result values. To must match the 4537/// number and types of values returned by From. 4538void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4539 const SDValue *To, 4540 DAGUpdateListener *UpdateListener) { 4541 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4542 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4543 4544 while (!From->use_empty()) { 4545 SDNode::use_iterator UI = From->use_begin(); 4546 SDNode *U = *UI; 4547 4548 // This node is about to morph, remove its old self from the CSE maps. 4549 RemoveNodeFromCSEMaps(U); 4550 int operandNum = 0; 4551 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4552 I != E; ++I, ++operandNum) 4553 if (I->getVal() == From) { 4554 const SDValue &ToOp = To[I->getSDValue().getResNo()]; 4555 From->removeUser(operandNum, U); 4556 *I = ToOp; 4557 I->setUser(U); 4558 ToOp.getNode()->addUser(operandNum, U); 4559 } 4560 4561 // Now that we have modified U, add it back to the CSE maps. If it already 4562 // exists there, recursively merge the results together. 4563 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4564 ReplaceAllUsesWith(U, Existing, UpdateListener); 4565 // U is now dead. Inform the listener if it exists and delete it. 4566 if (UpdateListener) 4567 UpdateListener->NodeDeleted(U, Existing); 4568 DeleteNodeNotInCSEMaps(U); 4569 } else { 4570 // If the node doesn't already exist, we updated it. Inform a listener if 4571 // it exists. 4572 if (UpdateListener) 4573 UpdateListener->NodeUpdated(U); 4574 } 4575 } 4576} 4577 4578/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4579/// uses of other values produced by From.getVal() alone. The Deleted vector is 4580/// handled the same way as for ReplaceAllUsesWith. 4581void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4582 DAGUpdateListener *UpdateListener){ 4583 // Handle the really simple, really trivial case efficiently. 4584 if (From == To) return; 4585 4586 // Handle the simple, trivial, case efficiently. 4587 if (From.getNode()->getNumValues() == 1) { 4588 ReplaceAllUsesWith(From, To, UpdateListener); 4589 return; 4590 } 4591 4592 // Get all of the users of From.getNode(). We want these in a nice, 4593 // deterministically ordered and uniqued set, so we use a SmallSetVector. 4594 SmallSetVector<SDNode*, 16> Users(From.getNode()->use_begin(), From.getNode()->use_end()); 4595 4596 while (!Users.empty()) { 4597 // We know that this user uses some value of From. If it is the right 4598 // value, update it. 4599 SDNode *User = Users.back(); 4600 Users.pop_back(); 4601 4602 // Scan for an operand that matches From. 4603 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4604 for (; Op != E; ++Op) 4605 if (*Op == From) break; 4606 4607 // If there are no matches, the user must use some other result of From. 4608 if (Op == E) continue; 4609 4610 // Okay, we know this user needs to be updated. Remove its old self 4611 // from the CSE maps. 4612 RemoveNodeFromCSEMaps(User); 4613 4614 // Update all operands that match "From" in case there are multiple uses. 4615 for (; Op != E; ++Op) { 4616 if (*Op == From) { 4617 From.getNode()->removeUser(Op-User->op_begin(), User); 4618 *Op = To; 4619 Op->setUser(User); 4620 To.getNode()->addUser(Op-User->op_begin(), User); 4621 } 4622 } 4623 4624 // Now that we have modified User, add it back to the CSE maps. If it 4625 // already exists there, recursively merge the results together. 4626 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4627 if (!Existing) { 4628 if (UpdateListener) UpdateListener->NodeUpdated(User); 4629 continue; // Continue on to next user. 4630 } 4631 4632 // If there was already an existing matching node, use ReplaceAllUsesWith 4633 // to replace the dead one with the existing one. This can cause 4634 // recursive merging of other unrelated nodes down the line. 4635 ReplaceAllUsesWith(User, Existing, UpdateListener); 4636 4637 // User is now dead. Notify a listener if present. 4638 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4639 DeleteNodeNotInCSEMaps(User); 4640 } 4641} 4642 4643/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4644/// uses of other values produced by From.getVal() alone. The same value may 4645/// appear in both the From and To list. The Deleted vector is 4646/// handled the same way as for ReplaceAllUsesWith. 4647void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4648 const SDValue *To, 4649 unsigned Num, 4650 DAGUpdateListener *UpdateListener){ 4651 // Handle the simple, trivial case efficiently. 4652 if (Num == 1) 4653 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4654 4655 SmallVector<std::pair<SDNode *, unsigned>, 16> Users; 4656 for (unsigned i = 0; i != Num; ++i) 4657 for (SDNode::use_iterator UI = From[i].getNode()->use_begin(), 4658 E = From[i].getNode()->use_end(); UI != E; ++UI) 4659 Users.push_back(std::make_pair(*UI, i)); 4660 4661 while (!Users.empty()) { 4662 // We know that this user uses some value of From. If it is the right 4663 // value, update it. 4664 SDNode *User = Users.back().first; 4665 unsigned i = Users.back().second; 4666 Users.pop_back(); 4667 4668 // Scan for an operand that matches From. 4669 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4670 for (; Op != E; ++Op) 4671 if (*Op == From[i]) break; 4672 4673 // If there are no matches, the user must use some other result of From. 4674 if (Op == E) continue; 4675 4676 // Okay, we know this user needs to be updated. Remove its old self 4677 // from the CSE maps. 4678 RemoveNodeFromCSEMaps(User); 4679 4680 // Update all operands that match "From" in case there are multiple uses. 4681 for (; Op != E; ++Op) { 4682 if (*Op == From[i]) { 4683 From[i].getNode()->removeUser(Op-User->op_begin(), User); 4684 *Op = To[i]; 4685 Op->setUser(User); 4686 To[i].getNode()->addUser(Op-User->op_begin(), User); 4687 } 4688 } 4689 4690 // Now that we have modified User, add it back to the CSE maps. If it 4691 // already exists there, recursively merge the results together. 4692 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4693 if (!Existing) { 4694 if (UpdateListener) UpdateListener->NodeUpdated(User); 4695 continue; // Continue on to next user. 4696 } 4697 4698 // If there was already an existing matching node, use ReplaceAllUsesWith 4699 // to replace the dead one with the existing one. This can cause 4700 // recursive merging of other unrelated nodes down the line. 4701 ReplaceAllUsesWith(User, Existing, UpdateListener); 4702 4703 // User is now dead. Notify a listener if present. 4704 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4705 DeleteNodeNotInCSEMaps(User); 4706 } 4707} 4708 4709/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4710/// based on their topological order. It returns the maximum id and a vector 4711/// of the SDNodes* in assigned order by reference. 4712unsigned SelectionDAG::AssignTopologicalOrder() { 4713 4714 unsigned DAGSize = 0; 4715 4716 // SortedPos tracks the progress of the algorithm. Nodes before it are 4717 // sorted, nodes after it are unsorted. When the algorithm completes 4718 // it is at the end of the list. 4719 allnodes_iterator SortedPos = allnodes_begin(); 4720 4721 // Visit all the nodes. Move nodes with no operands to the front of 4722 // the list immediately. Annotate nodes that do have operands with their 4723 // operand count. Before we do this, the Node Id fields of the nodes 4724 // may contain arbitrary values. After, the Node Id fields for nodes 4725 // before SortedPos will contain the topological sort index, and the 4726 // Node Id fields for nodes At SortedPos and after will contain the 4727 // count of outstanding operands. 4728 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4729 SDNode *N = I++; 4730 unsigned Degree = N->getNumOperands(); 4731 if (Degree == 0) { 4732 // A node with no uses, add it to the result array immediately. 4733 N->setNodeId(DAGSize++); 4734 allnodes_iterator Q = N; 4735 if (Q != SortedPos) 4736 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4737 ++SortedPos; 4738 } else { 4739 // Temporarily use the Node Id as scratch space for the degree count. 4740 N->setNodeId(Degree); 4741 } 4742 } 4743 4744 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4745 // such that by the time the end is reached all nodes will be sorted. 4746 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4747 SDNode *N = I; 4748 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4749 UI != UE; ++UI) { 4750 SDNode *P = *UI; 4751 unsigned Degree = P->getNodeId(); 4752 --Degree; 4753 if (Degree == 0) { 4754 // All of P's operands are sorted, so P may sorted now. 4755 P->setNodeId(DAGSize++); 4756 if (P != SortedPos) 4757 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4758 ++SortedPos; 4759 } else { 4760 // Update P's outstanding operand count. 4761 P->setNodeId(Degree); 4762 } 4763 } 4764 } 4765 4766 assert(SortedPos == AllNodes.end() && 4767 "Topological sort incomplete!"); 4768 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4769 "First node in topological sort is not the entry token!"); 4770 assert(AllNodes.front().getNodeId() == 0 && 4771 "First node in topological sort has non-zero id!"); 4772 assert(AllNodes.front().getNumOperands() == 0 && 4773 "First node in topological sort has operands!"); 4774 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4775 "Last node in topologic sort has unexpected id!"); 4776 assert(AllNodes.back().use_empty() && 4777 "Last node in topologic sort has users!"); 4778 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 4779 return DAGSize; 4780} 4781 4782 4783 4784//===----------------------------------------------------------------------===// 4785// SDNode Class 4786//===----------------------------------------------------------------------===// 4787 4788// Out-of-line virtual method to give class a home. 4789void SDNode::ANCHOR() {} 4790void UnarySDNode::ANCHOR() {} 4791void BinarySDNode::ANCHOR() {} 4792void TernarySDNode::ANCHOR() {} 4793void HandleSDNode::ANCHOR() {} 4794void ConstantSDNode::ANCHOR() {} 4795void ConstantFPSDNode::ANCHOR() {} 4796void GlobalAddressSDNode::ANCHOR() {} 4797void FrameIndexSDNode::ANCHOR() {} 4798void JumpTableSDNode::ANCHOR() {} 4799void ConstantPoolSDNode::ANCHOR() {} 4800void BasicBlockSDNode::ANCHOR() {} 4801void SrcValueSDNode::ANCHOR() {} 4802void MemOperandSDNode::ANCHOR() {} 4803void RegisterSDNode::ANCHOR() {} 4804void DbgStopPointSDNode::ANCHOR() {} 4805void LabelSDNode::ANCHOR() {} 4806void ExternalSymbolSDNode::ANCHOR() {} 4807void CondCodeSDNode::ANCHOR() {} 4808void ARG_FLAGSSDNode::ANCHOR() {} 4809void VTSDNode::ANCHOR() {} 4810void MemSDNode::ANCHOR() {} 4811void LoadSDNode::ANCHOR() {} 4812void StoreSDNode::ANCHOR() {} 4813void AtomicSDNode::ANCHOR() {} 4814void MemIntrinsicSDNode::ANCHOR() {} 4815void CallSDNode::ANCHOR() {} 4816void CvtRndSatSDNode::ANCHOR() {} 4817 4818HandleSDNode::~HandleSDNode() { 4819 DropOperands(); 4820} 4821 4822GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4823 MVT VT, int64_t o) 4824 : SDNode(isa<GlobalVariable>(GA) && 4825 cast<GlobalVariable>(GA)->isThreadLocal() ? 4826 // Thread Local 4827 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4828 // Non Thread Local 4829 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4830 getSDVTList(VT)), Offset(o) { 4831 TheGlobal = const_cast<GlobalValue*>(GA); 4832} 4833 4834MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt, 4835 const Value *srcValue, int SVO, 4836 unsigned alignment, bool vol) 4837 : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4838 Flags(encodeMemSDNodeFlags(vol, alignment)) { 4839 4840 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4841 assert(getAlignment() == alignment && "Alignment representation error!"); 4842 assert(isVolatile() == vol && "Volatile representation error!"); 4843} 4844 4845MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, 4846 unsigned NumOps, MVT memvt, const Value *srcValue, 4847 int SVO, unsigned alignment, bool vol) 4848 : SDNode(Opc, VTs, Ops, NumOps), 4849 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4850 Flags(vol | ((Log2_32(alignment) + 1) << 1)) { 4851 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4852 assert(getAlignment() == alignment && "Alignment representation error!"); 4853 assert(isVolatile() == vol && "Volatile representation error!"); 4854} 4855 4856/// getMemOperand - Return a MachineMemOperand object describing the memory 4857/// reference performed by this memory reference. 4858MachineMemOperand MemSDNode::getMemOperand() const { 4859 int Flags = 0; 4860 if (isa<LoadSDNode>(this)) 4861 Flags = MachineMemOperand::MOLoad; 4862 else if (isa<StoreSDNode>(this)) 4863 Flags = MachineMemOperand::MOStore; 4864 else if (isa<AtomicSDNode>(this)) { 4865 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4866 } 4867 else { 4868 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4869 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4870 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4871 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4872 } 4873 4874 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4875 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4876 4877 // Check if the memory reference references a frame index 4878 const FrameIndexSDNode *FI = 4879 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4880 if (!getSrcValue() && FI) 4881 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4882 Flags, 0, Size, getAlignment()); 4883 else 4884 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4885 Size, getAlignment()); 4886} 4887 4888/// Profile - Gather unique data for the node. 4889/// 4890void SDNode::Profile(FoldingSetNodeID &ID) const { 4891 AddNodeIDNode(ID, this); 4892} 4893 4894/// getValueTypeList - Return a pointer to the specified value type. 4895/// 4896const MVT *SDNode::getValueTypeList(MVT VT) { 4897 if (VT.isExtended()) { 4898 static std::set<MVT, MVT::compareRawBits> EVTs; 4899 return &(*EVTs.insert(VT).first); 4900 } else { 4901 static MVT VTs[MVT::LAST_VALUETYPE]; 4902 VTs[VT.getSimpleVT()] = VT; 4903 return &VTs[VT.getSimpleVT()]; 4904 } 4905} 4906 4907/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4908/// indicated value. This method ignores uses of other values defined by this 4909/// operation. 4910bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4911 assert(Value < getNumValues() && "Bad value!"); 4912 4913 // TODO: Only iterate over uses of a given value of the node 4914 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4915 if (UI.getUse().getSDValue().getResNo() == Value) { 4916 if (NUses == 0) 4917 return false; 4918 --NUses; 4919 } 4920 } 4921 4922 // Found exactly the right number of uses? 4923 return NUses == 0; 4924} 4925 4926 4927/// hasAnyUseOfValue - Return true if there are any use of the indicated 4928/// value. This method ignores uses of other values defined by this operation. 4929bool SDNode::hasAnyUseOfValue(unsigned Value) const { 4930 assert(Value < getNumValues() && "Bad value!"); 4931 4932 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 4933 if (UI.getUse().getSDValue().getResNo() == Value) 4934 return true; 4935 4936 return false; 4937} 4938 4939 4940/// isOnlyUserOf - Return true if this node is the only use of N. 4941/// 4942bool SDNode::isOnlyUserOf(SDNode *N) const { 4943 bool Seen = false; 4944 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 4945 SDNode *User = *I; 4946 if (User == this) 4947 Seen = true; 4948 else 4949 return false; 4950 } 4951 4952 return Seen; 4953} 4954 4955/// isOperand - Return true if this node is an operand of N. 4956/// 4957bool SDValue::isOperandOf(SDNode *N) const { 4958 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4959 if (*this == N->getOperand(i)) 4960 return true; 4961 return false; 4962} 4963 4964bool SDNode::isOperandOf(SDNode *N) const { 4965 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 4966 if (this == N->OperandList[i].getVal()) 4967 return true; 4968 return false; 4969} 4970 4971/// reachesChainWithoutSideEffects - Return true if this operand (which must 4972/// be a chain) reaches the specified operand without crossing any 4973/// side-effecting instructions. In practice, this looks through token 4974/// factors and non-volatile loads. In order to remain efficient, this only 4975/// looks a couple of nodes in, it does not do an exhaustive search. 4976bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 4977 unsigned Depth) const { 4978 if (*this == Dest) return true; 4979 4980 // Don't search too deeply, we just want to be able to see through 4981 // TokenFactor's etc. 4982 if (Depth == 0) return false; 4983 4984 // If this is a token factor, all inputs to the TF happen in parallel. If any 4985 // of the operands of the TF reach dest, then we can do the xform. 4986 if (getOpcode() == ISD::TokenFactor) { 4987 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 4988 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 4989 return true; 4990 return false; 4991 } 4992 4993 // Loads don't have side effects, look through them. 4994 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 4995 if (!Ld->isVolatile()) 4996 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 4997 } 4998 return false; 4999} 5000 5001 5002static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 5003 SmallPtrSet<SDNode *, 32> &Visited) { 5004 if (found || !Visited.insert(N)) 5005 return; 5006 5007 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 5008 SDNode *Op = N->getOperand(i).getNode(); 5009 if (Op == P) { 5010 found = true; 5011 return; 5012 } 5013 findPredecessor(Op, P, found, Visited); 5014 } 5015} 5016 5017/// isPredecessorOf - Return true if this node is a predecessor of N. This node 5018/// is either an operand of N or it can be reached by recursively traversing 5019/// up the operands. 5020/// NOTE: this is an expensive method. Use it carefully. 5021bool SDNode::isPredecessorOf(SDNode *N) const { 5022 SmallPtrSet<SDNode *, 32> Visited; 5023 bool found = false; 5024 findPredecessor(N, this, found, Visited); 5025 return found; 5026} 5027 5028uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 5029 assert(Num < NumOperands && "Invalid child # of SDNode!"); 5030 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 5031} 5032 5033std::string SDNode::getOperationName(const SelectionDAG *G) const { 5034 switch (getOpcode()) { 5035 default: 5036 if (getOpcode() < ISD::BUILTIN_OP_END) 5037 return "<<Unknown DAG Node>>"; 5038 if (isMachineOpcode()) { 5039 if (G) 5040 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 5041 if (getMachineOpcode() < TII->getNumOpcodes()) 5042 return TII->get(getMachineOpcode()).getName(); 5043 return "<<Unknown Machine Node>>"; 5044 } 5045 if (G) { 5046 TargetLowering &TLI = G->getTargetLoweringInfo(); 5047 const char *Name = TLI.getTargetNodeName(getOpcode()); 5048 if (Name) return Name; 5049 return "<<Unknown Target Node>>"; 5050 } 5051 return "<<Unknown Node>>"; 5052 5053#ifndef NDEBUG 5054 case ISD::DELETED_NODE: 5055 return "<<Deleted Node!>>"; 5056#endif 5057 case ISD::PREFETCH: return "Prefetch"; 5058 case ISD::MEMBARRIER: return "MemBarrier"; 5059 case ISD::ATOMIC_CMP_SWAP_8: return "AtomicCmpSwap8"; 5060 case ISD::ATOMIC_SWAP_8: return "AtomicSwap8"; 5061 case ISD::ATOMIC_LOAD_ADD_8: return "AtomicLoadAdd8"; 5062 case ISD::ATOMIC_LOAD_SUB_8: return "AtomicLoadSub8"; 5063 case ISD::ATOMIC_LOAD_AND_8: return "AtomicLoadAnd8"; 5064 case ISD::ATOMIC_LOAD_OR_8: return "AtomicLoadOr8"; 5065 case ISD::ATOMIC_LOAD_XOR_8: return "AtomicLoadXor8"; 5066 case ISD::ATOMIC_LOAD_NAND_8: return "AtomicLoadNand8"; 5067 case ISD::ATOMIC_LOAD_MIN_8: return "AtomicLoadMin8"; 5068 case ISD::ATOMIC_LOAD_MAX_8: return "AtomicLoadMax8"; 5069 case ISD::ATOMIC_LOAD_UMIN_8: return "AtomicLoadUMin8"; 5070 case ISD::ATOMIC_LOAD_UMAX_8: return "AtomicLoadUMax8"; 5071 case ISD::ATOMIC_CMP_SWAP_16: return "AtomicCmpSwap16"; 5072 case ISD::ATOMIC_SWAP_16: return "AtomicSwap16"; 5073 case ISD::ATOMIC_LOAD_ADD_16: return "AtomicLoadAdd16"; 5074 case ISD::ATOMIC_LOAD_SUB_16: return "AtomicLoadSub16"; 5075 case ISD::ATOMIC_LOAD_AND_16: return "AtomicLoadAnd16"; 5076 case ISD::ATOMIC_LOAD_OR_16: return "AtomicLoadOr16"; 5077 case ISD::ATOMIC_LOAD_XOR_16: return "AtomicLoadXor16"; 5078 case ISD::ATOMIC_LOAD_NAND_16: return "AtomicLoadNand16"; 5079 case ISD::ATOMIC_LOAD_MIN_16: return "AtomicLoadMin16"; 5080 case ISD::ATOMIC_LOAD_MAX_16: return "AtomicLoadMax16"; 5081 case ISD::ATOMIC_LOAD_UMIN_16: return "AtomicLoadUMin16"; 5082 case ISD::ATOMIC_LOAD_UMAX_16: return "AtomicLoadUMax16"; 5083 case ISD::ATOMIC_CMP_SWAP_32: return "AtomicCmpSwap32"; 5084 case ISD::ATOMIC_SWAP_32: return "AtomicSwap32"; 5085 case ISD::ATOMIC_LOAD_ADD_32: return "AtomicLoadAdd32"; 5086 case ISD::ATOMIC_LOAD_SUB_32: return "AtomicLoadSub32"; 5087 case ISD::ATOMIC_LOAD_AND_32: return "AtomicLoadAnd32"; 5088 case ISD::ATOMIC_LOAD_OR_32: return "AtomicLoadOr32"; 5089 case ISD::ATOMIC_LOAD_XOR_32: return "AtomicLoadXor32"; 5090 case ISD::ATOMIC_LOAD_NAND_32: return "AtomicLoadNand32"; 5091 case ISD::ATOMIC_LOAD_MIN_32: return "AtomicLoadMin32"; 5092 case ISD::ATOMIC_LOAD_MAX_32: return "AtomicLoadMax32"; 5093 case ISD::ATOMIC_LOAD_UMIN_32: return "AtomicLoadUMin32"; 5094 case ISD::ATOMIC_LOAD_UMAX_32: return "AtomicLoadUMax32"; 5095 case ISD::ATOMIC_CMP_SWAP_64: return "AtomicCmpSwap64"; 5096 case ISD::ATOMIC_SWAP_64: return "AtomicSwap64"; 5097 case ISD::ATOMIC_LOAD_ADD_64: return "AtomicLoadAdd64"; 5098 case ISD::ATOMIC_LOAD_SUB_64: return "AtomicLoadSub64"; 5099 case ISD::ATOMIC_LOAD_AND_64: return "AtomicLoadAnd64"; 5100 case ISD::ATOMIC_LOAD_OR_64: return "AtomicLoadOr64"; 5101 case ISD::ATOMIC_LOAD_XOR_64: return "AtomicLoadXor64"; 5102 case ISD::ATOMIC_LOAD_NAND_64: return "AtomicLoadNand64"; 5103 case ISD::ATOMIC_LOAD_MIN_64: return "AtomicLoadMin64"; 5104 case ISD::ATOMIC_LOAD_MAX_64: return "AtomicLoadMax64"; 5105 case ISD::ATOMIC_LOAD_UMIN_64: return "AtomicLoadUMin64"; 5106 case ISD::ATOMIC_LOAD_UMAX_64: return "AtomicLoadUMax64"; 5107 case ISD::PCMARKER: return "PCMarker"; 5108 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5109 case ISD::SRCVALUE: return "SrcValue"; 5110 case ISD::MEMOPERAND: return "MemOperand"; 5111 case ISD::EntryToken: return "EntryToken"; 5112 case ISD::TokenFactor: return "TokenFactor"; 5113 case ISD::AssertSext: return "AssertSext"; 5114 case ISD::AssertZext: return "AssertZext"; 5115 5116 case ISD::BasicBlock: return "BasicBlock"; 5117 case ISD::ARG_FLAGS: return "ArgFlags"; 5118 case ISD::VALUETYPE: return "ValueType"; 5119 case ISD::Register: return "Register"; 5120 5121 case ISD::Constant: return "Constant"; 5122 case ISD::ConstantFP: return "ConstantFP"; 5123 case ISD::GlobalAddress: return "GlobalAddress"; 5124 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5125 case ISD::FrameIndex: return "FrameIndex"; 5126 case ISD::JumpTable: return "JumpTable"; 5127 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5128 case ISD::RETURNADDR: return "RETURNADDR"; 5129 case ISD::FRAMEADDR: return "FRAMEADDR"; 5130 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5131 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5132 case ISD::EHSELECTION: return "EHSELECTION"; 5133 case ISD::EH_RETURN: return "EH_RETURN"; 5134 case ISD::ConstantPool: return "ConstantPool"; 5135 case ISD::ExternalSymbol: return "ExternalSymbol"; 5136 case ISD::INTRINSIC_WO_CHAIN: { 5137 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5138 return Intrinsic::getName((Intrinsic::ID)IID); 5139 } 5140 case ISD::INTRINSIC_VOID: 5141 case ISD::INTRINSIC_W_CHAIN: { 5142 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5143 return Intrinsic::getName((Intrinsic::ID)IID); 5144 } 5145 5146 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5147 case ISD::TargetConstant: return "TargetConstant"; 5148 case ISD::TargetConstantFP:return "TargetConstantFP"; 5149 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5150 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5151 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5152 case ISD::TargetJumpTable: return "TargetJumpTable"; 5153 case ISD::TargetConstantPool: return "TargetConstantPool"; 5154 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5155 5156 case ISD::CopyToReg: return "CopyToReg"; 5157 case ISD::CopyFromReg: return "CopyFromReg"; 5158 case ISD::UNDEF: return "undef"; 5159 case ISD::MERGE_VALUES: return "merge_values"; 5160 case ISD::INLINEASM: return "inlineasm"; 5161 case ISD::DBG_LABEL: return "dbg_label"; 5162 case ISD::EH_LABEL: return "eh_label"; 5163 case ISD::DECLARE: return "declare"; 5164 case ISD::HANDLENODE: return "handlenode"; 5165 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5166 case ISD::CALL: return "call"; 5167 5168 // Unary operators 5169 case ISD::FABS: return "fabs"; 5170 case ISD::FNEG: return "fneg"; 5171 case ISD::FSQRT: return "fsqrt"; 5172 case ISD::FSIN: return "fsin"; 5173 case ISD::FCOS: return "fcos"; 5174 case ISD::FPOWI: return "fpowi"; 5175 case ISD::FPOW: return "fpow"; 5176 case ISD::FTRUNC: return "ftrunc"; 5177 case ISD::FFLOOR: return "ffloor"; 5178 case ISD::FCEIL: return "fceil"; 5179 case ISD::FRINT: return "frint"; 5180 case ISD::FNEARBYINT: return "fnearbyint"; 5181 5182 // Binary operators 5183 case ISD::ADD: return "add"; 5184 case ISD::SUB: return "sub"; 5185 case ISD::MUL: return "mul"; 5186 case ISD::MULHU: return "mulhu"; 5187 case ISD::MULHS: return "mulhs"; 5188 case ISD::SDIV: return "sdiv"; 5189 case ISD::UDIV: return "udiv"; 5190 case ISD::SREM: return "srem"; 5191 case ISD::UREM: return "urem"; 5192 case ISD::SMUL_LOHI: return "smul_lohi"; 5193 case ISD::UMUL_LOHI: return "umul_lohi"; 5194 case ISD::SDIVREM: return "sdivrem"; 5195 case ISD::UDIVREM: return "udivrem"; 5196 case ISD::AND: return "and"; 5197 case ISD::OR: return "or"; 5198 case ISD::XOR: return "xor"; 5199 case ISD::SHL: return "shl"; 5200 case ISD::SRA: return "sra"; 5201 case ISD::SRL: return "srl"; 5202 case ISD::ROTL: return "rotl"; 5203 case ISD::ROTR: return "rotr"; 5204 case ISD::FADD: return "fadd"; 5205 case ISD::FSUB: return "fsub"; 5206 case ISD::FMUL: return "fmul"; 5207 case ISD::FDIV: return "fdiv"; 5208 case ISD::FREM: return "frem"; 5209 case ISD::FCOPYSIGN: return "fcopysign"; 5210 case ISD::FGETSIGN: return "fgetsign"; 5211 5212 case ISD::SETCC: return "setcc"; 5213 case ISD::VSETCC: return "vsetcc"; 5214 case ISD::SELECT: return "select"; 5215 case ISD::SELECT_CC: return "select_cc"; 5216 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5217 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5218 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5219 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5220 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5221 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5222 case ISD::CARRY_FALSE: return "carry_false"; 5223 case ISD::ADDC: return "addc"; 5224 case ISD::ADDE: return "adde"; 5225 case ISD::SADDO: return "saddo"; 5226 case ISD::UADDO: return "uaddo"; 5227 case ISD::SSUBO: return "ssubo"; 5228 case ISD::USUBO: return "usubo"; 5229 case ISD::SMULO: return "smulo"; 5230 case ISD::UMULO: return "umulo"; 5231 case ISD::SUBC: return "subc"; 5232 case ISD::SUBE: return "sube"; 5233 case ISD::SHL_PARTS: return "shl_parts"; 5234 case ISD::SRA_PARTS: return "sra_parts"; 5235 case ISD::SRL_PARTS: return "srl_parts"; 5236 5237 case ISD::EXTRACT_SUBREG: return "extract_subreg"; 5238 case ISD::INSERT_SUBREG: return "insert_subreg"; 5239 5240 // Conversion operators. 5241 case ISD::SIGN_EXTEND: return "sign_extend"; 5242 case ISD::ZERO_EXTEND: return "zero_extend"; 5243 case ISD::ANY_EXTEND: return "any_extend"; 5244 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5245 case ISD::TRUNCATE: return "truncate"; 5246 case ISD::FP_ROUND: return "fp_round"; 5247 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5248 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5249 case ISD::FP_EXTEND: return "fp_extend"; 5250 5251 case ISD::SINT_TO_FP: return "sint_to_fp"; 5252 case ISD::UINT_TO_FP: return "uint_to_fp"; 5253 case ISD::FP_TO_SINT: return "fp_to_sint"; 5254 case ISD::FP_TO_UINT: return "fp_to_uint"; 5255 case ISD::BIT_CONVERT: return "bit_convert"; 5256 5257 case ISD::CONVERT_RNDSAT: { 5258 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5259 default: assert(0 && "Unknown cvt code!"); 5260 case ISD::CVT_FF: return "cvt_ff"; 5261 case ISD::CVT_FS: return "cvt_fs"; 5262 case ISD::CVT_FU: return "cvt_fu"; 5263 case ISD::CVT_SF: return "cvt_sf"; 5264 case ISD::CVT_UF: return "cvt_uf"; 5265 case ISD::CVT_SS: return "cvt_ss"; 5266 case ISD::CVT_SU: return "cvt_su"; 5267 case ISD::CVT_US: return "cvt_us"; 5268 case ISD::CVT_UU: return "cvt_uu"; 5269 } 5270 } 5271 5272 // Control flow instructions 5273 case ISD::BR: return "br"; 5274 case ISD::BRIND: return "brind"; 5275 case ISD::BR_JT: return "br_jt"; 5276 case ISD::BRCOND: return "brcond"; 5277 case ISD::BR_CC: return "br_cc"; 5278 case ISD::RET: return "ret"; 5279 case ISD::CALLSEQ_START: return "callseq_start"; 5280 case ISD::CALLSEQ_END: return "callseq_end"; 5281 5282 // Other operators 5283 case ISD::LOAD: return "load"; 5284 case ISD::STORE: return "store"; 5285 case ISD::VAARG: return "vaarg"; 5286 case ISD::VACOPY: return "vacopy"; 5287 case ISD::VAEND: return "vaend"; 5288 case ISD::VASTART: return "vastart"; 5289 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5290 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5291 case ISD::BUILD_PAIR: return "build_pair"; 5292 case ISD::STACKSAVE: return "stacksave"; 5293 case ISD::STACKRESTORE: return "stackrestore"; 5294 case ISD::TRAP: return "trap"; 5295 5296 // Bit manipulation 5297 case ISD::BSWAP: return "bswap"; 5298 case ISD::CTPOP: return "ctpop"; 5299 case ISD::CTTZ: return "cttz"; 5300 case ISD::CTLZ: return "ctlz"; 5301 5302 // Debug info 5303 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5304 case ISD::DEBUG_LOC: return "debug_loc"; 5305 5306 // Trampolines 5307 case ISD::TRAMPOLINE: return "trampoline"; 5308 5309 case ISD::CONDCODE: 5310 switch (cast<CondCodeSDNode>(this)->get()) { 5311 default: assert(0 && "Unknown setcc condition!"); 5312 case ISD::SETOEQ: return "setoeq"; 5313 case ISD::SETOGT: return "setogt"; 5314 case ISD::SETOGE: return "setoge"; 5315 case ISD::SETOLT: return "setolt"; 5316 case ISD::SETOLE: return "setole"; 5317 case ISD::SETONE: return "setone"; 5318 5319 case ISD::SETO: return "seto"; 5320 case ISD::SETUO: return "setuo"; 5321 case ISD::SETUEQ: return "setue"; 5322 case ISD::SETUGT: return "setugt"; 5323 case ISD::SETUGE: return "setuge"; 5324 case ISD::SETULT: return "setult"; 5325 case ISD::SETULE: return "setule"; 5326 case ISD::SETUNE: return "setune"; 5327 5328 case ISD::SETEQ: return "seteq"; 5329 case ISD::SETGT: return "setgt"; 5330 case ISD::SETGE: return "setge"; 5331 case ISD::SETLT: return "setlt"; 5332 case ISD::SETLE: return "setle"; 5333 case ISD::SETNE: return "setne"; 5334 } 5335 } 5336} 5337 5338const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5339 switch (AM) { 5340 default: 5341 return ""; 5342 case ISD::PRE_INC: 5343 return "<pre-inc>"; 5344 case ISD::PRE_DEC: 5345 return "<pre-dec>"; 5346 case ISD::POST_INC: 5347 return "<post-inc>"; 5348 case ISD::POST_DEC: 5349 return "<post-dec>"; 5350 } 5351} 5352 5353std::string ISD::ArgFlagsTy::getArgFlagsString() { 5354 std::string S = "< "; 5355 5356 if (isZExt()) 5357 S += "zext "; 5358 if (isSExt()) 5359 S += "sext "; 5360 if (isInReg()) 5361 S += "inreg "; 5362 if (isSRet()) 5363 S += "sret "; 5364 if (isByVal()) 5365 S += "byval "; 5366 if (isNest()) 5367 S += "nest "; 5368 if (getByValAlign()) 5369 S += "byval-align:" + utostr(getByValAlign()) + " "; 5370 if (getOrigAlign()) 5371 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5372 if (getByValSize()) 5373 S += "byval-size:" + utostr(getByValSize()) + " "; 5374 return S + ">"; 5375} 5376 5377void SDNode::dump() const { dump(0); } 5378void SDNode::dump(const SelectionDAG *G) const { 5379 print(errs(), G); 5380 errs().flush(); 5381} 5382 5383void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5384 OS << (void*)this << ": "; 5385 5386 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5387 if (i) OS << ","; 5388 if (getValueType(i) == MVT::Other) 5389 OS << "ch"; 5390 else 5391 OS << getValueType(i).getMVTString(); 5392 } 5393 OS << " = " << getOperationName(G); 5394 5395 OS << " "; 5396 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5397 if (i) OS << ", "; 5398 OS << (void*)getOperand(i).getNode(); 5399 if (unsigned RN = getOperand(i).getResNo()) 5400 OS << ":" << RN; 5401 } 5402 5403 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5404 SDNode *Mask = getOperand(2).getNode(); 5405 OS << "<"; 5406 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 5407 if (i) OS << ","; 5408 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 5409 OS << "u"; 5410 else 5411 OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue(); 5412 } 5413 OS << ">"; 5414 } 5415 5416 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5417 OS << '<' << CSDN->getAPIntValue() << '>'; 5418 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5419 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5420 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5421 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5422 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5423 else { 5424 OS << "<APFloat("; 5425 CSDN->getValueAPF().bitcastToAPInt().dump(); 5426 OS << ")>"; 5427 } 5428 } else if (const GlobalAddressSDNode *GADN = 5429 dyn_cast<GlobalAddressSDNode>(this)) { 5430 int64_t offset = GADN->getOffset(); 5431 OS << '<'; 5432 WriteAsOperand(OS, GADN->getGlobal()); 5433 OS << '>'; 5434 if (offset > 0) 5435 OS << " + " << offset; 5436 else 5437 OS << " " << offset; 5438 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5439 OS << "<" << FIDN->getIndex() << ">"; 5440 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5441 OS << "<" << JTDN->getIndex() << ">"; 5442 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5443 int offset = CP->getOffset(); 5444 if (CP->isMachineConstantPoolEntry()) 5445 OS << "<" << *CP->getMachineCPVal() << ">"; 5446 else 5447 OS << "<" << *CP->getConstVal() << ">"; 5448 if (offset > 0) 5449 OS << " + " << offset; 5450 else 5451 OS << " " << offset; 5452 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5453 OS << "<"; 5454 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5455 if (LBB) 5456 OS << LBB->getName() << " "; 5457 OS << (const void*)BBDN->getBasicBlock() << ">"; 5458 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5459 if (G && R->getReg() && 5460 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5461 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5462 } else { 5463 OS << " #" << R->getReg(); 5464 } 5465 } else if (const ExternalSymbolSDNode *ES = 5466 dyn_cast<ExternalSymbolSDNode>(this)) { 5467 OS << "'" << ES->getSymbol() << "'"; 5468 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5469 if (M->getValue()) 5470 OS << "<" << M->getValue() << ">"; 5471 else 5472 OS << "<null>"; 5473 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5474 if (M->MO.getValue()) 5475 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5476 else 5477 OS << "<null:" << M->MO.getOffset() << ">"; 5478 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5479 OS << N->getArgFlags().getArgFlagsString(); 5480 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5481 OS << ":" << N->getVT().getMVTString(); 5482 } 5483 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5484 const Value *SrcValue = LD->getSrcValue(); 5485 int SrcOffset = LD->getSrcValueOffset(); 5486 OS << " <"; 5487 if (SrcValue) 5488 OS << SrcValue; 5489 else 5490 OS << "null"; 5491 OS << ":" << SrcOffset << ">"; 5492 5493 bool doExt = true; 5494 switch (LD->getExtensionType()) { 5495 default: doExt = false; break; 5496 case ISD::EXTLOAD: OS << " <anyext "; break; 5497 case ISD::SEXTLOAD: OS << " <sext "; break; 5498 case ISD::ZEXTLOAD: OS << " <zext "; break; 5499 } 5500 if (doExt) 5501 OS << LD->getMemoryVT().getMVTString() << ">"; 5502 5503 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5504 if (*AM) 5505 OS << " " << AM; 5506 if (LD->isVolatile()) 5507 OS << " <volatile>"; 5508 OS << " alignment=" << LD->getAlignment(); 5509 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5510 const Value *SrcValue = ST->getSrcValue(); 5511 int SrcOffset = ST->getSrcValueOffset(); 5512 OS << " <"; 5513 if (SrcValue) 5514 OS << SrcValue; 5515 else 5516 OS << "null"; 5517 OS << ":" << SrcOffset << ">"; 5518 5519 if (ST->isTruncatingStore()) 5520 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5521 5522 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5523 if (*AM) 5524 OS << " " << AM; 5525 if (ST->isVolatile()) 5526 OS << " <volatile>"; 5527 OS << " alignment=" << ST->getAlignment(); 5528 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5529 const Value *SrcValue = AT->getSrcValue(); 5530 int SrcOffset = AT->getSrcValueOffset(); 5531 OS << " <"; 5532 if (SrcValue) 5533 OS << SrcValue; 5534 else 5535 OS << "null"; 5536 OS << ":" << SrcOffset << ">"; 5537 if (AT->isVolatile()) 5538 OS << " <volatile>"; 5539 OS << " alignment=" << AT->getAlignment(); 5540 } 5541} 5542 5543static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5544 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5545 if (N->getOperand(i).getNode()->hasOneUse()) 5546 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5547 else 5548 cerr << "\n" << std::string(indent+2, ' ') 5549 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5550 5551 5552 cerr << "\n" << std::string(indent, ' '); 5553 N->dump(G); 5554} 5555 5556void SelectionDAG::dump() const { 5557 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5558 5559 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5560 I != E; ++I) { 5561 const SDNode *N = I; 5562 if (!N->hasOneUse() && N != getRoot().getNode()) 5563 DumpNodes(N, 2, this); 5564 } 5565 5566 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5567 5568 cerr << "\n\n"; 5569} 5570 5571const Type *ConstantPoolSDNode::getType() const { 5572 if (isMachineConstantPoolEntry()) 5573 return Val.MachineCPVal->getType(); 5574 return Val.ConstVal->getType(); 5575} 5576