SelectionDAG.cpp revision 9901e73caec653599f27d04075961afe4a7c29a1
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetInstrInfo.h" 31#include "llvm/Target/TargetMachine.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/ADT/SetVector.h" 36#include "llvm/ADT/SmallPtrSet.h" 37#include "llvm/ADT/SmallSet.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/ADT/StringExtras.h" 40#include <algorithm> 41#include <cmath> 42using namespace llvm; 43 44/// makeVTList - Return an instance of the SDVTList struct initialized with the 45/// specified members. 46static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 47 SDVTList Res = {VTs, NumVTs}; 48 return Res; 49} 50 51static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 52 switch (VT.getSimpleVT()) { 53 default: assert(0 && "Unknown FP format"); 54 case MVT::f32: return &APFloat::IEEEsingle; 55 case MVT::f64: return &APFloat::IEEEdouble; 56 case MVT::f80: return &APFloat::x87DoubleExtended; 57 case MVT::f128: return &APFloat::IEEEquad; 58 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 59 } 60} 61 62SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 63 64//===----------------------------------------------------------------------===// 65// ConstantFPSDNode Class 66//===----------------------------------------------------------------------===// 67 68/// isExactlyValue - We don't rely on operator== working on double values, as 69/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 70/// As such, this method can be used to do an exact bit-for-bit comparison of 71/// two floating point values. 72bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 73 return getValueAPF().bitwiseIsEqual(V); 74} 75 76bool ConstantFPSDNode::isValueValidForType(MVT VT, 77 const APFloat& Val) { 78 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 79 80 // PPC long double cannot be converted to any other type. 81 if (VT == MVT::ppcf128 || 82 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 83 return false; 84 85 // convert modifies in place, so make a copy. 86 APFloat Val2 = APFloat(Val); 87 bool losesInfo; 88 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 89 &losesInfo); 90 return !losesInfo; 91} 92 93//===----------------------------------------------------------------------===// 94// ISD Namespace 95//===----------------------------------------------------------------------===// 96 97/// isBuildVectorAllOnes - Return true if the specified node is a 98/// BUILD_VECTOR where all of the elements are ~0 or undef. 99bool ISD::isBuildVectorAllOnes(const SDNode *N) { 100 // Look through a bit convert. 101 if (N->getOpcode() == ISD::BIT_CONVERT) 102 N = N->getOperand(0).getNode(); 103 104 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 105 106 unsigned i = 0, e = N->getNumOperands(); 107 108 // Skip over all of the undef values. 109 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 110 ++i; 111 112 // Do not accept an all-undef vector. 113 if (i == e) return false; 114 115 // Do not accept build_vectors that aren't all constants or which have non-~0 116 // elements. 117 SDValue NotZero = N->getOperand(i); 118 if (isa<ConstantSDNode>(NotZero)) { 119 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 120 return false; 121 } else if (isa<ConstantFPSDNode>(NotZero)) { 122 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 123 bitcastToAPInt().isAllOnesValue()) 124 return false; 125 } else 126 return false; 127 128 // Okay, we have at least one ~0 value, check to see if the rest match or are 129 // undefs. 130 for (++i; i != e; ++i) 131 if (N->getOperand(i) != NotZero && 132 N->getOperand(i).getOpcode() != ISD::UNDEF) 133 return false; 134 return true; 135} 136 137 138/// isBuildVectorAllZeros - Return true if the specified node is a 139/// BUILD_VECTOR where all of the elements are 0 or undef. 140bool ISD::isBuildVectorAllZeros(const SDNode *N) { 141 // Look through a bit convert. 142 if (N->getOpcode() == ISD::BIT_CONVERT) 143 N = N->getOperand(0).getNode(); 144 145 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 146 147 unsigned i = 0, e = N->getNumOperands(); 148 149 // Skip over all of the undef values. 150 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 151 ++i; 152 153 // Do not accept an all-undef vector. 154 if (i == e) return false; 155 156 // Do not accept build_vectors that aren't all constants or which have non-~0 157 // elements. 158 SDValue Zero = N->getOperand(i); 159 if (isa<ConstantSDNode>(Zero)) { 160 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 161 return false; 162 } else if (isa<ConstantFPSDNode>(Zero)) { 163 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 164 return false; 165 } else 166 return false; 167 168 // Okay, we have at least one ~0 value, check to see if the rest match or are 169 // undefs. 170 for (++i; i != e; ++i) 171 if (N->getOperand(i) != Zero && 172 N->getOperand(i).getOpcode() != ISD::UNDEF) 173 return false; 174 return true; 175} 176 177/// isScalarToVector - Return true if the specified node is a 178/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 179/// element is not an undef. 180bool ISD::isScalarToVector(const SDNode *N) { 181 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 182 return true; 183 184 if (N->getOpcode() != ISD::BUILD_VECTOR) 185 return false; 186 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 187 return false; 188 unsigned NumElems = N->getNumOperands(); 189 for (unsigned i = 1; i < NumElems; ++i) { 190 SDValue V = N->getOperand(i); 191 if (V.getOpcode() != ISD::UNDEF) 192 return false; 193 } 194 return true; 195} 196 197 198/// isDebugLabel - Return true if the specified node represents a debug 199/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 200bool ISD::isDebugLabel(const SDNode *N) { 201 SDValue Zero; 202 if (N->getOpcode() == ISD::DBG_LABEL) 203 return true; 204 if (N->isMachineOpcode() && 205 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 206 return true; 207 return false; 208} 209 210/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 211/// when given the operation for (X op Y). 212ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 213 // To perform this operation, we just need to swap the L and G bits of the 214 // operation. 215 unsigned OldL = (Operation >> 2) & 1; 216 unsigned OldG = (Operation >> 1) & 1; 217 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 218 (OldL << 1) | // New G bit 219 (OldG << 2)); // New L bit. 220} 221 222/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 223/// 'op' is a valid SetCC operation. 224ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 225 unsigned Operation = Op; 226 if (isInteger) 227 Operation ^= 7; // Flip L, G, E bits, but not U. 228 else 229 Operation ^= 15; // Flip all of the condition bits. 230 231 if (Operation > ISD::SETTRUE2) 232 Operation &= ~8; // Don't let N and U bits get set. 233 234 return ISD::CondCode(Operation); 235} 236 237 238/// isSignedOp - For an integer comparison, return 1 if the comparison is a 239/// signed operation and 2 if the result is an unsigned comparison. Return zero 240/// if the operation does not depend on the sign of the input (setne and seteq). 241static int isSignedOp(ISD::CondCode Opcode) { 242 switch (Opcode) { 243 default: assert(0 && "Illegal integer setcc operation!"); 244 case ISD::SETEQ: 245 case ISD::SETNE: return 0; 246 case ISD::SETLT: 247 case ISD::SETLE: 248 case ISD::SETGT: 249 case ISD::SETGE: return 1; 250 case ISD::SETULT: 251 case ISD::SETULE: 252 case ISD::SETUGT: 253 case ISD::SETUGE: return 2; 254 } 255} 256 257/// getSetCCOrOperation - Return the result of a logical OR between different 258/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 259/// returns SETCC_INVALID if it is not possible to represent the resultant 260/// comparison. 261ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 262 bool isInteger) { 263 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 264 // Cannot fold a signed integer setcc with an unsigned integer setcc. 265 return ISD::SETCC_INVALID; 266 267 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 268 269 // If the N and U bits get set then the resultant comparison DOES suddenly 270 // care about orderedness, and is true when ordered. 271 if (Op > ISD::SETTRUE2) 272 Op &= ~16; // Clear the U bit if the N bit is set. 273 274 // Canonicalize illegal integer setcc's. 275 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 276 Op = ISD::SETNE; 277 278 return ISD::CondCode(Op); 279} 280 281/// getSetCCAndOperation - Return the result of a logical AND between different 282/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 283/// function returns zero if it is not possible to represent the resultant 284/// comparison. 285ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 286 bool isInteger) { 287 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 288 // Cannot fold a signed setcc with an unsigned setcc. 289 return ISD::SETCC_INVALID; 290 291 // Combine all of the condition bits. 292 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 293 294 // Canonicalize illegal integer setcc's. 295 if (isInteger) { 296 switch (Result) { 297 default: break; 298 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 299 case ISD::SETOEQ: // SETEQ & SETU[LG]E 300 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 301 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 302 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 303 } 304 } 305 306 return Result; 307} 308 309const TargetMachine &SelectionDAG::getTarget() const { 310 return MF->getTarget(); 311} 312 313//===----------------------------------------------------------------------===// 314// SDNode Profile Support 315//===----------------------------------------------------------------------===// 316 317/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 318/// 319static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 320 ID.AddInteger(OpC); 321} 322 323/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 324/// solely with their pointer. 325static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 326 ID.AddPointer(VTList.VTs); 327} 328 329/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 330/// 331static void AddNodeIDOperands(FoldingSetNodeID &ID, 332 const SDValue *Ops, unsigned NumOps) { 333 for (; NumOps; --NumOps, ++Ops) { 334 ID.AddPointer(Ops->getNode()); 335 ID.AddInteger(Ops->getResNo()); 336 } 337} 338 339/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 340/// 341static void AddNodeIDOperands(FoldingSetNodeID &ID, 342 const SDUse *Ops, unsigned NumOps) { 343 for (; NumOps; --NumOps, ++Ops) { 344 ID.AddPointer(Ops->getVal()); 345 ID.AddInteger(Ops->getSDValue().getResNo()); 346 } 347} 348 349static void AddNodeIDNode(FoldingSetNodeID &ID, 350 unsigned short OpC, SDVTList VTList, 351 const SDValue *OpList, unsigned N) { 352 AddNodeIDOpcode(ID, OpC); 353 AddNodeIDValueTypes(ID, VTList); 354 AddNodeIDOperands(ID, OpList, N); 355} 356 357/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 358/// the NodeID data. 359static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 360 switch (N->getOpcode()) { 361 default: break; // Normal nodes don't need extra info. 362 case ISD::ARG_FLAGS: 363 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 364 break; 365 case ISD::TargetConstant: 366 case ISD::Constant: 367 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 368 break; 369 case ISD::TargetConstantFP: 370 case ISD::ConstantFP: { 371 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 372 break; 373 } 374 case ISD::TargetGlobalAddress: 375 case ISD::GlobalAddress: 376 case ISD::TargetGlobalTLSAddress: 377 case ISD::GlobalTLSAddress: { 378 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 379 ID.AddPointer(GA->getGlobal()); 380 ID.AddInteger(GA->getOffset()); 381 break; 382 } 383 case ISD::BasicBlock: 384 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 385 break; 386 case ISD::Register: 387 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 388 break; 389 case ISD::DBG_STOPPOINT: { 390 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 391 ID.AddInteger(DSP->getLine()); 392 ID.AddInteger(DSP->getColumn()); 393 ID.AddPointer(DSP->getCompileUnit()); 394 break; 395 } 396 case ISD::SRCVALUE: 397 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 398 break; 399 case ISD::MEMOPERAND: { 400 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 401 MO.Profile(ID); 402 break; 403 } 404 case ISD::FrameIndex: 405 case ISD::TargetFrameIndex: 406 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 407 break; 408 case ISD::JumpTable: 409 case ISD::TargetJumpTable: 410 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 411 break; 412 case ISD::ConstantPool: 413 case ISD::TargetConstantPool: { 414 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 415 ID.AddInteger(CP->getAlignment()); 416 ID.AddInteger(CP->getOffset()); 417 if (CP->isMachineConstantPoolEntry()) 418 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 419 else 420 ID.AddPointer(CP->getConstVal()); 421 break; 422 } 423 case ISD::CALL: { 424 const CallSDNode *Call = cast<CallSDNode>(N); 425 ID.AddInteger(Call->getCallingConv()); 426 ID.AddInteger(Call->isVarArg()); 427 break; 428 } 429 case ISD::LOAD: { 430 const LoadSDNode *LD = cast<LoadSDNode>(N); 431 ID.AddInteger(LD->getAddressingMode()); 432 ID.AddInteger(LD->getExtensionType()); 433 ID.AddInteger(LD->getMemoryVT().getRawBits()); 434 ID.AddInteger(LD->getRawFlags()); 435 break; 436 } 437 case ISD::STORE: { 438 const StoreSDNode *ST = cast<StoreSDNode>(N); 439 ID.AddInteger(ST->getAddressingMode()); 440 ID.AddInteger(ST->isTruncatingStore()); 441 ID.AddInteger(ST->getMemoryVT().getRawBits()); 442 ID.AddInteger(ST->getRawFlags()); 443 break; 444 } 445 case ISD::ATOMIC_CMP_SWAP_8: 446 case ISD::ATOMIC_SWAP_8: 447 case ISD::ATOMIC_LOAD_ADD_8: 448 case ISD::ATOMIC_LOAD_SUB_8: 449 case ISD::ATOMIC_LOAD_AND_8: 450 case ISD::ATOMIC_LOAD_OR_8: 451 case ISD::ATOMIC_LOAD_XOR_8: 452 case ISD::ATOMIC_LOAD_NAND_8: 453 case ISD::ATOMIC_LOAD_MIN_8: 454 case ISD::ATOMIC_LOAD_MAX_8: 455 case ISD::ATOMIC_LOAD_UMIN_8: 456 case ISD::ATOMIC_LOAD_UMAX_8: 457 case ISD::ATOMIC_CMP_SWAP_16: 458 case ISD::ATOMIC_SWAP_16: 459 case ISD::ATOMIC_LOAD_ADD_16: 460 case ISD::ATOMIC_LOAD_SUB_16: 461 case ISD::ATOMIC_LOAD_AND_16: 462 case ISD::ATOMIC_LOAD_OR_16: 463 case ISD::ATOMIC_LOAD_XOR_16: 464 case ISD::ATOMIC_LOAD_NAND_16: 465 case ISD::ATOMIC_LOAD_MIN_16: 466 case ISD::ATOMIC_LOAD_MAX_16: 467 case ISD::ATOMIC_LOAD_UMIN_16: 468 case ISD::ATOMIC_LOAD_UMAX_16: 469 case ISD::ATOMIC_CMP_SWAP_32: 470 case ISD::ATOMIC_SWAP_32: 471 case ISD::ATOMIC_LOAD_ADD_32: 472 case ISD::ATOMIC_LOAD_SUB_32: 473 case ISD::ATOMIC_LOAD_AND_32: 474 case ISD::ATOMIC_LOAD_OR_32: 475 case ISD::ATOMIC_LOAD_XOR_32: 476 case ISD::ATOMIC_LOAD_NAND_32: 477 case ISD::ATOMIC_LOAD_MIN_32: 478 case ISD::ATOMIC_LOAD_MAX_32: 479 case ISD::ATOMIC_LOAD_UMIN_32: 480 case ISD::ATOMIC_LOAD_UMAX_32: 481 case ISD::ATOMIC_CMP_SWAP_64: 482 case ISD::ATOMIC_SWAP_64: 483 case ISD::ATOMIC_LOAD_ADD_64: 484 case ISD::ATOMIC_LOAD_SUB_64: 485 case ISD::ATOMIC_LOAD_AND_64: 486 case ISD::ATOMIC_LOAD_OR_64: 487 case ISD::ATOMIC_LOAD_XOR_64: 488 case ISD::ATOMIC_LOAD_NAND_64: 489 case ISD::ATOMIC_LOAD_MIN_64: 490 case ISD::ATOMIC_LOAD_MAX_64: 491 case ISD::ATOMIC_LOAD_UMIN_64: 492 case ISD::ATOMIC_LOAD_UMAX_64: { 493 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 494 ID.AddInteger(AT->getRawFlags()); 495 break; 496 } 497 } // end switch (N->getOpcode()) 498} 499 500/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 501/// data. 502static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 503 AddNodeIDOpcode(ID, N->getOpcode()); 504 // Add the return value info. 505 AddNodeIDValueTypes(ID, N->getVTList()); 506 // Add the operand info. 507 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 508 509 // Handle SDNode leafs with special info. 510 AddNodeIDCustom(ID, N); 511} 512 513/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 514/// the CSE map that carries both alignment and volatility information. 515/// 516static inline unsigned 517encodeMemSDNodeFlags(bool isVolatile, unsigned Alignment) { 518 return isVolatile | ((Log2_32(Alignment) + 1) << 1); 519} 520 521//===----------------------------------------------------------------------===// 522// SelectionDAG Class 523//===----------------------------------------------------------------------===// 524 525/// doNotCSE - Return true if CSE should not be performed for this node. 526static bool doNotCSE(SDNode *N) { 527 if (N->getValueType(0) == MVT::Flag) 528 return true; // Never CSE anything that produces a flag. 529 530 switch (N->getOpcode()) { 531 default: break; 532 case ISD::HANDLENODE: 533 case ISD::DBG_LABEL: 534 case ISD::DBG_STOPPOINT: 535 case ISD::EH_LABEL: 536 case ISD::DECLARE: 537 return true; // Never CSE these nodes. 538 } 539 540 // Check that remaining values produced are not flags. 541 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 542 if (N->getValueType(i) == MVT::Flag) 543 return true; // Never CSE anything that produces a flag. 544 545 return false; 546} 547 548/// RemoveDeadNodes - This method deletes all unreachable nodes in the 549/// SelectionDAG. 550void SelectionDAG::RemoveDeadNodes() { 551 // Create a dummy node (which is not added to allnodes), that adds a reference 552 // to the root node, preventing it from being deleted. 553 HandleSDNode Dummy(getRoot()); 554 555 SmallVector<SDNode*, 128> DeadNodes; 556 557 // Add all obviously-dead nodes to the DeadNodes worklist. 558 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 559 if (I->use_empty()) 560 DeadNodes.push_back(I); 561 562 RemoveDeadNodes(DeadNodes); 563 564 // If the root changed (e.g. it was a dead load, update the root). 565 setRoot(Dummy.getValue()); 566} 567 568/// RemoveDeadNodes - This method deletes the unreachable nodes in the 569/// given list, and any nodes that become unreachable as a result. 570void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 571 DAGUpdateListener *UpdateListener) { 572 573 // Process the worklist, deleting the nodes and adding their uses to the 574 // worklist. 575 while (!DeadNodes.empty()) { 576 SDNode *N = DeadNodes.back(); 577 DeadNodes.pop_back(); 578 579 if (UpdateListener) 580 UpdateListener->NodeDeleted(N, 0); 581 582 // Take the node out of the appropriate CSE map. 583 RemoveNodeFromCSEMaps(N); 584 585 // Next, brutally remove the operand list. This is safe to do, as there are 586 // no cycles in the graph. 587 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) { 588 SDNode *Operand = I->getVal(); 589 Operand->removeUser(std::distance(N->op_begin(), I), N); 590 591 // Now that we removed this operand, see if there are no uses of it left. 592 if (Operand->use_empty()) 593 DeadNodes.push_back(Operand); 594 } 595 596 if (N->OperandsNeedDelete) 597 delete[] N->OperandList; 598 599 N->OperandList = 0; 600 N->NumOperands = 0; 601 602 // Finally, remove N itself. 603 NodeAllocator.Deallocate(AllNodes.remove(N)); 604 } 605} 606 607void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 608 SmallVector<SDNode*, 16> DeadNodes(1, N); 609 RemoveDeadNodes(DeadNodes, UpdateListener); 610} 611 612void SelectionDAG::DeleteNode(SDNode *N) { 613 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 614 615 // First take this out of the appropriate CSE map. 616 RemoveNodeFromCSEMaps(N); 617 618 // Finally, remove uses due to operands of this node, remove from the 619 // AllNodes list, and delete the node. 620 DeleteNodeNotInCSEMaps(N); 621} 622 623void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 624 // Drop all of the operands and decrement used node's use counts. 625 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 626 I->getVal()->removeUser(std::distance(N->op_begin(), I), N); 627 628 if (N->OperandsNeedDelete) { 629 delete[] N->OperandList; 630 N->OperandList = 0; 631 } 632 633 assert(N != AllNodes.begin()); 634 NodeAllocator.Deallocate(AllNodes.remove(N)); 635} 636 637/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 638/// correspond to it. This is useful when we're about to delete or repurpose 639/// the node. We don't want future request for structurally identical nodes 640/// to return N anymore. 641bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 642 bool Erased = false; 643 switch (N->getOpcode()) { 644 case ISD::EntryToken: 645 assert(0 && "EntryToken should not be in CSEMaps!"); 646 return false; 647 case ISD::HANDLENODE: return false; // noop. 648 case ISD::CONDCODE: 649 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 650 "Cond code doesn't exist!"); 651 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 652 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 653 break; 654 case ISD::ExternalSymbol: 655 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 656 break; 657 case ISD::TargetExternalSymbol: 658 Erased = 659 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 660 break; 661 case ISD::VALUETYPE: { 662 MVT VT = cast<VTSDNode>(N)->getVT(); 663 if (VT.isExtended()) { 664 Erased = ExtendedValueTypeNodes.erase(VT); 665 } else { 666 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 667 ValueTypeNodes[VT.getSimpleVT()] = 0; 668 } 669 break; 670 } 671 default: 672 // Remove it from the CSE Map. 673 Erased = CSEMap.RemoveNode(N); 674 break; 675 } 676#ifndef NDEBUG 677 // Verify that the node was actually in one of the CSE maps, unless it has a 678 // flag result (which cannot be CSE'd) or is one of the special cases that are 679 // not subject to CSE. 680 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 681 !N->isMachineOpcode() && !doNotCSE(N)) { 682 N->dump(this); 683 cerr << "\n"; 684 assert(0 && "Node is not in map!"); 685 } 686#endif 687 return Erased; 688} 689 690/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 691/// has been taken out and modified in some way. If the specified node already 692/// exists in the CSE maps, do not modify the maps, but return the existing node 693/// instead. If it doesn't exist, add it and return null. 694/// 695SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 696 assert(N->getNumOperands() && "This is a leaf node!"); 697 698 if (doNotCSE(N)) 699 return 0; 700 701 SDNode *New = CSEMap.GetOrInsertNode(N); 702 if (New != N) return New; // Node already existed. 703 return 0; 704} 705 706/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 707/// were replaced with those specified. If this node is never memoized, 708/// return null, otherwise return a pointer to the slot it would take. If a 709/// node already exists with these operands, the slot will be non-null. 710SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 711 void *&InsertPos) { 712 if (doNotCSE(N)) 713 return 0; 714 715 SDValue Ops[] = { Op }; 716 FoldingSetNodeID ID; 717 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 718 AddNodeIDCustom(ID, N); 719 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 720} 721 722/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 723/// were replaced with those specified. If this node is never memoized, 724/// return null, otherwise return a pointer to the slot it would take. If a 725/// node already exists with these operands, the slot will be non-null. 726SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 727 SDValue Op1, SDValue Op2, 728 void *&InsertPos) { 729 if (doNotCSE(N)) 730 return 0; 731 732 SDValue Ops[] = { Op1, Op2 }; 733 FoldingSetNodeID ID; 734 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 735 AddNodeIDCustom(ID, N); 736 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 737} 738 739 740/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 741/// were replaced with those specified. If this node is never memoized, 742/// return null, otherwise return a pointer to the slot it would take. If a 743/// node already exists with these operands, the slot will be non-null. 744SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 745 const SDValue *Ops,unsigned NumOps, 746 void *&InsertPos) { 747 if (doNotCSE(N)) 748 return 0; 749 750 FoldingSetNodeID ID; 751 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 752 AddNodeIDCustom(ID, N); 753 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 754} 755 756/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 757void SelectionDAG::VerifyNode(SDNode *N) { 758 switch (N->getOpcode()) { 759 default: 760 break; 761 case ISD::BUILD_PAIR: { 762 MVT VT = N->getValueType(0); 763 assert(N->getNumValues() == 1 && "Too many results!"); 764 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 765 "Wrong return type!"); 766 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 767 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 768 "Mismatched operand types!"); 769 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 770 "Wrong operand type!"); 771 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 772 "Wrong return type size"); 773 break; 774 } 775 case ISD::BUILD_VECTOR: { 776 assert(N->getNumValues() == 1 && "Too many results!"); 777 assert(N->getValueType(0).isVector() && "Wrong return type!"); 778 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 779 "Wrong number of operands!"); 780 // FIXME: Change vector_shuffle to a variadic node with mask elements being 781 // operands of the node. Currently the mask is a BUILD_VECTOR passed as an 782 // operand, and it is not always possible to legalize it. Turning off the 783 // following checks at least makes it possible to legalize most of the time. 784// MVT EltVT = N->getValueType(0).getVectorElementType(); 785// for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 786// assert(I->getSDValue().getValueType() == EltVT && 787// "Wrong operand type!"); 788 break; 789 } 790 } 791} 792 793/// getMVTAlignment - Compute the default alignment value for the 794/// given type. 795/// 796unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 797 const Type *Ty = VT == MVT::iPTR ? 798 PointerType::get(Type::Int8Ty, 0) : 799 VT.getTypeForMVT(); 800 801 return TLI.getTargetData()->getABITypeAlignment(Ty); 802} 803 804SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 805 : TLI(tli), FLI(fli), 806 EntryNode(ISD::EntryToken, getVTList(MVT::Other)), 807 Root(getEntryNode()) { 808 AllNodes.push_back(&EntryNode); 809} 810 811void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi) { 812 MF = &mf; 813 MMI = mmi; 814} 815 816SelectionDAG::~SelectionDAG() { 817 allnodes_clear(); 818} 819 820void SelectionDAG::allnodes_clear() { 821 assert(&*AllNodes.begin() == &EntryNode); 822 AllNodes.remove(AllNodes.begin()); 823 while (!AllNodes.empty()) { 824 SDNode *N = AllNodes.remove(AllNodes.begin()); 825 N->SetNextInBucket(0); 826 827 if (N->OperandsNeedDelete) { 828 delete [] N->OperandList; 829 N->OperandList = 0; 830 } 831 832 NodeAllocator.Deallocate(N); 833 } 834} 835 836void SelectionDAG::clear() { 837 allnodes_clear(); 838 OperandAllocator.Reset(); 839 CSEMap.clear(); 840 841 ExtendedValueTypeNodes.clear(); 842 ExternalSymbols.clear(); 843 TargetExternalSymbols.clear(); 844 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 845 static_cast<CondCodeSDNode*>(0)); 846 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 847 static_cast<SDNode*>(0)); 848 849 EntryNode.Uses = 0; 850 AllNodes.push_back(&EntryNode); 851 Root = getEntryNode(); 852} 853 854SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) { 855 if (Op.getValueType() == VT) return Op; 856 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 857 VT.getSizeInBits()); 858 return getNode(ISD::AND, Op.getValueType(), Op, 859 getConstant(Imm, Op.getValueType())); 860} 861 862SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 863 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 864 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 865} 866 867SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 868 return getConstant(*ConstantInt::get(Val), VT, isT); 869} 870 871SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 872 assert(VT.isInteger() && "Cannot create FP integer constant!"); 873 874 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 875 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 876 "APInt size does not match type size!"); 877 878 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 879 FoldingSetNodeID ID; 880 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 881 ID.AddPointer(&Val); 882 void *IP = 0; 883 SDNode *N = NULL; 884 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 885 if (!VT.isVector()) 886 return SDValue(N, 0); 887 if (!N) { 888 N = NodeAllocator.Allocate<ConstantSDNode>(); 889 new (N) ConstantSDNode(isT, &Val, EltVT); 890 CSEMap.InsertNode(N, IP); 891 AllNodes.push_back(N); 892 } 893 894 SDValue Result(N, 0); 895 if (VT.isVector()) { 896 SmallVector<SDValue, 8> Ops; 897 Ops.assign(VT.getVectorNumElements(), Result); 898 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 899 } 900 return Result; 901} 902 903SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 904 return getConstant(Val, TLI.getPointerTy(), isTarget); 905} 906 907 908SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 909 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 910} 911 912SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 913 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 914 915 MVT EltVT = 916 VT.isVector() ? VT.getVectorElementType() : VT; 917 918 // Do the map lookup using the actual bit pattern for the floating point 919 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 920 // we don't have issues with SNANs. 921 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 922 FoldingSetNodeID ID; 923 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 924 ID.AddPointer(&V); 925 void *IP = 0; 926 SDNode *N = NULL; 927 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 928 if (!VT.isVector()) 929 return SDValue(N, 0); 930 if (!N) { 931 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 932 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 933 CSEMap.InsertNode(N, IP); 934 AllNodes.push_back(N); 935 } 936 937 SDValue Result(N, 0); 938 if (VT.isVector()) { 939 SmallVector<SDValue, 8> Ops; 940 Ops.assign(VT.getVectorNumElements(), Result); 941 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 942 } 943 return Result; 944} 945 946SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 947 MVT EltVT = 948 VT.isVector() ? VT.getVectorElementType() : VT; 949 if (EltVT==MVT::f32) 950 return getConstantFP(APFloat((float)Val), VT, isTarget); 951 else 952 return getConstantFP(APFloat(Val), VT, isTarget); 953} 954 955SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 956 MVT VT, int64_t Offset, 957 bool isTargetGA) { 958 unsigned Opc; 959 960 // Truncate (with sign-extension) the offset value to the pointer size. 961 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 962 if (BitWidth < 64) 963 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 964 965 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 966 if (!GVar) { 967 // If GV is an alias then use the aliasee for determining thread-localness. 968 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 969 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 970 } 971 972 if (GVar && GVar->isThreadLocal()) 973 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 974 else 975 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 976 977 FoldingSetNodeID ID; 978 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 979 ID.AddPointer(GV); 980 ID.AddInteger(Offset); 981 void *IP = 0; 982 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 983 return SDValue(E, 0); 984 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 985 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 986 CSEMap.InsertNode(N, IP); 987 AllNodes.push_back(N); 988 return SDValue(N, 0); 989} 990 991SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 992 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 993 FoldingSetNodeID ID; 994 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 995 ID.AddInteger(FI); 996 void *IP = 0; 997 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 998 return SDValue(E, 0); 999 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 1000 new (N) FrameIndexSDNode(FI, VT, isTarget); 1001 CSEMap.InsertNode(N, IP); 1002 AllNodes.push_back(N); 1003 return SDValue(N, 0); 1004} 1005 1006SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 1007 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1008 FoldingSetNodeID ID; 1009 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1010 ID.AddInteger(JTI); 1011 void *IP = 0; 1012 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1013 return SDValue(E, 0); 1014 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1015 new (N) JumpTableSDNode(JTI, VT, isTarget); 1016 CSEMap.InsertNode(N, IP); 1017 AllNodes.push_back(N); 1018 return SDValue(N, 0); 1019} 1020 1021SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1022 unsigned Alignment, int Offset, 1023 bool isTarget) { 1024 if (Alignment == 0) 1025 Alignment = 1026 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1027 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1028 FoldingSetNodeID ID; 1029 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1030 ID.AddInteger(Alignment); 1031 ID.AddInteger(Offset); 1032 ID.AddPointer(C); 1033 void *IP = 0; 1034 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1035 return SDValue(E, 0); 1036 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1037 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1038 CSEMap.InsertNode(N, IP); 1039 AllNodes.push_back(N); 1040 return SDValue(N, 0); 1041} 1042 1043 1044SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1045 unsigned Alignment, int Offset, 1046 bool isTarget) { 1047 if (Alignment == 0) 1048 Alignment = 1049 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1050 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1051 FoldingSetNodeID ID; 1052 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1053 ID.AddInteger(Alignment); 1054 ID.AddInteger(Offset); 1055 C->AddSelectionDAGCSEId(ID); 1056 void *IP = 0; 1057 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1058 return SDValue(E, 0); 1059 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1060 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1061 CSEMap.InsertNode(N, IP); 1062 AllNodes.push_back(N); 1063 return SDValue(N, 0); 1064} 1065 1066 1067SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1068 FoldingSetNodeID ID; 1069 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1070 ID.AddPointer(MBB); 1071 void *IP = 0; 1072 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1073 return SDValue(E, 0); 1074 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1075 new (N) BasicBlockSDNode(MBB); 1076 CSEMap.InsertNode(N, IP); 1077 AllNodes.push_back(N); 1078 return SDValue(N, 0); 1079} 1080 1081SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1082 FoldingSetNodeID ID; 1083 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1084 ID.AddInteger(Flags.getRawBits()); 1085 void *IP = 0; 1086 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1087 return SDValue(E, 0); 1088 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1089 new (N) ARG_FLAGSSDNode(Flags); 1090 CSEMap.InsertNode(N, IP); 1091 AllNodes.push_back(N); 1092 return SDValue(N, 0); 1093} 1094 1095SDValue SelectionDAG::getValueType(MVT VT) { 1096 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1097 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1098 1099 SDNode *&N = VT.isExtended() ? 1100 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1101 1102 if (N) return SDValue(N, 0); 1103 N = NodeAllocator.Allocate<VTSDNode>(); 1104 new (N) VTSDNode(VT); 1105 AllNodes.push_back(N); 1106 return SDValue(N, 0); 1107} 1108 1109SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1110 SDNode *&N = ExternalSymbols[Sym]; 1111 if (N) return SDValue(N, 0); 1112 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1113 new (N) ExternalSymbolSDNode(false, Sym, VT); 1114 AllNodes.push_back(N); 1115 return SDValue(N, 0); 1116} 1117 1118SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1119 SDNode *&N = TargetExternalSymbols[Sym]; 1120 if (N) return SDValue(N, 0); 1121 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1122 new (N) ExternalSymbolSDNode(true, Sym, VT); 1123 AllNodes.push_back(N); 1124 return SDValue(N, 0); 1125} 1126 1127SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1128 if ((unsigned)Cond >= CondCodeNodes.size()) 1129 CondCodeNodes.resize(Cond+1); 1130 1131 if (CondCodeNodes[Cond] == 0) { 1132 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1133 new (N) CondCodeSDNode(Cond); 1134 CondCodeNodes[Cond] = N; 1135 AllNodes.push_back(N); 1136 } 1137 return SDValue(CondCodeNodes[Cond], 0); 1138} 1139 1140SDValue SelectionDAG::getConvertRndSat(MVT VT, SDValue Val, SDValue DTy, 1141 SDValue STy, SDValue Rnd, SDValue Sat, 1142 ISD::CvtCode Code) { 1143 FoldingSetNodeID ID; 1144 void* IP = 0; 1145 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1146 return SDValue(E, 0); 1147 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1148 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1149 new (N) CvtRndSatSDNode(VT, Ops, 5, Code); 1150 CSEMap.InsertNode(N, IP); 1151 AllNodes.push_back(N); 1152 return SDValue(N, 0); 1153} 1154 1155SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1156 FoldingSetNodeID ID; 1157 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1158 ID.AddInteger(RegNo); 1159 void *IP = 0; 1160 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1161 return SDValue(E, 0); 1162 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1163 new (N) RegisterSDNode(RegNo, VT); 1164 CSEMap.InsertNode(N, IP); 1165 AllNodes.push_back(N); 1166 return SDValue(N, 0); 1167} 1168 1169SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1170 unsigned Line, unsigned Col, 1171 const CompileUnitDesc *CU) { 1172 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1173 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1174 AllNodes.push_back(N); 1175 return SDValue(N, 0); 1176} 1177 1178SDValue SelectionDAG::getLabel(unsigned Opcode, 1179 SDValue Root, 1180 unsigned LabelID) { 1181 FoldingSetNodeID ID; 1182 SDValue Ops[] = { Root }; 1183 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1184 ID.AddInteger(LabelID); 1185 void *IP = 0; 1186 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1187 return SDValue(E, 0); 1188 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1189 new (N) LabelSDNode(Opcode, Root, LabelID); 1190 CSEMap.InsertNode(N, IP); 1191 AllNodes.push_back(N); 1192 return SDValue(N, 0); 1193} 1194 1195SDValue SelectionDAG::getSrcValue(const Value *V) { 1196 assert((!V || isa<PointerType>(V->getType())) && 1197 "SrcValue is not a pointer?"); 1198 1199 FoldingSetNodeID ID; 1200 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1201 ID.AddPointer(V); 1202 1203 void *IP = 0; 1204 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1205 return SDValue(E, 0); 1206 1207 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1208 new (N) SrcValueSDNode(V); 1209 CSEMap.InsertNode(N, IP); 1210 AllNodes.push_back(N); 1211 return SDValue(N, 0); 1212} 1213 1214SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1215#ifndef NDEBUG 1216 const Value *v = MO.getValue(); 1217 assert((!v || isa<PointerType>(v->getType())) && 1218 "SrcValue is not a pointer?"); 1219#endif 1220 1221 FoldingSetNodeID ID; 1222 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1223 MO.Profile(ID); 1224 1225 void *IP = 0; 1226 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1227 return SDValue(E, 0); 1228 1229 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1230 new (N) MemOperandSDNode(MO); 1231 CSEMap.InsertNode(N, IP); 1232 AllNodes.push_back(N); 1233 return SDValue(N, 0); 1234} 1235 1236/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1237/// specified value type. 1238SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1239 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1240 unsigned ByteSize = VT.getStoreSizeInBits()/8; 1241 const Type *Ty = VT.getTypeForMVT(); 1242 unsigned StackAlign = 1243 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1244 1245 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1246 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1247} 1248 1249SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1250 SDValue N2, ISD::CondCode Cond) { 1251 // These setcc operations always fold. 1252 switch (Cond) { 1253 default: break; 1254 case ISD::SETFALSE: 1255 case ISD::SETFALSE2: return getConstant(0, VT); 1256 case ISD::SETTRUE: 1257 case ISD::SETTRUE2: return getConstant(1, VT); 1258 1259 case ISD::SETOEQ: 1260 case ISD::SETOGT: 1261 case ISD::SETOGE: 1262 case ISD::SETOLT: 1263 case ISD::SETOLE: 1264 case ISD::SETONE: 1265 case ISD::SETO: 1266 case ISD::SETUO: 1267 case ISD::SETUEQ: 1268 case ISD::SETUNE: 1269 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1270 break; 1271 } 1272 1273 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1274 const APInt &C2 = N2C->getAPIntValue(); 1275 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1276 const APInt &C1 = N1C->getAPIntValue(); 1277 1278 switch (Cond) { 1279 default: assert(0 && "Unknown integer setcc!"); 1280 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1281 case ISD::SETNE: return getConstant(C1 != C2, VT); 1282 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1283 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1284 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1285 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1286 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1287 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1288 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1289 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1290 } 1291 } 1292 } 1293 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1294 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1295 // No compile time operations on this type yet. 1296 if (N1C->getValueType(0) == MVT::ppcf128) 1297 return SDValue(); 1298 1299 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1300 switch (Cond) { 1301 default: break; 1302 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1303 return getNode(ISD::UNDEF, VT); 1304 // fall through 1305 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1306 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1307 return getNode(ISD::UNDEF, VT); 1308 // fall through 1309 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1310 R==APFloat::cmpLessThan, VT); 1311 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1312 return getNode(ISD::UNDEF, VT); 1313 // fall through 1314 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1315 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1316 return getNode(ISD::UNDEF, VT); 1317 // fall through 1318 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1319 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1320 return getNode(ISD::UNDEF, VT); 1321 // fall through 1322 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1323 R==APFloat::cmpEqual, VT); 1324 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1325 return getNode(ISD::UNDEF, VT); 1326 // fall through 1327 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1328 R==APFloat::cmpEqual, VT); 1329 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1330 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1331 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1332 R==APFloat::cmpEqual, VT); 1333 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1334 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1335 R==APFloat::cmpLessThan, VT); 1336 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1337 R==APFloat::cmpUnordered, VT); 1338 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1339 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1340 } 1341 } else { 1342 // Ensure that the constant occurs on the RHS. 1343 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1344 } 1345 } 1346 1347 // Could not fold it. 1348 return SDValue(); 1349} 1350 1351/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1352/// use this predicate to simplify operations downstream. 1353bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1354 unsigned BitWidth = Op.getValueSizeInBits(); 1355 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1356} 1357 1358/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1359/// this predicate to simplify operations downstream. Mask is known to be zero 1360/// for bits that V cannot have. 1361bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1362 unsigned Depth) const { 1363 APInt KnownZero, KnownOne; 1364 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1365 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1366 return (KnownZero & Mask) == Mask; 1367} 1368 1369/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1370/// known to be either zero or one and return them in the KnownZero/KnownOne 1371/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1372/// processing. 1373void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1374 APInt &KnownZero, APInt &KnownOne, 1375 unsigned Depth) const { 1376 unsigned BitWidth = Mask.getBitWidth(); 1377 assert(BitWidth == Op.getValueType().getSizeInBits() && 1378 "Mask size mismatches value type size!"); 1379 1380 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1381 if (Depth == 6 || Mask == 0) 1382 return; // Limit search depth. 1383 1384 APInt KnownZero2, KnownOne2; 1385 1386 switch (Op.getOpcode()) { 1387 case ISD::Constant: 1388 // We know all of the bits for a constant! 1389 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1390 KnownZero = ~KnownOne & Mask; 1391 return; 1392 case ISD::AND: 1393 // If either the LHS or the RHS are Zero, the result is zero. 1394 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1395 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1396 KnownZero2, KnownOne2, Depth+1); 1397 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1398 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1399 1400 // Output known-1 bits are only known if set in both the LHS & RHS. 1401 KnownOne &= KnownOne2; 1402 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1403 KnownZero |= KnownZero2; 1404 return; 1405 case ISD::OR: 1406 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1407 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1408 KnownZero2, KnownOne2, Depth+1); 1409 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1410 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1411 1412 // Output known-0 bits are only known if clear in both the LHS & RHS. 1413 KnownZero &= KnownZero2; 1414 // Output known-1 are known to be set if set in either the LHS | RHS. 1415 KnownOne |= KnownOne2; 1416 return; 1417 case ISD::XOR: { 1418 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1419 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1420 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1421 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1422 1423 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1424 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1425 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1426 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1427 KnownZero = KnownZeroOut; 1428 return; 1429 } 1430 case ISD::MUL: { 1431 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1432 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1433 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1434 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1435 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1436 1437 // If low bits are zero in either operand, output low known-0 bits. 1438 // Also compute a conserative estimate for high known-0 bits. 1439 // More trickiness is possible, but this is sufficient for the 1440 // interesting case of alignment computation. 1441 KnownOne.clear(); 1442 unsigned TrailZ = KnownZero.countTrailingOnes() + 1443 KnownZero2.countTrailingOnes(); 1444 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1445 KnownZero2.countLeadingOnes(), 1446 BitWidth) - BitWidth; 1447 1448 TrailZ = std::min(TrailZ, BitWidth); 1449 LeadZ = std::min(LeadZ, BitWidth); 1450 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1451 APInt::getHighBitsSet(BitWidth, LeadZ); 1452 KnownZero &= Mask; 1453 return; 1454 } 1455 case ISD::UDIV: { 1456 // For the purposes of computing leading zeros we can conservatively 1457 // treat a udiv as a logical right shift by the power of 2 known to 1458 // be less than the denominator. 1459 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1460 ComputeMaskedBits(Op.getOperand(0), 1461 AllOnes, KnownZero2, KnownOne2, Depth+1); 1462 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1463 1464 KnownOne2.clear(); 1465 KnownZero2.clear(); 1466 ComputeMaskedBits(Op.getOperand(1), 1467 AllOnes, KnownZero2, KnownOne2, Depth+1); 1468 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1469 if (RHSUnknownLeadingOnes != BitWidth) 1470 LeadZ = std::min(BitWidth, 1471 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1472 1473 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1474 return; 1475 } 1476 case ISD::SELECT: 1477 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1478 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1479 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1480 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1481 1482 // Only known if known in both the LHS and RHS. 1483 KnownOne &= KnownOne2; 1484 KnownZero &= KnownZero2; 1485 return; 1486 case ISD::SELECT_CC: 1487 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1488 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1489 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1490 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1491 1492 // Only known if known in both the LHS and RHS. 1493 KnownOne &= KnownOne2; 1494 KnownZero &= KnownZero2; 1495 return; 1496 case ISD::SADDO: 1497 case ISD::UADDO: 1498 if (Op.getResNo() != 1) 1499 return; 1500 // The boolean result conforms to getBooleanContents. Fall through. 1501 case ISD::SETCC: 1502 // If we know the result of a setcc has the top bits zero, use this info. 1503 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1504 BitWidth > 1) 1505 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1506 return; 1507 case ISD::SHL: 1508 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1509 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1510 unsigned ShAmt = SA->getZExtValue(); 1511 1512 // If the shift count is an invalid immediate, don't do anything. 1513 if (ShAmt >= BitWidth) 1514 return; 1515 1516 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1517 KnownZero, KnownOne, Depth+1); 1518 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1519 KnownZero <<= ShAmt; 1520 KnownOne <<= ShAmt; 1521 // low bits known zero. 1522 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1523 } 1524 return; 1525 case ISD::SRL: 1526 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1527 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1528 unsigned ShAmt = SA->getZExtValue(); 1529 1530 // If the shift count is an invalid immediate, don't do anything. 1531 if (ShAmt >= BitWidth) 1532 return; 1533 1534 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1535 KnownZero, KnownOne, Depth+1); 1536 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1537 KnownZero = KnownZero.lshr(ShAmt); 1538 KnownOne = KnownOne.lshr(ShAmt); 1539 1540 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1541 KnownZero |= HighBits; // High bits known zero. 1542 } 1543 return; 1544 case ISD::SRA: 1545 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1546 unsigned ShAmt = SA->getZExtValue(); 1547 1548 // If the shift count is an invalid immediate, don't do anything. 1549 if (ShAmt >= BitWidth) 1550 return; 1551 1552 APInt InDemandedMask = (Mask << ShAmt); 1553 // If any of the demanded bits are produced by the sign extension, we also 1554 // demand the input sign bit. 1555 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1556 if (HighBits.getBoolValue()) 1557 InDemandedMask |= APInt::getSignBit(BitWidth); 1558 1559 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1560 Depth+1); 1561 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1562 KnownZero = KnownZero.lshr(ShAmt); 1563 KnownOne = KnownOne.lshr(ShAmt); 1564 1565 // Handle the sign bits. 1566 APInt SignBit = APInt::getSignBit(BitWidth); 1567 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1568 1569 if (KnownZero.intersects(SignBit)) { 1570 KnownZero |= HighBits; // New bits are known zero. 1571 } else if (KnownOne.intersects(SignBit)) { 1572 KnownOne |= HighBits; // New bits are known one. 1573 } 1574 } 1575 return; 1576 case ISD::SIGN_EXTEND_INREG: { 1577 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1578 unsigned EBits = EVT.getSizeInBits(); 1579 1580 // Sign extension. Compute the demanded bits in the result that are not 1581 // present in the input. 1582 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1583 1584 APInt InSignBit = APInt::getSignBit(EBits); 1585 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1586 1587 // If the sign extended bits are demanded, we know that the sign 1588 // bit is demanded. 1589 InSignBit.zext(BitWidth); 1590 if (NewBits.getBoolValue()) 1591 InputDemandedBits |= InSignBit; 1592 1593 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1594 KnownZero, KnownOne, Depth+1); 1595 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1596 1597 // If the sign bit of the input is known set or clear, then we know the 1598 // top bits of the result. 1599 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1600 KnownZero |= NewBits; 1601 KnownOne &= ~NewBits; 1602 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1603 KnownOne |= NewBits; 1604 KnownZero &= ~NewBits; 1605 } else { // Input sign bit unknown 1606 KnownZero &= ~NewBits; 1607 KnownOne &= ~NewBits; 1608 } 1609 return; 1610 } 1611 case ISD::CTTZ: 1612 case ISD::CTLZ: 1613 case ISD::CTPOP: { 1614 unsigned LowBits = Log2_32(BitWidth)+1; 1615 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1616 KnownOne.clear(); 1617 return; 1618 } 1619 case ISD::LOAD: { 1620 if (ISD::isZEXTLoad(Op.getNode())) { 1621 LoadSDNode *LD = cast<LoadSDNode>(Op); 1622 MVT VT = LD->getMemoryVT(); 1623 unsigned MemBits = VT.getSizeInBits(); 1624 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1625 } 1626 return; 1627 } 1628 case ISD::ZERO_EXTEND: { 1629 MVT InVT = Op.getOperand(0).getValueType(); 1630 unsigned InBits = InVT.getSizeInBits(); 1631 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1632 APInt InMask = Mask; 1633 InMask.trunc(InBits); 1634 KnownZero.trunc(InBits); 1635 KnownOne.trunc(InBits); 1636 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1637 KnownZero.zext(BitWidth); 1638 KnownOne.zext(BitWidth); 1639 KnownZero |= NewBits; 1640 return; 1641 } 1642 case ISD::SIGN_EXTEND: { 1643 MVT InVT = Op.getOperand(0).getValueType(); 1644 unsigned InBits = InVT.getSizeInBits(); 1645 APInt InSignBit = APInt::getSignBit(InBits); 1646 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1647 APInt InMask = Mask; 1648 InMask.trunc(InBits); 1649 1650 // If any of the sign extended bits are demanded, we know that the sign 1651 // bit is demanded. Temporarily set this bit in the mask for our callee. 1652 if (NewBits.getBoolValue()) 1653 InMask |= InSignBit; 1654 1655 KnownZero.trunc(InBits); 1656 KnownOne.trunc(InBits); 1657 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1658 1659 // Note if the sign bit is known to be zero or one. 1660 bool SignBitKnownZero = KnownZero.isNegative(); 1661 bool SignBitKnownOne = KnownOne.isNegative(); 1662 assert(!(SignBitKnownZero && SignBitKnownOne) && 1663 "Sign bit can't be known to be both zero and one!"); 1664 1665 // If the sign bit wasn't actually demanded by our caller, we don't 1666 // want it set in the KnownZero and KnownOne result values. Reset the 1667 // mask and reapply it to the result values. 1668 InMask = Mask; 1669 InMask.trunc(InBits); 1670 KnownZero &= InMask; 1671 KnownOne &= InMask; 1672 1673 KnownZero.zext(BitWidth); 1674 KnownOne.zext(BitWidth); 1675 1676 // If the sign bit is known zero or one, the top bits match. 1677 if (SignBitKnownZero) 1678 KnownZero |= NewBits; 1679 else if (SignBitKnownOne) 1680 KnownOne |= NewBits; 1681 return; 1682 } 1683 case ISD::ANY_EXTEND: { 1684 MVT InVT = Op.getOperand(0).getValueType(); 1685 unsigned InBits = InVT.getSizeInBits(); 1686 APInt InMask = Mask; 1687 InMask.trunc(InBits); 1688 KnownZero.trunc(InBits); 1689 KnownOne.trunc(InBits); 1690 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1691 KnownZero.zext(BitWidth); 1692 KnownOne.zext(BitWidth); 1693 return; 1694 } 1695 case ISD::TRUNCATE: { 1696 MVT InVT = Op.getOperand(0).getValueType(); 1697 unsigned InBits = InVT.getSizeInBits(); 1698 APInt InMask = Mask; 1699 InMask.zext(InBits); 1700 KnownZero.zext(InBits); 1701 KnownOne.zext(InBits); 1702 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1703 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1704 KnownZero.trunc(BitWidth); 1705 KnownOne.trunc(BitWidth); 1706 break; 1707 } 1708 case ISD::AssertZext: { 1709 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1710 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1711 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1712 KnownOne, Depth+1); 1713 KnownZero |= (~InMask) & Mask; 1714 return; 1715 } 1716 case ISD::FGETSIGN: 1717 // All bits are zero except the low bit. 1718 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1719 return; 1720 1721 case ISD::SUB: { 1722 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1723 // We know that the top bits of C-X are clear if X contains less bits 1724 // than C (i.e. no wrap-around can happen). For example, 20-X is 1725 // positive if we can prove that X is >= 0 and < 16. 1726 if (CLHS->getAPIntValue().isNonNegative()) { 1727 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1728 // NLZ can't be BitWidth with no sign bit 1729 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1730 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1731 Depth+1); 1732 1733 // If all of the MaskV bits are known to be zero, then we know the 1734 // output top bits are zero, because we now know that the output is 1735 // from [0-C]. 1736 if ((KnownZero2 & MaskV) == MaskV) { 1737 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1738 // Top bits known zero. 1739 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1740 } 1741 } 1742 } 1743 } 1744 // fall through 1745 case ISD::ADD: { 1746 // Output known-0 bits are known if clear or set in both the low clear bits 1747 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1748 // low 3 bits clear. 1749 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1750 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1751 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1752 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1753 1754 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1755 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1756 KnownZeroOut = std::min(KnownZeroOut, 1757 KnownZero2.countTrailingOnes()); 1758 1759 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1760 return; 1761 } 1762 case ISD::SREM: 1763 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1764 const APInt &RA = Rem->getAPIntValue(); 1765 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1766 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1767 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1768 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1769 1770 // If the sign bit of the first operand is zero, the sign bit of 1771 // the result is zero. If the first operand has no one bits below 1772 // the second operand's single 1 bit, its sign will be zero. 1773 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1774 KnownZero2 |= ~LowBits; 1775 1776 KnownZero |= KnownZero2 & Mask; 1777 1778 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1779 } 1780 } 1781 return; 1782 case ISD::UREM: { 1783 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1784 const APInt &RA = Rem->getAPIntValue(); 1785 if (RA.isPowerOf2()) { 1786 APInt LowBits = (RA - 1); 1787 APInt Mask2 = LowBits & Mask; 1788 KnownZero |= ~LowBits & Mask; 1789 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1790 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1791 break; 1792 } 1793 } 1794 1795 // Since the result is less than or equal to either operand, any leading 1796 // zero bits in either operand must also exist in the result. 1797 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1798 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1799 Depth+1); 1800 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1801 Depth+1); 1802 1803 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1804 KnownZero2.countLeadingOnes()); 1805 KnownOne.clear(); 1806 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1807 return; 1808 } 1809 default: 1810 // Allow the target to implement this method for its nodes. 1811 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1812 case ISD::INTRINSIC_WO_CHAIN: 1813 case ISD::INTRINSIC_W_CHAIN: 1814 case ISD::INTRINSIC_VOID: 1815 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1816 } 1817 return; 1818 } 1819} 1820 1821/// ComputeNumSignBits - Return the number of times the sign bit of the 1822/// register is replicated into the other bits. We know that at least 1 bit 1823/// is always equal to the sign bit (itself), but other cases can give us 1824/// information. For example, immediately after an "SRA X, 2", we know that 1825/// the top 3 bits are all equal to each other, so we return 3. 1826unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1827 MVT VT = Op.getValueType(); 1828 assert(VT.isInteger() && "Invalid VT!"); 1829 unsigned VTBits = VT.getSizeInBits(); 1830 unsigned Tmp, Tmp2; 1831 unsigned FirstAnswer = 1; 1832 1833 if (Depth == 6) 1834 return 1; // Limit search depth. 1835 1836 switch (Op.getOpcode()) { 1837 default: break; 1838 case ISD::AssertSext: 1839 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1840 return VTBits-Tmp+1; 1841 case ISD::AssertZext: 1842 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1843 return VTBits-Tmp; 1844 1845 case ISD::Constant: { 1846 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1847 // If negative, return # leading ones. 1848 if (Val.isNegative()) 1849 return Val.countLeadingOnes(); 1850 1851 // Return # leading zeros. 1852 return Val.countLeadingZeros(); 1853 } 1854 1855 case ISD::SIGN_EXTEND: 1856 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1857 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1858 1859 case ISD::SIGN_EXTEND_INREG: 1860 // Max of the input and what this extends. 1861 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1862 Tmp = VTBits-Tmp+1; 1863 1864 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1865 return std::max(Tmp, Tmp2); 1866 1867 case ISD::SRA: 1868 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1869 // SRA X, C -> adds C sign bits. 1870 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1871 Tmp += C->getZExtValue(); 1872 if (Tmp > VTBits) Tmp = VTBits; 1873 } 1874 return Tmp; 1875 case ISD::SHL: 1876 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1877 // shl destroys sign bits. 1878 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1879 if (C->getZExtValue() >= VTBits || // Bad shift. 1880 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 1881 return Tmp - C->getZExtValue(); 1882 } 1883 break; 1884 case ISD::AND: 1885 case ISD::OR: 1886 case ISD::XOR: // NOT is handled here. 1887 // Logical binary ops preserve the number of sign bits at the worst. 1888 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1889 if (Tmp != 1) { 1890 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1891 FirstAnswer = std::min(Tmp, Tmp2); 1892 // We computed what we know about the sign bits as our first 1893 // answer. Now proceed to the generic code that uses 1894 // ComputeMaskedBits, and pick whichever answer is better. 1895 } 1896 break; 1897 1898 case ISD::SELECT: 1899 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1900 if (Tmp == 1) return 1; // Early out. 1901 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1902 return std::min(Tmp, Tmp2); 1903 1904 case ISD::SADDO: 1905 case ISD::UADDO: 1906 if (Op.getResNo() != 1) 1907 break; 1908 // The boolean result conforms to getBooleanContents. Fall through. 1909 case ISD::SETCC: 1910 // If setcc returns 0/-1, all bits are sign bits. 1911 if (TLI.getBooleanContents() == 1912 TargetLowering::ZeroOrNegativeOneBooleanContent) 1913 return VTBits; 1914 break; 1915 case ISD::ROTL: 1916 case ISD::ROTR: 1917 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1918 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 1919 1920 // Handle rotate right by N like a rotate left by 32-N. 1921 if (Op.getOpcode() == ISD::ROTR) 1922 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1923 1924 // If we aren't rotating out all of the known-in sign bits, return the 1925 // number that are left. This handles rotl(sext(x), 1) for example. 1926 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1927 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1928 } 1929 break; 1930 case ISD::ADD: 1931 // Add can have at most one carry bit. Thus we know that the output 1932 // is, at worst, one more bit than the inputs. 1933 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1934 if (Tmp == 1) return 1; // Early out. 1935 1936 // Special case decrementing a value (ADD X, -1): 1937 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1938 if (CRHS->isAllOnesValue()) { 1939 APInt KnownZero, KnownOne; 1940 APInt Mask = APInt::getAllOnesValue(VTBits); 1941 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1942 1943 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1944 // sign bits set. 1945 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1946 return VTBits; 1947 1948 // If we are subtracting one from a positive number, there is no carry 1949 // out of the result. 1950 if (KnownZero.isNegative()) 1951 return Tmp; 1952 } 1953 1954 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1955 if (Tmp2 == 1) return 1; 1956 return std::min(Tmp, Tmp2)-1; 1957 break; 1958 1959 case ISD::SUB: 1960 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1961 if (Tmp2 == 1) return 1; 1962 1963 // Handle NEG. 1964 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1965 if (CLHS->isNullValue()) { 1966 APInt KnownZero, KnownOne; 1967 APInt Mask = APInt::getAllOnesValue(VTBits); 1968 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1969 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1970 // sign bits set. 1971 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1972 return VTBits; 1973 1974 // If the input is known to be positive (the sign bit is known clear), 1975 // the output of the NEG has the same number of sign bits as the input. 1976 if (KnownZero.isNegative()) 1977 return Tmp2; 1978 1979 // Otherwise, we treat this like a SUB. 1980 } 1981 1982 // Sub can have at most one carry bit. Thus we know that the output 1983 // is, at worst, one more bit than the inputs. 1984 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1985 if (Tmp == 1) return 1; // Early out. 1986 return std::min(Tmp, Tmp2)-1; 1987 break; 1988 case ISD::TRUNCATE: 1989 // FIXME: it's tricky to do anything useful for this, but it is an important 1990 // case for targets like X86. 1991 break; 1992 } 1993 1994 // Handle LOADX separately here. EXTLOAD case will fallthrough. 1995 if (Op.getOpcode() == ISD::LOAD) { 1996 LoadSDNode *LD = cast<LoadSDNode>(Op); 1997 unsigned ExtType = LD->getExtensionType(); 1998 switch (ExtType) { 1999 default: break; 2000 case ISD::SEXTLOAD: // '17' bits known 2001 Tmp = LD->getMemoryVT().getSizeInBits(); 2002 return VTBits-Tmp+1; 2003 case ISD::ZEXTLOAD: // '16' bits known 2004 Tmp = LD->getMemoryVT().getSizeInBits(); 2005 return VTBits-Tmp; 2006 } 2007 } 2008 2009 // Allow the target to implement this method for its nodes. 2010 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2011 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2012 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2013 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2014 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2015 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2016 } 2017 2018 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2019 // use this information. 2020 APInt KnownZero, KnownOne; 2021 APInt Mask = APInt::getAllOnesValue(VTBits); 2022 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2023 2024 if (KnownZero.isNegative()) { // sign bit is 0 2025 Mask = KnownZero; 2026 } else if (KnownOne.isNegative()) { // sign bit is 1; 2027 Mask = KnownOne; 2028 } else { 2029 // Nothing known. 2030 return FirstAnswer; 2031 } 2032 2033 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2034 // the number of identical bits in the top of the input value. 2035 Mask = ~Mask; 2036 Mask <<= Mask.getBitWidth()-VTBits; 2037 // Return # leading zeros. We use 'min' here in case Val was zero before 2038 // shifting. We don't want to return '64' as for an i32 "0". 2039 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2040} 2041 2042 2043bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2044 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2045 if (!GA) return false; 2046 if (GA->getOffset() != 0) return false; 2047 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2048 if (!GV) return false; 2049 MachineModuleInfo *MMI = getMachineModuleInfo(); 2050 return MMI && MMI->hasDebugInfo() && MMI->isVerified(GV); 2051} 2052 2053 2054/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2055/// element of the result of the vector shuffle. 2056SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 2057 MVT VT = N->getValueType(0); 2058 SDValue PermMask = N->getOperand(2); 2059 SDValue Idx = PermMask.getOperand(i); 2060 if (Idx.getOpcode() == ISD::UNDEF) 2061 return getNode(ISD::UNDEF, VT.getVectorElementType()); 2062 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 2063 unsigned NumElems = PermMask.getNumOperands(); 2064 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2065 Index %= NumElems; 2066 2067 if (V.getOpcode() == ISD::BIT_CONVERT) { 2068 V = V.getOperand(0); 2069 MVT VVT = V.getValueType(); 2070 if (!VVT.isVector() || VVT.getVectorNumElements() != NumElems) 2071 return SDValue(); 2072 } 2073 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2074 return (Index == 0) ? V.getOperand(0) 2075 : getNode(ISD::UNDEF, VT.getVectorElementType()); 2076 if (V.getOpcode() == ISD::BUILD_VECTOR) 2077 return V.getOperand(Index); 2078 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 2079 return getShuffleScalarElt(V.getNode(), Index); 2080 return SDValue(); 2081} 2082 2083 2084/// getNode - Gets or creates the specified node. 2085/// 2086SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) { 2087 FoldingSetNodeID ID; 2088 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2089 void *IP = 0; 2090 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2091 return SDValue(E, 0); 2092 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2093 new (N) SDNode(Opcode, SDNode::getSDVTList(VT)); 2094 CSEMap.InsertNode(N, IP); 2095 2096 AllNodes.push_back(N); 2097#ifndef NDEBUG 2098 VerifyNode(N); 2099#endif 2100 return SDValue(N, 0); 2101} 2102 2103SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) { 2104 // Constant fold unary operations with an integer constant operand. 2105 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2106 const APInt &Val = C->getAPIntValue(); 2107 unsigned BitWidth = VT.getSizeInBits(); 2108 switch (Opcode) { 2109 default: break; 2110 case ISD::SIGN_EXTEND: 2111 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2112 case ISD::ANY_EXTEND: 2113 case ISD::ZERO_EXTEND: 2114 case ISD::TRUNCATE: 2115 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2116 case ISD::UINT_TO_FP: 2117 case ISD::SINT_TO_FP: { 2118 const uint64_t zero[] = {0, 0}; 2119 // No compile time operations on this type. 2120 if (VT==MVT::ppcf128) 2121 break; 2122 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2123 (void)apf.convertFromAPInt(Val, 2124 Opcode==ISD::SINT_TO_FP, 2125 APFloat::rmNearestTiesToEven); 2126 return getConstantFP(apf, VT); 2127 } 2128 case ISD::BIT_CONVERT: 2129 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2130 return getConstantFP(Val.bitsToFloat(), VT); 2131 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2132 return getConstantFP(Val.bitsToDouble(), VT); 2133 break; 2134 case ISD::BSWAP: 2135 return getConstant(Val.byteSwap(), VT); 2136 case ISD::CTPOP: 2137 return getConstant(Val.countPopulation(), VT); 2138 case ISD::CTLZ: 2139 return getConstant(Val.countLeadingZeros(), VT); 2140 case ISD::CTTZ: 2141 return getConstant(Val.countTrailingZeros(), VT); 2142 } 2143 } 2144 2145 // Constant fold unary operations with a floating point constant operand. 2146 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2147 APFloat V = C->getValueAPF(); // make copy 2148 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2149 switch (Opcode) { 2150 case ISD::FNEG: 2151 V.changeSign(); 2152 return getConstantFP(V, VT); 2153 case ISD::FABS: 2154 V.clearSign(); 2155 return getConstantFP(V, VT); 2156 case ISD::FP_ROUND: 2157 case ISD::FP_EXTEND: { 2158 bool ignored; 2159 // This can return overflow, underflow, or inexact; we don't care. 2160 // FIXME need to be more flexible about rounding mode. 2161 (void)V.convert(*MVTToAPFloatSemantics(VT), 2162 APFloat::rmNearestTiesToEven, &ignored); 2163 return getConstantFP(V, VT); 2164 } 2165 case ISD::FP_TO_SINT: 2166 case ISD::FP_TO_UINT: { 2167 integerPart x; 2168 bool ignored; 2169 assert(integerPartWidth >= 64); 2170 // FIXME need to be more flexible about rounding mode. 2171 APFloat::opStatus s = V.convertToInteger(&x, 64U, 2172 Opcode==ISD::FP_TO_SINT, 2173 APFloat::rmTowardZero, &ignored); 2174 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2175 break; 2176 return getConstant(x, VT); 2177 } 2178 case ISD::BIT_CONVERT: 2179 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2180 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2181 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2182 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2183 break; 2184 } 2185 } 2186 } 2187 2188 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2189 switch (Opcode) { 2190 case ISD::TokenFactor: 2191 case ISD::MERGE_VALUES: 2192 case ISD::CONCAT_VECTORS: 2193 return Operand; // Factor, merge or concat of one node? No need. 2194 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2195 case ISD::FP_EXTEND: 2196 assert(VT.isFloatingPoint() && 2197 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2198 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2199 if (Operand.getOpcode() == ISD::UNDEF) 2200 return getNode(ISD::UNDEF, VT); 2201 break; 2202 case ISD::SIGN_EXTEND: 2203 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2204 "Invalid SIGN_EXTEND!"); 2205 if (Operand.getValueType() == VT) return Operand; // noop extension 2206 assert(Operand.getValueType().bitsLT(VT) 2207 && "Invalid sext node, dst < src!"); 2208 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2209 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2210 break; 2211 case ISD::ZERO_EXTEND: 2212 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2213 "Invalid ZERO_EXTEND!"); 2214 if (Operand.getValueType() == VT) return Operand; // noop extension 2215 assert(Operand.getValueType().bitsLT(VT) 2216 && "Invalid zext node, dst < src!"); 2217 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2218 return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()->getOperand(0)); 2219 break; 2220 case ISD::ANY_EXTEND: 2221 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2222 "Invalid ANY_EXTEND!"); 2223 if (Operand.getValueType() == VT) return Operand; // noop extension 2224 assert(Operand.getValueType().bitsLT(VT) 2225 && "Invalid anyext node, dst < src!"); 2226 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2227 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2228 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2229 break; 2230 case ISD::TRUNCATE: 2231 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2232 "Invalid TRUNCATE!"); 2233 if (Operand.getValueType() == VT) return Operand; // noop truncate 2234 assert(Operand.getValueType().bitsGT(VT) 2235 && "Invalid truncate node, src < dst!"); 2236 if (OpOpcode == ISD::TRUNCATE) 2237 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2238 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2239 OpOpcode == ISD::ANY_EXTEND) { 2240 // If the source is smaller than the dest, we still need an extend. 2241 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2242 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2243 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2244 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2245 else 2246 return Operand.getNode()->getOperand(0); 2247 } 2248 break; 2249 case ISD::BIT_CONVERT: 2250 // Basic sanity checking. 2251 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2252 && "Cannot BIT_CONVERT between types of different sizes!"); 2253 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2254 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2255 return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0)); 2256 if (OpOpcode == ISD::UNDEF) 2257 return getNode(ISD::UNDEF, VT); 2258 break; 2259 case ISD::SCALAR_TO_VECTOR: 2260 assert(VT.isVector() && !Operand.getValueType().isVector() && 2261 VT.getVectorElementType() == Operand.getValueType() && 2262 "Illegal SCALAR_TO_VECTOR node!"); 2263 if (OpOpcode == ISD::UNDEF) 2264 return getNode(ISD::UNDEF, VT); 2265 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2266 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2267 isa<ConstantSDNode>(Operand.getOperand(1)) && 2268 Operand.getConstantOperandVal(1) == 0 && 2269 Operand.getOperand(0).getValueType() == VT) 2270 return Operand.getOperand(0); 2271 break; 2272 case ISD::FNEG: 2273 if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X) 2274 return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1), 2275 Operand.getNode()->getOperand(0)); 2276 if (OpOpcode == ISD::FNEG) // --X -> X 2277 return Operand.getNode()->getOperand(0); 2278 break; 2279 case ISD::FABS: 2280 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2281 return getNode(ISD::FABS, VT, Operand.getNode()->getOperand(0)); 2282 break; 2283 } 2284 2285 SDNode *N; 2286 SDVTList VTs = getVTList(VT); 2287 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2288 FoldingSetNodeID ID; 2289 SDValue Ops[1] = { Operand }; 2290 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2291 void *IP = 0; 2292 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2293 return SDValue(E, 0); 2294 N = NodeAllocator.Allocate<UnarySDNode>(); 2295 new (N) UnarySDNode(Opcode, VTs, Operand); 2296 CSEMap.InsertNode(N, IP); 2297 } else { 2298 N = NodeAllocator.Allocate<UnarySDNode>(); 2299 new (N) UnarySDNode(Opcode, VTs, Operand); 2300 } 2301 2302 AllNodes.push_back(N); 2303#ifndef NDEBUG 2304 VerifyNode(N); 2305#endif 2306 return SDValue(N, 0); 2307} 2308 2309SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2310 MVT VT, 2311 ConstantSDNode *Cst1, 2312 ConstantSDNode *Cst2) { 2313 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2314 2315 switch (Opcode) { 2316 case ISD::ADD: return getConstant(C1 + C2, VT); 2317 case ISD::SUB: return getConstant(C1 - C2, VT); 2318 case ISD::MUL: return getConstant(C1 * C2, VT); 2319 case ISD::UDIV: 2320 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2321 break; 2322 case ISD::UREM: 2323 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2324 break; 2325 case ISD::SDIV: 2326 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2327 break; 2328 case ISD::SREM: 2329 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2330 break; 2331 case ISD::AND: return getConstant(C1 & C2, VT); 2332 case ISD::OR: return getConstant(C1 | C2, VT); 2333 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2334 case ISD::SHL: return getConstant(C1 << C2, VT); 2335 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2336 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2337 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2338 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2339 default: break; 2340 } 2341 2342 return SDValue(); 2343} 2344 2345SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2346 SDValue N1, SDValue N2) { 2347 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2348 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2349 switch (Opcode) { 2350 default: break; 2351 case ISD::TokenFactor: 2352 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2353 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2354 // Fold trivial token factors. 2355 if (N1.getOpcode() == ISD::EntryToken) return N2; 2356 if (N2.getOpcode() == ISD::EntryToken) return N1; 2357 if (N1 == N2) return N1; 2358 break; 2359 case ISD::CONCAT_VECTORS: 2360 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2361 // one big BUILD_VECTOR. 2362 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2363 N2.getOpcode() == ISD::BUILD_VECTOR) { 2364 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2365 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2366 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2367 } 2368 break; 2369 case ISD::AND: 2370 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2371 N1.getValueType() == VT && "Binary operator types must match!"); 2372 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2373 // worth handling here. 2374 if (N2C && N2C->isNullValue()) 2375 return N2; 2376 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2377 return N1; 2378 break; 2379 case ISD::OR: 2380 case ISD::XOR: 2381 case ISD::ADD: 2382 case ISD::SUB: 2383 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2384 N1.getValueType() == VT && "Binary operator types must match!"); 2385 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2386 // it's worth handling here. 2387 if (N2C && N2C->isNullValue()) 2388 return N1; 2389 break; 2390 case ISD::UDIV: 2391 case ISD::UREM: 2392 case ISD::MULHU: 2393 case ISD::MULHS: 2394 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2395 // fall through 2396 case ISD::MUL: 2397 case ISD::SDIV: 2398 case ISD::SREM: 2399 case ISD::FADD: 2400 case ISD::FSUB: 2401 case ISD::FMUL: 2402 case ISD::FDIV: 2403 case ISD::FREM: 2404 assert(N1.getValueType() == N2.getValueType() && 2405 N1.getValueType() == VT && "Binary operator types must match!"); 2406 break; 2407 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2408 assert(N1.getValueType() == VT && 2409 N1.getValueType().isFloatingPoint() && 2410 N2.getValueType().isFloatingPoint() && 2411 "Invalid FCOPYSIGN!"); 2412 break; 2413 case ISD::SHL: 2414 case ISD::SRA: 2415 case ISD::SRL: 2416 case ISD::ROTL: 2417 case ISD::ROTR: 2418 assert(VT == N1.getValueType() && 2419 "Shift operators return type must be the same as their first arg"); 2420 assert(VT.isInteger() && N2.getValueType().isInteger() && 2421 "Shifts only work on integers"); 2422 assert((N2.getValueType() == TLI.getShiftAmountTy() || 2423 (N2.getValueType().isVector() && N2.getValueType().isInteger())) && 2424 "Wrong type for shift amount"); 2425 2426 // Always fold shifts of i1 values so the code generator doesn't need to 2427 // handle them. Since we know the size of the shift has to be less than the 2428 // size of the value, the shift/rotate count is guaranteed to be zero. 2429 if (VT == MVT::i1) 2430 return N1; 2431 break; 2432 case ISD::FP_ROUND_INREG: { 2433 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2434 assert(VT == N1.getValueType() && "Not an inreg round!"); 2435 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2436 "Cannot FP_ROUND_INREG integer types"); 2437 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2438 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2439 break; 2440 } 2441 case ISD::FP_ROUND: 2442 assert(VT.isFloatingPoint() && 2443 N1.getValueType().isFloatingPoint() && 2444 VT.bitsLE(N1.getValueType()) && 2445 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2446 if (N1.getValueType() == VT) return N1; // noop conversion. 2447 break; 2448 case ISD::AssertSext: 2449 case ISD::AssertZext: { 2450 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2451 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2452 assert(VT.isInteger() && EVT.isInteger() && 2453 "Cannot *_EXTEND_INREG FP types"); 2454 assert(EVT.bitsLE(VT) && "Not extending!"); 2455 if (VT == EVT) return N1; // noop assertion. 2456 break; 2457 } 2458 case ISD::SIGN_EXTEND_INREG: { 2459 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2460 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2461 assert(VT.isInteger() && EVT.isInteger() && 2462 "Cannot *_EXTEND_INREG FP types"); 2463 assert(EVT.bitsLE(VT) && "Not extending!"); 2464 if (EVT == VT) return N1; // Not actually extending 2465 2466 if (N1C) { 2467 APInt Val = N1C->getAPIntValue(); 2468 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2469 Val <<= Val.getBitWidth()-FromBits; 2470 Val = Val.ashr(Val.getBitWidth()-FromBits); 2471 return getConstant(Val, VT); 2472 } 2473 break; 2474 } 2475 case ISD::EXTRACT_VECTOR_ELT: 2476 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2477 if (N1.getOpcode() == ISD::UNDEF) 2478 return getNode(ISD::UNDEF, VT); 2479 2480 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2481 // expanding copies of large vectors from registers. 2482 if (N2C && 2483 N1.getOpcode() == ISD::CONCAT_VECTORS && 2484 N1.getNumOperands() > 0) { 2485 unsigned Factor = 2486 N1.getOperand(0).getValueType().getVectorNumElements(); 2487 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, 2488 N1.getOperand(N2C->getZExtValue() / Factor), 2489 getConstant(N2C->getZExtValue() % Factor, 2490 N2.getValueType())); 2491 } 2492 2493 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2494 // expanding large vector constants. 2495 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) 2496 return N1.getOperand(N2C->getZExtValue()); 2497 2498 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2499 // operations are lowered to scalars. 2500 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2501 if (N1.getOperand(2) == N2) 2502 return N1.getOperand(1); 2503 else 2504 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2); 2505 } 2506 break; 2507 case ISD::EXTRACT_ELEMENT: 2508 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2509 assert(!N1.getValueType().isVector() && !VT.isVector() && 2510 (N1.getValueType().isInteger() == VT.isInteger()) && 2511 "Wrong types for EXTRACT_ELEMENT!"); 2512 2513 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2514 // 64-bit integers into 32-bit parts. Instead of building the extract of 2515 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2516 if (N1.getOpcode() == ISD::BUILD_PAIR) 2517 return N1.getOperand(N2C->getZExtValue()); 2518 2519 // EXTRACT_ELEMENT of a constant int is also very common. 2520 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2521 unsigned ElementSize = VT.getSizeInBits(); 2522 unsigned Shift = ElementSize * N2C->getZExtValue(); 2523 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2524 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2525 } 2526 break; 2527 case ISD::EXTRACT_SUBVECTOR: 2528 if (N1.getValueType() == VT) // Trivial extraction. 2529 return N1; 2530 break; 2531 } 2532 2533 if (N1C) { 2534 if (N2C) { 2535 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2536 if (SV.getNode()) return SV; 2537 } else { // Cannonicalize constant to RHS if commutative 2538 if (isCommutativeBinOp(Opcode)) { 2539 std::swap(N1C, N2C); 2540 std::swap(N1, N2); 2541 } 2542 } 2543 } 2544 2545 // Constant fold FP operations. 2546 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2547 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2548 if (N1CFP) { 2549 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2550 // Cannonicalize constant to RHS if commutative 2551 std::swap(N1CFP, N2CFP); 2552 std::swap(N1, N2); 2553 } else if (N2CFP && VT != MVT::ppcf128) { 2554 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2555 APFloat::opStatus s; 2556 switch (Opcode) { 2557 case ISD::FADD: 2558 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2559 if (s != APFloat::opInvalidOp) 2560 return getConstantFP(V1, VT); 2561 break; 2562 case ISD::FSUB: 2563 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2564 if (s!=APFloat::opInvalidOp) 2565 return getConstantFP(V1, VT); 2566 break; 2567 case ISD::FMUL: 2568 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2569 if (s!=APFloat::opInvalidOp) 2570 return getConstantFP(V1, VT); 2571 break; 2572 case ISD::FDIV: 2573 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2574 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2575 return getConstantFP(V1, VT); 2576 break; 2577 case ISD::FREM : 2578 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2579 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2580 return getConstantFP(V1, VT); 2581 break; 2582 case ISD::FCOPYSIGN: 2583 V1.copySign(V2); 2584 return getConstantFP(V1, VT); 2585 default: break; 2586 } 2587 } 2588 } 2589 2590 // Canonicalize an UNDEF to the RHS, even over a constant. 2591 if (N1.getOpcode() == ISD::UNDEF) { 2592 if (isCommutativeBinOp(Opcode)) { 2593 std::swap(N1, N2); 2594 } else { 2595 switch (Opcode) { 2596 case ISD::FP_ROUND_INREG: 2597 case ISD::SIGN_EXTEND_INREG: 2598 case ISD::SUB: 2599 case ISD::FSUB: 2600 case ISD::FDIV: 2601 case ISD::FREM: 2602 case ISD::SRA: 2603 return N1; // fold op(undef, arg2) -> undef 2604 case ISD::UDIV: 2605 case ISD::SDIV: 2606 case ISD::UREM: 2607 case ISD::SREM: 2608 case ISD::SRL: 2609 case ISD::SHL: 2610 if (!VT.isVector()) 2611 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2612 // For vectors, we can't easily build an all zero vector, just return 2613 // the LHS. 2614 return N2; 2615 } 2616 } 2617 } 2618 2619 // Fold a bunch of operators when the RHS is undef. 2620 if (N2.getOpcode() == ISD::UNDEF) { 2621 switch (Opcode) { 2622 case ISD::XOR: 2623 if (N1.getOpcode() == ISD::UNDEF) 2624 // Handle undef ^ undef -> 0 special case. This is a common 2625 // idiom (misuse). 2626 return getConstant(0, VT); 2627 // fallthrough 2628 case ISD::ADD: 2629 case ISD::ADDC: 2630 case ISD::ADDE: 2631 case ISD::SUB: 2632 case ISD::FADD: 2633 case ISD::FSUB: 2634 case ISD::FMUL: 2635 case ISD::FDIV: 2636 case ISD::FREM: 2637 case ISD::UDIV: 2638 case ISD::SDIV: 2639 case ISD::UREM: 2640 case ISD::SREM: 2641 return N2; // fold op(arg1, undef) -> undef 2642 case ISD::MUL: 2643 case ISD::AND: 2644 case ISD::SRL: 2645 case ISD::SHL: 2646 if (!VT.isVector()) 2647 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2648 // For vectors, we can't easily build an all zero vector, just return 2649 // the LHS. 2650 return N1; 2651 case ISD::OR: 2652 if (!VT.isVector()) 2653 return getConstant(VT.getIntegerVTBitMask(), VT); 2654 // For vectors, we can't easily build an all one vector, just return 2655 // the LHS. 2656 return N1; 2657 case ISD::SRA: 2658 return N1; 2659 } 2660 } 2661 2662 // Memoize this node if possible. 2663 SDNode *N; 2664 SDVTList VTs = getVTList(VT); 2665 if (VT != MVT::Flag) { 2666 SDValue Ops[] = { N1, N2 }; 2667 FoldingSetNodeID ID; 2668 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2669 void *IP = 0; 2670 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2671 return SDValue(E, 0); 2672 N = NodeAllocator.Allocate<BinarySDNode>(); 2673 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2674 CSEMap.InsertNode(N, IP); 2675 } else { 2676 N = NodeAllocator.Allocate<BinarySDNode>(); 2677 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2678 } 2679 2680 AllNodes.push_back(N); 2681#ifndef NDEBUG 2682 VerifyNode(N); 2683#endif 2684 return SDValue(N, 0); 2685} 2686 2687SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2688 SDValue N1, SDValue N2, SDValue N3) { 2689 // Perform various simplifications. 2690 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2691 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2692 switch (Opcode) { 2693 case ISD::CONCAT_VECTORS: 2694 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2695 // one big BUILD_VECTOR. 2696 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2697 N2.getOpcode() == ISD::BUILD_VECTOR && 2698 N3.getOpcode() == ISD::BUILD_VECTOR) { 2699 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2700 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2701 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2702 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2703 } 2704 break; 2705 case ISD::SETCC: { 2706 // Use FoldSetCC to simplify SETCC's. 2707 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 2708 if (Simp.getNode()) return Simp; 2709 break; 2710 } 2711 case ISD::SELECT: 2712 if (N1C) { 2713 if (N1C->getZExtValue()) 2714 return N2; // select true, X, Y -> X 2715 else 2716 return N3; // select false, X, Y -> Y 2717 } 2718 2719 if (N2 == N3) return N2; // select C, X, X -> X 2720 break; 2721 case ISD::BRCOND: 2722 if (N2C) { 2723 if (N2C->getZExtValue()) // Unconditional branch 2724 return getNode(ISD::BR, MVT::Other, N1, N3); 2725 else 2726 return N1; // Never-taken branch 2727 } 2728 break; 2729 case ISD::VECTOR_SHUFFLE: 2730 assert(N1.getValueType() == N2.getValueType() && 2731 N1.getValueType().isVector() && 2732 VT.isVector() && N3.getValueType().isVector() && 2733 N3.getOpcode() == ISD::BUILD_VECTOR && 2734 VT.getVectorNumElements() == N3.getNumOperands() && 2735 "Illegal VECTOR_SHUFFLE node!"); 2736 break; 2737 case ISD::BIT_CONVERT: 2738 // Fold bit_convert nodes from a type to themselves. 2739 if (N1.getValueType() == VT) 2740 return N1; 2741 break; 2742 } 2743 2744 // Memoize node if it doesn't produce a flag. 2745 SDNode *N; 2746 SDVTList VTs = getVTList(VT); 2747 if (VT != MVT::Flag) { 2748 SDValue Ops[] = { N1, N2, N3 }; 2749 FoldingSetNodeID ID; 2750 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2751 void *IP = 0; 2752 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2753 return SDValue(E, 0); 2754 N = NodeAllocator.Allocate<TernarySDNode>(); 2755 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2756 CSEMap.InsertNode(N, IP); 2757 } else { 2758 N = NodeAllocator.Allocate<TernarySDNode>(); 2759 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2760 } 2761 AllNodes.push_back(N); 2762#ifndef NDEBUG 2763 VerifyNode(N); 2764#endif 2765 return SDValue(N, 0); 2766} 2767 2768SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2769 SDValue N1, SDValue N2, SDValue N3, 2770 SDValue N4) { 2771 SDValue Ops[] = { N1, N2, N3, N4 }; 2772 return getNode(Opcode, VT, Ops, 4); 2773} 2774 2775SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2776 SDValue N1, SDValue N2, SDValue N3, 2777 SDValue N4, SDValue N5) { 2778 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2779 return getNode(Opcode, VT, Ops, 5); 2780} 2781 2782/// getMemsetValue - Vectorized representation of the memset value 2783/// operand. 2784static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) { 2785 unsigned NumBits = VT.isVector() ? 2786 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2787 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2788 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2789 unsigned Shift = 8; 2790 for (unsigned i = NumBits; i > 8; i >>= 1) { 2791 Val = (Val << Shift) | Val; 2792 Shift <<= 1; 2793 } 2794 if (VT.isInteger()) 2795 return DAG.getConstant(Val, VT); 2796 return DAG.getConstantFP(APFloat(Val), VT); 2797 } 2798 2799 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2800 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 2801 unsigned Shift = 8; 2802 for (unsigned i = NumBits; i > 8; i >>= 1) { 2803 Value = DAG.getNode(ISD::OR, VT, 2804 DAG.getNode(ISD::SHL, VT, Value, 2805 DAG.getConstant(Shift, 2806 TLI.getShiftAmountTy())), 2807 Value); 2808 Shift <<= 1; 2809 } 2810 2811 return Value; 2812} 2813 2814/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2815/// used when a memcpy is turned into a memset when the source is a constant 2816/// string ptr. 2817static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG, 2818 const TargetLowering &TLI, 2819 std::string &Str, unsigned Offset) { 2820 // Handle vector with all elements zero. 2821 if (Str.empty()) { 2822 if (VT.isInteger()) 2823 return DAG.getConstant(0, VT); 2824 unsigned NumElts = VT.getVectorNumElements(); 2825 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2826 return DAG.getNode(ISD::BIT_CONVERT, VT, 2827 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2828 } 2829 2830 assert(!VT.isVector() && "Can't handle vector type here!"); 2831 unsigned NumBits = VT.getSizeInBits(); 2832 unsigned MSB = NumBits / 8; 2833 uint64_t Val = 0; 2834 if (TLI.isLittleEndian()) 2835 Offset = Offset + MSB - 1; 2836 for (unsigned i = 0; i != MSB; ++i) { 2837 Val = (Val << 8) | (unsigned char)Str[Offset]; 2838 Offset += TLI.isLittleEndian() ? -1 : 1; 2839 } 2840 return DAG.getConstant(Val, VT); 2841} 2842 2843/// getMemBasePlusOffset - Returns base and offset node for the 2844/// 2845static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2846 SelectionDAG &DAG) { 2847 MVT VT = Base.getValueType(); 2848 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 2849} 2850 2851/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2852/// 2853static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2854 unsigned SrcDelta = 0; 2855 GlobalAddressSDNode *G = NULL; 2856 if (Src.getOpcode() == ISD::GlobalAddress) 2857 G = cast<GlobalAddressSDNode>(Src); 2858 else if (Src.getOpcode() == ISD::ADD && 2859 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2860 Src.getOperand(1).getOpcode() == ISD::Constant) { 2861 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2862 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 2863 } 2864 if (!G) 2865 return false; 2866 2867 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2868 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 2869 return true; 2870 2871 return false; 2872} 2873 2874/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2875/// to replace the memset / memcpy is below the threshold. It also returns the 2876/// types of the sequence of memory ops to perform memset / memcpy. 2877static 2878bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 2879 SDValue Dst, SDValue Src, 2880 unsigned Limit, uint64_t Size, unsigned &Align, 2881 std::string &Str, bool &isSrcStr, 2882 SelectionDAG &DAG, 2883 const TargetLowering &TLI) { 2884 isSrcStr = isMemSrcFromString(Src, Str); 2885 bool isSrcConst = isa<ConstantSDNode>(Src); 2886 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 2887 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 2888 if (VT != MVT::iAny) { 2889 unsigned NewAlign = (unsigned) 2890 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 2891 // If source is a string constant, this will require an unaligned load. 2892 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 2893 if (Dst.getOpcode() != ISD::FrameIndex) { 2894 // Can't change destination alignment. It requires a unaligned store. 2895 if (AllowUnalign) 2896 VT = MVT::iAny; 2897 } else { 2898 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 2899 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2900 if (MFI->isFixedObjectIndex(FI)) { 2901 // Can't change destination alignment. It requires a unaligned store. 2902 if (AllowUnalign) 2903 VT = MVT::iAny; 2904 } else { 2905 // Give the stack frame object a larger alignment if needed. 2906 if (MFI->getObjectAlignment(FI) < NewAlign) 2907 MFI->setObjectAlignment(FI, NewAlign); 2908 Align = NewAlign; 2909 } 2910 } 2911 } 2912 } 2913 2914 if (VT == MVT::iAny) { 2915 if (AllowUnalign) { 2916 VT = MVT::i64; 2917 } else { 2918 switch (Align & 7) { 2919 case 0: VT = MVT::i64; break; 2920 case 4: VT = MVT::i32; break; 2921 case 2: VT = MVT::i16; break; 2922 default: VT = MVT::i8; break; 2923 } 2924 } 2925 2926 MVT LVT = MVT::i64; 2927 while (!TLI.isTypeLegal(LVT)) 2928 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 2929 assert(LVT.isInteger()); 2930 2931 if (VT.bitsGT(LVT)) 2932 VT = LVT; 2933 } 2934 2935 unsigned NumMemOps = 0; 2936 while (Size != 0) { 2937 unsigned VTSize = VT.getSizeInBits() / 8; 2938 while (VTSize > Size) { 2939 // For now, only use non-vector load / store's for the left-over pieces. 2940 if (VT.isVector()) { 2941 VT = MVT::i64; 2942 while (!TLI.isTypeLegal(VT)) 2943 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2944 VTSize = VT.getSizeInBits() / 8; 2945 } else { 2946 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2947 VTSize >>= 1; 2948 } 2949 } 2950 2951 if (++NumMemOps > Limit) 2952 return false; 2953 MemOps.push_back(VT); 2954 Size -= VTSize; 2955 } 2956 2957 return true; 2958} 2959 2960static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, 2961 SDValue Chain, SDValue Dst, 2962 SDValue Src, uint64_t Size, 2963 unsigned Align, bool AlwaysInline, 2964 const Value *DstSV, uint64_t DstSVOff, 2965 const Value *SrcSV, uint64_t SrcSVOff){ 2966 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2967 2968 // Expand memcpy to a series of load and store ops if the size operand falls 2969 // below a certain threshold. 2970 std::vector<MVT> MemOps; 2971 uint64_t Limit = -1ULL; 2972 if (!AlwaysInline) 2973 Limit = TLI.getMaxStoresPerMemcpy(); 2974 unsigned DstAlign = Align; // Destination alignment can change. 2975 std::string Str; 2976 bool CopyFromStr; 2977 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 2978 Str, CopyFromStr, DAG, TLI)) 2979 return SDValue(); 2980 2981 2982 bool isZeroStr = CopyFromStr && Str.empty(); 2983 SmallVector<SDValue, 8> OutChains; 2984 unsigned NumMemOps = MemOps.size(); 2985 uint64_t SrcOff = 0, DstOff = 0; 2986 for (unsigned i = 0; i < NumMemOps; i++) { 2987 MVT VT = MemOps[i]; 2988 unsigned VTSize = VT.getSizeInBits() / 8; 2989 SDValue Value, Store; 2990 2991 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 2992 // It's unlikely a store of a vector immediate can be done in a single 2993 // instruction. It would require a load from a constantpool first. 2994 // We also handle store a vector with all zero's. 2995 // FIXME: Handle other cases where store of vector immediate is done in 2996 // a single instruction. 2997 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 2998 Store = DAG.getStore(Chain, Value, 2999 getMemBasePlusOffset(Dst, DstOff, DAG), 3000 DstSV, DstSVOff + DstOff, false, DstAlign); 3001 } else { 3002 Value = DAG.getLoad(VT, Chain, 3003 getMemBasePlusOffset(Src, SrcOff, DAG), 3004 SrcSV, SrcSVOff + SrcOff, false, Align); 3005 Store = DAG.getStore(Chain, Value, 3006 getMemBasePlusOffset(Dst, DstOff, DAG), 3007 DstSV, DstSVOff + DstOff, false, DstAlign); 3008 } 3009 OutChains.push_back(Store); 3010 SrcOff += VTSize; 3011 DstOff += VTSize; 3012 } 3013 3014 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3015 &OutChains[0], OutChains.size()); 3016} 3017 3018static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, 3019 SDValue Chain, SDValue Dst, 3020 SDValue Src, uint64_t Size, 3021 unsigned Align, bool AlwaysInline, 3022 const Value *DstSV, uint64_t DstSVOff, 3023 const Value *SrcSV, uint64_t SrcSVOff){ 3024 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3025 3026 // Expand memmove to a series of load and store ops if the size operand falls 3027 // below a certain threshold. 3028 std::vector<MVT> MemOps; 3029 uint64_t Limit = -1ULL; 3030 if (!AlwaysInline) 3031 Limit = TLI.getMaxStoresPerMemmove(); 3032 unsigned DstAlign = Align; // Destination alignment can change. 3033 std::string Str; 3034 bool CopyFromStr; 3035 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3036 Str, CopyFromStr, DAG, TLI)) 3037 return SDValue(); 3038 3039 uint64_t SrcOff = 0, DstOff = 0; 3040 3041 SmallVector<SDValue, 8> LoadValues; 3042 SmallVector<SDValue, 8> LoadChains; 3043 SmallVector<SDValue, 8> OutChains; 3044 unsigned NumMemOps = MemOps.size(); 3045 for (unsigned i = 0; i < NumMemOps; i++) { 3046 MVT VT = MemOps[i]; 3047 unsigned VTSize = VT.getSizeInBits() / 8; 3048 SDValue Value, Store; 3049 3050 Value = DAG.getLoad(VT, Chain, 3051 getMemBasePlusOffset(Src, SrcOff, DAG), 3052 SrcSV, SrcSVOff + SrcOff, false, Align); 3053 LoadValues.push_back(Value); 3054 LoadChains.push_back(Value.getValue(1)); 3055 SrcOff += VTSize; 3056 } 3057 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3058 &LoadChains[0], LoadChains.size()); 3059 OutChains.clear(); 3060 for (unsigned i = 0; i < NumMemOps; i++) { 3061 MVT VT = MemOps[i]; 3062 unsigned VTSize = VT.getSizeInBits() / 8; 3063 SDValue Value, Store; 3064 3065 Store = DAG.getStore(Chain, LoadValues[i], 3066 getMemBasePlusOffset(Dst, DstOff, DAG), 3067 DstSV, DstSVOff + DstOff, false, DstAlign); 3068 OutChains.push_back(Store); 3069 DstOff += VTSize; 3070 } 3071 3072 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3073 &OutChains[0], OutChains.size()); 3074} 3075 3076static SDValue getMemsetStores(SelectionDAG &DAG, 3077 SDValue Chain, SDValue Dst, 3078 SDValue Src, uint64_t Size, 3079 unsigned Align, 3080 const Value *DstSV, uint64_t DstSVOff) { 3081 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3082 3083 // Expand memset to a series of load/store ops if the size operand 3084 // falls below a certain threshold. 3085 std::vector<MVT> MemOps; 3086 std::string Str; 3087 bool CopyFromStr; 3088 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3089 Size, Align, Str, CopyFromStr, DAG, TLI)) 3090 return SDValue(); 3091 3092 SmallVector<SDValue, 8> OutChains; 3093 uint64_t DstOff = 0; 3094 3095 unsigned NumMemOps = MemOps.size(); 3096 for (unsigned i = 0; i < NumMemOps; i++) { 3097 MVT VT = MemOps[i]; 3098 unsigned VTSize = VT.getSizeInBits() / 8; 3099 SDValue Value = getMemsetValue(Src, VT, DAG); 3100 SDValue Store = DAG.getStore(Chain, Value, 3101 getMemBasePlusOffset(Dst, DstOff, DAG), 3102 DstSV, DstSVOff + DstOff); 3103 OutChains.push_back(Store); 3104 DstOff += VTSize; 3105 } 3106 3107 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3108 &OutChains[0], OutChains.size()); 3109} 3110 3111SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst, 3112 SDValue Src, SDValue Size, 3113 unsigned Align, bool AlwaysInline, 3114 const Value *DstSV, uint64_t DstSVOff, 3115 const Value *SrcSV, uint64_t SrcSVOff) { 3116 3117 // Check to see if we should lower the memcpy to loads and stores first. 3118 // For cases within the target-specified limits, this is the best choice. 3119 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3120 if (ConstantSize) { 3121 // Memcpy with size zero? Just return the original chain. 3122 if (ConstantSize->isNullValue()) 3123 return Chain; 3124 3125 SDValue Result = 3126 getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3127 ConstantSize->getZExtValue(), 3128 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3129 if (Result.getNode()) 3130 return Result; 3131 } 3132 3133 // Then check to see if we should lower the memcpy with target-specific 3134 // code. If the target chooses to do this, this is the next best. 3135 SDValue Result = 3136 TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align, 3137 AlwaysInline, 3138 DstSV, DstSVOff, SrcSV, SrcSVOff); 3139 if (Result.getNode()) 3140 return Result; 3141 3142 // If we really need inline code and the target declined to provide it, 3143 // use a (potentially long) sequence of loads and stores. 3144 if (AlwaysInline) { 3145 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3146 return getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3147 ConstantSize->getZExtValue(), Align, true, 3148 DstSV, DstSVOff, SrcSV, SrcSVOff); 3149 } 3150 3151 // Emit a library call. 3152 TargetLowering::ArgListTy Args; 3153 TargetLowering::ArgListEntry Entry; 3154 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3155 Entry.Node = Dst; Args.push_back(Entry); 3156 Entry.Node = Src; Args.push_back(Entry); 3157 Entry.Node = Size; Args.push_back(Entry); 3158 std::pair<SDValue,SDValue> CallResult = 3159 TLI.LowerCallTo(Chain, Type::VoidTy, 3160 false, false, false, false, CallingConv::C, false, 3161 getExternalSymbol("memcpy", TLI.getPointerTy()), 3162 Args, *this); 3163 return CallResult.second; 3164} 3165 3166SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst, 3167 SDValue Src, SDValue Size, 3168 unsigned Align, 3169 const Value *DstSV, uint64_t DstSVOff, 3170 const Value *SrcSV, uint64_t SrcSVOff) { 3171 3172 // Check to see if we should lower the memmove to loads and stores first. 3173 // For cases within the target-specified limits, this is the best choice. 3174 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3175 if (ConstantSize) { 3176 // Memmove with size zero? Just return the original chain. 3177 if (ConstantSize->isNullValue()) 3178 return Chain; 3179 3180 SDValue Result = 3181 getMemmoveLoadsAndStores(*this, Chain, Dst, Src, 3182 ConstantSize->getZExtValue(), 3183 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3184 if (Result.getNode()) 3185 return Result; 3186 } 3187 3188 // Then check to see if we should lower the memmove with target-specific 3189 // code. If the target chooses to do this, this is the next best. 3190 SDValue Result = 3191 TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align, 3192 DstSV, DstSVOff, SrcSV, SrcSVOff); 3193 if (Result.getNode()) 3194 return Result; 3195 3196 // Emit a library call. 3197 TargetLowering::ArgListTy Args; 3198 TargetLowering::ArgListEntry Entry; 3199 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3200 Entry.Node = Dst; Args.push_back(Entry); 3201 Entry.Node = Src; Args.push_back(Entry); 3202 Entry.Node = Size; Args.push_back(Entry); 3203 std::pair<SDValue,SDValue> CallResult = 3204 TLI.LowerCallTo(Chain, Type::VoidTy, 3205 false, false, false, false, CallingConv::C, false, 3206 getExternalSymbol("memmove", TLI.getPointerTy()), 3207 Args, *this); 3208 return CallResult.second; 3209} 3210 3211SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst, 3212 SDValue Src, SDValue Size, 3213 unsigned Align, 3214 const Value *DstSV, uint64_t DstSVOff) { 3215 3216 // Check to see if we should lower the memset to stores first. 3217 // For cases within the target-specified limits, this is the best choice. 3218 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3219 if (ConstantSize) { 3220 // Memset with size zero? Just return the original chain. 3221 if (ConstantSize->isNullValue()) 3222 return Chain; 3223 3224 SDValue Result = 3225 getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getZExtValue(), 3226 Align, DstSV, DstSVOff); 3227 if (Result.getNode()) 3228 return Result; 3229 } 3230 3231 // Then check to see if we should lower the memset with target-specific 3232 // code. If the target chooses to do this, this is the next best. 3233 SDValue Result = 3234 TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align, 3235 DstSV, DstSVOff); 3236 if (Result.getNode()) 3237 return Result; 3238 3239 // Emit a library call. 3240 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3241 TargetLowering::ArgListTy Args; 3242 TargetLowering::ArgListEntry Entry; 3243 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3244 Args.push_back(Entry); 3245 // Extend or truncate the argument to be an i32 value for the call. 3246 if (Src.getValueType().bitsGT(MVT::i32)) 3247 Src = getNode(ISD::TRUNCATE, MVT::i32, Src); 3248 else 3249 Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src); 3250 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3251 Args.push_back(Entry); 3252 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3253 Args.push_back(Entry); 3254 std::pair<SDValue,SDValue> CallResult = 3255 TLI.LowerCallTo(Chain, Type::VoidTy, 3256 false, false, false, false, CallingConv::C, false, 3257 getExternalSymbol("memset", TLI.getPointerTy()), 3258 Args, *this); 3259 return CallResult.second; 3260} 3261 3262SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3263 SDValue Ptr, SDValue Cmp, 3264 SDValue Swp, const Value* PtrVal, 3265 unsigned Alignment) { 3266 assert((Opcode == ISD::ATOMIC_CMP_SWAP_8 || 3267 Opcode == ISD::ATOMIC_CMP_SWAP_16 || 3268 Opcode == ISD::ATOMIC_CMP_SWAP_32 || 3269 Opcode == ISD::ATOMIC_CMP_SWAP_64) && "Invalid Atomic Op"); 3270 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3271 3272 MVT VT = Cmp.getValueType(); 3273 3274 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3275 Alignment = getMVTAlignment(VT); 3276 3277 SDVTList VTs = getVTList(VT, MVT::Other); 3278 FoldingSetNodeID ID; 3279 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3280 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3281 void* IP = 0; 3282 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3283 return SDValue(E, 0); 3284 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3285 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3286 CSEMap.InsertNode(N, IP); 3287 AllNodes.push_back(N); 3288 return SDValue(N, 0); 3289} 3290 3291SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3292 SDValue Ptr, SDValue Val, 3293 const Value* PtrVal, 3294 unsigned Alignment) { 3295 assert((Opcode == ISD::ATOMIC_LOAD_ADD_8 || 3296 Opcode == ISD::ATOMIC_LOAD_SUB_8 || 3297 Opcode == ISD::ATOMIC_LOAD_AND_8 || 3298 Opcode == ISD::ATOMIC_LOAD_OR_8 || 3299 Opcode == ISD::ATOMIC_LOAD_XOR_8 || 3300 Opcode == ISD::ATOMIC_LOAD_NAND_8 || 3301 Opcode == ISD::ATOMIC_LOAD_MIN_8 || 3302 Opcode == ISD::ATOMIC_LOAD_MAX_8 || 3303 Opcode == ISD::ATOMIC_LOAD_UMIN_8 || 3304 Opcode == ISD::ATOMIC_LOAD_UMAX_8 || 3305 Opcode == ISD::ATOMIC_SWAP_8 || 3306 Opcode == ISD::ATOMIC_LOAD_ADD_16 || 3307 Opcode == ISD::ATOMIC_LOAD_SUB_16 || 3308 Opcode == ISD::ATOMIC_LOAD_AND_16 || 3309 Opcode == ISD::ATOMIC_LOAD_OR_16 || 3310 Opcode == ISD::ATOMIC_LOAD_XOR_16 || 3311 Opcode == ISD::ATOMIC_LOAD_NAND_16 || 3312 Opcode == ISD::ATOMIC_LOAD_MIN_16 || 3313 Opcode == ISD::ATOMIC_LOAD_MAX_16 || 3314 Opcode == ISD::ATOMIC_LOAD_UMIN_16 || 3315 Opcode == ISD::ATOMIC_LOAD_UMAX_16 || 3316 Opcode == ISD::ATOMIC_SWAP_16 || 3317 Opcode == ISD::ATOMIC_LOAD_ADD_32 || 3318 Opcode == ISD::ATOMIC_LOAD_SUB_32 || 3319 Opcode == ISD::ATOMIC_LOAD_AND_32 || 3320 Opcode == ISD::ATOMIC_LOAD_OR_32 || 3321 Opcode == ISD::ATOMIC_LOAD_XOR_32 || 3322 Opcode == ISD::ATOMIC_LOAD_NAND_32 || 3323 Opcode == ISD::ATOMIC_LOAD_MIN_32 || 3324 Opcode == ISD::ATOMIC_LOAD_MAX_32 || 3325 Opcode == ISD::ATOMIC_LOAD_UMIN_32 || 3326 Opcode == ISD::ATOMIC_LOAD_UMAX_32 || 3327 Opcode == ISD::ATOMIC_SWAP_32 || 3328 Opcode == ISD::ATOMIC_LOAD_ADD_64 || 3329 Opcode == ISD::ATOMIC_LOAD_SUB_64 || 3330 Opcode == ISD::ATOMIC_LOAD_AND_64 || 3331 Opcode == ISD::ATOMIC_LOAD_OR_64 || 3332 Opcode == ISD::ATOMIC_LOAD_XOR_64 || 3333 Opcode == ISD::ATOMIC_LOAD_NAND_64 || 3334 Opcode == ISD::ATOMIC_LOAD_MIN_64 || 3335 Opcode == ISD::ATOMIC_LOAD_MAX_64 || 3336 Opcode == ISD::ATOMIC_LOAD_UMIN_64 || 3337 Opcode == ISD::ATOMIC_LOAD_UMAX_64 || 3338 Opcode == ISD::ATOMIC_SWAP_64) && "Invalid Atomic Op"); 3339 3340 MVT VT = Val.getValueType(); 3341 3342 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3343 Alignment = getMVTAlignment(VT); 3344 3345 SDVTList VTs = getVTList(VT, MVT::Other); 3346 FoldingSetNodeID ID; 3347 SDValue Ops[] = {Chain, Ptr, Val}; 3348 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3349 void* IP = 0; 3350 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3351 return SDValue(E, 0); 3352 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3353 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Val, PtrVal, Alignment); 3354 CSEMap.InsertNode(N, IP); 3355 AllNodes.push_back(N); 3356 return SDValue(N, 0); 3357} 3358 3359/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3360/// Allowed to return something different (and simpler) if Simplify is true. 3361SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps) { 3362 if (NumOps == 1) 3363 return Ops[0]; 3364 3365 SmallVector<MVT, 4> VTs; 3366 VTs.reserve(NumOps); 3367 for (unsigned i = 0; i < NumOps; ++i) 3368 VTs.push_back(Ops[i].getValueType()); 3369 return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps); 3370} 3371 3372SDValue 3373SelectionDAG::getMemIntrinsicNode(unsigned Opcode, 3374 const MVT *VTs, unsigned NumVTs, 3375 const SDValue *Ops, unsigned NumOps, 3376 MVT MemVT, const Value *srcValue, int SVOff, 3377 unsigned Align, bool Vol, 3378 bool ReadMem, bool WriteMem) { 3379 return getMemIntrinsicNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps, 3380 MemVT, srcValue, SVOff, Align, Vol, 3381 ReadMem, WriteMem); 3382} 3383 3384SDValue 3385SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDVTList VTList, 3386 const SDValue *Ops, unsigned NumOps, 3387 MVT MemVT, const Value *srcValue, int SVOff, 3388 unsigned Align, bool Vol, 3389 bool ReadMem, bool WriteMem) { 3390 // Memoize the node unless it returns a flag. 3391 MemIntrinsicSDNode *N; 3392 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3393 FoldingSetNodeID ID; 3394 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3395 void *IP = 0; 3396 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3397 return SDValue(E, 0); 3398 3399 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3400 new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, 3401 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3402 CSEMap.InsertNode(N, IP); 3403 } else { 3404 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3405 new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, 3406 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3407 } 3408 AllNodes.push_back(N); 3409 return SDValue(N, 0); 3410} 3411 3412SDValue 3413SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall, 3414 bool IsInreg, SDVTList VTs, 3415 const SDValue *Operands, unsigned NumOperands) { 3416 // Do not include isTailCall in the folding set profile. 3417 FoldingSetNodeID ID; 3418 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3419 ID.AddInteger(CallingConv); 3420 ID.AddInteger(IsVarArgs); 3421 void *IP = 0; 3422 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3423 // Instead of including isTailCall in the folding set, we just 3424 // set the flag of the existing node. 3425 if (!IsTailCall) 3426 cast<CallSDNode>(E)->setNotTailCall(); 3427 return SDValue(E, 0); 3428 } 3429 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3430 new (N) CallSDNode(CallingConv, IsVarArgs, IsTailCall, IsInreg, 3431 VTs, Operands, NumOperands); 3432 CSEMap.InsertNode(N, IP); 3433 AllNodes.push_back(N); 3434 return SDValue(N, 0); 3435} 3436 3437SDValue 3438SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, 3439 MVT VT, SDValue Chain, 3440 SDValue Ptr, SDValue Offset, 3441 const Value *SV, int SVOffset, MVT EVT, 3442 bool isVolatile, unsigned Alignment) { 3443 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3444 Alignment = getMVTAlignment(VT); 3445 3446 if (VT == EVT) { 3447 ExtType = ISD::NON_EXTLOAD; 3448 } else if (ExtType == ISD::NON_EXTLOAD) { 3449 assert(VT == EVT && "Non-extending load from different memory type!"); 3450 } else { 3451 // Extending load. 3452 if (VT.isVector()) 3453 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3454 "Invalid vector extload!"); 3455 else 3456 assert(EVT.bitsLT(VT) && 3457 "Should only be an extending load, not truncating!"); 3458 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3459 "Cannot sign/zero extend a FP/Vector load!"); 3460 assert(VT.isInteger() == EVT.isInteger() && 3461 "Cannot convert from FP to Int or Int -> FP!"); 3462 } 3463 3464 bool Indexed = AM != ISD::UNINDEXED; 3465 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3466 "Unindexed load with an offset!"); 3467 3468 SDVTList VTs = Indexed ? 3469 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3470 SDValue Ops[] = { Chain, Ptr, Offset }; 3471 FoldingSetNodeID ID; 3472 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3473 ID.AddInteger(AM); 3474 ID.AddInteger(ExtType); 3475 ID.AddInteger(EVT.getRawBits()); 3476 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3477 void *IP = 0; 3478 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3479 return SDValue(E, 0); 3480 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3481 new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset, 3482 Alignment, isVolatile); 3483 CSEMap.InsertNode(N, IP); 3484 AllNodes.push_back(N); 3485 return SDValue(N, 0); 3486} 3487 3488SDValue SelectionDAG::getLoad(MVT VT, 3489 SDValue Chain, SDValue Ptr, 3490 const Value *SV, int SVOffset, 3491 bool isVolatile, unsigned Alignment) { 3492 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3493 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3494 SV, SVOffset, VT, isVolatile, Alignment); 3495} 3496 3497SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT, 3498 SDValue Chain, SDValue Ptr, 3499 const Value *SV, 3500 int SVOffset, MVT EVT, 3501 bool isVolatile, unsigned Alignment) { 3502 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3503 return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef, 3504 SV, SVOffset, EVT, isVolatile, Alignment); 3505} 3506 3507SDValue 3508SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base, 3509 SDValue Offset, ISD::MemIndexedMode AM) { 3510 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3511 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3512 "Load is already a indexed load!"); 3513 return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), 3514 LD->getChain(), Base, Offset, LD->getSrcValue(), 3515 LD->getSrcValueOffset(), LD->getMemoryVT(), 3516 LD->isVolatile(), LD->getAlignment()); 3517} 3518 3519SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val, 3520 SDValue Ptr, const Value *SV, int SVOffset, 3521 bool isVolatile, unsigned Alignment) { 3522 MVT VT = Val.getValueType(); 3523 3524 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3525 Alignment = getMVTAlignment(VT); 3526 3527 SDVTList VTs = getVTList(MVT::Other); 3528 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3529 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3530 FoldingSetNodeID ID; 3531 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3532 ID.AddInteger(ISD::UNINDEXED); 3533 ID.AddInteger(false); 3534 ID.AddInteger(VT.getRawBits()); 3535 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3536 void *IP = 0; 3537 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3538 return SDValue(E, 0); 3539 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3540 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false, 3541 VT, SV, SVOffset, Alignment, isVolatile); 3542 CSEMap.InsertNode(N, IP); 3543 AllNodes.push_back(N); 3544 return SDValue(N, 0); 3545} 3546 3547SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val, 3548 SDValue Ptr, const Value *SV, 3549 int SVOffset, MVT SVT, 3550 bool isVolatile, unsigned Alignment) { 3551 MVT VT = Val.getValueType(); 3552 3553 if (VT == SVT) 3554 return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3555 3556 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3557 assert(VT.isInteger() == SVT.isInteger() && 3558 "Can't do FP-INT conversion!"); 3559 3560 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3561 Alignment = getMVTAlignment(VT); 3562 3563 SDVTList VTs = getVTList(MVT::Other); 3564 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3565 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3566 FoldingSetNodeID ID; 3567 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3568 ID.AddInteger(ISD::UNINDEXED); 3569 ID.AddInteger(1); 3570 ID.AddInteger(SVT.getRawBits()); 3571 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3572 void *IP = 0; 3573 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3574 return SDValue(E, 0); 3575 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3576 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true, 3577 SVT, SV, SVOffset, Alignment, isVolatile); 3578 CSEMap.InsertNode(N, IP); 3579 AllNodes.push_back(N); 3580 return SDValue(N, 0); 3581} 3582 3583SDValue 3584SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base, 3585 SDValue Offset, ISD::MemIndexedMode AM) { 3586 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3587 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3588 "Store is already a indexed store!"); 3589 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3590 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3591 FoldingSetNodeID ID; 3592 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3593 ID.AddInteger(AM); 3594 ID.AddInteger(ST->isTruncatingStore()); 3595 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3596 ID.AddInteger(ST->getRawFlags()); 3597 void *IP = 0; 3598 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3599 return SDValue(E, 0); 3600 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3601 new (N) StoreSDNode(Ops, VTs, AM, 3602 ST->isTruncatingStore(), ST->getMemoryVT(), 3603 ST->getSrcValue(), ST->getSrcValueOffset(), 3604 ST->getAlignment(), ST->isVolatile()); 3605 CSEMap.InsertNode(N, IP); 3606 AllNodes.push_back(N); 3607 return SDValue(N, 0); 3608} 3609 3610SDValue SelectionDAG::getVAArg(MVT VT, 3611 SDValue Chain, SDValue Ptr, 3612 SDValue SV) { 3613 SDValue Ops[] = { Chain, Ptr, SV }; 3614 return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); 3615} 3616 3617SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3618 const SDUse *Ops, unsigned NumOps) { 3619 switch (NumOps) { 3620 case 0: return getNode(Opcode, VT); 3621 case 1: return getNode(Opcode, VT, Ops[0]); 3622 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3623 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3624 default: break; 3625 } 3626 3627 // Copy from an SDUse array into an SDValue array for use with 3628 // the regular getNode logic. 3629 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3630 return getNode(Opcode, VT, &NewOps[0], NumOps); 3631} 3632 3633SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3634 const SDValue *Ops, unsigned NumOps) { 3635 switch (NumOps) { 3636 case 0: return getNode(Opcode, VT); 3637 case 1: return getNode(Opcode, VT, Ops[0]); 3638 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3639 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3640 default: break; 3641 } 3642 3643 switch (Opcode) { 3644 default: break; 3645 case ISD::SELECT_CC: { 3646 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3647 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3648 "LHS and RHS of condition must have same type!"); 3649 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3650 "True and False arms of SelectCC must have same type!"); 3651 assert(Ops[2].getValueType() == VT && 3652 "select_cc node must be of same type as true and false value!"); 3653 break; 3654 } 3655 case ISD::BR_CC: { 3656 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3657 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3658 "LHS/RHS of comparison should match types!"); 3659 break; 3660 } 3661 } 3662 3663 // Memoize nodes. 3664 SDNode *N; 3665 SDVTList VTs = getVTList(VT); 3666 if (VT != MVT::Flag) { 3667 FoldingSetNodeID ID; 3668 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3669 void *IP = 0; 3670 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3671 return SDValue(E, 0); 3672 N = NodeAllocator.Allocate<SDNode>(); 3673 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3674 CSEMap.InsertNode(N, IP); 3675 } else { 3676 N = NodeAllocator.Allocate<SDNode>(); 3677 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3678 } 3679 AllNodes.push_back(N); 3680#ifndef NDEBUG 3681 VerifyNode(N); 3682#endif 3683 return SDValue(N, 0); 3684} 3685 3686SDValue SelectionDAG::getNode(unsigned Opcode, 3687 const std::vector<MVT> &ResultTys, 3688 const SDValue *Ops, unsigned NumOps) { 3689 return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(), 3690 Ops, NumOps); 3691} 3692 3693SDValue SelectionDAG::getNode(unsigned Opcode, 3694 const MVT *VTs, unsigned NumVTs, 3695 const SDValue *Ops, unsigned NumOps) { 3696 if (NumVTs == 1) 3697 return getNode(Opcode, VTs[0], Ops, NumOps); 3698 return getNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps); 3699} 3700 3701SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3702 const SDValue *Ops, unsigned NumOps) { 3703 if (VTList.NumVTs == 1) 3704 return getNode(Opcode, VTList.VTs[0], Ops, NumOps); 3705 3706 switch (Opcode) { 3707 // FIXME: figure out how to safely handle things like 3708 // int foo(int x) { return 1 << (x & 255); } 3709 // int bar() { return foo(256); } 3710#if 0 3711 case ISD::SRA_PARTS: 3712 case ISD::SRL_PARTS: 3713 case ISD::SHL_PARTS: 3714 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3715 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3716 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3717 else if (N3.getOpcode() == ISD::AND) 3718 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3719 // If the and is only masking out bits that cannot effect the shift, 3720 // eliminate the and. 3721 unsigned NumBits = VT.getSizeInBits()*2; 3722 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3723 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3724 } 3725 break; 3726#endif 3727 } 3728 3729 // Memoize the node unless it returns a flag. 3730 SDNode *N; 3731 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3732 FoldingSetNodeID ID; 3733 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3734 void *IP = 0; 3735 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3736 return SDValue(E, 0); 3737 if (NumOps == 1) { 3738 N = NodeAllocator.Allocate<UnarySDNode>(); 3739 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3740 } else if (NumOps == 2) { 3741 N = NodeAllocator.Allocate<BinarySDNode>(); 3742 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3743 } else if (NumOps == 3) { 3744 N = NodeAllocator.Allocate<TernarySDNode>(); 3745 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3746 } else { 3747 N = NodeAllocator.Allocate<SDNode>(); 3748 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3749 } 3750 CSEMap.InsertNode(N, IP); 3751 } else { 3752 if (NumOps == 1) { 3753 N = NodeAllocator.Allocate<UnarySDNode>(); 3754 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3755 } else if (NumOps == 2) { 3756 N = NodeAllocator.Allocate<BinarySDNode>(); 3757 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3758 } else if (NumOps == 3) { 3759 N = NodeAllocator.Allocate<TernarySDNode>(); 3760 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3761 } else { 3762 N = NodeAllocator.Allocate<SDNode>(); 3763 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3764 } 3765 } 3766 AllNodes.push_back(N); 3767#ifndef NDEBUG 3768 VerifyNode(N); 3769#endif 3770 return SDValue(N, 0); 3771} 3772 3773SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) { 3774 return getNode(Opcode, VTList, 0, 0); 3775} 3776 3777SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3778 SDValue N1) { 3779 SDValue Ops[] = { N1 }; 3780 return getNode(Opcode, VTList, Ops, 1); 3781} 3782 3783SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3784 SDValue N1, SDValue N2) { 3785 SDValue Ops[] = { N1, N2 }; 3786 return getNode(Opcode, VTList, Ops, 2); 3787} 3788 3789SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3790 SDValue N1, SDValue N2, SDValue N3) { 3791 SDValue Ops[] = { N1, N2, N3 }; 3792 return getNode(Opcode, VTList, Ops, 3); 3793} 3794 3795SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3796 SDValue N1, SDValue N2, SDValue N3, 3797 SDValue N4) { 3798 SDValue Ops[] = { N1, N2, N3, N4 }; 3799 return getNode(Opcode, VTList, Ops, 4); 3800} 3801 3802SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3803 SDValue N1, SDValue N2, SDValue N3, 3804 SDValue N4, SDValue N5) { 3805 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3806 return getNode(Opcode, VTList, Ops, 5); 3807} 3808 3809SDVTList SelectionDAG::getVTList(MVT VT) { 3810 return makeVTList(SDNode::getValueTypeList(VT), 1); 3811} 3812 3813SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3814 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3815 E = VTList.rend(); I != E; ++I) 3816 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3817 return *I; 3818 3819 MVT *Array = Allocator.Allocate<MVT>(2); 3820 Array[0] = VT1; 3821 Array[1] = VT2; 3822 SDVTList Result = makeVTList(Array, 2); 3823 VTList.push_back(Result); 3824 return Result; 3825} 3826 3827SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3828 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3829 E = VTList.rend(); I != E; ++I) 3830 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3831 I->VTs[2] == VT3) 3832 return *I; 3833 3834 MVT *Array = Allocator.Allocate<MVT>(3); 3835 Array[0] = VT1; 3836 Array[1] = VT2; 3837 Array[2] = VT3; 3838 SDVTList Result = makeVTList(Array, 3); 3839 VTList.push_back(Result); 3840 return Result; 3841} 3842 3843SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { 3844 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3845 E = VTList.rend(); I != E; ++I) 3846 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3847 I->VTs[2] == VT3 && I->VTs[3] == VT4) 3848 return *I; 3849 3850 MVT *Array = Allocator.Allocate<MVT>(3); 3851 Array[0] = VT1; 3852 Array[1] = VT2; 3853 Array[2] = VT3; 3854 Array[3] = VT4; 3855 SDVTList Result = makeVTList(Array, 4); 3856 VTList.push_back(Result); 3857 return Result; 3858} 3859 3860SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3861 switch (NumVTs) { 3862 case 0: assert(0 && "Cannot have nodes without results!"); 3863 case 1: return getVTList(VTs[0]); 3864 case 2: return getVTList(VTs[0], VTs[1]); 3865 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3866 default: break; 3867 } 3868 3869 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3870 E = VTList.rend(); I != E; ++I) { 3871 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3872 continue; 3873 3874 bool NoMatch = false; 3875 for (unsigned i = 2; i != NumVTs; ++i) 3876 if (VTs[i] != I->VTs[i]) { 3877 NoMatch = true; 3878 break; 3879 } 3880 if (!NoMatch) 3881 return *I; 3882 } 3883 3884 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 3885 std::copy(VTs, VTs+NumVTs, Array); 3886 SDVTList Result = makeVTList(Array, NumVTs); 3887 VTList.push_back(Result); 3888 return Result; 3889} 3890 3891 3892/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 3893/// specified operands. If the resultant node already exists in the DAG, 3894/// this does not modify the specified node, instead it returns the node that 3895/// already exists. If the resultant node does not exist in the DAG, the 3896/// input node is returned. As a degenerate case, if you specify the same 3897/// input operands as the node already has, the input node is returned. 3898SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 3899 SDNode *N = InN.getNode(); 3900 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 3901 3902 // Check to see if there is no change. 3903 if (Op == N->getOperand(0)) return InN; 3904 3905 // See if the modified node already exists. 3906 void *InsertPos = 0; 3907 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 3908 return SDValue(Existing, InN.getResNo()); 3909 3910 // Nope it doesn't. Remove the node from its current place in the maps. 3911 if (InsertPos) 3912 if (!RemoveNodeFromCSEMaps(N)) 3913 InsertPos = 0; 3914 3915 // Now we update the operands. 3916 N->OperandList[0].getVal()->removeUser(0, N); 3917 N->OperandList[0] = Op; 3918 N->OperandList[0].setUser(N); 3919 Op.getNode()->addUser(0, N); 3920 3921 // If this gets put into a CSE map, add it. 3922 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3923 return InN; 3924} 3925 3926SDValue SelectionDAG:: 3927UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 3928 SDNode *N = InN.getNode(); 3929 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 3930 3931 // Check to see if there is no change. 3932 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 3933 return InN; // No operands changed, just return the input node. 3934 3935 // See if the modified node already exists. 3936 void *InsertPos = 0; 3937 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 3938 return SDValue(Existing, InN.getResNo()); 3939 3940 // Nope it doesn't. Remove the node from its current place in the maps. 3941 if (InsertPos) 3942 if (!RemoveNodeFromCSEMaps(N)) 3943 InsertPos = 0; 3944 3945 // Now we update the operands. 3946 if (N->OperandList[0] != Op1) { 3947 N->OperandList[0].getVal()->removeUser(0, N); 3948 N->OperandList[0] = Op1; 3949 N->OperandList[0].setUser(N); 3950 Op1.getNode()->addUser(0, N); 3951 } 3952 if (N->OperandList[1] != Op2) { 3953 N->OperandList[1].getVal()->removeUser(1, N); 3954 N->OperandList[1] = Op2; 3955 N->OperandList[1].setUser(N); 3956 Op2.getNode()->addUser(1, N); 3957 } 3958 3959 // If this gets put into a CSE map, add it. 3960 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3961 return InN; 3962} 3963 3964SDValue SelectionDAG:: 3965UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 3966 SDValue Ops[] = { Op1, Op2, Op3 }; 3967 return UpdateNodeOperands(N, Ops, 3); 3968} 3969 3970SDValue SelectionDAG:: 3971UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3972 SDValue Op3, SDValue Op4) { 3973 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 3974 return UpdateNodeOperands(N, Ops, 4); 3975} 3976 3977SDValue SelectionDAG:: 3978UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 3979 SDValue Op3, SDValue Op4, SDValue Op5) { 3980 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 3981 return UpdateNodeOperands(N, Ops, 5); 3982} 3983 3984SDValue SelectionDAG:: 3985UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 3986 SDNode *N = InN.getNode(); 3987 assert(N->getNumOperands() == NumOps && 3988 "Update with wrong number of operands"); 3989 3990 // Check to see if there is no change. 3991 bool AnyChange = false; 3992 for (unsigned i = 0; i != NumOps; ++i) { 3993 if (Ops[i] != N->getOperand(i)) { 3994 AnyChange = true; 3995 break; 3996 } 3997 } 3998 3999 // No operands changed, just return the input node. 4000 if (!AnyChange) return InN; 4001 4002 // See if the modified node already exists. 4003 void *InsertPos = 0; 4004 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 4005 return SDValue(Existing, InN.getResNo()); 4006 4007 // Nope it doesn't. Remove the node from its current place in the maps. 4008 if (InsertPos) 4009 if (!RemoveNodeFromCSEMaps(N)) 4010 InsertPos = 0; 4011 4012 // Now we update the operands. 4013 for (unsigned i = 0; i != NumOps; ++i) { 4014 if (N->OperandList[i] != Ops[i]) { 4015 N->OperandList[i].getVal()->removeUser(i, N); 4016 N->OperandList[i] = Ops[i]; 4017 N->OperandList[i].setUser(N); 4018 Ops[i].getNode()->addUser(i, N); 4019 } 4020 } 4021 4022 // If this gets put into a CSE map, add it. 4023 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4024 return InN; 4025} 4026 4027/// DropOperands - Release the operands and set this node to have 4028/// zero operands. 4029void SDNode::DropOperands() { 4030 // Unlike the code in MorphNodeTo that does this, we don't need to 4031 // watch for dead nodes here. 4032 for (op_iterator I = op_begin(), E = op_end(); I != E; ++I) 4033 I->getVal()->removeUser(std::distance(op_begin(), I), this); 4034 4035 NumOperands = 0; 4036} 4037 4038/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4039/// machine opcode. 4040/// 4041SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4042 MVT VT) { 4043 SDVTList VTs = getVTList(VT); 4044 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4045} 4046 4047SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4048 MVT VT, SDValue Op1) { 4049 SDVTList VTs = getVTList(VT); 4050 SDValue Ops[] = { Op1 }; 4051 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4052} 4053 4054SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4055 MVT VT, SDValue Op1, 4056 SDValue Op2) { 4057 SDVTList VTs = getVTList(VT); 4058 SDValue Ops[] = { Op1, Op2 }; 4059 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4060} 4061 4062SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4063 MVT VT, SDValue Op1, 4064 SDValue Op2, SDValue Op3) { 4065 SDVTList VTs = getVTList(VT); 4066 SDValue Ops[] = { Op1, Op2, Op3 }; 4067 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4068} 4069 4070SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4071 MVT VT, const SDValue *Ops, 4072 unsigned NumOps) { 4073 SDVTList VTs = getVTList(VT); 4074 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4075} 4076 4077SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4078 MVT VT1, MVT VT2, const SDValue *Ops, 4079 unsigned NumOps) { 4080 SDVTList VTs = getVTList(VT1, VT2); 4081 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4082} 4083 4084SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4085 MVT VT1, MVT VT2) { 4086 SDVTList VTs = getVTList(VT1, VT2); 4087 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4088} 4089 4090SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4091 MVT VT1, MVT VT2, MVT VT3, 4092 const SDValue *Ops, unsigned NumOps) { 4093 SDVTList VTs = getVTList(VT1, VT2, VT3); 4094 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4095} 4096 4097SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4098 MVT VT1, MVT VT2, MVT VT3, MVT VT4, 4099 const SDValue *Ops, unsigned NumOps) { 4100 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4101 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4102} 4103 4104SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4105 MVT VT1, MVT VT2, 4106 SDValue Op1) { 4107 SDVTList VTs = getVTList(VT1, VT2); 4108 SDValue Ops[] = { Op1 }; 4109 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4110} 4111 4112SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4113 MVT VT1, MVT VT2, 4114 SDValue Op1, SDValue Op2) { 4115 SDVTList VTs = getVTList(VT1, VT2); 4116 SDValue Ops[] = { Op1, Op2 }; 4117 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4118} 4119 4120SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4121 MVT VT1, MVT VT2, 4122 SDValue Op1, SDValue Op2, 4123 SDValue Op3) { 4124 SDVTList VTs = getVTList(VT1, VT2); 4125 SDValue Ops[] = { Op1, Op2, Op3 }; 4126 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4127} 4128 4129SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4130 MVT VT1, MVT VT2, MVT VT3, 4131 SDValue Op1, SDValue Op2, 4132 SDValue Op3) { 4133 SDVTList VTs = getVTList(VT1, VT2, VT3); 4134 SDValue Ops[] = { Op1, Op2, Op3 }; 4135 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4136} 4137 4138SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4139 SDVTList VTs, const SDValue *Ops, 4140 unsigned NumOps) { 4141 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4142} 4143 4144SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4145 MVT VT) { 4146 SDVTList VTs = getVTList(VT); 4147 return MorphNodeTo(N, Opc, VTs, 0, 0); 4148} 4149 4150SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4151 MVT VT, SDValue Op1) { 4152 SDVTList VTs = getVTList(VT); 4153 SDValue Ops[] = { Op1 }; 4154 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4155} 4156 4157SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4158 MVT VT, SDValue Op1, 4159 SDValue Op2) { 4160 SDVTList VTs = getVTList(VT); 4161 SDValue Ops[] = { Op1, Op2 }; 4162 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4163} 4164 4165SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4166 MVT VT, SDValue Op1, 4167 SDValue Op2, SDValue Op3) { 4168 SDVTList VTs = getVTList(VT); 4169 SDValue Ops[] = { Op1, Op2, Op3 }; 4170 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4171} 4172 4173SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4174 MVT VT, const SDValue *Ops, 4175 unsigned NumOps) { 4176 SDVTList VTs = getVTList(VT); 4177 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4178} 4179 4180SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4181 MVT VT1, MVT VT2, const SDValue *Ops, 4182 unsigned NumOps) { 4183 SDVTList VTs = getVTList(VT1, VT2); 4184 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4185} 4186 4187SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4188 MVT VT1, MVT VT2) { 4189 SDVTList VTs = getVTList(VT1, VT2); 4190 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4191} 4192 4193SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4194 MVT VT1, MVT VT2, MVT VT3, 4195 const SDValue *Ops, unsigned NumOps) { 4196 SDVTList VTs = getVTList(VT1, VT2, VT3); 4197 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4198} 4199 4200SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4201 MVT VT1, MVT VT2, 4202 SDValue Op1) { 4203 SDVTList VTs = getVTList(VT1, VT2); 4204 SDValue Ops[] = { Op1 }; 4205 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4206} 4207 4208SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4209 MVT VT1, MVT VT2, 4210 SDValue Op1, SDValue Op2) { 4211 SDVTList VTs = getVTList(VT1, VT2); 4212 SDValue Ops[] = { Op1, Op2 }; 4213 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4214} 4215 4216SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4217 MVT VT1, MVT VT2, 4218 SDValue Op1, SDValue Op2, 4219 SDValue Op3) { 4220 SDVTList VTs = getVTList(VT1, VT2); 4221 SDValue Ops[] = { Op1, Op2, Op3 }; 4222 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4223} 4224 4225/// MorphNodeTo - These *mutate* the specified node to have the specified 4226/// return type, opcode, and operands. 4227/// 4228/// Note that MorphNodeTo returns the resultant node. If there is already a 4229/// node of the specified opcode and operands, it returns that node instead of 4230/// the current one. 4231/// 4232/// Using MorphNodeTo is faster than creating a new node and swapping it in 4233/// with ReplaceAllUsesWith both because it often avoids allocating a new 4234/// node, and because it doesn't require CSE recalculation for any of 4235/// the node's users. 4236/// 4237SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4238 SDVTList VTs, const SDValue *Ops, 4239 unsigned NumOps) { 4240 // If an identical node already exists, use it. 4241 void *IP = 0; 4242 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4243 FoldingSetNodeID ID; 4244 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4245 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4246 return ON; 4247 } 4248 4249 if (!RemoveNodeFromCSEMaps(N)) 4250 IP = 0; 4251 4252 // Start the morphing. 4253 N->NodeType = Opc; 4254 N->ValueList = VTs.VTs; 4255 N->NumValues = VTs.NumVTs; 4256 4257 // Clear the operands list, updating used nodes to remove this from their 4258 // use list. Keep track of any operands that become dead as a result. 4259 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4260 for (SDNode::op_iterator B = N->op_begin(), I = B, E = N->op_end(); 4261 I != E; ++I) { 4262 SDNode *Used = I->getVal(); 4263 Used->removeUser(std::distance(B, I), N); 4264 if (Used->use_empty()) 4265 DeadNodeSet.insert(Used); 4266 } 4267 4268 // If NumOps is larger than the # of operands we currently have, reallocate 4269 // the operand list. 4270 if (NumOps > N->NumOperands) { 4271 if (N->OperandsNeedDelete) 4272 delete[] N->OperandList; 4273 4274 if (N->isMachineOpcode()) { 4275 // We're creating a final node that will live unmorphed for the 4276 // remainder of the current SelectionDAG iteration, so we can allocate 4277 // the operands directly out of a pool with no recycling metadata. 4278 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4279 N->OperandsNeedDelete = false; 4280 } else { 4281 N->OperandList = new SDUse[NumOps]; 4282 N->OperandsNeedDelete = true; 4283 } 4284 } 4285 4286 // Assign the new operands. 4287 N->NumOperands = NumOps; 4288 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4289 N->OperandList[i] = Ops[i]; 4290 N->OperandList[i].setUser(N); 4291 SDNode *ToUse = N->OperandList[i].getVal(); 4292 ToUse->addUser(i, N); 4293 } 4294 4295 // Delete any nodes that are still dead after adding the uses for the 4296 // new operands. 4297 SmallVector<SDNode *, 16> DeadNodes; 4298 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4299 E = DeadNodeSet.end(); I != E; ++I) 4300 if ((*I)->use_empty()) 4301 DeadNodes.push_back(*I); 4302 RemoveDeadNodes(DeadNodes); 4303 4304 if (IP) 4305 CSEMap.InsertNode(N, IP); // Memoize the new node. 4306 return N; 4307} 4308 4309 4310/// getTargetNode - These are used for target selectors to create a new node 4311/// with specified return type(s), target opcode, and operands. 4312/// 4313/// Note that getTargetNode returns the resultant node. If there is already a 4314/// node of the specified opcode and operands, it returns that node instead of 4315/// the current one. 4316SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { 4317 return getNode(~Opcode, VT).getNode(); 4318} 4319SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) { 4320 return getNode(~Opcode, VT, Op1).getNode(); 4321} 4322SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4323 SDValue Op1, SDValue Op2) { 4324 return getNode(~Opcode, VT, Op1, Op2).getNode(); 4325} 4326SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4327 SDValue Op1, SDValue Op2, 4328 SDValue Op3) { 4329 return getNode(~Opcode, VT, Op1, Op2, Op3).getNode(); 4330} 4331SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4332 const SDValue *Ops, unsigned NumOps) { 4333 return getNode(~Opcode, VT, Ops, NumOps).getNode(); 4334} 4335SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { 4336 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4337 SDValue Op; 4338 return getNode(~Opcode, VTs, 2, &Op, 0).getNode(); 4339} 4340SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4341 MVT VT2, SDValue Op1) { 4342 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4343 return getNode(~Opcode, VTs, 2, &Op1, 1).getNode(); 4344} 4345SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4346 MVT VT2, SDValue Op1, 4347 SDValue Op2) { 4348 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4349 SDValue Ops[] = { Op1, Op2 }; 4350 return getNode(~Opcode, VTs, 2, Ops, 2).getNode(); 4351} 4352SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4353 MVT VT2, SDValue Op1, 4354 SDValue Op2, SDValue Op3) { 4355 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4356 SDValue Ops[] = { Op1, Op2, Op3 }; 4357 return getNode(~Opcode, VTs, 2, Ops, 3).getNode(); 4358} 4359SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, 4360 const SDValue *Ops, unsigned NumOps) { 4361 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4362 return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode(); 4363} 4364SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4365 SDValue Op1, SDValue Op2) { 4366 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4367 SDValue Ops[] = { Op1, Op2 }; 4368 return getNode(~Opcode, VTs, 3, Ops, 2).getNode(); 4369} 4370SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4371 SDValue Op1, SDValue Op2, 4372 SDValue Op3) { 4373 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4374 SDValue Ops[] = { Op1, Op2, Op3 }; 4375 return getNode(~Opcode, VTs, 3, Ops, 3).getNode(); 4376} 4377SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4378 const SDValue *Ops, unsigned NumOps) { 4379 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4380 return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode(); 4381} 4382SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4383 MVT VT2, MVT VT3, MVT VT4, 4384 const SDValue *Ops, unsigned NumOps) { 4385 std::vector<MVT> VTList; 4386 VTList.push_back(VT1); 4387 VTList.push_back(VT2); 4388 VTList.push_back(VT3); 4389 VTList.push_back(VT4); 4390 const MVT *VTs = getNodeValueTypes(VTList); 4391 return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode(); 4392} 4393SDNode *SelectionDAG::getTargetNode(unsigned Opcode, 4394 const std::vector<MVT> &ResultTys, 4395 const SDValue *Ops, unsigned NumOps) { 4396 const MVT *VTs = getNodeValueTypes(ResultTys); 4397 return getNode(~Opcode, VTs, ResultTys.size(), 4398 Ops, NumOps).getNode(); 4399} 4400 4401/// getNodeIfExists - Get the specified node if it's already available, or 4402/// else return NULL. 4403SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4404 const SDValue *Ops, unsigned NumOps) { 4405 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4406 FoldingSetNodeID ID; 4407 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4408 void *IP = 0; 4409 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4410 return E; 4411 } 4412 return NULL; 4413} 4414 4415 4416/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4417/// This can cause recursive merging of nodes in the DAG. 4418/// 4419/// This version assumes From has a single result value. 4420/// 4421void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4422 DAGUpdateListener *UpdateListener) { 4423 SDNode *From = FromN.getNode(); 4424 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4425 "Cannot replace with this method!"); 4426 assert(From != To.getNode() && "Cannot replace uses of with self"); 4427 4428 while (!From->use_empty()) { 4429 SDNode::use_iterator UI = From->use_begin(); 4430 SDNode *U = *UI; 4431 4432 // This node is about to morph, remove its old self from the CSE maps. 4433 RemoveNodeFromCSEMaps(U); 4434 int operandNum = 0; 4435 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4436 I != E; ++I, ++operandNum) 4437 if (I->getVal() == From) { 4438 From->removeUser(operandNum, U); 4439 *I = To; 4440 I->setUser(U); 4441 To.getNode()->addUser(operandNum, U); 4442 } 4443 4444 // Now that we have modified U, add it back to the CSE maps. If it already 4445 // exists there, recursively merge the results together. 4446 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4447 ReplaceAllUsesWith(U, Existing, UpdateListener); 4448 // U is now dead. Inform the listener if it exists and delete it. 4449 if (UpdateListener) 4450 UpdateListener->NodeDeleted(U, Existing); 4451 DeleteNodeNotInCSEMaps(U); 4452 } else { 4453 // If the node doesn't already exist, we updated it. Inform a listener if 4454 // it exists. 4455 if (UpdateListener) 4456 UpdateListener->NodeUpdated(U); 4457 } 4458 } 4459} 4460 4461/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4462/// This can cause recursive merging of nodes in the DAG. 4463/// 4464/// This version assumes From/To have matching types and numbers of result 4465/// values. 4466/// 4467void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4468 DAGUpdateListener *UpdateListener) { 4469 assert(From->getVTList().VTs == To->getVTList().VTs && 4470 From->getNumValues() == To->getNumValues() && 4471 "Cannot use this version of ReplaceAllUsesWith!"); 4472 4473 // Handle the trivial case. 4474 if (From == To) 4475 return; 4476 4477 while (!From->use_empty()) { 4478 SDNode::use_iterator UI = From->use_begin(); 4479 SDNode *U = *UI; 4480 4481 // This node is about to morph, remove its old self from the CSE maps. 4482 RemoveNodeFromCSEMaps(U); 4483 int operandNum = 0; 4484 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4485 I != E; ++I, ++operandNum) 4486 if (I->getVal() == From) { 4487 From->removeUser(operandNum, U); 4488 I->getSDValue().setNode(To); 4489 To->addUser(operandNum, U); 4490 } 4491 4492 // Now that we have modified U, add it back to the CSE maps. If it already 4493 // exists there, recursively merge the results together. 4494 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4495 ReplaceAllUsesWith(U, Existing, UpdateListener); 4496 // U is now dead. Inform the listener if it exists and delete it. 4497 if (UpdateListener) 4498 UpdateListener->NodeDeleted(U, Existing); 4499 DeleteNodeNotInCSEMaps(U); 4500 } else { 4501 // If the node doesn't already exist, we updated it. Inform a listener if 4502 // it exists. 4503 if (UpdateListener) 4504 UpdateListener->NodeUpdated(U); 4505 } 4506 } 4507} 4508 4509/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4510/// This can cause recursive merging of nodes in the DAG. 4511/// 4512/// This version can replace From with any result values. To must match the 4513/// number and types of values returned by From. 4514void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4515 const SDValue *To, 4516 DAGUpdateListener *UpdateListener) { 4517 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4518 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4519 4520 while (!From->use_empty()) { 4521 SDNode::use_iterator UI = From->use_begin(); 4522 SDNode *U = *UI; 4523 4524 // This node is about to morph, remove its old self from the CSE maps. 4525 RemoveNodeFromCSEMaps(U); 4526 int operandNum = 0; 4527 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4528 I != E; ++I, ++operandNum) 4529 if (I->getVal() == From) { 4530 const SDValue &ToOp = To[I->getSDValue().getResNo()]; 4531 From->removeUser(operandNum, U); 4532 *I = ToOp; 4533 I->setUser(U); 4534 ToOp.getNode()->addUser(operandNum, U); 4535 } 4536 4537 // Now that we have modified U, add it back to the CSE maps. If it already 4538 // exists there, recursively merge the results together. 4539 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4540 ReplaceAllUsesWith(U, Existing, UpdateListener); 4541 // U is now dead. Inform the listener if it exists and delete it. 4542 if (UpdateListener) 4543 UpdateListener->NodeDeleted(U, Existing); 4544 DeleteNodeNotInCSEMaps(U); 4545 } else { 4546 // If the node doesn't already exist, we updated it. Inform a listener if 4547 // it exists. 4548 if (UpdateListener) 4549 UpdateListener->NodeUpdated(U); 4550 } 4551 } 4552} 4553 4554/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4555/// uses of other values produced by From.getVal() alone. The Deleted vector is 4556/// handled the same way as for ReplaceAllUsesWith. 4557void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4558 DAGUpdateListener *UpdateListener){ 4559 // Handle the really simple, really trivial case efficiently. 4560 if (From == To) return; 4561 4562 // Handle the simple, trivial, case efficiently. 4563 if (From.getNode()->getNumValues() == 1) { 4564 ReplaceAllUsesWith(From, To, UpdateListener); 4565 return; 4566 } 4567 4568 // Get all of the users of From.getNode(). We want these in a nice, 4569 // deterministically ordered and uniqued set, so we use a SmallSetVector. 4570 SmallSetVector<SDNode*, 16> Users(From.getNode()->use_begin(), From.getNode()->use_end()); 4571 4572 while (!Users.empty()) { 4573 // We know that this user uses some value of From. If it is the right 4574 // value, update it. 4575 SDNode *User = Users.back(); 4576 Users.pop_back(); 4577 4578 // Scan for an operand that matches From. 4579 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4580 for (; Op != E; ++Op) 4581 if (*Op == From) break; 4582 4583 // If there are no matches, the user must use some other result of From. 4584 if (Op == E) continue; 4585 4586 // Okay, we know this user needs to be updated. Remove its old self 4587 // from the CSE maps. 4588 RemoveNodeFromCSEMaps(User); 4589 4590 // Update all operands that match "From" in case there are multiple uses. 4591 for (; Op != E; ++Op) { 4592 if (*Op == From) { 4593 From.getNode()->removeUser(Op-User->op_begin(), User); 4594 *Op = To; 4595 Op->setUser(User); 4596 To.getNode()->addUser(Op-User->op_begin(), User); 4597 } 4598 } 4599 4600 // Now that we have modified User, add it back to the CSE maps. If it 4601 // already exists there, recursively merge the results together. 4602 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4603 if (!Existing) { 4604 if (UpdateListener) UpdateListener->NodeUpdated(User); 4605 continue; // Continue on to next user. 4606 } 4607 4608 // If there was already an existing matching node, use ReplaceAllUsesWith 4609 // to replace the dead one with the existing one. This can cause 4610 // recursive merging of other unrelated nodes down the line. 4611 ReplaceAllUsesWith(User, Existing, UpdateListener); 4612 4613 // User is now dead. Notify a listener if present. 4614 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4615 DeleteNodeNotInCSEMaps(User); 4616 } 4617} 4618 4619/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4620/// uses of other values produced by From.getVal() alone. The same value may 4621/// appear in both the From and To list. The Deleted vector is 4622/// handled the same way as for ReplaceAllUsesWith. 4623void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4624 const SDValue *To, 4625 unsigned Num, 4626 DAGUpdateListener *UpdateListener){ 4627 // Handle the simple, trivial case efficiently. 4628 if (Num == 1) 4629 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4630 4631 SmallVector<std::pair<SDNode *, unsigned>, 16> Users; 4632 for (unsigned i = 0; i != Num; ++i) 4633 for (SDNode::use_iterator UI = From[i].getNode()->use_begin(), 4634 E = From[i].getNode()->use_end(); UI != E; ++UI) 4635 Users.push_back(std::make_pair(*UI, i)); 4636 4637 while (!Users.empty()) { 4638 // We know that this user uses some value of From. If it is the right 4639 // value, update it. 4640 SDNode *User = Users.back().first; 4641 unsigned i = Users.back().second; 4642 Users.pop_back(); 4643 4644 // Scan for an operand that matches From. 4645 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4646 for (; Op != E; ++Op) 4647 if (*Op == From[i]) break; 4648 4649 // If there are no matches, the user must use some other result of From. 4650 if (Op == E) continue; 4651 4652 // Okay, we know this user needs to be updated. Remove its old self 4653 // from the CSE maps. 4654 RemoveNodeFromCSEMaps(User); 4655 4656 // Update all operands that match "From" in case there are multiple uses. 4657 for (; Op != E; ++Op) { 4658 if (*Op == From[i]) { 4659 From[i].getNode()->removeUser(Op-User->op_begin(), User); 4660 *Op = To[i]; 4661 Op->setUser(User); 4662 To[i].getNode()->addUser(Op-User->op_begin(), User); 4663 } 4664 } 4665 4666 // Now that we have modified User, add it back to the CSE maps. If it 4667 // already exists there, recursively merge the results together. 4668 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4669 if (!Existing) { 4670 if (UpdateListener) UpdateListener->NodeUpdated(User); 4671 continue; // Continue on to next user. 4672 } 4673 4674 // If there was already an existing matching node, use ReplaceAllUsesWith 4675 // to replace the dead one with the existing one. This can cause 4676 // recursive merging of other unrelated nodes down the line. 4677 ReplaceAllUsesWith(User, Existing, UpdateListener); 4678 4679 // User is now dead. Notify a listener if present. 4680 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4681 DeleteNodeNotInCSEMaps(User); 4682 } 4683} 4684 4685/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4686/// based on their topological order. It returns the maximum id and a vector 4687/// of the SDNodes* in assigned order by reference. 4688unsigned SelectionDAG::AssignTopologicalOrder() { 4689 4690 unsigned DAGSize = 0; 4691 4692 // SortedPos tracks the progress of the algorithm. Nodes before it are 4693 // sorted, nodes after it are unsorted. When the algorithm completes 4694 // it is at the end of the list. 4695 allnodes_iterator SortedPos = allnodes_begin(); 4696 4697 // Visit all the nodes. Move nodes with no operands to the front of 4698 // the list immediately. Annotate nodes that do have operands with their 4699 // operand count. Before we do this, the Node Id fields of the nodes 4700 // may contain arbitrary values. After, the Node Id fields for nodes 4701 // before SortedPos will contain the topological sort index, and the 4702 // Node Id fields for nodes At SortedPos and after will contain the 4703 // count of outstanding operands. 4704 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4705 SDNode *N = I++; 4706 unsigned Degree = N->getNumOperands(); 4707 if (Degree == 0) { 4708 // A node with no uses, add it to the result array immediately. 4709 N->setNodeId(DAGSize++); 4710 allnodes_iterator Q = N; 4711 if (Q != SortedPos) 4712 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4713 ++SortedPos; 4714 } else { 4715 // Temporarily use the Node Id as scratch space for the degree count. 4716 N->setNodeId(Degree); 4717 } 4718 } 4719 4720 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4721 // such that by the time the end is reached all nodes will be sorted. 4722 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4723 SDNode *N = I; 4724 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4725 UI != UE; ++UI) { 4726 SDNode *P = *UI; 4727 unsigned Degree = P->getNodeId(); 4728 --Degree; 4729 if (Degree == 0) { 4730 // All of P's operands are sorted, so P may sorted now. 4731 P->setNodeId(DAGSize++); 4732 if (P != SortedPos) 4733 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4734 ++SortedPos; 4735 } else { 4736 // Update P's outstanding operand count. 4737 P->setNodeId(Degree); 4738 } 4739 } 4740 } 4741 4742 assert(SortedPos == AllNodes.end() && 4743 "Topological sort incomplete!"); 4744 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4745 "First node in topological sort is not the entry token!"); 4746 assert(AllNodes.front().getNodeId() == 0 && 4747 "First node in topological sort has non-zero id!"); 4748 assert(AllNodes.front().getNumOperands() == 0 && 4749 "First node in topological sort has operands!"); 4750 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4751 "Last node in topologic sort has unexpected id!"); 4752 assert(AllNodes.back().use_empty() && 4753 "Last node in topologic sort has users!"); 4754 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 4755 return DAGSize; 4756} 4757 4758 4759 4760//===----------------------------------------------------------------------===// 4761// SDNode Class 4762//===----------------------------------------------------------------------===// 4763 4764// Out-of-line virtual method to give class a home. 4765void SDNode::ANCHOR() {} 4766void UnarySDNode::ANCHOR() {} 4767void BinarySDNode::ANCHOR() {} 4768void TernarySDNode::ANCHOR() {} 4769void HandleSDNode::ANCHOR() {} 4770void ConstantSDNode::ANCHOR() {} 4771void ConstantFPSDNode::ANCHOR() {} 4772void GlobalAddressSDNode::ANCHOR() {} 4773void FrameIndexSDNode::ANCHOR() {} 4774void JumpTableSDNode::ANCHOR() {} 4775void ConstantPoolSDNode::ANCHOR() {} 4776void BasicBlockSDNode::ANCHOR() {} 4777void SrcValueSDNode::ANCHOR() {} 4778void MemOperandSDNode::ANCHOR() {} 4779void RegisterSDNode::ANCHOR() {} 4780void DbgStopPointSDNode::ANCHOR() {} 4781void LabelSDNode::ANCHOR() {} 4782void ExternalSymbolSDNode::ANCHOR() {} 4783void CondCodeSDNode::ANCHOR() {} 4784void ARG_FLAGSSDNode::ANCHOR() {} 4785void VTSDNode::ANCHOR() {} 4786void MemSDNode::ANCHOR() {} 4787void LoadSDNode::ANCHOR() {} 4788void StoreSDNode::ANCHOR() {} 4789void AtomicSDNode::ANCHOR() {} 4790void MemIntrinsicSDNode::ANCHOR() {} 4791void CallSDNode::ANCHOR() {} 4792void CvtRndSatSDNode::ANCHOR() {} 4793 4794HandleSDNode::~HandleSDNode() { 4795 DropOperands(); 4796} 4797 4798GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4799 MVT VT, int64_t o) 4800 : SDNode(isa<GlobalVariable>(GA) && 4801 cast<GlobalVariable>(GA)->isThreadLocal() ? 4802 // Thread Local 4803 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4804 // Non Thread Local 4805 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4806 getSDVTList(VT)), Offset(o) { 4807 TheGlobal = const_cast<GlobalValue*>(GA); 4808} 4809 4810MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt, 4811 const Value *srcValue, int SVO, 4812 unsigned alignment, bool vol) 4813 : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4814 Flags(encodeMemSDNodeFlags(vol, alignment)) { 4815 4816 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4817 assert(getAlignment() == alignment && "Alignment representation error!"); 4818 assert(isVolatile() == vol && "Volatile representation error!"); 4819} 4820 4821MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, 4822 unsigned NumOps, MVT memvt, const Value *srcValue, 4823 int SVO, unsigned alignment, bool vol) 4824 : SDNode(Opc, VTs, Ops, NumOps), 4825 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4826 Flags(vol | ((Log2_32(alignment) + 1) << 1)) { 4827 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4828 assert(getAlignment() == alignment && "Alignment representation error!"); 4829 assert(isVolatile() == vol && "Volatile representation error!"); 4830} 4831 4832/// getMemOperand - Return a MachineMemOperand object describing the memory 4833/// reference performed by this memory reference. 4834MachineMemOperand MemSDNode::getMemOperand() const { 4835 int Flags = 0; 4836 if (isa<LoadSDNode>(this)) 4837 Flags = MachineMemOperand::MOLoad; 4838 else if (isa<StoreSDNode>(this)) 4839 Flags = MachineMemOperand::MOStore; 4840 else if (isa<AtomicSDNode>(this)) { 4841 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4842 } 4843 else { 4844 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4845 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4846 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4847 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4848 } 4849 4850 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4851 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4852 4853 // Check if the memory reference references a frame index 4854 const FrameIndexSDNode *FI = 4855 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4856 if (!getSrcValue() && FI) 4857 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4858 Flags, 0, Size, getAlignment()); 4859 else 4860 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4861 Size, getAlignment()); 4862} 4863 4864/// Profile - Gather unique data for the node. 4865/// 4866void SDNode::Profile(FoldingSetNodeID &ID) const { 4867 AddNodeIDNode(ID, this); 4868} 4869 4870/// getValueTypeList - Return a pointer to the specified value type. 4871/// 4872const MVT *SDNode::getValueTypeList(MVT VT) { 4873 if (VT.isExtended()) { 4874 static std::set<MVT, MVT::compareRawBits> EVTs; 4875 return &(*EVTs.insert(VT).first); 4876 } else { 4877 static MVT VTs[MVT::LAST_VALUETYPE]; 4878 VTs[VT.getSimpleVT()] = VT; 4879 return &VTs[VT.getSimpleVT()]; 4880 } 4881} 4882 4883/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4884/// indicated value. This method ignores uses of other values defined by this 4885/// operation. 4886bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4887 assert(Value < getNumValues() && "Bad value!"); 4888 4889 // TODO: Only iterate over uses of a given value of the node 4890 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4891 if (UI.getUse().getSDValue().getResNo() == Value) { 4892 if (NUses == 0) 4893 return false; 4894 --NUses; 4895 } 4896 } 4897 4898 // Found exactly the right number of uses? 4899 return NUses == 0; 4900} 4901 4902 4903/// hasAnyUseOfValue - Return true if there are any use of the indicated 4904/// value. This method ignores uses of other values defined by this operation. 4905bool SDNode::hasAnyUseOfValue(unsigned Value) const { 4906 assert(Value < getNumValues() && "Bad value!"); 4907 4908 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 4909 if (UI.getUse().getSDValue().getResNo() == Value) 4910 return true; 4911 4912 return false; 4913} 4914 4915 4916/// isOnlyUserOf - Return true if this node is the only use of N. 4917/// 4918bool SDNode::isOnlyUserOf(SDNode *N) const { 4919 bool Seen = false; 4920 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 4921 SDNode *User = *I; 4922 if (User == this) 4923 Seen = true; 4924 else 4925 return false; 4926 } 4927 4928 return Seen; 4929} 4930 4931/// isOperand - Return true if this node is an operand of N. 4932/// 4933bool SDValue::isOperandOf(SDNode *N) const { 4934 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4935 if (*this == N->getOperand(i)) 4936 return true; 4937 return false; 4938} 4939 4940bool SDNode::isOperandOf(SDNode *N) const { 4941 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 4942 if (this == N->OperandList[i].getVal()) 4943 return true; 4944 return false; 4945} 4946 4947/// reachesChainWithoutSideEffects - Return true if this operand (which must 4948/// be a chain) reaches the specified operand without crossing any 4949/// side-effecting instructions. In practice, this looks through token 4950/// factors and non-volatile loads. In order to remain efficient, this only 4951/// looks a couple of nodes in, it does not do an exhaustive search. 4952bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 4953 unsigned Depth) const { 4954 if (*this == Dest) return true; 4955 4956 // Don't search too deeply, we just want to be able to see through 4957 // TokenFactor's etc. 4958 if (Depth == 0) return false; 4959 4960 // If this is a token factor, all inputs to the TF happen in parallel. If any 4961 // of the operands of the TF reach dest, then we can do the xform. 4962 if (getOpcode() == ISD::TokenFactor) { 4963 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 4964 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 4965 return true; 4966 return false; 4967 } 4968 4969 // Loads don't have side effects, look through them. 4970 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 4971 if (!Ld->isVolatile()) 4972 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 4973 } 4974 return false; 4975} 4976 4977 4978static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 4979 SmallPtrSet<SDNode *, 32> &Visited) { 4980 if (found || !Visited.insert(N)) 4981 return; 4982 4983 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 4984 SDNode *Op = N->getOperand(i).getNode(); 4985 if (Op == P) { 4986 found = true; 4987 return; 4988 } 4989 findPredecessor(Op, P, found, Visited); 4990 } 4991} 4992 4993/// isPredecessorOf - Return true if this node is a predecessor of N. This node 4994/// is either an operand of N or it can be reached by recursively traversing 4995/// up the operands. 4996/// NOTE: this is an expensive method. Use it carefully. 4997bool SDNode::isPredecessorOf(SDNode *N) const { 4998 SmallPtrSet<SDNode *, 32> Visited; 4999 bool found = false; 5000 findPredecessor(N, this, found, Visited); 5001 return found; 5002} 5003 5004uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 5005 assert(Num < NumOperands && "Invalid child # of SDNode!"); 5006 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 5007} 5008 5009std::string SDNode::getOperationName(const SelectionDAG *G) const { 5010 switch (getOpcode()) { 5011 default: 5012 if (getOpcode() < ISD::BUILTIN_OP_END) 5013 return "<<Unknown DAG Node>>"; 5014 if (isMachineOpcode()) { 5015 if (G) 5016 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 5017 if (getMachineOpcode() < TII->getNumOpcodes()) 5018 return TII->get(getMachineOpcode()).getName(); 5019 return "<<Unknown Machine Node>>"; 5020 } 5021 if (G) { 5022 TargetLowering &TLI = G->getTargetLoweringInfo(); 5023 const char *Name = TLI.getTargetNodeName(getOpcode()); 5024 if (Name) return Name; 5025 return "<<Unknown Target Node>>"; 5026 } 5027 return "<<Unknown Node>>"; 5028 5029#ifndef NDEBUG 5030 case ISD::DELETED_NODE: 5031 return "<<Deleted Node!>>"; 5032#endif 5033 case ISD::PREFETCH: return "Prefetch"; 5034 case ISD::MEMBARRIER: return "MemBarrier"; 5035 case ISD::ATOMIC_CMP_SWAP_8: return "AtomicCmpSwap8"; 5036 case ISD::ATOMIC_SWAP_8: return "AtomicSwap8"; 5037 case ISD::ATOMIC_LOAD_ADD_8: return "AtomicLoadAdd8"; 5038 case ISD::ATOMIC_LOAD_SUB_8: return "AtomicLoadSub8"; 5039 case ISD::ATOMIC_LOAD_AND_8: return "AtomicLoadAnd8"; 5040 case ISD::ATOMIC_LOAD_OR_8: return "AtomicLoadOr8"; 5041 case ISD::ATOMIC_LOAD_XOR_8: return "AtomicLoadXor8"; 5042 case ISD::ATOMIC_LOAD_NAND_8: return "AtomicLoadNand8"; 5043 case ISD::ATOMIC_LOAD_MIN_8: return "AtomicLoadMin8"; 5044 case ISD::ATOMIC_LOAD_MAX_8: return "AtomicLoadMax8"; 5045 case ISD::ATOMIC_LOAD_UMIN_8: return "AtomicLoadUMin8"; 5046 case ISD::ATOMIC_LOAD_UMAX_8: return "AtomicLoadUMax8"; 5047 case ISD::ATOMIC_CMP_SWAP_16: return "AtomicCmpSwap16"; 5048 case ISD::ATOMIC_SWAP_16: return "AtomicSwap16"; 5049 case ISD::ATOMIC_LOAD_ADD_16: return "AtomicLoadAdd16"; 5050 case ISD::ATOMIC_LOAD_SUB_16: return "AtomicLoadSub16"; 5051 case ISD::ATOMIC_LOAD_AND_16: return "AtomicLoadAnd16"; 5052 case ISD::ATOMIC_LOAD_OR_16: return "AtomicLoadOr16"; 5053 case ISD::ATOMIC_LOAD_XOR_16: return "AtomicLoadXor16"; 5054 case ISD::ATOMIC_LOAD_NAND_16: return "AtomicLoadNand16"; 5055 case ISD::ATOMIC_LOAD_MIN_16: return "AtomicLoadMin16"; 5056 case ISD::ATOMIC_LOAD_MAX_16: return "AtomicLoadMax16"; 5057 case ISD::ATOMIC_LOAD_UMIN_16: return "AtomicLoadUMin16"; 5058 case ISD::ATOMIC_LOAD_UMAX_16: return "AtomicLoadUMax16"; 5059 case ISD::ATOMIC_CMP_SWAP_32: return "AtomicCmpSwap32"; 5060 case ISD::ATOMIC_SWAP_32: return "AtomicSwap32"; 5061 case ISD::ATOMIC_LOAD_ADD_32: return "AtomicLoadAdd32"; 5062 case ISD::ATOMIC_LOAD_SUB_32: return "AtomicLoadSub32"; 5063 case ISD::ATOMIC_LOAD_AND_32: return "AtomicLoadAnd32"; 5064 case ISD::ATOMIC_LOAD_OR_32: return "AtomicLoadOr32"; 5065 case ISD::ATOMIC_LOAD_XOR_32: return "AtomicLoadXor32"; 5066 case ISD::ATOMIC_LOAD_NAND_32: return "AtomicLoadNand32"; 5067 case ISD::ATOMIC_LOAD_MIN_32: return "AtomicLoadMin32"; 5068 case ISD::ATOMIC_LOAD_MAX_32: return "AtomicLoadMax32"; 5069 case ISD::ATOMIC_LOAD_UMIN_32: return "AtomicLoadUMin32"; 5070 case ISD::ATOMIC_LOAD_UMAX_32: return "AtomicLoadUMax32"; 5071 case ISD::ATOMIC_CMP_SWAP_64: return "AtomicCmpSwap64"; 5072 case ISD::ATOMIC_SWAP_64: return "AtomicSwap64"; 5073 case ISD::ATOMIC_LOAD_ADD_64: return "AtomicLoadAdd64"; 5074 case ISD::ATOMIC_LOAD_SUB_64: return "AtomicLoadSub64"; 5075 case ISD::ATOMIC_LOAD_AND_64: return "AtomicLoadAnd64"; 5076 case ISD::ATOMIC_LOAD_OR_64: return "AtomicLoadOr64"; 5077 case ISD::ATOMIC_LOAD_XOR_64: return "AtomicLoadXor64"; 5078 case ISD::ATOMIC_LOAD_NAND_64: return "AtomicLoadNand64"; 5079 case ISD::ATOMIC_LOAD_MIN_64: return "AtomicLoadMin64"; 5080 case ISD::ATOMIC_LOAD_MAX_64: return "AtomicLoadMax64"; 5081 case ISD::ATOMIC_LOAD_UMIN_64: return "AtomicLoadUMin64"; 5082 case ISD::ATOMIC_LOAD_UMAX_64: return "AtomicLoadUMax64"; 5083 case ISD::PCMARKER: return "PCMarker"; 5084 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5085 case ISD::SRCVALUE: return "SrcValue"; 5086 case ISD::MEMOPERAND: return "MemOperand"; 5087 case ISD::EntryToken: return "EntryToken"; 5088 case ISD::TokenFactor: return "TokenFactor"; 5089 case ISD::AssertSext: return "AssertSext"; 5090 case ISD::AssertZext: return "AssertZext"; 5091 5092 case ISD::BasicBlock: return "BasicBlock"; 5093 case ISD::ARG_FLAGS: return "ArgFlags"; 5094 case ISD::VALUETYPE: return "ValueType"; 5095 case ISD::Register: return "Register"; 5096 5097 case ISD::Constant: return "Constant"; 5098 case ISD::ConstantFP: return "ConstantFP"; 5099 case ISD::GlobalAddress: return "GlobalAddress"; 5100 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5101 case ISD::FrameIndex: return "FrameIndex"; 5102 case ISD::JumpTable: return "JumpTable"; 5103 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5104 case ISD::RETURNADDR: return "RETURNADDR"; 5105 case ISD::FRAMEADDR: return "FRAMEADDR"; 5106 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5107 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5108 case ISD::EHSELECTION: return "EHSELECTION"; 5109 case ISD::EH_RETURN: return "EH_RETURN"; 5110 case ISD::ConstantPool: return "ConstantPool"; 5111 case ISD::ExternalSymbol: return "ExternalSymbol"; 5112 case ISD::INTRINSIC_WO_CHAIN: { 5113 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5114 return Intrinsic::getName((Intrinsic::ID)IID); 5115 } 5116 case ISD::INTRINSIC_VOID: 5117 case ISD::INTRINSIC_W_CHAIN: { 5118 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5119 return Intrinsic::getName((Intrinsic::ID)IID); 5120 } 5121 5122 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5123 case ISD::TargetConstant: return "TargetConstant"; 5124 case ISD::TargetConstantFP:return "TargetConstantFP"; 5125 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5126 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5127 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5128 case ISD::TargetJumpTable: return "TargetJumpTable"; 5129 case ISD::TargetConstantPool: return "TargetConstantPool"; 5130 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5131 5132 case ISD::CopyToReg: return "CopyToReg"; 5133 case ISD::CopyFromReg: return "CopyFromReg"; 5134 case ISD::UNDEF: return "undef"; 5135 case ISD::MERGE_VALUES: return "merge_values"; 5136 case ISD::INLINEASM: return "inlineasm"; 5137 case ISD::DBG_LABEL: return "dbg_label"; 5138 case ISD::EH_LABEL: return "eh_label"; 5139 case ISD::DECLARE: return "declare"; 5140 case ISD::HANDLENODE: return "handlenode"; 5141 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5142 case ISD::CALL: return "call"; 5143 5144 // Unary operators 5145 case ISD::FABS: return "fabs"; 5146 case ISD::FNEG: return "fneg"; 5147 case ISD::FSQRT: return "fsqrt"; 5148 case ISD::FSIN: return "fsin"; 5149 case ISD::FCOS: return "fcos"; 5150 case ISD::FPOWI: return "fpowi"; 5151 case ISD::FPOW: return "fpow"; 5152 case ISD::FTRUNC: return "ftrunc"; 5153 case ISD::FFLOOR: return "ffloor"; 5154 case ISD::FCEIL: return "fceil"; 5155 case ISD::FRINT: return "frint"; 5156 case ISD::FNEARBYINT: return "fnearbyint"; 5157 5158 // Binary operators 5159 case ISD::ADD: return "add"; 5160 case ISD::SUB: return "sub"; 5161 case ISD::MUL: return "mul"; 5162 case ISD::MULHU: return "mulhu"; 5163 case ISD::MULHS: return "mulhs"; 5164 case ISD::SDIV: return "sdiv"; 5165 case ISD::UDIV: return "udiv"; 5166 case ISD::SREM: return "srem"; 5167 case ISD::UREM: return "urem"; 5168 case ISD::SMUL_LOHI: return "smul_lohi"; 5169 case ISD::UMUL_LOHI: return "umul_lohi"; 5170 case ISD::SDIVREM: return "sdivrem"; 5171 case ISD::UDIVREM: return "udivrem"; 5172 case ISD::AND: return "and"; 5173 case ISD::OR: return "or"; 5174 case ISD::XOR: return "xor"; 5175 case ISD::SHL: return "shl"; 5176 case ISD::SRA: return "sra"; 5177 case ISD::SRL: return "srl"; 5178 case ISD::ROTL: return "rotl"; 5179 case ISD::ROTR: return "rotr"; 5180 case ISD::FADD: return "fadd"; 5181 case ISD::FSUB: return "fsub"; 5182 case ISD::FMUL: return "fmul"; 5183 case ISD::FDIV: return "fdiv"; 5184 case ISD::FREM: return "frem"; 5185 case ISD::FCOPYSIGN: return "fcopysign"; 5186 case ISD::FGETSIGN: return "fgetsign"; 5187 5188 case ISD::SETCC: return "setcc"; 5189 case ISD::VSETCC: return "vsetcc"; 5190 case ISD::SELECT: return "select"; 5191 case ISD::SELECT_CC: return "select_cc"; 5192 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5193 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5194 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5195 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5196 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5197 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5198 case ISD::CARRY_FALSE: return "carry_false"; 5199 case ISD::ADDC: return "addc"; 5200 case ISD::ADDE: return "adde"; 5201 case ISD::SADDO: return "saddo"; 5202 case ISD::UADDO: return "uaddo"; 5203 case ISD::SUBC: return "subc"; 5204 case ISD::SUBE: return "sube"; 5205 case ISD::SHL_PARTS: return "shl_parts"; 5206 case ISD::SRA_PARTS: return "sra_parts"; 5207 case ISD::SRL_PARTS: return "srl_parts"; 5208 5209 case ISD::EXTRACT_SUBREG: return "extract_subreg"; 5210 case ISD::INSERT_SUBREG: return "insert_subreg"; 5211 5212 // Conversion operators. 5213 case ISD::SIGN_EXTEND: return "sign_extend"; 5214 case ISD::ZERO_EXTEND: return "zero_extend"; 5215 case ISD::ANY_EXTEND: return "any_extend"; 5216 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5217 case ISD::TRUNCATE: return "truncate"; 5218 case ISD::FP_ROUND: return "fp_round"; 5219 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5220 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5221 case ISD::FP_EXTEND: return "fp_extend"; 5222 5223 case ISD::SINT_TO_FP: return "sint_to_fp"; 5224 case ISD::UINT_TO_FP: return "uint_to_fp"; 5225 case ISD::FP_TO_SINT: return "fp_to_sint"; 5226 case ISD::FP_TO_UINT: return "fp_to_uint"; 5227 case ISD::BIT_CONVERT: return "bit_convert"; 5228 5229 case ISD::CONVERT_RNDSAT: { 5230 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5231 default: assert(0 && "Unknown cvt code!"); 5232 case ISD::CVT_FF: return "cvt_ff"; 5233 case ISD::CVT_FS: return "cvt_fs"; 5234 case ISD::CVT_FU: return "cvt_fu"; 5235 case ISD::CVT_SF: return "cvt_sf"; 5236 case ISD::CVT_UF: return "cvt_uf"; 5237 case ISD::CVT_SS: return "cvt_ss"; 5238 case ISD::CVT_SU: return "cvt_su"; 5239 case ISD::CVT_US: return "cvt_us"; 5240 case ISD::CVT_UU: return "cvt_uu"; 5241 } 5242 } 5243 5244 // Control flow instructions 5245 case ISD::BR: return "br"; 5246 case ISD::BRIND: return "brind"; 5247 case ISD::BR_JT: return "br_jt"; 5248 case ISD::BRCOND: return "brcond"; 5249 case ISD::BR_CC: return "br_cc"; 5250 case ISD::RET: return "ret"; 5251 case ISD::CALLSEQ_START: return "callseq_start"; 5252 case ISD::CALLSEQ_END: return "callseq_end"; 5253 5254 // Other operators 5255 case ISD::LOAD: return "load"; 5256 case ISD::STORE: return "store"; 5257 case ISD::VAARG: return "vaarg"; 5258 case ISD::VACOPY: return "vacopy"; 5259 case ISD::VAEND: return "vaend"; 5260 case ISD::VASTART: return "vastart"; 5261 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5262 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5263 case ISD::BUILD_PAIR: return "build_pair"; 5264 case ISD::STACKSAVE: return "stacksave"; 5265 case ISD::STACKRESTORE: return "stackrestore"; 5266 case ISD::TRAP: return "trap"; 5267 5268 // Bit manipulation 5269 case ISD::BSWAP: return "bswap"; 5270 case ISD::CTPOP: return "ctpop"; 5271 case ISD::CTTZ: return "cttz"; 5272 case ISD::CTLZ: return "ctlz"; 5273 5274 // Debug info 5275 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5276 case ISD::DEBUG_LOC: return "debug_loc"; 5277 5278 // Trampolines 5279 case ISD::TRAMPOLINE: return "trampoline"; 5280 5281 case ISD::CONDCODE: 5282 switch (cast<CondCodeSDNode>(this)->get()) { 5283 default: assert(0 && "Unknown setcc condition!"); 5284 case ISD::SETOEQ: return "setoeq"; 5285 case ISD::SETOGT: return "setogt"; 5286 case ISD::SETOGE: return "setoge"; 5287 case ISD::SETOLT: return "setolt"; 5288 case ISD::SETOLE: return "setole"; 5289 case ISD::SETONE: return "setone"; 5290 5291 case ISD::SETO: return "seto"; 5292 case ISD::SETUO: return "setuo"; 5293 case ISD::SETUEQ: return "setue"; 5294 case ISD::SETUGT: return "setugt"; 5295 case ISD::SETUGE: return "setuge"; 5296 case ISD::SETULT: return "setult"; 5297 case ISD::SETULE: return "setule"; 5298 case ISD::SETUNE: return "setune"; 5299 5300 case ISD::SETEQ: return "seteq"; 5301 case ISD::SETGT: return "setgt"; 5302 case ISD::SETGE: return "setge"; 5303 case ISD::SETLT: return "setlt"; 5304 case ISD::SETLE: return "setle"; 5305 case ISD::SETNE: return "setne"; 5306 } 5307 } 5308} 5309 5310const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5311 switch (AM) { 5312 default: 5313 return ""; 5314 case ISD::PRE_INC: 5315 return "<pre-inc>"; 5316 case ISD::PRE_DEC: 5317 return "<pre-dec>"; 5318 case ISD::POST_INC: 5319 return "<post-inc>"; 5320 case ISD::POST_DEC: 5321 return "<post-dec>"; 5322 } 5323} 5324 5325std::string ISD::ArgFlagsTy::getArgFlagsString() { 5326 std::string S = "< "; 5327 5328 if (isZExt()) 5329 S += "zext "; 5330 if (isSExt()) 5331 S += "sext "; 5332 if (isInReg()) 5333 S += "inreg "; 5334 if (isSRet()) 5335 S += "sret "; 5336 if (isByVal()) 5337 S += "byval "; 5338 if (isNest()) 5339 S += "nest "; 5340 if (getByValAlign()) 5341 S += "byval-align:" + utostr(getByValAlign()) + " "; 5342 if (getOrigAlign()) 5343 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5344 if (getByValSize()) 5345 S += "byval-size:" + utostr(getByValSize()) + " "; 5346 return S + ">"; 5347} 5348 5349void SDNode::dump() const { dump(0); } 5350void SDNode::dump(const SelectionDAG *G) const { 5351 print(errs(), G); 5352 errs().flush(); 5353} 5354 5355void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5356 OS << (void*)this << ": "; 5357 5358 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5359 if (i) OS << ","; 5360 if (getValueType(i) == MVT::Other) 5361 OS << "ch"; 5362 else 5363 OS << getValueType(i).getMVTString(); 5364 } 5365 OS << " = " << getOperationName(G); 5366 5367 OS << " "; 5368 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5369 if (i) OS << ", "; 5370 OS << (void*)getOperand(i).getNode(); 5371 if (unsigned RN = getOperand(i).getResNo()) 5372 OS << ":" << RN; 5373 } 5374 5375 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5376 SDNode *Mask = getOperand(2).getNode(); 5377 OS << "<"; 5378 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 5379 if (i) OS << ","; 5380 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 5381 OS << "u"; 5382 else 5383 OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue(); 5384 } 5385 OS << ">"; 5386 } 5387 5388 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5389 OS << '<' << CSDN->getAPIntValue() << '>'; 5390 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5391 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5392 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5393 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5394 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5395 else { 5396 OS << "<APFloat("; 5397 CSDN->getValueAPF().bitcastToAPInt().dump(); 5398 OS << ")>"; 5399 } 5400 } else if (const GlobalAddressSDNode *GADN = 5401 dyn_cast<GlobalAddressSDNode>(this)) { 5402 int64_t offset = GADN->getOffset(); 5403 OS << '<'; 5404 WriteAsOperand(OS, GADN->getGlobal()); 5405 OS << '>'; 5406 if (offset > 0) 5407 OS << " + " << offset; 5408 else 5409 OS << " " << offset; 5410 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5411 OS << "<" << FIDN->getIndex() << ">"; 5412 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5413 OS << "<" << JTDN->getIndex() << ">"; 5414 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5415 int offset = CP->getOffset(); 5416 if (CP->isMachineConstantPoolEntry()) 5417 OS << "<" << *CP->getMachineCPVal() << ">"; 5418 else 5419 OS << "<" << *CP->getConstVal() << ">"; 5420 if (offset > 0) 5421 OS << " + " << offset; 5422 else 5423 OS << " " << offset; 5424 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5425 OS << "<"; 5426 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5427 if (LBB) 5428 OS << LBB->getName() << " "; 5429 OS << (const void*)BBDN->getBasicBlock() << ">"; 5430 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5431 if (G && R->getReg() && 5432 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5433 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5434 } else { 5435 OS << " #" << R->getReg(); 5436 } 5437 } else if (const ExternalSymbolSDNode *ES = 5438 dyn_cast<ExternalSymbolSDNode>(this)) { 5439 OS << "'" << ES->getSymbol() << "'"; 5440 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5441 if (M->getValue()) 5442 OS << "<" << M->getValue() << ">"; 5443 else 5444 OS << "<null>"; 5445 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5446 if (M->MO.getValue()) 5447 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5448 else 5449 OS << "<null:" << M->MO.getOffset() << ">"; 5450 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5451 OS << N->getArgFlags().getArgFlagsString(); 5452 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5453 OS << ":" << N->getVT().getMVTString(); 5454 } 5455 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5456 const Value *SrcValue = LD->getSrcValue(); 5457 int SrcOffset = LD->getSrcValueOffset(); 5458 OS << " <"; 5459 if (SrcValue) 5460 OS << SrcValue; 5461 else 5462 OS << "null"; 5463 OS << ":" << SrcOffset << ">"; 5464 5465 bool doExt = true; 5466 switch (LD->getExtensionType()) { 5467 default: doExt = false; break; 5468 case ISD::EXTLOAD: OS << " <anyext "; break; 5469 case ISD::SEXTLOAD: OS << " <sext "; break; 5470 case ISD::ZEXTLOAD: OS << " <zext "; break; 5471 } 5472 if (doExt) 5473 OS << LD->getMemoryVT().getMVTString() << ">"; 5474 5475 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5476 if (*AM) 5477 OS << " " << AM; 5478 if (LD->isVolatile()) 5479 OS << " <volatile>"; 5480 OS << " alignment=" << LD->getAlignment(); 5481 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5482 const Value *SrcValue = ST->getSrcValue(); 5483 int SrcOffset = ST->getSrcValueOffset(); 5484 OS << " <"; 5485 if (SrcValue) 5486 OS << SrcValue; 5487 else 5488 OS << "null"; 5489 OS << ":" << SrcOffset << ">"; 5490 5491 if (ST->isTruncatingStore()) 5492 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5493 5494 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5495 if (*AM) 5496 OS << " " << AM; 5497 if (ST->isVolatile()) 5498 OS << " <volatile>"; 5499 OS << " alignment=" << ST->getAlignment(); 5500 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5501 const Value *SrcValue = AT->getSrcValue(); 5502 int SrcOffset = AT->getSrcValueOffset(); 5503 OS << " <"; 5504 if (SrcValue) 5505 OS << SrcValue; 5506 else 5507 OS << "null"; 5508 OS << ":" << SrcOffset << ">"; 5509 if (AT->isVolatile()) 5510 OS << " <volatile>"; 5511 OS << " alignment=" << AT->getAlignment(); 5512 } 5513} 5514 5515static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5516 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5517 if (N->getOperand(i).getNode()->hasOneUse()) 5518 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5519 else 5520 cerr << "\n" << std::string(indent+2, ' ') 5521 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5522 5523 5524 cerr << "\n" << std::string(indent, ' '); 5525 N->dump(G); 5526} 5527 5528void SelectionDAG::dump() const { 5529 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5530 5531 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5532 I != E; ++I) { 5533 const SDNode *N = I; 5534 if (!N->hasOneUse() && N != getRoot().getNode()) 5535 DumpNodes(N, 2, this); 5536 } 5537 5538 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5539 5540 cerr << "\n\n"; 5541} 5542 5543const Type *ConstantPoolSDNode::getType() const { 5544 if (isMachineConstantPoolEntry()) 5545 return Val.MachineCPVal->getType(); 5546 return Val.ConstVal->getType(); 5547} 5548