SelectionDAG.cpp revision c7a09ab3110b9462ad9646cb60c22c8527491ad9
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/ADT/SetVector.h" 37#include "llvm/ADT/SmallPtrSet.h" 38#include "llvm/ADT/SmallSet.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/ADT/StringExtras.h" 41#include <algorithm> 42#include <cmath> 43using namespace llvm; 44 45/// makeVTList - Return an instance of the SDVTList struct initialized with the 46/// specified members. 47static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 48 SDVTList Res = {VTs, NumVTs}; 49 return Res; 50} 51 52static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 53 switch (VT.getSimpleVT()) { 54 default: assert(0 && "Unknown FP format"); 55 case MVT::f32: return &APFloat::IEEEsingle; 56 case MVT::f64: return &APFloat::IEEEdouble; 57 case MVT::f80: return &APFloat::x87DoubleExtended; 58 case MVT::f128: return &APFloat::IEEEquad; 59 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 60 } 61} 62 63SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 64 65//===----------------------------------------------------------------------===// 66// ConstantFPSDNode Class 67//===----------------------------------------------------------------------===// 68 69/// isExactlyValue - We don't rely on operator== working on double values, as 70/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 71/// As such, this method can be used to do an exact bit-for-bit comparison of 72/// two floating point values. 73bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 74 return getValueAPF().bitwiseIsEqual(V); 75} 76 77bool ConstantFPSDNode::isValueValidForType(MVT VT, 78 const APFloat& Val) { 79 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 80 81 // PPC long double cannot be converted to any other type. 82 if (VT == MVT::ppcf128 || 83 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 84 return false; 85 86 // convert modifies in place, so make a copy. 87 APFloat Val2 = APFloat(Val); 88 bool losesInfo; 89 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 90 &losesInfo); 91 return !losesInfo; 92} 93 94//===----------------------------------------------------------------------===// 95// ISD Namespace 96//===----------------------------------------------------------------------===// 97 98/// isBuildVectorAllOnes - Return true if the specified node is a 99/// BUILD_VECTOR where all of the elements are ~0 or undef. 100bool ISD::isBuildVectorAllOnes(const SDNode *N) { 101 // Look through a bit convert. 102 if (N->getOpcode() == ISD::BIT_CONVERT) 103 N = N->getOperand(0).getNode(); 104 105 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 106 107 unsigned i = 0, e = N->getNumOperands(); 108 109 // Skip over all of the undef values. 110 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 111 ++i; 112 113 // Do not accept an all-undef vector. 114 if (i == e) return false; 115 116 // Do not accept build_vectors that aren't all constants or which have non-~0 117 // elements. 118 SDValue NotZero = N->getOperand(i); 119 if (isa<ConstantSDNode>(NotZero)) { 120 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 121 return false; 122 } else if (isa<ConstantFPSDNode>(NotZero)) { 123 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 124 bitcastToAPInt().isAllOnesValue()) 125 return false; 126 } else 127 return false; 128 129 // Okay, we have at least one ~0 value, check to see if the rest match or are 130 // undefs. 131 for (++i; i != e; ++i) 132 if (N->getOperand(i) != NotZero && 133 N->getOperand(i).getOpcode() != ISD::UNDEF) 134 return false; 135 return true; 136} 137 138 139/// isBuildVectorAllZeros - Return true if the specified node is a 140/// BUILD_VECTOR where all of the elements are 0 or undef. 141bool ISD::isBuildVectorAllZeros(const SDNode *N) { 142 // Look through a bit convert. 143 if (N->getOpcode() == ISD::BIT_CONVERT) 144 N = N->getOperand(0).getNode(); 145 146 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 147 148 unsigned i = 0, e = N->getNumOperands(); 149 150 // Skip over all of the undef values. 151 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 152 ++i; 153 154 // Do not accept an all-undef vector. 155 if (i == e) return false; 156 157 // Do not accept build_vectors that aren't all constants or which have non-~0 158 // elements. 159 SDValue Zero = N->getOperand(i); 160 if (isa<ConstantSDNode>(Zero)) { 161 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 162 return false; 163 } else if (isa<ConstantFPSDNode>(Zero)) { 164 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 165 return false; 166 } else 167 return false; 168 169 // Okay, we have at least one ~0 value, check to see if the rest match or are 170 // undefs. 171 for (++i; i != e; ++i) 172 if (N->getOperand(i) != Zero && 173 N->getOperand(i).getOpcode() != ISD::UNDEF) 174 return false; 175 return true; 176} 177 178/// isScalarToVector - Return true if the specified node is a 179/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 180/// element is not an undef. 181bool ISD::isScalarToVector(const SDNode *N) { 182 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 183 return true; 184 185 if (N->getOpcode() != ISD::BUILD_VECTOR) 186 return false; 187 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 188 return false; 189 unsigned NumElems = N->getNumOperands(); 190 for (unsigned i = 1; i < NumElems; ++i) { 191 SDValue V = N->getOperand(i); 192 if (V.getOpcode() != ISD::UNDEF) 193 return false; 194 } 195 return true; 196} 197 198 199/// isDebugLabel - Return true if the specified node represents a debug 200/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 201bool ISD::isDebugLabel(const SDNode *N) { 202 SDValue Zero; 203 if (N->getOpcode() == ISD::DBG_LABEL) 204 return true; 205 if (N->isMachineOpcode() && 206 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 207 return true; 208 return false; 209} 210 211/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 212/// when given the operation for (X op Y). 213ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 214 // To perform this operation, we just need to swap the L and G bits of the 215 // operation. 216 unsigned OldL = (Operation >> 2) & 1; 217 unsigned OldG = (Operation >> 1) & 1; 218 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 219 (OldL << 1) | // New G bit 220 (OldG << 2)); // New L bit. 221} 222 223/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 224/// 'op' is a valid SetCC operation. 225ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 226 unsigned Operation = Op; 227 if (isInteger) 228 Operation ^= 7; // Flip L, G, E bits, but not U. 229 else 230 Operation ^= 15; // Flip all of the condition bits. 231 232 if (Operation > ISD::SETTRUE2) 233 Operation &= ~8; // Don't let N and U bits get set. 234 235 return ISD::CondCode(Operation); 236} 237 238 239/// isSignedOp - For an integer comparison, return 1 if the comparison is a 240/// signed operation and 2 if the result is an unsigned comparison. Return zero 241/// if the operation does not depend on the sign of the input (setne and seteq). 242static int isSignedOp(ISD::CondCode Opcode) { 243 switch (Opcode) { 244 default: assert(0 && "Illegal integer setcc operation!"); 245 case ISD::SETEQ: 246 case ISD::SETNE: return 0; 247 case ISD::SETLT: 248 case ISD::SETLE: 249 case ISD::SETGT: 250 case ISD::SETGE: return 1; 251 case ISD::SETULT: 252 case ISD::SETULE: 253 case ISD::SETUGT: 254 case ISD::SETUGE: return 2; 255 } 256} 257 258/// getSetCCOrOperation - Return the result of a logical OR between different 259/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 260/// returns SETCC_INVALID if it is not possible to represent the resultant 261/// comparison. 262ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 263 bool isInteger) { 264 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 265 // Cannot fold a signed integer setcc with an unsigned integer setcc. 266 return ISD::SETCC_INVALID; 267 268 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 269 270 // If the N and U bits get set then the resultant comparison DOES suddenly 271 // care about orderedness, and is true when ordered. 272 if (Op > ISD::SETTRUE2) 273 Op &= ~16; // Clear the U bit if the N bit is set. 274 275 // Canonicalize illegal integer setcc's. 276 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 277 Op = ISD::SETNE; 278 279 return ISD::CondCode(Op); 280} 281 282/// getSetCCAndOperation - Return the result of a logical AND between different 283/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 284/// function returns zero if it is not possible to represent the resultant 285/// comparison. 286ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 287 bool isInteger) { 288 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 289 // Cannot fold a signed setcc with an unsigned setcc. 290 return ISD::SETCC_INVALID; 291 292 // Combine all of the condition bits. 293 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 294 295 // Canonicalize illegal integer setcc's. 296 if (isInteger) { 297 switch (Result) { 298 default: break; 299 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 300 case ISD::SETOEQ: // SETEQ & SETU[LG]E 301 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 302 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 303 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 304 } 305 } 306 307 return Result; 308} 309 310const TargetMachine &SelectionDAG::getTarget() const { 311 return MF->getTarget(); 312} 313 314//===----------------------------------------------------------------------===// 315// SDNode Profile Support 316//===----------------------------------------------------------------------===// 317 318/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 319/// 320static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 321 ID.AddInteger(OpC); 322} 323 324/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 325/// solely with their pointer. 326static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 327 ID.AddPointer(VTList.VTs); 328} 329 330/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 331/// 332static void AddNodeIDOperands(FoldingSetNodeID &ID, 333 const SDValue *Ops, unsigned NumOps) { 334 for (; NumOps; --NumOps, ++Ops) { 335 ID.AddPointer(Ops->getNode()); 336 ID.AddInteger(Ops->getResNo()); 337 } 338} 339 340/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 341/// 342static void AddNodeIDOperands(FoldingSetNodeID &ID, 343 const SDUse *Ops, unsigned NumOps) { 344 for (; NumOps; --NumOps, ++Ops) { 345 ID.AddPointer(Ops->getNode()); 346 ID.AddInteger(Ops->getResNo()); 347 } 348} 349 350static void AddNodeIDNode(FoldingSetNodeID &ID, 351 unsigned short OpC, SDVTList VTList, 352 const SDValue *OpList, unsigned N) { 353 AddNodeIDOpcode(ID, OpC); 354 AddNodeIDValueTypes(ID, VTList); 355 AddNodeIDOperands(ID, OpList, N); 356} 357 358/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 359/// the NodeID data. 360static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 361 switch (N->getOpcode()) { 362 default: break; // Normal nodes don't need extra info. 363 case ISD::ARG_FLAGS: 364 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 365 break; 366 case ISD::TargetConstant: 367 case ISD::Constant: 368 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 369 break; 370 case ISD::TargetConstantFP: 371 case ISD::ConstantFP: { 372 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 373 break; 374 } 375 case ISD::TargetGlobalAddress: 376 case ISD::GlobalAddress: 377 case ISD::TargetGlobalTLSAddress: 378 case ISD::GlobalTLSAddress: { 379 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 380 ID.AddPointer(GA->getGlobal()); 381 ID.AddInteger(GA->getOffset()); 382 break; 383 } 384 case ISD::BasicBlock: 385 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 386 break; 387 case ISD::Register: 388 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 389 break; 390 case ISD::DBG_STOPPOINT: { 391 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 392 ID.AddInteger(DSP->getLine()); 393 ID.AddInteger(DSP->getColumn()); 394 ID.AddPointer(DSP->getCompileUnit()); 395 break; 396 } 397 case ISD::SRCVALUE: 398 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 399 break; 400 case ISD::MEMOPERAND: { 401 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 402 MO.Profile(ID); 403 break; 404 } 405 case ISD::FrameIndex: 406 case ISD::TargetFrameIndex: 407 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 408 break; 409 case ISD::JumpTable: 410 case ISD::TargetJumpTable: 411 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 412 break; 413 case ISD::ConstantPool: 414 case ISD::TargetConstantPool: { 415 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 416 ID.AddInteger(CP->getAlignment()); 417 ID.AddInteger(CP->getOffset()); 418 if (CP->isMachineConstantPoolEntry()) 419 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 420 else 421 ID.AddPointer(CP->getConstVal()); 422 break; 423 } 424 case ISD::CALL: { 425 const CallSDNode *Call = cast<CallSDNode>(N); 426 ID.AddInteger(Call->getCallingConv()); 427 ID.AddInteger(Call->isVarArg()); 428 break; 429 } 430 case ISD::LOAD: { 431 const LoadSDNode *LD = cast<LoadSDNode>(N); 432 ID.AddInteger(LD->getMemoryVT().getRawBits()); 433 ID.AddInteger(LD->getRawSubclassData()); 434 break; 435 } 436 case ISD::STORE: { 437 const StoreSDNode *ST = cast<StoreSDNode>(N); 438 ID.AddInteger(ST->getMemoryVT().getRawBits()); 439 ID.AddInteger(ST->getRawSubclassData()); 440 break; 441 } 442 case ISD::ATOMIC_CMP_SWAP: 443 case ISD::ATOMIC_SWAP: 444 case ISD::ATOMIC_LOAD_ADD: 445 case ISD::ATOMIC_LOAD_SUB: 446 case ISD::ATOMIC_LOAD_AND: 447 case ISD::ATOMIC_LOAD_OR: 448 case ISD::ATOMIC_LOAD_XOR: 449 case ISD::ATOMIC_LOAD_NAND: 450 case ISD::ATOMIC_LOAD_MIN: 451 case ISD::ATOMIC_LOAD_MAX: 452 case ISD::ATOMIC_LOAD_UMIN: 453 case ISD::ATOMIC_LOAD_UMAX: { 454 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 455 ID.AddInteger(AT->getMemoryVT().getRawBits()); 456 ID.AddInteger(AT->getRawSubclassData()); 457 break; 458 } 459 } // end switch (N->getOpcode()) 460} 461 462/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 463/// data. 464static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 465 AddNodeIDOpcode(ID, N->getOpcode()); 466 // Add the return value info. 467 AddNodeIDValueTypes(ID, N->getVTList()); 468 // Add the operand info. 469 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 470 471 // Handle SDNode leafs with special info. 472 AddNodeIDCustom(ID, N); 473} 474 475/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 476/// the CSE map that carries alignment, volatility, indexing mode, and 477/// extension/truncation information. 478/// 479static inline unsigned 480encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, 481 bool isVolatile, unsigned Alignment) { 482 assert((ConvType & 3) == ConvType && 483 "ConvType may not require more than 2 bits!"); 484 assert((AM & 7) == AM && 485 "AM may not require more than 3 bits!"); 486 return ConvType | 487 (AM << 2) | 488 (isVolatile << 5) | 489 ((Log2_32(Alignment) + 1) << 6); 490} 491 492//===----------------------------------------------------------------------===// 493// SelectionDAG Class 494//===----------------------------------------------------------------------===// 495 496/// doNotCSE - Return true if CSE should not be performed for this node. 497static bool doNotCSE(SDNode *N) { 498 if (N->getValueType(0) == MVT::Flag) 499 return true; // Never CSE anything that produces a flag. 500 501 switch (N->getOpcode()) { 502 default: break; 503 case ISD::HANDLENODE: 504 case ISD::DBG_LABEL: 505 case ISD::DBG_STOPPOINT: 506 case ISD::EH_LABEL: 507 case ISD::DECLARE: 508 return true; // Never CSE these nodes. 509 } 510 511 // Check that remaining values produced are not flags. 512 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 513 if (N->getValueType(i) == MVT::Flag) 514 return true; // Never CSE anything that produces a flag. 515 516 return false; 517} 518 519/// RemoveDeadNodes - This method deletes all unreachable nodes in the 520/// SelectionDAG. 521void SelectionDAG::RemoveDeadNodes() { 522 // Create a dummy node (which is not added to allnodes), that adds a reference 523 // to the root node, preventing it from being deleted. 524 HandleSDNode Dummy(getRoot()); 525 526 SmallVector<SDNode*, 128> DeadNodes; 527 528 // Add all obviously-dead nodes to the DeadNodes worklist. 529 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 530 if (I->use_empty()) 531 DeadNodes.push_back(I); 532 533 RemoveDeadNodes(DeadNodes); 534 535 // If the root changed (e.g. it was a dead load, update the root). 536 setRoot(Dummy.getValue()); 537} 538 539/// RemoveDeadNodes - This method deletes the unreachable nodes in the 540/// given list, and any nodes that become unreachable as a result. 541void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 542 DAGUpdateListener *UpdateListener) { 543 544 // Process the worklist, deleting the nodes and adding their uses to the 545 // worklist. 546 while (!DeadNodes.empty()) { 547 SDNode *N = DeadNodes.pop_back_val(); 548 549 if (UpdateListener) 550 UpdateListener->NodeDeleted(N, 0); 551 552 // Take the node out of the appropriate CSE map. 553 RemoveNodeFromCSEMaps(N); 554 555 // Next, brutally remove the operand list. This is safe to do, as there are 556 // no cycles in the graph. 557 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 558 SDUse &Use = *I++; 559 SDNode *Operand = Use.getNode(); 560 Use.set(SDValue()); 561 562 // Now that we removed this operand, see if there are no uses of it left. 563 if (Operand->use_empty()) 564 DeadNodes.push_back(Operand); 565 } 566 567 DeallocateNode(N); 568 } 569} 570 571void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 572 SmallVector<SDNode*, 16> DeadNodes(1, N); 573 RemoveDeadNodes(DeadNodes, UpdateListener); 574} 575 576void SelectionDAG::DeleteNode(SDNode *N) { 577 // First take this out of the appropriate CSE map. 578 RemoveNodeFromCSEMaps(N); 579 580 // Finally, remove uses due to operands of this node, remove from the 581 // AllNodes list, and delete the node. 582 DeleteNodeNotInCSEMaps(N); 583} 584 585void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 586 assert(N != AllNodes.begin() && "Cannot delete the entry node!"); 587 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 588 589 // Drop all of the operands and decrement used node's use counts. 590 N->DropOperands(); 591 592 DeallocateNode(N); 593} 594 595void SelectionDAG::DeallocateNode(SDNode *N) { 596 if (N->OperandsNeedDelete) 597 delete[] N->OperandList; 598 599 // Set the opcode to DELETED_NODE to help catch bugs when node 600 // memory is reallocated. 601 N->NodeType = ISD::DELETED_NODE; 602 603 NodeAllocator.Deallocate(AllNodes.remove(N)); 604} 605 606/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 607/// correspond to it. This is useful when we're about to delete or repurpose 608/// the node. We don't want future request for structurally identical nodes 609/// to return N anymore. 610bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 611 bool Erased = false; 612 switch (N->getOpcode()) { 613 case ISD::EntryToken: 614 assert(0 && "EntryToken should not be in CSEMaps!"); 615 return false; 616 case ISD::HANDLENODE: return false; // noop. 617 case ISD::CONDCODE: 618 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 619 "Cond code doesn't exist!"); 620 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 621 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 622 break; 623 case ISD::ExternalSymbol: 624 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 625 break; 626 case ISD::TargetExternalSymbol: 627 Erased = 628 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 629 break; 630 case ISD::VALUETYPE: { 631 MVT VT = cast<VTSDNode>(N)->getVT(); 632 if (VT.isExtended()) { 633 Erased = ExtendedValueTypeNodes.erase(VT); 634 } else { 635 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 636 ValueTypeNodes[VT.getSimpleVT()] = 0; 637 } 638 break; 639 } 640 default: 641 // Remove it from the CSE Map. 642 Erased = CSEMap.RemoveNode(N); 643 break; 644 } 645#ifndef NDEBUG 646 // Verify that the node was actually in one of the CSE maps, unless it has a 647 // flag result (which cannot be CSE'd) or is one of the special cases that are 648 // not subject to CSE. 649 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 650 !N->isMachineOpcode() && !doNotCSE(N)) { 651 N->dump(this); 652 cerr << "\n"; 653 assert(0 && "Node is not in map!"); 654 } 655#endif 656 return Erased; 657} 658 659/// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE 660/// maps and modified in place. Add it back to the CSE maps, unless an identical 661/// node already exists, in which case transfer all its users to the existing 662/// node. This transfer can potentially trigger recursive merging. 663/// 664void 665SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N, 666 DAGUpdateListener *UpdateListener) { 667 // For node types that aren't CSE'd, just act as if no identical node 668 // already exists. 669 if (!doNotCSE(N)) { 670 SDNode *Existing = CSEMap.GetOrInsertNode(N); 671 if (Existing != N) { 672 // If there was already an existing matching node, use ReplaceAllUsesWith 673 // to replace the dead one with the existing one. This can cause 674 // recursive merging of other unrelated nodes down the line. 675 ReplaceAllUsesWith(N, Existing, UpdateListener); 676 677 // N is now dead. Inform the listener if it exists and delete it. 678 if (UpdateListener) 679 UpdateListener->NodeDeleted(N, Existing); 680 DeleteNodeNotInCSEMaps(N); 681 return; 682 } 683 } 684 685 // If the node doesn't already exist, we updated it. Inform a listener if 686 // it exists. 687 if (UpdateListener) 688 UpdateListener->NodeUpdated(N); 689} 690 691/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 692/// were replaced with those specified. If this node is never memoized, 693/// return null, otherwise return a pointer to the slot it would take. If a 694/// node already exists with these operands, the slot will be non-null. 695SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 696 void *&InsertPos) { 697 if (doNotCSE(N)) 698 return 0; 699 700 SDValue Ops[] = { Op }; 701 FoldingSetNodeID ID; 702 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 703 AddNodeIDCustom(ID, N); 704 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 705} 706 707/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 708/// were replaced with those specified. If this node is never memoized, 709/// return null, otherwise return a pointer to the slot it would take. If a 710/// node already exists with these operands, the slot will be non-null. 711SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 712 SDValue Op1, SDValue Op2, 713 void *&InsertPos) { 714 if (doNotCSE(N)) 715 return 0; 716 717 SDValue Ops[] = { Op1, Op2 }; 718 FoldingSetNodeID ID; 719 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 720 AddNodeIDCustom(ID, N); 721 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 722} 723 724 725/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 726/// were replaced with those specified. If this node is never memoized, 727/// return null, otherwise return a pointer to the slot it would take. If a 728/// node already exists with these operands, the slot will be non-null. 729SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 730 const SDValue *Ops,unsigned NumOps, 731 void *&InsertPos) { 732 if (doNotCSE(N)) 733 return 0; 734 735 FoldingSetNodeID ID; 736 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 737 AddNodeIDCustom(ID, N); 738 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 739} 740 741/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 742void SelectionDAG::VerifyNode(SDNode *N) { 743 switch (N->getOpcode()) { 744 default: 745 break; 746 case ISD::BUILD_PAIR: { 747 MVT VT = N->getValueType(0); 748 assert(N->getNumValues() == 1 && "Too many results!"); 749 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 750 "Wrong return type!"); 751 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 752 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 753 "Mismatched operand types!"); 754 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 755 "Wrong operand type!"); 756 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 757 "Wrong return type size"); 758 break; 759 } 760 case ISD::BUILD_VECTOR: { 761 assert(N->getNumValues() == 1 && "Too many results!"); 762 assert(N->getValueType(0).isVector() && "Wrong return type!"); 763 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 764 "Wrong number of operands!"); 765 // FIXME: Change vector_shuffle to a variadic node with mask elements being 766 // operands of the node. Currently the mask is a BUILD_VECTOR passed as an 767 // operand, and it is not always possible to legalize it. Turning off the 768 // following checks at least makes it possible to legalize most of the time. 769// MVT EltVT = N->getValueType(0).getVectorElementType(); 770// for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 771// assert(I->getValueType() == EltVT && 772// "Wrong operand type!"); 773 break; 774 } 775 } 776} 777 778/// getMVTAlignment - Compute the default alignment value for the 779/// given type. 780/// 781unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 782 const Type *Ty = VT == MVT::iPTR ? 783 PointerType::get(Type::Int8Ty, 0) : 784 VT.getTypeForMVT(); 785 786 return TLI.getTargetData()->getABITypeAlignment(Ty); 787} 788 789// EntryNode could meaningfully have debug info if we can find it... 790SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 791 : TLI(tli), FLI(fli), DW(0), 792 EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(), 793 getVTList(MVT::Other)), Root(getEntryNode()) { 794 AllNodes.push_back(&EntryNode); 795} 796 797void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi, 798 DwarfWriter *dw) { 799 MF = &mf; 800 MMI = mmi; 801 DW = dw; 802} 803 804SelectionDAG::~SelectionDAG() { 805 allnodes_clear(); 806} 807 808void SelectionDAG::allnodes_clear() { 809 assert(&*AllNodes.begin() == &EntryNode); 810 AllNodes.remove(AllNodes.begin()); 811 while (!AllNodes.empty()) 812 DeallocateNode(AllNodes.begin()); 813} 814 815void SelectionDAG::clear() { 816 allnodes_clear(); 817 OperandAllocator.Reset(); 818 CSEMap.clear(); 819 820 ExtendedValueTypeNodes.clear(); 821 ExternalSymbols.clear(); 822 TargetExternalSymbols.clear(); 823 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 824 static_cast<CondCodeSDNode*>(0)); 825 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 826 static_cast<SDNode*>(0)); 827 828 EntryNode.UseList = 0; 829 AllNodes.push_back(&EntryNode); 830 Root = getEntryNode(); 831} 832 833SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { 834 if (Op.getValueType() == VT) return Op; 835 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 836 VT.getSizeInBits()); 837 return getNode(ISD::AND, DL, Op.getValueType(), Op, 838 getConstant(Imm, Op.getValueType())); 839} 840 841/// getNOT - Create a bitwise NOT operation as (XOR Val, -1). 842/// 843SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) { 844 SDValue NegOne; 845 if (VT.isVector()) { 846 MVT EltVT = VT.getVectorElementType(); 847 SDValue NegOneElt = 848 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), EltVT); 849 std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOneElt); 850 NegOne = getNode(ISD::BUILD_VECTOR, DL, VT, &NegOnes[0], NegOnes.size()); 851 } else { 852 NegOne = getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 853 } 854 return getNode(ISD::XOR, DL, VT, Val, NegOne); 855} 856 857SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 858 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 859 assert((EltVT.getSizeInBits() >= 64 || 860 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) && 861 "getConstant with a uint64_t value that doesn't fit in the type!"); 862 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 863} 864 865SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 866 return getConstant(*ConstantInt::get(Val), VT, isT); 867} 868 869SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 870 assert(VT.isInteger() && "Cannot create FP integer constant!"); 871 872 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 873 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 874 "APInt size does not match type size!"); 875 876 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 877 FoldingSetNodeID ID; 878 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 879 ID.AddPointer(&Val); 880 void *IP = 0; 881 SDNode *N = NULL; 882 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 883 if (!VT.isVector()) 884 return SDValue(N, 0); 885 if (!N) { 886 N = NodeAllocator.Allocate<ConstantSDNode>(); 887 new (N) ConstantSDNode(isT, &Val, EltVT); 888 CSEMap.InsertNode(N, IP); 889 AllNodes.push_back(N); 890 } 891 892 SDValue Result(N, 0); 893 if (VT.isVector()) { 894 SmallVector<SDValue, 8> Ops; 895 Ops.assign(VT.getVectorNumElements(), Result); 896 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 897 VT, &Ops[0], Ops.size()); 898 } 899 return Result; 900} 901 902SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 903 return getConstant(Val, TLI.getPointerTy(), isTarget); 904} 905 906 907SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 908 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 909} 910 911SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 912 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 913 914 MVT EltVT = 915 VT.isVector() ? VT.getVectorElementType() : VT; 916 917 // Do the map lookup using the actual bit pattern for the floating point 918 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 919 // we don't have issues with SNANs. 920 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 921 FoldingSetNodeID ID; 922 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 923 ID.AddPointer(&V); 924 void *IP = 0; 925 SDNode *N = NULL; 926 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 927 if (!VT.isVector()) 928 return SDValue(N, 0); 929 if (!N) { 930 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 931 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 932 CSEMap.InsertNode(N, IP); 933 AllNodes.push_back(N); 934 } 935 936 SDValue Result(N, 0); 937 if (VT.isVector()) { 938 SmallVector<SDValue, 8> Ops; 939 Ops.assign(VT.getVectorNumElements(), Result); 940 // FIXME DebugLoc info might be appropriate here 941 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 942 VT, &Ops[0], Ops.size()); 943 } 944 return Result; 945} 946 947SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 948 MVT EltVT = 949 VT.isVector() ? VT.getVectorElementType() : VT; 950 if (EltVT==MVT::f32) 951 return getConstantFP(APFloat((float)Val), VT, isTarget); 952 else 953 return getConstantFP(APFloat(Val), VT, isTarget); 954} 955 956SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 957 MVT VT, int64_t Offset, 958 bool isTargetGA) { 959 unsigned Opc; 960 961 // Truncate (with sign-extension) the offset value to the pointer size. 962 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 963 if (BitWidth < 64) 964 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 965 966 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 967 if (!GVar) { 968 // If GV is an alias then use the aliasee for determining thread-localness. 969 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 970 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 971 } 972 973 if (GVar && GVar->isThreadLocal()) 974 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 975 else 976 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 977 978 FoldingSetNodeID ID; 979 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 980 ID.AddPointer(GV); 981 ID.AddInteger(Offset); 982 void *IP = 0; 983 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 984 return SDValue(E, 0); 985 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 986 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 987 CSEMap.InsertNode(N, IP); 988 AllNodes.push_back(N); 989 return SDValue(N, 0); 990} 991 992SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 993 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 994 FoldingSetNodeID ID; 995 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 996 ID.AddInteger(FI); 997 void *IP = 0; 998 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 999 return SDValue(E, 0); 1000 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 1001 new (N) FrameIndexSDNode(FI, VT, isTarget); 1002 CSEMap.InsertNode(N, IP); 1003 AllNodes.push_back(N); 1004 return SDValue(N, 0); 1005} 1006 1007SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 1008 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1009 FoldingSetNodeID ID; 1010 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1011 ID.AddInteger(JTI); 1012 void *IP = 0; 1013 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1014 return SDValue(E, 0); 1015 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1016 new (N) JumpTableSDNode(JTI, VT, isTarget); 1017 CSEMap.InsertNode(N, IP); 1018 AllNodes.push_back(N); 1019 return SDValue(N, 0); 1020} 1021 1022SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1023 unsigned Alignment, int Offset, 1024 bool isTarget) { 1025 if (Alignment == 0) 1026 Alignment = 1027 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1028 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1029 FoldingSetNodeID ID; 1030 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1031 ID.AddInteger(Alignment); 1032 ID.AddInteger(Offset); 1033 ID.AddPointer(C); 1034 void *IP = 0; 1035 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1036 return SDValue(E, 0); 1037 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1038 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1039 CSEMap.InsertNode(N, IP); 1040 AllNodes.push_back(N); 1041 return SDValue(N, 0); 1042} 1043 1044 1045SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1046 unsigned Alignment, int Offset, 1047 bool isTarget) { 1048 if (Alignment == 0) 1049 Alignment = 1050 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1051 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1052 FoldingSetNodeID ID; 1053 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1054 ID.AddInteger(Alignment); 1055 ID.AddInteger(Offset); 1056 C->AddSelectionDAGCSEId(ID); 1057 void *IP = 0; 1058 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1059 return SDValue(E, 0); 1060 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1061 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1062 CSEMap.InsertNode(N, IP); 1063 AllNodes.push_back(N); 1064 return SDValue(N, 0); 1065} 1066 1067SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1068 FoldingSetNodeID ID; 1069 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1070 ID.AddPointer(MBB); 1071 void *IP = 0; 1072 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1073 return SDValue(E, 0); 1074 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1075 new (N) BasicBlockSDNode(MBB); 1076 CSEMap.InsertNode(N, IP); 1077 AllNodes.push_back(N); 1078 return SDValue(N, 0); 1079} 1080 1081SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1082 FoldingSetNodeID ID; 1083 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1084 ID.AddInteger(Flags.getRawBits()); 1085 void *IP = 0; 1086 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1087 return SDValue(E, 0); 1088 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1089 new (N) ARG_FLAGSSDNode(Flags); 1090 CSEMap.InsertNode(N, IP); 1091 AllNodes.push_back(N); 1092 return SDValue(N, 0); 1093} 1094 1095SDValue SelectionDAG::getValueType(MVT VT) { 1096 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1097 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1098 1099 SDNode *&N = VT.isExtended() ? 1100 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1101 1102 if (N) return SDValue(N, 0); 1103 N = NodeAllocator.Allocate<VTSDNode>(); 1104 new (N) VTSDNode(VT); 1105 AllNodes.push_back(N); 1106 return SDValue(N, 0); 1107} 1108 1109SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1110 SDNode *&N = ExternalSymbols[Sym]; 1111 if (N) return SDValue(N, 0); 1112 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1113 new (N) ExternalSymbolSDNode(false, Sym, VT); 1114 AllNodes.push_back(N); 1115 return SDValue(N, 0); 1116} 1117 1118SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1119 SDNode *&N = TargetExternalSymbols[Sym]; 1120 if (N) return SDValue(N, 0); 1121 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1122 new (N) ExternalSymbolSDNode(true, Sym, VT); 1123 AllNodes.push_back(N); 1124 return SDValue(N, 0); 1125} 1126 1127SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1128 if ((unsigned)Cond >= CondCodeNodes.size()) 1129 CondCodeNodes.resize(Cond+1); 1130 1131 if (CondCodeNodes[Cond] == 0) { 1132 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1133 new (N) CondCodeSDNode(Cond); 1134 CondCodeNodes[Cond] = N; 1135 AllNodes.push_back(N); 1136 } 1137 return SDValue(CondCodeNodes[Cond], 0); 1138} 1139 1140SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl, 1141 SDValue Val, SDValue DTy, 1142 SDValue STy, SDValue Rnd, SDValue Sat, 1143 ISD::CvtCode Code) { 1144 // If the src and dest types are the same and the conversion is between 1145 // integer types of the same sign or two floats, no conversion is necessary. 1146 if (DTy == STy && 1147 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF)) 1148 return Val; 1149 1150 FoldingSetNodeID ID; 1151 void* IP = 0; 1152 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1153 return SDValue(E, 0); 1154 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1155 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1156 new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code); 1157 CSEMap.InsertNode(N, IP); 1158 AllNodes.push_back(N); 1159 return SDValue(N, 0); 1160} 1161 1162SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1163 FoldingSetNodeID ID; 1164 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1165 ID.AddInteger(RegNo); 1166 void *IP = 0; 1167 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1168 return SDValue(E, 0); 1169 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1170 new (N) RegisterSDNode(RegNo, VT); 1171 CSEMap.InsertNode(N, IP); 1172 AllNodes.push_back(N); 1173 return SDValue(N, 0); 1174} 1175 1176SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1177 unsigned Line, unsigned Col, 1178 Value *CU) { 1179 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1180 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1181 AllNodes.push_back(N); 1182 return SDValue(N, 0); 1183} 1184 1185SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, 1186 SDValue Root, 1187 unsigned LabelID) { 1188 FoldingSetNodeID ID; 1189 SDValue Ops[] = { Root }; 1190 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1191 ID.AddInteger(LabelID); 1192 void *IP = 0; 1193 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1194 return SDValue(E, 0); 1195 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1196 new (N) LabelSDNode(Opcode, dl, Root, LabelID); 1197 CSEMap.InsertNode(N, IP); 1198 AllNodes.push_back(N); 1199 return SDValue(N, 0); 1200} 1201 1202SDValue SelectionDAG::getSrcValue(const Value *V) { 1203 assert((!V || isa<PointerType>(V->getType())) && 1204 "SrcValue is not a pointer?"); 1205 1206 FoldingSetNodeID ID; 1207 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1208 ID.AddPointer(V); 1209 1210 void *IP = 0; 1211 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1212 return SDValue(E, 0); 1213 1214 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1215 new (N) SrcValueSDNode(V); 1216 CSEMap.InsertNode(N, IP); 1217 AllNodes.push_back(N); 1218 return SDValue(N, 0); 1219} 1220 1221SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1222#ifndef NDEBUG 1223 const Value *v = MO.getValue(); 1224 assert((!v || isa<PointerType>(v->getType())) && 1225 "SrcValue is not a pointer?"); 1226#endif 1227 1228 FoldingSetNodeID ID; 1229 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1230 MO.Profile(ID); 1231 1232 void *IP = 0; 1233 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1234 return SDValue(E, 0); 1235 1236 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1237 new (N) MemOperandSDNode(MO); 1238 CSEMap.InsertNode(N, IP); 1239 AllNodes.push_back(N); 1240 return SDValue(N, 0); 1241} 1242 1243/// getShiftAmountOperand - Return the specified value casted to 1244/// the target's desired shift amount type. 1245SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { 1246 MVT OpTy = Op.getValueType(); 1247 MVT ShTy = TLI.getShiftAmountTy(); 1248 if (OpTy == ShTy || OpTy.isVector()) return Op; 1249 1250 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1251 return getNode(Opcode, Op.getDebugLoc(), ShTy, Op); 1252} 1253 1254/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1255/// specified value type. 1256SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1257 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1258 unsigned ByteSize = VT.getStoreSizeInBits()/8; 1259 const Type *Ty = VT.getTypeForMVT(); 1260 unsigned StackAlign = 1261 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1262 1263 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1264 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1265} 1266 1267/// CreateStackTemporary - Create a stack temporary suitable for holding 1268/// either of the specified value types. 1269SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) { 1270 unsigned Bytes = std::max(VT1.getStoreSizeInBits(), 1271 VT2.getStoreSizeInBits())/8; 1272 const Type *Ty1 = VT1.getTypeForMVT(); 1273 const Type *Ty2 = VT2.getTypeForMVT(); 1274 const TargetData *TD = TLI.getTargetData(); 1275 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1), 1276 TD->getPrefTypeAlignment(Ty2)); 1277 1278 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1279 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align); 1280 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1281} 1282 1283SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1284 SDValue N2, ISD::CondCode Cond, DebugLoc dl) { 1285 // These setcc operations always fold. 1286 switch (Cond) { 1287 default: break; 1288 case ISD::SETFALSE: 1289 case ISD::SETFALSE2: return getConstant(0, VT); 1290 case ISD::SETTRUE: 1291 case ISD::SETTRUE2: return getConstant(1, VT); 1292 1293 case ISD::SETOEQ: 1294 case ISD::SETOGT: 1295 case ISD::SETOGE: 1296 case ISD::SETOLT: 1297 case ISD::SETOLE: 1298 case ISD::SETONE: 1299 case ISD::SETO: 1300 case ISD::SETUO: 1301 case ISD::SETUEQ: 1302 case ISD::SETUNE: 1303 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1304 break; 1305 } 1306 1307 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1308 const APInt &C2 = N2C->getAPIntValue(); 1309 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1310 const APInt &C1 = N1C->getAPIntValue(); 1311 1312 switch (Cond) { 1313 default: assert(0 && "Unknown integer setcc!"); 1314 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1315 case ISD::SETNE: return getConstant(C1 != C2, VT); 1316 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1317 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1318 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1319 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1320 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1321 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1322 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1323 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1324 } 1325 } 1326 } 1327 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1328 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1329 // No compile time operations on this type yet. 1330 if (N1C->getValueType(0) == MVT::ppcf128) 1331 return SDValue(); 1332 1333 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1334 switch (Cond) { 1335 default: break; 1336 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1337 return getUNDEF(VT); 1338 // fall through 1339 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1340 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1341 return getUNDEF(VT); 1342 // fall through 1343 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1344 R==APFloat::cmpLessThan, VT); 1345 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1346 return getUNDEF(VT); 1347 // fall through 1348 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1349 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1350 return getUNDEF(VT); 1351 // fall through 1352 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1353 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1354 return getUNDEF(VT); 1355 // fall through 1356 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1357 R==APFloat::cmpEqual, VT); 1358 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1359 return getUNDEF(VT); 1360 // fall through 1361 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1362 R==APFloat::cmpEqual, VT); 1363 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1364 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1365 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1366 R==APFloat::cmpEqual, VT); 1367 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1368 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1369 R==APFloat::cmpLessThan, VT); 1370 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1371 R==APFloat::cmpUnordered, VT); 1372 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1373 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1374 } 1375 } else { 1376 // Ensure that the constant occurs on the RHS. 1377 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1378 } 1379 } 1380 1381 // Could not fold it. 1382 return SDValue(); 1383} 1384 1385/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1386/// use this predicate to simplify operations downstream. 1387bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1388 unsigned BitWidth = Op.getValueSizeInBits(); 1389 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1390} 1391 1392/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1393/// this predicate to simplify operations downstream. Mask is known to be zero 1394/// for bits that V cannot have. 1395bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1396 unsigned Depth) const { 1397 APInt KnownZero, KnownOne; 1398 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1399 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1400 return (KnownZero & Mask) == Mask; 1401} 1402 1403/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1404/// known to be either zero or one and return them in the KnownZero/KnownOne 1405/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1406/// processing. 1407void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1408 APInt &KnownZero, APInt &KnownOne, 1409 unsigned Depth) const { 1410 unsigned BitWidth = Mask.getBitWidth(); 1411 assert(BitWidth == Op.getValueType().getSizeInBits() && 1412 "Mask size mismatches value type size!"); 1413 1414 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1415 if (Depth == 6 || Mask == 0) 1416 return; // Limit search depth. 1417 1418 APInt KnownZero2, KnownOne2; 1419 1420 switch (Op.getOpcode()) { 1421 case ISD::Constant: 1422 // We know all of the bits for a constant! 1423 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1424 KnownZero = ~KnownOne & Mask; 1425 return; 1426 case ISD::AND: 1427 // If either the LHS or the RHS are Zero, the result is zero. 1428 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1429 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1430 KnownZero2, KnownOne2, Depth+1); 1431 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1432 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1433 1434 // Output known-1 bits are only known if set in both the LHS & RHS. 1435 KnownOne &= KnownOne2; 1436 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1437 KnownZero |= KnownZero2; 1438 return; 1439 case ISD::OR: 1440 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1441 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1442 KnownZero2, KnownOne2, Depth+1); 1443 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1444 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1445 1446 // Output known-0 bits are only known if clear in both the LHS & RHS. 1447 KnownZero &= KnownZero2; 1448 // Output known-1 are known to be set if set in either the LHS | RHS. 1449 KnownOne |= KnownOne2; 1450 return; 1451 case ISD::XOR: { 1452 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1453 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1454 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1455 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1456 1457 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1458 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1459 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1460 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1461 KnownZero = KnownZeroOut; 1462 return; 1463 } 1464 case ISD::MUL: { 1465 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1466 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1467 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1468 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1469 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1470 1471 // If low bits are zero in either operand, output low known-0 bits. 1472 // Also compute a conserative estimate for high known-0 bits. 1473 // More trickiness is possible, but this is sufficient for the 1474 // interesting case of alignment computation. 1475 KnownOne.clear(); 1476 unsigned TrailZ = KnownZero.countTrailingOnes() + 1477 KnownZero2.countTrailingOnes(); 1478 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1479 KnownZero2.countLeadingOnes(), 1480 BitWidth) - BitWidth; 1481 1482 TrailZ = std::min(TrailZ, BitWidth); 1483 LeadZ = std::min(LeadZ, BitWidth); 1484 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1485 APInt::getHighBitsSet(BitWidth, LeadZ); 1486 KnownZero &= Mask; 1487 return; 1488 } 1489 case ISD::UDIV: { 1490 // For the purposes of computing leading zeros we can conservatively 1491 // treat a udiv as a logical right shift by the power of 2 known to 1492 // be less than the denominator. 1493 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1494 ComputeMaskedBits(Op.getOperand(0), 1495 AllOnes, KnownZero2, KnownOne2, Depth+1); 1496 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1497 1498 KnownOne2.clear(); 1499 KnownZero2.clear(); 1500 ComputeMaskedBits(Op.getOperand(1), 1501 AllOnes, KnownZero2, KnownOne2, Depth+1); 1502 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1503 if (RHSUnknownLeadingOnes != BitWidth) 1504 LeadZ = std::min(BitWidth, 1505 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1506 1507 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1508 return; 1509 } 1510 case ISD::SELECT: 1511 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1512 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1513 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1514 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1515 1516 // Only known if known in both the LHS and RHS. 1517 KnownOne &= KnownOne2; 1518 KnownZero &= KnownZero2; 1519 return; 1520 case ISD::SELECT_CC: 1521 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1522 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1523 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1524 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1525 1526 // Only known if known in both the LHS and RHS. 1527 KnownOne &= KnownOne2; 1528 KnownZero &= KnownZero2; 1529 return; 1530 case ISD::SADDO: 1531 case ISD::UADDO: 1532 case ISD::SSUBO: 1533 case ISD::USUBO: 1534 case ISD::SMULO: 1535 case ISD::UMULO: 1536 if (Op.getResNo() != 1) 1537 return; 1538 // The boolean result conforms to getBooleanContents. Fall through. 1539 case ISD::SETCC: 1540 // If we know the result of a setcc has the top bits zero, use this info. 1541 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1542 BitWidth > 1) 1543 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1544 return; 1545 case ISD::SHL: 1546 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1547 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1548 unsigned ShAmt = SA->getZExtValue(); 1549 1550 // If the shift count is an invalid immediate, don't do anything. 1551 if (ShAmt >= BitWidth) 1552 return; 1553 1554 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1555 KnownZero, KnownOne, Depth+1); 1556 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1557 KnownZero <<= ShAmt; 1558 KnownOne <<= ShAmt; 1559 // low bits known zero. 1560 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1561 } 1562 return; 1563 case ISD::SRL: 1564 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1565 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1566 unsigned ShAmt = SA->getZExtValue(); 1567 1568 // If the shift count is an invalid immediate, don't do anything. 1569 if (ShAmt >= BitWidth) 1570 return; 1571 1572 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1573 KnownZero, KnownOne, Depth+1); 1574 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1575 KnownZero = KnownZero.lshr(ShAmt); 1576 KnownOne = KnownOne.lshr(ShAmt); 1577 1578 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1579 KnownZero |= HighBits; // High bits known zero. 1580 } 1581 return; 1582 case ISD::SRA: 1583 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1584 unsigned ShAmt = SA->getZExtValue(); 1585 1586 // If the shift count is an invalid immediate, don't do anything. 1587 if (ShAmt >= BitWidth) 1588 return; 1589 1590 APInt InDemandedMask = (Mask << ShAmt); 1591 // If any of the demanded bits are produced by the sign extension, we also 1592 // demand the input sign bit. 1593 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1594 if (HighBits.getBoolValue()) 1595 InDemandedMask |= APInt::getSignBit(BitWidth); 1596 1597 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1598 Depth+1); 1599 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1600 KnownZero = KnownZero.lshr(ShAmt); 1601 KnownOne = KnownOne.lshr(ShAmt); 1602 1603 // Handle the sign bits. 1604 APInt SignBit = APInt::getSignBit(BitWidth); 1605 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1606 1607 if (KnownZero.intersects(SignBit)) { 1608 KnownZero |= HighBits; // New bits are known zero. 1609 } else if (KnownOne.intersects(SignBit)) { 1610 KnownOne |= HighBits; // New bits are known one. 1611 } 1612 } 1613 return; 1614 case ISD::SIGN_EXTEND_INREG: { 1615 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1616 unsigned EBits = EVT.getSizeInBits(); 1617 1618 // Sign extension. Compute the demanded bits in the result that are not 1619 // present in the input. 1620 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1621 1622 APInt InSignBit = APInt::getSignBit(EBits); 1623 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1624 1625 // If the sign extended bits are demanded, we know that the sign 1626 // bit is demanded. 1627 InSignBit.zext(BitWidth); 1628 if (NewBits.getBoolValue()) 1629 InputDemandedBits |= InSignBit; 1630 1631 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1632 KnownZero, KnownOne, Depth+1); 1633 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1634 1635 // If the sign bit of the input is known set or clear, then we know the 1636 // top bits of the result. 1637 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1638 KnownZero |= NewBits; 1639 KnownOne &= ~NewBits; 1640 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1641 KnownOne |= NewBits; 1642 KnownZero &= ~NewBits; 1643 } else { // Input sign bit unknown 1644 KnownZero &= ~NewBits; 1645 KnownOne &= ~NewBits; 1646 } 1647 return; 1648 } 1649 case ISD::CTTZ: 1650 case ISD::CTLZ: 1651 case ISD::CTPOP: { 1652 unsigned LowBits = Log2_32(BitWidth)+1; 1653 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1654 KnownOne.clear(); 1655 return; 1656 } 1657 case ISD::LOAD: { 1658 if (ISD::isZEXTLoad(Op.getNode())) { 1659 LoadSDNode *LD = cast<LoadSDNode>(Op); 1660 MVT VT = LD->getMemoryVT(); 1661 unsigned MemBits = VT.getSizeInBits(); 1662 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1663 } 1664 return; 1665 } 1666 case ISD::ZERO_EXTEND: { 1667 MVT InVT = Op.getOperand(0).getValueType(); 1668 unsigned InBits = InVT.getSizeInBits(); 1669 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1670 APInt InMask = Mask; 1671 InMask.trunc(InBits); 1672 KnownZero.trunc(InBits); 1673 KnownOne.trunc(InBits); 1674 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1675 KnownZero.zext(BitWidth); 1676 KnownOne.zext(BitWidth); 1677 KnownZero |= NewBits; 1678 return; 1679 } 1680 case ISD::SIGN_EXTEND: { 1681 MVT InVT = Op.getOperand(0).getValueType(); 1682 unsigned InBits = InVT.getSizeInBits(); 1683 APInt InSignBit = APInt::getSignBit(InBits); 1684 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1685 APInt InMask = Mask; 1686 InMask.trunc(InBits); 1687 1688 // If any of the sign extended bits are demanded, we know that the sign 1689 // bit is demanded. Temporarily set this bit in the mask for our callee. 1690 if (NewBits.getBoolValue()) 1691 InMask |= InSignBit; 1692 1693 KnownZero.trunc(InBits); 1694 KnownOne.trunc(InBits); 1695 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1696 1697 // Note if the sign bit is known to be zero or one. 1698 bool SignBitKnownZero = KnownZero.isNegative(); 1699 bool SignBitKnownOne = KnownOne.isNegative(); 1700 assert(!(SignBitKnownZero && SignBitKnownOne) && 1701 "Sign bit can't be known to be both zero and one!"); 1702 1703 // If the sign bit wasn't actually demanded by our caller, we don't 1704 // want it set in the KnownZero and KnownOne result values. Reset the 1705 // mask and reapply it to the result values. 1706 InMask = Mask; 1707 InMask.trunc(InBits); 1708 KnownZero &= InMask; 1709 KnownOne &= InMask; 1710 1711 KnownZero.zext(BitWidth); 1712 KnownOne.zext(BitWidth); 1713 1714 // If the sign bit is known zero or one, the top bits match. 1715 if (SignBitKnownZero) 1716 KnownZero |= NewBits; 1717 else if (SignBitKnownOne) 1718 KnownOne |= NewBits; 1719 return; 1720 } 1721 case ISD::ANY_EXTEND: { 1722 MVT InVT = Op.getOperand(0).getValueType(); 1723 unsigned InBits = InVT.getSizeInBits(); 1724 APInt InMask = Mask; 1725 InMask.trunc(InBits); 1726 KnownZero.trunc(InBits); 1727 KnownOne.trunc(InBits); 1728 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1729 KnownZero.zext(BitWidth); 1730 KnownOne.zext(BitWidth); 1731 return; 1732 } 1733 case ISD::TRUNCATE: { 1734 MVT InVT = Op.getOperand(0).getValueType(); 1735 unsigned InBits = InVT.getSizeInBits(); 1736 APInt InMask = Mask; 1737 InMask.zext(InBits); 1738 KnownZero.zext(InBits); 1739 KnownOne.zext(InBits); 1740 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1741 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1742 KnownZero.trunc(BitWidth); 1743 KnownOne.trunc(BitWidth); 1744 break; 1745 } 1746 case ISD::AssertZext: { 1747 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1748 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1749 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1750 KnownOne, Depth+1); 1751 KnownZero |= (~InMask) & Mask; 1752 return; 1753 } 1754 case ISD::FGETSIGN: 1755 // All bits are zero except the low bit. 1756 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1757 return; 1758 1759 case ISD::SUB: { 1760 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1761 // We know that the top bits of C-X are clear if X contains less bits 1762 // than C (i.e. no wrap-around can happen). For example, 20-X is 1763 // positive if we can prove that X is >= 0 and < 16. 1764 if (CLHS->getAPIntValue().isNonNegative()) { 1765 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1766 // NLZ can't be BitWidth with no sign bit 1767 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1768 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1769 Depth+1); 1770 1771 // If all of the MaskV bits are known to be zero, then we know the 1772 // output top bits are zero, because we now know that the output is 1773 // from [0-C]. 1774 if ((KnownZero2 & MaskV) == MaskV) { 1775 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1776 // Top bits known zero. 1777 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1778 } 1779 } 1780 } 1781 } 1782 // fall through 1783 case ISD::ADD: { 1784 // Output known-0 bits are known if clear or set in both the low clear bits 1785 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1786 // low 3 bits clear. 1787 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1788 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1789 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1790 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1791 1792 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1793 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1794 KnownZeroOut = std::min(KnownZeroOut, 1795 KnownZero2.countTrailingOnes()); 1796 1797 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1798 return; 1799 } 1800 case ISD::SREM: 1801 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1802 const APInt &RA = Rem->getAPIntValue(); 1803 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1804 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1805 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1806 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1807 1808 // If the sign bit of the first operand is zero, the sign bit of 1809 // the result is zero. If the first operand has no one bits below 1810 // the second operand's single 1 bit, its sign will be zero. 1811 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1812 KnownZero2 |= ~LowBits; 1813 1814 KnownZero |= KnownZero2 & Mask; 1815 1816 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1817 } 1818 } 1819 return; 1820 case ISD::UREM: { 1821 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1822 const APInt &RA = Rem->getAPIntValue(); 1823 if (RA.isPowerOf2()) { 1824 APInt LowBits = (RA - 1); 1825 APInt Mask2 = LowBits & Mask; 1826 KnownZero |= ~LowBits & Mask; 1827 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1828 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1829 break; 1830 } 1831 } 1832 1833 // Since the result is less than or equal to either operand, any leading 1834 // zero bits in either operand must also exist in the result. 1835 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1836 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1837 Depth+1); 1838 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1839 Depth+1); 1840 1841 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1842 KnownZero2.countLeadingOnes()); 1843 KnownOne.clear(); 1844 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1845 return; 1846 } 1847 default: 1848 // Allow the target to implement this method for its nodes. 1849 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1850 case ISD::INTRINSIC_WO_CHAIN: 1851 case ISD::INTRINSIC_W_CHAIN: 1852 case ISD::INTRINSIC_VOID: 1853 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1854 } 1855 return; 1856 } 1857} 1858 1859/// ComputeNumSignBits - Return the number of times the sign bit of the 1860/// register is replicated into the other bits. We know that at least 1 bit 1861/// is always equal to the sign bit (itself), but other cases can give us 1862/// information. For example, immediately after an "SRA X, 2", we know that 1863/// the top 3 bits are all equal to each other, so we return 3. 1864unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1865 MVT VT = Op.getValueType(); 1866 assert(VT.isInteger() && "Invalid VT!"); 1867 unsigned VTBits = VT.getSizeInBits(); 1868 unsigned Tmp, Tmp2; 1869 unsigned FirstAnswer = 1; 1870 1871 if (Depth == 6) 1872 return 1; // Limit search depth. 1873 1874 switch (Op.getOpcode()) { 1875 default: break; 1876 case ISD::AssertSext: 1877 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1878 return VTBits-Tmp+1; 1879 case ISD::AssertZext: 1880 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1881 return VTBits-Tmp; 1882 1883 case ISD::Constant: { 1884 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1885 // If negative, return # leading ones. 1886 if (Val.isNegative()) 1887 return Val.countLeadingOnes(); 1888 1889 // Return # leading zeros. 1890 return Val.countLeadingZeros(); 1891 } 1892 1893 case ISD::SIGN_EXTEND: 1894 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1895 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1896 1897 case ISD::SIGN_EXTEND_INREG: 1898 // Max of the input and what this extends. 1899 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1900 Tmp = VTBits-Tmp+1; 1901 1902 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1903 return std::max(Tmp, Tmp2); 1904 1905 case ISD::SRA: 1906 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1907 // SRA X, C -> adds C sign bits. 1908 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1909 Tmp += C->getZExtValue(); 1910 if (Tmp > VTBits) Tmp = VTBits; 1911 } 1912 return Tmp; 1913 case ISD::SHL: 1914 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1915 // shl destroys sign bits. 1916 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1917 if (C->getZExtValue() >= VTBits || // Bad shift. 1918 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 1919 return Tmp - C->getZExtValue(); 1920 } 1921 break; 1922 case ISD::AND: 1923 case ISD::OR: 1924 case ISD::XOR: // NOT is handled here. 1925 // Logical binary ops preserve the number of sign bits at the worst. 1926 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1927 if (Tmp != 1) { 1928 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1929 FirstAnswer = std::min(Tmp, Tmp2); 1930 // We computed what we know about the sign bits as our first 1931 // answer. Now proceed to the generic code that uses 1932 // ComputeMaskedBits, and pick whichever answer is better. 1933 } 1934 break; 1935 1936 case ISD::SELECT: 1937 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1938 if (Tmp == 1) return 1; // Early out. 1939 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1940 return std::min(Tmp, Tmp2); 1941 1942 case ISD::SADDO: 1943 case ISD::UADDO: 1944 case ISD::SSUBO: 1945 case ISD::USUBO: 1946 case ISD::SMULO: 1947 case ISD::UMULO: 1948 if (Op.getResNo() != 1) 1949 break; 1950 // The boolean result conforms to getBooleanContents. Fall through. 1951 case ISD::SETCC: 1952 // If setcc returns 0/-1, all bits are sign bits. 1953 if (TLI.getBooleanContents() == 1954 TargetLowering::ZeroOrNegativeOneBooleanContent) 1955 return VTBits; 1956 break; 1957 case ISD::ROTL: 1958 case ISD::ROTR: 1959 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1960 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 1961 1962 // Handle rotate right by N like a rotate left by 32-N. 1963 if (Op.getOpcode() == ISD::ROTR) 1964 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1965 1966 // If we aren't rotating out all of the known-in sign bits, return the 1967 // number that are left. This handles rotl(sext(x), 1) for example. 1968 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1969 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1970 } 1971 break; 1972 case ISD::ADD: 1973 // Add can have at most one carry bit. Thus we know that the output 1974 // is, at worst, one more bit than the inputs. 1975 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1976 if (Tmp == 1) return 1; // Early out. 1977 1978 // Special case decrementing a value (ADD X, -1): 1979 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 1980 if (CRHS->isAllOnesValue()) { 1981 APInt KnownZero, KnownOne; 1982 APInt Mask = APInt::getAllOnesValue(VTBits); 1983 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1984 1985 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1986 // sign bits set. 1987 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1988 return VTBits; 1989 1990 // If we are subtracting one from a positive number, there is no carry 1991 // out of the result. 1992 if (KnownZero.isNegative()) 1993 return Tmp; 1994 } 1995 1996 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1997 if (Tmp2 == 1) return 1; 1998 return std::min(Tmp, Tmp2)-1; 1999 break; 2000 2001 case ISD::SUB: 2002 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2003 if (Tmp2 == 1) return 1; 2004 2005 // Handle NEG. 2006 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 2007 if (CLHS->isNullValue()) { 2008 APInt KnownZero, KnownOne; 2009 APInt Mask = APInt::getAllOnesValue(VTBits); 2010 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 2011 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2012 // sign bits set. 2013 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2014 return VTBits; 2015 2016 // If the input is known to be positive (the sign bit is known clear), 2017 // the output of the NEG has the same number of sign bits as the input. 2018 if (KnownZero.isNegative()) 2019 return Tmp2; 2020 2021 // Otherwise, we treat this like a SUB. 2022 } 2023 2024 // Sub can have at most one carry bit. Thus we know that the output 2025 // is, at worst, one more bit than the inputs. 2026 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2027 if (Tmp == 1) return 1; // Early out. 2028 return std::min(Tmp, Tmp2)-1; 2029 break; 2030 case ISD::TRUNCATE: 2031 // FIXME: it's tricky to do anything useful for this, but it is an important 2032 // case for targets like X86. 2033 break; 2034 } 2035 2036 // Handle LOADX separately here. EXTLOAD case will fallthrough. 2037 if (Op.getOpcode() == ISD::LOAD) { 2038 LoadSDNode *LD = cast<LoadSDNode>(Op); 2039 unsigned ExtType = LD->getExtensionType(); 2040 switch (ExtType) { 2041 default: break; 2042 case ISD::SEXTLOAD: // '17' bits known 2043 Tmp = LD->getMemoryVT().getSizeInBits(); 2044 return VTBits-Tmp+1; 2045 case ISD::ZEXTLOAD: // '16' bits known 2046 Tmp = LD->getMemoryVT().getSizeInBits(); 2047 return VTBits-Tmp; 2048 } 2049 } 2050 2051 // Allow the target to implement this method for its nodes. 2052 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2053 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2054 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2055 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2056 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2057 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2058 } 2059 2060 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2061 // use this information. 2062 APInt KnownZero, KnownOne; 2063 APInt Mask = APInt::getAllOnesValue(VTBits); 2064 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2065 2066 if (KnownZero.isNegative()) { // sign bit is 0 2067 Mask = KnownZero; 2068 } else if (KnownOne.isNegative()) { // sign bit is 1; 2069 Mask = KnownOne; 2070 } else { 2071 // Nothing known. 2072 return FirstAnswer; 2073 } 2074 2075 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2076 // the number of identical bits in the top of the input value. 2077 Mask = ~Mask; 2078 Mask <<= Mask.getBitWidth()-VTBits; 2079 // Return # leading zeros. We use 'min' here in case Val was zero before 2080 // shifting. We don't want to return '64' as for an i32 "0". 2081 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2082} 2083 2084 2085bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2086 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2087 if (!GA) return false; 2088 if (GA->getOffset() != 0) return false; 2089 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2090 if (!GV) return false; 2091 MachineModuleInfo *MMI = getMachineModuleInfo(); 2092 return MMI && MMI->hasDebugInfo(); 2093} 2094 2095 2096/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2097/// element of the result of the vector shuffle. 2098SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 2099 MVT VT = N->getValueType(0); 2100 DebugLoc dl = N->getDebugLoc(); 2101 SDValue PermMask = N->getOperand(2); 2102 SDValue Idx = PermMask.getOperand(i); 2103 if (Idx.getOpcode() == ISD::UNDEF) 2104 return getUNDEF(VT.getVectorElementType()); 2105 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 2106 unsigned NumElems = PermMask.getNumOperands(); 2107 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2108 Index %= NumElems; 2109 2110 if (V.getOpcode() == ISD::BIT_CONVERT) { 2111 V = V.getOperand(0); 2112 MVT VVT = V.getValueType(); 2113 if (!VVT.isVector() || VVT.getVectorNumElements() != NumElems) 2114 return SDValue(); 2115 } 2116 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2117 return (Index == 0) ? V.getOperand(0) 2118 : getUNDEF(VT.getVectorElementType()); 2119 if (V.getOpcode() == ISD::BUILD_VECTOR) 2120 return V.getOperand(Index); 2121 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 2122 return getShuffleScalarElt(V.getNode(), Index); 2123 return SDValue(); 2124} 2125 2126 2127/// getNode - Gets or creates the specified node. 2128/// 2129SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) { 2130 FoldingSetNodeID ID; 2131 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2132 void *IP = 0; 2133 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2134 return SDValue(E, 0); 2135 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2136 new (N) SDNode(Opcode, DL, SDNode::getSDVTList(VT)); 2137 CSEMap.InsertNode(N, IP); 2138 2139 AllNodes.push_back(N); 2140#ifndef NDEBUG 2141 VerifyNode(N); 2142#endif 2143 return SDValue(N, 0); 2144} 2145 2146SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 2147 MVT VT, SDValue Operand) { 2148 // Constant fold unary operations with an integer constant operand. 2149 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2150 const APInt &Val = C->getAPIntValue(); 2151 unsigned BitWidth = VT.getSizeInBits(); 2152 switch (Opcode) { 2153 default: break; 2154 case ISD::SIGN_EXTEND: 2155 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2156 case ISD::ANY_EXTEND: 2157 case ISD::ZERO_EXTEND: 2158 case ISD::TRUNCATE: 2159 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2160 case ISD::UINT_TO_FP: 2161 case ISD::SINT_TO_FP: { 2162 const uint64_t zero[] = {0, 0}; 2163 // No compile time operations on this type. 2164 if (VT==MVT::ppcf128) 2165 break; 2166 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2167 (void)apf.convertFromAPInt(Val, 2168 Opcode==ISD::SINT_TO_FP, 2169 APFloat::rmNearestTiesToEven); 2170 return getConstantFP(apf, VT); 2171 } 2172 case ISD::BIT_CONVERT: 2173 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2174 return getConstantFP(Val.bitsToFloat(), VT); 2175 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2176 return getConstantFP(Val.bitsToDouble(), VT); 2177 break; 2178 case ISD::BSWAP: 2179 return getConstant(Val.byteSwap(), VT); 2180 case ISD::CTPOP: 2181 return getConstant(Val.countPopulation(), VT); 2182 case ISD::CTLZ: 2183 return getConstant(Val.countLeadingZeros(), VT); 2184 case ISD::CTTZ: 2185 return getConstant(Val.countTrailingZeros(), VT); 2186 } 2187 } 2188 2189 // Constant fold unary operations with a floating point constant operand. 2190 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2191 APFloat V = C->getValueAPF(); // make copy 2192 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2193 switch (Opcode) { 2194 case ISD::FNEG: 2195 V.changeSign(); 2196 return getConstantFP(V, VT); 2197 case ISD::FABS: 2198 V.clearSign(); 2199 return getConstantFP(V, VT); 2200 case ISD::FP_ROUND: 2201 case ISD::FP_EXTEND: { 2202 bool ignored; 2203 // This can return overflow, underflow, or inexact; we don't care. 2204 // FIXME need to be more flexible about rounding mode. 2205 (void)V.convert(*MVTToAPFloatSemantics(VT), 2206 APFloat::rmNearestTiesToEven, &ignored); 2207 return getConstantFP(V, VT); 2208 } 2209 case ISD::FP_TO_SINT: 2210 case ISD::FP_TO_UINT: { 2211 integerPart x; 2212 bool ignored; 2213 assert(integerPartWidth >= 64); 2214 // FIXME need to be more flexible about rounding mode. 2215 APFloat::opStatus s = V.convertToInteger(&x, 64U, 2216 Opcode==ISD::FP_TO_SINT, 2217 APFloat::rmTowardZero, &ignored); 2218 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2219 break; 2220 return getConstant(x, VT); 2221 } 2222 case ISD::BIT_CONVERT: 2223 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2224 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2225 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2226 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2227 break; 2228 } 2229 } 2230 } 2231 2232 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2233 switch (Opcode) { 2234 case ISD::TokenFactor: 2235 case ISD::MERGE_VALUES: 2236 case ISD::CONCAT_VECTORS: 2237 return Operand; // Factor, merge or concat of one node? No need. 2238 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2239 case ISD::FP_EXTEND: 2240 assert(VT.isFloatingPoint() && 2241 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2242 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2243 if (Operand.getOpcode() == ISD::UNDEF) 2244 return getUNDEF(VT); 2245 break; 2246 case ISD::SIGN_EXTEND: 2247 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2248 "Invalid SIGN_EXTEND!"); 2249 if (Operand.getValueType() == VT) return Operand; // noop extension 2250 assert(Operand.getValueType().bitsLT(VT) 2251 && "Invalid sext node, dst < src!"); 2252 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2253 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2254 break; 2255 case ISD::ZERO_EXTEND: 2256 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2257 "Invalid ZERO_EXTEND!"); 2258 if (Operand.getValueType() == VT) return Operand; // noop extension 2259 assert(Operand.getValueType().bitsLT(VT) 2260 && "Invalid zext node, dst < src!"); 2261 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2262 return getNode(ISD::ZERO_EXTEND, DL, VT, 2263 Operand.getNode()->getOperand(0)); 2264 break; 2265 case ISD::ANY_EXTEND: 2266 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2267 "Invalid ANY_EXTEND!"); 2268 if (Operand.getValueType() == VT) return Operand; // noop extension 2269 assert(Operand.getValueType().bitsLT(VT) 2270 && "Invalid anyext node, dst < src!"); 2271 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2272 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2273 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2274 break; 2275 case ISD::TRUNCATE: 2276 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2277 "Invalid TRUNCATE!"); 2278 if (Operand.getValueType() == VT) return Operand; // noop truncate 2279 assert(Operand.getValueType().bitsGT(VT) 2280 && "Invalid truncate node, src < dst!"); 2281 if (OpOpcode == ISD::TRUNCATE) 2282 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2283 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2284 OpOpcode == ISD::ANY_EXTEND) { 2285 // If the source is smaller than the dest, we still need an extend. 2286 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2287 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2288 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2289 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2290 else 2291 return Operand.getNode()->getOperand(0); 2292 } 2293 break; 2294 case ISD::BIT_CONVERT: 2295 // Basic sanity checking. 2296 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2297 && "Cannot BIT_CONVERT between types of different sizes!"); 2298 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2299 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2300 return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0)); 2301 if (OpOpcode == ISD::UNDEF) 2302 return getUNDEF(VT); 2303 break; 2304 case ISD::SCALAR_TO_VECTOR: 2305 assert(VT.isVector() && !Operand.getValueType().isVector() && 2306 VT.getVectorElementType() == Operand.getValueType() && 2307 "Illegal SCALAR_TO_VECTOR node!"); 2308 if (OpOpcode == ISD::UNDEF) 2309 return getUNDEF(VT); 2310 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2311 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2312 isa<ConstantSDNode>(Operand.getOperand(1)) && 2313 Operand.getConstantOperandVal(1) == 0 && 2314 Operand.getOperand(0).getValueType() == VT) 2315 return Operand.getOperand(0); 2316 break; 2317 case ISD::FNEG: 2318 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 2319 if (UnsafeFPMath && OpOpcode == ISD::FSUB) 2320 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1), 2321 Operand.getNode()->getOperand(0)); 2322 if (OpOpcode == ISD::FNEG) // --X -> X 2323 return Operand.getNode()->getOperand(0); 2324 break; 2325 case ISD::FABS: 2326 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2327 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0)); 2328 break; 2329 } 2330 2331 SDNode *N; 2332 SDVTList VTs = getVTList(VT); 2333 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2334 FoldingSetNodeID ID; 2335 SDValue Ops[1] = { Operand }; 2336 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2337 void *IP = 0; 2338 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2339 return SDValue(E, 0); 2340 N = NodeAllocator.Allocate<UnarySDNode>(); 2341 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2342 CSEMap.InsertNode(N, IP); 2343 } else { 2344 N = NodeAllocator.Allocate<UnarySDNode>(); 2345 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2346 } 2347 2348 AllNodes.push_back(N); 2349#ifndef NDEBUG 2350 VerifyNode(N); 2351#endif 2352 return SDValue(N, 0); 2353} 2354 2355SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2356 MVT VT, 2357 ConstantSDNode *Cst1, 2358 ConstantSDNode *Cst2) { 2359 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2360 2361 switch (Opcode) { 2362 case ISD::ADD: return getConstant(C1 + C2, VT); 2363 case ISD::SUB: return getConstant(C1 - C2, VT); 2364 case ISD::MUL: return getConstant(C1 * C2, VT); 2365 case ISD::UDIV: 2366 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2367 break; 2368 case ISD::UREM: 2369 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2370 break; 2371 case ISD::SDIV: 2372 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2373 break; 2374 case ISD::SREM: 2375 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2376 break; 2377 case ISD::AND: return getConstant(C1 & C2, VT); 2378 case ISD::OR: return getConstant(C1 | C2, VT); 2379 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2380 case ISD::SHL: return getConstant(C1 << C2, VT); 2381 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2382 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2383 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2384 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2385 default: break; 2386 } 2387 2388 return SDValue(); 2389} 2390 2391SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2392 SDValue N1, SDValue N2) { 2393 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2394 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2395 switch (Opcode) { 2396 default: break; 2397 case ISD::TokenFactor: 2398 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2399 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2400 // Fold trivial token factors. 2401 if (N1.getOpcode() == ISD::EntryToken) return N2; 2402 if (N2.getOpcode() == ISD::EntryToken) return N1; 2403 if (N1 == N2) return N1; 2404 break; 2405 case ISD::CONCAT_VECTORS: 2406 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2407 // one big BUILD_VECTOR. 2408 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2409 N2.getOpcode() == ISD::BUILD_VECTOR) { 2410 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2411 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2412 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2413 } 2414 break; 2415 case ISD::AND: 2416 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2417 N1.getValueType() == VT && "Binary operator types must match!"); 2418 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2419 // worth handling here. 2420 if (N2C && N2C->isNullValue()) 2421 return N2; 2422 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2423 return N1; 2424 break; 2425 case ISD::OR: 2426 case ISD::XOR: 2427 case ISD::ADD: 2428 case ISD::SUB: 2429 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2430 N1.getValueType() == VT && "Binary operator types must match!"); 2431 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2432 // it's worth handling here. 2433 if (N2C && N2C->isNullValue()) 2434 return N1; 2435 break; 2436 case ISD::UDIV: 2437 case ISD::UREM: 2438 case ISD::MULHU: 2439 case ISD::MULHS: 2440 case ISD::MUL: 2441 case ISD::SDIV: 2442 case ISD::SREM: 2443 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2444 // fall through 2445 case ISD::FADD: 2446 case ISD::FSUB: 2447 case ISD::FMUL: 2448 case ISD::FDIV: 2449 case ISD::FREM: 2450 if (UnsafeFPMath) { 2451 if (Opcode == ISD::FADD) { 2452 // 0+x --> x 2453 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) 2454 if (CFP->getValueAPF().isZero()) 2455 return N2; 2456 // x+0 --> x 2457 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2458 if (CFP->getValueAPF().isZero()) 2459 return N1; 2460 } else if (Opcode == ISD::FSUB) { 2461 // x-0 --> x 2462 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2463 if (CFP->getValueAPF().isZero()) 2464 return N1; 2465 } 2466 } 2467 assert(N1.getValueType() == N2.getValueType() && 2468 N1.getValueType() == VT && "Binary operator types must match!"); 2469 break; 2470 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2471 assert(N1.getValueType() == VT && 2472 N1.getValueType().isFloatingPoint() && 2473 N2.getValueType().isFloatingPoint() && 2474 "Invalid FCOPYSIGN!"); 2475 break; 2476 case ISD::SHL: 2477 case ISD::SRA: 2478 case ISD::SRL: 2479 case ISD::ROTL: 2480 case ISD::ROTR: 2481 assert(VT == N1.getValueType() && 2482 "Shift operators return type must be the same as their first arg"); 2483 assert(VT.isInteger() && N2.getValueType().isInteger() && 2484 "Shifts only work on integers"); 2485 2486 // Always fold shifts of i1 values so the code generator doesn't need to 2487 // handle them. Since we know the size of the shift has to be less than the 2488 // size of the value, the shift/rotate count is guaranteed to be zero. 2489 if (VT == MVT::i1) 2490 return N1; 2491 break; 2492 case ISD::FP_ROUND_INREG: { 2493 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2494 assert(VT == N1.getValueType() && "Not an inreg round!"); 2495 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2496 "Cannot FP_ROUND_INREG integer types"); 2497 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2498 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2499 break; 2500 } 2501 case ISD::FP_ROUND: 2502 assert(VT.isFloatingPoint() && 2503 N1.getValueType().isFloatingPoint() && 2504 VT.bitsLE(N1.getValueType()) && 2505 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2506 if (N1.getValueType() == VT) return N1; // noop conversion. 2507 break; 2508 case ISD::AssertSext: 2509 case ISD::AssertZext: { 2510 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2511 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2512 assert(VT.isInteger() && EVT.isInteger() && 2513 "Cannot *_EXTEND_INREG FP types"); 2514 assert(EVT.bitsLE(VT) && "Not extending!"); 2515 if (VT == EVT) return N1; // noop assertion. 2516 break; 2517 } 2518 case ISD::SIGN_EXTEND_INREG: { 2519 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2520 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2521 assert(VT.isInteger() && EVT.isInteger() && 2522 "Cannot *_EXTEND_INREG FP types"); 2523 assert(EVT.bitsLE(VT) && "Not extending!"); 2524 if (EVT == VT) return N1; // Not actually extending 2525 2526 if (N1C) { 2527 APInt Val = N1C->getAPIntValue(); 2528 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2529 Val <<= Val.getBitWidth()-FromBits; 2530 Val = Val.ashr(Val.getBitWidth()-FromBits); 2531 return getConstant(Val, VT); 2532 } 2533 break; 2534 } 2535 case ISD::EXTRACT_VECTOR_ELT: 2536 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2537 if (N1.getOpcode() == ISD::UNDEF) 2538 return getUNDEF(VT); 2539 2540 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2541 // expanding copies of large vectors from registers. 2542 if (N2C && 2543 N1.getOpcode() == ISD::CONCAT_VECTORS && 2544 N1.getNumOperands() > 0) { 2545 unsigned Factor = 2546 N1.getOperand(0).getValueType().getVectorNumElements(); 2547 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, 2548 N1.getOperand(N2C->getZExtValue() / Factor), 2549 getConstant(N2C->getZExtValue() % Factor, 2550 N2.getValueType())); 2551 } 2552 2553 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2554 // expanding large vector constants. 2555 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) 2556 return N1.getOperand(N2C->getZExtValue()); 2557 2558 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2559 // operations are lowered to scalars. 2560 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2561 // If the indices are the same, return the inserted element. 2562 if (N1.getOperand(2) == N2) 2563 return N1.getOperand(1); 2564 // If the indices are known different, extract the element from 2565 // the original vector. 2566 else if (isa<ConstantSDNode>(N1.getOperand(2)) && 2567 isa<ConstantSDNode>(N2)) 2568 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2); 2569 } 2570 break; 2571 case ISD::EXTRACT_ELEMENT: 2572 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2573 assert(!N1.getValueType().isVector() && !VT.isVector() && 2574 (N1.getValueType().isInteger() == VT.isInteger()) && 2575 "Wrong types for EXTRACT_ELEMENT!"); 2576 2577 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2578 // 64-bit integers into 32-bit parts. Instead of building the extract of 2579 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2580 if (N1.getOpcode() == ISD::BUILD_PAIR) 2581 return N1.getOperand(N2C->getZExtValue()); 2582 2583 // EXTRACT_ELEMENT of a constant int is also very common. 2584 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2585 unsigned ElementSize = VT.getSizeInBits(); 2586 unsigned Shift = ElementSize * N2C->getZExtValue(); 2587 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2588 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2589 } 2590 break; 2591 case ISD::EXTRACT_SUBVECTOR: 2592 if (N1.getValueType() == VT) // Trivial extraction. 2593 return N1; 2594 break; 2595 } 2596 2597 if (N1C) { 2598 if (N2C) { 2599 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2600 if (SV.getNode()) return SV; 2601 } else { // Cannonicalize constant to RHS if commutative 2602 if (isCommutativeBinOp(Opcode)) { 2603 std::swap(N1C, N2C); 2604 std::swap(N1, N2); 2605 } 2606 } 2607 } 2608 2609 // Constant fold FP operations. 2610 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2611 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2612 if (N1CFP) { 2613 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2614 // Cannonicalize constant to RHS if commutative 2615 std::swap(N1CFP, N2CFP); 2616 std::swap(N1, N2); 2617 } else if (N2CFP && VT != MVT::ppcf128) { 2618 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2619 APFloat::opStatus s; 2620 switch (Opcode) { 2621 case ISD::FADD: 2622 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2623 if (s != APFloat::opInvalidOp) 2624 return getConstantFP(V1, VT); 2625 break; 2626 case ISD::FSUB: 2627 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2628 if (s!=APFloat::opInvalidOp) 2629 return getConstantFP(V1, VT); 2630 break; 2631 case ISD::FMUL: 2632 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2633 if (s!=APFloat::opInvalidOp) 2634 return getConstantFP(V1, VT); 2635 break; 2636 case ISD::FDIV: 2637 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2638 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2639 return getConstantFP(V1, VT); 2640 break; 2641 case ISD::FREM : 2642 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2643 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2644 return getConstantFP(V1, VT); 2645 break; 2646 case ISD::FCOPYSIGN: 2647 V1.copySign(V2); 2648 return getConstantFP(V1, VT); 2649 default: break; 2650 } 2651 } 2652 } 2653 2654 // Canonicalize an UNDEF to the RHS, even over a constant. 2655 if (N1.getOpcode() == ISD::UNDEF) { 2656 if (isCommutativeBinOp(Opcode)) { 2657 std::swap(N1, N2); 2658 } else { 2659 switch (Opcode) { 2660 case ISD::FP_ROUND_INREG: 2661 case ISD::SIGN_EXTEND_INREG: 2662 case ISD::SUB: 2663 case ISD::FSUB: 2664 case ISD::FDIV: 2665 case ISD::FREM: 2666 case ISD::SRA: 2667 return N1; // fold op(undef, arg2) -> undef 2668 case ISD::UDIV: 2669 case ISD::SDIV: 2670 case ISD::UREM: 2671 case ISD::SREM: 2672 case ISD::SRL: 2673 case ISD::SHL: 2674 if (!VT.isVector()) 2675 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2676 // For vectors, we can't easily build an all zero vector, just return 2677 // the LHS. 2678 return N2; 2679 } 2680 } 2681 } 2682 2683 // Fold a bunch of operators when the RHS is undef. 2684 if (N2.getOpcode() == ISD::UNDEF) { 2685 switch (Opcode) { 2686 case ISD::XOR: 2687 if (N1.getOpcode() == ISD::UNDEF) 2688 // Handle undef ^ undef -> 0 special case. This is a common 2689 // idiom (misuse). 2690 return getConstant(0, VT); 2691 // fallthrough 2692 case ISD::ADD: 2693 case ISD::ADDC: 2694 case ISD::ADDE: 2695 case ISD::SUB: 2696 case ISD::FADD: 2697 case ISD::FSUB: 2698 case ISD::FMUL: 2699 case ISD::FDIV: 2700 case ISD::FREM: 2701 case ISD::UDIV: 2702 case ISD::SDIV: 2703 case ISD::UREM: 2704 case ISD::SREM: 2705 return N2; // fold op(arg1, undef) -> undef 2706 case ISD::MUL: 2707 case ISD::AND: 2708 case ISD::SRL: 2709 case ISD::SHL: 2710 if (!VT.isVector()) 2711 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2712 // For vectors, we can't easily build an all zero vector, just return 2713 // the LHS. 2714 return N1; 2715 case ISD::OR: 2716 if (!VT.isVector()) 2717 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 2718 // For vectors, we can't easily build an all one vector, just return 2719 // the LHS. 2720 return N1; 2721 case ISD::SRA: 2722 return N1; 2723 } 2724 } 2725 2726 // Memoize this node if possible. 2727 SDNode *N; 2728 SDVTList VTs = getVTList(VT); 2729 if (VT != MVT::Flag) { 2730 SDValue Ops[] = { N1, N2 }; 2731 FoldingSetNodeID ID; 2732 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2733 void *IP = 0; 2734 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2735 return SDValue(E, 0); 2736 N = NodeAllocator.Allocate<BinarySDNode>(); 2737 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2738 CSEMap.InsertNode(N, IP); 2739 } else { 2740 N = NodeAllocator.Allocate<BinarySDNode>(); 2741 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2742 } 2743 2744 AllNodes.push_back(N); 2745#ifndef NDEBUG 2746 VerifyNode(N); 2747#endif 2748 return SDValue(N, 0); 2749} 2750 2751SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2752 SDValue N1, SDValue N2, SDValue N3) { 2753 // Perform various simplifications. 2754 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2755 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2756 switch (Opcode) { 2757 case ISD::CONCAT_VECTORS: 2758 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2759 // one big BUILD_VECTOR. 2760 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2761 N2.getOpcode() == ISD::BUILD_VECTOR && 2762 N3.getOpcode() == ISD::BUILD_VECTOR) { 2763 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2764 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2765 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2766 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2767 } 2768 break; 2769 case ISD::SETCC: { 2770 // Use FoldSetCC to simplify SETCC's. 2771 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL); 2772 if (Simp.getNode()) return Simp; 2773 break; 2774 } 2775 case ISD::SELECT: 2776 if (N1C) { 2777 if (N1C->getZExtValue()) 2778 return N2; // select true, X, Y -> X 2779 else 2780 return N3; // select false, X, Y -> Y 2781 } 2782 2783 if (N2 == N3) return N2; // select C, X, X -> X 2784 break; 2785 case ISD::BRCOND: 2786 if (N2C) { 2787 if (N2C->getZExtValue()) // Unconditional branch 2788 return getNode(ISD::BR, DL, MVT::Other, N1, N3); 2789 else 2790 return N1; // Never-taken branch 2791 } 2792 break; 2793 case ISD::VECTOR_SHUFFLE: 2794 assert(N1.getValueType() == N2.getValueType() && 2795 N1.getValueType().isVector() && 2796 VT.isVector() && N3.getValueType().isVector() && 2797 N3.getOpcode() == ISD::BUILD_VECTOR && 2798 VT.getVectorNumElements() == N3.getNumOperands() && 2799 "Illegal VECTOR_SHUFFLE node!"); 2800 break; 2801 case ISD::BIT_CONVERT: 2802 // Fold bit_convert nodes from a type to themselves. 2803 if (N1.getValueType() == VT) 2804 return N1; 2805 break; 2806 } 2807 2808 // Memoize node if it doesn't produce a flag. 2809 SDNode *N; 2810 SDVTList VTs = getVTList(VT); 2811 if (VT != MVT::Flag) { 2812 SDValue Ops[] = { N1, N2, N3 }; 2813 FoldingSetNodeID ID; 2814 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2815 void *IP = 0; 2816 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2817 return SDValue(E, 0); 2818 N = NodeAllocator.Allocate<TernarySDNode>(); 2819 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2820 CSEMap.InsertNode(N, IP); 2821 } else { 2822 N = NodeAllocator.Allocate<TernarySDNode>(); 2823 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2824 } 2825 AllNodes.push_back(N); 2826#ifndef NDEBUG 2827 VerifyNode(N); 2828#endif 2829 return SDValue(N, 0); 2830} 2831 2832SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2833 SDValue N1, SDValue N2, SDValue N3, 2834 SDValue N4) { 2835 SDValue Ops[] = { N1, N2, N3, N4 }; 2836 return getNode(Opcode, DL, VT, Ops, 4); 2837} 2838 2839SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2840 SDValue N1, SDValue N2, SDValue N3, 2841 SDValue N4, SDValue N5) { 2842 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2843 return getNode(Opcode, DL, VT, Ops, 5); 2844} 2845 2846/// getMemsetValue - Vectorized representation of the memset value 2847/// operand. 2848static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG, 2849 DebugLoc dl) { 2850 unsigned NumBits = VT.isVector() ? 2851 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2852 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2853 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2854 unsigned Shift = 8; 2855 for (unsigned i = NumBits; i > 8; i >>= 1) { 2856 Val = (Val << Shift) | Val; 2857 Shift <<= 1; 2858 } 2859 if (VT.isInteger()) 2860 return DAG.getConstant(Val, VT); 2861 return DAG.getConstantFP(APFloat(Val), VT); 2862 } 2863 2864 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2865 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); 2866 unsigned Shift = 8; 2867 for (unsigned i = NumBits; i > 8; i >>= 1) { 2868 Value = DAG.getNode(ISD::OR, dl, VT, 2869 DAG.getNode(ISD::SHL, dl, VT, Value, 2870 DAG.getConstant(Shift, 2871 TLI.getShiftAmountTy())), 2872 Value); 2873 Shift <<= 1; 2874 } 2875 2876 return Value; 2877} 2878 2879/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2880/// used when a memcpy is turned into a memset when the source is a constant 2881/// string ptr. 2882static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, 2883 const TargetLowering &TLI, 2884 std::string &Str, unsigned Offset) { 2885 // Handle vector with all elements zero. 2886 if (Str.empty()) { 2887 if (VT.isInteger()) 2888 return DAG.getConstant(0, VT); 2889 unsigned NumElts = VT.getVectorNumElements(); 2890 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2891 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 2892 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2893 } 2894 2895 assert(!VT.isVector() && "Can't handle vector type here!"); 2896 unsigned NumBits = VT.getSizeInBits(); 2897 unsigned MSB = NumBits / 8; 2898 uint64_t Val = 0; 2899 if (TLI.isLittleEndian()) 2900 Offset = Offset + MSB - 1; 2901 for (unsigned i = 0; i != MSB; ++i) { 2902 Val = (Val << 8) | (unsigned char)Str[Offset]; 2903 Offset += TLI.isLittleEndian() ? -1 : 1; 2904 } 2905 return DAG.getConstant(Val, VT); 2906} 2907 2908/// getMemBasePlusOffset - Returns base and offset node for the 2909/// 2910static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2911 SelectionDAG &DAG) { 2912 MVT VT = Base.getValueType(); 2913 return DAG.getNode(ISD::ADD, Base.getDebugLoc(), 2914 VT, Base, DAG.getConstant(Offset, VT)); 2915} 2916 2917/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2918/// 2919static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2920 unsigned SrcDelta = 0; 2921 GlobalAddressSDNode *G = NULL; 2922 if (Src.getOpcode() == ISD::GlobalAddress) 2923 G = cast<GlobalAddressSDNode>(Src); 2924 else if (Src.getOpcode() == ISD::ADD && 2925 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2926 Src.getOperand(1).getOpcode() == ISD::Constant) { 2927 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2928 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 2929 } 2930 if (!G) 2931 return false; 2932 2933 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2934 if (GV) { 2935 const char *SI = GetConstantStringInfo(GV, SrcDelta, false); 2936 Str = (SI ? SI : ""); 2937 if (!Str.empty()) return true; 2938 } 2939 2940 return false; 2941} 2942 2943/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2944/// to replace the memset / memcpy is below the threshold. It also returns the 2945/// types of the sequence of memory ops to perform memset / memcpy. 2946static 2947bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 2948 SDValue Dst, SDValue Src, 2949 unsigned Limit, uint64_t Size, unsigned &Align, 2950 std::string &Str, bool &isSrcStr, 2951 SelectionDAG &DAG, 2952 const TargetLowering &TLI) { 2953 isSrcStr = isMemSrcFromString(Src, Str); 2954 bool isSrcConst = isa<ConstantSDNode>(Src); 2955 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 2956 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 2957 if (VT != MVT::iAny) { 2958 unsigned NewAlign = (unsigned) 2959 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 2960 // If source is a string constant, this will require an unaligned load. 2961 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 2962 if (Dst.getOpcode() != ISD::FrameIndex) { 2963 // Can't change destination alignment. It requires a unaligned store. 2964 if (AllowUnalign) 2965 VT = MVT::iAny; 2966 } else { 2967 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 2968 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2969 if (MFI->isFixedObjectIndex(FI)) { 2970 // Can't change destination alignment. It requires a unaligned store. 2971 if (AllowUnalign) 2972 VT = MVT::iAny; 2973 } else { 2974 // Give the stack frame object a larger alignment if needed. 2975 if (MFI->getObjectAlignment(FI) < NewAlign) 2976 MFI->setObjectAlignment(FI, NewAlign); 2977 Align = NewAlign; 2978 } 2979 } 2980 } 2981 } 2982 2983 if (VT == MVT::iAny) { 2984 if (AllowUnalign) { 2985 VT = MVT::i64; 2986 } else { 2987 switch (Align & 7) { 2988 case 0: VT = MVT::i64; break; 2989 case 4: VT = MVT::i32; break; 2990 case 2: VT = MVT::i16; break; 2991 default: VT = MVT::i8; break; 2992 } 2993 } 2994 2995 MVT LVT = MVT::i64; 2996 while (!TLI.isTypeLegal(LVT)) 2997 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 2998 assert(LVT.isInteger()); 2999 3000 if (VT.bitsGT(LVT)) 3001 VT = LVT; 3002 } 3003 3004 unsigned NumMemOps = 0; 3005 while (Size != 0) { 3006 unsigned VTSize = VT.getSizeInBits() / 8; 3007 while (VTSize > Size) { 3008 // For now, only use non-vector load / store's for the left-over pieces. 3009 if (VT.isVector()) { 3010 VT = MVT::i64; 3011 while (!TLI.isTypeLegal(VT)) 3012 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3013 VTSize = VT.getSizeInBits() / 8; 3014 } else { 3015 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3016 VTSize >>= 1; 3017 } 3018 } 3019 3020 if (++NumMemOps > Limit) 3021 return false; 3022 MemOps.push_back(VT); 3023 Size -= VTSize; 3024 } 3025 3026 return true; 3027} 3028 3029static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3030 SDValue Chain, SDValue Dst, 3031 SDValue Src, uint64_t Size, 3032 unsigned Align, bool AlwaysInline, 3033 const Value *DstSV, uint64_t DstSVOff, 3034 const Value *SrcSV, uint64_t SrcSVOff){ 3035 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3036 3037 // Expand memcpy to a series of load and store ops if the size operand falls 3038 // below a certain threshold. 3039 std::vector<MVT> MemOps; 3040 uint64_t Limit = -1ULL; 3041 if (!AlwaysInline) 3042 Limit = TLI.getMaxStoresPerMemcpy(); 3043 unsigned DstAlign = Align; // Destination alignment can change. 3044 std::string Str; 3045 bool CopyFromStr; 3046 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3047 Str, CopyFromStr, DAG, TLI)) 3048 return SDValue(); 3049 3050 3051 bool isZeroStr = CopyFromStr && Str.empty(); 3052 SmallVector<SDValue, 8> OutChains; 3053 unsigned NumMemOps = MemOps.size(); 3054 uint64_t SrcOff = 0, DstOff = 0; 3055 for (unsigned i = 0; i < NumMemOps; i++) { 3056 MVT VT = MemOps[i]; 3057 unsigned VTSize = VT.getSizeInBits() / 8; 3058 SDValue Value, Store; 3059 3060 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 3061 // It's unlikely a store of a vector immediate can be done in a single 3062 // instruction. It would require a load from a constantpool first. 3063 // We also handle store a vector with all zero's. 3064 // FIXME: Handle other cases where store of vector immediate is done in 3065 // a single instruction. 3066 Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff); 3067 Store = DAG.getStore(Chain, dl, Value, 3068 getMemBasePlusOffset(Dst, DstOff, DAG), 3069 DstSV, DstSVOff + DstOff, false, DstAlign); 3070 } else { 3071 Value = DAG.getLoad(VT, dl, Chain, 3072 getMemBasePlusOffset(Src, SrcOff, DAG), 3073 SrcSV, SrcSVOff + SrcOff, false, Align); 3074 Store = DAG.getStore(Chain, dl, Value, 3075 getMemBasePlusOffset(Dst, DstOff, DAG), 3076 DstSV, DstSVOff + DstOff, false, DstAlign); 3077 } 3078 OutChains.push_back(Store); 3079 SrcOff += VTSize; 3080 DstOff += VTSize; 3081 } 3082 3083 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3084 &OutChains[0], OutChains.size()); 3085} 3086 3087static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3088 SDValue Chain, SDValue Dst, 3089 SDValue Src, uint64_t Size, 3090 unsigned Align, bool AlwaysInline, 3091 const Value *DstSV, uint64_t DstSVOff, 3092 const Value *SrcSV, uint64_t SrcSVOff){ 3093 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3094 3095 // Expand memmove to a series of load and store ops if the size operand falls 3096 // below a certain threshold. 3097 std::vector<MVT> MemOps; 3098 uint64_t Limit = -1ULL; 3099 if (!AlwaysInline) 3100 Limit = TLI.getMaxStoresPerMemmove(); 3101 unsigned DstAlign = Align; // Destination alignment can change. 3102 std::string Str; 3103 bool CopyFromStr; 3104 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3105 Str, CopyFromStr, DAG, TLI)) 3106 return SDValue(); 3107 3108 uint64_t SrcOff = 0, DstOff = 0; 3109 3110 SmallVector<SDValue, 8> LoadValues; 3111 SmallVector<SDValue, 8> LoadChains; 3112 SmallVector<SDValue, 8> OutChains; 3113 unsigned NumMemOps = MemOps.size(); 3114 for (unsigned i = 0; i < NumMemOps; i++) { 3115 MVT VT = MemOps[i]; 3116 unsigned VTSize = VT.getSizeInBits() / 8; 3117 SDValue Value, Store; 3118 3119 Value = DAG.getLoad(VT, dl, Chain, 3120 getMemBasePlusOffset(Src, SrcOff, DAG), 3121 SrcSV, SrcSVOff + SrcOff, false, Align); 3122 LoadValues.push_back(Value); 3123 LoadChains.push_back(Value.getValue(1)); 3124 SrcOff += VTSize; 3125 } 3126 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3127 &LoadChains[0], LoadChains.size()); 3128 OutChains.clear(); 3129 for (unsigned i = 0; i < NumMemOps; i++) { 3130 MVT VT = MemOps[i]; 3131 unsigned VTSize = VT.getSizeInBits() / 8; 3132 SDValue Value, Store; 3133 3134 Store = DAG.getStore(Chain, dl, LoadValues[i], 3135 getMemBasePlusOffset(Dst, DstOff, DAG), 3136 DstSV, DstSVOff + DstOff, false, DstAlign); 3137 OutChains.push_back(Store); 3138 DstOff += VTSize; 3139 } 3140 3141 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3142 &OutChains[0], OutChains.size()); 3143} 3144 3145static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, 3146 SDValue Chain, SDValue Dst, 3147 SDValue Src, uint64_t Size, 3148 unsigned Align, 3149 const Value *DstSV, uint64_t DstSVOff) { 3150 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3151 3152 // Expand memset to a series of load/store ops if the size operand 3153 // falls below a certain threshold. 3154 std::vector<MVT> MemOps; 3155 std::string Str; 3156 bool CopyFromStr; 3157 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3158 Size, Align, Str, CopyFromStr, DAG, TLI)) 3159 return SDValue(); 3160 3161 SmallVector<SDValue, 8> OutChains; 3162 uint64_t DstOff = 0; 3163 3164 unsigned NumMemOps = MemOps.size(); 3165 for (unsigned i = 0; i < NumMemOps; i++) { 3166 MVT VT = MemOps[i]; 3167 unsigned VTSize = VT.getSizeInBits() / 8; 3168 SDValue Value = getMemsetValue(Src, VT, DAG, dl); 3169 SDValue Store = DAG.getStore(Chain, dl, Value, 3170 getMemBasePlusOffset(Dst, DstOff, DAG), 3171 DstSV, DstSVOff + DstOff); 3172 OutChains.push_back(Store); 3173 DstOff += VTSize; 3174 } 3175 3176 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3177 &OutChains[0], OutChains.size()); 3178} 3179 3180SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, 3181 SDValue Src, SDValue Size, 3182 unsigned Align, bool AlwaysInline, 3183 const Value *DstSV, uint64_t DstSVOff, 3184 const Value *SrcSV, uint64_t SrcSVOff) { 3185 3186 // Check to see if we should lower the memcpy to loads and stores first. 3187 // For cases within the target-specified limits, this is the best choice. 3188 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3189 if (ConstantSize) { 3190 // Memcpy with size zero? Just return the original chain. 3191 if (ConstantSize->isNullValue()) 3192 return Chain; 3193 3194 SDValue Result = 3195 getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3196 ConstantSize->getZExtValue(), 3197 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3198 if (Result.getNode()) 3199 return Result; 3200 } 3201 3202 // Then check to see if we should lower the memcpy with target-specific 3203 // code. If the target chooses to do this, this is the next best. 3204 SDValue Result = 3205 TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align, 3206 AlwaysInline, 3207 DstSV, DstSVOff, SrcSV, SrcSVOff); 3208 if (Result.getNode()) 3209 return Result; 3210 3211 // If we really need inline code and the target declined to provide it, 3212 // use a (potentially long) sequence of loads and stores. 3213 if (AlwaysInline) { 3214 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3215 return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3216 ConstantSize->getZExtValue(), Align, true, 3217 DstSV, DstSVOff, SrcSV, SrcSVOff); 3218 } 3219 3220 // Emit a library call. 3221 TargetLowering::ArgListTy Args; 3222 TargetLowering::ArgListEntry Entry; 3223 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3224 Entry.Node = Dst; Args.push_back(Entry); 3225 Entry.Node = Src; Args.push_back(Entry); 3226 Entry.Node = Size; Args.push_back(Entry); 3227 // FIXME: pass in DebugLoc 3228 std::pair<SDValue,SDValue> CallResult = 3229 TLI.LowerCallTo(Chain, Type::VoidTy, 3230 false, false, false, false, CallingConv::C, false, 3231 getExternalSymbol("memcpy", TLI.getPointerTy()), 3232 Args, *this, dl); 3233 return CallResult.second; 3234} 3235 3236SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, 3237 SDValue Src, SDValue Size, 3238 unsigned Align, 3239 const Value *DstSV, uint64_t DstSVOff, 3240 const Value *SrcSV, uint64_t SrcSVOff) { 3241 3242 // Check to see if we should lower the memmove to loads and stores first. 3243 // For cases within the target-specified limits, this is the best choice. 3244 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3245 if (ConstantSize) { 3246 // Memmove with size zero? Just return the original chain. 3247 if (ConstantSize->isNullValue()) 3248 return Chain; 3249 3250 SDValue Result = 3251 getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src, 3252 ConstantSize->getZExtValue(), 3253 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3254 if (Result.getNode()) 3255 return Result; 3256 } 3257 3258 // Then check to see if we should lower the memmove with target-specific 3259 // code. If the target chooses to do this, this is the next best. 3260 SDValue Result = 3261 TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align, 3262 DstSV, DstSVOff, SrcSV, SrcSVOff); 3263 if (Result.getNode()) 3264 return Result; 3265 3266 // Emit a library call. 3267 TargetLowering::ArgListTy Args; 3268 TargetLowering::ArgListEntry Entry; 3269 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3270 Entry.Node = Dst; Args.push_back(Entry); 3271 Entry.Node = Src; Args.push_back(Entry); 3272 Entry.Node = Size; Args.push_back(Entry); 3273 // FIXME: pass in DebugLoc 3274 std::pair<SDValue,SDValue> CallResult = 3275 TLI.LowerCallTo(Chain, Type::VoidTy, 3276 false, false, false, false, CallingConv::C, false, 3277 getExternalSymbol("memmove", TLI.getPointerTy()), 3278 Args, *this, dl); 3279 return CallResult.second; 3280} 3281 3282SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, 3283 SDValue Src, SDValue Size, 3284 unsigned Align, 3285 const Value *DstSV, uint64_t DstSVOff) { 3286 3287 // Check to see if we should lower the memset to stores first. 3288 // For cases within the target-specified limits, this is the best choice. 3289 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3290 if (ConstantSize) { 3291 // Memset with size zero? Just return the original chain. 3292 if (ConstantSize->isNullValue()) 3293 return Chain; 3294 3295 SDValue Result = 3296 getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), 3297 Align, DstSV, DstSVOff); 3298 if (Result.getNode()) 3299 return Result; 3300 } 3301 3302 // Then check to see if we should lower the memset with target-specific 3303 // code. If the target chooses to do this, this is the next best. 3304 SDValue Result = 3305 TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align, 3306 DstSV, DstSVOff); 3307 if (Result.getNode()) 3308 return Result; 3309 3310 // Emit a library call. 3311 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3312 TargetLowering::ArgListTy Args; 3313 TargetLowering::ArgListEntry Entry; 3314 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3315 Args.push_back(Entry); 3316 // Extend or truncate the argument to be an i32 value for the call. 3317 if (Src.getValueType().bitsGT(MVT::i32)) 3318 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src); 3319 else 3320 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); 3321 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3322 Args.push_back(Entry); 3323 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3324 Args.push_back(Entry); 3325 // FIXME: pass in DebugLoc 3326 std::pair<SDValue,SDValue> CallResult = 3327 TLI.LowerCallTo(Chain, Type::VoidTy, 3328 false, false, false, false, CallingConv::C, false, 3329 getExternalSymbol("memset", TLI.getPointerTy()), 3330 Args, *this, dl); 3331 return CallResult.second; 3332} 3333 3334SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3335 SDValue Chain, 3336 SDValue Ptr, SDValue Cmp, 3337 SDValue Swp, const Value* PtrVal, 3338 unsigned Alignment) { 3339 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); 3340 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3341 3342 MVT VT = Cmp.getValueType(); 3343 3344 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3345 Alignment = getMVTAlignment(MemVT); 3346 3347 SDVTList VTs = getVTList(VT, MVT::Other); 3348 FoldingSetNodeID ID; 3349 ID.AddInteger(MemVT.getRawBits()); 3350 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3351 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3352 void* IP = 0; 3353 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3354 return SDValue(E, 0); 3355 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3356 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3357 Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3358 CSEMap.InsertNode(N, IP); 3359 AllNodes.push_back(N); 3360 return SDValue(N, 0); 3361} 3362 3363SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3364 SDValue Chain, 3365 SDValue Ptr, SDValue Val, 3366 const Value* PtrVal, 3367 unsigned Alignment) { 3368 assert((Opcode == ISD::ATOMIC_LOAD_ADD || 3369 Opcode == ISD::ATOMIC_LOAD_SUB || 3370 Opcode == ISD::ATOMIC_LOAD_AND || 3371 Opcode == ISD::ATOMIC_LOAD_OR || 3372 Opcode == ISD::ATOMIC_LOAD_XOR || 3373 Opcode == ISD::ATOMIC_LOAD_NAND || 3374 Opcode == ISD::ATOMIC_LOAD_MIN || 3375 Opcode == ISD::ATOMIC_LOAD_MAX || 3376 Opcode == ISD::ATOMIC_LOAD_UMIN || 3377 Opcode == ISD::ATOMIC_LOAD_UMAX || 3378 Opcode == ISD::ATOMIC_SWAP) && 3379 "Invalid Atomic Op"); 3380 3381 MVT VT = Val.getValueType(); 3382 3383 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3384 Alignment = getMVTAlignment(MemVT); 3385 3386 SDVTList VTs = getVTList(VT, MVT::Other); 3387 FoldingSetNodeID ID; 3388 ID.AddInteger(MemVT.getRawBits()); 3389 SDValue Ops[] = {Chain, Ptr, Val}; 3390 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3391 void* IP = 0; 3392 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3393 return SDValue(E, 0); 3394 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3395 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3396 Chain, Ptr, Val, PtrVal, Alignment); 3397 CSEMap.InsertNode(N, IP); 3398 AllNodes.push_back(N); 3399 return SDValue(N, 0); 3400} 3401 3402/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3403/// Allowed to return something different (and simpler) if Simplify is true. 3404SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3405 DebugLoc dl) { 3406 if (NumOps == 1) 3407 return Ops[0]; 3408 3409 SmallVector<MVT, 4> VTs; 3410 VTs.reserve(NumOps); 3411 for (unsigned i = 0; i < NumOps; ++i) 3412 VTs.push_back(Ops[i].getValueType()); 3413 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps), 3414 Ops, NumOps); 3415} 3416 3417SDValue 3418SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, 3419 const MVT *VTs, unsigned NumVTs, 3420 const SDValue *Ops, unsigned NumOps, 3421 MVT MemVT, const Value *srcValue, int SVOff, 3422 unsigned Align, bool Vol, 3423 bool ReadMem, bool WriteMem) { 3424 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps, 3425 MemVT, srcValue, SVOff, Align, Vol, 3426 ReadMem, WriteMem); 3427} 3428 3429SDValue 3430SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, 3431 const SDValue *Ops, unsigned NumOps, 3432 MVT MemVT, const Value *srcValue, int SVOff, 3433 unsigned Align, bool Vol, 3434 bool ReadMem, bool WriteMem) { 3435 // Memoize the node unless it returns a flag. 3436 MemIntrinsicSDNode *N; 3437 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3438 FoldingSetNodeID ID; 3439 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3440 void *IP = 0; 3441 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3442 return SDValue(E, 0); 3443 3444 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3445 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3446 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3447 CSEMap.InsertNode(N, IP); 3448 } else { 3449 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3450 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3451 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3452 } 3453 AllNodes.push_back(N); 3454 return SDValue(N, 0); 3455} 3456 3457SDValue 3458SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, 3459 bool IsTailCall, bool IsInreg, SDVTList VTs, 3460 const SDValue *Operands, unsigned NumOperands) { 3461 // Do not include isTailCall in the folding set profile. 3462 FoldingSetNodeID ID; 3463 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3464 ID.AddInteger(CallingConv); 3465 ID.AddInteger(IsVarArgs); 3466 void *IP = 0; 3467 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3468 // Instead of including isTailCall in the folding set, we just 3469 // set the flag of the existing node. 3470 if (!IsTailCall) 3471 cast<CallSDNode>(E)->setNotTailCall(); 3472 return SDValue(E, 0); 3473 } 3474 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3475 new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg, 3476 VTs, Operands, NumOperands); 3477 CSEMap.InsertNode(N, IP); 3478 AllNodes.push_back(N); 3479 return SDValue(N, 0); 3480} 3481 3482SDValue 3483SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, 3484 ISD::LoadExtType ExtType, MVT VT, SDValue Chain, 3485 SDValue Ptr, SDValue Offset, 3486 const Value *SV, int SVOffset, MVT EVT, 3487 bool isVolatile, unsigned Alignment) { 3488 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3489 Alignment = getMVTAlignment(VT); 3490 3491 if (VT == EVT) { 3492 ExtType = ISD::NON_EXTLOAD; 3493 } else if (ExtType == ISD::NON_EXTLOAD) { 3494 assert(VT == EVT && "Non-extending load from different memory type!"); 3495 } else { 3496 // Extending load. 3497 if (VT.isVector()) 3498 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3499 "Invalid vector extload!"); 3500 else 3501 assert(EVT.bitsLT(VT) && 3502 "Should only be an extending load, not truncating!"); 3503 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3504 "Cannot sign/zero extend a FP/Vector load!"); 3505 assert(VT.isInteger() == EVT.isInteger() && 3506 "Cannot convert from FP to Int or Int -> FP!"); 3507 } 3508 3509 bool Indexed = AM != ISD::UNINDEXED; 3510 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3511 "Unindexed load with an offset!"); 3512 3513 SDVTList VTs = Indexed ? 3514 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3515 SDValue Ops[] = { Chain, Ptr, Offset }; 3516 FoldingSetNodeID ID; 3517 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3518 ID.AddInteger(EVT.getRawBits()); 3519 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); 3520 void *IP = 0; 3521 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3522 return SDValue(E, 0); 3523 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3524 new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset, 3525 Alignment, isVolatile); 3526 CSEMap.InsertNode(N, IP); 3527 AllNodes.push_back(N); 3528 return SDValue(N, 0); 3529} 3530 3531SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, 3532 SDValue Chain, SDValue Ptr, 3533 const Value *SV, int SVOffset, 3534 bool isVolatile, unsigned Alignment) { 3535 SDValue Undef = getUNDEF(Ptr.getValueType()); 3536 return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3537 SV, SVOffset, VT, isVolatile, Alignment); 3538} 3539 3540SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, 3541 SDValue Chain, SDValue Ptr, 3542 const Value *SV, 3543 int SVOffset, MVT EVT, 3544 bool isVolatile, unsigned Alignment) { 3545 SDValue Undef = getUNDEF(Ptr.getValueType()); 3546 return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef, 3547 SV, SVOffset, EVT, isVolatile, Alignment); 3548} 3549 3550SDValue 3551SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, 3552 SDValue Offset, ISD::MemIndexedMode AM) { 3553 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3554 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3555 "Load is already a indexed load!"); 3556 return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(), 3557 LD->getChain(), Base, Offset, LD->getSrcValue(), 3558 LD->getSrcValueOffset(), LD->getMemoryVT(), 3559 LD->isVolatile(), LD->getAlignment()); 3560} 3561 3562SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, 3563 SDValue Ptr, const Value *SV, int SVOffset, 3564 bool isVolatile, unsigned Alignment) { 3565 MVT VT = Val.getValueType(); 3566 3567 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3568 Alignment = getMVTAlignment(VT); 3569 3570 SDVTList VTs = getVTList(MVT::Other); 3571 SDValue Undef = getUNDEF(Ptr.getValueType()); 3572 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3573 FoldingSetNodeID ID; 3574 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3575 ID.AddInteger(VT.getRawBits()); 3576 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, 3577 isVolatile, Alignment)); 3578 void *IP = 0; 3579 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3580 return SDValue(E, 0); 3581 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3582 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false, 3583 VT, SV, SVOffset, Alignment, isVolatile); 3584 CSEMap.InsertNode(N, IP); 3585 AllNodes.push_back(N); 3586 return SDValue(N, 0); 3587} 3588 3589SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, 3590 SDValue Ptr, const Value *SV, 3591 int SVOffset, MVT SVT, 3592 bool isVolatile, unsigned Alignment) { 3593 MVT VT = Val.getValueType(); 3594 3595 if (VT == SVT) 3596 return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3597 3598 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3599 assert(VT.isInteger() == SVT.isInteger() && 3600 "Can't do FP-INT conversion!"); 3601 3602 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3603 Alignment = getMVTAlignment(VT); 3604 3605 SDVTList VTs = getVTList(MVT::Other); 3606 SDValue Undef = getUNDEF(Ptr.getValueType()); 3607 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3608 FoldingSetNodeID ID; 3609 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3610 ID.AddInteger(SVT.getRawBits()); 3611 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, 3612 isVolatile, Alignment)); 3613 void *IP = 0; 3614 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3615 return SDValue(E, 0); 3616 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3617 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true, 3618 SVT, SV, SVOffset, Alignment, isVolatile); 3619 CSEMap.InsertNode(N, IP); 3620 AllNodes.push_back(N); 3621 return SDValue(N, 0); 3622} 3623 3624SDValue 3625SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, 3626 SDValue Offset, ISD::MemIndexedMode AM) { 3627 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3628 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3629 "Store is already a indexed store!"); 3630 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3631 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3632 FoldingSetNodeID ID; 3633 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3634 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3635 ID.AddInteger(ST->getRawSubclassData()); 3636 void *IP = 0; 3637 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3638 return SDValue(E, 0); 3639 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3640 new (N) StoreSDNode(Ops, dl, VTs, AM, 3641 ST->isTruncatingStore(), ST->getMemoryVT(), 3642 ST->getSrcValue(), ST->getSrcValueOffset(), 3643 ST->getAlignment(), ST->isVolatile()); 3644 CSEMap.InsertNode(N, IP); 3645 AllNodes.push_back(N); 3646 return SDValue(N, 0); 3647} 3648 3649SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl, 3650 SDValue Chain, SDValue Ptr, 3651 SDValue SV) { 3652 SDValue Ops[] = { Chain, Ptr, SV }; 3653 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3); 3654} 3655 3656SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3657 const SDUse *Ops, unsigned NumOps) { 3658 switch (NumOps) { 3659 case 0: return getNode(Opcode, DL, VT); 3660 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3661 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3662 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3663 default: break; 3664 } 3665 3666 // Copy from an SDUse array into an SDValue array for use with 3667 // the regular getNode logic. 3668 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3669 return getNode(Opcode, DL, VT, &NewOps[0], NumOps); 3670} 3671 3672SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3673 const SDValue *Ops, unsigned NumOps) { 3674 switch (NumOps) { 3675 case 0: return getNode(Opcode, DL, VT); 3676 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3677 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3678 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3679 default: break; 3680 } 3681 3682 switch (Opcode) { 3683 default: break; 3684 case ISD::SELECT_CC: { 3685 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3686 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3687 "LHS and RHS of condition must have same type!"); 3688 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3689 "True and False arms of SelectCC must have same type!"); 3690 assert(Ops[2].getValueType() == VT && 3691 "select_cc node must be of same type as true and false value!"); 3692 break; 3693 } 3694 case ISD::BR_CC: { 3695 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3696 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3697 "LHS/RHS of comparison should match types!"); 3698 break; 3699 } 3700 } 3701 3702 // Memoize nodes. 3703 SDNode *N; 3704 SDVTList VTs = getVTList(VT); 3705 3706 if (VT != MVT::Flag) { 3707 FoldingSetNodeID ID; 3708 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3709 void *IP = 0; 3710 3711 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3712 return SDValue(E, 0); 3713 3714 N = NodeAllocator.Allocate<SDNode>(); 3715 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3716 CSEMap.InsertNode(N, IP); 3717 } else { 3718 N = NodeAllocator.Allocate<SDNode>(); 3719 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3720 } 3721 3722 AllNodes.push_back(N); 3723#ifndef NDEBUG 3724 VerifyNode(N); 3725#endif 3726 return SDValue(N, 0); 3727} 3728 3729SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3730 const std::vector<MVT> &ResultTys, 3731 const SDValue *Ops, unsigned NumOps) { 3732 return getNode(Opcode, DL, getNodeValueTypes(ResultTys), ResultTys.size(), 3733 Ops, NumOps); 3734} 3735 3736SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3737 const MVT *VTs, unsigned NumVTs, 3738 const SDValue *Ops, unsigned NumOps) { 3739 if (NumVTs == 1) 3740 return getNode(Opcode, DL, VTs[0], Ops, NumOps); 3741 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps); 3742} 3743 3744SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3745 const SDValue *Ops, unsigned NumOps) { 3746 if (VTList.NumVTs == 1) 3747 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps); 3748 3749 switch (Opcode) { 3750 // FIXME: figure out how to safely handle things like 3751 // int foo(int x) { return 1 << (x & 255); } 3752 // int bar() { return foo(256); } 3753#if 0 3754 case ISD::SRA_PARTS: 3755 case ISD::SRL_PARTS: 3756 case ISD::SHL_PARTS: 3757 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3758 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3759 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3760 else if (N3.getOpcode() == ISD::AND) 3761 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3762 // If the and is only masking out bits that cannot effect the shift, 3763 // eliminate the and. 3764 unsigned NumBits = VT.getSizeInBits()*2; 3765 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3766 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3767 } 3768 break; 3769#endif 3770 } 3771 3772 // Memoize the node unless it returns a flag. 3773 SDNode *N; 3774 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3775 FoldingSetNodeID ID; 3776 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3777 void *IP = 0; 3778 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3779 return SDValue(E, 0); 3780 if (NumOps == 1) { 3781 N = NodeAllocator.Allocate<UnarySDNode>(); 3782 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3783 } else if (NumOps == 2) { 3784 N = NodeAllocator.Allocate<BinarySDNode>(); 3785 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3786 } else if (NumOps == 3) { 3787 N = NodeAllocator.Allocate<TernarySDNode>(); 3788 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3789 } else { 3790 N = NodeAllocator.Allocate<SDNode>(); 3791 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3792 } 3793 CSEMap.InsertNode(N, IP); 3794 } else { 3795 if (NumOps == 1) { 3796 N = NodeAllocator.Allocate<UnarySDNode>(); 3797 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3798 } else if (NumOps == 2) { 3799 N = NodeAllocator.Allocate<BinarySDNode>(); 3800 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3801 } else if (NumOps == 3) { 3802 N = NodeAllocator.Allocate<TernarySDNode>(); 3803 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3804 } else { 3805 N = NodeAllocator.Allocate<SDNode>(); 3806 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3807 } 3808 } 3809 AllNodes.push_back(N); 3810#ifndef NDEBUG 3811 VerifyNode(N); 3812#endif 3813 return SDValue(N, 0); 3814} 3815 3816SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) { 3817 return getNode(Opcode, DL, VTList, 0, 0); 3818} 3819 3820SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3821 SDValue N1) { 3822 SDValue Ops[] = { N1 }; 3823 return getNode(Opcode, DL, VTList, Ops, 1); 3824} 3825 3826SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3827 SDValue N1, SDValue N2) { 3828 SDValue Ops[] = { N1, N2 }; 3829 return getNode(Opcode, DL, VTList, Ops, 2); 3830} 3831 3832SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3833 SDValue N1, SDValue N2, SDValue N3) { 3834 SDValue Ops[] = { N1, N2, N3 }; 3835 return getNode(Opcode, DL, VTList, Ops, 3); 3836} 3837 3838SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3839 SDValue N1, SDValue N2, SDValue N3, 3840 SDValue N4) { 3841 SDValue Ops[] = { N1, N2, N3, N4 }; 3842 return getNode(Opcode, DL, VTList, Ops, 4); 3843} 3844 3845SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3846 SDValue N1, SDValue N2, SDValue N3, 3847 SDValue N4, SDValue N5) { 3848 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3849 return getNode(Opcode, DL, VTList, Ops, 5); 3850} 3851 3852SDVTList SelectionDAG::getVTList(MVT VT) { 3853 return makeVTList(SDNode::getValueTypeList(VT), 1); 3854} 3855 3856SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3857 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3858 E = VTList.rend(); I != E; ++I) 3859 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3860 return *I; 3861 3862 MVT *Array = Allocator.Allocate<MVT>(2); 3863 Array[0] = VT1; 3864 Array[1] = VT2; 3865 SDVTList Result = makeVTList(Array, 2); 3866 VTList.push_back(Result); 3867 return Result; 3868} 3869 3870SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3871 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3872 E = VTList.rend(); I != E; ++I) 3873 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3874 I->VTs[2] == VT3) 3875 return *I; 3876 3877 MVT *Array = Allocator.Allocate<MVT>(3); 3878 Array[0] = VT1; 3879 Array[1] = VT2; 3880 Array[2] = VT3; 3881 SDVTList Result = makeVTList(Array, 3); 3882 VTList.push_back(Result); 3883 return Result; 3884} 3885 3886SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { 3887 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3888 E = VTList.rend(); I != E; ++I) 3889 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3890 I->VTs[2] == VT3 && I->VTs[3] == VT4) 3891 return *I; 3892 3893 MVT *Array = Allocator.Allocate<MVT>(3); 3894 Array[0] = VT1; 3895 Array[1] = VT2; 3896 Array[2] = VT3; 3897 Array[3] = VT4; 3898 SDVTList Result = makeVTList(Array, 4); 3899 VTList.push_back(Result); 3900 return Result; 3901} 3902 3903SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3904 switch (NumVTs) { 3905 case 0: assert(0 && "Cannot have nodes without results!"); 3906 case 1: return getVTList(VTs[0]); 3907 case 2: return getVTList(VTs[0], VTs[1]); 3908 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3909 default: break; 3910 } 3911 3912 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3913 E = VTList.rend(); I != E; ++I) { 3914 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3915 continue; 3916 3917 bool NoMatch = false; 3918 for (unsigned i = 2; i != NumVTs; ++i) 3919 if (VTs[i] != I->VTs[i]) { 3920 NoMatch = true; 3921 break; 3922 } 3923 if (!NoMatch) 3924 return *I; 3925 } 3926 3927 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 3928 std::copy(VTs, VTs+NumVTs, Array); 3929 SDVTList Result = makeVTList(Array, NumVTs); 3930 VTList.push_back(Result); 3931 return Result; 3932} 3933 3934 3935/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 3936/// specified operands. If the resultant node already exists in the DAG, 3937/// this does not modify the specified node, instead it returns the node that 3938/// already exists. If the resultant node does not exist in the DAG, the 3939/// input node is returned. As a degenerate case, if you specify the same 3940/// input operands as the node already has, the input node is returned. 3941SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 3942 SDNode *N = InN.getNode(); 3943 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 3944 3945 // Check to see if there is no change. 3946 if (Op == N->getOperand(0)) return InN; 3947 3948 // See if the modified node already exists. 3949 void *InsertPos = 0; 3950 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 3951 return SDValue(Existing, InN.getResNo()); 3952 3953 // Nope it doesn't. Remove the node from its current place in the maps. 3954 if (InsertPos) 3955 if (!RemoveNodeFromCSEMaps(N)) 3956 InsertPos = 0; 3957 3958 // Now we update the operands. 3959 N->OperandList[0].set(Op); 3960 3961 // If this gets put into a CSE map, add it. 3962 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3963 return InN; 3964} 3965 3966SDValue SelectionDAG:: 3967UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 3968 SDNode *N = InN.getNode(); 3969 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 3970 3971 // Check to see if there is no change. 3972 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 3973 return InN; // No operands changed, just return the input node. 3974 3975 // See if the modified node already exists. 3976 void *InsertPos = 0; 3977 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 3978 return SDValue(Existing, InN.getResNo()); 3979 3980 // Nope it doesn't. Remove the node from its current place in the maps. 3981 if (InsertPos) 3982 if (!RemoveNodeFromCSEMaps(N)) 3983 InsertPos = 0; 3984 3985 // Now we update the operands. 3986 if (N->OperandList[0] != Op1) 3987 N->OperandList[0].set(Op1); 3988 if (N->OperandList[1] != Op2) 3989 N->OperandList[1].set(Op2); 3990 3991 // If this gets put into a CSE map, add it. 3992 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3993 return InN; 3994} 3995 3996SDValue SelectionDAG:: 3997UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 3998 SDValue Ops[] = { Op1, Op2, Op3 }; 3999 return UpdateNodeOperands(N, Ops, 3); 4000} 4001 4002SDValue SelectionDAG:: 4003UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4004 SDValue Op3, SDValue Op4) { 4005 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 4006 return UpdateNodeOperands(N, Ops, 4); 4007} 4008 4009SDValue SelectionDAG:: 4010UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4011 SDValue Op3, SDValue Op4, SDValue Op5) { 4012 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 4013 return UpdateNodeOperands(N, Ops, 5); 4014} 4015 4016SDValue SelectionDAG:: 4017UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 4018 SDNode *N = InN.getNode(); 4019 assert(N->getNumOperands() == NumOps && 4020 "Update with wrong number of operands"); 4021 4022 // Check to see if there is no change. 4023 bool AnyChange = false; 4024 for (unsigned i = 0; i != NumOps; ++i) { 4025 if (Ops[i] != N->getOperand(i)) { 4026 AnyChange = true; 4027 break; 4028 } 4029 } 4030 4031 // No operands changed, just return the input node. 4032 if (!AnyChange) return InN; 4033 4034 // See if the modified node already exists. 4035 void *InsertPos = 0; 4036 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 4037 return SDValue(Existing, InN.getResNo()); 4038 4039 // Nope it doesn't. Remove the node from its current place in the maps. 4040 if (InsertPos) 4041 if (!RemoveNodeFromCSEMaps(N)) 4042 InsertPos = 0; 4043 4044 // Now we update the operands. 4045 for (unsigned i = 0; i != NumOps; ++i) 4046 if (N->OperandList[i] != Ops[i]) 4047 N->OperandList[i].set(Ops[i]); 4048 4049 // If this gets put into a CSE map, add it. 4050 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4051 return InN; 4052} 4053 4054/// DropOperands - Release the operands and set this node to have 4055/// zero operands. 4056void SDNode::DropOperands() { 4057 // Unlike the code in MorphNodeTo that does this, we don't need to 4058 // watch for dead nodes here. 4059 for (op_iterator I = op_begin(), E = op_end(); I != E; ) { 4060 SDUse &Use = *I++; 4061 Use.set(SDValue()); 4062 } 4063} 4064 4065/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4066/// machine opcode. 4067/// 4068SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4069 MVT VT) { 4070 SDVTList VTs = getVTList(VT); 4071 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4072} 4073 4074SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4075 MVT VT, SDValue Op1) { 4076 SDVTList VTs = getVTList(VT); 4077 SDValue Ops[] = { Op1 }; 4078 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4079} 4080 4081SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4082 MVT VT, SDValue Op1, 4083 SDValue Op2) { 4084 SDVTList VTs = getVTList(VT); 4085 SDValue Ops[] = { Op1, Op2 }; 4086 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4087} 4088 4089SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4090 MVT VT, SDValue Op1, 4091 SDValue Op2, SDValue Op3) { 4092 SDVTList VTs = getVTList(VT); 4093 SDValue Ops[] = { Op1, Op2, Op3 }; 4094 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4095} 4096 4097SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4098 MVT VT, const SDValue *Ops, 4099 unsigned NumOps) { 4100 SDVTList VTs = getVTList(VT); 4101 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4102} 4103 4104SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4105 MVT VT1, MVT VT2, const SDValue *Ops, 4106 unsigned NumOps) { 4107 SDVTList VTs = getVTList(VT1, VT2); 4108 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4109} 4110 4111SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4112 MVT VT1, MVT VT2) { 4113 SDVTList VTs = getVTList(VT1, VT2); 4114 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4115} 4116 4117SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4118 MVT VT1, MVT VT2, MVT VT3, 4119 const SDValue *Ops, unsigned NumOps) { 4120 SDVTList VTs = getVTList(VT1, VT2, VT3); 4121 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4122} 4123 4124SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4125 MVT VT1, MVT VT2, MVT VT3, MVT VT4, 4126 const SDValue *Ops, unsigned NumOps) { 4127 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4128 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4129} 4130 4131SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4132 MVT VT1, MVT VT2, 4133 SDValue Op1) { 4134 SDVTList VTs = getVTList(VT1, VT2); 4135 SDValue Ops[] = { Op1 }; 4136 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4137} 4138 4139SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4140 MVT VT1, MVT VT2, 4141 SDValue Op1, SDValue Op2) { 4142 SDVTList VTs = getVTList(VT1, VT2); 4143 SDValue Ops[] = { Op1, Op2 }; 4144 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4145} 4146 4147SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4148 MVT VT1, MVT VT2, 4149 SDValue Op1, SDValue Op2, 4150 SDValue Op3) { 4151 SDVTList VTs = getVTList(VT1, VT2); 4152 SDValue Ops[] = { Op1, Op2, Op3 }; 4153 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4154} 4155 4156SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4157 MVT VT1, MVT VT2, MVT VT3, 4158 SDValue Op1, SDValue Op2, 4159 SDValue Op3) { 4160 SDVTList VTs = getVTList(VT1, VT2, VT3); 4161 SDValue Ops[] = { Op1, Op2, Op3 }; 4162 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4163} 4164 4165SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4166 SDVTList VTs, const SDValue *Ops, 4167 unsigned NumOps) { 4168 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4169} 4170 4171SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4172 MVT VT) { 4173 SDVTList VTs = getVTList(VT); 4174 return MorphNodeTo(N, Opc, VTs, 0, 0); 4175} 4176 4177SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4178 MVT VT, SDValue Op1) { 4179 SDVTList VTs = getVTList(VT); 4180 SDValue Ops[] = { Op1 }; 4181 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4182} 4183 4184SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4185 MVT VT, SDValue Op1, 4186 SDValue Op2) { 4187 SDVTList VTs = getVTList(VT); 4188 SDValue Ops[] = { Op1, Op2 }; 4189 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4190} 4191 4192SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4193 MVT VT, SDValue Op1, 4194 SDValue Op2, SDValue Op3) { 4195 SDVTList VTs = getVTList(VT); 4196 SDValue Ops[] = { Op1, Op2, Op3 }; 4197 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4198} 4199 4200SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4201 MVT VT, const SDValue *Ops, 4202 unsigned NumOps) { 4203 SDVTList VTs = getVTList(VT); 4204 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4205} 4206 4207SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4208 MVT VT1, MVT VT2, const SDValue *Ops, 4209 unsigned NumOps) { 4210 SDVTList VTs = getVTList(VT1, VT2); 4211 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4212} 4213 4214SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4215 MVT VT1, MVT VT2) { 4216 SDVTList VTs = getVTList(VT1, VT2); 4217 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4218} 4219 4220SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4221 MVT VT1, MVT VT2, MVT VT3, 4222 const SDValue *Ops, unsigned NumOps) { 4223 SDVTList VTs = getVTList(VT1, VT2, VT3); 4224 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4225} 4226 4227SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4228 MVT VT1, MVT VT2, 4229 SDValue Op1) { 4230 SDVTList VTs = getVTList(VT1, VT2); 4231 SDValue Ops[] = { Op1 }; 4232 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4233} 4234 4235SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4236 MVT VT1, MVT VT2, 4237 SDValue Op1, SDValue Op2) { 4238 SDVTList VTs = getVTList(VT1, VT2); 4239 SDValue Ops[] = { Op1, Op2 }; 4240 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4241} 4242 4243SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4244 MVT VT1, MVT VT2, 4245 SDValue Op1, SDValue Op2, 4246 SDValue Op3) { 4247 SDVTList VTs = getVTList(VT1, VT2); 4248 SDValue Ops[] = { Op1, Op2, Op3 }; 4249 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4250} 4251 4252/// MorphNodeTo - These *mutate* the specified node to have the specified 4253/// return type, opcode, and operands. 4254/// 4255/// Note that MorphNodeTo returns the resultant node. If there is already a 4256/// node of the specified opcode and operands, it returns that node instead of 4257/// the current one. Note that the DebugLoc need not be the same. 4258/// 4259/// Using MorphNodeTo is faster than creating a new node and swapping it in 4260/// with ReplaceAllUsesWith both because it often avoids allocating a new 4261/// node, and because it doesn't require CSE recalculation for any of 4262/// the node's users. 4263/// 4264SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4265 SDVTList VTs, const SDValue *Ops, 4266 unsigned NumOps) { 4267 // If an identical node already exists, use it. 4268 void *IP = 0; 4269 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4270 FoldingSetNodeID ID; 4271 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4272 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4273 return ON; 4274 } 4275 4276 if (!RemoveNodeFromCSEMaps(N)) 4277 IP = 0; 4278 4279 // Start the morphing. 4280 N->NodeType = Opc; 4281 N->ValueList = VTs.VTs; 4282 N->NumValues = VTs.NumVTs; 4283 4284 // Clear the operands list, updating used nodes to remove this from their 4285 // use list. Keep track of any operands that become dead as a result. 4286 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4287 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 4288 SDUse &Use = *I++; 4289 SDNode *Used = Use.getNode(); 4290 Use.set(SDValue()); 4291 if (Used->use_empty()) 4292 DeadNodeSet.insert(Used); 4293 } 4294 4295 // If NumOps is larger than the # of operands we currently have, reallocate 4296 // the operand list. 4297 if (NumOps > N->NumOperands) { 4298 if (N->OperandsNeedDelete) 4299 delete[] N->OperandList; 4300 4301 if (N->isMachineOpcode()) { 4302 // We're creating a final node that will live unmorphed for the 4303 // remainder of the current SelectionDAG iteration, so we can allocate 4304 // the operands directly out of a pool with no recycling metadata. 4305 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4306 N->OperandsNeedDelete = false; 4307 } else { 4308 N->OperandList = new SDUse[NumOps]; 4309 N->OperandsNeedDelete = true; 4310 } 4311 } 4312 4313 // Assign the new operands. 4314 N->NumOperands = NumOps; 4315 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4316 N->OperandList[i].setUser(N); 4317 N->OperandList[i].setInitial(Ops[i]); 4318 } 4319 4320 // Delete any nodes that are still dead after adding the uses for the 4321 // new operands. 4322 SmallVector<SDNode *, 16> DeadNodes; 4323 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4324 E = DeadNodeSet.end(); I != E; ++I) 4325 if ((*I)->use_empty()) 4326 DeadNodes.push_back(*I); 4327 RemoveDeadNodes(DeadNodes); 4328 4329 if (IP) 4330 CSEMap.InsertNode(N, IP); // Memoize the new node. 4331 return N; 4332} 4333 4334 4335/// getTargetNode - These are used for target selectors to create a new node 4336/// with specified return type(s), target opcode, and operands. 4337/// 4338/// Note that getTargetNode returns the resultant node. If there is already a 4339/// node of the specified opcode and operands, it returns that node instead of 4340/// the current one. 4341SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) { 4342 return getNode(~Opcode, dl, VT).getNode(); 4343} 4344 4345SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4346 SDValue Op1) { 4347 return getNode(~Opcode, dl, VT, Op1).getNode(); 4348} 4349 4350SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4351 SDValue Op1, SDValue Op2) { 4352 return getNode(~Opcode, dl, VT, Op1, Op2).getNode(); 4353} 4354 4355SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4356 SDValue Op1, SDValue Op2, 4357 SDValue Op3) { 4358 return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode(); 4359} 4360 4361SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4362 const SDValue *Ops, unsigned NumOps) { 4363 return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); 4364} 4365 4366SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4367 MVT VT1, MVT VT2) { 4368 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4369 SDValue Op; 4370 return getNode(~Opcode, dl, VTs, 2, &Op, 0).getNode(); 4371} 4372 4373SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4374 MVT VT2, SDValue Op1) { 4375 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4376 return getNode(~Opcode, dl, VTs, 2, &Op1, 1).getNode(); 4377} 4378 4379SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4380 MVT VT2, SDValue Op1, 4381 SDValue Op2) { 4382 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4383 SDValue Ops[] = { Op1, Op2 }; 4384 return getNode(~Opcode, dl, VTs, 2, Ops, 2).getNode(); 4385} 4386 4387SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4388 MVT VT2, SDValue Op1, 4389 SDValue Op2, SDValue Op3) { 4390 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4391 SDValue Ops[] = { Op1, Op2, Op3 }; 4392 return getNode(~Opcode, dl, VTs, 2, Ops, 3).getNode(); 4393} 4394 4395SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4396 MVT VT1, MVT VT2, 4397 const SDValue *Ops, unsigned NumOps) { 4398 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4399 return getNode(~Opcode, dl, VTs, 2, Ops, NumOps).getNode(); 4400} 4401 4402SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4403 MVT VT1, MVT VT2, MVT VT3, 4404 SDValue Op1, SDValue Op2) { 4405 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4406 SDValue Ops[] = { Op1, Op2 }; 4407 return getNode(~Opcode, dl, VTs, 3, Ops, 2).getNode(); 4408} 4409 4410SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4411 MVT VT1, MVT VT2, MVT VT3, 4412 SDValue Op1, SDValue Op2, 4413 SDValue Op3) { 4414 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4415 SDValue Ops[] = { Op1, Op2, Op3 }; 4416 return getNode(~Opcode, dl, VTs, 3, Ops, 3).getNode(); 4417} 4418 4419SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4420 MVT VT1, MVT VT2, MVT VT3, 4421 const SDValue *Ops, unsigned NumOps) { 4422 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4423 return getNode(~Opcode, dl, VTs, 3, Ops, NumOps).getNode(); 4424} 4425 4426SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4427 MVT VT2, MVT VT3, MVT VT4, 4428 const SDValue *Ops, unsigned NumOps) { 4429 std::vector<MVT> VTList; 4430 VTList.push_back(VT1); 4431 VTList.push_back(VT2); 4432 VTList.push_back(VT3); 4433 VTList.push_back(VT4); 4434 const MVT *VTs = getNodeValueTypes(VTList); 4435 return getNode(~Opcode, dl, VTs, 4, Ops, NumOps).getNode(); 4436} 4437 4438SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4439 const std::vector<MVT> &ResultTys, 4440 const SDValue *Ops, unsigned NumOps) { 4441 const MVT *VTs = getNodeValueTypes(ResultTys); 4442 return getNode(~Opcode, dl, VTs, ResultTys.size(), 4443 Ops, NumOps).getNode(); 4444} 4445 4446/// getNodeIfExists - Get the specified node if it's already available, or 4447/// else return NULL. 4448SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4449 const SDValue *Ops, unsigned NumOps) { 4450 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4451 FoldingSetNodeID ID; 4452 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4453 void *IP = 0; 4454 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4455 return E; 4456 } 4457 return NULL; 4458} 4459 4460/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4461/// This can cause recursive merging of nodes in the DAG. 4462/// 4463/// This version assumes From has a single result value. 4464/// 4465void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4466 DAGUpdateListener *UpdateListener) { 4467 SDNode *From = FromN.getNode(); 4468 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4469 "Cannot replace with this method!"); 4470 assert(From != To.getNode() && "Cannot replace uses of with self"); 4471 4472 // Iterate over all the existing uses of From. New uses will be added 4473 // to the beginning of the use list, which we avoid visiting. 4474 // This specifically avoids visiting uses of From that arise while the 4475 // replacement is happening, because any such uses would be the result 4476 // of CSE: If an existing node looks like From after one of its operands 4477 // is replaced by To, we don't want to replace of all its users with To 4478 // too. See PR3018 for more info. 4479 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4480 while (UI != UE) { 4481 SDNode *User = *UI; 4482 4483 // This node is about to morph, remove its old self from the CSE maps. 4484 RemoveNodeFromCSEMaps(User); 4485 4486 // A user can appear in a use list multiple times, and when this 4487 // happens the uses are usually next to each other in the list. 4488 // To help reduce the number of CSE recomputations, process all 4489 // the uses of this user that we can find this way. 4490 do { 4491 SDUse &Use = UI.getUse(); 4492 ++UI; 4493 Use.set(To); 4494 } while (UI != UE && *UI == User); 4495 4496 // Now that we have modified User, add it back to the CSE maps. If it 4497 // already exists there, recursively merge the results together. 4498 AddModifiedNodeToCSEMaps(User, UpdateListener); 4499 } 4500} 4501 4502/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4503/// This can cause recursive merging of nodes in the DAG. 4504/// 4505/// This version assumes From/To have matching types and numbers of result 4506/// values. 4507/// 4508void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4509 DAGUpdateListener *UpdateListener) { 4510 assert(From->getVTList().VTs == To->getVTList().VTs && 4511 From->getNumValues() == To->getNumValues() && 4512 "Cannot use this version of ReplaceAllUsesWith!"); 4513 4514 // Handle the trivial case. 4515 if (From == To) 4516 return; 4517 4518 // Iterate over just the existing users of From. See the comments in 4519 // the ReplaceAllUsesWith above. 4520 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4521 while (UI != UE) { 4522 SDNode *User = *UI; 4523 4524 // This node is about to morph, remove its old self from the CSE maps. 4525 RemoveNodeFromCSEMaps(User); 4526 4527 // A user can appear in a use list multiple times, and when this 4528 // happens the uses are usually next to each other in the list. 4529 // To help reduce the number of CSE recomputations, process all 4530 // the uses of this user that we can find this way. 4531 do { 4532 SDUse &Use = UI.getUse(); 4533 ++UI; 4534 Use.setNode(To); 4535 } while (UI != UE && *UI == User); 4536 4537 // Now that we have modified User, add it back to the CSE maps. If it 4538 // already exists there, recursively merge the results together. 4539 AddModifiedNodeToCSEMaps(User, UpdateListener); 4540 } 4541} 4542 4543/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4544/// This can cause recursive merging of nodes in the DAG. 4545/// 4546/// This version can replace From with any result values. To must match the 4547/// number and types of values returned by From. 4548void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4549 const SDValue *To, 4550 DAGUpdateListener *UpdateListener) { 4551 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4552 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4553 4554 // Iterate over just the existing users of From. See the comments in 4555 // the ReplaceAllUsesWith above. 4556 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4557 while (UI != UE) { 4558 SDNode *User = *UI; 4559 4560 // This node is about to morph, remove its old self from the CSE maps. 4561 RemoveNodeFromCSEMaps(User); 4562 4563 // A user can appear in a use list multiple times, and when this 4564 // happens the uses are usually next to each other in the list. 4565 // To help reduce the number of CSE recomputations, process all 4566 // the uses of this user that we can find this way. 4567 do { 4568 SDUse &Use = UI.getUse(); 4569 const SDValue &ToOp = To[Use.getResNo()]; 4570 ++UI; 4571 Use.set(ToOp); 4572 } while (UI != UE && *UI == User); 4573 4574 // Now that we have modified User, add it back to the CSE maps. If it 4575 // already exists there, recursively merge the results together. 4576 AddModifiedNodeToCSEMaps(User, UpdateListener); 4577 } 4578} 4579 4580/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4581/// uses of other values produced by From.getNode() alone. The Deleted 4582/// vector is handled the same way as for ReplaceAllUsesWith. 4583void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4584 DAGUpdateListener *UpdateListener){ 4585 // Handle the really simple, really trivial case efficiently. 4586 if (From == To) return; 4587 4588 // Handle the simple, trivial, case efficiently. 4589 if (From.getNode()->getNumValues() == 1) { 4590 ReplaceAllUsesWith(From, To, UpdateListener); 4591 return; 4592 } 4593 4594 // Iterate over just the existing users of From. See the comments in 4595 // the ReplaceAllUsesWith above. 4596 SDNode::use_iterator UI = From.getNode()->use_begin(), 4597 UE = From.getNode()->use_end(); 4598 while (UI != UE) { 4599 SDNode *User = *UI; 4600 bool UserRemovedFromCSEMaps = false; 4601 4602 // A user can appear in a use list multiple times, and when this 4603 // happens the uses are usually next to each other in the list. 4604 // To help reduce the number of CSE recomputations, process all 4605 // the uses of this user that we can find this way. 4606 do { 4607 SDUse &Use = UI.getUse(); 4608 4609 // Skip uses of different values from the same node. 4610 if (Use.getResNo() != From.getResNo()) { 4611 ++UI; 4612 continue; 4613 } 4614 4615 // If this node hasn't been modified yet, it's still in the CSE maps, 4616 // so remove its old self from the CSE maps. 4617 if (!UserRemovedFromCSEMaps) { 4618 RemoveNodeFromCSEMaps(User); 4619 UserRemovedFromCSEMaps = true; 4620 } 4621 4622 ++UI; 4623 Use.set(To); 4624 } while (UI != UE && *UI == User); 4625 4626 // We are iterating over all uses of the From node, so if a use 4627 // doesn't use the specific value, no changes are made. 4628 if (!UserRemovedFromCSEMaps) 4629 continue; 4630 4631 // Now that we have modified User, add it back to the CSE maps. If it 4632 // already exists there, recursively merge the results together. 4633 AddModifiedNodeToCSEMaps(User, UpdateListener); 4634 } 4635} 4636 4637namespace { 4638 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith 4639 /// to record information about a use. 4640 struct UseMemo { 4641 SDNode *User; 4642 unsigned Index; 4643 SDUse *Use; 4644 }; 4645 4646 /// operator< - Sort Memos by User. 4647 bool operator<(const UseMemo &L, const UseMemo &R) { 4648 return (intptr_t)L.User < (intptr_t)R.User; 4649 } 4650} 4651 4652/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4653/// uses of other values produced by From.getNode() alone. The same value 4654/// may appear in both the From and To list. The Deleted vector is 4655/// handled the same way as for ReplaceAllUsesWith. 4656void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4657 const SDValue *To, 4658 unsigned Num, 4659 DAGUpdateListener *UpdateListener){ 4660 // Handle the simple, trivial case efficiently. 4661 if (Num == 1) 4662 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4663 4664 // Read up all the uses and make records of them. This helps 4665 // processing new uses that are introduced during the 4666 // replacement process. 4667 SmallVector<UseMemo, 4> Uses; 4668 for (unsigned i = 0; i != Num; ++i) { 4669 unsigned FromResNo = From[i].getResNo(); 4670 SDNode *FromNode = From[i].getNode(); 4671 for (SDNode::use_iterator UI = FromNode->use_begin(), 4672 E = FromNode->use_end(); UI != E; ++UI) { 4673 SDUse &Use = UI.getUse(); 4674 if (Use.getResNo() == FromResNo) { 4675 UseMemo Memo = { *UI, i, &Use }; 4676 Uses.push_back(Memo); 4677 } 4678 } 4679 } 4680 4681 // Sort the uses, so that all the uses from a given User are together. 4682 std::sort(Uses.begin(), Uses.end()); 4683 4684 for (unsigned UseIndex = 0, UseIndexEnd = Uses.size(); 4685 UseIndex != UseIndexEnd; ) { 4686 // We know that this user uses some value of From. If it is the right 4687 // value, update it. 4688 SDNode *User = Uses[UseIndex].User; 4689 4690 // This node is about to morph, remove its old self from the CSE maps. 4691 RemoveNodeFromCSEMaps(User); 4692 4693 // The Uses array is sorted, so all the uses for a given User 4694 // are next to each other in the list. 4695 // To help reduce the number of CSE recomputations, process all 4696 // the uses of this user that we can find this way. 4697 do { 4698 unsigned i = Uses[UseIndex].Index; 4699 SDUse &Use = *Uses[UseIndex].Use; 4700 ++UseIndex; 4701 4702 Use.set(To[i]); 4703 } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User); 4704 4705 // Now that we have modified User, add it back to the CSE maps. If it 4706 // already exists there, recursively merge the results together. 4707 AddModifiedNodeToCSEMaps(User, UpdateListener); 4708 } 4709} 4710 4711/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4712/// based on their topological order. It returns the maximum id and a vector 4713/// of the SDNodes* in assigned order by reference. 4714unsigned SelectionDAG::AssignTopologicalOrder() { 4715 4716 unsigned DAGSize = 0; 4717 4718 // SortedPos tracks the progress of the algorithm. Nodes before it are 4719 // sorted, nodes after it are unsorted. When the algorithm completes 4720 // it is at the end of the list. 4721 allnodes_iterator SortedPos = allnodes_begin(); 4722 4723 // Visit all the nodes. Move nodes with no operands to the front of 4724 // the list immediately. Annotate nodes that do have operands with their 4725 // operand count. Before we do this, the Node Id fields of the nodes 4726 // may contain arbitrary values. After, the Node Id fields for nodes 4727 // before SortedPos will contain the topological sort index, and the 4728 // Node Id fields for nodes At SortedPos and after will contain the 4729 // count of outstanding operands. 4730 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4731 SDNode *N = I++; 4732 unsigned Degree = N->getNumOperands(); 4733 if (Degree == 0) { 4734 // A node with no uses, add it to the result array immediately. 4735 N->setNodeId(DAGSize++); 4736 allnodes_iterator Q = N; 4737 if (Q != SortedPos) 4738 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4739 ++SortedPos; 4740 } else { 4741 // Temporarily use the Node Id as scratch space for the degree count. 4742 N->setNodeId(Degree); 4743 } 4744 } 4745 4746 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4747 // such that by the time the end is reached all nodes will be sorted. 4748 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4749 SDNode *N = I; 4750 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4751 UI != UE; ++UI) { 4752 SDNode *P = *UI; 4753 unsigned Degree = P->getNodeId(); 4754 --Degree; 4755 if (Degree == 0) { 4756 // All of P's operands are sorted, so P may sorted now. 4757 P->setNodeId(DAGSize++); 4758 if (P != SortedPos) 4759 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4760 ++SortedPos; 4761 } else { 4762 // Update P's outstanding operand count. 4763 P->setNodeId(Degree); 4764 } 4765 } 4766 } 4767 4768 assert(SortedPos == AllNodes.end() && 4769 "Topological sort incomplete!"); 4770 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4771 "First node in topological sort is not the entry token!"); 4772 assert(AllNodes.front().getNodeId() == 0 && 4773 "First node in topological sort has non-zero id!"); 4774 assert(AllNodes.front().getNumOperands() == 0 && 4775 "First node in topological sort has operands!"); 4776 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4777 "Last node in topologic sort has unexpected id!"); 4778 assert(AllNodes.back().use_empty() && 4779 "Last node in topologic sort has users!"); 4780 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 4781 return DAGSize; 4782} 4783 4784 4785 4786//===----------------------------------------------------------------------===// 4787// SDNode Class 4788//===----------------------------------------------------------------------===// 4789 4790HandleSDNode::~HandleSDNode() { 4791 DropOperands(); 4792} 4793 4794GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4795 MVT VT, int64_t o) 4796 : SDNode(isa<GlobalVariable>(GA) && 4797 cast<GlobalVariable>(GA)->isThreadLocal() ? 4798 // Thread Local 4799 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4800 // Non Thread Local 4801 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4802 DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o) { 4803 TheGlobal = const_cast<GlobalValue*>(GA); 4804} 4805 4806MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt, 4807 const Value *srcValue, int SVO, 4808 unsigned alignment, bool vol) 4809 : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4810 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4811 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4812 assert(getAlignment() == alignment && "Alignment representation error!"); 4813 assert(isVolatile() == vol && "Volatile representation error!"); 4814} 4815 4816MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, 4817 const SDValue *Ops, 4818 unsigned NumOps, MVT memvt, const Value *srcValue, 4819 int SVO, unsigned alignment, bool vol) 4820 : SDNode(Opc, dl, VTs, Ops, NumOps), 4821 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4822 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4823 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4824 assert(getAlignment() == alignment && "Alignment representation error!"); 4825 assert(isVolatile() == vol && "Volatile representation error!"); 4826} 4827 4828/// getMemOperand - Return a MachineMemOperand object describing the memory 4829/// reference performed by this memory reference. 4830MachineMemOperand MemSDNode::getMemOperand() const { 4831 int Flags = 0; 4832 if (isa<LoadSDNode>(this)) 4833 Flags = MachineMemOperand::MOLoad; 4834 else if (isa<StoreSDNode>(this)) 4835 Flags = MachineMemOperand::MOStore; 4836 else if (isa<AtomicSDNode>(this)) { 4837 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4838 } 4839 else { 4840 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4841 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4842 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4843 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4844 } 4845 4846 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4847 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4848 4849 // Check if the memory reference references a frame index 4850 const FrameIndexSDNode *FI = 4851 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4852 if (!getSrcValue() && FI) 4853 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4854 Flags, 0, Size, getAlignment()); 4855 else 4856 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4857 Size, getAlignment()); 4858} 4859 4860/// Profile - Gather unique data for the node. 4861/// 4862void SDNode::Profile(FoldingSetNodeID &ID) const { 4863 AddNodeIDNode(ID, this); 4864} 4865 4866/// getValueTypeList - Return a pointer to the specified value type. 4867/// 4868const MVT *SDNode::getValueTypeList(MVT VT) { 4869 if (VT.isExtended()) { 4870 static std::set<MVT, MVT::compareRawBits> EVTs; 4871 return &(*EVTs.insert(VT).first); 4872 } else { 4873 static MVT VTs[MVT::LAST_VALUETYPE]; 4874 VTs[VT.getSimpleVT()] = VT; 4875 return &VTs[VT.getSimpleVT()]; 4876 } 4877} 4878 4879/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4880/// indicated value. This method ignores uses of other values defined by this 4881/// operation. 4882bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4883 assert(Value < getNumValues() && "Bad value!"); 4884 4885 // TODO: Only iterate over uses of a given value of the node 4886 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4887 if (UI.getUse().getResNo() == Value) { 4888 if (NUses == 0) 4889 return false; 4890 --NUses; 4891 } 4892 } 4893 4894 // Found exactly the right number of uses? 4895 return NUses == 0; 4896} 4897 4898 4899/// hasAnyUseOfValue - Return true if there are any use of the indicated 4900/// value. This method ignores uses of other values defined by this operation. 4901bool SDNode::hasAnyUseOfValue(unsigned Value) const { 4902 assert(Value < getNumValues() && "Bad value!"); 4903 4904 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 4905 if (UI.getUse().getResNo() == Value) 4906 return true; 4907 4908 return false; 4909} 4910 4911 4912/// isOnlyUserOf - Return true if this node is the only use of N. 4913/// 4914bool SDNode::isOnlyUserOf(SDNode *N) const { 4915 bool Seen = false; 4916 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 4917 SDNode *User = *I; 4918 if (User == this) 4919 Seen = true; 4920 else 4921 return false; 4922 } 4923 4924 return Seen; 4925} 4926 4927/// isOperand - Return true if this node is an operand of N. 4928/// 4929bool SDValue::isOperandOf(SDNode *N) const { 4930 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4931 if (*this == N->getOperand(i)) 4932 return true; 4933 return false; 4934} 4935 4936bool SDNode::isOperandOf(SDNode *N) const { 4937 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 4938 if (this == N->OperandList[i].getNode()) 4939 return true; 4940 return false; 4941} 4942 4943/// reachesChainWithoutSideEffects - Return true if this operand (which must 4944/// be a chain) reaches the specified operand without crossing any 4945/// side-effecting instructions. In practice, this looks through token 4946/// factors and non-volatile loads. In order to remain efficient, this only 4947/// looks a couple of nodes in, it does not do an exhaustive search. 4948bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 4949 unsigned Depth) const { 4950 if (*this == Dest) return true; 4951 4952 // Don't search too deeply, we just want to be able to see through 4953 // TokenFactor's etc. 4954 if (Depth == 0) return false; 4955 4956 // If this is a token factor, all inputs to the TF happen in parallel. If any 4957 // of the operands of the TF reach dest, then we can do the xform. 4958 if (getOpcode() == ISD::TokenFactor) { 4959 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 4960 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 4961 return true; 4962 return false; 4963 } 4964 4965 // Loads don't have side effects, look through them. 4966 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 4967 if (!Ld->isVolatile()) 4968 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 4969 } 4970 return false; 4971} 4972 4973 4974static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 4975 SmallPtrSet<SDNode *, 32> &Visited) { 4976 if (found || !Visited.insert(N)) 4977 return; 4978 4979 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 4980 SDNode *Op = N->getOperand(i).getNode(); 4981 if (Op == P) { 4982 found = true; 4983 return; 4984 } 4985 findPredecessor(Op, P, found, Visited); 4986 } 4987} 4988 4989/// isPredecessorOf - Return true if this node is a predecessor of N. This node 4990/// is either an operand of N or it can be reached by recursively traversing 4991/// up the operands. 4992/// NOTE: this is an expensive method. Use it carefully. 4993bool SDNode::isPredecessorOf(SDNode *N) const { 4994 SmallPtrSet<SDNode *, 32> Visited; 4995 bool found = false; 4996 findPredecessor(N, this, found, Visited); 4997 return found; 4998} 4999 5000uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 5001 assert(Num < NumOperands && "Invalid child # of SDNode!"); 5002 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 5003} 5004 5005std::string SDNode::getOperationName(const SelectionDAG *G) const { 5006 switch (getOpcode()) { 5007 default: 5008 if (getOpcode() < ISD::BUILTIN_OP_END) 5009 return "<<Unknown DAG Node>>"; 5010 if (isMachineOpcode()) { 5011 if (G) 5012 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 5013 if (getMachineOpcode() < TII->getNumOpcodes()) 5014 return TII->get(getMachineOpcode()).getName(); 5015 return "<<Unknown Machine Node>>"; 5016 } 5017 if (G) { 5018 const TargetLowering &TLI = G->getTargetLoweringInfo(); 5019 const char *Name = TLI.getTargetNodeName(getOpcode()); 5020 if (Name) return Name; 5021 return "<<Unknown Target Node>>"; 5022 } 5023 return "<<Unknown Node>>"; 5024 5025#ifndef NDEBUG 5026 case ISD::DELETED_NODE: 5027 return "<<Deleted Node!>>"; 5028#endif 5029 case ISD::PREFETCH: return "Prefetch"; 5030 case ISD::MEMBARRIER: return "MemBarrier"; 5031 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 5032 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 5033 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 5034 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 5035 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; 5036 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; 5037 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor"; 5038 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand"; 5039 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin"; 5040 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; 5041 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; 5042 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; 5043 case ISD::PCMARKER: return "PCMarker"; 5044 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5045 case ISD::SRCVALUE: return "SrcValue"; 5046 case ISD::MEMOPERAND: return "MemOperand"; 5047 case ISD::EntryToken: return "EntryToken"; 5048 case ISD::TokenFactor: return "TokenFactor"; 5049 case ISD::AssertSext: return "AssertSext"; 5050 case ISD::AssertZext: return "AssertZext"; 5051 5052 case ISD::BasicBlock: return "BasicBlock"; 5053 case ISD::ARG_FLAGS: return "ArgFlags"; 5054 case ISD::VALUETYPE: return "ValueType"; 5055 case ISD::Register: return "Register"; 5056 5057 case ISD::Constant: return "Constant"; 5058 case ISD::ConstantFP: return "ConstantFP"; 5059 case ISD::GlobalAddress: return "GlobalAddress"; 5060 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5061 case ISD::FrameIndex: return "FrameIndex"; 5062 case ISD::JumpTable: return "JumpTable"; 5063 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5064 case ISD::RETURNADDR: return "RETURNADDR"; 5065 case ISD::FRAMEADDR: return "FRAMEADDR"; 5066 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5067 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5068 case ISD::EHSELECTION: return "EHSELECTION"; 5069 case ISD::EH_RETURN: return "EH_RETURN"; 5070 case ISD::ConstantPool: return "ConstantPool"; 5071 case ISD::ExternalSymbol: return "ExternalSymbol"; 5072 case ISD::INTRINSIC_WO_CHAIN: { 5073 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5074 return Intrinsic::getName((Intrinsic::ID)IID); 5075 } 5076 case ISD::INTRINSIC_VOID: 5077 case ISD::INTRINSIC_W_CHAIN: { 5078 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5079 return Intrinsic::getName((Intrinsic::ID)IID); 5080 } 5081 5082 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5083 case ISD::TargetConstant: return "TargetConstant"; 5084 case ISD::TargetConstantFP:return "TargetConstantFP"; 5085 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5086 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5087 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5088 case ISD::TargetJumpTable: return "TargetJumpTable"; 5089 case ISD::TargetConstantPool: return "TargetConstantPool"; 5090 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5091 5092 case ISD::CopyToReg: return "CopyToReg"; 5093 case ISD::CopyFromReg: return "CopyFromReg"; 5094 case ISD::UNDEF: return "undef"; 5095 case ISD::MERGE_VALUES: return "merge_values"; 5096 case ISD::INLINEASM: return "inlineasm"; 5097 case ISD::DBG_LABEL: return "dbg_label"; 5098 case ISD::EH_LABEL: return "eh_label"; 5099 case ISD::DECLARE: return "declare"; 5100 case ISD::HANDLENODE: return "handlenode"; 5101 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5102 case ISD::CALL: return "call"; 5103 5104 // Unary operators 5105 case ISD::FABS: return "fabs"; 5106 case ISD::FNEG: return "fneg"; 5107 case ISD::FSQRT: return "fsqrt"; 5108 case ISD::FSIN: return "fsin"; 5109 case ISD::FCOS: return "fcos"; 5110 case ISD::FPOWI: return "fpowi"; 5111 case ISD::FPOW: return "fpow"; 5112 case ISD::FTRUNC: return "ftrunc"; 5113 case ISD::FFLOOR: return "ffloor"; 5114 case ISD::FCEIL: return "fceil"; 5115 case ISD::FRINT: return "frint"; 5116 case ISD::FNEARBYINT: return "fnearbyint"; 5117 5118 // Binary operators 5119 case ISD::ADD: return "add"; 5120 case ISD::SUB: return "sub"; 5121 case ISD::MUL: return "mul"; 5122 case ISD::MULHU: return "mulhu"; 5123 case ISD::MULHS: return "mulhs"; 5124 case ISD::SDIV: return "sdiv"; 5125 case ISD::UDIV: return "udiv"; 5126 case ISD::SREM: return "srem"; 5127 case ISD::UREM: return "urem"; 5128 case ISD::SMUL_LOHI: return "smul_lohi"; 5129 case ISD::UMUL_LOHI: return "umul_lohi"; 5130 case ISD::SDIVREM: return "sdivrem"; 5131 case ISD::UDIVREM: return "udivrem"; 5132 case ISD::AND: return "and"; 5133 case ISD::OR: return "or"; 5134 case ISD::XOR: return "xor"; 5135 case ISD::SHL: return "shl"; 5136 case ISD::SRA: return "sra"; 5137 case ISD::SRL: return "srl"; 5138 case ISD::ROTL: return "rotl"; 5139 case ISD::ROTR: return "rotr"; 5140 case ISD::FADD: return "fadd"; 5141 case ISD::FSUB: return "fsub"; 5142 case ISD::FMUL: return "fmul"; 5143 case ISD::FDIV: return "fdiv"; 5144 case ISD::FREM: return "frem"; 5145 case ISD::FCOPYSIGN: return "fcopysign"; 5146 case ISD::FGETSIGN: return "fgetsign"; 5147 5148 case ISD::SETCC: return "setcc"; 5149 case ISD::VSETCC: return "vsetcc"; 5150 case ISD::SELECT: return "select"; 5151 case ISD::SELECT_CC: return "select_cc"; 5152 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5153 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5154 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5155 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5156 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5157 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5158 case ISD::CARRY_FALSE: return "carry_false"; 5159 case ISD::ADDC: return "addc"; 5160 case ISD::ADDE: return "adde"; 5161 case ISD::SADDO: return "saddo"; 5162 case ISD::UADDO: return "uaddo"; 5163 case ISD::SSUBO: return "ssubo"; 5164 case ISD::USUBO: return "usubo"; 5165 case ISD::SMULO: return "smulo"; 5166 case ISD::UMULO: return "umulo"; 5167 case ISD::SUBC: return "subc"; 5168 case ISD::SUBE: return "sube"; 5169 case ISD::SHL_PARTS: return "shl_parts"; 5170 case ISD::SRA_PARTS: return "sra_parts"; 5171 case ISD::SRL_PARTS: return "srl_parts"; 5172 5173 case ISD::EXTRACT_SUBREG: return "extract_subreg"; 5174 case ISD::INSERT_SUBREG: return "insert_subreg"; 5175 5176 // Conversion operators. 5177 case ISD::SIGN_EXTEND: return "sign_extend"; 5178 case ISD::ZERO_EXTEND: return "zero_extend"; 5179 case ISD::ANY_EXTEND: return "any_extend"; 5180 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5181 case ISD::TRUNCATE: return "truncate"; 5182 case ISD::FP_ROUND: return "fp_round"; 5183 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5184 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5185 case ISD::FP_EXTEND: return "fp_extend"; 5186 5187 case ISD::SINT_TO_FP: return "sint_to_fp"; 5188 case ISD::UINT_TO_FP: return "uint_to_fp"; 5189 case ISD::FP_TO_SINT: return "fp_to_sint"; 5190 case ISD::FP_TO_UINT: return "fp_to_uint"; 5191 case ISD::BIT_CONVERT: return "bit_convert"; 5192 5193 case ISD::CONVERT_RNDSAT: { 5194 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5195 default: assert(0 && "Unknown cvt code!"); 5196 case ISD::CVT_FF: return "cvt_ff"; 5197 case ISD::CVT_FS: return "cvt_fs"; 5198 case ISD::CVT_FU: return "cvt_fu"; 5199 case ISD::CVT_SF: return "cvt_sf"; 5200 case ISD::CVT_UF: return "cvt_uf"; 5201 case ISD::CVT_SS: return "cvt_ss"; 5202 case ISD::CVT_SU: return "cvt_su"; 5203 case ISD::CVT_US: return "cvt_us"; 5204 case ISD::CVT_UU: return "cvt_uu"; 5205 } 5206 } 5207 5208 // Control flow instructions 5209 case ISD::BR: return "br"; 5210 case ISD::BRIND: return "brind"; 5211 case ISD::BR_JT: return "br_jt"; 5212 case ISD::BRCOND: return "brcond"; 5213 case ISD::BR_CC: return "br_cc"; 5214 case ISD::RET: return "ret"; 5215 case ISD::CALLSEQ_START: return "callseq_start"; 5216 case ISD::CALLSEQ_END: return "callseq_end"; 5217 5218 // Other operators 5219 case ISD::LOAD: return "load"; 5220 case ISD::STORE: return "store"; 5221 case ISD::VAARG: return "vaarg"; 5222 case ISD::VACOPY: return "vacopy"; 5223 case ISD::VAEND: return "vaend"; 5224 case ISD::VASTART: return "vastart"; 5225 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5226 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5227 case ISD::BUILD_PAIR: return "build_pair"; 5228 case ISD::STACKSAVE: return "stacksave"; 5229 case ISD::STACKRESTORE: return "stackrestore"; 5230 case ISD::TRAP: return "trap"; 5231 5232 // Bit manipulation 5233 case ISD::BSWAP: return "bswap"; 5234 case ISD::CTPOP: return "ctpop"; 5235 case ISD::CTTZ: return "cttz"; 5236 case ISD::CTLZ: return "ctlz"; 5237 5238 // Debug info 5239 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5240 case ISD::DEBUG_LOC: return "debug_loc"; 5241 5242 // Trampolines 5243 case ISD::TRAMPOLINE: return "trampoline"; 5244 5245 case ISD::CONDCODE: 5246 switch (cast<CondCodeSDNode>(this)->get()) { 5247 default: assert(0 && "Unknown setcc condition!"); 5248 case ISD::SETOEQ: return "setoeq"; 5249 case ISD::SETOGT: return "setogt"; 5250 case ISD::SETOGE: return "setoge"; 5251 case ISD::SETOLT: return "setolt"; 5252 case ISD::SETOLE: return "setole"; 5253 case ISD::SETONE: return "setone"; 5254 5255 case ISD::SETO: return "seto"; 5256 case ISD::SETUO: return "setuo"; 5257 case ISD::SETUEQ: return "setue"; 5258 case ISD::SETUGT: return "setugt"; 5259 case ISD::SETUGE: return "setuge"; 5260 case ISD::SETULT: return "setult"; 5261 case ISD::SETULE: return "setule"; 5262 case ISD::SETUNE: return "setune"; 5263 5264 case ISD::SETEQ: return "seteq"; 5265 case ISD::SETGT: return "setgt"; 5266 case ISD::SETGE: return "setge"; 5267 case ISD::SETLT: return "setlt"; 5268 case ISD::SETLE: return "setle"; 5269 case ISD::SETNE: return "setne"; 5270 } 5271 } 5272} 5273 5274const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5275 switch (AM) { 5276 default: 5277 return ""; 5278 case ISD::PRE_INC: 5279 return "<pre-inc>"; 5280 case ISD::PRE_DEC: 5281 return "<pre-dec>"; 5282 case ISD::POST_INC: 5283 return "<post-inc>"; 5284 case ISD::POST_DEC: 5285 return "<post-dec>"; 5286 } 5287} 5288 5289std::string ISD::ArgFlagsTy::getArgFlagsString() { 5290 std::string S = "< "; 5291 5292 if (isZExt()) 5293 S += "zext "; 5294 if (isSExt()) 5295 S += "sext "; 5296 if (isInReg()) 5297 S += "inreg "; 5298 if (isSRet()) 5299 S += "sret "; 5300 if (isByVal()) 5301 S += "byval "; 5302 if (isNest()) 5303 S += "nest "; 5304 if (getByValAlign()) 5305 S += "byval-align:" + utostr(getByValAlign()) + " "; 5306 if (getOrigAlign()) 5307 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5308 if (getByValSize()) 5309 S += "byval-size:" + utostr(getByValSize()) + " "; 5310 return S + ">"; 5311} 5312 5313void SDNode::dump() const { dump(0); } 5314void SDNode::dump(const SelectionDAG *G) const { 5315 print(errs(), G); 5316 errs().flush(); 5317} 5318 5319void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const { 5320 OS << (void*)this << ": "; 5321 5322 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5323 if (i) OS << ","; 5324 if (getValueType(i) == MVT::Other) 5325 OS << "ch"; 5326 else 5327 OS << getValueType(i).getMVTString(); 5328 } 5329 OS << " = " << getOperationName(G); 5330} 5331 5332void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { 5333 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5334 SDNode *Mask = getOperand(2).getNode(); 5335 OS << "<"; 5336 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 5337 if (i) OS << ","; 5338 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 5339 OS << "u"; 5340 else 5341 OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue(); 5342 } 5343 OS << ">"; 5344 } 5345 5346 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5347 OS << '<' << CSDN->getAPIntValue() << '>'; 5348 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5349 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5350 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5351 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5352 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5353 else { 5354 OS << "<APFloat("; 5355 CSDN->getValueAPF().bitcastToAPInt().dump(); 5356 OS << ")>"; 5357 } 5358 } else if (const GlobalAddressSDNode *GADN = 5359 dyn_cast<GlobalAddressSDNode>(this)) { 5360 int64_t offset = GADN->getOffset(); 5361 OS << '<'; 5362 WriteAsOperand(OS, GADN->getGlobal()); 5363 OS << '>'; 5364 if (offset > 0) 5365 OS << " + " << offset; 5366 else 5367 OS << " " << offset; 5368 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5369 OS << "<" << FIDN->getIndex() << ">"; 5370 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5371 OS << "<" << JTDN->getIndex() << ">"; 5372 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5373 int offset = CP->getOffset(); 5374 if (CP->isMachineConstantPoolEntry()) 5375 OS << "<" << *CP->getMachineCPVal() << ">"; 5376 else 5377 OS << "<" << *CP->getConstVal() << ">"; 5378 if (offset > 0) 5379 OS << " + " << offset; 5380 else 5381 OS << " " << offset; 5382 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5383 OS << "<"; 5384 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5385 if (LBB) 5386 OS << LBB->getName() << " "; 5387 OS << (const void*)BBDN->getBasicBlock() << ">"; 5388 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5389 if (G && R->getReg() && 5390 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5391 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5392 } else { 5393 OS << " #" << R->getReg(); 5394 } 5395 } else if (const ExternalSymbolSDNode *ES = 5396 dyn_cast<ExternalSymbolSDNode>(this)) { 5397 OS << "'" << ES->getSymbol() << "'"; 5398 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5399 if (M->getValue()) 5400 OS << "<" << M->getValue() << ">"; 5401 else 5402 OS << "<null>"; 5403 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5404 if (M->MO.getValue()) 5405 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5406 else 5407 OS << "<null:" << M->MO.getOffset() << ">"; 5408 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5409 OS << N->getArgFlags().getArgFlagsString(); 5410 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5411 OS << ":" << N->getVT().getMVTString(); 5412 } 5413 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5414 const Value *SrcValue = LD->getSrcValue(); 5415 int SrcOffset = LD->getSrcValueOffset(); 5416 OS << " <"; 5417 if (SrcValue) 5418 OS << SrcValue; 5419 else 5420 OS << "null"; 5421 OS << ":" << SrcOffset << ">"; 5422 5423 bool doExt = true; 5424 switch (LD->getExtensionType()) { 5425 default: doExt = false; break; 5426 case ISD::EXTLOAD: OS << " <anyext "; break; 5427 case ISD::SEXTLOAD: OS << " <sext "; break; 5428 case ISD::ZEXTLOAD: OS << " <zext "; break; 5429 } 5430 if (doExt) 5431 OS << LD->getMemoryVT().getMVTString() << ">"; 5432 5433 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5434 if (*AM) 5435 OS << " " << AM; 5436 if (LD->isVolatile()) 5437 OS << " <volatile>"; 5438 OS << " alignment=" << LD->getAlignment(); 5439 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5440 const Value *SrcValue = ST->getSrcValue(); 5441 int SrcOffset = ST->getSrcValueOffset(); 5442 OS << " <"; 5443 if (SrcValue) 5444 OS << SrcValue; 5445 else 5446 OS << "null"; 5447 OS << ":" << SrcOffset << ">"; 5448 5449 if (ST->isTruncatingStore()) 5450 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5451 5452 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5453 if (*AM) 5454 OS << " " << AM; 5455 if (ST->isVolatile()) 5456 OS << " <volatile>"; 5457 OS << " alignment=" << ST->getAlignment(); 5458 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5459 const Value *SrcValue = AT->getSrcValue(); 5460 int SrcOffset = AT->getSrcValueOffset(); 5461 OS << " <"; 5462 if (SrcValue) 5463 OS << SrcValue; 5464 else 5465 OS << "null"; 5466 OS << ":" << SrcOffset << ">"; 5467 if (AT->isVolatile()) 5468 OS << " <volatile>"; 5469 OS << " alignment=" << AT->getAlignment(); 5470 } 5471} 5472 5473void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5474 print_types(OS, G); 5475 OS << " "; 5476 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5477 if (i) OS << ", "; 5478 OS << (void*)getOperand(i).getNode(); 5479 if (unsigned RN = getOperand(i).getResNo()) 5480 OS << ":" << RN; 5481 } 5482 print_details(OS, G); 5483} 5484 5485static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5486 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5487 if (N->getOperand(i).getNode()->hasOneUse()) 5488 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5489 else 5490 cerr << "\n" << std::string(indent+2, ' ') 5491 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5492 5493 5494 cerr << "\n" << std::string(indent, ' '); 5495 N->dump(G); 5496} 5497 5498void SelectionDAG::dump() const { 5499 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5500 5501 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5502 I != E; ++I) { 5503 const SDNode *N = I; 5504 if (!N->hasOneUse() && N != getRoot().getNode()) 5505 DumpNodes(N, 2, this); 5506 } 5507 5508 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5509 5510 cerr << "\n\n"; 5511} 5512 5513void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const { 5514 print_types(OS, G); 5515 print_details(OS, G); 5516} 5517 5518typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet; 5519static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, 5520 const SelectionDAG *G, VisitedSDNodeSet &once) { 5521 if (!once.insert(N)) // If we've been here before, return now. 5522 return; 5523 // Dump the current SDNode, but don't end the line yet. 5524 OS << std::string(indent, ' '); 5525 N->printr(OS, G); 5526 // Having printed this SDNode, walk the children: 5527 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5528 const SDNode *child = N->getOperand(i).getNode(); 5529 if (i) OS << ","; 5530 OS << " "; 5531 if (child->getNumOperands() == 0) { 5532 // This child has no grandchildren; print it inline right here. 5533 child->printr(OS, G); 5534 once.insert(child); 5535 } else { // Just the address. FIXME: also print the child's opcode 5536 OS << (void*)child; 5537 if (unsigned RN = N->getOperand(i).getResNo()) 5538 OS << ":" << RN; 5539 } 5540 } 5541 OS << "\n"; 5542 // Dump children that have grandchildren on their own line(s). 5543 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5544 const SDNode *child = N->getOperand(i).getNode(); 5545 DumpNodesr(OS, child, indent+2, G, once); 5546 } 5547} 5548 5549void SDNode::dumpr() const { 5550 VisitedSDNodeSet once; 5551 DumpNodesr(errs(), this, 0, 0, once); 5552 errs().flush(); 5553} 5554 5555const Type *ConstantPoolSDNode::getType() const { 5556 if (isMachineConstantPoolEntry()) 5557 return Val.MachineCPVal->getType(); 5558 return Val.ConstVal->getType(); 5559} 5560 5561bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue, 5562 APInt &SplatUndef, 5563 unsigned &SplatBitSize, 5564 bool &HasAnyUndefs, 5565 unsigned MinSplatBits) { 5566 MVT VT = getValueType(0); 5567 assert(VT.isVector() && "Expected a vector type"); 5568 unsigned sz = VT.getSizeInBits(); 5569 if (MinSplatBits > sz) 5570 return false; 5571 5572 SplatValue = APInt(sz, 0); 5573 SplatUndef = APInt(sz, 0); 5574 5575 // Get the bits. Bits with undefined values (when the corresponding element 5576 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared 5577 // in SplatValue. If any of the values are not constant, give up and return 5578 // false. 5579 unsigned int nOps = getNumOperands(); 5580 assert(nOps > 0 && "isConstantSplat has 0-size build vector"); 5581 unsigned EltBitSize = VT.getVectorElementType().getSizeInBits(); 5582 for (unsigned i = 0; i < nOps; ++i) { 5583 SDValue OpVal = getOperand(i); 5584 unsigned BitPos = i * EltBitSize; 5585 5586 if (OpVal.getOpcode() == ISD::UNDEF) 5587 SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos +EltBitSize); 5588 else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) 5589 SplatValue |= APInt(CN->getAPIntValue()).zextOrTrunc(sz) << BitPos; 5590 else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) 5591 SplatValue |= CN->getValueAPF().bitcastToAPInt().zextOrTrunc(sz) <<BitPos; 5592 else 5593 return false; 5594 } 5595 5596 // The build_vector is all constants or undefs. Find the smallest element 5597 // size that splats the vector. 5598 5599 HasAnyUndefs = (SplatUndef != 0); 5600 while (sz > 8) { 5601 5602 unsigned HalfSize = sz / 2; 5603 APInt HighValue = APInt(SplatValue).lshr(HalfSize).trunc(HalfSize); 5604 APInt LowValue = APInt(SplatValue).trunc(HalfSize); 5605 APInt HighUndef = APInt(SplatUndef).lshr(HalfSize).trunc(HalfSize); 5606 APInt LowUndef = APInt(SplatUndef).trunc(HalfSize); 5607 5608 // If the two halves do not match (ignoring undef bits), stop here. 5609 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) || 5610 MinSplatBits > HalfSize) 5611 break; 5612 5613 SplatValue = HighValue | LowValue; 5614 SplatUndef = HighUndef & LowUndef; 5615 5616 sz = HalfSize; 5617 } 5618 5619 SplatBitSize = sz; 5620 return true; 5621} 5622