SelectionDAG.cpp revision c885165e664f3b465403e1b6ce57ba63f57c5f0c
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/ADT/SetVector.h" 37#include "llvm/ADT/SmallPtrSet.h" 38#include "llvm/ADT/SmallSet.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/ADT/StringExtras.h" 41#include <algorithm> 42#include <cmath> 43using namespace llvm; 44 45/// makeVTList - Return an instance of the SDVTList struct initialized with the 46/// specified members. 47static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 48 SDVTList Res = {VTs, NumVTs}; 49 return Res; 50} 51 52static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 53 switch (VT.getSimpleVT()) { 54 default: assert(0 && "Unknown FP format"); 55 case MVT::f32: return &APFloat::IEEEsingle; 56 case MVT::f64: return &APFloat::IEEEdouble; 57 case MVT::f80: return &APFloat::x87DoubleExtended; 58 case MVT::f128: return &APFloat::IEEEquad; 59 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 60 } 61} 62 63SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 64 65//===----------------------------------------------------------------------===// 66// ConstantFPSDNode Class 67//===----------------------------------------------------------------------===// 68 69/// isExactlyValue - We don't rely on operator== working on double values, as 70/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 71/// As such, this method can be used to do an exact bit-for-bit comparison of 72/// two floating point values. 73bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 74 return getValueAPF().bitwiseIsEqual(V); 75} 76 77bool ConstantFPSDNode::isValueValidForType(MVT VT, 78 const APFloat& Val) { 79 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 80 81 // PPC long double cannot be converted to any other type. 82 if (VT == MVT::ppcf128 || 83 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 84 return false; 85 86 // convert modifies in place, so make a copy. 87 APFloat Val2 = APFloat(Val); 88 bool losesInfo; 89 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 90 &losesInfo); 91 return !losesInfo; 92} 93 94//===----------------------------------------------------------------------===// 95// ISD Namespace 96//===----------------------------------------------------------------------===// 97 98/// isBuildVectorAllOnes - Return true if the specified node is a 99/// BUILD_VECTOR where all of the elements are ~0 or undef. 100bool ISD::isBuildVectorAllOnes(const SDNode *N) { 101 // Look through a bit convert. 102 if (N->getOpcode() == ISD::BIT_CONVERT) 103 N = N->getOperand(0).getNode(); 104 105 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 106 107 unsigned i = 0, e = N->getNumOperands(); 108 109 // Skip over all of the undef values. 110 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 111 ++i; 112 113 // Do not accept an all-undef vector. 114 if (i == e) return false; 115 116 // Do not accept build_vectors that aren't all constants or which have non-~0 117 // elements. 118 SDValue NotZero = N->getOperand(i); 119 if (isa<ConstantSDNode>(NotZero)) { 120 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 121 return false; 122 } else if (isa<ConstantFPSDNode>(NotZero)) { 123 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 124 bitcastToAPInt().isAllOnesValue()) 125 return false; 126 } else 127 return false; 128 129 // Okay, we have at least one ~0 value, check to see if the rest match or are 130 // undefs. 131 for (++i; i != e; ++i) 132 if (N->getOperand(i) != NotZero && 133 N->getOperand(i).getOpcode() != ISD::UNDEF) 134 return false; 135 return true; 136} 137 138 139/// isBuildVectorAllZeros - Return true if the specified node is a 140/// BUILD_VECTOR where all of the elements are 0 or undef. 141bool ISD::isBuildVectorAllZeros(const SDNode *N) { 142 // Look through a bit convert. 143 if (N->getOpcode() == ISD::BIT_CONVERT) 144 N = N->getOperand(0).getNode(); 145 146 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 147 148 unsigned i = 0, e = N->getNumOperands(); 149 150 // Skip over all of the undef values. 151 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 152 ++i; 153 154 // Do not accept an all-undef vector. 155 if (i == e) return false; 156 157 // Do not accept build_vectors that aren't all constants or which have non-~0 158 // elements. 159 SDValue Zero = N->getOperand(i); 160 if (isa<ConstantSDNode>(Zero)) { 161 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 162 return false; 163 } else if (isa<ConstantFPSDNode>(Zero)) { 164 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 165 return false; 166 } else 167 return false; 168 169 // Okay, we have at least one ~0 value, check to see if the rest match or are 170 // undefs. 171 for (++i; i != e; ++i) 172 if (N->getOperand(i) != Zero && 173 N->getOperand(i).getOpcode() != ISD::UNDEF) 174 return false; 175 return true; 176} 177 178/// isScalarToVector - Return true if the specified node is a 179/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 180/// element is not an undef. 181bool ISD::isScalarToVector(const SDNode *N) { 182 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 183 return true; 184 185 if (N->getOpcode() != ISD::BUILD_VECTOR) 186 return false; 187 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 188 return false; 189 unsigned NumElems = N->getNumOperands(); 190 for (unsigned i = 1; i < NumElems; ++i) { 191 SDValue V = N->getOperand(i); 192 if (V.getOpcode() != ISD::UNDEF) 193 return false; 194 } 195 return true; 196} 197 198 199/// isDebugLabel - Return true if the specified node represents a debug 200/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 201bool ISD::isDebugLabel(const SDNode *N) { 202 SDValue Zero; 203 if (N->getOpcode() == ISD::DBG_LABEL) 204 return true; 205 if (N->isMachineOpcode() && 206 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 207 return true; 208 return false; 209} 210 211/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 212/// when given the operation for (X op Y). 213ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 214 // To perform this operation, we just need to swap the L and G bits of the 215 // operation. 216 unsigned OldL = (Operation >> 2) & 1; 217 unsigned OldG = (Operation >> 1) & 1; 218 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 219 (OldL << 1) | // New G bit 220 (OldG << 2)); // New L bit. 221} 222 223/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 224/// 'op' is a valid SetCC operation. 225ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 226 unsigned Operation = Op; 227 if (isInteger) 228 Operation ^= 7; // Flip L, G, E bits, but not U. 229 else 230 Operation ^= 15; // Flip all of the condition bits. 231 232 if (Operation > ISD::SETTRUE2) 233 Operation &= ~8; // Don't let N and U bits get set. 234 235 return ISD::CondCode(Operation); 236} 237 238 239/// isSignedOp - For an integer comparison, return 1 if the comparison is a 240/// signed operation and 2 if the result is an unsigned comparison. Return zero 241/// if the operation does not depend on the sign of the input (setne and seteq). 242static int isSignedOp(ISD::CondCode Opcode) { 243 switch (Opcode) { 244 default: assert(0 && "Illegal integer setcc operation!"); 245 case ISD::SETEQ: 246 case ISD::SETNE: return 0; 247 case ISD::SETLT: 248 case ISD::SETLE: 249 case ISD::SETGT: 250 case ISD::SETGE: return 1; 251 case ISD::SETULT: 252 case ISD::SETULE: 253 case ISD::SETUGT: 254 case ISD::SETUGE: return 2; 255 } 256} 257 258/// getSetCCOrOperation - Return the result of a logical OR between different 259/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 260/// returns SETCC_INVALID if it is not possible to represent the resultant 261/// comparison. 262ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 263 bool isInteger) { 264 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 265 // Cannot fold a signed integer setcc with an unsigned integer setcc. 266 return ISD::SETCC_INVALID; 267 268 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 269 270 // If the N and U bits get set then the resultant comparison DOES suddenly 271 // care about orderedness, and is true when ordered. 272 if (Op > ISD::SETTRUE2) 273 Op &= ~16; // Clear the U bit if the N bit is set. 274 275 // Canonicalize illegal integer setcc's. 276 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 277 Op = ISD::SETNE; 278 279 return ISD::CondCode(Op); 280} 281 282/// getSetCCAndOperation - Return the result of a logical AND between different 283/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 284/// function returns zero if it is not possible to represent the resultant 285/// comparison. 286ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 287 bool isInteger) { 288 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 289 // Cannot fold a signed setcc with an unsigned setcc. 290 return ISD::SETCC_INVALID; 291 292 // Combine all of the condition bits. 293 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 294 295 // Canonicalize illegal integer setcc's. 296 if (isInteger) { 297 switch (Result) { 298 default: break; 299 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 300 case ISD::SETOEQ: // SETEQ & SETU[LG]E 301 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 302 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 303 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 304 } 305 } 306 307 return Result; 308} 309 310const TargetMachine &SelectionDAG::getTarget() const { 311 return MF->getTarget(); 312} 313 314//===----------------------------------------------------------------------===// 315// SDNode Profile Support 316//===----------------------------------------------------------------------===// 317 318/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 319/// 320static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 321 ID.AddInteger(OpC); 322} 323 324/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 325/// solely with their pointer. 326static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 327 ID.AddPointer(VTList.VTs); 328} 329 330/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 331/// 332static void AddNodeIDOperands(FoldingSetNodeID &ID, 333 const SDValue *Ops, unsigned NumOps) { 334 for (; NumOps; --NumOps, ++Ops) { 335 ID.AddPointer(Ops->getNode()); 336 ID.AddInteger(Ops->getResNo()); 337 } 338} 339 340/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 341/// 342static void AddNodeIDOperands(FoldingSetNodeID &ID, 343 const SDUse *Ops, unsigned NumOps) { 344 for (; NumOps; --NumOps, ++Ops) { 345 ID.AddPointer(Ops->getNode()); 346 ID.AddInteger(Ops->getResNo()); 347 } 348} 349 350static void AddNodeIDNode(FoldingSetNodeID &ID, 351 unsigned short OpC, SDVTList VTList, 352 const SDValue *OpList, unsigned N) { 353 AddNodeIDOpcode(ID, OpC); 354 AddNodeIDValueTypes(ID, VTList); 355 AddNodeIDOperands(ID, OpList, N); 356} 357 358/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 359/// the NodeID data. 360static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 361 switch (N->getOpcode()) { 362 default: break; // Normal nodes don't need extra info. 363 case ISD::ARG_FLAGS: 364 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 365 break; 366 case ISD::TargetConstant: 367 case ISD::Constant: 368 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 369 break; 370 case ISD::TargetConstantFP: 371 case ISD::ConstantFP: { 372 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 373 break; 374 } 375 case ISD::TargetGlobalAddress: 376 case ISD::GlobalAddress: 377 case ISD::TargetGlobalTLSAddress: 378 case ISD::GlobalTLSAddress: { 379 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 380 ID.AddPointer(GA->getGlobal()); 381 ID.AddInteger(GA->getOffset()); 382 break; 383 } 384 case ISD::BasicBlock: 385 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 386 break; 387 case ISD::Register: 388 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 389 break; 390 case ISD::DBG_STOPPOINT: { 391 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 392 ID.AddInteger(DSP->getLine()); 393 ID.AddInteger(DSP->getColumn()); 394 ID.AddPointer(DSP->getCompileUnit()); 395 break; 396 } 397 case ISD::SRCVALUE: 398 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 399 break; 400 case ISD::MEMOPERAND: { 401 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 402 MO.Profile(ID); 403 break; 404 } 405 case ISD::FrameIndex: 406 case ISD::TargetFrameIndex: 407 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 408 break; 409 case ISD::JumpTable: 410 case ISD::TargetJumpTable: 411 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 412 break; 413 case ISD::ConstantPool: 414 case ISD::TargetConstantPool: { 415 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 416 ID.AddInteger(CP->getAlignment()); 417 ID.AddInteger(CP->getOffset()); 418 if (CP->isMachineConstantPoolEntry()) 419 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 420 else 421 ID.AddPointer(CP->getConstVal()); 422 break; 423 } 424 case ISD::CALL: { 425 const CallSDNode *Call = cast<CallSDNode>(N); 426 ID.AddInteger(Call->getCallingConv()); 427 ID.AddInteger(Call->isVarArg()); 428 break; 429 } 430 case ISD::LOAD: { 431 const LoadSDNode *LD = cast<LoadSDNode>(N); 432 ID.AddInteger(LD->getMemoryVT().getRawBits()); 433 ID.AddInteger(LD->getRawSubclassData()); 434 break; 435 } 436 case ISD::STORE: { 437 const StoreSDNode *ST = cast<StoreSDNode>(N); 438 ID.AddInteger(ST->getMemoryVT().getRawBits()); 439 ID.AddInteger(ST->getRawSubclassData()); 440 break; 441 } 442 case ISD::ATOMIC_CMP_SWAP: 443 case ISD::ATOMIC_SWAP: 444 case ISD::ATOMIC_LOAD_ADD: 445 case ISD::ATOMIC_LOAD_SUB: 446 case ISD::ATOMIC_LOAD_AND: 447 case ISD::ATOMIC_LOAD_OR: 448 case ISD::ATOMIC_LOAD_XOR: 449 case ISD::ATOMIC_LOAD_NAND: 450 case ISD::ATOMIC_LOAD_MIN: 451 case ISD::ATOMIC_LOAD_MAX: 452 case ISD::ATOMIC_LOAD_UMIN: 453 case ISD::ATOMIC_LOAD_UMAX: { 454 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 455 ID.AddInteger(AT->getMemoryVT().getRawBits()); 456 ID.AddInteger(AT->getRawSubclassData()); 457 break; 458 } 459 } // end switch (N->getOpcode()) 460} 461 462/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 463/// data. 464static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 465 AddNodeIDOpcode(ID, N->getOpcode()); 466 // Add the return value info. 467 AddNodeIDValueTypes(ID, N->getVTList()); 468 // Add the operand info. 469 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 470 471 // Handle SDNode leafs with special info. 472 AddNodeIDCustom(ID, N); 473} 474 475/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 476/// the CSE map that carries alignment, volatility, indexing mode, and 477/// extension/truncation information. 478/// 479static inline unsigned 480encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, 481 bool isVolatile, unsigned Alignment) { 482 assert((ConvType & 3) == ConvType && 483 "ConvType may not require more than 2 bits!"); 484 assert((AM & 7) == AM && 485 "AM may not require more than 3 bits!"); 486 return ConvType | 487 (AM << 2) | 488 (isVolatile << 5) | 489 ((Log2_32(Alignment) + 1) << 6); 490} 491 492//===----------------------------------------------------------------------===// 493// SelectionDAG Class 494//===----------------------------------------------------------------------===// 495 496/// doNotCSE - Return true if CSE should not be performed for this node. 497static bool doNotCSE(SDNode *N) { 498 if (N->getValueType(0) == MVT::Flag) 499 return true; // Never CSE anything that produces a flag. 500 501 switch (N->getOpcode()) { 502 default: break; 503 case ISD::HANDLENODE: 504 case ISD::DBG_LABEL: 505 case ISD::DBG_STOPPOINT: 506 case ISD::EH_LABEL: 507 case ISD::DECLARE: 508 return true; // Never CSE these nodes. 509 } 510 511 // Check that remaining values produced are not flags. 512 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 513 if (N->getValueType(i) == MVT::Flag) 514 return true; // Never CSE anything that produces a flag. 515 516 return false; 517} 518 519/// RemoveDeadNodes - This method deletes all unreachable nodes in the 520/// SelectionDAG. 521void SelectionDAG::RemoveDeadNodes() { 522 // Create a dummy node (which is not added to allnodes), that adds a reference 523 // to the root node, preventing it from being deleted. 524 HandleSDNode Dummy(getRoot()); 525 526 SmallVector<SDNode*, 128> DeadNodes; 527 528 // Add all obviously-dead nodes to the DeadNodes worklist. 529 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 530 if (I->use_empty()) 531 DeadNodes.push_back(I); 532 533 RemoveDeadNodes(DeadNodes); 534 535 // If the root changed (e.g. it was a dead load, update the root). 536 setRoot(Dummy.getValue()); 537} 538 539/// RemoveDeadNodes - This method deletes the unreachable nodes in the 540/// given list, and any nodes that become unreachable as a result. 541void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 542 DAGUpdateListener *UpdateListener) { 543 544 // Process the worklist, deleting the nodes and adding their uses to the 545 // worklist. 546 while (!DeadNodes.empty()) { 547 SDNode *N = DeadNodes.pop_back_val(); 548 549 if (UpdateListener) 550 UpdateListener->NodeDeleted(N, 0); 551 552 // Take the node out of the appropriate CSE map. 553 RemoveNodeFromCSEMaps(N); 554 555 // Next, brutally remove the operand list. This is safe to do, as there are 556 // no cycles in the graph. 557 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 558 SDUse &Use = *I++; 559 SDNode *Operand = Use.getNode(); 560 Use.set(SDValue()); 561 562 // Now that we removed this operand, see if there are no uses of it left. 563 if (Operand->use_empty()) 564 DeadNodes.push_back(Operand); 565 } 566 567 DeallocateNode(N); 568 } 569} 570 571void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 572 SmallVector<SDNode*, 16> DeadNodes(1, N); 573 RemoveDeadNodes(DeadNodes, UpdateListener); 574} 575 576void SelectionDAG::DeleteNode(SDNode *N) { 577 // First take this out of the appropriate CSE map. 578 RemoveNodeFromCSEMaps(N); 579 580 // Finally, remove uses due to operands of this node, remove from the 581 // AllNodes list, and delete the node. 582 DeleteNodeNotInCSEMaps(N); 583} 584 585void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 586 assert(N != AllNodes.begin() && "Cannot delete the entry node!"); 587 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 588 589 // Drop all of the operands and decrement used node's use counts. 590 N->DropOperands(); 591 592 DeallocateNode(N); 593} 594 595void SelectionDAG::DeallocateNode(SDNode *N) { 596 if (N->OperandsNeedDelete) 597 delete[] N->OperandList; 598 599 // Set the opcode to DELETED_NODE to help catch bugs when node 600 // memory is reallocated. 601 N->NodeType = ISD::DELETED_NODE; 602 603 NodeAllocator.Deallocate(AllNodes.remove(N)); 604} 605 606/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 607/// correspond to it. This is useful when we're about to delete or repurpose 608/// the node. We don't want future request for structurally identical nodes 609/// to return N anymore. 610bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 611 bool Erased = false; 612 switch (N->getOpcode()) { 613 case ISD::EntryToken: 614 assert(0 && "EntryToken should not be in CSEMaps!"); 615 return false; 616 case ISD::HANDLENODE: return false; // noop. 617 case ISD::CONDCODE: 618 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 619 "Cond code doesn't exist!"); 620 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 621 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 622 break; 623 case ISD::ExternalSymbol: 624 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 625 break; 626 case ISD::TargetExternalSymbol: 627 Erased = 628 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 629 break; 630 case ISD::VALUETYPE: { 631 MVT VT = cast<VTSDNode>(N)->getVT(); 632 if (VT.isExtended()) { 633 Erased = ExtendedValueTypeNodes.erase(VT); 634 } else { 635 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 636 ValueTypeNodes[VT.getSimpleVT()] = 0; 637 } 638 break; 639 } 640 default: 641 // Remove it from the CSE Map. 642 Erased = CSEMap.RemoveNode(N); 643 break; 644 } 645#ifndef NDEBUG 646 // Verify that the node was actually in one of the CSE maps, unless it has a 647 // flag result (which cannot be CSE'd) or is one of the special cases that are 648 // not subject to CSE. 649 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 650 !N->isMachineOpcode() && !doNotCSE(N)) { 651 N->dump(this); 652 cerr << "\n"; 653 assert(0 && "Node is not in map!"); 654 } 655#endif 656 return Erased; 657} 658 659/// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE 660/// maps and modified in place. Add it back to the CSE maps, unless an identical 661/// node already exists, in which case transfer all its users to the existing 662/// node. This transfer can potentially trigger recursive merging. 663/// 664void 665SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N, 666 DAGUpdateListener *UpdateListener) { 667 // For node types that aren't CSE'd, just act as if no identical node 668 // already exists. 669 if (!doNotCSE(N)) { 670 SDNode *Existing = CSEMap.GetOrInsertNode(N); 671 if (Existing != N) { 672 // If there was already an existing matching node, use ReplaceAllUsesWith 673 // to replace the dead one with the existing one. This can cause 674 // recursive merging of other unrelated nodes down the line. 675 ReplaceAllUsesWith(N, Existing, UpdateListener); 676 677 // N is now dead. Inform the listener if it exists and delete it. 678 if (UpdateListener) 679 UpdateListener->NodeDeleted(N, Existing); 680 DeleteNodeNotInCSEMaps(N); 681 return; 682 } 683 } 684 685 // If the node doesn't already exist, we updated it. Inform a listener if 686 // it exists. 687 if (UpdateListener) 688 UpdateListener->NodeUpdated(N); 689} 690 691/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 692/// were replaced with those specified. If this node is never memoized, 693/// return null, otherwise return a pointer to the slot it would take. If a 694/// node already exists with these operands, the slot will be non-null. 695SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 696 void *&InsertPos) { 697 if (doNotCSE(N)) 698 return 0; 699 700 SDValue Ops[] = { Op }; 701 FoldingSetNodeID ID; 702 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 703 AddNodeIDCustom(ID, N); 704 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 705} 706 707/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 708/// were replaced with those specified. If this node is never memoized, 709/// return null, otherwise return a pointer to the slot it would take. If a 710/// node already exists with these operands, the slot will be non-null. 711SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 712 SDValue Op1, SDValue Op2, 713 void *&InsertPos) { 714 if (doNotCSE(N)) 715 return 0; 716 717 SDValue Ops[] = { Op1, Op2 }; 718 FoldingSetNodeID ID; 719 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 720 AddNodeIDCustom(ID, N); 721 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 722} 723 724 725/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 726/// were replaced with those specified. If this node is never memoized, 727/// return null, otherwise return a pointer to the slot it would take. If a 728/// node already exists with these operands, the slot will be non-null. 729SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 730 const SDValue *Ops,unsigned NumOps, 731 void *&InsertPos) { 732 if (doNotCSE(N)) 733 return 0; 734 735 FoldingSetNodeID ID; 736 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 737 AddNodeIDCustom(ID, N); 738 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 739} 740 741/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 742void SelectionDAG::VerifyNode(SDNode *N) { 743 switch (N->getOpcode()) { 744 default: 745 break; 746 case ISD::BUILD_PAIR: { 747 MVT VT = N->getValueType(0); 748 assert(N->getNumValues() == 1 && "Too many results!"); 749 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 750 "Wrong return type!"); 751 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 752 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 753 "Mismatched operand types!"); 754 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 755 "Wrong operand type!"); 756 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 757 "Wrong return type size"); 758 break; 759 } 760 case ISD::BUILD_VECTOR: { 761 assert(N->getNumValues() == 1 && "Too many results!"); 762 assert(N->getValueType(0).isVector() && "Wrong return type!"); 763 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 764 "Wrong number of operands!"); 765 MVT EltVT = N->getValueType(0).getVectorElementType(); 766 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 767 assert((I->getValueType() == EltVT || 768 (EltVT.isInteger() && I->getValueType().isInteger() && 769 EltVT.bitsLE(I->getValueType()))) && 770 "Wrong operand type!"); 771 break; 772 } 773 } 774} 775 776/// getMVTAlignment - Compute the default alignment value for the 777/// given type. 778/// 779unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 780 const Type *Ty = VT == MVT::iPTR ? 781 PointerType::get(Type::Int8Ty, 0) : 782 VT.getTypeForMVT(); 783 784 return TLI.getTargetData()->getABITypeAlignment(Ty); 785} 786 787// EntryNode could meaningfully have debug info if we can find it... 788SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 789 : TLI(tli), FLI(fli), DW(0), 790 EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(), 791 getVTList(MVT::Other)), Root(getEntryNode()) { 792 AllNodes.push_back(&EntryNode); 793} 794 795void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi, 796 DwarfWriter *dw) { 797 MF = &mf; 798 MMI = mmi; 799 DW = dw; 800} 801 802SelectionDAG::~SelectionDAG() { 803 allnodes_clear(); 804} 805 806void SelectionDAG::allnodes_clear() { 807 assert(&*AllNodes.begin() == &EntryNode); 808 AllNodes.remove(AllNodes.begin()); 809 while (!AllNodes.empty()) 810 DeallocateNode(AllNodes.begin()); 811} 812 813void SelectionDAG::clear() { 814 allnodes_clear(); 815 OperandAllocator.Reset(); 816 CSEMap.clear(); 817 818 ExtendedValueTypeNodes.clear(); 819 ExternalSymbols.clear(); 820 TargetExternalSymbols.clear(); 821 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 822 static_cast<CondCodeSDNode*>(0)); 823 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 824 static_cast<SDNode*>(0)); 825 826 EntryNode.UseList = 0; 827 AllNodes.push_back(&EntryNode); 828 Root = getEntryNode(); 829} 830 831SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { 832 if (Op.getValueType() == VT) return Op; 833 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 834 VT.getSizeInBits()); 835 return getNode(ISD::AND, DL, Op.getValueType(), Op, 836 getConstant(Imm, Op.getValueType())); 837} 838 839/// getNOT - Create a bitwise NOT operation as (XOR Val, -1). 840/// 841SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) { 842 SDValue NegOne; 843 if (VT.isVector()) { 844 MVT EltVT = VT.getVectorElementType(); 845 SDValue NegOneElt = 846 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), EltVT); 847 std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOneElt); 848 NegOne = getNode(ISD::BUILD_VECTOR, DL, VT, &NegOnes[0], NegOnes.size()); 849 } else { 850 NegOne = getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 851 } 852 return getNode(ISD::XOR, DL, VT, Val, NegOne); 853} 854 855SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 856 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 857 assert((EltVT.getSizeInBits() >= 64 || 858 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) && 859 "getConstant with a uint64_t value that doesn't fit in the type!"); 860 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 861} 862 863SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 864 return getConstant(*ConstantInt::get(Val), VT, isT); 865} 866 867SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 868 assert(VT.isInteger() && "Cannot create FP integer constant!"); 869 870 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 871 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 872 "APInt size does not match type size!"); 873 874 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 875 FoldingSetNodeID ID; 876 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 877 ID.AddPointer(&Val); 878 void *IP = 0; 879 SDNode *N = NULL; 880 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 881 if (!VT.isVector()) 882 return SDValue(N, 0); 883 if (!N) { 884 N = NodeAllocator.Allocate<ConstantSDNode>(); 885 new (N) ConstantSDNode(isT, &Val, EltVT); 886 CSEMap.InsertNode(N, IP); 887 AllNodes.push_back(N); 888 } 889 890 SDValue Result(N, 0); 891 if (VT.isVector()) { 892 SmallVector<SDValue, 8> Ops; 893 Ops.assign(VT.getVectorNumElements(), Result); 894 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 895 VT, &Ops[0], Ops.size()); 896 } 897 return Result; 898} 899 900SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 901 return getConstant(Val, TLI.getPointerTy(), isTarget); 902} 903 904 905SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 906 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 907} 908 909SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 910 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 911 912 MVT EltVT = 913 VT.isVector() ? VT.getVectorElementType() : VT; 914 915 // Do the map lookup using the actual bit pattern for the floating point 916 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 917 // we don't have issues with SNANs. 918 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 919 FoldingSetNodeID ID; 920 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 921 ID.AddPointer(&V); 922 void *IP = 0; 923 SDNode *N = NULL; 924 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 925 if (!VT.isVector()) 926 return SDValue(N, 0); 927 if (!N) { 928 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 929 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 930 CSEMap.InsertNode(N, IP); 931 AllNodes.push_back(N); 932 } 933 934 SDValue Result(N, 0); 935 if (VT.isVector()) { 936 SmallVector<SDValue, 8> Ops; 937 Ops.assign(VT.getVectorNumElements(), Result); 938 // FIXME DebugLoc info might be appropriate here 939 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 940 VT, &Ops[0], Ops.size()); 941 } 942 return Result; 943} 944 945SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 946 MVT EltVT = 947 VT.isVector() ? VT.getVectorElementType() : VT; 948 if (EltVT==MVT::f32) 949 return getConstantFP(APFloat((float)Val), VT, isTarget); 950 else 951 return getConstantFP(APFloat(Val), VT, isTarget); 952} 953 954SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 955 MVT VT, int64_t Offset, 956 bool isTargetGA) { 957 unsigned Opc; 958 959 // Truncate (with sign-extension) the offset value to the pointer size. 960 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 961 if (BitWidth < 64) 962 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 963 964 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 965 if (!GVar) { 966 // If GV is an alias then use the aliasee for determining thread-localness. 967 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 968 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 969 } 970 971 if (GVar && GVar->isThreadLocal()) 972 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 973 else 974 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 975 976 FoldingSetNodeID ID; 977 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 978 ID.AddPointer(GV); 979 ID.AddInteger(Offset); 980 void *IP = 0; 981 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 982 return SDValue(E, 0); 983 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 984 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 985 CSEMap.InsertNode(N, IP); 986 AllNodes.push_back(N); 987 return SDValue(N, 0); 988} 989 990SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 991 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 992 FoldingSetNodeID ID; 993 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 994 ID.AddInteger(FI); 995 void *IP = 0; 996 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 997 return SDValue(E, 0); 998 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 999 new (N) FrameIndexSDNode(FI, VT, isTarget); 1000 CSEMap.InsertNode(N, IP); 1001 AllNodes.push_back(N); 1002 return SDValue(N, 0); 1003} 1004 1005SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 1006 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1007 FoldingSetNodeID ID; 1008 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1009 ID.AddInteger(JTI); 1010 void *IP = 0; 1011 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1012 return SDValue(E, 0); 1013 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1014 new (N) JumpTableSDNode(JTI, VT, isTarget); 1015 CSEMap.InsertNode(N, IP); 1016 AllNodes.push_back(N); 1017 return SDValue(N, 0); 1018} 1019 1020SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1021 unsigned Alignment, int Offset, 1022 bool isTarget) { 1023 if (Alignment == 0) 1024 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1025 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1026 FoldingSetNodeID ID; 1027 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1028 ID.AddInteger(Alignment); 1029 ID.AddInteger(Offset); 1030 ID.AddPointer(C); 1031 void *IP = 0; 1032 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1033 return SDValue(E, 0); 1034 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1035 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1036 CSEMap.InsertNode(N, IP); 1037 AllNodes.push_back(N); 1038 return SDValue(N, 0); 1039} 1040 1041 1042SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1043 unsigned Alignment, int Offset, 1044 bool isTarget) { 1045 if (Alignment == 0) 1046 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1047 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1048 FoldingSetNodeID ID; 1049 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1050 ID.AddInteger(Alignment); 1051 ID.AddInteger(Offset); 1052 C->AddSelectionDAGCSEId(ID); 1053 void *IP = 0; 1054 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1055 return SDValue(E, 0); 1056 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1057 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1058 CSEMap.InsertNode(N, IP); 1059 AllNodes.push_back(N); 1060 return SDValue(N, 0); 1061} 1062 1063SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1064 FoldingSetNodeID ID; 1065 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1066 ID.AddPointer(MBB); 1067 void *IP = 0; 1068 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1069 return SDValue(E, 0); 1070 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1071 new (N) BasicBlockSDNode(MBB); 1072 CSEMap.InsertNode(N, IP); 1073 AllNodes.push_back(N); 1074 return SDValue(N, 0); 1075} 1076 1077SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1078 FoldingSetNodeID ID; 1079 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1080 ID.AddInteger(Flags.getRawBits()); 1081 void *IP = 0; 1082 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1083 return SDValue(E, 0); 1084 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1085 new (N) ARG_FLAGSSDNode(Flags); 1086 CSEMap.InsertNode(N, IP); 1087 AllNodes.push_back(N); 1088 return SDValue(N, 0); 1089} 1090 1091SDValue SelectionDAG::getValueType(MVT VT) { 1092 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1093 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1094 1095 SDNode *&N = VT.isExtended() ? 1096 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1097 1098 if (N) return SDValue(N, 0); 1099 N = NodeAllocator.Allocate<VTSDNode>(); 1100 new (N) VTSDNode(VT); 1101 AllNodes.push_back(N); 1102 return SDValue(N, 0); 1103} 1104 1105SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1106 SDNode *&N = ExternalSymbols[Sym]; 1107 if (N) return SDValue(N, 0); 1108 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1109 new (N) ExternalSymbolSDNode(false, Sym, VT); 1110 AllNodes.push_back(N); 1111 return SDValue(N, 0); 1112} 1113 1114SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1115 SDNode *&N = TargetExternalSymbols[Sym]; 1116 if (N) return SDValue(N, 0); 1117 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1118 new (N) ExternalSymbolSDNode(true, Sym, VT); 1119 AllNodes.push_back(N); 1120 return SDValue(N, 0); 1121} 1122 1123SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1124 if ((unsigned)Cond >= CondCodeNodes.size()) 1125 CondCodeNodes.resize(Cond+1); 1126 1127 if (CondCodeNodes[Cond] == 0) { 1128 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1129 new (N) CondCodeSDNode(Cond); 1130 CondCodeNodes[Cond] = N; 1131 AllNodes.push_back(N); 1132 } 1133 return SDValue(CondCodeNodes[Cond], 0); 1134} 1135 1136SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl, 1137 SDValue Val, SDValue DTy, 1138 SDValue STy, SDValue Rnd, SDValue Sat, 1139 ISD::CvtCode Code) { 1140 // If the src and dest types are the same and the conversion is between 1141 // integer types of the same sign or two floats, no conversion is necessary. 1142 if (DTy == STy && 1143 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF)) 1144 return Val; 1145 1146 FoldingSetNodeID ID; 1147 void* IP = 0; 1148 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1149 return SDValue(E, 0); 1150 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1151 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1152 new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code); 1153 CSEMap.InsertNode(N, IP); 1154 AllNodes.push_back(N); 1155 return SDValue(N, 0); 1156} 1157 1158SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1159 FoldingSetNodeID ID; 1160 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1161 ID.AddInteger(RegNo); 1162 void *IP = 0; 1163 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1164 return SDValue(E, 0); 1165 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1166 new (N) RegisterSDNode(RegNo, VT); 1167 CSEMap.InsertNode(N, IP); 1168 AllNodes.push_back(N); 1169 return SDValue(N, 0); 1170} 1171 1172SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1173 unsigned Line, unsigned Col, 1174 Value *CU) { 1175 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1176 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1177 AllNodes.push_back(N); 1178 return SDValue(N, 0); 1179} 1180 1181SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, 1182 SDValue Root, 1183 unsigned LabelID) { 1184 FoldingSetNodeID ID; 1185 SDValue Ops[] = { Root }; 1186 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1187 ID.AddInteger(LabelID); 1188 void *IP = 0; 1189 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1190 return SDValue(E, 0); 1191 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1192 new (N) LabelSDNode(Opcode, dl, Root, LabelID); 1193 CSEMap.InsertNode(N, IP); 1194 AllNodes.push_back(N); 1195 return SDValue(N, 0); 1196} 1197 1198SDValue SelectionDAG::getSrcValue(const Value *V) { 1199 assert((!V || isa<PointerType>(V->getType())) && 1200 "SrcValue is not a pointer?"); 1201 1202 FoldingSetNodeID ID; 1203 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1204 ID.AddPointer(V); 1205 1206 void *IP = 0; 1207 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1208 return SDValue(E, 0); 1209 1210 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1211 new (N) SrcValueSDNode(V); 1212 CSEMap.InsertNode(N, IP); 1213 AllNodes.push_back(N); 1214 return SDValue(N, 0); 1215} 1216 1217SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1218#ifndef NDEBUG 1219 const Value *v = MO.getValue(); 1220 assert((!v || isa<PointerType>(v->getType())) && 1221 "SrcValue is not a pointer?"); 1222#endif 1223 1224 FoldingSetNodeID ID; 1225 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1226 MO.Profile(ID); 1227 1228 void *IP = 0; 1229 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1230 return SDValue(E, 0); 1231 1232 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1233 new (N) MemOperandSDNode(MO); 1234 CSEMap.InsertNode(N, IP); 1235 AllNodes.push_back(N); 1236 return SDValue(N, 0); 1237} 1238 1239/// getShiftAmountOperand - Return the specified value casted to 1240/// the target's desired shift amount type. 1241SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { 1242 MVT OpTy = Op.getValueType(); 1243 MVT ShTy = TLI.getShiftAmountTy(); 1244 if (OpTy == ShTy || OpTy.isVector()) return Op; 1245 1246 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1247 return getNode(Opcode, Op.getDebugLoc(), ShTy, Op); 1248} 1249 1250/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1251/// specified value type. 1252SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1253 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1254 unsigned ByteSize = VT.getStoreSizeInBits()/8; 1255 const Type *Ty = VT.getTypeForMVT(); 1256 unsigned StackAlign = 1257 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1258 1259 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1260 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1261} 1262 1263/// CreateStackTemporary - Create a stack temporary suitable for holding 1264/// either of the specified value types. 1265SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) { 1266 unsigned Bytes = std::max(VT1.getStoreSizeInBits(), 1267 VT2.getStoreSizeInBits())/8; 1268 const Type *Ty1 = VT1.getTypeForMVT(); 1269 const Type *Ty2 = VT2.getTypeForMVT(); 1270 const TargetData *TD = TLI.getTargetData(); 1271 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1), 1272 TD->getPrefTypeAlignment(Ty2)); 1273 1274 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1275 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align); 1276 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1277} 1278 1279SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1280 SDValue N2, ISD::CondCode Cond, DebugLoc dl) { 1281 // These setcc operations always fold. 1282 switch (Cond) { 1283 default: break; 1284 case ISD::SETFALSE: 1285 case ISD::SETFALSE2: return getConstant(0, VT); 1286 case ISD::SETTRUE: 1287 case ISD::SETTRUE2: return getConstant(1, VT); 1288 1289 case ISD::SETOEQ: 1290 case ISD::SETOGT: 1291 case ISD::SETOGE: 1292 case ISD::SETOLT: 1293 case ISD::SETOLE: 1294 case ISD::SETONE: 1295 case ISD::SETO: 1296 case ISD::SETUO: 1297 case ISD::SETUEQ: 1298 case ISD::SETUNE: 1299 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1300 break; 1301 } 1302 1303 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1304 const APInt &C2 = N2C->getAPIntValue(); 1305 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1306 const APInt &C1 = N1C->getAPIntValue(); 1307 1308 switch (Cond) { 1309 default: assert(0 && "Unknown integer setcc!"); 1310 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1311 case ISD::SETNE: return getConstant(C1 != C2, VT); 1312 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1313 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1314 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1315 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1316 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1317 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1318 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1319 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1320 } 1321 } 1322 } 1323 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1324 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1325 // No compile time operations on this type yet. 1326 if (N1C->getValueType(0) == MVT::ppcf128) 1327 return SDValue(); 1328 1329 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1330 switch (Cond) { 1331 default: break; 1332 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1333 return getUNDEF(VT); 1334 // fall through 1335 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1336 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1337 return getUNDEF(VT); 1338 // fall through 1339 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1340 R==APFloat::cmpLessThan, VT); 1341 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1342 return getUNDEF(VT); 1343 // fall through 1344 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1345 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1346 return getUNDEF(VT); 1347 // fall through 1348 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1349 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1350 return getUNDEF(VT); 1351 // fall through 1352 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1353 R==APFloat::cmpEqual, VT); 1354 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1355 return getUNDEF(VT); 1356 // fall through 1357 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1358 R==APFloat::cmpEqual, VT); 1359 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1360 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1361 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1362 R==APFloat::cmpEqual, VT); 1363 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1364 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1365 R==APFloat::cmpLessThan, VT); 1366 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1367 R==APFloat::cmpUnordered, VT); 1368 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1369 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1370 } 1371 } else { 1372 // Ensure that the constant occurs on the RHS. 1373 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1374 } 1375 } 1376 1377 // Could not fold it. 1378 return SDValue(); 1379} 1380 1381/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1382/// use this predicate to simplify operations downstream. 1383bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1384 unsigned BitWidth = Op.getValueSizeInBits(); 1385 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1386} 1387 1388/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1389/// this predicate to simplify operations downstream. Mask is known to be zero 1390/// for bits that V cannot have. 1391bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1392 unsigned Depth) const { 1393 APInt KnownZero, KnownOne; 1394 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1395 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1396 return (KnownZero & Mask) == Mask; 1397} 1398 1399/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1400/// known to be either zero or one and return them in the KnownZero/KnownOne 1401/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1402/// processing. 1403void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1404 APInt &KnownZero, APInt &KnownOne, 1405 unsigned Depth) const { 1406 unsigned BitWidth = Mask.getBitWidth(); 1407 assert(BitWidth == Op.getValueType().getSizeInBits() && 1408 "Mask size mismatches value type size!"); 1409 1410 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1411 if (Depth == 6 || Mask == 0) 1412 return; // Limit search depth. 1413 1414 APInt KnownZero2, KnownOne2; 1415 1416 switch (Op.getOpcode()) { 1417 case ISD::Constant: 1418 // We know all of the bits for a constant! 1419 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1420 KnownZero = ~KnownOne & Mask; 1421 return; 1422 case ISD::AND: 1423 // If either the LHS or the RHS are Zero, the result is zero. 1424 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1425 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1426 KnownZero2, KnownOne2, Depth+1); 1427 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1428 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1429 1430 // Output known-1 bits are only known if set in both the LHS & RHS. 1431 KnownOne &= KnownOne2; 1432 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1433 KnownZero |= KnownZero2; 1434 return; 1435 case ISD::OR: 1436 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1437 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1438 KnownZero2, KnownOne2, Depth+1); 1439 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1440 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1441 1442 // Output known-0 bits are only known if clear in both the LHS & RHS. 1443 KnownZero &= KnownZero2; 1444 // Output known-1 are known to be set if set in either the LHS | RHS. 1445 KnownOne |= KnownOne2; 1446 return; 1447 case ISD::XOR: { 1448 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1449 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1450 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1451 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1452 1453 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1454 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1455 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1456 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1457 KnownZero = KnownZeroOut; 1458 return; 1459 } 1460 case ISD::MUL: { 1461 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1462 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1463 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1464 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1465 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1466 1467 // If low bits are zero in either operand, output low known-0 bits. 1468 // Also compute a conserative estimate for high known-0 bits. 1469 // More trickiness is possible, but this is sufficient for the 1470 // interesting case of alignment computation. 1471 KnownOne.clear(); 1472 unsigned TrailZ = KnownZero.countTrailingOnes() + 1473 KnownZero2.countTrailingOnes(); 1474 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1475 KnownZero2.countLeadingOnes(), 1476 BitWidth) - BitWidth; 1477 1478 TrailZ = std::min(TrailZ, BitWidth); 1479 LeadZ = std::min(LeadZ, BitWidth); 1480 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1481 APInt::getHighBitsSet(BitWidth, LeadZ); 1482 KnownZero &= Mask; 1483 return; 1484 } 1485 case ISD::UDIV: { 1486 // For the purposes of computing leading zeros we can conservatively 1487 // treat a udiv as a logical right shift by the power of 2 known to 1488 // be less than the denominator. 1489 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1490 ComputeMaskedBits(Op.getOperand(0), 1491 AllOnes, KnownZero2, KnownOne2, Depth+1); 1492 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1493 1494 KnownOne2.clear(); 1495 KnownZero2.clear(); 1496 ComputeMaskedBits(Op.getOperand(1), 1497 AllOnes, KnownZero2, KnownOne2, Depth+1); 1498 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1499 if (RHSUnknownLeadingOnes != BitWidth) 1500 LeadZ = std::min(BitWidth, 1501 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1502 1503 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1504 return; 1505 } 1506 case ISD::SELECT: 1507 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1508 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1509 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1510 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1511 1512 // Only known if known in both the LHS and RHS. 1513 KnownOne &= KnownOne2; 1514 KnownZero &= KnownZero2; 1515 return; 1516 case ISD::SELECT_CC: 1517 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1518 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1519 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1520 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1521 1522 // Only known if known in both the LHS and RHS. 1523 KnownOne &= KnownOne2; 1524 KnownZero &= KnownZero2; 1525 return; 1526 case ISD::SADDO: 1527 case ISD::UADDO: 1528 case ISD::SSUBO: 1529 case ISD::USUBO: 1530 case ISD::SMULO: 1531 case ISD::UMULO: 1532 if (Op.getResNo() != 1) 1533 return; 1534 // The boolean result conforms to getBooleanContents. Fall through. 1535 case ISD::SETCC: 1536 // If we know the result of a setcc has the top bits zero, use this info. 1537 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1538 BitWidth > 1) 1539 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1540 return; 1541 case ISD::SHL: 1542 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1543 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1544 unsigned ShAmt = SA->getZExtValue(); 1545 1546 // If the shift count is an invalid immediate, don't do anything. 1547 if (ShAmt >= BitWidth) 1548 return; 1549 1550 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1551 KnownZero, KnownOne, Depth+1); 1552 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1553 KnownZero <<= ShAmt; 1554 KnownOne <<= ShAmt; 1555 // low bits known zero. 1556 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1557 } 1558 return; 1559 case ISD::SRL: 1560 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1561 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1562 unsigned ShAmt = SA->getZExtValue(); 1563 1564 // If the shift count is an invalid immediate, don't do anything. 1565 if (ShAmt >= BitWidth) 1566 return; 1567 1568 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1569 KnownZero, KnownOne, Depth+1); 1570 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1571 KnownZero = KnownZero.lshr(ShAmt); 1572 KnownOne = KnownOne.lshr(ShAmt); 1573 1574 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1575 KnownZero |= HighBits; // High bits known zero. 1576 } 1577 return; 1578 case ISD::SRA: 1579 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1580 unsigned ShAmt = SA->getZExtValue(); 1581 1582 // If the shift count is an invalid immediate, don't do anything. 1583 if (ShAmt >= BitWidth) 1584 return; 1585 1586 APInt InDemandedMask = (Mask << ShAmt); 1587 // If any of the demanded bits are produced by the sign extension, we also 1588 // demand the input sign bit. 1589 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1590 if (HighBits.getBoolValue()) 1591 InDemandedMask |= APInt::getSignBit(BitWidth); 1592 1593 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1594 Depth+1); 1595 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1596 KnownZero = KnownZero.lshr(ShAmt); 1597 KnownOne = KnownOne.lshr(ShAmt); 1598 1599 // Handle the sign bits. 1600 APInt SignBit = APInt::getSignBit(BitWidth); 1601 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1602 1603 if (KnownZero.intersects(SignBit)) { 1604 KnownZero |= HighBits; // New bits are known zero. 1605 } else if (KnownOne.intersects(SignBit)) { 1606 KnownOne |= HighBits; // New bits are known one. 1607 } 1608 } 1609 return; 1610 case ISD::SIGN_EXTEND_INREG: { 1611 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1612 unsigned EBits = EVT.getSizeInBits(); 1613 1614 // Sign extension. Compute the demanded bits in the result that are not 1615 // present in the input. 1616 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1617 1618 APInt InSignBit = APInt::getSignBit(EBits); 1619 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1620 1621 // If the sign extended bits are demanded, we know that the sign 1622 // bit is demanded. 1623 InSignBit.zext(BitWidth); 1624 if (NewBits.getBoolValue()) 1625 InputDemandedBits |= InSignBit; 1626 1627 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1628 KnownZero, KnownOne, Depth+1); 1629 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1630 1631 // If the sign bit of the input is known set or clear, then we know the 1632 // top bits of the result. 1633 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1634 KnownZero |= NewBits; 1635 KnownOne &= ~NewBits; 1636 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1637 KnownOne |= NewBits; 1638 KnownZero &= ~NewBits; 1639 } else { // Input sign bit unknown 1640 KnownZero &= ~NewBits; 1641 KnownOne &= ~NewBits; 1642 } 1643 return; 1644 } 1645 case ISD::CTTZ: 1646 case ISD::CTLZ: 1647 case ISD::CTPOP: { 1648 unsigned LowBits = Log2_32(BitWidth)+1; 1649 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1650 KnownOne.clear(); 1651 return; 1652 } 1653 case ISD::LOAD: { 1654 if (ISD::isZEXTLoad(Op.getNode())) { 1655 LoadSDNode *LD = cast<LoadSDNode>(Op); 1656 MVT VT = LD->getMemoryVT(); 1657 unsigned MemBits = VT.getSizeInBits(); 1658 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1659 } 1660 return; 1661 } 1662 case ISD::ZERO_EXTEND: { 1663 MVT InVT = Op.getOperand(0).getValueType(); 1664 unsigned InBits = InVT.getSizeInBits(); 1665 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1666 APInt InMask = Mask; 1667 InMask.trunc(InBits); 1668 KnownZero.trunc(InBits); 1669 KnownOne.trunc(InBits); 1670 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1671 KnownZero.zext(BitWidth); 1672 KnownOne.zext(BitWidth); 1673 KnownZero |= NewBits; 1674 return; 1675 } 1676 case ISD::SIGN_EXTEND: { 1677 MVT InVT = Op.getOperand(0).getValueType(); 1678 unsigned InBits = InVT.getSizeInBits(); 1679 APInt InSignBit = APInt::getSignBit(InBits); 1680 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1681 APInt InMask = Mask; 1682 InMask.trunc(InBits); 1683 1684 // If any of the sign extended bits are demanded, we know that the sign 1685 // bit is demanded. Temporarily set this bit in the mask for our callee. 1686 if (NewBits.getBoolValue()) 1687 InMask |= InSignBit; 1688 1689 KnownZero.trunc(InBits); 1690 KnownOne.trunc(InBits); 1691 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1692 1693 // Note if the sign bit is known to be zero or one. 1694 bool SignBitKnownZero = KnownZero.isNegative(); 1695 bool SignBitKnownOne = KnownOne.isNegative(); 1696 assert(!(SignBitKnownZero && SignBitKnownOne) && 1697 "Sign bit can't be known to be both zero and one!"); 1698 1699 // If the sign bit wasn't actually demanded by our caller, we don't 1700 // want it set in the KnownZero and KnownOne result values. Reset the 1701 // mask and reapply it to the result values. 1702 InMask = Mask; 1703 InMask.trunc(InBits); 1704 KnownZero &= InMask; 1705 KnownOne &= InMask; 1706 1707 KnownZero.zext(BitWidth); 1708 KnownOne.zext(BitWidth); 1709 1710 // If the sign bit is known zero or one, the top bits match. 1711 if (SignBitKnownZero) 1712 KnownZero |= NewBits; 1713 else if (SignBitKnownOne) 1714 KnownOne |= NewBits; 1715 return; 1716 } 1717 case ISD::ANY_EXTEND: { 1718 MVT InVT = Op.getOperand(0).getValueType(); 1719 unsigned InBits = InVT.getSizeInBits(); 1720 APInt InMask = Mask; 1721 InMask.trunc(InBits); 1722 KnownZero.trunc(InBits); 1723 KnownOne.trunc(InBits); 1724 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1725 KnownZero.zext(BitWidth); 1726 KnownOne.zext(BitWidth); 1727 return; 1728 } 1729 case ISD::TRUNCATE: { 1730 MVT InVT = Op.getOperand(0).getValueType(); 1731 unsigned InBits = InVT.getSizeInBits(); 1732 APInt InMask = Mask; 1733 InMask.zext(InBits); 1734 KnownZero.zext(InBits); 1735 KnownOne.zext(InBits); 1736 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1737 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1738 KnownZero.trunc(BitWidth); 1739 KnownOne.trunc(BitWidth); 1740 break; 1741 } 1742 case ISD::AssertZext: { 1743 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1744 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1745 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1746 KnownOne, Depth+1); 1747 KnownZero |= (~InMask) & Mask; 1748 return; 1749 } 1750 case ISD::FGETSIGN: 1751 // All bits are zero except the low bit. 1752 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1753 return; 1754 1755 case ISD::SUB: { 1756 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1757 // We know that the top bits of C-X are clear if X contains less bits 1758 // than C (i.e. no wrap-around can happen). For example, 20-X is 1759 // positive if we can prove that X is >= 0 and < 16. 1760 if (CLHS->getAPIntValue().isNonNegative()) { 1761 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1762 // NLZ can't be BitWidth with no sign bit 1763 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1764 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1765 Depth+1); 1766 1767 // If all of the MaskV bits are known to be zero, then we know the 1768 // output top bits are zero, because we now know that the output is 1769 // from [0-C]. 1770 if ((KnownZero2 & MaskV) == MaskV) { 1771 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1772 // Top bits known zero. 1773 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1774 } 1775 } 1776 } 1777 } 1778 // fall through 1779 case ISD::ADD: { 1780 // Output known-0 bits are known if clear or set in both the low clear bits 1781 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1782 // low 3 bits clear. 1783 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1784 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1785 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1786 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1787 1788 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1789 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1790 KnownZeroOut = std::min(KnownZeroOut, 1791 KnownZero2.countTrailingOnes()); 1792 1793 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1794 return; 1795 } 1796 case ISD::SREM: 1797 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1798 const APInt &RA = Rem->getAPIntValue(); 1799 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1800 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1801 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1802 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1803 1804 // If the sign bit of the first operand is zero, the sign bit of 1805 // the result is zero. If the first operand has no one bits below 1806 // the second operand's single 1 bit, its sign will be zero. 1807 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1808 KnownZero2 |= ~LowBits; 1809 1810 KnownZero |= KnownZero2 & Mask; 1811 1812 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1813 } 1814 } 1815 return; 1816 case ISD::UREM: { 1817 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1818 const APInt &RA = Rem->getAPIntValue(); 1819 if (RA.isPowerOf2()) { 1820 APInt LowBits = (RA - 1); 1821 APInt Mask2 = LowBits & Mask; 1822 KnownZero |= ~LowBits & Mask; 1823 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1824 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1825 break; 1826 } 1827 } 1828 1829 // Since the result is less than or equal to either operand, any leading 1830 // zero bits in either operand must also exist in the result. 1831 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1832 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1833 Depth+1); 1834 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1835 Depth+1); 1836 1837 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1838 KnownZero2.countLeadingOnes()); 1839 KnownOne.clear(); 1840 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1841 return; 1842 } 1843 default: 1844 // Allow the target to implement this method for its nodes. 1845 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1846 case ISD::INTRINSIC_WO_CHAIN: 1847 case ISD::INTRINSIC_W_CHAIN: 1848 case ISD::INTRINSIC_VOID: 1849 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1850 } 1851 return; 1852 } 1853} 1854 1855/// ComputeNumSignBits - Return the number of times the sign bit of the 1856/// register is replicated into the other bits. We know that at least 1 bit 1857/// is always equal to the sign bit (itself), but other cases can give us 1858/// information. For example, immediately after an "SRA X, 2", we know that 1859/// the top 3 bits are all equal to each other, so we return 3. 1860unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1861 MVT VT = Op.getValueType(); 1862 assert(VT.isInteger() && "Invalid VT!"); 1863 unsigned VTBits = VT.getSizeInBits(); 1864 unsigned Tmp, Tmp2; 1865 unsigned FirstAnswer = 1; 1866 1867 if (Depth == 6) 1868 return 1; // Limit search depth. 1869 1870 switch (Op.getOpcode()) { 1871 default: break; 1872 case ISD::AssertSext: 1873 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1874 return VTBits-Tmp+1; 1875 case ISD::AssertZext: 1876 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1877 return VTBits-Tmp; 1878 1879 case ISD::Constant: { 1880 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1881 // If negative, return # leading ones. 1882 if (Val.isNegative()) 1883 return Val.countLeadingOnes(); 1884 1885 // Return # leading zeros. 1886 return Val.countLeadingZeros(); 1887 } 1888 1889 case ISD::SIGN_EXTEND: 1890 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1891 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1892 1893 case ISD::SIGN_EXTEND_INREG: 1894 // Max of the input and what this extends. 1895 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1896 Tmp = VTBits-Tmp+1; 1897 1898 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1899 return std::max(Tmp, Tmp2); 1900 1901 case ISD::SRA: 1902 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1903 // SRA X, C -> adds C sign bits. 1904 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1905 Tmp += C->getZExtValue(); 1906 if (Tmp > VTBits) Tmp = VTBits; 1907 } 1908 return Tmp; 1909 case ISD::SHL: 1910 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1911 // shl destroys sign bits. 1912 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1913 if (C->getZExtValue() >= VTBits || // Bad shift. 1914 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 1915 return Tmp - C->getZExtValue(); 1916 } 1917 break; 1918 case ISD::AND: 1919 case ISD::OR: 1920 case ISD::XOR: // NOT is handled here. 1921 // Logical binary ops preserve the number of sign bits at the worst. 1922 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1923 if (Tmp != 1) { 1924 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1925 FirstAnswer = std::min(Tmp, Tmp2); 1926 // We computed what we know about the sign bits as our first 1927 // answer. Now proceed to the generic code that uses 1928 // ComputeMaskedBits, and pick whichever answer is better. 1929 } 1930 break; 1931 1932 case ISD::SELECT: 1933 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1934 if (Tmp == 1) return 1; // Early out. 1935 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1936 return std::min(Tmp, Tmp2); 1937 1938 case ISD::SADDO: 1939 case ISD::UADDO: 1940 case ISD::SSUBO: 1941 case ISD::USUBO: 1942 case ISD::SMULO: 1943 case ISD::UMULO: 1944 if (Op.getResNo() != 1) 1945 break; 1946 // The boolean result conforms to getBooleanContents. Fall through. 1947 case ISD::SETCC: 1948 // If setcc returns 0/-1, all bits are sign bits. 1949 if (TLI.getBooleanContents() == 1950 TargetLowering::ZeroOrNegativeOneBooleanContent) 1951 return VTBits; 1952 break; 1953 case ISD::ROTL: 1954 case ISD::ROTR: 1955 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1956 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 1957 1958 // Handle rotate right by N like a rotate left by 32-N. 1959 if (Op.getOpcode() == ISD::ROTR) 1960 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1961 1962 // If we aren't rotating out all of the known-in sign bits, return the 1963 // number that are left. This handles rotl(sext(x), 1) for example. 1964 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1965 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1966 } 1967 break; 1968 case ISD::ADD: 1969 // Add can have at most one carry bit. Thus we know that the output 1970 // is, at worst, one more bit than the inputs. 1971 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1972 if (Tmp == 1) return 1; // Early out. 1973 1974 // Special case decrementing a value (ADD X, -1): 1975 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 1976 if (CRHS->isAllOnesValue()) { 1977 APInt KnownZero, KnownOne; 1978 APInt Mask = APInt::getAllOnesValue(VTBits); 1979 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1980 1981 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1982 // sign bits set. 1983 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1984 return VTBits; 1985 1986 // If we are subtracting one from a positive number, there is no carry 1987 // out of the result. 1988 if (KnownZero.isNegative()) 1989 return Tmp; 1990 } 1991 1992 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1993 if (Tmp2 == 1) return 1; 1994 return std::min(Tmp, Tmp2)-1; 1995 break; 1996 1997 case ISD::SUB: 1998 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1999 if (Tmp2 == 1) return 1; 2000 2001 // Handle NEG. 2002 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 2003 if (CLHS->isNullValue()) { 2004 APInt KnownZero, KnownOne; 2005 APInt Mask = APInt::getAllOnesValue(VTBits); 2006 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 2007 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2008 // sign bits set. 2009 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2010 return VTBits; 2011 2012 // If the input is known to be positive (the sign bit is known clear), 2013 // the output of the NEG has the same number of sign bits as the input. 2014 if (KnownZero.isNegative()) 2015 return Tmp2; 2016 2017 // Otherwise, we treat this like a SUB. 2018 } 2019 2020 // Sub can have at most one carry bit. Thus we know that the output 2021 // is, at worst, one more bit than the inputs. 2022 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2023 if (Tmp == 1) return 1; // Early out. 2024 return std::min(Tmp, Tmp2)-1; 2025 break; 2026 case ISD::TRUNCATE: 2027 // FIXME: it's tricky to do anything useful for this, but it is an important 2028 // case for targets like X86. 2029 break; 2030 } 2031 2032 // Handle LOADX separately here. EXTLOAD case will fallthrough. 2033 if (Op.getOpcode() == ISD::LOAD) { 2034 LoadSDNode *LD = cast<LoadSDNode>(Op); 2035 unsigned ExtType = LD->getExtensionType(); 2036 switch (ExtType) { 2037 default: break; 2038 case ISD::SEXTLOAD: // '17' bits known 2039 Tmp = LD->getMemoryVT().getSizeInBits(); 2040 return VTBits-Tmp+1; 2041 case ISD::ZEXTLOAD: // '16' bits known 2042 Tmp = LD->getMemoryVT().getSizeInBits(); 2043 return VTBits-Tmp; 2044 } 2045 } 2046 2047 // Allow the target to implement this method for its nodes. 2048 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2049 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2050 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2051 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2052 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2053 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2054 } 2055 2056 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2057 // use this information. 2058 APInt KnownZero, KnownOne; 2059 APInt Mask = APInt::getAllOnesValue(VTBits); 2060 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2061 2062 if (KnownZero.isNegative()) { // sign bit is 0 2063 Mask = KnownZero; 2064 } else if (KnownOne.isNegative()) { // sign bit is 1; 2065 Mask = KnownOne; 2066 } else { 2067 // Nothing known. 2068 return FirstAnswer; 2069 } 2070 2071 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2072 // the number of identical bits in the top of the input value. 2073 Mask = ~Mask; 2074 Mask <<= Mask.getBitWidth()-VTBits; 2075 // Return # leading zeros. We use 'min' here in case Val was zero before 2076 // shifting. We don't want to return '64' as for an i32 "0". 2077 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2078} 2079 2080 2081bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2082 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2083 if (!GA) return false; 2084 if (GA->getOffset() != 0) return false; 2085 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2086 if (!GV) return false; 2087 MachineModuleInfo *MMI = getMachineModuleInfo(); 2088 return MMI && MMI->hasDebugInfo(); 2089} 2090 2091 2092/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2093/// element of the result of the vector shuffle. 2094SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 2095 MVT VT = N->getValueType(0); 2096 DebugLoc dl = N->getDebugLoc(); 2097 SDValue PermMask = N->getOperand(2); 2098 SDValue Idx = PermMask.getOperand(i); 2099 if (Idx.getOpcode() == ISD::UNDEF) 2100 return getUNDEF(VT.getVectorElementType()); 2101 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 2102 unsigned NumElems = PermMask.getNumOperands(); 2103 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2104 Index %= NumElems; 2105 2106 if (V.getOpcode() == ISD::BIT_CONVERT) { 2107 V = V.getOperand(0); 2108 MVT VVT = V.getValueType(); 2109 if (!VVT.isVector() || VVT.getVectorNumElements() != NumElems) 2110 return SDValue(); 2111 } 2112 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2113 return (Index == 0) ? V.getOperand(0) 2114 : getUNDEF(VT.getVectorElementType()); 2115 if (V.getOpcode() == ISD::BUILD_VECTOR) 2116 return V.getOperand(Index); 2117 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 2118 return getShuffleScalarElt(V.getNode(), Index); 2119 return SDValue(); 2120} 2121 2122 2123/// getNode - Gets or creates the specified node. 2124/// 2125SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) { 2126 FoldingSetNodeID ID; 2127 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2128 void *IP = 0; 2129 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2130 return SDValue(E, 0); 2131 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2132 new (N) SDNode(Opcode, DL, getVTList(VT)); 2133 CSEMap.InsertNode(N, IP); 2134 2135 AllNodes.push_back(N); 2136#ifndef NDEBUG 2137 VerifyNode(N); 2138#endif 2139 return SDValue(N, 0); 2140} 2141 2142SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 2143 MVT VT, SDValue Operand) { 2144 // Constant fold unary operations with an integer constant operand. 2145 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2146 const APInt &Val = C->getAPIntValue(); 2147 unsigned BitWidth = VT.getSizeInBits(); 2148 switch (Opcode) { 2149 default: break; 2150 case ISD::SIGN_EXTEND: 2151 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2152 case ISD::ANY_EXTEND: 2153 case ISD::ZERO_EXTEND: 2154 case ISD::TRUNCATE: 2155 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2156 case ISD::UINT_TO_FP: 2157 case ISD::SINT_TO_FP: { 2158 const uint64_t zero[] = {0, 0}; 2159 // No compile time operations on this type. 2160 if (VT==MVT::ppcf128) 2161 break; 2162 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2163 (void)apf.convertFromAPInt(Val, 2164 Opcode==ISD::SINT_TO_FP, 2165 APFloat::rmNearestTiesToEven); 2166 return getConstantFP(apf, VT); 2167 } 2168 case ISD::BIT_CONVERT: 2169 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2170 return getConstantFP(Val.bitsToFloat(), VT); 2171 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2172 return getConstantFP(Val.bitsToDouble(), VT); 2173 break; 2174 case ISD::BSWAP: 2175 return getConstant(Val.byteSwap(), VT); 2176 case ISD::CTPOP: 2177 return getConstant(Val.countPopulation(), VT); 2178 case ISD::CTLZ: 2179 return getConstant(Val.countLeadingZeros(), VT); 2180 case ISD::CTTZ: 2181 return getConstant(Val.countTrailingZeros(), VT); 2182 } 2183 } 2184 2185 // Constant fold unary operations with a floating point constant operand. 2186 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2187 APFloat V = C->getValueAPF(); // make copy 2188 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2189 switch (Opcode) { 2190 case ISD::FNEG: 2191 V.changeSign(); 2192 return getConstantFP(V, VT); 2193 case ISD::FABS: 2194 V.clearSign(); 2195 return getConstantFP(V, VT); 2196 case ISD::FP_ROUND: 2197 case ISD::FP_EXTEND: { 2198 bool ignored; 2199 // This can return overflow, underflow, or inexact; we don't care. 2200 // FIXME need to be more flexible about rounding mode. 2201 (void)V.convert(*MVTToAPFloatSemantics(VT), 2202 APFloat::rmNearestTiesToEven, &ignored); 2203 return getConstantFP(V, VT); 2204 } 2205 case ISD::FP_TO_SINT: 2206 case ISD::FP_TO_UINT: { 2207 integerPart x; 2208 bool ignored; 2209 assert(integerPartWidth >= 64); 2210 // FIXME need to be more flexible about rounding mode. 2211 APFloat::opStatus s = V.convertToInteger(&x, 64U, 2212 Opcode==ISD::FP_TO_SINT, 2213 APFloat::rmTowardZero, &ignored); 2214 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2215 break; 2216 return getConstant(x, VT); 2217 } 2218 case ISD::BIT_CONVERT: 2219 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2220 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2221 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2222 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2223 break; 2224 } 2225 } 2226 } 2227 2228 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2229 switch (Opcode) { 2230 case ISD::TokenFactor: 2231 case ISD::MERGE_VALUES: 2232 case ISD::CONCAT_VECTORS: 2233 return Operand; // Factor, merge or concat of one node? No need. 2234 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2235 case ISD::FP_EXTEND: 2236 assert(VT.isFloatingPoint() && 2237 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2238 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2239 if (Operand.getOpcode() == ISD::UNDEF) 2240 return getUNDEF(VT); 2241 break; 2242 case ISD::SIGN_EXTEND: 2243 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2244 "Invalid SIGN_EXTEND!"); 2245 if (Operand.getValueType() == VT) return Operand; // noop extension 2246 assert(Operand.getValueType().bitsLT(VT) 2247 && "Invalid sext node, dst < src!"); 2248 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2249 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2250 break; 2251 case ISD::ZERO_EXTEND: 2252 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2253 "Invalid ZERO_EXTEND!"); 2254 if (Operand.getValueType() == VT) return Operand; // noop extension 2255 assert(Operand.getValueType().bitsLT(VT) 2256 && "Invalid zext node, dst < src!"); 2257 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2258 return getNode(ISD::ZERO_EXTEND, DL, VT, 2259 Operand.getNode()->getOperand(0)); 2260 break; 2261 case ISD::ANY_EXTEND: 2262 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2263 "Invalid ANY_EXTEND!"); 2264 if (Operand.getValueType() == VT) return Operand; // noop extension 2265 assert(Operand.getValueType().bitsLT(VT) 2266 && "Invalid anyext node, dst < src!"); 2267 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2268 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2269 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2270 break; 2271 case ISD::TRUNCATE: 2272 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2273 "Invalid TRUNCATE!"); 2274 if (Operand.getValueType() == VT) return Operand; // noop truncate 2275 assert(Operand.getValueType().bitsGT(VT) 2276 && "Invalid truncate node, src < dst!"); 2277 if (OpOpcode == ISD::TRUNCATE) 2278 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2279 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2280 OpOpcode == ISD::ANY_EXTEND) { 2281 // If the source is smaller than the dest, we still need an extend. 2282 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2283 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2284 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2285 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2286 else 2287 return Operand.getNode()->getOperand(0); 2288 } 2289 break; 2290 case ISD::BIT_CONVERT: 2291 // Basic sanity checking. 2292 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2293 && "Cannot BIT_CONVERT between types of different sizes!"); 2294 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2295 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2296 return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0)); 2297 if (OpOpcode == ISD::UNDEF) 2298 return getUNDEF(VT); 2299 break; 2300 case ISD::SCALAR_TO_VECTOR: 2301 assert(VT.isVector() && !Operand.getValueType().isVector() && 2302 (VT.getVectorElementType() == Operand.getValueType() || 2303 (VT.getVectorElementType().isInteger() && 2304 Operand.getValueType().isInteger() && 2305 VT.getVectorElementType().bitsLE(Operand.getValueType()))) && 2306 "Illegal SCALAR_TO_VECTOR node!"); 2307 if (OpOpcode == ISD::UNDEF) 2308 return getUNDEF(VT); 2309 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2310 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2311 isa<ConstantSDNode>(Operand.getOperand(1)) && 2312 Operand.getConstantOperandVal(1) == 0 && 2313 Operand.getOperand(0).getValueType() == VT) 2314 return Operand.getOperand(0); 2315 break; 2316 case ISD::FNEG: 2317 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 2318 if (UnsafeFPMath && OpOpcode == ISD::FSUB) 2319 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1), 2320 Operand.getNode()->getOperand(0)); 2321 if (OpOpcode == ISD::FNEG) // --X -> X 2322 return Operand.getNode()->getOperand(0); 2323 break; 2324 case ISD::FABS: 2325 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2326 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0)); 2327 break; 2328 } 2329 2330 SDNode *N; 2331 SDVTList VTs = getVTList(VT); 2332 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2333 FoldingSetNodeID ID; 2334 SDValue Ops[1] = { Operand }; 2335 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2336 void *IP = 0; 2337 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2338 return SDValue(E, 0); 2339 N = NodeAllocator.Allocate<UnarySDNode>(); 2340 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2341 CSEMap.InsertNode(N, IP); 2342 } else { 2343 N = NodeAllocator.Allocate<UnarySDNode>(); 2344 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2345 } 2346 2347 AllNodes.push_back(N); 2348#ifndef NDEBUG 2349 VerifyNode(N); 2350#endif 2351 return SDValue(N, 0); 2352} 2353 2354SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2355 MVT VT, 2356 ConstantSDNode *Cst1, 2357 ConstantSDNode *Cst2) { 2358 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2359 2360 switch (Opcode) { 2361 case ISD::ADD: return getConstant(C1 + C2, VT); 2362 case ISD::SUB: return getConstant(C1 - C2, VT); 2363 case ISD::MUL: return getConstant(C1 * C2, VT); 2364 case ISD::UDIV: 2365 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2366 break; 2367 case ISD::UREM: 2368 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2369 break; 2370 case ISD::SDIV: 2371 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2372 break; 2373 case ISD::SREM: 2374 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2375 break; 2376 case ISD::AND: return getConstant(C1 & C2, VT); 2377 case ISD::OR: return getConstant(C1 | C2, VT); 2378 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2379 case ISD::SHL: return getConstant(C1 << C2, VT); 2380 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2381 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2382 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2383 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2384 default: break; 2385 } 2386 2387 return SDValue(); 2388} 2389 2390SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2391 SDValue N1, SDValue N2) { 2392 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2393 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2394 switch (Opcode) { 2395 default: break; 2396 case ISD::TokenFactor: 2397 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2398 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2399 // Fold trivial token factors. 2400 if (N1.getOpcode() == ISD::EntryToken) return N2; 2401 if (N2.getOpcode() == ISD::EntryToken) return N1; 2402 if (N1 == N2) return N1; 2403 break; 2404 case ISD::CONCAT_VECTORS: 2405 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2406 // one big BUILD_VECTOR. 2407 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2408 N2.getOpcode() == ISD::BUILD_VECTOR) { 2409 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2410 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2411 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2412 } 2413 break; 2414 case ISD::AND: 2415 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2416 N1.getValueType() == VT && "Binary operator types must match!"); 2417 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2418 // worth handling here. 2419 if (N2C && N2C->isNullValue()) 2420 return N2; 2421 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2422 return N1; 2423 break; 2424 case ISD::OR: 2425 case ISD::XOR: 2426 case ISD::ADD: 2427 case ISD::SUB: 2428 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2429 N1.getValueType() == VT && "Binary operator types must match!"); 2430 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2431 // it's worth handling here. 2432 if (N2C && N2C->isNullValue()) 2433 return N1; 2434 break; 2435 case ISD::UDIV: 2436 case ISD::UREM: 2437 case ISD::MULHU: 2438 case ISD::MULHS: 2439 case ISD::MUL: 2440 case ISD::SDIV: 2441 case ISD::SREM: 2442 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2443 // fall through 2444 case ISD::FADD: 2445 case ISD::FSUB: 2446 case ISD::FMUL: 2447 case ISD::FDIV: 2448 case ISD::FREM: 2449 if (UnsafeFPMath) { 2450 if (Opcode == ISD::FADD) { 2451 // 0+x --> x 2452 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) 2453 if (CFP->getValueAPF().isZero()) 2454 return N2; 2455 // x+0 --> x 2456 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2457 if (CFP->getValueAPF().isZero()) 2458 return N1; 2459 } else if (Opcode == ISD::FSUB) { 2460 // x-0 --> x 2461 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2462 if (CFP->getValueAPF().isZero()) 2463 return N1; 2464 } 2465 } 2466 assert(N1.getValueType() == N2.getValueType() && 2467 N1.getValueType() == VT && "Binary operator types must match!"); 2468 break; 2469 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2470 assert(N1.getValueType() == VT && 2471 N1.getValueType().isFloatingPoint() && 2472 N2.getValueType().isFloatingPoint() && 2473 "Invalid FCOPYSIGN!"); 2474 break; 2475 case ISD::SHL: 2476 case ISD::SRA: 2477 case ISD::SRL: 2478 case ISD::ROTL: 2479 case ISD::ROTR: 2480 assert(VT == N1.getValueType() && 2481 "Shift operators return type must be the same as their first arg"); 2482 assert(VT.isInteger() && N2.getValueType().isInteger() && 2483 "Shifts only work on integers"); 2484 2485 // Always fold shifts of i1 values so the code generator doesn't need to 2486 // handle them. Since we know the size of the shift has to be less than the 2487 // size of the value, the shift/rotate count is guaranteed to be zero. 2488 if (VT == MVT::i1) 2489 return N1; 2490 break; 2491 case ISD::FP_ROUND_INREG: { 2492 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2493 assert(VT == N1.getValueType() && "Not an inreg round!"); 2494 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2495 "Cannot FP_ROUND_INREG integer types"); 2496 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2497 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2498 break; 2499 } 2500 case ISD::FP_ROUND: 2501 assert(VT.isFloatingPoint() && 2502 N1.getValueType().isFloatingPoint() && 2503 VT.bitsLE(N1.getValueType()) && 2504 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2505 if (N1.getValueType() == VT) return N1; // noop conversion. 2506 break; 2507 case ISD::AssertSext: 2508 case ISD::AssertZext: { 2509 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2510 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2511 assert(VT.isInteger() && EVT.isInteger() && 2512 "Cannot *_EXTEND_INREG FP types"); 2513 assert(EVT.bitsLE(VT) && "Not extending!"); 2514 if (VT == EVT) return N1; // noop assertion. 2515 break; 2516 } 2517 case ISD::SIGN_EXTEND_INREG: { 2518 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2519 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2520 assert(VT.isInteger() && EVT.isInteger() && 2521 "Cannot *_EXTEND_INREG FP types"); 2522 assert(EVT.bitsLE(VT) && "Not extending!"); 2523 if (EVT == VT) return N1; // Not actually extending 2524 2525 if (N1C) { 2526 APInt Val = N1C->getAPIntValue(); 2527 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2528 Val <<= Val.getBitWidth()-FromBits; 2529 Val = Val.ashr(Val.getBitWidth()-FromBits); 2530 return getConstant(Val, VT); 2531 } 2532 break; 2533 } 2534 case ISD::EXTRACT_VECTOR_ELT: 2535 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2536 if (N1.getOpcode() == ISD::UNDEF) 2537 return getUNDEF(VT); 2538 2539 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2540 // expanding copies of large vectors from registers. 2541 if (N2C && 2542 N1.getOpcode() == ISD::CONCAT_VECTORS && 2543 N1.getNumOperands() > 0) { 2544 unsigned Factor = 2545 N1.getOperand(0).getValueType().getVectorNumElements(); 2546 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, 2547 N1.getOperand(N2C->getZExtValue() / Factor), 2548 getConstant(N2C->getZExtValue() % Factor, 2549 N2.getValueType())); 2550 } 2551 2552 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2553 // expanding large vector constants. 2554 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) { 2555 SDValue Elt = N1.getOperand(N2C->getZExtValue()); 2556 if (Elt.getValueType() != VT) { 2557 // If the vector element type is not legal, the BUILD_VECTOR operands 2558 // are promoted and implicitly truncated. Make that explicit here. 2559 assert(VT.isInteger() && Elt.getValueType().isInteger() && 2560 VT.bitsLE(Elt.getValueType()) && 2561 "Bad type for BUILD_VECTOR operand"); 2562 Elt = getNode(ISD::TRUNCATE, DL, VT, Elt); 2563 } 2564 return Elt; 2565 } 2566 2567 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2568 // operations are lowered to scalars. 2569 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2570 // If the indices are the same, return the inserted element. 2571 if (N1.getOperand(2) == N2) 2572 return N1.getOperand(1); 2573 // If the indices are known different, extract the element from 2574 // the original vector. 2575 else if (isa<ConstantSDNode>(N1.getOperand(2)) && 2576 isa<ConstantSDNode>(N2)) 2577 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2); 2578 } 2579 break; 2580 case ISD::EXTRACT_ELEMENT: 2581 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2582 assert(!N1.getValueType().isVector() && !VT.isVector() && 2583 (N1.getValueType().isInteger() == VT.isInteger()) && 2584 "Wrong types for EXTRACT_ELEMENT!"); 2585 2586 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2587 // 64-bit integers into 32-bit parts. Instead of building the extract of 2588 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2589 if (N1.getOpcode() == ISD::BUILD_PAIR) 2590 return N1.getOperand(N2C->getZExtValue()); 2591 2592 // EXTRACT_ELEMENT of a constant int is also very common. 2593 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2594 unsigned ElementSize = VT.getSizeInBits(); 2595 unsigned Shift = ElementSize * N2C->getZExtValue(); 2596 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2597 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2598 } 2599 break; 2600 case ISD::EXTRACT_SUBVECTOR: 2601 if (N1.getValueType() == VT) // Trivial extraction. 2602 return N1; 2603 break; 2604 } 2605 2606 if (N1C) { 2607 if (N2C) { 2608 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2609 if (SV.getNode()) return SV; 2610 } else { // Cannonicalize constant to RHS if commutative 2611 if (isCommutativeBinOp(Opcode)) { 2612 std::swap(N1C, N2C); 2613 std::swap(N1, N2); 2614 } 2615 } 2616 } 2617 2618 // Constant fold FP operations. 2619 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2620 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2621 if (N1CFP) { 2622 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2623 // Cannonicalize constant to RHS if commutative 2624 std::swap(N1CFP, N2CFP); 2625 std::swap(N1, N2); 2626 } else if (N2CFP && VT != MVT::ppcf128) { 2627 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2628 APFloat::opStatus s; 2629 switch (Opcode) { 2630 case ISD::FADD: 2631 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2632 if (s != APFloat::opInvalidOp) 2633 return getConstantFP(V1, VT); 2634 break; 2635 case ISD::FSUB: 2636 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2637 if (s!=APFloat::opInvalidOp) 2638 return getConstantFP(V1, VT); 2639 break; 2640 case ISD::FMUL: 2641 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2642 if (s!=APFloat::opInvalidOp) 2643 return getConstantFP(V1, VT); 2644 break; 2645 case ISD::FDIV: 2646 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2647 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2648 return getConstantFP(V1, VT); 2649 break; 2650 case ISD::FREM : 2651 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2652 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2653 return getConstantFP(V1, VT); 2654 break; 2655 case ISD::FCOPYSIGN: 2656 V1.copySign(V2); 2657 return getConstantFP(V1, VT); 2658 default: break; 2659 } 2660 } 2661 } 2662 2663 // Canonicalize an UNDEF to the RHS, even over a constant. 2664 if (N1.getOpcode() == ISD::UNDEF) { 2665 if (isCommutativeBinOp(Opcode)) { 2666 std::swap(N1, N2); 2667 } else { 2668 switch (Opcode) { 2669 case ISD::FP_ROUND_INREG: 2670 case ISD::SIGN_EXTEND_INREG: 2671 case ISD::SUB: 2672 case ISD::FSUB: 2673 case ISD::FDIV: 2674 case ISD::FREM: 2675 case ISD::SRA: 2676 return N1; // fold op(undef, arg2) -> undef 2677 case ISD::UDIV: 2678 case ISD::SDIV: 2679 case ISD::UREM: 2680 case ISD::SREM: 2681 case ISD::SRL: 2682 case ISD::SHL: 2683 if (!VT.isVector()) 2684 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2685 // For vectors, we can't easily build an all zero vector, just return 2686 // the LHS. 2687 return N2; 2688 } 2689 } 2690 } 2691 2692 // Fold a bunch of operators when the RHS is undef. 2693 if (N2.getOpcode() == ISD::UNDEF) { 2694 switch (Opcode) { 2695 case ISD::XOR: 2696 if (N1.getOpcode() == ISD::UNDEF) 2697 // Handle undef ^ undef -> 0 special case. This is a common 2698 // idiom (misuse). 2699 return getConstant(0, VT); 2700 // fallthrough 2701 case ISD::ADD: 2702 case ISD::ADDC: 2703 case ISD::ADDE: 2704 case ISD::SUB: 2705 case ISD::FADD: 2706 case ISD::FSUB: 2707 case ISD::FMUL: 2708 case ISD::FDIV: 2709 case ISD::FREM: 2710 case ISD::UDIV: 2711 case ISD::SDIV: 2712 case ISD::UREM: 2713 case ISD::SREM: 2714 return N2; // fold op(arg1, undef) -> undef 2715 case ISD::MUL: 2716 case ISD::AND: 2717 case ISD::SRL: 2718 case ISD::SHL: 2719 if (!VT.isVector()) 2720 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2721 // For vectors, we can't easily build an all zero vector, just return 2722 // the LHS. 2723 return N1; 2724 case ISD::OR: 2725 if (!VT.isVector()) 2726 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 2727 // For vectors, we can't easily build an all one vector, just return 2728 // the LHS. 2729 return N1; 2730 case ISD::SRA: 2731 return N1; 2732 } 2733 } 2734 2735 // Memoize this node if possible. 2736 SDNode *N; 2737 SDVTList VTs = getVTList(VT); 2738 if (VT != MVT::Flag) { 2739 SDValue Ops[] = { N1, N2 }; 2740 FoldingSetNodeID ID; 2741 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2742 void *IP = 0; 2743 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2744 return SDValue(E, 0); 2745 N = NodeAllocator.Allocate<BinarySDNode>(); 2746 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2747 CSEMap.InsertNode(N, IP); 2748 } else { 2749 N = NodeAllocator.Allocate<BinarySDNode>(); 2750 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2751 } 2752 2753 AllNodes.push_back(N); 2754#ifndef NDEBUG 2755 VerifyNode(N); 2756#endif 2757 return SDValue(N, 0); 2758} 2759 2760SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2761 SDValue N1, SDValue N2, SDValue N3) { 2762 // Perform various simplifications. 2763 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2764 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2765 switch (Opcode) { 2766 case ISD::CONCAT_VECTORS: 2767 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2768 // one big BUILD_VECTOR. 2769 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2770 N2.getOpcode() == ISD::BUILD_VECTOR && 2771 N3.getOpcode() == ISD::BUILD_VECTOR) { 2772 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2773 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2774 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2775 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2776 } 2777 break; 2778 case ISD::SETCC: { 2779 // Use FoldSetCC to simplify SETCC's. 2780 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL); 2781 if (Simp.getNode()) return Simp; 2782 break; 2783 } 2784 case ISD::SELECT: 2785 if (N1C) { 2786 if (N1C->getZExtValue()) 2787 return N2; // select true, X, Y -> X 2788 else 2789 return N3; // select false, X, Y -> Y 2790 } 2791 2792 if (N2 == N3) return N2; // select C, X, X -> X 2793 break; 2794 case ISD::BRCOND: 2795 if (N2C) { 2796 if (N2C->getZExtValue()) // Unconditional branch 2797 return getNode(ISD::BR, DL, MVT::Other, N1, N3); 2798 else 2799 return N1; // Never-taken branch 2800 } 2801 break; 2802 case ISD::VECTOR_SHUFFLE: 2803 assert(N1.getValueType() == N2.getValueType() && 2804 N1.getValueType().isVector() && 2805 VT.isVector() && N3.getValueType().isVector() && 2806 N3.getOpcode() == ISD::BUILD_VECTOR && 2807 VT.getVectorNumElements() == N3.getNumOperands() && 2808 "Illegal VECTOR_SHUFFLE node!"); 2809 break; 2810 case ISD::BIT_CONVERT: 2811 // Fold bit_convert nodes from a type to themselves. 2812 if (N1.getValueType() == VT) 2813 return N1; 2814 break; 2815 } 2816 2817 // Memoize node if it doesn't produce a flag. 2818 SDNode *N; 2819 SDVTList VTs = getVTList(VT); 2820 if (VT != MVT::Flag) { 2821 SDValue Ops[] = { N1, N2, N3 }; 2822 FoldingSetNodeID ID; 2823 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2824 void *IP = 0; 2825 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2826 return SDValue(E, 0); 2827 N = NodeAllocator.Allocate<TernarySDNode>(); 2828 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2829 CSEMap.InsertNode(N, IP); 2830 } else { 2831 N = NodeAllocator.Allocate<TernarySDNode>(); 2832 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2833 } 2834 AllNodes.push_back(N); 2835#ifndef NDEBUG 2836 VerifyNode(N); 2837#endif 2838 return SDValue(N, 0); 2839} 2840 2841SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2842 SDValue N1, SDValue N2, SDValue N3, 2843 SDValue N4) { 2844 SDValue Ops[] = { N1, N2, N3, N4 }; 2845 return getNode(Opcode, DL, VT, Ops, 4); 2846} 2847 2848SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2849 SDValue N1, SDValue N2, SDValue N3, 2850 SDValue N4, SDValue N5) { 2851 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2852 return getNode(Opcode, DL, VT, Ops, 5); 2853} 2854 2855/// getMemsetValue - Vectorized representation of the memset value 2856/// operand. 2857static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG, 2858 DebugLoc dl) { 2859 unsigned NumBits = VT.isVector() ? 2860 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2861 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2862 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2863 unsigned Shift = 8; 2864 for (unsigned i = NumBits; i > 8; i >>= 1) { 2865 Val = (Val << Shift) | Val; 2866 Shift <<= 1; 2867 } 2868 if (VT.isInteger()) 2869 return DAG.getConstant(Val, VT); 2870 return DAG.getConstantFP(APFloat(Val), VT); 2871 } 2872 2873 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2874 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); 2875 unsigned Shift = 8; 2876 for (unsigned i = NumBits; i > 8; i >>= 1) { 2877 Value = DAG.getNode(ISD::OR, dl, VT, 2878 DAG.getNode(ISD::SHL, dl, VT, Value, 2879 DAG.getConstant(Shift, 2880 TLI.getShiftAmountTy())), 2881 Value); 2882 Shift <<= 1; 2883 } 2884 2885 return Value; 2886} 2887 2888/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2889/// used when a memcpy is turned into a memset when the source is a constant 2890/// string ptr. 2891static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, 2892 const TargetLowering &TLI, 2893 std::string &Str, unsigned Offset) { 2894 // Handle vector with all elements zero. 2895 if (Str.empty()) { 2896 if (VT.isInteger()) 2897 return DAG.getConstant(0, VT); 2898 unsigned NumElts = VT.getVectorNumElements(); 2899 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2900 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 2901 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2902 } 2903 2904 assert(!VT.isVector() && "Can't handle vector type here!"); 2905 unsigned NumBits = VT.getSizeInBits(); 2906 unsigned MSB = NumBits / 8; 2907 uint64_t Val = 0; 2908 if (TLI.isLittleEndian()) 2909 Offset = Offset + MSB - 1; 2910 for (unsigned i = 0; i != MSB; ++i) { 2911 Val = (Val << 8) | (unsigned char)Str[Offset]; 2912 Offset += TLI.isLittleEndian() ? -1 : 1; 2913 } 2914 return DAG.getConstant(Val, VT); 2915} 2916 2917/// getMemBasePlusOffset - Returns base and offset node for the 2918/// 2919static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2920 SelectionDAG &DAG) { 2921 MVT VT = Base.getValueType(); 2922 return DAG.getNode(ISD::ADD, Base.getDebugLoc(), 2923 VT, Base, DAG.getConstant(Offset, VT)); 2924} 2925 2926/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2927/// 2928static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2929 unsigned SrcDelta = 0; 2930 GlobalAddressSDNode *G = NULL; 2931 if (Src.getOpcode() == ISD::GlobalAddress) 2932 G = cast<GlobalAddressSDNode>(Src); 2933 else if (Src.getOpcode() == ISD::ADD && 2934 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2935 Src.getOperand(1).getOpcode() == ISD::Constant) { 2936 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2937 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 2938 } 2939 if (!G) 2940 return false; 2941 2942 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2943 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 2944 return true; 2945 2946 return false; 2947} 2948 2949/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2950/// to replace the memset / memcpy is below the threshold. It also returns the 2951/// types of the sequence of memory ops to perform memset / memcpy. 2952static 2953bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 2954 SDValue Dst, SDValue Src, 2955 unsigned Limit, uint64_t Size, unsigned &Align, 2956 std::string &Str, bool &isSrcStr, 2957 SelectionDAG &DAG, 2958 const TargetLowering &TLI) { 2959 isSrcStr = isMemSrcFromString(Src, Str); 2960 bool isSrcConst = isa<ConstantSDNode>(Src); 2961 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 2962 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 2963 if (VT != MVT::iAny) { 2964 unsigned NewAlign = (unsigned) 2965 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 2966 // If source is a string constant, this will require an unaligned load. 2967 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 2968 if (Dst.getOpcode() != ISD::FrameIndex) { 2969 // Can't change destination alignment. It requires a unaligned store. 2970 if (AllowUnalign) 2971 VT = MVT::iAny; 2972 } else { 2973 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 2974 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2975 if (MFI->isFixedObjectIndex(FI)) { 2976 // Can't change destination alignment. It requires a unaligned store. 2977 if (AllowUnalign) 2978 VT = MVT::iAny; 2979 } else { 2980 // Give the stack frame object a larger alignment if needed. 2981 if (MFI->getObjectAlignment(FI) < NewAlign) 2982 MFI->setObjectAlignment(FI, NewAlign); 2983 Align = NewAlign; 2984 } 2985 } 2986 } 2987 } 2988 2989 if (VT == MVT::iAny) { 2990 if (AllowUnalign) { 2991 VT = MVT::i64; 2992 } else { 2993 switch (Align & 7) { 2994 case 0: VT = MVT::i64; break; 2995 case 4: VT = MVT::i32; break; 2996 case 2: VT = MVT::i16; break; 2997 default: VT = MVT::i8; break; 2998 } 2999 } 3000 3001 MVT LVT = MVT::i64; 3002 while (!TLI.isTypeLegal(LVT)) 3003 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 3004 assert(LVT.isInteger()); 3005 3006 if (VT.bitsGT(LVT)) 3007 VT = LVT; 3008 } 3009 3010 unsigned NumMemOps = 0; 3011 while (Size != 0) { 3012 unsigned VTSize = VT.getSizeInBits() / 8; 3013 while (VTSize > Size) { 3014 // For now, only use non-vector load / store's for the left-over pieces. 3015 if (VT.isVector()) { 3016 VT = MVT::i64; 3017 while (!TLI.isTypeLegal(VT)) 3018 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3019 VTSize = VT.getSizeInBits() / 8; 3020 } else { 3021 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3022 VTSize >>= 1; 3023 } 3024 } 3025 3026 if (++NumMemOps > Limit) 3027 return false; 3028 MemOps.push_back(VT); 3029 Size -= VTSize; 3030 } 3031 3032 return true; 3033} 3034 3035static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3036 SDValue Chain, SDValue Dst, 3037 SDValue Src, uint64_t Size, 3038 unsigned Align, bool AlwaysInline, 3039 const Value *DstSV, uint64_t DstSVOff, 3040 const Value *SrcSV, uint64_t SrcSVOff){ 3041 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3042 3043 // Expand memcpy to a series of load and store ops if the size operand falls 3044 // below a certain threshold. 3045 std::vector<MVT> MemOps; 3046 uint64_t Limit = -1ULL; 3047 if (!AlwaysInline) 3048 Limit = TLI.getMaxStoresPerMemcpy(); 3049 unsigned DstAlign = Align; // Destination alignment can change. 3050 std::string Str; 3051 bool CopyFromStr; 3052 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3053 Str, CopyFromStr, DAG, TLI)) 3054 return SDValue(); 3055 3056 3057 bool isZeroStr = CopyFromStr && Str.empty(); 3058 SmallVector<SDValue, 8> OutChains; 3059 unsigned NumMemOps = MemOps.size(); 3060 uint64_t SrcOff = 0, DstOff = 0; 3061 for (unsigned i = 0; i < NumMemOps; i++) { 3062 MVT VT = MemOps[i]; 3063 unsigned VTSize = VT.getSizeInBits() / 8; 3064 SDValue Value, Store; 3065 3066 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 3067 // It's unlikely a store of a vector immediate can be done in a single 3068 // instruction. It would require a load from a constantpool first. 3069 // We also handle store a vector with all zero's. 3070 // FIXME: Handle other cases where store of vector immediate is done in 3071 // a single instruction. 3072 Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff); 3073 Store = DAG.getStore(Chain, dl, Value, 3074 getMemBasePlusOffset(Dst, DstOff, DAG), 3075 DstSV, DstSVOff + DstOff, false, DstAlign); 3076 } else { 3077 Value = DAG.getLoad(VT, dl, Chain, 3078 getMemBasePlusOffset(Src, SrcOff, DAG), 3079 SrcSV, SrcSVOff + SrcOff, false, Align); 3080 Store = DAG.getStore(Chain, dl, Value, 3081 getMemBasePlusOffset(Dst, DstOff, DAG), 3082 DstSV, DstSVOff + DstOff, false, DstAlign); 3083 } 3084 OutChains.push_back(Store); 3085 SrcOff += VTSize; 3086 DstOff += VTSize; 3087 } 3088 3089 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3090 &OutChains[0], OutChains.size()); 3091} 3092 3093static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3094 SDValue Chain, SDValue Dst, 3095 SDValue Src, uint64_t Size, 3096 unsigned Align, bool AlwaysInline, 3097 const Value *DstSV, uint64_t DstSVOff, 3098 const Value *SrcSV, uint64_t SrcSVOff){ 3099 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3100 3101 // Expand memmove to a series of load and store ops if the size operand falls 3102 // below a certain threshold. 3103 std::vector<MVT> MemOps; 3104 uint64_t Limit = -1ULL; 3105 if (!AlwaysInline) 3106 Limit = TLI.getMaxStoresPerMemmove(); 3107 unsigned DstAlign = Align; // Destination alignment can change. 3108 std::string Str; 3109 bool CopyFromStr; 3110 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3111 Str, CopyFromStr, DAG, TLI)) 3112 return SDValue(); 3113 3114 uint64_t SrcOff = 0, DstOff = 0; 3115 3116 SmallVector<SDValue, 8> LoadValues; 3117 SmallVector<SDValue, 8> LoadChains; 3118 SmallVector<SDValue, 8> OutChains; 3119 unsigned NumMemOps = MemOps.size(); 3120 for (unsigned i = 0; i < NumMemOps; i++) { 3121 MVT VT = MemOps[i]; 3122 unsigned VTSize = VT.getSizeInBits() / 8; 3123 SDValue Value, Store; 3124 3125 Value = DAG.getLoad(VT, dl, Chain, 3126 getMemBasePlusOffset(Src, SrcOff, DAG), 3127 SrcSV, SrcSVOff + SrcOff, false, Align); 3128 LoadValues.push_back(Value); 3129 LoadChains.push_back(Value.getValue(1)); 3130 SrcOff += VTSize; 3131 } 3132 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3133 &LoadChains[0], LoadChains.size()); 3134 OutChains.clear(); 3135 for (unsigned i = 0; i < NumMemOps; i++) { 3136 MVT VT = MemOps[i]; 3137 unsigned VTSize = VT.getSizeInBits() / 8; 3138 SDValue Value, Store; 3139 3140 Store = DAG.getStore(Chain, dl, LoadValues[i], 3141 getMemBasePlusOffset(Dst, DstOff, DAG), 3142 DstSV, DstSVOff + DstOff, false, DstAlign); 3143 OutChains.push_back(Store); 3144 DstOff += VTSize; 3145 } 3146 3147 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3148 &OutChains[0], OutChains.size()); 3149} 3150 3151static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, 3152 SDValue Chain, SDValue Dst, 3153 SDValue Src, uint64_t Size, 3154 unsigned Align, 3155 const Value *DstSV, uint64_t DstSVOff) { 3156 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3157 3158 // Expand memset to a series of load/store ops if the size operand 3159 // falls below a certain threshold. 3160 std::vector<MVT> MemOps; 3161 std::string Str; 3162 bool CopyFromStr; 3163 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3164 Size, Align, Str, CopyFromStr, DAG, TLI)) 3165 return SDValue(); 3166 3167 SmallVector<SDValue, 8> OutChains; 3168 uint64_t DstOff = 0; 3169 3170 unsigned NumMemOps = MemOps.size(); 3171 for (unsigned i = 0; i < NumMemOps; i++) { 3172 MVT VT = MemOps[i]; 3173 unsigned VTSize = VT.getSizeInBits() / 8; 3174 SDValue Value = getMemsetValue(Src, VT, DAG, dl); 3175 SDValue Store = DAG.getStore(Chain, dl, Value, 3176 getMemBasePlusOffset(Dst, DstOff, DAG), 3177 DstSV, DstSVOff + DstOff); 3178 OutChains.push_back(Store); 3179 DstOff += VTSize; 3180 } 3181 3182 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3183 &OutChains[0], OutChains.size()); 3184} 3185 3186SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, 3187 SDValue Src, SDValue Size, 3188 unsigned Align, bool AlwaysInline, 3189 const Value *DstSV, uint64_t DstSVOff, 3190 const Value *SrcSV, uint64_t SrcSVOff) { 3191 3192 // Check to see if we should lower the memcpy to loads and stores first. 3193 // For cases within the target-specified limits, this is the best choice. 3194 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3195 if (ConstantSize) { 3196 // Memcpy with size zero? Just return the original chain. 3197 if (ConstantSize->isNullValue()) 3198 return Chain; 3199 3200 SDValue Result = 3201 getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3202 ConstantSize->getZExtValue(), 3203 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3204 if (Result.getNode()) 3205 return Result; 3206 } 3207 3208 // Then check to see if we should lower the memcpy with target-specific 3209 // code. If the target chooses to do this, this is the next best. 3210 SDValue Result = 3211 TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align, 3212 AlwaysInline, 3213 DstSV, DstSVOff, SrcSV, SrcSVOff); 3214 if (Result.getNode()) 3215 return Result; 3216 3217 // If we really need inline code and the target declined to provide it, 3218 // use a (potentially long) sequence of loads and stores. 3219 if (AlwaysInline) { 3220 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3221 return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3222 ConstantSize->getZExtValue(), Align, true, 3223 DstSV, DstSVOff, SrcSV, SrcSVOff); 3224 } 3225 3226 // Emit a library call. 3227 TargetLowering::ArgListTy Args; 3228 TargetLowering::ArgListEntry Entry; 3229 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3230 Entry.Node = Dst; Args.push_back(Entry); 3231 Entry.Node = Src; Args.push_back(Entry); 3232 Entry.Node = Size; Args.push_back(Entry); 3233 // FIXME: pass in DebugLoc 3234 std::pair<SDValue,SDValue> CallResult = 3235 TLI.LowerCallTo(Chain, Type::VoidTy, 3236 false, false, false, false, CallingConv::C, false, 3237 getExternalSymbol("memcpy", TLI.getPointerTy()), 3238 Args, *this, dl); 3239 return CallResult.second; 3240} 3241 3242SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, 3243 SDValue Src, SDValue Size, 3244 unsigned Align, 3245 const Value *DstSV, uint64_t DstSVOff, 3246 const Value *SrcSV, uint64_t SrcSVOff) { 3247 3248 // Check to see if we should lower the memmove to loads and stores first. 3249 // For cases within the target-specified limits, this is the best choice. 3250 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3251 if (ConstantSize) { 3252 // Memmove with size zero? Just return the original chain. 3253 if (ConstantSize->isNullValue()) 3254 return Chain; 3255 3256 SDValue Result = 3257 getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src, 3258 ConstantSize->getZExtValue(), 3259 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3260 if (Result.getNode()) 3261 return Result; 3262 } 3263 3264 // Then check to see if we should lower the memmove with target-specific 3265 // code. If the target chooses to do this, this is the next best. 3266 SDValue Result = 3267 TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align, 3268 DstSV, DstSVOff, SrcSV, SrcSVOff); 3269 if (Result.getNode()) 3270 return Result; 3271 3272 // Emit a library call. 3273 TargetLowering::ArgListTy Args; 3274 TargetLowering::ArgListEntry Entry; 3275 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3276 Entry.Node = Dst; Args.push_back(Entry); 3277 Entry.Node = Src; Args.push_back(Entry); 3278 Entry.Node = Size; Args.push_back(Entry); 3279 // FIXME: pass in DebugLoc 3280 std::pair<SDValue,SDValue> CallResult = 3281 TLI.LowerCallTo(Chain, Type::VoidTy, 3282 false, false, false, false, CallingConv::C, false, 3283 getExternalSymbol("memmove", TLI.getPointerTy()), 3284 Args, *this, dl); 3285 return CallResult.second; 3286} 3287 3288SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, 3289 SDValue Src, SDValue Size, 3290 unsigned Align, 3291 const Value *DstSV, uint64_t DstSVOff) { 3292 3293 // Check to see if we should lower the memset to stores first. 3294 // For cases within the target-specified limits, this is the best choice. 3295 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3296 if (ConstantSize) { 3297 // Memset with size zero? Just return the original chain. 3298 if (ConstantSize->isNullValue()) 3299 return Chain; 3300 3301 SDValue Result = 3302 getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), 3303 Align, DstSV, DstSVOff); 3304 if (Result.getNode()) 3305 return Result; 3306 } 3307 3308 // Then check to see if we should lower the memset with target-specific 3309 // code. If the target chooses to do this, this is the next best. 3310 SDValue Result = 3311 TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align, 3312 DstSV, DstSVOff); 3313 if (Result.getNode()) 3314 return Result; 3315 3316 // Emit a library call. 3317 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3318 TargetLowering::ArgListTy Args; 3319 TargetLowering::ArgListEntry Entry; 3320 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3321 Args.push_back(Entry); 3322 // Extend or truncate the argument to be an i32 value for the call. 3323 if (Src.getValueType().bitsGT(MVT::i32)) 3324 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src); 3325 else 3326 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); 3327 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3328 Args.push_back(Entry); 3329 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3330 Args.push_back(Entry); 3331 // FIXME: pass in DebugLoc 3332 std::pair<SDValue,SDValue> CallResult = 3333 TLI.LowerCallTo(Chain, Type::VoidTy, 3334 false, false, false, false, CallingConv::C, false, 3335 getExternalSymbol("memset", TLI.getPointerTy()), 3336 Args, *this, dl); 3337 return CallResult.second; 3338} 3339 3340SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3341 SDValue Chain, 3342 SDValue Ptr, SDValue Cmp, 3343 SDValue Swp, const Value* PtrVal, 3344 unsigned Alignment) { 3345 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); 3346 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3347 3348 MVT VT = Cmp.getValueType(); 3349 3350 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3351 Alignment = getMVTAlignment(MemVT); 3352 3353 SDVTList VTs = getVTList(VT, MVT::Other); 3354 FoldingSetNodeID ID; 3355 ID.AddInteger(MemVT.getRawBits()); 3356 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3357 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3358 void* IP = 0; 3359 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3360 return SDValue(E, 0); 3361 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3362 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3363 Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3364 CSEMap.InsertNode(N, IP); 3365 AllNodes.push_back(N); 3366 return SDValue(N, 0); 3367} 3368 3369SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3370 SDValue Chain, 3371 SDValue Ptr, SDValue Val, 3372 const Value* PtrVal, 3373 unsigned Alignment) { 3374 assert((Opcode == ISD::ATOMIC_LOAD_ADD || 3375 Opcode == ISD::ATOMIC_LOAD_SUB || 3376 Opcode == ISD::ATOMIC_LOAD_AND || 3377 Opcode == ISD::ATOMIC_LOAD_OR || 3378 Opcode == ISD::ATOMIC_LOAD_XOR || 3379 Opcode == ISD::ATOMIC_LOAD_NAND || 3380 Opcode == ISD::ATOMIC_LOAD_MIN || 3381 Opcode == ISD::ATOMIC_LOAD_MAX || 3382 Opcode == ISD::ATOMIC_LOAD_UMIN || 3383 Opcode == ISD::ATOMIC_LOAD_UMAX || 3384 Opcode == ISD::ATOMIC_SWAP) && 3385 "Invalid Atomic Op"); 3386 3387 MVT VT = Val.getValueType(); 3388 3389 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3390 Alignment = getMVTAlignment(MemVT); 3391 3392 SDVTList VTs = getVTList(VT, MVT::Other); 3393 FoldingSetNodeID ID; 3394 ID.AddInteger(MemVT.getRawBits()); 3395 SDValue Ops[] = {Chain, Ptr, Val}; 3396 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3397 void* IP = 0; 3398 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3399 return SDValue(E, 0); 3400 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3401 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3402 Chain, Ptr, Val, PtrVal, Alignment); 3403 CSEMap.InsertNode(N, IP); 3404 AllNodes.push_back(N); 3405 return SDValue(N, 0); 3406} 3407 3408/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3409/// Allowed to return something different (and simpler) if Simplify is true. 3410SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3411 DebugLoc dl) { 3412 if (NumOps == 1) 3413 return Ops[0]; 3414 3415 SmallVector<MVT, 4> VTs; 3416 VTs.reserve(NumOps); 3417 for (unsigned i = 0; i < NumOps; ++i) 3418 VTs.push_back(Ops[i].getValueType()); 3419 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps), 3420 Ops, NumOps); 3421} 3422 3423SDValue 3424SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, 3425 const MVT *VTs, unsigned NumVTs, 3426 const SDValue *Ops, unsigned NumOps, 3427 MVT MemVT, const Value *srcValue, int SVOff, 3428 unsigned Align, bool Vol, 3429 bool ReadMem, bool WriteMem) { 3430 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps, 3431 MemVT, srcValue, SVOff, Align, Vol, 3432 ReadMem, WriteMem); 3433} 3434 3435SDValue 3436SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, 3437 const SDValue *Ops, unsigned NumOps, 3438 MVT MemVT, const Value *srcValue, int SVOff, 3439 unsigned Align, bool Vol, 3440 bool ReadMem, bool WriteMem) { 3441 // Memoize the node unless it returns a flag. 3442 MemIntrinsicSDNode *N; 3443 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3444 FoldingSetNodeID ID; 3445 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3446 void *IP = 0; 3447 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3448 return SDValue(E, 0); 3449 3450 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3451 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3452 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3453 CSEMap.InsertNode(N, IP); 3454 } else { 3455 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3456 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3457 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3458 } 3459 AllNodes.push_back(N); 3460 return SDValue(N, 0); 3461} 3462 3463SDValue 3464SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, 3465 bool IsTailCall, bool IsInreg, SDVTList VTs, 3466 const SDValue *Operands, unsigned NumOperands) { 3467 // Do not include isTailCall in the folding set profile. 3468 FoldingSetNodeID ID; 3469 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3470 ID.AddInteger(CallingConv); 3471 ID.AddInteger(IsVarArgs); 3472 void *IP = 0; 3473 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3474 // Instead of including isTailCall in the folding set, we just 3475 // set the flag of the existing node. 3476 if (!IsTailCall) 3477 cast<CallSDNode>(E)->setNotTailCall(); 3478 return SDValue(E, 0); 3479 } 3480 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3481 new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg, 3482 VTs, Operands, NumOperands); 3483 CSEMap.InsertNode(N, IP); 3484 AllNodes.push_back(N); 3485 return SDValue(N, 0); 3486} 3487 3488SDValue 3489SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, 3490 ISD::LoadExtType ExtType, MVT VT, SDValue Chain, 3491 SDValue Ptr, SDValue Offset, 3492 const Value *SV, int SVOffset, MVT EVT, 3493 bool isVolatile, unsigned Alignment) { 3494 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3495 Alignment = getMVTAlignment(VT); 3496 3497 if (VT == EVT) { 3498 ExtType = ISD::NON_EXTLOAD; 3499 } else if (ExtType == ISD::NON_EXTLOAD) { 3500 assert(VT == EVT && "Non-extending load from different memory type!"); 3501 } else { 3502 // Extending load. 3503 if (VT.isVector()) 3504 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3505 "Invalid vector extload!"); 3506 else 3507 assert(EVT.bitsLT(VT) && 3508 "Should only be an extending load, not truncating!"); 3509 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3510 "Cannot sign/zero extend a FP/Vector load!"); 3511 assert(VT.isInteger() == EVT.isInteger() && 3512 "Cannot convert from FP to Int or Int -> FP!"); 3513 } 3514 3515 bool Indexed = AM != ISD::UNINDEXED; 3516 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3517 "Unindexed load with an offset!"); 3518 3519 SDVTList VTs = Indexed ? 3520 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3521 SDValue Ops[] = { Chain, Ptr, Offset }; 3522 FoldingSetNodeID ID; 3523 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3524 ID.AddInteger(EVT.getRawBits()); 3525 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); 3526 void *IP = 0; 3527 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3528 return SDValue(E, 0); 3529 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3530 new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset, 3531 Alignment, isVolatile); 3532 CSEMap.InsertNode(N, IP); 3533 AllNodes.push_back(N); 3534 return SDValue(N, 0); 3535} 3536 3537SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, 3538 SDValue Chain, SDValue Ptr, 3539 const Value *SV, int SVOffset, 3540 bool isVolatile, unsigned Alignment) { 3541 SDValue Undef = getUNDEF(Ptr.getValueType()); 3542 return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3543 SV, SVOffset, VT, isVolatile, Alignment); 3544} 3545 3546SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, 3547 SDValue Chain, SDValue Ptr, 3548 const Value *SV, 3549 int SVOffset, MVT EVT, 3550 bool isVolatile, unsigned Alignment) { 3551 SDValue Undef = getUNDEF(Ptr.getValueType()); 3552 return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef, 3553 SV, SVOffset, EVT, isVolatile, Alignment); 3554} 3555 3556SDValue 3557SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, 3558 SDValue Offset, ISD::MemIndexedMode AM) { 3559 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3560 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3561 "Load is already a indexed load!"); 3562 return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(), 3563 LD->getChain(), Base, Offset, LD->getSrcValue(), 3564 LD->getSrcValueOffset(), LD->getMemoryVT(), 3565 LD->isVolatile(), LD->getAlignment()); 3566} 3567 3568SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, 3569 SDValue Ptr, const Value *SV, int SVOffset, 3570 bool isVolatile, unsigned Alignment) { 3571 MVT VT = Val.getValueType(); 3572 3573 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3574 Alignment = getMVTAlignment(VT); 3575 3576 SDVTList VTs = getVTList(MVT::Other); 3577 SDValue Undef = getUNDEF(Ptr.getValueType()); 3578 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3579 FoldingSetNodeID ID; 3580 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3581 ID.AddInteger(VT.getRawBits()); 3582 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, 3583 isVolatile, Alignment)); 3584 void *IP = 0; 3585 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3586 return SDValue(E, 0); 3587 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3588 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false, 3589 VT, SV, SVOffset, Alignment, isVolatile); 3590 CSEMap.InsertNode(N, IP); 3591 AllNodes.push_back(N); 3592 return SDValue(N, 0); 3593} 3594 3595SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, 3596 SDValue Ptr, const Value *SV, 3597 int SVOffset, MVT SVT, 3598 bool isVolatile, unsigned Alignment) { 3599 MVT VT = Val.getValueType(); 3600 3601 if (VT == SVT) 3602 return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3603 3604 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3605 assert(VT.isInteger() == SVT.isInteger() && 3606 "Can't do FP-INT conversion!"); 3607 3608 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3609 Alignment = getMVTAlignment(VT); 3610 3611 SDVTList VTs = getVTList(MVT::Other); 3612 SDValue Undef = getUNDEF(Ptr.getValueType()); 3613 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3614 FoldingSetNodeID ID; 3615 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3616 ID.AddInteger(SVT.getRawBits()); 3617 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, 3618 isVolatile, Alignment)); 3619 void *IP = 0; 3620 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3621 return SDValue(E, 0); 3622 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3623 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true, 3624 SVT, SV, SVOffset, Alignment, isVolatile); 3625 CSEMap.InsertNode(N, IP); 3626 AllNodes.push_back(N); 3627 return SDValue(N, 0); 3628} 3629 3630SDValue 3631SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, 3632 SDValue Offset, ISD::MemIndexedMode AM) { 3633 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3634 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3635 "Store is already a indexed store!"); 3636 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3637 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3638 FoldingSetNodeID ID; 3639 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3640 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3641 ID.AddInteger(ST->getRawSubclassData()); 3642 void *IP = 0; 3643 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3644 return SDValue(E, 0); 3645 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3646 new (N) StoreSDNode(Ops, dl, VTs, AM, 3647 ST->isTruncatingStore(), ST->getMemoryVT(), 3648 ST->getSrcValue(), ST->getSrcValueOffset(), 3649 ST->getAlignment(), ST->isVolatile()); 3650 CSEMap.InsertNode(N, IP); 3651 AllNodes.push_back(N); 3652 return SDValue(N, 0); 3653} 3654 3655SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl, 3656 SDValue Chain, SDValue Ptr, 3657 SDValue SV) { 3658 SDValue Ops[] = { Chain, Ptr, SV }; 3659 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3); 3660} 3661 3662SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3663 const SDUse *Ops, unsigned NumOps) { 3664 switch (NumOps) { 3665 case 0: return getNode(Opcode, DL, VT); 3666 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3667 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3668 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3669 default: break; 3670 } 3671 3672 // Copy from an SDUse array into an SDValue array for use with 3673 // the regular getNode logic. 3674 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3675 return getNode(Opcode, DL, VT, &NewOps[0], NumOps); 3676} 3677 3678SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3679 const SDValue *Ops, unsigned NumOps) { 3680 switch (NumOps) { 3681 case 0: return getNode(Opcode, DL, VT); 3682 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3683 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3684 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3685 default: break; 3686 } 3687 3688 switch (Opcode) { 3689 default: break; 3690 case ISD::SELECT_CC: { 3691 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3692 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3693 "LHS and RHS of condition must have same type!"); 3694 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3695 "True and False arms of SelectCC must have same type!"); 3696 assert(Ops[2].getValueType() == VT && 3697 "select_cc node must be of same type as true and false value!"); 3698 break; 3699 } 3700 case ISD::BR_CC: { 3701 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3702 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3703 "LHS/RHS of comparison should match types!"); 3704 break; 3705 } 3706 } 3707 3708 // Memoize nodes. 3709 SDNode *N; 3710 SDVTList VTs = getVTList(VT); 3711 3712 if (VT != MVT::Flag) { 3713 FoldingSetNodeID ID; 3714 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3715 void *IP = 0; 3716 3717 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3718 return SDValue(E, 0); 3719 3720 N = NodeAllocator.Allocate<SDNode>(); 3721 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3722 CSEMap.InsertNode(N, IP); 3723 } else { 3724 N = NodeAllocator.Allocate<SDNode>(); 3725 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3726 } 3727 3728 AllNodes.push_back(N); 3729#ifndef NDEBUG 3730 VerifyNode(N); 3731#endif 3732 return SDValue(N, 0); 3733} 3734 3735SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3736 const std::vector<MVT> &ResultTys, 3737 const SDValue *Ops, unsigned NumOps) { 3738 return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()), 3739 Ops, NumOps); 3740} 3741 3742SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3743 const MVT *VTs, unsigned NumVTs, 3744 const SDValue *Ops, unsigned NumOps) { 3745 if (NumVTs == 1) 3746 return getNode(Opcode, DL, VTs[0], Ops, NumOps); 3747 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps); 3748} 3749 3750SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3751 const SDValue *Ops, unsigned NumOps) { 3752 if (VTList.NumVTs == 1) 3753 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps); 3754 3755 switch (Opcode) { 3756 // FIXME: figure out how to safely handle things like 3757 // int foo(int x) { return 1 << (x & 255); } 3758 // int bar() { return foo(256); } 3759#if 0 3760 case ISD::SRA_PARTS: 3761 case ISD::SRL_PARTS: 3762 case ISD::SHL_PARTS: 3763 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3764 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3765 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3766 else if (N3.getOpcode() == ISD::AND) 3767 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3768 // If the and is only masking out bits that cannot effect the shift, 3769 // eliminate the and. 3770 unsigned NumBits = VT.getSizeInBits()*2; 3771 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3772 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3773 } 3774 break; 3775#endif 3776 } 3777 3778 // Memoize the node unless it returns a flag. 3779 SDNode *N; 3780 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3781 FoldingSetNodeID ID; 3782 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3783 void *IP = 0; 3784 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3785 return SDValue(E, 0); 3786 if (NumOps == 1) { 3787 N = NodeAllocator.Allocate<UnarySDNode>(); 3788 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3789 } else if (NumOps == 2) { 3790 N = NodeAllocator.Allocate<BinarySDNode>(); 3791 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3792 } else if (NumOps == 3) { 3793 N = NodeAllocator.Allocate<TernarySDNode>(); 3794 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3795 } else { 3796 N = NodeAllocator.Allocate<SDNode>(); 3797 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3798 } 3799 CSEMap.InsertNode(N, IP); 3800 } else { 3801 if (NumOps == 1) { 3802 N = NodeAllocator.Allocate<UnarySDNode>(); 3803 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3804 } else if (NumOps == 2) { 3805 N = NodeAllocator.Allocate<BinarySDNode>(); 3806 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3807 } else if (NumOps == 3) { 3808 N = NodeAllocator.Allocate<TernarySDNode>(); 3809 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3810 } else { 3811 N = NodeAllocator.Allocate<SDNode>(); 3812 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3813 } 3814 } 3815 AllNodes.push_back(N); 3816#ifndef NDEBUG 3817 VerifyNode(N); 3818#endif 3819 return SDValue(N, 0); 3820} 3821 3822SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) { 3823 return getNode(Opcode, DL, VTList, 0, 0); 3824} 3825 3826SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3827 SDValue N1) { 3828 SDValue Ops[] = { N1 }; 3829 return getNode(Opcode, DL, VTList, Ops, 1); 3830} 3831 3832SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3833 SDValue N1, SDValue N2) { 3834 SDValue Ops[] = { N1, N2 }; 3835 return getNode(Opcode, DL, VTList, Ops, 2); 3836} 3837 3838SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3839 SDValue N1, SDValue N2, SDValue N3) { 3840 SDValue Ops[] = { N1, N2, N3 }; 3841 return getNode(Opcode, DL, VTList, Ops, 3); 3842} 3843 3844SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3845 SDValue N1, SDValue N2, SDValue N3, 3846 SDValue N4) { 3847 SDValue Ops[] = { N1, N2, N3, N4 }; 3848 return getNode(Opcode, DL, VTList, Ops, 4); 3849} 3850 3851SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3852 SDValue N1, SDValue N2, SDValue N3, 3853 SDValue N4, SDValue N5) { 3854 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3855 return getNode(Opcode, DL, VTList, Ops, 5); 3856} 3857 3858SDVTList SelectionDAG::getVTList(MVT VT) { 3859 return makeVTList(SDNode::getValueTypeList(VT), 1); 3860} 3861 3862SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3863 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3864 E = VTList.rend(); I != E; ++I) 3865 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3866 return *I; 3867 3868 MVT *Array = Allocator.Allocate<MVT>(2); 3869 Array[0] = VT1; 3870 Array[1] = VT2; 3871 SDVTList Result = makeVTList(Array, 2); 3872 VTList.push_back(Result); 3873 return Result; 3874} 3875 3876SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3877 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3878 E = VTList.rend(); I != E; ++I) 3879 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3880 I->VTs[2] == VT3) 3881 return *I; 3882 3883 MVT *Array = Allocator.Allocate<MVT>(3); 3884 Array[0] = VT1; 3885 Array[1] = VT2; 3886 Array[2] = VT3; 3887 SDVTList Result = makeVTList(Array, 3); 3888 VTList.push_back(Result); 3889 return Result; 3890} 3891 3892SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { 3893 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3894 E = VTList.rend(); I != E; ++I) 3895 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3896 I->VTs[2] == VT3 && I->VTs[3] == VT4) 3897 return *I; 3898 3899 MVT *Array = Allocator.Allocate<MVT>(3); 3900 Array[0] = VT1; 3901 Array[1] = VT2; 3902 Array[2] = VT3; 3903 Array[3] = VT4; 3904 SDVTList Result = makeVTList(Array, 4); 3905 VTList.push_back(Result); 3906 return Result; 3907} 3908 3909SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3910 switch (NumVTs) { 3911 case 0: assert(0 && "Cannot have nodes without results!"); 3912 case 1: return getVTList(VTs[0]); 3913 case 2: return getVTList(VTs[0], VTs[1]); 3914 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3915 default: break; 3916 } 3917 3918 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3919 E = VTList.rend(); I != E; ++I) { 3920 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3921 continue; 3922 3923 bool NoMatch = false; 3924 for (unsigned i = 2; i != NumVTs; ++i) 3925 if (VTs[i] != I->VTs[i]) { 3926 NoMatch = true; 3927 break; 3928 } 3929 if (!NoMatch) 3930 return *I; 3931 } 3932 3933 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 3934 std::copy(VTs, VTs+NumVTs, Array); 3935 SDVTList Result = makeVTList(Array, NumVTs); 3936 VTList.push_back(Result); 3937 return Result; 3938} 3939 3940 3941/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 3942/// specified operands. If the resultant node already exists in the DAG, 3943/// this does not modify the specified node, instead it returns the node that 3944/// already exists. If the resultant node does not exist in the DAG, the 3945/// input node is returned. As a degenerate case, if you specify the same 3946/// input operands as the node already has, the input node is returned. 3947SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 3948 SDNode *N = InN.getNode(); 3949 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 3950 3951 // Check to see if there is no change. 3952 if (Op == N->getOperand(0)) return InN; 3953 3954 // See if the modified node already exists. 3955 void *InsertPos = 0; 3956 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 3957 return SDValue(Existing, InN.getResNo()); 3958 3959 // Nope it doesn't. Remove the node from its current place in the maps. 3960 if (InsertPos) 3961 if (!RemoveNodeFromCSEMaps(N)) 3962 InsertPos = 0; 3963 3964 // Now we update the operands. 3965 N->OperandList[0].set(Op); 3966 3967 // If this gets put into a CSE map, add it. 3968 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3969 return InN; 3970} 3971 3972SDValue SelectionDAG:: 3973UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 3974 SDNode *N = InN.getNode(); 3975 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 3976 3977 // Check to see if there is no change. 3978 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 3979 return InN; // No operands changed, just return the input node. 3980 3981 // See if the modified node already exists. 3982 void *InsertPos = 0; 3983 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 3984 return SDValue(Existing, InN.getResNo()); 3985 3986 // Nope it doesn't. Remove the node from its current place in the maps. 3987 if (InsertPos) 3988 if (!RemoveNodeFromCSEMaps(N)) 3989 InsertPos = 0; 3990 3991 // Now we update the operands. 3992 if (N->OperandList[0] != Op1) 3993 N->OperandList[0].set(Op1); 3994 if (N->OperandList[1] != Op2) 3995 N->OperandList[1].set(Op2); 3996 3997 // If this gets put into a CSE map, add it. 3998 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3999 return InN; 4000} 4001 4002SDValue SelectionDAG:: 4003UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 4004 SDValue Ops[] = { Op1, Op2, Op3 }; 4005 return UpdateNodeOperands(N, Ops, 3); 4006} 4007 4008SDValue SelectionDAG:: 4009UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4010 SDValue Op3, SDValue Op4) { 4011 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 4012 return UpdateNodeOperands(N, Ops, 4); 4013} 4014 4015SDValue SelectionDAG:: 4016UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4017 SDValue Op3, SDValue Op4, SDValue Op5) { 4018 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 4019 return UpdateNodeOperands(N, Ops, 5); 4020} 4021 4022SDValue SelectionDAG:: 4023UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 4024 SDNode *N = InN.getNode(); 4025 assert(N->getNumOperands() == NumOps && 4026 "Update with wrong number of operands"); 4027 4028 // Check to see if there is no change. 4029 bool AnyChange = false; 4030 for (unsigned i = 0; i != NumOps; ++i) { 4031 if (Ops[i] != N->getOperand(i)) { 4032 AnyChange = true; 4033 break; 4034 } 4035 } 4036 4037 // No operands changed, just return the input node. 4038 if (!AnyChange) return InN; 4039 4040 // See if the modified node already exists. 4041 void *InsertPos = 0; 4042 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 4043 return SDValue(Existing, InN.getResNo()); 4044 4045 // Nope it doesn't. Remove the node from its current place in the maps. 4046 if (InsertPos) 4047 if (!RemoveNodeFromCSEMaps(N)) 4048 InsertPos = 0; 4049 4050 // Now we update the operands. 4051 for (unsigned i = 0; i != NumOps; ++i) 4052 if (N->OperandList[i] != Ops[i]) 4053 N->OperandList[i].set(Ops[i]); 4054 4055 // If this gets put into a CSE map, add it. 4056 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4057 return InN; 4058} 4059 4060/// DropOperands - Release the operands and set this node to have 4061/// zero operands. 4062void SDNode::DropOperands() { 4063 // Unlike the code in MorphNodeTo that does this, we don't need to 4064 // watch for dead nodes here. 4065 for (op_iterator I = op_begin(), E = op_end(); I != E; ) { 4066 SDUse &Use = *I++; 4067 Use.set(SDValue()); 4068 } 4069} 4070 4071/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4072/// machine opcode. 4073/// 4074SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4075 MVT VT) { 4076 SDVTList VTs = getVTList(VT); 4077 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4078} 4079 4080SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4081 MVT VT, SDValue Op1) { 4082 SDVTList VTs = getVTList(VT); 4083 SDValue Ops[] = { Op1 }; 4084 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4085} 4086 4087SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4088 MVT VT, SDValue Op1, 4089 SDValue Op2) { 4090 SDVTList VTs = getVTList(VT); 4091 SDValue Ops[] = { Op1, Op2 }; 4092 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4093} 4094 4095SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4096 MVT VT, SDValue Op1, 4097 SDValue Op2, SDValue Op3) { 4098 SDVTList VTs = getVTList(VT); 4099 SDValue Ops[] = { Op1, Op2, Op3 }; 4100 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4101} 4102 4103SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4104 MVT VT, const SDValue *Ops, 4105 unsigned NumOps) { 4106 SDVTList VTs = getVTList(VT); 4107 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4108} 4109 4110SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4111 MVT VT1, MVT VT2, const SDValue *Ops, 4112 unsigned NumOps) { 4113 SDVTList VTs = getVTList(VT1, VT2); 4114 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4115} 4116 4117SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4118 MVT VT1, MVT VT2) { 4119 SDVTList VTs = getVTList(VT1, VT2); 4120 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4121} 4122 4123SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4124 MVT VT1, MVT VT2, MVT VT3, 4125 const SDValue *Ops, unsigned NumOps) { 4126 SDVTList VTs = getVTList(VT1, VT2, VT3); 4127 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4128} 4129 4130SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4131 MVT VT1, MVT VT2, MVT VT3, MVT VT4, 4132 const SDValue *Ops, unsigned NumOps) { 4133 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4134 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4135} 4136 4137SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4138 MVT VT1, MVT VT2, 4139 SDValue Op1) { 4140 SDVTList VTs = getVTList(VT1, VT2); 4141 SDValue Ops[] = { Op1 }; 4142 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4143} 4144 4145SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4146 MVT VT1, MVT VT2, 4147 SDValue Op1, SDValue Op2) { 4148 SDVTList VTs = getVTList(VT1, VT2); 4149 SDValue Ops[] = { Op1, Op2 }; 4150 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4151} 4152 4153SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4154 MVT VT1, MVT VT2, 4155 SDValue Op1, SDValue Op2, 4156 SDValue Op3) { 4157 SDVTList VTs = getVTList(VT1, VT2); 4158 SDValue Ops[] = { Op1, Op2, Op3 }; 4159 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4160} 4161 4162SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4163 MVT VT1, MVT VT2, MVT VT3, 4164 SDValue Op1, SDValue Op2, 4165 SDValue Op3) { 4166 SDVTList VTs = getVTList(VT1, VT2, VT3); 4167 SDValue Ops[] = { Op1, Op2, Op3 }; 4168 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4169} 4170 4171SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4172 SDVTList VTs, const SDValue *Ops, 4173 unsigned NumOps) { 4174 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4175} 4176 4177SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4178 MVT VT) { 4179 SDVTList VTs = getVTList(VT); 4180 return MorphNodeTo(N, Opc, VTs, 0, 0); 4181} 4182 4183SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4184 MVT VT, SDValue Op1) { 4185 SDVTList VTs = getVTList(VT); 4186 SDValue Ops[] = { Op1 }; 4187 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4188} 4189 4190SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4191 MVT VT, SDValue Op1, 4192 SDValue Op2) { 4193 SDVTList VTs = getVTList(VT); 4194 SDValue Ops[] = { Op1, Op2 }; 4195 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4196} 4197 4198SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4199 MVT VT, SDValue Op1, 4200 SDValue Op2, SDValue Op3) { 4201 SDVTList VTs = getVTList(VT); 4202 SDValue Ops[] = { Op1, Op2, Op3 }; 4203 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4204} 4205 4206SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4207 MVT VT, const SDValue *Ops, 4208 unsigned NumOps) { 4209 SDVTList VTs = getVTList(VT); 4210 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4211} 4212 4213SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4214 MVT VT1, MVT VT2, const SDValue *Ops, 4215 unsigned NumOps) { 4216 SDVTList VTs = getVTList(VT1, VT2); 4217 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4218} 4219 4220SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4221 MVT VT1, MVT VT2) { 4222 SDVTList VTs = getVTList(VT1, VT2); 4223 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4224} 4225 4226SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4227 MVT VT1, MVT VT2, MVT VT3, 4228 const SDValue *Ops, unsigned NumOps) { 4229 SDVTList VTs = getVTList(VT1, VT2, VT3); 4230 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4231} 4232 4233SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4234 MVT VT1, MVT VT2, 4235 SDValue Op1) { 4236 SDVTList VTs = getVTList(VT1, VT2); 4237 SDValue Ops[] = { Op1 }; 4238 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4239} 4240 4241SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4242 MVT VT1, MVT VT2, 4243 SDValue Op1, SDValue Op2) { 4244 SDVTList VTs = getVTList(VT1, VT2); 4245 SDValue Ops[] = { Op1, Op2 }; 4246 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4247} 4248 4249SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4250 MVT VT1, MVT VT2, 4251 SDValue Op1, SDValue Op2, 4252 SDValue Op3) { 4253 SDVTList VTs = getVTList(VT1, VT2); 4254 SDValue Ops[] = { Op1, Op2, Op3 }; 4255 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4256} 4257 4258/// MorphNodeTo - These *mutate* the specified node to have the specified 4259/// return type, opcode, and operands. 4260/// 4261/// Note that MorphNodeTo returns the resultant node. If there is already a 4262/// node of the specified opcode and operands, it returns that node instead of 4263/// the current one. Note that the DebugLoc need not be the same. 4264/// 4265/// Using MorphNodeTo is faster than creating a new node and swapping it in 4266/// with ReplaceAllUsesWith both because it often avoids allocating a new 4267/// node, and because it doesn't require CSE recalculation for any of 4268/// the node's users. 4269/// 4270SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4271 SDVTList VTs, const SDValue *Ops, 4272 unsigned NumOps) { 4273 // If an identical node already exists, use it. 4274 void *IP = 0; 4275 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4276 FoldingSetNodeID ID; 4277 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4278 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4279 return ON; 4280 } 4281 4282 if (!RemoveNodeFromCSEMaps(N)) 4283 IP = 0; 4284 4285 // Start the morphing. 4286 N->NodeType = Opc; 4287 N->ValueList = VTs.VTs; 4288 N->NumValues = VTs.NumVTs; 4289 4290 // Clear the operands list, updating used nodes to remove this from their 4291 // use list. Keep track of any operands that become dead as a result. 4292 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4293 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 4294 SDUse &Use = *I++; 4295 SDNode *Used = Use.getNode(); 4296 Use.set(SDValue()); 4297 if (Used->use_empty()) 4298 DeadNodeSet.insert(Used); 4299 } 4300 4301 // If NumOps is larger than the # of operands we currently have, reallocate 4302 // the operand list. 4303 if (NumOps > N->NumOperands) { 4304 if (N->OperandsNeedDelete) 4305 delete[] N->OperandList; 4306 4307 if (N->isMachineOpcode()) { 4308 // We're creating a final node that will live unmorphed for the 4309 // remainder of the current SelectionDAG iteration, so we can allocate 4310 // the operands directly out of a pool with no recycling metadata. 4311 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4312 N->OperandsNeedDelete = false; 4313 } else { 4314 N->OperandList = new SDUse[NumOps]; 4315 N->OperandsNeedDelete = true; 4316 } 4317 } 4318 4319 // Assign the new operands. 4320 N->NumOperands = NumOps; 4321 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4322 N->OperandList[i].setUser(N); 4323 N->OperandList[i].setInitial(Ops[i]); 4324 } 4325 4326 // Delete any nodes that are still dead after adding the uses for the 4327 // new operands. 4328 SmallVector<SDNode *, 16> DeadNodes; 4329 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4330 E = DeadNodeSet.end(); I != E; ++I) 4331 if ((*I)->use_empty()) 4332 DeadNodes.push_back(*I); 4333 RemoveDeadNodes(DeadNodes); 4334 4335 if (IP) 4336 CSEMap.InsertNode(N, IP); // Memoize the new node. 4337 return N; 4338} 4339 4340 4341/// getTargetNode - These are used for target selectors to create a new node 4342/// with specified return type(s), target opcode, and operands. 4343/// 4344/// Note that getTargetNode returns the resultant node. If there is already a 4345/// node of the specified opcode and operands, it returns that node instead of 4346/// the current one. 4347SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) { 4348 return getNode(~Opcode, dl, VT).getNode(); 4349} 4350 4351SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4352 SDValue Op1) { 4353 return getNode(~Opcode, dl, VT, Op1).getNode(); 4354} 4355 4356SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4357 SDValue Op1, SDValue Op2) { 4358 return getNode(~Opcode, dl, VT, Op1, Op2).getNode(); 4359} 4360 4361SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4362 SDValue Op1, SDValue Op2, 4363 SDValue Op3) { 4364 return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode(); 4365} 4366 4367SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4368 const SDValue *Ops, unsigned NumOps) { 4369 return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); 4370} 4371 4372SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4373 MVT VT1, MVT VT2) { 4374 SDVTList VTs = getVTList(VT1, VT2); 4375 SDValue Op; 4376 return getNode(~Opcode, dl, VTs, &Op, 0).getNode(); 4377} 4378 4379SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4380 MVT VT2, SDValue Op1) { 4381 SDVTList VTs = getVTList(VT1, VT2); 4382 return getNode(~Opcode, dl, VTs, &Op1, 1).getNode(); 4383} 4384 4385SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4386 MVT VT2, SDValue Op1, 4387 SDValue Op2) { 4388 SDVTList VTs = getVTList(VT1, VT2); 4389 SDValue Ops[] = { Op1, Op2 }; 4390 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4391} 4392 4393SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4394 MVT VT2, SDValue Op1, 4395 SDValue Op2, SDValue Op3) { 4396 SDVTList VTs = getVTList(VT1, VT2); 4397 SDValue Ops[] = { Op1, Op2, Op3 }; 4398 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4399} 4400 4401SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4402 MVT VT1, MVT VT2, 4403 const SDValue *Ops, unsigned NumOps) { 4404 SDVTList VTs = getVTList(VT1, VT2); 4405 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4406} 4407 4408SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4409 MVT VT1, MVT VT2, MVT VT3, 4410 SDValue Op1, SDValue Op2) { 4411 SDVTList VTs = getVTList(VT1, VT2, VT3); 4412 SDValue Ops[] = { Op1, Op2 }; 4413 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4414} 4415 4416SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4417 MVT VT1, MVT VT2, MVT VT3, 4418 SDValue Op1, SDValue Op2, 4419 SDValue Op3) { 4420 SDVTList VTs = getVTList(VT1, VT2, VT3); 4421 SDValue Ops[] = { Op1, Op2, Op3 }; 4422 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4423} 4424 4425SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4426 MVT VT1, MVT VT2, MVT VT3, 4427 const SDValue *Ops, unsigned NumOps) { 4428 SDVTList VTs = getVTList(VT1, VT2, VT3); 4429 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4430} 4431 4432SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4433 MVT VT2, MVT VT3, MVT VT4, 4434 const SDValue *Ops, unsigned NumOps) { 4435 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4436 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4437} 4438 4439SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4440 const std::vector<MVT> &ResultTys, 4441 const SDValue *Ops, unsigned NumOps) { 4442 return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode(); 4443} 4444 4445/// getNodeIfExists - Get the specified node if it's already available, or 4446/// else return NULL. 4447SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4448 const SDValue *Ops, unsigned NumOps) { 4449 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4450 FoldingSetNodeID ID; 4451 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4452 void *IP = 0; 4453 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4454 return E; 4455 } 4456 return NULL; 4457} 4458 4459/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4460/// This can cause recursive merging of nodes in the DAG. 4461/// 4462/// This version assumes From has a single result value. 4463/// 4464void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4465 DAGUpdateListener *UpdateListener) { 4466 SDNode *From = FromN.getNode(); 4467 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4468 "Cannot replace with this method!"); 4469 assert(From != To.getNode() && "Cannot replace uses of with self"); 4470 4471 // Iterate over all the existing uses of From. New uses will be added 4472 // to the beginning of the use list, which we avoid visiting. 4473 // This specifically avoids visiting uses of From that arise while the 4474 // replacement is happening, because any such uses would be the result 4475 // of CSE: If an existing node looks like From after one of its operands 4476 // is replaced by To, we don't want to replace of all its users with To 4477 // too. See PR3018 for more info. 4478 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4479 while (UI != UE) { 4480 SDNode *User = *UI; 4481 4482 // This node is about to morph, remove its old self from the CSE maps. 4483 RemoveNodeFromCSEMaps(User); 4484 4485 // A user can appear in a use list multiple times, and when this 4486 // happens the uses are usually next to each other in the list. 4487 // To help reduce the number of CSE recomputations, process all 4488 // the uses of this user that we can find this way. 4489 do { 4490 SDUse &Use = UI.getUse(); 4491 ++UI; 4492 Use.set(To); 4493 } while (UI != UE && *UI == User); 4494 4495 // Now that we have modified User, add it back to the CSE maps. If it 4496 // already exists there, recursively merge the results together. 4497 AddModifiedNodeToCSEMaps(User, UpdateListener); 4498 } 4499} 4500 4501/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4502/// This can cause recursive merging of nodes in the DAG. 4503/// 4504/// This version assumes that for each value of From, there is a 4505/// corresponding value in To in the same position with the same type. 4506/// 4507void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4508 DAGUpdateListener *UpdateListener) { 4509#ifndef NDEBUG 4510 for (unsigned i = 0, e = From->getNumValues(); i != e; ++i) 4511 assert((!From->hasAnyUseOfValue(i) || 4512 From->getValueType(i) == To->getValueType(i)) && 4513 "Cannot use this version of ReplaceAllUsesWith!"); 4514#endif 4515 4516 // Handle the trivial case. 4517 if (From == To) 4518 return; 4519 4520 // Iterate over just the existing users of From. See the comments in 4521 // the ReplaceAllUsesWith above. 4522 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4523 while (UI != UE) { 4524 SDNode *User = *UI; 4525 4526 // This node is about to morph, remove its old self from the CSE maps. 4527 RemoveNodeFromCSEMaps(User); 4528 4529 // A user can appear in a use list multiple times, and when this 4530 // happens the uses are usually next to each other in the list. 4531 // To help reduce the number of CSE recomputations, process all 4532 // the uses of this user that we can find this way. 4533 do { 4534 SDUse &Use = UI.getUse(); 4535 ++UI; 4536 Use.setNode(To); 4537 } while (UI != UE && *UI == User); 4538 4539 // Now that we have modified User, add it back to the CSE maps. If it 4540 // already exists there, recursively merge the results together. 4541 AddModifiedNodeToCSEMaps(User, UpdateListener); 4542 } 4543} 4544 4545/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4546/// This can cause recursive merging of nodes in the DAG. 4547/// 4548/// This version can replace From with any result values. To must match the 4549/// number and types of values returned by From. 4550void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4551 const SDValue *To, 4552 DAGUpdateListener *UpdateListener) { 4553 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4554 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4555 4556 // Iterate over just the existing users of From. See the comments in 4557 // the ReplaceAllUsesWith above. 4558 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4559 while (UI != UE) { 4560 SDNode *User = *UI; 4561 4562 // This node is about to morph, remove its old self from the CSE maps. 4563 RemoveNodeFromCSEMaps(User); 4564 4565 // A user can appear in a use list multiple times, and when this 4566 // happens the uses are usually next to each other in the list. 4567 // To help reduce the number of CSE recomputations, process all 4568 // the uses of this user that we can find this way. 4569 do { 4570 SDUse &Use = UI.getUse(); 4571 const SDValue &ToOp = To[Use.getResNo()]; 4572 ++UI; 4573 Use.set(ToOp); 4574 } while (UI != UE && *UI == User); 4575 4576 // Now that we have modified User, add it back to the CSE maps. If it 4577 // already exists there, recursively merge the results together. 4578 AddModifiedNodeToCSEMaps(User, UpdateListener); 4579 } 4580} 4581 4582/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4583/// uses of other values produced by From.getNode() alone. The Deleted 4584/// vector is handled the same way as for ReplaceAllUsesWith. 4585void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4586 DAGUpdateListener *UpdateListener){ 4587 // Handle the really simple, really trivial case efficiently. 4588 if (From == To) return; 4589 4590 // Handle the simple, trivial, case efficiently. 4591 if (From.getNode()->getNumValues() == 1) { 4592 ReplaceAllUsesWith(From, To, UpdateListener); 4593 return; 4594 } 4595 4596 // Iterate over just the existing users of From. See the comments in 4597 // the ReplaceAllUsesWith above. 4598 SDNode::use_iterator UI = From.getNode()->use_begin(), 4599 UE = From.getNode()->use_end(); 4600 while (UI != UE) { 4601 SDNode *User = *UI; 4602 bool UserRemovedFromCSEMaps = false; 4603 4604 // A user can appear in a use list multiple times, and when this 4605 // happens the uses are usually next to each other in the list. 4606 // To help reduce the number of CSE recomputations, process all 4607 // the uses of this user that we can find this way. 4608 do { 4609 SDUse &Use = UI.getUse(); 4610 4611 // Skip uses of different values from the same node. 4612 if (Use.getResNo() != From.getResNo()) { 4613 ++UI; 4614 continue; 4615 } 4616 4617 // If this node hasn't been modified yet, it's still in the CSE maps, 4618 // so remove its old self from the CSE maps. 4619 if (!UserRemovedFromCSEMaps) { 4620 RemoveNodeFromCSEMaps(User); 4621 UserRemovedFromCSEMaps = true; 4622 } 4623 4624 ++UI; 4625 Use.set(To); 4626 } while (UI != UE && *UI == User); 4627 4628 // We are iterating over all uses of the From node, so if a use 4629 // doesn't use the specific value, no changes are made. 4630 if (!UserRemovedFromCSEMaps) 4631 continue; 4632 4633 // Now that we have modified User, add it back to the CSE maps. If it 4634 // already exists there, recursively merge the results together. 4635 AddModifiedNodeToCSEMaps(User, UpdateListener); 4636 } 4637} 4638 4639namespace { 4640 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith 4641 /// to record information about a use. 4642 struct UseMemo { 4643 SDNode *User; 4644 unsigned Index; 4645 SDUse *Use; 4646 }; 4647 4648 /// operator< - Sort Memos by User. 4649 bool operator<(const UseMemo &L, const UseMemo &R) { 4650 return (intptr_t)L.User < (intptr_t)R.User; 4651 } 4652} 4653 4654/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4655/// uses of other values produced by From.getNode() alone. The same value 4656/// may appear in both the From and To list. The Deleted vector is 4657/// handled the same way as for ReplaceAllUsesWith. 4658void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4659 const SDValue *To, 4660 unsigned Num, 4661 DAGUpdateListener *UpdateListener){ 4662 // Handle the simple, trivial case efficiently. 4663 if (Num == 1) 4664 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4665 4666 // Read up all the uses and make records of them. This helps 4667 // processing new uses that are introduced during the 4668 // replacement process. 4669 SmallVector<UseMemo, 4> Uses; 4670 for (unsigned i = 0; i != Num; ++i) { 4671 unsigned FromResNo = From[i].getResNo(); 4672 SDNode *FromNode = From[i].getNode(); 4673 for (SDNode::use_iterator UI = FromNode->use_begin(), 4674 E = FromNode->use_end(); UI != E; ++UI) { 4675 SDUse &Use = UI.getUse(); 4676 if (Use.getResNo() == FromResNo) { 4677 UseMemo Memo = { *UI, i, &Use }; 4678 Uses.push_back(Memo); 4679 } 4680 } 4681 } 4682 4683 // Sort the uses, so that all the uses from a given User are together. 4684 std::sort(Uses.begin(), Uses.end()); 4685 4686 for (unsigned UseIndex = 0, UseIndexEnd = Uses.size(); 4687 UseIndex != UseIndexEnd; ) { 4688 // We know that this user uses some value of From. If it is the right 4689 // value, update it. 4690 SDNode *User = Uses[UseIndex].User; 4691 4692 // This node is about to morph, remove its old self from the CSE maps. 4693 RemoveNodeFromCSEMaps(User); 4694 4695 // The Uses array is sorted, so all the uses for a given User 4696 // are next to each other in the list. 4697 // To help reduce the number of CSE recomputations, process all 4698 // the uses of this user that we can find this way. 4699 do { 4700 unsigned i = Uses[UseIndex].Index; 4701 SDUse &Use = *Uses[UseIndex].Use; 4702 ++UseIndex; 4703 4704 Use.set(To[i]); 4705 } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User); 4706 4707 // Now that we have modified User, add it back to the CSE maps. If it 4708 // already exists there, recursively merge the results together. 4709 AddModifiedNodeToCSEMaps(User, UpdateListener); 4710 } 4711} 4712 4713/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4714/// based on their topological order. It returns the maximum id and a vector 4715/// of the SDNodes* in assigned order by reference. 4716unsigned SelectionDAG::AssignTopologicalOrder() { 4717 4718 unsigned DAGSize = 0; 4719 4720 // SortedPos tracks the progress of the algorithm. Nodes before it are 4721 // sorted, nodes after it are unsorted. When the algorithm completes 4722 // it is at the end of the list. 4723 allnodes_iterator SortedPos = allnodes_begin(); 4724 4725 // Visit all the nodes. Move nodes with no operands to the front of 4726 // the list immediately. Annotate nodes that do have operands with their 4727 // operand count. Before we do this, the Node Id fields of the nodes 4728 // may contain arbitrary values. After, the Node Id fields for nodes 4729 // before SortedPos will contain the topological sort index, and the 4730 // Node Id fields for nodes At SortedPos and after will contain the 4731 // count of outstanding operands. 4732 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4733 SDNode *N = I++; 4734 unsigned Degree = N->getNumOperands(); 4735 if (Degree == 0) { 4736 // A node with no uses, add it to the result array immediately. 4737 N->setNodeId(DAGSize++); 4738 allnodes_iterator Q = N; 4739 if (Q != SortedPos) 4740 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4741 ++SortedPos; 4742 } else { 4743 // Temporarily use the Node Id as scratch space for the degree count. 4744 N->setNodeId(Degree); 4745 } 4746 } 4747 4748 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4749 // such that by the time the end is reached all nodes will be sorted. 4750 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4751 SDNode *N = I; 4752 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4753 UI != UE; ++UI) { 4754 SDNode *P = *UI; 4755 unsigned Degree = P->getNodeId(); 4756 --Degree; 4757 if (Degree == 0) { 4758 // All of P's operands are sorted, so P may sorted now. 4759 P->setNodeId(DAGSize++); 4760 if (P != SortedPos) 4761 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4762 ++SortedPos; 4763 } else { 4764 // Update P's outstanding operand count. 4765 P->setNodeId(Degree); 4766 } 4767 } 4768 } 4769 4770 assert(SortedPos == AllNodes.end() && 4771 "Topological sort incomplete!"); 4772 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4773 "First node in topological sort is not the entry token!"); 4774 assert(AllNodes.front().getNodeId() == 0 && 4775 "First node in topological sort has non-zero id!"); 4776 assert(AllNodes.front().getNumOperands() == 0 && 4777 "First node in topological sort has operands!"); 4778 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4779 "Last node in topologic sort has unexpected id!"); 4780 assert(AllNodes.back().use_empty() && 4781 "Last node in topologic sort has users!"); 4782 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 4783 return DAGSize; 4784} 4785 4786 4787 4788//===----------------------------------------------------------------------===// 4789// SDNode Class 4790//===----------------------------------------------------------------------===// 4791 4792HandleSDNode::~HandleSDNode() { 4793 DropOperands(); 4794} 4795 4796GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4797 MVT VT, int64_t o) 4798 : SDNode(isa<GlobalVariable>(GA) && 4799 cast<GlobalVariable>(GA)->isThreadLocal() ? 4800 // Thread Local 4801 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4802 // Non Thread Local 4803 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4804 DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o) { 4805 TheGlobal = const_cast<GlobalValue*>(GA); 4806} 4807 4808MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt, 4809 const Value *srcValue, int SVO, 4810 unsigned alignment, bool vol) 4811 : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4812 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4813 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4814 assert(getAlignment() == alignment && "Alignment representation error!"); 4815 assert(isVolatile() == vol && "Volatile representation error!"); 4816} 4817 4818MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, 4819 const SDValue *Ops, 4820 unsigned NumOps, MVT memvt, const Value *srcValue, 4821 int SVO, unsigned alignment, bool vol) 4822 : SDNode(Opc, dl, VTs, Ops, NumOps), 4823 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4824 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4825 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4826 assert(getAlignment() == alignment && "Alignment representation error!"); 4827 assert(isVolatile() == vol && "Volatile representation error!"); 4828} 4829 4830/// getMemOperand - Return a MachineMemOperand object describing the memory 4831/// reference performed by this memory reference. 4832MachineMemOperand MemSDNode::getMemOperand() const { 4833 int Flags = 0; 4834 if (isa<LoadSDNode>(this)) 4835 Flags = MachineMemOperand::MOLoad; 4836 else if (isa<StoreSDNode>(this)) 4837 Flags = MachineMemOperand::MOStore; 4838 else if (isa<AtomicSDNode>(this)) { 4839 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4840 } 4841 else { 4842 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4843 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4844 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4845 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4846 } 4847 4848 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4849 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4850 4851 // Check if the memory reference references a frame index 4852 const FrameIndexSDNode *FI = 4853 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4854 if (!getSrcValue() && FI) 4855 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4856 Flags, 0, Size, getAlignment()); 4857 else 4858 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4859 Size, getAlignment()); 4860} 4861 4862/// Profile - Gather unique data for the node. 4863/// 4864void SDNode::Profile(FoldingSetNodeID &ID) const { 4865 AddNodeIDNode(ID, this); 4866} 4867 4868/// getValueTypeList - Return a pointer to the specified value type. 4869/// 4870const MVT *SDNode::getValueTypeList(MVT VT) { 4871 if (VT.isExtended()) { 4872 static std::set<MVT, MVT::compareRawBits> EVTs; 4873 return &(*EVTs.insert(VT).first); 4874 } else { 4875 static MVT VTs[MVT::LAST_VALUETYPE]; 4876 VTs[VT.getSimpleVT()] = VT; 4877 return &VTs[VT.getSimpleVT()]; 4878 } 4879} 4880 4881/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4882/// indicated value. This method ignores uses of other values defined by this 4883/// operation. 4884bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4885 assert(Value < getNumValues() && "Bad value!"); 4886 4887 // TODO: Only iterate over uses of a given value of the node 4888 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4889 if (UI.getUse().getResNo() == Value) { 4890 if (NUses == 0) 4891 return false; 4892 --NUses; 4893 } 4894 } 4895 4896 // Found exactly the right number of uses? 4897 return NUses == 0; 4898} 4899 4900 4901/// hasAnyUseOfValue - Return true if there are any use of the indicated 4902/// value. This method ignores uses of other values defined by this operation. 4903bool SDNode::hasAnyUseOfValue(unsigned Value) const { 4904 assert(Value < getNumValues() && "Bad value!"); 4905 4906 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 4907 if (UI.getUse().getResNo() == Value) 4908 return true; 4909 4910 return false; 4911} 4912 4913 4914/// isOnlyUserOf - Return true if this node is the only use of N. 4915/// 4916bool SDNode::isOnlyUserOf(SDNode *N) const { 4917 bool Seen = false; 4918 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 4919 SDNode *User = *I; 4920 if (User == this) 4921 Seen = true; 4922 else 4923 return false; 4924 } 4925 4926 return Seen; 4927} 4928 4929/// isOperand - Return true if this node is an operand of N. 4930/// 4931bool SDValue::isOperandOf(SDNode *N) const { 4932 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4933 if (*this == N->getOperand(i)) 4934 return true; 4935 return false; 4936} 4937 4938bool SDNode::isOperandOf(SDNode *N) const { 4939 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 4940 if (this == N->OperandList[i].getNode()) 4941 return true; 4942 return false; 4943} 4944 4945/// reachesChainWithoutSideEffects - Return true if this operand (which must 4946/// be a chain) reaches the specified operand without crossing any 4947/// side-effecting instructions. In practice, this looks through token 4948/// factors and non-volatile loads. In order to remain efficient, this only 4949/// looks a couple of nodes in, it does not do an exhaustive search. 4950bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 4951 unsigned Depth) const { 4952 if (*this == Dest) return true; 4953 4954 // Don't search too deeply, we just want to be able to see through 4955 // TokenFactor's etc. 4956 if (Depth == 0) return false; 4957 4958 // If this is a token factor, all inputs to the TF happen in parallel. If any 4959 // of the operands of the TF reach dest, then we can do the xform. 4960 if (getOpcode() == ISD::TokenFactor) { 4961 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 4962 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 4963 return true; 4964 return false; 4965 } 4966 4967 // Loads don't have side effects, look through them. 4968 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 4969 if (!Ld->isVolatile()) 4970 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 4971 } 4972 return false; 4973} 4974 4975 4976static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 4977 SmallPtrSet<SDNode *, 32> &Visited) { 4978 if (found || !Visited.insert(N)) 4979 return; 4980 4981 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 4982 SDNode *Op = N->getOperand(i).getNode(); 4983 if (Op == P) { 4984 found = true; 4985 return; 4986 } 4987 findPredecessor(Op, P, found, Visited); 4988 } 4989} 4990 4991/// isPredecessorOf - Return true if this node is a predecessor of N. This node 4992/// is either an operand of N or it can be reached by recursively traversing 4993/// up the operands. 4994/// NOTE: this is an expensive method. Use it carefully. 4995bool SDNode::isPredecessorOf(SDNode *N) const { 4996 SmallPtrSet<SDNode *, 32> Visited; 4997 bool found = false; 4998 findPredecessor(N, this, found, Visited); 4999 return found; 5000} 5001 5002uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 5003 assert(Num < NumOperands && "Invalid child # of SDNode!"); 5004 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 5005} 5006 5007std::string SDNode::getOperationName(const SelectionDAG *G) const { 5008 switch (getOpcode()) { 5009 default: 5010 if (getOpcode() < ISD::BUILTIN_OP_END) 5011 return "<<Unknown DAG Node>>"; 5012 if (isMachineOpcode()) { 5013 if (G) 5014 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 5015 if (getMachineOpcode() < TII->getNumOpcodes()) 5016 return TII->get(getMachineOpcode()).getName(); 5017 return "<<Unknown Machine Node>>"; 5018 } 5019 if (G) { 5020 const TargetLowering &TLI = G->getTargetLoweringInfo(); 5021 const char *Name = TLI.getTargetNodeName(getOpcode()); 5022 if (Name) return Name; 5023 return "<<Unknown Target Node>>"; 5024 } 5025 return "<<Unknown Node>>"; 5026 5027#ifndef NDEBUG 5028 case ISD::DELETED_NODE: 5029 return "<<Deleted Node!>>"; 5030#endif 5031 case ISD::PREFETCH: return "Prefetch"; 5032 case ISD::MEMBARRIER: return "MemBarrier"; 5033 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 5034 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 5035 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 5036 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 5037 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; 5038 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; 5039 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor"; 5040 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand"; 5041 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin"; 5042 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; 5043 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; 5044 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; 5045 case ISD::PCMARKER: return "PCMarker"; 5046 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5047 case ISD::SRCVALUE: return "SrcValue"; 5048 case ISD::MEMOPERAND: return "MemOperand"; 5049 case ISD::EntryToken: return "EntryToken"; 5050 case ISD::TokenFactor: return "TokenFactor"; 5051 case ISD::AssertSext: return "AssertSext"; 5052 case ISD::AssertZext: return "AssertZext"; 5053 5054 case ISD::BasicBlock: return "BasicBlock"; 5055 case ISD::ARG_FLAGS: return "ArgFlags"; 5056 case ISD::VALUETYPE: return "ValueType"; 5057 case ISD::Register: return "Register"; 5058 5059 case ISD::Constant: return "Constant"; 5060 case ISD::ConstantFP: return "ConstantFP"; 5061 case ISD::GlobalAddress: return "GlobalAddress"; 5062 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5063 case ISD::FrameIndex: return "FrameIndex"; 5064 case ISD::JumpTable: return "JumpTable"; 5065 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5066 case ISD::RETURNADDR: return "RETURNADDR"; 5067 case ISD::FRAMEADDR: return "FRAMEADDR"; 5068 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5069 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5070 case ISD::EHSELECTION: return "EHSELECTION"; 5071 case ISD::EH_RETURN: return "EH_RETURN"; 5072 case ISD::ConstantPool: return "ConstantPool"; 5073 case ISD::ExternalSymbol: return "ExternalSymbol"; 5074 case ISD::INTRINSIC_WO_CHAIN: { 5075 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5076 return Intrinsic::getName((Intrinsic::ID)IID); 5077 } 5078 case ISD::INTRINSIC_VOID: 5079 case ISD::INTRINSIC_W_CHAIN: { 5080 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5081 return Intrinsic::getName((Intrinsic::ID)IID); 5082 } 5083 5084 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5085 case ISD::TargetConstant: return "TargetConstant"; 5086 case ISD::TargetConstantFP:return "TargetConstantFP"; 5087 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5088 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5089 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5090 case ISD::TargetJumpTable: return "TargetJumpTable"; 5091 case ISD::TargetConstantPool: return "TargetConstantPool"; 5092 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5093 5094 case ISD::CopyToReg: return "CopyToReg"; 5095 case ISD::CopyFromReg: return "CopyFromReg"; 5096 case ISD::UNDEF: return "undef"; 5097 case ISD::MERGE_VALUES: return "merge_values"; 5098 case ISD::INLINEASM: return "inlineasm"; 5099 case ISD::DBG_LABEL: return "dbg_label"; 5100 case ISD::EH_LABEL: return "eh_label"; 5101 case ISD::DECLARE: return "declare"; 5102 case ISD::HANDLENODE: return "handlenode"; 5103 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5104 case ISD::CALL: return "call"; 5105 5106 // Unary operators 5107 case ISD::FABS: return "fabs"; 5108 case ISD::FNEG: return "fneg"; 5109 case ISD::FSQRT: return "fsqrt"; 5110 case ISD::FSIN: return "fsin"; 5111 case ISD::FCOS: return "fcos"; 5112 case ISD::FPOWI: return "fpowi"; 5113 case ISD::FPOW: return "fpow"; 5114 case ISD::FTRUNC: return "ftrunc"; 5115 case ISD::FFLOOR: return "ffloor"; 5116 case ISD::FCEIL: return "fceil"; 5117 case ISD::FRINT: return "frint"; 5118 case ISD::FNEARBYINT: return "fnearbyint"; 5119 5120 // Binary operators 5121 case ISD::ADD: return "add"; 5122 case ISD::SUB: return "sub"; 5123 case ISD::MUL: return "mul"; 5124 case ISD::MULHU: return "mulhu"; 5125 case ISD::MULHS: return "mulhs"; 5126 case ISD::SDIV: return "sdiv"; 5127 case ISD::UDIV: return "udiv"; 5128 case ISD::SREM: return "srem"; 5129 case ISD::UREM: return "urem"; 5130 case ISD::SMUL_LOHI: return "smul_lohi"; 5131 case ISD::UMUL_LOHI: return "umul_lohi"; 5132 case ISD::SDIVREM: return "sdivrem"; 5133 case ISD::UDIVREM: return "udivrem"; 5134 case ISD::AND: return "and"; 5135 case ISD::OR: return "or"; 5136 case ISD::XOR: return "xor"; 5137 case ISD::SHL: return "shl"; 5138 case ISD::SRA: return "sra"; 5139 case ISD::SRL: return "srl"; 5140 case ISD::ROTL: return "rotl"; 5141 case ISD::ROTR: return "rotr"; 5142 case ISD::FADD: return "fadd"; 5143 case ISD::FSUB: return "fsub"; 5144 case ISD::FMUL: return "fmul"; 5145 case ISD::FDIV: return "fdiv"; 5146 case ISD::FREM: return "frem"; 5147 case ISD::FCOPYSIGN: return "fcopysign"; 5148 case ISD::FGETSIGN: return "fgetsign"; 5149 5150 case ISD::SETCC: return "setcc"; 5151 case ISD::VSETCC: return "vsetcc"; 5152 case ISD::SELECT: return "select"; 5153 case ISD::SELECT_CC: return "select_cc"; 5154 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5155 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5156 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5157 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5158 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5159 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5160 case ISD::CARRY_FALSE: return "carry_false"; 5161 case ISD::ADDC: return "addc"; 5162 case ISD::ADDE: return "adde"; 5163 case ISD::SADDO: return "saddo"; 5164 case ISD::UADDO: return "uaddo"; 5165 case ISD::SSUBO: return "ssubo"; 5166 case ISD::USUBO: return "usubo"; 5167 case ISD::SMULO: return "smulo"; 5168 case ISD::UMULO: return "umulo"; 5169 case ISD::SUBC: return "subc"; 5170 case ISD::SUBE: return "sube"; 5171 case ISD::SHL_PARTS: return "shl_parts"; 5172 case ISD::SRA_PARTS: return "sra_parts"; 5173 case ISD::SRL_PARTS: return "srl_parts"; 5174 5175 // Conversion operators. 5176 case ISD::SIGN_EXTEND: return "sign_extend"; 5177 case ISD::ZERO_EXTEND: return "zero_extend"; 5178 case ISD::ANY_EXTEND: return "any_extend"; 5179 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5180 case ISD::TRUNCATE: return "truncate"; 5181 case ISD::FP_ROUND: return "fp_round"; 5182 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5183 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5184 case ISD::FP_EXTEND: return "fp_extend"; 5185 5186 case ISD::SINT_TO_FP: return "sint_to_fp"; 5187 case ISD::UINT_TO_FP: return "uint_to_fp"; 5188 case ISD::FP_TO_SINT: return "fp_to_sint"; 5189 case ISD::FP_TO_UINT: return "fp_to_uint"; 5190 case ISD::BIT_CONVERT: return "bit_convert"; 5191 5192 case ISD::CONVERT_RNDSAT: { 5193 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5194 default: assert(0 && "Unknown cvt code!"); 5195 case ISD::CVT_FF: return "cvt_ff"; 5196 case ISD::CVT_FS: return "cvt_fs"; 5197 case ISD::CVT_FU: return "cvt_fu"; 5198 case ISD::CVT_SF: return "cvt_sf"; 5199 case ISD::CVT_UF: return "cvt_uf"; 5200 case ISD::CVT_SS: return "cvt_ss"; 5201 case ISD::CVT_SU: return "cvt_su"; 5202 case ISD::CVT_US: return "cvt_us"; 5203 case ISD::CVT_UU: return "cvt_uu"; 5204 } 5205 } 5206 5207 // Control flow instructions 5208 case ISD::BR: return "br"; 5209 case ISD::BRIND: return "brind"; 5210 case ISD::BR_JT: return "br_jt"; 5211 case ISD::BRCOND: return "brcond"; 5212 case ISD::BR_CC: return "br_cc"; 5213 case ISD::RET: return "ret"; 5214 case ISD::CALLSEQ_START: return "callseq_start"; 5215 case ISD::CALLSEQ_END: return "callseq_end"; 5216 5217 // Other operators 5218 case ISD::LOAD: return "load"; 5219 case ISD::STORE: return "store"; 5220 case ISD::VAARG: return "vaarg"; 5221 case ISD::VACOPY: return "vacopy"; 5222 case ISD::VAEND: return "vaend"; 5223 case ISD::VASTART: return "vastart"; 5224 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5225 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5226 case ISD::BUILD_PAIR: return "build_pair"; 5227 case ISD::STACKSAVE: return "stacksave"; 5228 case ISD::STACKRESTORE: return "stackrestore"; 5229 case ISD::TRAP: return "trap"; 5230 5231 // Bit manipulation 5232 case ISD::BSWAP: return "bswap"; 5233 case ISD::CTPOP: return "ctpop"; 5234 case ISD::CTTZ: return "cttz"; 5235 case ISD::CTLZ: return "ctlz"; 5236 5237 // Debug info 5238 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5239 case ISD::DEBUG_LOC: return "debug_loc"; 5240 5241 // Trampolines 5242 case ISD::TRAMPOLINE: return "trampoline"; 5243 5244 case ISD::CONDCODE: 5245 switch (cast<CondCodeSDNode>(this)->get()) { 5246 default: assert(0 && "Unknown setcc condition!"); 5247 case ISD::SETOEQ: return "setoeq"; 5248 case ISD::SETOGT: return "setogt"; 5249 case ISD::SETOGE: return "setoge"; 5250 case ISD::SETOLT: return "setolt"; 5251 case ISD::SETOLE: return "setole"; 5252 case ISD::SETONE: return "setone"; 5253 5254 case ISD::SETO: return "seto"; 5255 case ISD::SETUO: return "setuo"; 5256 case ISD::SETUEQ: return "setue"; 5257 case ISD::SETUGT: return "setugt"; 5258 case ISD::SETUGE: return "setuge"; 5259 case ISD::SETULT: return "setult"; 5260 case ISD::SETULE: return "setule"; 5261 case ISD::SETUNE: return "setune"; 5262 5263 case ISD::SETEQ: return "seteq"; 5264 case ISD::SETGT: return "setgt"; 5265 case ISD::SETGE: return "setge"; 5266 case ISD::SETLT: return "setlt"; 5267 case ISD::SETLE: return "setle"; 5268 case ISD::SETNE: return "setne"; 5269 } 5270 } 5271} 5272 5273const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5274 switch (AM) { 5275 default: 5276 return ""; 5277 case ISD::PRE_INC: 5278 return "<pre-inc>"; 5279 case ISD::PRE_DEC: 5280 return "<pre-dec>"; 5281 case ISD::POST_INC: 5282 return "<post-inc>"; 5283 case ISD::POST_DEC: 5284 return "<post-dec>"; 5285 } 5286} 5287 5288std::string ISD::ArgFlagsTy::getArgFlagsString() { 5289 std::string S = "< "; 5290 5291 if (isZExt()) 5292 S += "zext "; 5293 if (isSExt()) 5294 S += "sext "; 5295 if (isInReg()) 5296 S += "inreg "; 5297 if (isSRet()) 5298 S += "sret "; 5299 if (isByVal()) 5300 S += "byval "; 5301 if (isNest()) 5302 S += "nest "; 5303 if (getByValAlign()) 5304 S += "byval-align:" + utostr(getByValAlign()) + " "; 5305 if (getOrigAlign()) 5306 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5307 if (getByValSize()) 5308 S += "byval-size:" + utostr(getByValSize()) + " "; 5309 return S + ">"; 5310} 5311 5312void SDNode::dump() const { dump(0); } 5313void SDNode::dump(const SelectionDAG *G) const { 5314 print(errs(), G); 5315} 5316 5317void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const { 5318 OS << (void*)this << ": "; 5319 5320 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5321 if (i) OS << ","; 5322 if (getValueType(i) == MVT::Other) 5323 OS << "ch"; 5324 else 5325 OS << getValueType(i).getMVTString(); 5326 } 5327 OS << " = " << getOperationName(G); 5328} 5329 5330void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { 5331 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5332 SDNode *Mask = getOperand(2).getNode(); 5333 OS << "<"; 5334 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 5335 if (i) OS << ","; 5336 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 5337 OS << "u"; 5338 else 5339 OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue(); 5340 } 5341 OS << ">"; 5342 } 5343 5344 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5345 OS << '<' << CSDN->getAPIntValue() << '>'; 5346 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5347 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5348 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5349 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5350 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5351 else { 5352 OS << "<APFloat("; 5353 CSDN->getValueAPF().bitcastToAPInt().dump(); 5354 OS << ")>"; 5355 } 5356 } else if (const GlobalAddressSDNode *GADN = 5357 dyn_cast<GlobalAddressSDNode>(this)) { 5358 int64_t offset = GADN->getOffset(); 5359 OS << '<'; 5360 WriteAsOperand(OS, GADN->getGlobal()); 5361 OS << '>'; 5362 if (offset > 0) 5363 OS << " + " << offset; 5364 else 5365 OS << " " << offset; 5366 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5367 OS << "<" << FIDN->getIndex() << ">"; 5368 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5369 OS << "<" << JTDN->getIndex() << ">"; 5370 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5371 int offset = CP->getOffset(); 5372 if (CP->isMachineConstantPoolEntry()) 5373 OS << "<" << *CP->getMachineCPVal() << ">"; 5374 else 5375 OS << "<" << *CP->getConstVal() << ">"; 5376 if (offset > 0) 5377 OS << " + " << offset; 5378 else 5379 OS << " " << offset; 5380 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5381 OS << "<"; 5382 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5383 if (LBB) 5384 OS << LBB->getName() << " "; 5385 OS << (const void*)BBDN->getBasicBlock() << ">"; 5386 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5387 if (G && R->getReg() && 5388 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5389 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5390 } else { 5391 OS << " #" << R->getReg(); 5392 } 5393 } else if (const ExternalSymbolSDNode *ES = 5394 dyn_cast<ExternalSymbolSDNode>(this)) { 5395 OS << "'" << ES->getSymbol() << "'"; 5396 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5397 if (M->getValue()) 5398 OS << "<" << M->getValue() << ">"; 5399 else 5400 OS << "<null>"; 5401 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5402 if (M->MO.getValue()) 5403 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5404 else 5405 OS << "<null:" << M->MO.getOffset() << ">"; 5406 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5407 OS << N->getArgFlags().getArgFlagsString(); 5408 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5409 OS << ":" << N->getVT().getMVTString(); 5410 } 5411 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5412 const Value *SrcValue = LD->getSrcValue(); 5413 int SrcOffset = LD->getSrcValueOffset(); 5414 OS << " <"; 5415 if (SrcValue) 5416 OS << SrcValue; 5417 else 5418 OS << "null"; 5419 OS << ":" << SrcOffset << ">"; 5420 5421 bool doExt = true; 5422 switch (LD->getExtensionType()) { 5423 default: doExt = false; break; 5424 case ISD::EXTLOAD: OS << " <anyext "; break; 5425 case ISD::SEXTLOAD: OS << " <sext "; break; 5426 case ISD::ZEXTLOAD: OS << " <zext "; break; 5427 } 5428 if (doExt) 5429 OS << LD->getMemoryVT().getMVTString() << ">"; 5430 5431 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5432 if (*AM) 5433 OS << " " << AM; 5434 if (LD->isVolatile()) 5435 OS << " <volatile>"; 5436 OS << " alignment=" << LD->getAlignment(); 5437 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5438 const Value *SrcValue = ST->getSrcValue(); 5439 int SrcOffset = ST->getSrcValueOffset(); 5440 OS << " <"; 5441 if (SrcValue) 5442 OS << SrcValue; 5443 else 5444 OS << "null"; 5445 OS << ":" << SrcOffset << ">"; 5446 5447 if (ST->isTruncatingStore()) 5448 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5449 5450 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5451 if (*AM) 5452 OS << " " << AM; 5453 if (ST->isVolatile()) 5454 OS << " <volatile>"; 5455 OS << " alignment=" << ST->getAlignment(); 5456 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5457 const Value *SrcValue = AT->getSrcValue(); 5458 int SrcOffset = AT->getSrcValueOffset(); 5459 OS << " <"; 5460 if (SrcValue) 5461 OS << SrcValue; 5462 else 5463 OS << "null"; 5464 OS << ":" << SrcOffset << ">"; 5465 if (AT->isVolatile()) 5466 OS << " <volatile>"; 5467 OS << " alignment=" << AT->getAlignment(); 5468 } 5469} 5470 5471void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5472 print_types(OS, G); 5473 OS << " "; 5474 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5475 if (i) OS << ", "; 5476 OS << (void*)getOperand(i).getNode(); 5477 if (unsigned RN = getOperand(i).getResNo()) 5478 OS << ":" << RN; 5479 } 5480 print_details(OS, G); 5481} 5482 5483static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5484 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5485 if (N->getOperand(i).getNode()->hasOneUse()) 5486 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5487 else 5488 cerr << "\n" << std::string(indent+2, ' ') 5489 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5490 5491 5492 cerr << "\n" << std::string(indent, ' '); 5493 N->dump(G); 5494} 5495 5496void SelectionDAG::dump() const { 5497 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5498 5499 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5500 I != E; ++I) { 5501 const SDNode *N = I; 5502 if (!N->hasOneUse() && N != getRoot().getNode()) 5503 DumpNodes(N, 2, this); 5504 } 5505 5506 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5507 5508 cerr << "\n\n"; 5509} 5510 5511void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const { 5512 print_types(OS, G); 5513 print_details(OS, G); 5514} 5515 5516typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet; 5517static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, 5518 const SelectionDAG *G, VisitedSDNodeSet &once) { 5519 if (!once.insert(N)) // If we've been here before, return now. 5520 return; 5521 // Dump the current SDNode, but don't end the line yet. 5522 OS << std::string(indent, ' '); 5523 N->printr(OS, G); 5524 // Having printed this SDNode, walk the children: 5525 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5526 const SDNode *child = N->getOperand(i).getNode(); 5527 if (i) OS << ","; 5528 OS << " "; 5529 if (child->getNumOperands() == 0) { 5530 // This child has no grandchildren; print it inline right here. 5531 child->printr(OS, G); 5532 once.insert(child); 5533 } else { // Just the address. FIXME: also print the child's opcode 5534 OS << (void*)child; 5535 if (unsigned RN = N->getOperand(i).getResNo()) 5536 OS << ":" << RN; 5537 } 5538 } 5539 OS << "\n"; 5540 // Dump children that have grandchildren on their own line(s). 5541 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5542 const SDNode *child = N->getOperand(i).getNode(); 5543 DumpNodesr(OS, child, indent+2, G, once); 5544 } 5545} 5546 5547void SDNode::dumpr() const { 5548 VisitedSDNodeSet once; 5549 DumpNodesr(errs(), this, 0, 0, once); 5550} 5551 5552const Type *ConstantPoolSDNode::getType() const { 5553 if (isMachineConstantPoolEntry()) 5554 return Val.MachineCPVal->getType(); 5555 return Val.ConstVal->getType(); 5556} 5557 5558bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue, 5559 APInt &SplatUndef, 5560 unsigned &SplatBitSize, 5561 bool &HasAnyUndefs, 5562 unsigned MinSplatBits) { 5563 MVT VT = getValueType(0); 5564 assert(VT.isVector() && "Expected a vector type"); 5565 unsigned sz = VT.getSizeInBits(); 5566 if (MinSplatBits > sz) 5567 return false; 5568 5569 SplatValue = APInt(sz, 0); 5570 SplatUndef = APInt(sz, 0); 5571 5572 // Get the bits. Bits with undefined values (when the corresponding element 5573 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared 5574 // in SplatValue. If any of the values are not constant, give up and return 5575 // false. 5576 unsigned int nOps = getNumOperands(); 5577 assert(nOps > 0 && "isConstantSplat has 0-size build vector"); 5578 unsigned EltBitSize = VT.getVectorElementType().getSizeInBits(); 5579 for (unsigned i = 0; i < nOps; ++i) { 5580 SDValue OpVal = getOperand(i); 5581 unsigned BitPos = i * EltBitSize; 5582 5583 if (OpVal.getOpcode() == ISD::UNDEF) 5584 SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos +EltBitSize); 5585 else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) 5586 SplatValue |= (APInt(CN->getAPIntValue()).zextOrTrunc(EltBitSize). 5587 zextOrTrunc(sz) << BitPos); 5588 else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) 5589 SplatValue |= CN->getValueAPF().bitcastToAPInt().zextOrTrunc(sz) <<BitPos; 5590 else 5591 return false; 5592 } 5593 5594 // The build_vector is all constants or undefs. Find the smallest element 5595 // size that splats the vector. 5596 5597 HasAnyUndefs = (SplatUndef != 0); 5598 while (sz > 8) { 5599 5600 unsigned HalfSize = sz / 2; 5601 APInt HighValue = APInt(SplatValue).lshr(HalfSize).trunc(HalfSize); 5602 APInt LowValue = APInt(SplatValue).trunc(HalfSize); 5603 APInt HighUndef = APInt(SplatUndef).lshr(HalfSize).trunc(HalfSize); 5604 APInt LowUndef = APInt(SplatUndef).trunc(HalfSize); 5605 5606 // If the two halves do not match (ignoring undef bits), stop here. 5607 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) || 5608 MinSplatBits > HalfSize) 5609 break; 5610 5611 SplatValue = HighValue | LowValue; 5612 SplatUndef = HighUndef & LowUndef; 5613 5614 sz = HalfSize; 5615 } 5616 5617 SplatBitSize = sz; 5618 return true; 5619} 5620