SelectionDAG.cpp revision fa252e56029c5a375f9c1f5d281f14eebb6e39be
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetInstrInfo.h" 31#include "llvm/Target/TargetMachine.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/ADT/SetVector.h" 36#include "llvm/ADT/SmallPtrSet.h" 37#include "llvm/ADT/SmallSet.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/ADT/StringExtras.h" 40#include <algorithm> 41#include <cmath> 42using namespace llvm; 43 44/// makeVTList - Return an instance of the SDVTList struct initialized with the 45/// specified members. 46static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 47 SDVTList Res = {VTs, NumVTs}; 48 return Res; 49} 50 51static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 52 switch (VT.getSimpleVT()) { 53 default: assert(0 && "Unknown FP format"); 54 case MVT::f32: return &APFloat::IEEEsingle; 55 case MVT::f64: return &APFloat::IEEEdouble; 56 case MVT::f80: return &APFloat::x87DoubleExtended; 57 case MVT::f128: return &APFloat::IEEEquad; 58 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 59 } 60} 61 62SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 63 64//===----------------------------------------------------------------------===// 65// ConstantFPSDNode Class 66//===----------------------------------------------------------------------===// 67 68/// isExactlyValue - We don't rely on operator== working on double values, as 69/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 70/// As such, this method can be used to do an exact bit-for-bit comparison of 71/// two floating point values. 72bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 73 return getValueAPF().bitwiseIsEqual(V); 74} 75 76bool ConstantFPSDNode::isValueValidForType(MVT VT, 77 const APFloat& Val) { 78 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 79 80 // PPC long double cannot be converted to any other type. 81 if (VT == MVT::ppcf128 || 82 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 83 return false; 84 85 // convert modifies in place, so make a copy. 86 APFloat Val2 = APFloat(Val); 87 bool losesInfo; 88 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 89 &losesInfo); 90 return !losesInfo; 91} 92 93//===----------------------------------------------------------------------===// 94// ISD Namespace 95//===----------------------------------------------------------------------===// 96 97/// isBuildVectorAllOnes - Return true if the specified node is a 98/// BUILD_VECTOR where all of the elements are ~0 or undef. 99bool ISD::isBuildVectorAllOnes(const SDNode *N) { 100 // Look through a bit convert. 101 if (N->getOpcode() == ISD::BIT_CONVERT) 102 N = N->getOperand(0).getNode(); 103 104 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 105 106 unsigned i = 0, e = N->getNumOperands(); 107 108 // Skip over all of the undef values. 109 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 110 ++i; 111 112 // Do not accept an all-undef vector. 113 if (i == e) return false; 114 115 // Do not accept build_vectors that aren't all constants or which have non-~0 116 // elements. 117 SDValue NotZero = N->getOperand(i); 118 if (isa<ConstantSDNode>(NotZero)) { 119 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 120 return false; 121 } else if (isa<ConstantFPSDNode>(NotZero)) { 122 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 123 bitcastToAPInt().isAllOnesValue()) 124 return false; 125 } else 126 return false; 127 128 // Okay, we have at least one ~0 value, check to see if the rest match or are 129 // undefs. 130 for (++i; i != e; ++i) 131 if (N->getOperand(i) != NotZero && 132 N->getOperand(i).getOpcode() != ISD::UNDEF) 133 return false; 134 return true; 135} 136 137 138/// isBuildVectorAllZeros - Return true if the specified node is a 139/// BUILD_VECTOR where all of the elements are 0 or undef. 140bool ISD::isBuildVectorAllZeros(const SDNode *N) { 141 // Look through a bit convert. 142 if (N->getOpcode() == ISD::BIT_CONVERT) 143 N = N->getOperand(0).getNode(); 144 145 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 146 147 unsigned i = 0, e = N->getNumOperands(); 148 149 // Skip over all of the undef values. 150 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 151 ++i; 152 153 // Do not accept an all-undef vector. 154 if (i == e) return false; 155 156 // Do not accept build_vectors that aren't all constants or which have non-~0 157 // elements. 158 SDValue Zero = N->getOperand(i); 159 if (isa<ConstantSDNode>(Zero)) { 160 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 161 return false; 162 } else if (isa<ConstantFPSDNode>(Zero)) { 163 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 164 return false; 165 } else 166 return false; 167 168 // Okay, we have at least one ~0 value, check to see if the rest match or are 169 // undefs. 170 for (++i; i != e; ++i) 171 if (N->getOperand(i) != Zero && 172 N->getOperand(i).getOpcode() != ISD::UNDEF) 173 return false; 174 return true; 175} 176 177/// isScalarToVector - Return true if the specified node is a 178/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 179/// element is not an undef. 180bool ISD::isScalarToVector(const SDNode *N) { 181 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 182 return true; 183 184 if (N->getOpcode() != ISD::BUILD_VECTOR) 185 return false; 186 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 187 return false; 188 unsigned NumElems = N->getNumOperands(); 189 for (unsigned i = 1; i < NumElems; ++i) { 190 SDValue V = N->getOperand(i); 191 if (V.getOpcode() != ISD::UNDEF) 192 return false; 193 } 194 return true; 195} 196 197 198/// isDebugLabel - Return true if the specified node represents a debug 199/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 200bool ISD::isDebugLabel(const SDNode *N) { 201 SDValue Zero; 202 if (N->getOpcode() == ISD::DBG_LABEL) 203 return true; 204 if (N->isMachineOpcode() && 205 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 206 return true; 207 return false; 208} 209 210/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 211/// when given the operation for (X op Y). 212ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 213 // To perform this operation, we just need to swap the L and G bits of the 214 // operation. 215 unsigned OldL = (Operation >> 2) & 1; 216 unsigned OldG = (Operation >> 1) & 1; 217 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 218 (OldL << 1) | // New G bit 219 (OldG << 2)); // New L bit. 220} 221 222/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 223/// 'op' is a valid SetCC operation. 224ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 225 unsigned Operation = Op; 226 if (isInteger) 227 Operation ^= 7; // Flip L, G, E bits, but not U. 228 else 229 Operation ^= 15; // Flip all of the condition bits. 230 231 if (Operation > ISD::SETTRUE2) 232 Operation &= ~8; // Don't let N and U bits get set. 233 234 return ISD::CondCode(Operation); 235} 236 237 238/// isSignedOp - For an integer comparison, return 1 if the comparison is a 239/// signed operation and 2 if the result is an unsigned comparison. Return zero 240/// if the operation does not depend on the sign of the input (setne and seteq). 241static int isSignedOp(ISD::CondCode Opcode) { 242 switch (Opcode) { 243 default: assert(0 && "Illegal integer setcc operation!"); 244 case ISD::SETEQ: 245 case ISD::SETNE: return 0; 246 case ISD::SETLT: 247 case ISD::SETLE: 248 case ISD::SETGT: 249 case ISD::SETGE: return 1; 250 case ISD::SETULT: 251 case ISD::SETULE: 252 case ISD::SETUGT: 253 case ISD::SETUGE: return 2; 254 } 255} 256 257/// getSetCCOrOperation - Return the result of a logical OR between different 258/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 259/// returns SETCC_INVALID if it is not possible to represent the resultant 260/// comparison. 261ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 262 bool isInteger) { 263 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 264 // Cannot fold a signed integer setcc with an unsigned integer setcc. 265 return ISD::SETCC_INVALID; 266 267 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 268 269 // If the N and U bits get set then the resultant comparison DOES suddenly 270 // care about orderedness, and is true when ordered. 271 if (Op > ISD::SETTRUE2) 272 Op &= ~16; // Clear the U bit if the N bit is set. 273 274 // Canonicalize illegal integer setcc's. 275 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 276 Op = ISD::SETNE; 277 278 return ISD::CondCode(Op); 279} 280 281/// getSetCCAndOperation - Return the result of a logical AND between different 282/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 283/// function returns zero if it is not possible to represent the resultant 284/// comparison. 285ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 286 bool isInteger) { 287 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 288 // Cannot fold a signed setcc with an unsigned setcc. 289 return ISD::SETCC_INVALID; 290 291 // Combine all of the condition bits. 292 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 293 294 // Canonicalize illegal integer setcc's. 295 if (isInteger) { 296 switch (Result) { 297 default: break; 298 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 299 case ISD::SETOEQ: // SETEQ & SETU[LG]E 300 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 301 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 302 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 303 } 304 } 305 306 return Result; 307} 308 309const TargetMachine &SelectionDAG::getTarget() const { 310 return MF->getTarget(); 311} 312 313//===----------------------------------------------------------------------===// 314// SDNode Profile Support 315//===----------------------------------------------------------------------===// 316 317/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 318/// 319static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 320 ID.AddInteger(OpC); 321} 322 323/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 324/// solely with their pointer. 325static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 326 ID.AddPointer(VTList.VTs); 327} 328 329/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 330/// 331static void AddNodeIDOperands(FoldingSetNodeID &ID, 332 const SDValue *Ops, unsigned NumOps) { 333 for (; NumOps; --NumOps, ++Ops) { 334 ID.AddPointer(Ops->getNode()); 335 ID.AddInteger(Ops->getResNo()); 336 } 337} 338 339/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 340/// 341static void AddNodeIDOperands(FoldingSetNodeID &ID, 342 const SDUse *Ops, unsigned NumOps) { 343 for (; NumOps; --NumOps, ++Ops) { 344 ID.AddPointer(Ops->getVal()); 345 ID.AddInteger(Ops->getSDValue().getResNo()); 346 } 347} 348 349static void AddNodeIDNode(FoldingSetNodeID &ID, 350 unsigned short OpC, SDVTList VTList, 351 const SDValue *OpList, unsigned N) { 352 AddNodeIDOpcode(ID, OpC); 353 AddNodeIDValueTypes(ID, VTList); 354 AddNodeIDOperands(ID, OpList, N); 355} 356 357/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 358/// the NodeID data. 359static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 360 switch (N->getOpcode()) { 361 default: break; // Normal nodes don't need extra info. 362 case ISD::ARG_FLAGS: 363 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 364 break; 365 case ISD::TargetConstant: 366 case ISD::Constant: 367 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 368 break; 369 case ISD::TargetConstantFP: 370 case ISD::ConstantFP: { 371 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 372 break; 373 } 374 case ISD::TargetGlobalAddress: 375 case ISD::GlobalAddress: 376 case ISD::TargetGlobalTLSAddress: 377 case ISD::GlobalTLSAddress: { 378 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 379 ID.AddPointer(GA->getGlobal()); 380 ID.AddInteger(GA->getOffset()); 381 break; 382 } 383 case ISD::BasicBlock: 384 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 385 break; 386 case ISD::Register: 387 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 388 break; 389 case ISD::DBG_STOPPOINT: { 390 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 391 ID.AddInteger(DSP->getLine()); 392 ID.AddInteger(DSP->getColumn()); 393 ID.AddPointer(DSP->getCompileUnit()); 394 break; 395 } 396 case ISD::SRCVALUE: 397 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 398 break; 399 case ISD::MEMOPERAND: { 400 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 401 MO.Profile(ID); 402 break; 403 } 404 case ISD::FrameIndex: 405 case ISD::TargetFrameIndex: 406 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 407 break; 408 case ISD::JumpTable: 409 case ISD::TargetJumpTable: 410 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 411 break; 412 case ISD::ConstantPool: 413 case ISD::TargetConstantPool: { 414 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 415 ID.AddInteger(CP->getAlignment()); 416 ID.AddInteger(CP->getOffset()); 417 if (CP->isMachineConstantPoolEntry()) 418 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 419 else 420 ID.AddPointer(CP->getConstVal()); 421 break; 422 } 423 case ISD::CALL: { 424 const CallSDNode *Call = cast<CallSDNode>(N); 425 ID.AddInteger(Call->getCallingConv()); 426 ID.AddInteger(Call->isVarArg()); 427 break; 428 } 429 case ISD::LOAD: { 430 const LoadSDNode *LD = cast<LoadSDNode>(N); 431 ID.AddInteger(LD->getAddressingMode()); 432 ID.AddInteger(LD->getExtensionType()); 433 ID.AddInteger(LD->getMemoryVT().getRawBits()); 434 ID.AddInteger(LD->getRawFlags()); 435 break; 436 } 437 case ISD::STORE: { 438 const StoreSDNode *ST = cast<StoreSDNode>(N); 439 ID.AddInteger(ST->getAddressingMode()); 440 ID.AddInteger(ST->isTruncatingStore()); 441 ID.AddInteger(ST->getMemoryVT().getRawBits()); 442 ID.AddInteger(ST->getRawFlags()); 443 break; 444 } 445 case ISD::ATOMIC_CMP_SWAP_8: 446 case ISD::ATOMIC_SWAP_8: 447 case ISD::ATOMIC_LOAD_ADD_8: 448 case ISD::ATOMIC_LOAD_SUB_8: 449 case ISD::ATOMIC_LOAD_AND_8: 450 case ISD::ATOMIC_LOAD_OR_8: 451 case ISD::ATOMIC_LOAD_XOR_8: 452 case ISD::ATOMIC_LOAD_NAND_8: 453 case ISD::ATOMIC_LOAD_MIN_8: 454 case ISD::ATOMIC_LOAD_MAX_8: 455 case ISD::ATOMIC_LOAD_UMIN_8: 456 case ISD::ATOMIC_LOAD_UMAX_8: 457 case ISD::ATOMIC_CMP_SWAP_16: 458 case ISD::ATOMIC_SWAP_16: 459 case ISD::ATOMIC_LOAD_ADD_16: 460 case ISD::ATOMIC_LOAD_SUB_16: 461 case ISD::ATOMIC_LOAD_AND_16: 462 case ISD::ATOMIC_LOAD_OR_16: 463 case ISD::ATOMIC_LOAD_XOR_16: 464 case ISD::ATOMIC_LOAD_NAND_16: 465 case ISD::ATOMIC_LOAD_MIN_16: 466 case ISD::ATOMIC_LOAD_MAX_16: 467 case ISD::ATOMIC_LOAD_UMIN_16: 468 case ISD::ATOMIC_LOAD_UMAX_16: 469 case ISD::ATOMIC_CMP_SWAP_32: 470 case ISD::ATOMIC_SWAP_32: 471 case ISD::ATOMIC_LOAD_ADD_32: 472 case ISD::ATOMIC_LOAD_SUB_32: 473 case ISD::ATOMIC_LOAD_AND_32: 474 case ISD::ATOMIC_LOAD_OR_32: 475 case ISD::ATOMIC_LOAD_XOR_32: 476 case ISD::ATOMIC_LOAD_NAND_32: 477 case ISD::ATOMIC_LOAD_MIN_32: 478 case ISD::ATOMIC_LOAD_MAX_32: 479 case ISD::ATOMIC_LOAD_UMIN_32: 480 case ISD::ATOMIC_LOAD_UMAX_32: 481 case ISD::ATOMIC_CMP_SWAP_64: 482 case ISD::ATOMIC_SWAP_64: 483 case ISD::ATOMIC_LOAD_ADD_64: 484 case ISD::ATOMIC_LOAD_SUB_64: 485 case ISD::ATOMIC_LOAD_AND_64: 486 case ISD::ATOMIC_LOAD_OR_64: 487 case ISD::ATOMIC_LOAD_XOR_64: 488 case ISD::ATOMIC_LOAD_NAND_64: 489 case ISD::ATOMIC_LOAD_MIN_64: 490 case ISD::ATOMIC_LOAD_MAX_64: 491 case ISD::ATOMIC_LOAD_UMIN_64: 492 case ISD::ATOMIC_LOAD_UMAX_64: { 493 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 494 ID.AddInteger(AT->getRawFlags()); 495 break; 496 } 497 } // end switch (N->getOpcode()) 498} 499 500/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 501/// data. 502static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 503 AddNodeIDOpcode(ID, N->getOpcode()); 504 // Add the return value info. 505 AddNodeIDValueTypes(ID, N->getVTList()); 506 // Add the operand info. 507 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 508 509 // Handle SDNode leafs with special info. 510 AddNodeIDCustom(ID, N); 511} 512 513/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 514/// the CSE map that carries both alignment and volatility information. 515/// 516static inline unsigned 517encodeMemSDNodeFlags(bool isVolatile, unsigned Alignment) { 518 return isVolatile | ((Log2_32(Alignment) + 1) << 1); 519} 520 521//===----------------------------------------------------------------------===// 522// SelectionDAG Class 523//===----------------------------------------------------------------------===// 524 525/// doNotCSE - Return true if CSE should not be performed for this node. 526static bool doNotCSE(SDNode *N) { 527 if (N->getValueType(0) == MVT::Flag) 528 return true; // Never CSE anything that produces a flag. 529 530 switch (N->getOpcode()) { 531 default: break; 532 case ISD::HANDLENODE: 533 case ISD::DBG_LABEL: 534 case ISD::DBG_STOPPOINT: 535 case ISD::EH_LABEL: 536 case ISD::DECLARE: 537 return true; // Never CSE these nodes. 538 } 539 540 // Check that remaining values produced are not flags. 541 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 542 if (N->getValueType(i) == MVT::Flag) 543 return true; // Never CSE anything that produces a flag. 544 545 return false; 546} 547 548/// RemoveDeadNodes - This method deletes all unreachable nodes in the 549/// SelectionDAG. 550void SelectionDAG::RemoveDeadNodes() { 551 // Create a dummy node (which is not added to allnodes), that adds a reference 552 // to the root node, preventing it from being deleted. 553 HandleSDNode Dummy(getRoot()); 554 555 SmallVector<SDNode*, 128> DeadNodes; 556 557 // Add all obviously-dead nodes to the DeadNodes worklist. 558 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 559 if (I->use_empty()) 560 DeadNodes.push_back(I); 561 562 RemoveDeadNodes(DeadNodes); 563 564 // If the root changed (e.g. it was a dead load, update the root). 565 setRoot(Dummy.getValue()); 566} 567 568/// RemoveDeadNodes - This method deletes the unreachable nodes in the 569/// given list, and any nodes that become unreachable as a result. 570void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 571 DAGUpdateListener *UpdateListener) { 572 573 // Process the worklist, deleting the nodes and adding their uses to the 574 // worklist. 575 while (!DeadNodes.empty()) { 576 SDNode *N = DeadNodes.back(); 577 DeadNodes.pop_back(); 578 579 if (UpdateListener) 580 UpdateListener->NodeDeleted(N, 0); 581 582 // Take the node out of the appropriate CSE map. 583 RemoveNodeFromCSEMaps(N); 584 585 // Next, brutally remove the operand list. This is safe to do, as there are 586 // no cycles in the graph. 587 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) { 588 SDNode *Operand = I->getVal(); 589 Operand->removeUser(std::distance(N->op_begin(), I), N); 590 591 // Now that we removed this operand, see if there are no uses of it left. 592 if (Operand->use_empty()) 593 DeadNodes.push_back(Operand); 594 } 595 596 if (N->OperandsNeedDelete) 597 delete[] N->OperandList; 598 599 N->OperandList = 0; 600 N->NumOperands = 0; 601 602 // Finally, remove N itself. 603 NodeAllocator.Deallocate(AllNodes.remove(N)); 604 } 605} 606 607void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 608 SmallVector<SDNode*, 16> DeadNodes(1, N); 609 RemoveDeadNodes(DeadNodes, UpdateListener); 610} 611 612void SelectionDAG::DeleteNode(SDNode *N) { 613 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 614 615 // First take this out of the appropriate CSE map. 616 RemoveNodeFromCSEMaps(N); 617 618 // Finally, remove uses due to operands of this node, remove from the 619 // AllNodes list, and delete the node. 620 DeleteNodeNotInCSEMaps(N); 621} 622 623void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 624 // Drop all of the operands and decrement used node's use counts. 625 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 626 I->getVal()->removeUser(std::distance(N->op_begin(), I), N); 627 628 if (N->OperandsNeedDelete) { 629 delete[] N->OperandList; 630 N->OperandList = 0; 631 } 632 633 assert(N != AllNodes.begin()); 634 NodeAllocator.Deallocate(AllNodes.remove(N)); 635} 636 637/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 638/// correspond to it. This is useful when we're about to delete or repurpose 639/// the node. We don't want future request for structurally identical nodes 640/// to return N anymore. 641bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 642 bool Erased = false; 643 switch (N->getOpcode()) { 644 case ISD::EntryToken: 645 assert(0 && "EntryToken should not be in CSEMaps!"); 646 return false; 647 case ISD::HANDLENODE: return false; // noop. 648 case ISD::CONDCODE: 649 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 650 "Cond code doesn't exist!"); 651 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 652 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 653 break; 654 case ISD::ExternalSymbol: 655 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 656 break; 657 case ISD::TargetExternalSymbol: 658 Erased = 659 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 660 break; 661 case ISD::VALUETYPE: { 662 MVT VT = cast<VTSDNode>(N)->getVT(); 663 if (VT.isExtended()) { 664 Erased = ExtendedValueTypeNodes.erase(VT); 665 } else { 666 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 667 ValueTypeNodes[VT.getSimpleVT()] = 0; 668 } 669 break; 670 } 671 default: 672 // Remove it from the CSE Map. 673 Erased = CSEMap.RemoveNode(N); 674 break; 675 } 676#ifndef NDEBUG 677 // Verify that the node was actually in one of the CSE maps, unless it has a 678 // flag result (which cannot be CSE'd) or is one of the special cases that are 679 // not subject to CSE. 680 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 681 !N->isMachineOpcode() && !doNotCSE(N)) { 682 N->dump(this); 683 cerr << "\n"; 684 assert(0 && "Node is not in map!"); 685 } 686#endif 687 return Erased; 688} 689 690/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 691/// has been taken out and modified in some way. If the specified node already 692/// exists in the CSE maps, do not modify the maps, but return the existing node 693/// instead. If it doesn't exist, add it and return null. 694/// 695SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 696 assert(N->getNumOperands() && "This is a leaf node!"); 697 698 if (doNotCSE(N)) 699 return 0; 700 701 SDNode *New = CSEMap.GetOrInsertNode(N); 702 if (New != N) return New; // Node already existed. 703 return 0; 704} 705 706/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 707/// were replaced with those specified. If this node is never memoized, 708/// return null, otherwise return a pointer to the slot it would take. If a 709/// node already exists with these operands, the slot will be non-null. 710SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 711 void *&InsertPos) { 712 if (doNotCSE(N)) 713 return 0; 714 715 SDValue Ops[] = { Op }; 716 FoldingSetNodeID ID; 717 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 718 AddNodeIDCustom(ID, N); 719 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 720} 721 722/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 723/// were replaced with those specified. If this node is never memoized, 724/// return null, otherwise return a pointer to the slot it would take. If a 725/// node already exists with these operands, the slot will be non-null. 726SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 727 SDValue Op1, SDValue Op2, 728 void *&InsertPos) { 729 if (doNotCSE(N)) 730 return 0; 731 732 SDValue Ops[] = { Op1, Op2 }; 733 FoldingSetNodeID ID; 734 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 735 AddNodeIDCustom(ID, N); 736 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 737} 738 739 740/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 741/// were replaced with those specified. If this node is never memoized, 742/// return null, otherwise return a pointer to the slot it would take. If a 743/// node already exists with these operands, the slot will be non-null. 744SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 745 const SDValue *Ops,unsigned NumOps, 746 void *&InsertPos) { 747 if (doNotCSE(N)) 748 return 0; 749 750 FoldingSetNodeID ID; 751 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 752 AddNodeIDCustom(ID, N); 753 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 754} 755 756/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 757void SelectionDAG::VerifyNode(SDNode *N) { 758 switch (N->getOpcode()) { 759 default: 760 break; 761 case ISD::BUILD_PAIR: { 762 MVT VT = N->getValueType(0); 763 assert(N->getNumValues() == 1 && "Too many results!"); 764 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 765 "Wrong return type!"); 766 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 767 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 768 "Mismatched operand types!"); 769 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 770 "Wrong operand type!"); 771 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 772 "Wrong return type size"); 773 break; 774 } 775 case ISD::BUILD_VECTOR: { 776 assert(N->getNumValues() == 1 && "Too many results!"); 777 assert(N->getValueType(0).isVector() && "Wrong return type!"); 778 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 779 "Wrong number of operands!"); 780 // FIXME: Change vector_shuffle to a variadic node with mask elements being 781 // operands of the node. Currently the mask is a BUILD_VECTOR passed as an 782 // operand, and it is not always possible to legalize it. Turning off the 783 // following checks at least makes it possible to legalize most of the time. 784// MVT EltVT = N->getValueType(0).getVectorElementType(); 785// for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 786// assert(I->getSDValue().getValueType() == EltVT && 787// "Wrong operand type!"); 788 break; 789 } 790 } 791} 792 793/// getMVTAlignment - Compute the default alignment value for the 794/// given type. 795/// 796unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 797 const Type *Ty = VT == MVT::iPTR ? 798 PointerType::get(Type::Int8Ty, 0) : 799 VT.getTypeForMVT(); 800 801 return TLI.getTargetData()->getABITypeAlignment(Ty); 802} 803 804SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 805 : TLI(tli), FLI(fli), 806 EntryNode(ISD::EntryToken, getVTList(MVT::Other)), 807 Root(getEntryNode()) { 808 AllNodes.push_back(&EntryNode); 809} 810 811void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi) { 812 MF = &mf; 813 MMI = mmi; 814} 815 816SelectionDAG::~SelectionDAG() { 817 allnodes_clear(); 818} 819 820void SelectionDAG::allnodes_clear() { 821 assert(&*AllNodes.begin() == &EntryNode); 822 AllNodes.remove(AllNodes.begin()); 823 while (!AllNodes.empty()) { 824 SDNode *N = AllNodes.remove(AllNodes.begin()); 825 N->SetNextInBucket(0); 826 827 if (N->OperandsNeedDelete) { 828 delete [] N->OperandList; 829 N->OperandList = 0; 830 } 831 832 NodeAllocator.Deallocate(N); 833 } 834} 835 836void SelectionDAG::clear() { 837 allnodes_clear(); 838 OperandAllocator.Reset(); 839 CSEMap.clear(); 840 841 ExtendedValueTypeNodes.clear(); 842 ExternalSymbols.clear(); 843 TargetExternalSymbols.clear(); 844 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 845 static_cast<CondCodeSDNode*>(0)); 846 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 847 static_cast<SDNode*>(0)); 848 849 EntryNode.Uses = 0; 850 AllNodes.push_back(&EntryNode); 851 Root = getEntryNode(); 852} 853 854SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) { 855 if (Op.getValueType() == VT) return Op; 856 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 857 VT.getSizeInBits()); 858 return getNode(ISD::AND, Op.getValueType(), Op, 859 getConstant(Imm, Op.getValueType())); 860} 861 862SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 863 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 864 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 865} 866 867SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 868 return getConstant(*ConstantInt::get(Val), VT, isT); 869} 870 871SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 872 assert(VT.isInteger() && "Cannot create FP integer constant!"); 873 874 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 875 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 876 "APInt size does not match type size!"); 877 878 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 879 FoldingSetNodeID ID; 880 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 881 ID.AddPointer(&Val); 882 void *IP = 0; 883 SDNode *N = NULL; 884 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 885 if (!VT.isVector()) 886 return SDValue(N, 0); 887 if (!N) { 888 N = NodeAllocator.Allocate<ConstantSDNode>(); 889 new (N) ConstantSDNode(isT, &Val, EltVT); 890 CSEMap.InsertNode(N, IP); 891 AllNodes.push_back(N); 892 } 893 894 SDValue Result(N, 0); 895 if (VT.isVector()) { 896 SmallVector<SDValue, 8> Ops; 897 Ops.assign(VT.getVectorNumElements(), Result); 898 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 899 } 900 return Result; 901} 902 903SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 904 return getConstant(Val, TLI.getPointerTy(), isTarget); 905} 906 907 908SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 909 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 910} 911 912SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 913 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 914 915 MVT EltVT = 916 VT.isVector() ? VT.getVectorElementType() : VT; 917 918 // Do the map lookup using the actual bit pattern for the floating point 919 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 920 // we don't have issues with SNANs. 921 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 922 FoldingSetNodeID ID; 923 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 924 ID.AddPointer(&V); 925 void *IP = 0; 926 SDNode *N = NULL; 927 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 928 if (!VT.isVector()) 929 return SDValue(N, 0); 930 if (!N) { 931 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 932 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 933 CSEMap.InsertNode(N, IP); 934 AllNodes.push_back(N); 935 } 936 937 SDValue Result(N, 0); 938 if (VT.isVector()) { 939 SmallVector<SDValue, 8> Ops; 940 Ops.assign(VT.getVectorNumElements(), Result); 941 Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 942 } 943 return Result; 944} 945 946SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 947 MVT EltVT = 948 VT.isVector() ? VT.getVectorElementType() : VT; 949 if (EltVT==MVT::f32) 950 return getConstantFP(APFloat((float)Val), VT, isTarget); 951 else 952 return getConstantFP(APFloat(Val), VT, isTarget); 953} 954 955SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 956 MVT VT, int64_t Offset, 957 bool isTargetGA) { 958 unsigned Opc; 959 960 // Truncate (with sign-extension) the offset value to the pointer size. 961 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 962 if (BitWidth < 64) 963 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 964 965 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 966 if (!GVar) { 967 // If GV is an alias then use the aliasee for determining thread-localness. 968 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 969 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 970 } 971 972 if (GVar && GVar->isThreadLocal()) 973 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 974 else 975 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 976 977 FoldingSetNodeID ID; 978 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 979 ID.AddPointer(GV); 980 ID.AddInteger(Offset); 981 void *IP = 0; 982 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 983 return SDValue(E, 0); 984 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 985 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 986 CSEMap.InsertNode(N, IP); 987 AllNodes.push_back(N); 988 return SDValue(N, 0); 989} 990 991SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 992 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 993 FoldingSetNodeID ID; 994 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 995 ID.AddInteger(FI); 996 void *IP = 0; 997 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 998 return SDValue(E, 0); 999 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 1000 new (N) FrameIndexSDNode(FI, VT, isTarget); 1001 CSEMap.InsertNode(N, IP); 1002 AllNodes.push_back(N); 1003 return SDValue(N, 0); 1004} 1005 1006SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 1007 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1008 FoldingSetNodeID ID; 1009 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1010 ID.AddInteger(JTI); 1011 void *IP = 0; 1012 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1013 return SDValue(E, 0); 1014 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1015 new (N) JumpTableSDNode(JTI, VT, isTarget); 1016 CSEMap.InsertNode(N, IP); 1017 AllNodes.push_back(N); 1018 return SDValue(N, 0); 1019} 1020 1021SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1022 unsigned Alignment, int Offset, 1023 bool isTarget) { 1024 if (Alignment == 0) 1025 Alignment = 1026 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1027 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1028 FoldingSetNodeID ID; 1029 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1030 ID.AddInteger(Alignment); 1031 ID.AddInteger(Offset); 1032 ID.AddPointer(C); 1033 void *IP = 0; 1034 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1035 return SDValue(E, 0); 1036 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1037 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1038 CSEMap.InsertNode(N, IP); 1039 AllNodes.push_back(N); 1040 return SDValue(N, 0); 1041} 1042 1043 1044SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1045 unsigned Alignment, int Offset, 1046 bool isTarget) { 1047 if (Alignment == 0) 1048 Alignment = 1049 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1050 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1051 FoldingSetNodeID ID; 1052 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1053 ID.AddInteger(Alignment); 1054 ID.AddInteger(Offset); 1055 C->AddSelectionDAGCSEId(ID); 1056 void *IP = 0; 1057 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1058 return SDValue(E, 0); 1059 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1060 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1061 CSEMap.InsertNode(N, IP); 1062 AllNodes.push_back(N); 1063 return SDValue(N, 0); 1064} 1065 1066 1067SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1068 FoldingSetNodeID ID; 1069 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1070 ID.AddPointer(MBB); 1071 void *IP = 0; 1072 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1073 return SDValue(E, 0); 1074 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1075 new (N) BasicBlockSDNode(MBB); 1076 CSEMap.InsertNode(N, IP); 1077 AllNodes.push_back(N); 1078 return SDValue(N, 0); 1079} 1080 1081SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1082 FoldingSetNodeID ID; 1083 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1084 ID.AddInteger(Flags.getRawBits()); 1085 void *IP = 0; 1086 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1087 return SDValue(E, 0); 1088 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1089 new (N) ARG_FLAGSSDNode(Flags); 1090 CSEMap.InsertNode(N, IP); 1091 AllNodes.push_back(N); 1092 return SDValue(N, 0); 1093} 1094 1095SDValue SelectionDAG::getValueType(MVT VT) { 1096 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1097 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1098 1099 SDNode *&N = VT.isExtended() ? 1100 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1101 1102 if (N) return SDValue(N, 0); 1103 N = NodeAllocator.Allocate<VTSDNode>(); 1104 new (N) VTSDNode(VT); 1105 AllNodes.push_back(N); 1106 return SDValue(N, 0); 1107} 1108 1109SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1110 SDNode *&N = ExternalSymbols[Sym]; 1111 if (N) return SDValue(N, 0); 1112 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1113 new (N) ExternalSymbolSDNode(false, Sym, VT); 1114 AllNodes.push_back(N); 1115 return SDValue(N, 0); 1116} 1117 1118SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1119 SDNode *&N = TargetExternalSymbols[Sym]; 1120 if (N) return SDValue(N, 0); 1121 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1122 new (N) ExternalSymbolSDNode(true, Sym, VT); 1123 AllNodes.push_back(N); 1124 return SDValue(N, 0); 1125} 1126 1127SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1128 if ((unsigned)Cond >= CondCodeNodes.size()) 1129 CondCodeNodes.resize(Cond+1); 1130 1131 if (CondCodeNodes[Cond] == 0) { 1132 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1133 new (N) CondCodeSDNode(Cond); 1134 CondCodeNodes[Cond] = N; 1135 AllNodes.push_back(N); 1136 } 1137 return SDValue(CondCodeNodes[Cond], 0); 1138} 1139 1140SDValue SelectionDAG::getConvertRndSat(MVT VT, SDValue Val, SDValue DTy, 1141 SDValue STy, SDValue Rnd, SDValue Sat, 1142 ISD::CvtCode Code) { 1143 // If the src and dest types are the same, no conversion is necessary. 1144 if (DTy == STy) 1145 return Val; 1146 1147 FoldingSetNodeID ID; 1148 void* IP = 0; 1149 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1150 return SDValue(E, 0); 1151 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1152 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1153 new (N) CvtRndSatSDNode(VT, Ops, 5, Code); 1154 CSEMap.InsertNode(N, IP); 1155 AllNodes.push_back(N); 1156 return SDValue(N, 0); 1157} 1158 1159SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1160 FoldingSetNodeID ID; 1161 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1162 ID.AddInteger(RegNo); 1163 void *IP = 0; 1164 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1165 return SDValue(E, 0); 1166 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1167 new (N) RegisterSDNode(RegNo, VT); 1168 CSEMap.InsertNode(N, IP); 1169 AllNodes.push_back(N); 1170 return SDValue(N, 0); 1171} 1172 1173SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1174 unsigned Line, unsigned Col, 1175 const CompileUnitDesc *CU) { 1176 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1177 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1178 AllNodes.push_back(N); 1179 return SDValue(N, 0); 1180} 1181 1182SDValue SelectionDAG::getLabel(unsigned Opcode, 1183 SDValue Root, 1184 unsigned LabelID) { 1185 FoldingSetNodeID ID; 1186 SDValue Ops[] = { Root }; 1187 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1188 ID.AddInteger(LabelID); 1189 void *IP = 0; 1190 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1191 return SDValue(E, 0); 1192 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1193 new (N) LabelSDNode(Opcode, Root, LabelID); 1194 CSEMap.InsertNode(N, IP); 1195 AllNodes.push_back(N); 1196 return SDValue(N, 0); 1197} 1198 1199SDValue SelectionDAG::getSrcValue(const Value *V) { 1200 assert((!V || isa<PointerType>(V->getType())) && 1201 "SrcValue is not a pointer?"); 1202 1203 FoldingSetNodeID ID; 1204 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1205 ID.AddPointer(V); 1206 1207 void *IP = 0; 1208 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1209 return SDValue(E, 0); 1210 1211 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1212 new (N) SrcValueSDNode(V); 1213 CSEMap.InsertNode(N, IP); 1214 AllNodes.push_back(N); 1215 return SDValue(N, 0); 1216} 1217 1218SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1219#ifndef NDEBUG 1220 const Value *v = MO.getValue(); 1221 assert((!v || isa<PointerType>(v->getType())) && 1222 "SrcValue is not a pointer?"); 1223#endif 1224 1225 FoldingSetNodeID ID; 1226 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1227 MO.Profile(ID); 1228 1229 void *IP = 0; 1230 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1231 return SDValue(E, 0); 1232 1233 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1234 new (N) MemOperandSDNode(MO); 1235 CSEMap.InsertNode(N, IP); 1236 AllNodes.push_back(N); 1237 return SDValue(N, 0); 1238} 1239 1240/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1241/// specified value type. 1242SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1243 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1244 unsigned ByteSize = VT.getStoreSizeInBits()/8; 1245 const Type *Ty = VT.getTypeForMVT(); 1246 unsigned StackAlign = 1247 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1248 1249 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1250 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1251} 1252 1253/// CreateStackTemporary - Create a stack temporary suitable for holding 1254/// either of the specified value types. 1255SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) { 1256 unsigned Bytes = std::max(VT1.getStoreSizeInBits(), 1257 VT2.getStoreSizeInBits())/8; 1258 const Type *Ty1 = VT1.getTypeForMVT(); 1259 const Type *Ty2 = VT2.getTypeForMVT(); 1260 const TargetData *TD = TLI.getTargetData(); 1261 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1), 1262 TD->getPrefTypeAlignment(Ty2)); 1263 1264 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1265 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align); 1266 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1267} 1268 1269SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1270 SDValue N2, ISD::CondCode Cond) { 1271 // These setcc operations always fold. 1272 switch (Cond) { 1273 default: break; 1274 case ISD::SETFALSE: 1275 case ISD::SETFALSE2: return getConstant(0, VT); 1276 case ISD::SETTRUE: 1277 case ISD::SETTRUE2: return getConstant(1, VT); 1278 1279 case ISD::SETOEQ: 1280 case ISD::SETOGT: 1281 case ISD::SETOGE: 1282 case ISD::SETOLT: 1283 case ISD::SETOLE: 1284 case ISD::SETONE: 1285 case ISD::SETO: 1286 case ISD::SETUO: 1287 case ISD::SETUEQ: 1288 case ISD::SETUNE: 1289 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1290 break; 1291 } 1292 1293 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1294 const APInt &C2 = N2C->getAPIntValue(); 1295 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1296 const APInt &C1 = N1C->getAPIntValue(); 1297 1298 switch (Cond) { 1299 default: assert(0 && "Unknown integer setcc!"); 1300 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1301 case ISD::SETNE: return getConstant(C1 != C2, VT); 1302 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1303 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1304 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1305 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1306 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1307 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1308 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1309 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1310 } 1311 } 1312 } 1313 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1314 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1315 // No compile time operations on this type yet. 1316 if (N1C->getValueType(0) == MVT::ppcf128) 1317 return SDValue(); 1318 1319 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1320 switch (Cond) { 1321 default: break; 1322 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1323 return getNode(ISD::UNDEF, VT); 1324 // fall through 1325 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1326 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1327 return getNode(ISD::UNDEF, VT); 1328 // fall through 1329 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1330 R==APFloat::cmpLessThan, VT); 1331 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1332 return getNode(ISD::UNDEF, VT); 1333 // fall through 1334 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1335 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1336 return getNode(ISD::UNDEF, VT); 1337 // fall through 1338 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1339 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1340 return getNode(ISD::UNDEF, VT); 1341 // fall through 1342 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1343 R==APFloat::cmpEqual, VT); 1344 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1345 return getNode(ISD::UNDEF, VT); 1346 // fall through 1347 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1348 R==APFloat::cmpEqual, VT); 1349 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1350 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1351 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1352 R==APFloat::cmpEqual, VT); 1353 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1354 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1355 R==APFloat::cmpLessThan, VT); 1356 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1357 R==APFloat::cmpUnordered, VT); 1358 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1359 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1360 } 1361 } else { 1362 // Ensure that the constant occurs on the RHS. 1363 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1364 } 1365 } 1366 1367 // Could not fold it. 1368 return SDValue(); 1369} 1370 1371/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1372/// use this predicate to simplify operations downstream. 1373bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1374 unsigned BitWidth = Op.getValueSizeInBits(); 1375 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1376} 1377 1378/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1379/// this predicate to simplify operations downstream. Mask is known to be zero 1380/// for bits that V cannot have. 1381bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1382 unsigned Depth) const { 1383 APInt KnownZero, KnownOne; 1384 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1385 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1386 return (KnownZero & Mask) == Mask; 1387} 1388 1389/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1390/// known to be either zero or one and return them in the KnownZero/KnownOne 1391/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1392/// processing. 1393void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1394 APInt &KnownZero, APInt &KnownOne, 1395 unsigned Depth) const { 1396 unsigned BitWidth = Mask.getBitWidth(); 1397 assert(BitWidth == Op.getValueType().getSizeInBits() && 1398 "Mask size mismatches value type size!"); 1399 1400 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1401 if (Depth == 6 || Mask == 0) 1402 return; // Limit search depth. 1403 1404 APInt KnownZero2, KnownOne2; 1405 1406 switch (Op.getOpcode()) { 1407 case ISD::Constant: 1408 // We know all of the bits for a constant! 1409 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1410 KnownZero = ~KnownOne & Mask; 1411 return; 1412 case ISD::AND: 1413 // If either the LHS or the RHS are Zero, the result is zero. 1414 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1415 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1416 KnownZero2, KnownOne2, Depth+1); 1417 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1418 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1419 1420 // Output known-1 bits are only known if set in both the LHS & RHS. 1421 KnownOne &= KnownOne2; 1422 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1423 KnownZero |= KnownZero2; 1424 return; 1425 case ISD::OR: 1426 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1427 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1428 KnownZero2, KnownOne2, Depth+1); 1429 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1430 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1431 1432 // Output known-0 bits are only known if clear in both the LHS & RHS. 1433 KnownZero &= KnownZero2; 1434 // Output known-1 are known to be set if set in either the LHS | RHS. 1435 KnownOne |= KnownOne2; 1436 return; 1437 case ISD::XOR: { 1438 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1439 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1440 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1441 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1442 1443 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1444 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1445 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1446 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1447 KnownZero = KnownZeroOut; 1448 return; 1449 } 1450 case ISD::MUL: { 1451 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1452 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1453 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1454 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1455 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1456 1457 // If low bits are zero in either operand, output low known-0 bits. 1458 // Also compute a conserative estimate for high known-0 bits. 1459 // More trickiness is possible, but this is sufficient for the 1460 // interesting case of alignment computation. 1461 KnownOne.clear(); 1462 unsigned TrailZ = KnownZero.countTrailingOnes() + 1463 KnownZero2.countTrailingOnes(); 1464 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1465 KnownZero2.countLeadingOnes(), 1466 BitWidth) - BitWidth; 1467 1468 TrailZ = std::min(TrailZ, BitWidth); 1469 LeadZ = std::min(LeadZ, BitWidth); 1470 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1471 APInt::getHighBitsSet(BitWidth, LeadZ); 1472 KnownZero &= Mask; 1473 return; 1474 } 1475 case ISD::UDIV: { 1476 // For the purposes of computing leading zeros we can conservatively 1477 // treat a udiv as a logical right shift by the power of 2 known to 1478 // be less than the denominator. 1479 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1480 ComputeMaskedBits(Op.getOperand(0), 1481 AllOnes, KnownZero2, KnownOne2, Depth+1); 1482 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1483 1484 KnownOne2.clear(); 1485 KnownZero2.clear(); 1486 ComputeMaskedBits(Op.getOperand(1), 1487 AllOnes, KnownZero2, KnownOne2, Depth+1); 1488 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1489 if (RHSUnknownLeadingOnes != BitWidth) 1490 LeadZ = std::min(BitWidth, 1491 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1492 1493 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1494 return; 1495 } 1496 case ISD::SELECT: 1497 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1498 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1499 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1500 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1501 1502 // Only known if known in both the LHS and RHS. 1503 KnownOne &= KnownOne2; 1504 KnownZero &= KnownZero2; 1505 return; 1506 case ISD::SELECT_CC: 1507 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1508 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1509 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1510 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1511 1512 // Only known if known in both the LHS and RHS. 1513 KnownOne &= KnownOne2; 1514 KnownZero &= KnownZero2; 1515 return; 1516 case ISD::SADDO: 1517 case ISD::UADDO: 1518 case ISD::SSUBO: 1519 case ISD::USUBO: 1520 case ISD::SMULO: 1521 case ISD::UMULO: 1522 if (Op.getResNo() != 1) 1523 return; 1524 // The boolean result conforms to getBooleanContents. Fall through. 1525 case ISD::SETCC: 1526 // If we know the result of a setcc has the top bits zero, use this info. 1527 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1528 BitWidth > 1) 1529 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1530 return; 1531 case ISD::SHL: 1532 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1533 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1534 unsigned ShAmt = SA->getZExtValue(); 1535 1536 // If the shift count is an invalid immediate, don't do anything. 1537 if (ShAmt >= BitWidth) 1538 return; 1539 1540 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1541 KnownZero, KnownOne, Depth+1); 1542 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1543 KnownZero <<= ShAmt; 1544 KnownOne <<= ShAmt; 1545 // low bits known zero. 1546 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1547 } 1548 return; 1549 case ISD::SRL: 1550 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1551 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1552 unsigned ShAmt = SA->getZExtValue(); 1553 1554 // If the shift count is an invalid immediate, don't do anything. 1555 if (ShAmt >= BitWidth) 1556 return; 1557 1558 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1559 KnownZero, KnownOne, Depth+1); 1560 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1561 KnownZero = KnownZero.lshr(ShAmt); 1562 KnownOne = KnownOne.lshr(ShAmt); 1563 1564 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1565 KnownZero |= HighBits; // High bits known zero. 1566 } 1567 return; 1568 case ISD::SRA: 1569 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1570 unsigned ShAmt = SA->getZExtValue(); 1571 1572 // If the shift count is an invalid immediate, don't do anything. 1573 if (ShAmt >= BitWidth) 1574 return; 1575 1576 APInt InDemandedMask = (Mask << ShAmt); 1577 // If any of the demanded bits are produced by the sign extension, we also 1578 // demand the input sign bit. 1579 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1580 if (HighBits.getBoolValue()) 1581 InDemandedMask |= APInt::getSignBit(BitWidth); 1582 1583 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1584 Depth+1); 1585 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1586 KnownZero = KnownZero.lshr(ShAmt); 1587 KnownOne = KnownOne.lshr(ShAmt); 1588 1589 // Handle the sign bits. 1590 APInt SignBit = APInt::getSignBit(BitWidth); 1591 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1592 1593 if (KnownZero.intersects(SignBit)) { 1594 KnownZero |= HighBits; // New bits are known zero. 1595 } else if (KnownOne.intersects(SignBit)) { 1596 KnownOne |= HighBits; // New bits are known one. 1597 } 1598 } 1599 return; 1600 case ISD::SIGN_EXTEND_INREG: { 1601 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1602 unsigned EBits = EVT.getSizeInBits(); 1603 1604 // Sign extension. Compute the demanded bits in the result that are not 1605 // present in the input. 1606 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1607 1608 APInt InSignBit = APInt::getSignBit(EBits); 1609 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1610 1611 // If the sign extended bits are demanded, we know that the sign 1612 // bit is demanded. 1613 InSignBit.zext(BitWidth); 1614 if (NewBits.getBoolValue()) 1615 InputDemandedBits |= InSignBit; 1616 1617 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1618 KnownZero, KnownOne, Depth+1); 1619 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1620 1621 // If the sign bit of the input is known set or clear, then we know the 1622 // top bits of the result. 1623 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1624 KnownZero |= NewBits; 1625 KnownOne &= ~NewBits; 1626 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1627 KnownOne |= NewBits; 1628 KnownZero &= ~NewBits; 1629 } else { // Input sign bit unknown 1630 KnownZero &= ~NewBits; 1631 KnownOne &= ~NewBits; 1632 } 1633 return; 1634 } 1635 case ISD::CTTZ: 1636 case ISD::CTLZ: 1637 case ISD::CTPOP: { 1638 unsigned LowBits = Log2_32(BitWidth)+1; 1639 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1640 KnownOne.clear(); 1641 return; 1642 } 1643 case ISD::LOAD: { 1644 if (ISD::isZEXTLoad(Op.getNode())) { 1645 LoadSDNode *LD = cast<LoadSDNode>(Op); 1646 MVT VT = LD->getMemoryVT(); 1647 unsigned MemBits = VT.getSizeInBits(); 1648 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1649 } 1650 return; 1651 } 1652 case ISD::ZERO_EXTEND: { 1653 MVT InVT = Op.getOperand(0).getValueType(); 1654 unsigned InBits = InVT.getSizeInBits(); 1655 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1656 APInt InMask = Mask; 1657 InMask.trunc(InBits); 1658 KnownZero.trunc(InBits); 1659 KnownOne.trunc(InBits); 1660 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1661 KnownZero.zext(BitWidth); 1662 KnownOne.zext(BitWidth); 1663 KnownZero |= NewBits; 1664 return; 1665 } 1666 case ISD::SIGN_EXTEND: { 1667 MVT InVT = Op.getOperand(0).getValueType(); 1668 unsigned InBits = InVT.getSizeInBits(); 1669 APInt InSignBit = APInt::getSignBit(InBits); 1670 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1671 APInt InMask = Mask; 1672 InMask.trunc(InBits); 1673 1674 // If any of the sign extended bits are demanded, we know that the sign 1675 // bit is demanded. Temporarily set this bit in the mask for our callee. 1676 if (NewBits.getBoolValue()) 1677 InMask |= InSignBit; 1678 1679 KnownZero.trunc(InBits); 1680 KnownOne.trunc(InBits); 1681 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1682 1683 // Note if the sign bit is known to be zero or one. 1684 bool SignBitKnownZero = KnownZero.isNegative(); 1685 bool SignBitKnownOne = KnownOne.isNegative(); 1686 assert(!(SignBitKnownZero && SignBitKnownOne) && 1687 "Sign bit can't be known to be both zero and one!"); 1688 1689 // If the sign bit wasn't actually demanded by our caller, we don't 1690 // want it set in the KnownZero and KnownOne result values. Reset the 1691 // mask and reapply it to the result values. 1692 InMask = Mask; 1693 InMask.trunc(InBits); 1694 KnownZero &= InMask; 1695 KnownOne &= InMask; 1696 1697 KnownZero.zext(BitWidth); 1698 KnownOne.zext(BitWidth); 1699 1700 // If the sign bit is known zero or one, the top bits match. 1701 if (SignBitKnownZero) 1702 KnownZero |= NewBits; 1703 else if (SignBitKnownOne) 1704 KnownOne |= NewBits; 1705 return; 1706 } 1707 case ISD::ANY_EXTEND: { 1708 MVT InVT = Op.getOperand(0).getValueType(); 1709 unsigned InBits = InVT.getSizeInBits(); 1710 APInt InMask = Mask; 1711 InMask.trunc(InBits); 1712 KnownZero.trunc(InBits); 1713 KnownOne.trunc(InBits); 1714 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1715 KnownZero.zext(BitWidth); 1716 KnownOne.zext(BitWidth); 1717 return; 1718 } 1719 case ISD::TRUNCATE: { 1720 MVT InVT = Op.getOperand(0).getValueType(); 1721 unsigned InBits = InVT.getSizeInBits(); 1722 APInt InMask = Mask; 1723 InMask.zext(InBits); 1724 KnownZero.zext(InBits); 1725 KnownOne.zext(InBits); 1726 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1727 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1728 KnownZero.trunc(BitWidth); 1729 KnownOne.trunc(BitWidth); 1730 break; 1731 } 1732 case ISD::AssertZext: { 1733 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1734 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1735 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1736 KnownOne, Depth+1); 1737 KnownZero |= (~InMask) & Mask; 1738 return; 1739 } 1740 case ISD::FGETSIGN: 1741 // All bits are zero except the low bit. 1742 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1743 return; 1744 1745 case ISD::SUB: { 1746 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1747 // We know that the top bits of C-X are clear if X contains less bits 1748 // than C (i.e. no wrap-around can happen). For example, 20-X is 1749 // positive if we can prove that X is >= 0 and < 16. 1750 if (CLHS->getAPIntValue().isNonNegative()) { 1751 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1752 // NLZ can't be BitWidth with no sign bit 1753 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1754 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1755 Depth+1); 1756 1757 // If all of the MaskV bits are known to be zero, then we know the 1758 // output top bits are zero, because we now know that the output is 1759 // from [0-C]. 1760 if ((KnownZero2 & MaskV) == MaskV) { 1761 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1762 // Top bits known zero. 1763 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1764 } 1765 } 1766 } 1767 } 1768 // fall through 1769 case ISD::ADD: { 1770 // Output known-0 bits are known if clear or set in both the low clear bits 1771 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1772 // low 3 bits clear. 1773 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1774 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1775 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1776 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1777 1778 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1779 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1780 KnownZeroOut = std::min(KnownZeroOut, 1781 KnownZero2.countTrailingOnes()); 1782 1783 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1784 return; 1785 } 1786 case ISD::SREM: 1787 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1788 const APInt &RA = Rem->getAPIntValue(); 1789 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1790 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1791 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1792 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1793 1794 // If the sign bit of the first operand is zero, the sign bit of 1795 // the result is zero. If the first operand has no one bits below 1796 // the second operand's single 1 bit, its sign will be zero. 1797 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1798 KnownZero2 |= ~LowBits; 1799 1800 KnownZero |= KnownZero2 & Mask; 1801 1802 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1803 } 1804 } 1805 return; 1806 case ISD::UREM: { 1807 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1808 const APInt &RA = Rem->getAPIntValue(); 1809 if (RA.isPowerOf2()) { 1810 APInt LowBits = (RA - 1); 1811 APInt Mask2 = LowBits & Mask; 1812 KnownZero |= ~LowBits & Mask; 1813 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1814 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1815 break; 1816 } 1817 } 1818 1819 // Since the result is less than or equal to either operand, any leading 1820 // zero bits in either operand must also exist in the result. 1821 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1822 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1823 Depth+1); 1824 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1825 Depth+1); 1826 1827 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1828 KnownZero2.countLeadingOnes()); 1829 KnownOne.clear(); 1830 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1831 return; 1832 } 1833 default: 1834 // Allow the target to implement this method for its nodes. 1835 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1836 case ISD::INTRINSIC_WO_CHAIN: 1837 case ISD::INTRINSIC_W_CHAIN: 1838 case ISD::INTRINSIC_VOID: 1839 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1840 } 1841 return; 1842 } 1843} 1844 1845/// ComputeNumSignBits - Return the number of times the sign bit of the 1846/// register is replicated into the other bits. We know that at least 1 bit 1847/// is always equal to the sign bit (itself), but other cases can give us 1848/// information. For example, immediately after an "SRA X, 2", we know that 1849/// the top 3 bits are all equal to each other, so we return 3. 1850unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1851 MVT VT = Op.getValueType(); 1852 assert(VT.isInteger() && "Invalid VT!"); 1853 unsigned VTBits = VT.getSizeInBits(); 1854 unsigned Tmp, Tmp2; 1855 unsigned FirstAnswer = 1; 1856 1857 if (Depth == 6) 1858 return 1; // Limit search depth. 1859 1860 switch (Op.getOpcode()) { 1861 default: break; 1862 case ISD::AssertSext: 1863 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1864 return VTBits-Tmp+1; 1865 case ISD::AssertZext: 1866 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1867 return VTBits-Tmp; 1868 1869 case ISD::Constant: { 1870 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1871 // If negative, return # leading ones. 1872 if (Val.isNegative()) 1873 return Val.countLeadingOnes(); 1874 1875 // Return # leading zeros. 1876 return Val.countLeadingZeros(); 1877 } 1878 1879 case ISD::SIGN_EXTEND: 1880 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1881 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1882 1883 case ISD::SIGN_EXTEND_INREG: 1884 // Max of the input and what this extends. 1885 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1886 Tmp = VTBits-Tmp+1; 1887 1888 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1889 return std::max(Tmp, Tmp2); 1890 1891 case ISD::SRA: 1892 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1893 // SRA X, C -> adds C sign bits. 1894 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1895 Tmp += C->getZExtValue(); 1896 if (Tmp > VTBits) Tmp = VTBits; 1897 } 1898 return Tmp; 1899 case ISD::SHL: 1900 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1901 // shl destroys sign bits. 1902 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1903 if (C->getZExtValue() >= VTBits || // Bad shift. 1904 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 1905 return Tmp - C->getZExtValue(); 1906 } 1907 break; 1908 case ISD::AND: 1909 case ISD::OR: 1910 case ISD::XOR: // NOT is handled here. 1911 // Logical binary ops preserve the number of sign bits at the worst. 1912 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1913 if (Tmp != 1) { 1914 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1915 FirstAnswer = std::min(Tmp, Tmp2); 1916 // We computed what we know about the sign bits as our first 1917 // answer. Now proceed to the generic code that uses 1918 // ComputeMaskedBits, and pick whichever answer is better. 1919 } 1920 break; 1921 1922 case ISD::SELECT: 1923 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1924 if (Tmp == 1) return 1; // Early out. 1925 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1926 return std::min(Tmp, Tmp2); 1927 1928 case ISD::SADDO: 1929 case ISD::UADDO: 1930 case ISD::SSUBO: 1931 case ISD::USUBO: 1932 case ISD::SMULO: 1933 case ISD::UMULO: 1934 if (Op.getResNo() != 1) 1935 break; 1936 // The boolean result conforms to getBooleanContents. Fall through. 1937 case ISD::SETCC: 1938 // If setcc returns 0/-1, all bits are sign bits. 1939 if (TLI.getBooleanContents() == 1940 TargetLowering::ZeroOrNegativeOneBooleanContent) 1941 return VTBits; 1942 break; 1943 case ISD::ROTL: 1944 case ISD::ROTR: 1945 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1946 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 1947 1948 // Handle rotate right by N like a rotate left by 32-N. 1949 if (Op.getOpcode() == ISD::ROTR) 1950 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1951 1952 // If we aren't rotating out all of the known-in sign bits, return the 1953 // number that are left. This handles rotl(sext(x), 1) for example. 1954 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1955 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1956 } 1957 break; 1958 case ISD::ADD: 1959 // Add can have at most one carry bit. Thus we know that the output 1960 // is, at worst, one more bit than the inputs. 1961 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1962 if (Tmp == 1) return 1; // Early out. 1963 1964 // Special case decrementing a value (ADD X, -1): 1965 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1966 if (CRHS->isAllOnesValue()) { 1967 APInt KnownZero, KnownOne; 1968 APInt Mask = APInt::getAllOnesValue(VTBits); 1969 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1970 1971 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1972 // sign bits set. 1973 if ((KnownZero | APInt(VTBits, 1)) == Mask) 1974 return VTBits; 1975 1976 // If we are subtracting one from a positive number, there is no carry 1977 // out of the result. 1978 if (KnownZero.isNegative()) 1979 return Tmp; 1980 } 1981 1982 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1983 if (Tmp2 == 1) return 1; 1984 return std::min(Tmp, Tmp2)-1; 1985 break; 1986 1987 case ISD::SUB: 1988 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1989 if (Tmp2 == 1) return 1; 1990 1991 // Handle NEG. 1992 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1993 if (CLHS->isNullValue()) { 1994 APInt KnownZero, KnownOne; 1995 APInt Mask = APInt::getAllOnesValue(VTBits); 1996 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1997 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1998 // sign bits set. 1999 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2000 return VTBits; 2001 2002 // If the input is known to be positive (the sign bit is known clear), 2003 // the output of the NEG has the same number of sign bits as the input. 2004 if (KnownZero.isNegative()) 2005 return Tmp2; 2006 2007 // Otherwise, we treat this like a SUB. 2008 } 2009 2010 // Sub can have at most one carry bit. Thus we know that the output 2011 // is, at worst, one more bit than the inputs. 2012 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2013 if (Tmp == 1) return 1; // Early out. 2014 return std::min(Tmp, Tmp2)-1; 2015 break; 2016 case ISD::TRUNCATE: 2017 // FIXME: it's tricky to do anything useful for this, but it is an important 2018 // case for targets like X86. 2019 break; 2020 } 2021 2022 // Handle LOADX separately here. EXTLOAD case will fallthrough. 2023 if (Op.getOpcode() == ISD::LOAD) { 2024 LoadSDNode *LD = cast<LoadSDNode>(Op); 2025 unsigned ExtType = LD->getExtensionType(); 2026 switch (ExtType) { 2027 default: break; 2028 case ISD::SEXTLOAD: // '17' bits known 2029 Tmp = LD->getMemoryVT().getSizeInBits(); 2030 return VTBits-Tmp+1; 2031 case ISD::ZEXTLOAD: // '16' bits known 2032 Tmp = LD->getMemoryVT().getSizeInBits(); 2033 return VTBits-Tmp; 2034 } 2035 } 2036 2037 // Allow the target to implement this method for its nodes. 2038 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2039 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2040 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2041 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2042 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2043 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2044 } 2045 2046 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2047 // use this information. 2048 APInt KnownZero, KnownOne; 2049 APInt Mask = APInt::getAllOnesValue(VTBits); 2050 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2051 2052 if (KnownZero.isNegative()) { // sign bit is 0 2053 Mask = KnownZero; 2054 } else if (KnownOne.isNegative()) { // sign bit is 1; 2055 Mask = KnownOne; 2056 } else { 2057 // Nothing known. 2058 return FirstAnswer; 2059 } 2060 2061 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2062 // the number of identical bits in the top of the input value. 2063 Mask = ~Mask; 2064 Mask <<= Mask.getBitWidth()-VTBits; 2065 // Return # leading zeros. We use 'min' here in case Val was zero before 2066 // shifting. We don't want to return '64' as for an i32 "0". 2067 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2068} 2069 2070 2071bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2072 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2073 if (!GA) return false; 2074 if (GA->getOffset() != 0) return false; 2075 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2076 if (!GV) return false; 2077 MachineModuleInfo *MMI = getMachineModuleInfo(); 2078 return MMI && MMI->hasDebugInfo() && MMI->isVerified(GV); 2079} 2080 2081 2082/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2083/// element of the result of the vector shuffle. 2084SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 2085 MVT VT = N->getValueType(0); 2086 SDValue PermMask = N->getOperand(2); 2087 SDValue Idx = PermMask.getOperand(i); 2088 if (Idx.getOpcode() == ISD::UNDEF) 2089 return getNode(ISD::UNDEF, VT.getVectorElementType()); 2090 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 2091 unsigned NumElems = PermMask.getNumOperands(); 2092 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2093 Index %= NumElems; 2094 2095 if (V.getOpcode() == ISD::BIT_CONVERT) { 2096 V = V.getOperand(0); 2097 MVT VVT = V.getValueType(); 2098 if (!VVT.isVector() || VVT.getVectorNumElements() != NumElems) 2099 return SDValue(); 2100 } 2101 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2102 return (Index == 0) ? V.getOperand(0) 2103 : getNode(ISD::UNDEF, VT.getVectorElementType()); 2104 if (V.getOpcode() == ISD::BUILD_VECTOR) 2105 return V.getOperand(Index); 2106 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 2107 return getShuffleScalarElt(V.getNode(), Index); 2108 return SDValue(); 2109} 2110 2111 2112/// getNode - Gets or creates the specified node. 2113/// 2114SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) { 2115 FoldingSetNodeID ID; 2116 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2117 void *IP = 0; 2118 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2119 return SDValue(E, 0); 2120 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2121 new (N) SDNode(Opcode, SDNode::getSDVTList(VT)); 2122 CSEMap.InsertNode(N, IP); 2123 2124 AllNodes.push_back(N); 2125#ifndef NDEBUG 2126 VerifyNode(N); 2127#endif 2128 return SDValue(N, 0); 2129} 2130 2131SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) { 2132 // Constant fold unary operations with an integer constant operand. 2133 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2134 const APInt &Val = C->getAPIntValue(); 2135 unsigned BitWidth = VT.getSizeInBits(); 2136 switch (Opcode) { 2137 default: break; 2138 case ISD::SIGN_EXTEND: 2139 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2140 case ISD::ANY_EXTEND: 2141 case ISD::ZERO_EXTEND: 2142 case ISD::TRUNCATE: 2143 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2144 case ISD::UINT_TO_FP: 2145 case ISD::SINT_TO_FP: { 2146 const uint64_t zero[] = {0, 0}; 2147 // No compile time operations on this type. 2148 if (VT==MVT::ppcf128) 2149 break; 2150 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2151 (void)apf.convertFromAPInt(Val, 2152 Opcode==ISD::SINT_TO_FP, 2153 APFloat::rmNearestTiesToEven); 2154 return getConstantFP(apf, VT); 2155 } 2156 case ISD::BIT_CONVERT: 2157 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2158 return getConstantFP(Val.bitsToFloat(), VT); 2159 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2160 return getConstantFP(Val.bitsToDouble(), VT); 2161 break; 2162 case ISD::BSWAP: 2163 return getConstant(Val.byteSwap(), VT); 2164 case ISD::CTPOP: 2165 return getConstant(Val.countPopulation(), VT); 2166 case ISD::CTLZ: 2167 return getConstant(Val.countLeadingZeros(), VT); 2168 case ISD::CTTZ: 2169 return getConstant(Val.countTrailingZeros(), VT); 2170 } 2171 } 2172 2173 // Constant fold unary operations with a floating point constant operand. 2174 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2175 APFloat V = C->getValueAPF(); // make copy 2176 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2177 switch (Opcode) { 2178 case ISD::FNEG: 2179 V.changeSign(); 2180 return getConstantFP(V, VT); 2181 case ISD::FABS: 2182 V.clearSign(); 2183 return getConstantFP(V, VT); 2184 case ISD::FP_ROUND: 2185 case ISD::FP_EXTEND: { 2186 bool ignored; 2187 // This can return overflow, underflow, or inexact; we don't care. 2188 // FIXME need to be more flexible about rounding mode. 2189 (void)V.convert(*MVTToAPFloatSemantics(VT), 2190 APFloat::rmNearestTiesToEven, &ignored); 2191 return getConstantFP(V, VT); 2192 } 2193 case ISD::FP_TO_SINT: 2194 case ISD::FP_TO_UINT: { 2195 integerPart x; 2196 bool ignored; 2197 assert(integerPartWidth >= 64); 2198 // FIXME need to be more flexible about rounding mode. 2199 APFloat::opStatus s = V.convertToInteger(&x, 64U, 2200 Opcode==ISD::FP_TO_SINT, 2201 APFloat::rmTowardZero, &ignored); 2202 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2203 break; 2204 return getConstant(x, VT); 2205 } 2206 case ISD::BIT_CONVERT: 2207 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2208 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2209 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2210 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2211 break; 2212 } 2213 } 2214 } 2215 2216 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2217 switch (Opcode) { 2218 case ISD::TokenFactor: 2219 case ISD::MERGE_VALUES: 2220 case ISD::CONCAT_VECTORS: 2221 return Operand; // Factor, merge or concat of one node? No need. 2222 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2223 case ISD::FP_EXTEND: 2224 assert(VT.isFloatingPoint() && 2225 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2226 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2227 if (Operand.getOpcode() == ISD::UNDEF) 2228 return getNode(ISD::UNDEF, VT); 2229 break; 2230 case ISD::SIGN_EXTEND: 2231 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2232 "Invalid SIGN_EXTEND!"); 2233 if (Operand.getValueType() == VT) return Operand; // noop extension 2234 assert(Operand.getValueType().bitsLT(VT) 2235 && "Invalid sext node, dst < src!"); 2236 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2237 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2238 break; 2239 case ISD::ZERO_EXTEND: 2240 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2241 "Invalid ZERO_EXTEND!"); 2242 if (Operand.getValueType() == VT) return Operand; // noop extension 2243 assert(Operand.getValueType().bitsLT(VT) 2244 && "Invalid zext node, dst < src!"); 2245 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2246 return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()->getOperand(0)); 2247 break; 2248 case ISD::ANY_EXTEND: 2249 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2250 "Invalid ANY_EXTEND!"); 2251 if (Operand.getValueType() == VT) return Operand; // noop extension 2252 assert(Operand.getValueType().bitsLT(VT) 2253 && "Invalid anyext node, dst < src!"); 2254 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2255 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2256 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2257 break; 2258 case ISD::TRUNCATE: 2259 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2260 "Invalid TRUNCATE!"); 2261 if (Operand.getValueType() == VT) return Operand; // noop truncate 2262 assert(Operand.getValueType().bitsGT(VT) 2263 && "Invalid truncate node, src < dst!"); 2264 if (OpOpcode == ISD::TRUNCATE) 2265 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2266 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2267 OpOpcode == ISD::ANY_EXTEND) { 2268 // If the source is smaller than the dest, we still need an extend. 2269 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2270 return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0)); 2271 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2272 return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0)); 2273 else 2274 return Operand.getNode()->getOperand(0); 2275 } 2276 break; 2277 case ISD::BIT_CONVERT: 2278 // Basic sanity checking. 2279 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2280 && "Cannot BIT_CONVERT between types of different sizes!"); 2281 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2282 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2283 return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0)); 2284 if (OpOpcode == ISD::UNDEF) 2285 return getNode(ISD::UNDEF, VT); 2286 break; 2287 case ISD::SCALAR_TO_VECTOR: 2288 assert(VT.isVector() && !Operand.getValueType().isVector() && 2289 VT.getVectorElementType() == Operand.getValueType() && 2290 "Illegal SCALAR_TO_VECTOR node!"); 2291 if (OpOpcode == ISD::UNDEF) 2292 return getNode(ISD::UNDEF, VT); 2293 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2294 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2295 isa<ConstantSDNode>(Operand.getOperand(1)) && 2296 Operand.getConstantOperandVal(1) == 0 && 2297 Operand.getOperand(0).getValueType() == VT) 2298 return Operand.getOperand(0); 2299 break; 2300 case ISD::FNEG: 2301 if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X) 2302 return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1), 2303 Operand.getNode()->getOperand(0)); 2304 if (OpOpcode == ISD::FNEG) // --X -> X 2305 return Operand.getNode()->getOperand(0); 2306 break; 2307 case ISD::FABS: 2308 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2309 return getNode(ISD::FABS, VT, Operand.getNode()->getOperand(0)); 2310 break; 2311 } 2312 2313 SDNode *N; 2314 SDVTList VTs = getVTList(VT); 2315 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2316 FoldingSetNodeID ID; 2317 SDValue Ops[1] = { Operand }; 2318 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2319 void *IP = 0; 2320 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2321 return SDValue(E, 0); 2322 N = NodeAllocator.Allocate<UnarySDNode>(); 2323 new (N) UnarySDNode(Opcode, VTs, Operand); 2324 CSEMap.InsertNode(N, IP); 2325 } else { 2326 N = NodeAllocator.Allocate<UnarySDNode>(); 2327 new (N) UnarySDNode(Opcode, VTs, Operand); 2328 } 2329 2330 AllNodes.push_back(N); 2331#ifndef NDEBUG 2332 VerifyNode(N); 2333#endif 2334 return SDValue(N, 0); 2335} 2336 2337SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2338 MVT VT, 2339 ConstantSDNode *Cst1, 2340 ConstantSDNode *Cst2) { 2341 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2342 2343 switch (Opcode) { 2344 case ISD::ADD: return getConstant(C1 + C2, VT); 2345 case ISD::SUB: return getConstant(C1 - C2, VT); 2346 case ISD::MUL: return getConstant(C1 * C2, VT); 2347 case ISD::UDIV: 2348 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2349 break; 2350 case ISD::UREM: 2351 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2352 break; 2353 case ISD::SDIV: 2354 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2355 break; 2356 case ISD::SREM: 2357 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2358 break; 2359 case ISD::AND: return getConstant(C1 & C2, VT); 2360 case ISD::OR: return getConstant(C1 | C2, VT); 2361 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2362 case ISD::SHL: return getConstant(C1 << C2, VT); 2363 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2364 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2365 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2366 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2367 default: break; 2368 } 2369 2370 return SDValue(); 2371} 2372 2373SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2374 SDValue N1, SDValue N2) { 2375 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2376 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2377 switch (Opcode) { 2378 default: break; 2379 case ISD::TokenFactor: 2380 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2381 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2382 // Fold trivial token factors. 2383 if (N1.getOpcode() == ISD::EntryToken) return N2; 2384 if (N2.getOpcode() == ISD::EntryToken) return N1; 2385 if (N1 == N2) return N1; 2386 break; 2387 case ISD::CONCAT_VECTORS: 2388 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2389 // one big BUILD_VECTOR. 2390 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2391 N2.getOpcode() == ISD::BUILD_VECTOR) { 2392 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2393 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2394 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2395 } 2396 break; 2397 case ISD::AND: 2398 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2399 N1.getValueType() == VT && "Binary operator types must match!"); 2400 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2401 // worth handling here. 2402 if (N2C && N2C->isNullValue()) 2403 return N2; 2404 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2405 return N1; 2406 break; 2407 case ISD::OR: 2408 case ISD::XOR: 2409 case ISD::ADD: 2410 case ISD::SUB: 2411 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2412 N1.getValueType() == VT && "Binary operator types must match!"); 2413 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2414 // it's worth handling here. 2415 if (N2C && N2C->isNullValue()) 2416 return N1; 2417 break; 2418 case ISD::UDIV: 2419 case ISD::UREM: 2420 case ISD::MULHU: 2421 case ISD::MULHS: 2422 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2423 // fall through 2424 case ISD::MUL: 2425 case ISD::SDIV: 2426 case ISD::SREM: 2427 case ISD::FADD: 2428 case ISD::FSUB: 2429 case ISD::FMUL: 2430 case ISD::FDIV: 2431 case ISD::FREM: 2432 assert(N1.getValueType() == N2.getValueType() && 2433 N1.getValueType() == VT && "Binary operator types must match!"); 2434 break; 2435 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2436 assert(N1.getValueType() == VT && 2437 N1.getValueType().isFloatingPoint() && 2438 N2.getValueType().isFloatingPoint() && 2439 "Invalid FCOPYSIGN!"); 2440 break; 2441 case ISD::SHL: 2442 case ISD::SRA: 2443 case ISD::SRL: 2444 case ISD::ROTL: 2445 case ISD::ROTR: 2446 assert(VT == N1.getValueType() && 2447 "Shift operators return type must be the same as their first arg"); 2448 assert(VT.isInteger() && N2.getValueType().isInteger() && 2449 "Shifts only work on integers"); 2450 assert((N2.getValueType() == TLI.getShiftAmountTy() || 2451 (N2.getValueType().isVector() && N2.getValueType().isInteger())) && 2452 "Wrong type for shift amount"); 2453 2454 // Always fold shifts of i1 values so the code generator doesn't need to 2455 // handle them. Since we know the size of the shift has to be less than the 2456 // size of the value, the shift/rotate count is guaranteed to be zero. 2457 if (VT == MVT::i1) 2458 return N1; 2459 break; 2460 case ISD::FP_ROUND_INREG: { 2461 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2462 assert(VT == N1.getValueType() && "Not an inreg round!"); 2463 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2464 "Cannot FP_ROUND_INREG integer types"); 2465 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2466 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2467 break; 2468 } 2469 case ISD::FP_ROUND: 2470 assert(VT.isFloatingPoint() && 2471 N1.getValueType().isFloatingPoint() && 2472 VT.bitsLE(N1.getValueType()) && 2473 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2474 if (N1.getValueType() == VT) return N1; // noop conversion. 2475 break; 2476 case ISD::AssertSext: 2477 case ISD::AssertZext: { 2478 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2479 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2480 assert(VT.isInteger() && EVT.isInteger() && 2481 "Cannot *_EXTEND_INREG FP types"); 2482 assert(EVT.bitsLE(VT) && "Not extending!"); 2483 if (VT == EVT) return N1; // noop assertion. 2484 break; 2485 } 2486 case ISD::SIGN_EXTEND_INREG: { 2487 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2488 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2489 assert(VT.isInteger() && EVT.isInteger() && 2490 "Cannot *_EXTEND_INREG FP types"); 2491 assert(EVT.bitsLE(VT) && "Not extending!"); 2492 if (EVT == VT) return N1; // Not actually extending 2493 2494 if (N1C) { 2495 APInt Val = N1C->getAPIntValue(); 2496 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2497 Val <<= Val.getBitWidth()-FromBits; 2498 Val = Val.ashr(Val.getBitWidth()-FromBits); 2499 return getConstant(Val, VT); 2500 } 2501 break; 2502 } 2503 case ISD::EXTRACT_VECTOR_ELT: 2504 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2505 if (N1.getOpcode() == ISD::UNDEF) 2506 return getNode(ISD::UNDEF, VT); 2507 2508 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2509 // expanding copies of large vectors from registers. 2510 if (N2C && 2511 N1.getOpcode() == ISD::CONCAT_VECTORS && 2512 N1.getNumOperands() > 0) { 2513 unsigned Factor = 2514 N1.getOperand(0).getValueType().getVectorNumElements(); 2515 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, 2516 N1.getOperand(N2C->getZExtValue() / Factor), 2517 getConstant(N2C->getZExtValue() % Factor, 2518 N2.getValueType())); 2519 } 2520 2521 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2522 // expanding large vector constants. 2523 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) 2524 return N1.getOperand(N2C->getZExtValue()); 2525 2526 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2527 // operations are lowered to scalars. 2528 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2529 if (N1.getOperand(2) == N2) 2530 return N1.getOperand(1); 2531 else 2532 return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2); 2533 } 2534 break; 2535 case ISD::EXTRACT_ELEMENT: 2536 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2537 assert(!N1.getValueType().isVector() && !VT.isVector() && 2538 (N1.getValueType().isInteger() == VT.isInteger()) && 2539 "Wrong types for EXTRACT_ELEMENT!"); 2540 2541 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2542 // 64-bit integers into 32-bit parts. Instead of building the extract of 2543 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2544 if (N1.getOpcode() == ISD::BUILD_PAIR) 2545 return N1.getOperand(N2C->getZExtValue()); 2546 2547 // EXTRACT_ELEMENT of a constant int is also very common. 2548 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2549 unsigned ElementSize = VT.getSizeInBits(); 2550 unsigned Shift = ElementSize * N2C->getZExtValue(); 2551 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2552 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2553 } 2554 break; 2555 case ISD::EXTRACT_SUBVECTOR: 2556 if (N1.getValueType() == VT) // Trivial extraction. 2557 return N1; 2558 break; 2559 } 2560 2561 if (N1C) { 2562 if (N2C) { 2563 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2564 if (SV.getNode()) return SV; 2565 } else { // Cannonicalize constant to RHS if commutative 2566 if (isCommutativeBinOp(Opcode)) { 2567 std::swap(N1C, N2C); 2568 std::swap(N1, N2); 2569 } 2570 } 2571 } 2572 2573 // Constant fold FP operations. 2574 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2575 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2576 if (N1CFP) { 2577 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2578 // Cannonicalize constant to RHS if commutative 2579 std::swap(N1CFP, N2CFP); 2580 std::swap(N1, N2); 2581 } else if (N2CFP && VT != MVT::ppcf128) { 2582 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2583 APFloat::opStatus s; 2584 switch (Opcode) { 2585 case ISD::FADD: 2586 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2587 if (s != APFloat::opInvalidOp) 2588 return getConstantFP(V1, VT); 2589 break; 2590 case ISD::FSUB: 2591 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2592 if (s!=APFloat::opInvalidOp) 2593 return getConstantFP(V1, VT); 2594 break; 2595 case ISD::FMUL: 2596 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2597 if (s!=APFloat::opInvalidOp) 2598 return getConstantFP(V1, VT); 2599 break; 2600 case ISD::FDIV: 2601 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2602 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2603 return getConstantFP(V1, VT); 2604 break; 2605 case ISD::FREM : 2606 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2607 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2608 return getConstantFP(V1, VT); 2609 break; 2610 case ISD::FCOPYSIGN: 2611 V1.copySign(V2); 2612 return getConstantFP(V1, VT); 2613 default: break; 2614 } 2615 } 2616 } 2617 2618 // Canonicalize an UNDEF to the RHS, even over a constant. 2619 if (N1.getOpcode() == ISD::UNDEF) { 2620 if (isCommutativeBinOp(Opcode)) { 2621 std::swap(N1, N2); 2622 } else { 2623 switch (Opcode) { 2624 case ISD::FP_ROUND_INREG: 2625 case ISD::SIGN_EXTEND_INREG: 2626 case ISD::SUB: 2627 case ISD::FSUB: 2628 case ISD::FDIV: 2629 case ISD::FREM: 2630 case ISD::SRA: 2631 return N1; // fold op(undef, arg2) -> undef 2632 case ISD::UDIV: 2633 case ISD::SDIV: 2634 case ISD::UREM: 2635 case ISD::SREM: 2636 case ISD::SRL: 2637 case ISD::SHL: 2638 if (!VT.isVector()) 2639 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2640 // For vectors, we can't easily build an all zero vector, just return 2641 // the LHS. 2642 return N2; 2643 } 2644 } 2645 } 2646 2647 // Fold a bunch of operators when the RHS is undef. 2648 if (N2.getOpcode() == ISD::UNDEF) { 2649 switch (Opcode) { 2650 case ISD::XOR: 2651 if (N1.getOpcode() == ISD::UNDEF) 2652 // Handle undef ^ undef -> 0 special case. This is a common 2653 // idiom (misuse). 2654 return getConstant(0, VT); 2655 // fallthrough 2656 case ISD::ADD: 2657 case ISD::ADDC: 2658 case ISD::ADDE: 2659 case ISD::SUB: 2660 case ISD::FADD: 2661 case ISD::FSUB: 2662 case ISD::FMUL: 2663 case ISD::FDIV: 2664 case ISD::FREM: 2665 case ISD::UDIV: 2666 case ISD::SDIV: 2667 case ISD::UREM: 2668 case ISD::SREM: 2669 return N2; // fold op(arg1, undef) -> undef 2670 case ISD::MUL: 2671 case ISD::AND: 2672 case ISD::SRL: 2673 case ISD::SHL: 2674 if (!VT.isVector()) 2675 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2676 // For vectors, we can't easily build an all zero vector, just return 2677 // the LHS. 2678 return N1; 2679 case ISD::OR: 2680 if (!VT.isVector()) 2681 return getConstant(VT.getIntegerVTBitMask(), VT); 2682 // For vectors, we can't easily build an all one vector, just return 2683 // the LHS. 2684 return N1; 2685 case ISD::SRA: 2686 return N1; 2687 } 2688 } 2689 2690 // Memoize this node if possible. 2691 SDNode *N; 2692 SDVTList VTs = getVTList(VT); 2693 if (VT != MVT::Flag) { 2694 SDValue Ops[] = { N1, N2 }; 2695 FoldingSetNodeID ID; 2696 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2697 void *IP = 0; 2698 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2699 return SDValue(E, 0); 2700 N = NodeAllocator.Allocate<BinarySDNode>(); 2701 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2702 CSEMap.InsertNode(N, IP); 2703 } else { 2704 N = NodeAllocator.Allocate<BinarySDNode>(); 2705 new (N) BinarySDNode(Opcode, VTs, N1, N2); 2706 } 2707 2708 AllNodes.push_back(N); 2709#ifndef NDEBUG 2710 VerifyNode(N); 2711#endif 2712 return SDValue(N, 0); 2713} 2714 2715SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2716 SDValue N1, SDValue N2, SDValue N3) { 2717 // Perform various simplifications. 2718 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2719 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2720 switch (Opcode) { 2721 case ISD::CONCAT_VECTORS: 2722 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2723 // one big BUILD_VECTOR. 2724 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2725 N2.getOpcode() == ISD::BUILD_VECTOR && 2726 N3.getOpcode() == ISD::BUILD_VECTOR) { 2727 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2728 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2729 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2730 return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size()); 2731 } 2732 break; 2733 case ISD::SETCC: { 2734 // Use FoldSetCC to simplify SETCC's. 2735 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 2736 if (Simp.getNode()) return Simp; 2737 break; 2738 } 2739 case ISD::SELECT: 2740 if (N1C) { 2741 if (N1C->getZExtValue()) 2742 return N2; // select true, X, Y -> X 2743 else 2744 return N3; // select false, X, Y -> Y 2745 } 2746 2747 if (N2 == N3) return N2; // select C, X, X -> X 2748 break; 2749 case ISD::BRCOND: 2750 if (N2C) { 2751 if (N2C->getZExtValue()) // Unconditional branch 2752 return getNode(ISD::BR, MVT::Other, N1, N3); 2753 else 2754 return N1; // Never-taken branch 2755 } 2756 break; 2757 case ISD::VECTOR_SHUFFLE: 2758 assert(N1.getValueType() == N2.getValueType() && 2759 N1.getValueType().isVector() && 2760 VT.isVector() && N3.getValueType().isVector() && 2761 N3.getOpcode() == ISD::BUILD_VECTOR && 2762 VT.getVectorNumElements() == N3.getNumOperands() && 2763 "Illegal VECTOR_SHUFFLE node!"); 2764 break; 2765 case ISD::BIT_CONVERT: 2766 // Fold bit_convert nodes from a type to themselves. 2767 if (N1.getValueType() == VT) 2768 return N1; 2769 break; 2770 } 2771 2772 // Memoize node if it doesn't produce a flag. 2773 SDNode *N; 2774 SDVTList VTs = getVTList(VT); 2775 if (VT != MVT::Flag) { 2776 SDValue Ops[] = { N1, N2, N3 }; 2777 FoldingSetNodeID ID; 2778 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2779 void *IP = 0; 2780 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2781 return SDValue(E, 0); 2782 N = NodeAllocator.Allocate<TernarySDNode>(); 2783 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2784 CSEMap.InsertNode(N, IP); 2785 } else { 2786 N = NodeAllocator.Allocate<TernarySDNode>(); 2787 new (N) TernarySDNode(Opcode, VTs, N1, N2, N3); 2788 } 2789 AllNodes.push_back(N); 2790#ifndef NDEBUG 2791 VerifyNode(N); 2792#endif 2793 return SDValue(N, 0); 2794} 2795 2796SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2797 SDValue N1, SDValue N2, SDValue N3, 2798 SDValue N4) { 2799 SDValue Ops[] = { N1, N2, N3, N4 }; 2800 return getNode(Opcode, VT, Ops, 4); 2801} 2802 2803SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2804 SDValue N1, SDValue N2, SDValue N3, 2805 SDValue N4, SDValue N5) { 2806 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2807 return getNode(Opcode, VT, Ops, 5); 2808} 2809 2810/// getMemsetValue - Vectorized representation of the memset value 2811/// operand. 2812static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) { 2813 unsigned NumBits = VT.isVector() ? 2814 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2815 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2816 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2817 unsigned Shift = 8; 2818 for (unsigned i = NumBits; i > 8; i >>= 1) { 2819 Val = (Val << Shift) | Val; 2820 Shift <<= 1; 2821 } 2822 if (VT.isInteger()) 2823 return DAG.getConstant(Val, VT); 2824 return DAG.getConstantFP(APFloat(Val), VT); 2825 } 2826 2827 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2828 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value); 2829 unsigned Shift = 8; 2830 for (unsigned i = NumBits; i > 8; i >>= 1) { 2831 Value = DAG.getNode(ISD::OR, VT, 2832 DAG.getNode(ISD::SHL, VT, Value, 2833 DAG.getConstant(Shift, 2834 TLI.getShiftAmountTy())), 2835 Value); 2836 Shift <<= 1; 2837 } 2838 2839 return Value; 2840} 2841 2842/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2843/// used when a memcpy is turned into a memset when the source is a constant 2844/// string ptr. 2845static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG, 2846 const TargetLowering &TLI, 2847 std::string &Str, unsigned Offset) { 2848 // Handle vector with all elements zero. 2849 if (Str.empty()) { 2850 if (VT.isInteger()) 2851 return DAG.getConstant(0, VT); 2852 unsigned NumElts = VT.getVectorNumElements(); 2853 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2854 return DAG.getNode(ISD::BIT_CONVERT, VT, 2855 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2856 } 2857 2858 assert(!VT.isVector() && "Can't handle vector type here!"); 2859 unsigned NumBits = VT.getSizeInBits(); 2860 unsigned MSB = NumBits / 8; 2861 uint64_t Val = 0; 2862 if (TLI.isLittleEndian()) 2863 Offset = Offset + MSB - 1; 2864 for (unsigned i = 0; i != MSB; ++i) { 2865 Val = (Val << 8) | (unsigned char)Str[Offset]; 2866 Offset += TLI.isLittleEndian() ? -1 : 1; 2867 } 2868 return DAG.getConstant(Val, VT); 2869} 2870 2871/// getMemBasePlusOffset - Returns base and offset node for the 2872/// 2873static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2874 SelectionDAG &DAG) { 2875 MVT VT = Base.getValueType(); 2876 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); 2877} 2878 2879/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2880/// 2881static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2882 unsigned SrcDelta = 0; 2883 GlobalAddressSDNode *G = NULL; 2884 if (Src.getOpcode() == ISD::GlobalAddress) 2885 G = cast<GlobalAddressSDNode>(Src); 2886 else if (Src.getOpcode() == ISD::ADD && 2887 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2888 Src.getOperand(1).getOpcode() == ISD::Constant) { 2889 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2890 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 2891 } 2892 if (!G) 2893 return false; 2894 2895 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2896 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 2897 return true; 2898 2899 return false; 2900} 2901 2902/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 2903/// to replace the memset / memcpy is below the threshold. It also returns the 2904/// types of the sequence of memory ops to perform memset / memcpy. 2905static 2906bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 2907 SDValue Dst, SDValue Src, 2908 unsigned Limit, uint64_t Size, unsigned &Align, 2909 std::string &Str, bool &isSrcStr, 2910 SelectionDAG &DAG, 2911 const TargetLowering &TLI) { 2912 isSrcStr = isMemSrcFromString(Src, Str); 2913 bool isSrcConst = isa<ConstantSDNode>(Src); 2914 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 2915 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 2916 if (VT != MVT::iAny) { 2917 unsigned NewAlign = (unsigned) 2918 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 2919 // If source is a string constant, this will require an unaligned load. 2920 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 2921 if (Dst.getOpcode() != ISD::FrameIndex) { 2922 // Can't change destination alignment. It requires a unaligned store. 2923 if (AllowUnalign) 2924 VT = MVT::iAny; 2925 } else { 2926 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 2927 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2928 if (MFI->isFixedObjectIndex(FI)) { 2929 // Can't change destination alignment. It requires a unaligned store. 2930 if (AllowUnalign) 2931 VT = MVT::iAny; 2932 } else { 2933 // Give the stack frame object a larger alignment if needed. 2934 if (MFI->getObjectAlignment(FI) < NewAlign) 2935 MFI->setObjectAlignment(FI, NewAlign); 2936 Align = NewAlign; 2937 } 2938 } 2939 } 2940 } 2941 2942 if (VT == MVT::iAny) { 2943 if (AllowUnalign) { 2944 VT = MVT::i64; 2945 } else { 2946 switch (Align & 7) { 2947 case 0: VT = MVT::i64; break; 2948 case 4: VT = MVT::i32; break; 2949 case 2: VT = MVT::i16; break; 2950 default: VT = MVT::i8; break; 2951 } 2952 } 2953 2954 MVT LVT = MVT::i64; 2955 while (!TLI.isTypeLegal(LVT)) 2956 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 2957 assert(LVT.isInteger()); 2958 2959 if (VT.bitsGT(LVT)) 2960 VT = LVT; 2961 } 2962 2963 unsigned NumMemOps = 0; 2964 while (Size != 0) { 2965 unsigned VTSize = VT.getSizeInBits() / 8; 2966 while (VTSize > Size) { 2967 // For now, only use non-vector load / store's for the left-over pieces. 2968 if (VT.isVector()) { 2969 VT = MVT::i64; 2970 while (!TLI.isTypeLegal(VT)) 2971 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2972 VTSize = VT.getSizeInBits() / 8; 2973 } else { 2974 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 2975 VTSize >>= 1; 2976 } 2977 } 2978 2979 if (++NumMemOps > Limit) 2980 return false; 2981 MemOps.push_back(VT); 2982 Size -= VTSize; 2983 } 2984 2985 return true; 2986} 2987 2988static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, 2989 SDValue Chain, SDValue Dst, 2990 SDValue Src, uint64_t Size, 2991 unsigned Align, bool AlwaysInline, 2992 const Value *DstSV, uint64_t DstSVOff, 2993 const Value *SrcSV, uint64_t SrcSVOff){ 2994 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2995 2996 // Expand memcpy to a series of load and store ops if the size operand falls 2997 // below a certain threshold. 2998 std::vector<MVT> MemOps; 2999 uint64_t Limit = -1ULL; 3000 if (!AlwaysInline) 3001 Limit = TLI.getMaxStoresPerMemcpy(); 3002 unsigned DstAlign = Align; // Destination alignment can change. 3003 std::string Str; 3004 bool CopyFromStr; 3005 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3006 Str, CopyFromStr, DAG, TLI)) 3007 return SDValue(); 3008 3009 3010 bool isZeroStr = CopyFromStr && Str.empty(); 3011 SmallVector<SDValue, 8> OutChains; 3012 unsigned NumMemOps = MemOps.size(); 3013 uint64_t SrcOff = 0, DstOff = 0; 3014 for (unsigned i = 0; i < NumMemOps; i++) { 3015 MVT VT = MemOps[i]; 3016 unsigned VTSize = VT.getSizeInBits() / 8; 3017 SDValue Value, Store; 3018 3019 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 3020 // It's unlikely a store of a vector immediate can be done in a single 3021 // instruction. It would require a load from a constantpool first. 3022 // We also handle store a vector with all zero's. 3023 // FIXME: Handle other cases where store of vector immediate is done in 3024 // a single instruction. 3025 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff); 3026 Store = DAG.getStore(Chain, Value, 3027 getMemBasePlusOffset(Dst, DstOff, DAG), 3028 DstSV, DstSVOff + DstOff, false, DstAlign); 3029 } else { 3030 Value = DAG.getLoad(VT, Chain, 3031 getMemBasePlusOffset(Src, SrcOff, DAG), 3032 SrcSV, SrcSVOff + SrcOff, false, Align); 3033 Store = DAG.getStore(Chain, Value, 3034 getMemBasePlusOffset(Dst, DstOff, DAG), 3035 DstSV, DstSVOff + DstOff, false, DstAlign); 3036 } 3037 OutChains.push_back(Store); 3038 SrcOff += VTSize; 3039 DstOff += VTSize; 3040 } 3041 3042 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3043 &OutChains[0], OutChains.size()); 3044} 3045 3046static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, 3047 SDValue Chain, SDValue Dst, 3048 SDValue Src, uint64_t Size, 3049 unsigned Align, bool AlwaysInline, 3050 const Value *DstSV, uint64_t DstSVOff, 3051 const Value *SrcSV, uint64_t SrcSVOff){ 3052 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3053 3054 // Expand memmove to a series of load and store ops if the size operand falls 3055 // below a certain threshold. 3056 std::vector<MVT> MemOps; 3057 uint64_t Limit = -1ULL; 3058 if (!AlwaysInline) 3059 Limit = TLI.getMaxStoresPerMemmove(); 3060 unsigned DstAlign = Align; // Destination alignment can change. 3061 std::string Str; 3062 bool CopyFromStr; 3063 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3064 Str, CopyFromStr, DAG, TLI)) 3065 return SDValue(); 3066 3067 uint64_t SrcOff = 0, DstOff = 0; 3068 3069 SmallVector<SDValue, 8> LoadValues; 3070 SmallVector<SDValue, 8> LoadChains; 3071 SmallVector<SDValue, 8> OutChains; 3072 unsigned NumMemOps = MemOps.size(); 3073 for (unsigned i = 0; i < NumMemOps; i++) { 3074 MVT VT = MemOps[i]; 3075 unsigned VTSize = VT.getSizeInBits() / 8; 3076 SDValue Value, Store; 3077 3078 Value = DAG.getLoad(VT, Chain, 3079 getMemBasePlusOffset(Src, SrcOff, DAG), 3080 SrcSV, SrcSVOff + SrcOff, false, Align); 3081 LoadValues.push_back(Value); 3082 LoadChains.push_back(Value.getValue(1)); 3083 SrcOff += VTSize; 3084 } 3085 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 3086 &LoadChains[0], LoadChains.size()); 3087 OutChains.clear(); 3088 for (unsigned i = 0; i < NumMemOps; i++) { 3089 MVT VT = MemOps[i]; 3090 unsigned VTSize = VT.getSizeInBits() / 8; 3091 SDValue Value, Store; 3092 3093 Store = DAG.getStore(Chain, LoadValues[i], 3094 getMemBasePlusOffset(Dst, DstOff, DAG), 3095 DstSV, DstSVOff + DstOff, false, DstAlign); 3096 OutChains.push_back(Store); 3097 DstOff += VTSize; 3098 } 3099 3100 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3101 &OutChains[0], OutChains.size()); 3102} 3103 3104static SDValue getMemsetStores(SelectionDAG &DAG, 3105 SDValue Chain, SDValue Dst, 3106 SDValue Src, uint64_t Size, 3107 unsigned Align, 3108 const Value *DstSV, uint64_t DstSVOff) { 3109 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3110 3111 // Expand memset to a series of load/store ops if the size operand 3112 // falls below a certain threshold. 3113 std::vector<MVT> MemOps; 3114 std::string Str; 3115 bool CopyFromStr; 3116 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3117 Size, Align, Str, CopyFromStr, DAG, TLI)) 3118 return SDValue(); 3119 3120 SmallVector<SDValue, 8> OutChains; 3121 uint64_t DstOff = 0; 3122 3123 unsigned NumMemOps = MemOps.size(); 3124 for (unsigned i = 0; i < NumMemOps; i++) { 3125 MVT VT = MemOps[i]; 3126 unsigned VTSize = VT.getSizeInBits() / 8; 3127 SDValue Value = getMemsetValue(Src, VT, DAG); 3128 SDValue Store = DAG.getStore(Chain, Value, 3129 getMemBasePlusOffset(Dst, DstOff, DAG), 3130 DstSV, DstSVOff + DstOff); 3131 OutChains.push_back(Store); 3132 DstOff += VTSize; 3133 } 3134 3135 return DAG.getNode(ISD::TokenFactor, MVT::Other, 3136 &OutChains[0], OutChains.size()); 3137} 3138 3139SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst, 3140 SDValue Src, SDValue Size, 3141 unsigned Align, bool AlwaysInline, 3142 const Value *DstSV, uint64_t DstSVOff, 3143 const Value *SrcSV, uint64_t SrcSVOff) { 3144 3145 // Check to see if we should lower the memcpy to loads and stores first. 3146 // For cases within the target-specified limits, this is the best choice. 3147 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3148 if (ConstantSize) { 3149 // Memcpy with size zero? Just return the original chain. 3150 if (ConstantSize->isNullValue()) 3151 return Chain; 3152 3153 SDValue Result = 3154 getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3155 ConstantSize->getZExtValue(), 3156 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3157 if (Result.getNode()) 3158 return Result; 3159 } 3160 3161 // Then check to see if we should lower the memcpy with target-specific 3162 // code. If the target chooses to do this, this is the next best. 3163 SDValue Result = 3164 TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align, 3165 AlwaysInline, 3166 DstSV, DstSVOff, SrcSV, SrcSVOff); 3167 if (Result.getNode()) 3168 return Result; 3169 3170 // If we really need inline code and the target declined to provide it, 3171 // use a (potentially long) sequence of loads and stores. 3172 if (AlwaysInline) { 3173 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3174 return getMemcpyLoadsAndStores(*this, Chain, Dst, Src, 3175 ConstantSize->getZExtValue(), Align, true, 3176 DstSV, DstSVOff, SrcSV, SrcSVOff); 3177 } 3178 3179 // Emit a library call. 3180 TargetLowering::ArgListTy Args; 3181 TargetLowering::ArgListEntry Entry; 3182 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3183 Entry.Node = Dst; Args.push_back(Entry); 3184 Entry.Node = Src; Args.push_back(Entry); 3185 Entry.Node = Size; Args.push_back(Entry); 3186 std::pair<SDValue,SDValue> CallResult = 3187 TLI.LowerCallTo(Chain, Type::VoidTy, 3188 false, false, false, false, CallingConv::C, false, 3189 getExternalSymbol("memcpy", TLI.getPointerTy()), 3190 Args, *this); 3191 return CallResult.second; 3192} 3193 3194SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst, 3195 SDValue Src, SDValue Size, 3196 unsigned Align, 3197 const Value *DstSV, uint64_t DstSVOff, 3198 const Value *SrcSV, uint64_t SrcSVOff) { 3199 3200 // Check to see if we should lower the memmove to loads and stores first. 3201 // For cases within the target-specified limits, this is the best choice. 3202 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3203 if (ConstantSize) { 3204 // Memmove with size zero? Just return the original chain. 3205 if (ConstantSize->isNullValue()) 3206 return Chain; 3207 3208 SDValue Result = 3209 getMemmoveLoadsAndStores(*this, Chain, Dst, Src, 3210 ConstantSize->getZExtValue(), 3211 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3212 if (Result.getNode()) 3213 return Result; 3214 } 3215 3216 // Then check to see if we should lower the memmove with target-specific 3217 // code. If the target chooses to do this, this is the next best. 3218 SDValue Result = 3219 TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align, 3220 DstSV, DstSVOff, SrcSV, SrcSVOff); 3221 if (Result.getNode()) 3222 return Result; 3223 3224 // Emit a library call. 3225 TargetLowering::ArgListTy Args; 3226 TargetLowering::ArgListEntry Entry; 3227 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3228 Entry.Node = Dst; Args.push_back(Entry); 3229 Entry.Node = Src; Args.push_back(Entry); 3230 Entry.Node = Size; Args.push_back(Entry); 3231 std::pair<SDValue,SDValue> CallResult = 3232 TLI.LowerCallTo(Chain, Type::VoidTy, 3233 false, false, false, false, CallingConv::C, false, 3234 getExternalSymbol("memmove", TLI.getPointerTy()), 3235 Args, *this); 3236 return CallResult.second; 3237} 3238 3239SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst, 3240 SDValue Src, SDValue Size, 3241 unsigned Align, 3242 const Value *DstSV, uint64_t DstSVOff) { 3243 3244 // Check to see if we should lower the memset to stores first. 3245 // For cases within the target-specified limits, this is the best choice. 3246 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3247 if (ConstantSize) { 3248 // Memset with size zero? Just return the original chain. 3249 if (ConstantSize->isNullValue()) 3250 return Chain; 3251 3252 SDValue Result = 3253 getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getZExtValue(), 3254 Align, DstSV, DstSVOff); 3255 if (Result.getNode()) 3256 return Result; 3257 } 3258 3259 // Then check to see if we should lower the memset with target-specific 3260 // code. If the target chooses to do this, this is the next best. 3261 SDValue Result = 3262 TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align, 3263 DstSV, DstSVOff); 3264 if (Result.getNode()) 3265 return Result; 3266 3267 // Emit a library call. 3268 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3269 TargetLowering::ArgListTy Args; 3270 TargetLowering::ArgListEntry Entry; 3271 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3272 Args.push_back(Entry); 3273 // Extend or truncate the argument to be an i32 value for the call. 3274 if (Src.getValueType().bitsGT(MVT::i32)) 3275 Src = getNode(ISD::TRUNCATE, MVT::i32, Src); 3276 else 3277 Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src); 3278 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3279 Args.push_back(Entry); 3280 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3281 Args.push_back(Entry); 3282 std::pair<SDValue,SDValue> CallResult = 3283 TLI.LowerCallTo(Chain, Type::VoidTy, 3284 false, false, false, false, CallingConv::C, false, 3285 getExternalSymbol("memset", TLI.getPointerTy()), 3286 Args, *this); 3287 return CallResult.second; 3288} 3289 3290SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3291 SDValue Ptr, SDValue Cmp, 3292 SDValue Swp, const Value* PtrVal, 3293 unsigned Alignment) { 3294 assert((Opcode == ISD::ATOMIC_CMP_SWAP_8 || 3295 Opcode == ISD::ATOMIC_CMP_SWAP_16 || 3296 Opcode == ISD::ATOMIC_CMP_SWAP_32 || 3297 Opcode == ISD::ATOMIC_CMP_SWAP_64) && "Invalid Atomic Op"); 3298 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3299 3300 MVT VT = Cmp.getValueType(); 3301 3302 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3303 Alignment = getMVTAlignment(VT); 3304 3305 SDVTList VTs = getVTList(VT, MVT::Other); 3306 FoldingSetNodeID ID; 3307 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3308 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3309 void* IP = 0; 3310 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3311 return SDValue(E, 0); 3312 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3313 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3314 CSEMap.InsertNode(N, IP); 3315 AllNodes.push_back(N); 3316 return SDValue(N, 0); 3317} 3318 3319SDValue SelectionDAG::getAtomic(unsigned Opcode, SDValue Chain, 3320 SDValue Ptr, SDValue Val, 3321 const Value* PtrVal, 3322 unsigned Alignment) { 3323 assert((Opcode == ISD::ATOMIC_LOAD_ADD_8 || 3324 Opcode == ISD::ATOMIC_LOAD_SUB_8 || 3325 Opcode == ISD::ATOMIC_LOAD_AND_8 || 3326 Opcode == ISD::ATOMIC_LOAD_OR_8 || 3327 Opcode == ISD::ATOMIC_LOAD_XOR_8 || 3328 Opcode == ISD::ATOMIC_LOAD_NAND_8 || 3329 Opcode == ISD::ATOMIC_LOAD_MIN_8 || 3330 Opcode == ISD::ATOMIC_LOAD_MAX_8 || 3331 Opcode == ISD::ATOMIC_LOAD_UMIN_8 || 3332 Opcode == ISD::ATOMIC_LOAD_UMAX_8 || 3333 Opcode == ISD::ATOMIC_SWAP_8 || 3334 Opcode == ISD::ATOMIC_LOAD_ADD_16 || 3335 Opcode == ISD::ATOMIC_LOAD_SUB_16 || 3336 Opcode == ISD::ATOMIC_LOAD_AND_16 || 3337 Opcode == ISD::ATOMIC_LOAD_OR_16 || 3338 Opcode == ISD::ATOMIC_LOAD_XOR_16 || 3339 Opcode == ISD::ATOMIC_LOAD_NAND_16 || 3340 Opcode == ISD::ATOMIC_LOAD_MIN_16 || 3341 Opcode == ISD::ATOMIC_LOAD_MAX_16 || 3342 Opcode == ISD::ATOMIC_LOAD_UMIN_16 || 3343 Opcode == ISD::ATOMIC_LOAD_UMAX_16 || 3344 Opcode == ISD::ATOMIC_SWAP_16 || 3345 Opcode == ISD::ATOMIC_LOAD_ADD_32 || 3346 Opcode == ISD::ATOMIC_LOAD_SUB_32 || 3347 Opcode == ISD::ATOMIC_LOAD_AND_32 || 3348 Opcode == ISD::ATOMIC_LOAD_OR_32 || 3349 Opcode == ISD::ATOMIC_LOAD_XOR_32 || 3350 Opcode == ISD::ATOMIC_LOAD_NAND_32 || 3351 Opcode == ISD::ATOMIC_LOAD_MIN_32 || 3352 Opcode == ISD::ATOMIC_LOAD_MAX_32 || 3353 Opcode == ISD::ATOMIC_LOAD_UMIN_32 || 3354 Opcode == ISD::ATOMIC_LOAD_UMAX_32 || 3355 Opcode == ISD::ATOMIC_SWAP_32 || 3356 Opcode == ISD::ATOMIC_LOAD_ADD_64 || 3357 Opcode == ISD::ATOMIC_LOAD_SUB_64 || 3358 Opcode == ISD::ATOMIC_LOAD_AND_64 || 3359 Opcode == ISD::ATOMIC_LOAD_OR_64 || 3360 Opcode == ISD::ATOMIC_LOAD_XOR_64 || 3361 Opcode == ISD::ATOMIC_LOAD_NAND_64 || 3362 Opcode == ISD::ATOMIC_LOAD_MIN_64 || 3363 Opcode == ISD::ATOMIC_LOAD_MAX_64 || 3364 Opcode == ISD::ATOMIC_LOAD_UMIN_64 || 3365 Opcode == ISD::ATOMIC_LOAD_UMAX_64 || 3366 Opcode == ISD::ATOMIC_SWAP_64) && "Invalid Atomic Op"); 3367 3368 MVT VT = Val.getValueType(); 3369 3370 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3371 Alignment = getMVTAlignment(VT); 3372 3373 SDVTList VTs = getVTList(VT, MVT::Other); 3374 FoldingSetNodeID ID; 3375 SDValue Ops[] = {Chain, Ptr, Val}; 3376 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3377 void* IP = 0; 3378 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3379 return SDValue(E, 0); 3380 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3381 new (N) AtomicSDNode(Opcode, VTs, Chain, Ptr, Val, PtrVal, Alignment); 3382 CSEMap.InsertNode(N, IP); 3383 AllNodes.push_back(N); 3384 return SDValue(N, 0); 3385} 3386 3387/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3388/// Allowed to return something different (and simpler) if Simplify is true. 3389SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps) { 3390 if (NumOps == 1) 3391 return Ops[0]; 3392 3393 SmallVector<MVT, 4> VTs; 3394 VTs.reserve(NumOps); 3395 for (unsigned i = 0; i < NumOps; ++i) 3396 VTs.push_back(Ops[i].getValueType()); 3397 return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps); 3398} 3399 3400SDValue 3401SelectionDAG::getMemIntrinsicNode(unsigned Opcode, 3402 const MVT *VTs, unsigned NumVTs, 3403 const SDValue *Ops, unsigned NumOps, 3404 MVT MemVT, const Value *srcValue, int SVOff, 3405 unsigned Align, bool Vol, 3406 bool ReadMem, bool WriteMem) { 3407 return getMemIntrinsicNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps, 3408 MemVT, srcValue, SVOff, Align, Vol, 3409 ReadMem, WriteMem); 3410} 3411 3412SDValue 3413SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDVTList VTList, 3414 const SDValue *Ops, unsigned NumOps, 3415 MVT MemVT, const Value *srcValue, int SVOff, 3416 unsigned Align, bool Vol, 3417 bool ReadMem, bool WriteMem) { 3418 // Memoize the node unless it returns a flag. 3419 MemIntrinsicSDNode *N; 3420 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3421 FoldingSetNodeID ID; 3422 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3423 void *IP = 0; 3424 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3425 return SDValue(E, 0); 3426 3427 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3428 new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, 3429 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3430 CSEMap.InsertNode(N, IP); 3431 } else { 3432 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3433 new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, 3434 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3435 } 3436 AllNodes.push_back(N); 3437 return SDValue(N, 0); 3438} 3439 3440SDValue 3441SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall, 3442 bool IsInreg, SDVTList VTs, 3443 const SDValue *Operands, unsigned NumOperands) { 3444 // Do not include isTailCall in the folding set profile. 3445 FoldingSetNodeID ID; 3446 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3447 ID.AddInteger(CallingConv); 3448 ID.AddInteger(IsVarArgs); 3449 void *IP = 0; 3450 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3451 // Instead of including isTailCall in the folding set, we just 3452 // set the flag of the existing node. 3453 if (!IsTailCall) 3454 cast<CallSDNode>(E)->setNotTailCall(); 3455 return SDValue(E, 0); 3456 } 3457 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3458 new (N) CallSDNode(CallingConv, IsVarArgs, IsTailCall, IsInreg, 3459 VTs, Operands, NumOperands); 3460 CSEMap.InsertNode(N, IP); 3461 AllNodes.push_back(N); 3462 return SDValue(N, 0); 3463} 3464 3465SDValue 3466SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, 3467 MVT VT, SDValue Chain, 3468 SDValue Ptr, SDValue Offset, 3469 const Value *SV, int SVOffset, MVT EVT, 3470 bool isVolatile, unsigned Alignment) { 3471 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3472 Alignment = getMVTAlignment(VT); 3473 3474 if (VT == EVT) { 3475 ExtType = ISD::NON_EXTLOAD; 3476 } else if (ExtType == ISD::NON_EXTLOAD) { 3477 assert(VT == EVT && "Non-extending load from different memory type!"); 3478 } else { 3479 // Extending load. 3480 if (VT.isVector()) 3481 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3482 "Invalid vector extload!"); 3483 else 3484 assert(EVT.bitsLT(VT) && 3485 "Should only be an extending load, not truncating!"); 3486 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3487 "Cannot sign/zero extend a FP/Vector load!"); 3488 assert(VT.isInteger() == EVT.isInteger() && 3489 "Cannot convert from FP to Int or Int -> FP!"); 3490 } 3491 3492 bool Indexed = AM != ISD::UNINDEXED; 3493 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3494 "Unindexed load with an offset!"); 3495 3496 SDVTList VTs = Indexed ? 3497 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3498 SDValue Ops[] = { Chain, Ptr, Offset }; 3499 FoldingSetNodeID ID; 3500 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3501 ID.AddInteger(AM); 3502 ID.AddInteger(ExtType); 3503 ID.AddInteger(EVT.getRawBits()); 3504 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3505 void *IP = 0; 3506 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3507 return SDValue(E, 0); 3508 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3509 new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset, 3510 Alignment, isVolatile); 3511 CSEMap.InsertNode(N, IP); 3512 AllNodes.push_back(N); 3513 return SDValue(N, 0); 3514} 3515 3516SDValue SelectionDAG::getLoad(MVT VT, 3517 SDValue Chain, SDValue Ptr, 3518 const Value *SV, int SVOffset, 3519 bool isVolatile, unsigned Alignment) { 3520 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3521 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3522 SV, SVOffset, VT, isVolatile, Alignment); 3523} 3524 3525SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT, 3526 SDValue Chain, SDValue Ptr, 3527 const Value *SV, 3528 int SVOffset, MVT EVT, 3529 bool isVolatile, unsigned Alignment) { 3530 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3531 return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef, 3532 SV, SVOffset, EVT, isVolatile, Alignment); 3533} 3534 3535SDValue 3536SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base, 3537 SDValue Offset, ISD::MemIndexedMode AM) { 3538 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3539 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3540 "Load is already a indexed load!"); 3541 return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), 3542 LD->getChain(), Base, Offset, LD->getSrcValue(), 3543 LD->getSrcValueOffset(), LD->getMemoryVT(), 3544 LD->isVolatile(), LD->getAlignment()); 3545} 3546 3547SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val, 3548 SDValue Ptr, const Value *SV, int SVOffset, 3549 bool isVolatile, unsigned Alignment) { 3550 MVT VT = Val.getValueType(); 3551 3552 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3553 Alignment = getMVTAlignment(VT); 3554 3555 SDVTList VTs = getVTList(MVT::Other); 3556 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3557 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3558 FoldingSetNodeID ID; 3559 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3560 ID.AddInteger(ISD::UNINDEXED); 3561 ID.AddInteger(false); 3562 ID.AddInteger(VT.getRawBits()); 3563 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3564 void *IP = 0; 3565 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3566 return SDValue(E, 0); 3567 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3568 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false, 3569 VT, SV, SVOffset, Alignment, isVolatile); 3570 CSEMap.InsertNode(N, IP); 3571 AllNodes.push_back(N); 3572 return SDValue(N, 0); 3573} 3574 3575SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val, 3576 SDValue Ptr, const Value *SV, 3577 int SVOffset, MVT SVT, 3578 bool isVolatile, unsigned Alignment) { 3579 MVT VT = Val.getValueType(); 3580 3581 if (VT == SVT) 3582 return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3583 3584 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3585 assert(VT.isInteger() == SVT.isInteger() && 3586 "Can't do FP-INT conversion!"); 3587 3588 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3589 Alignment = getMVTAlignment(VT); 3590 3591 SDVTList VTs = getVTList(MVT::Other); 3592 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3593 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3594 FoldingSetNodeID ID; 3595 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3596 ID.AddInteger(ISD::UNINDEXED); 3597 ID.AddInteger(1); 3598 ID.AddInteger(SVT.getRawBits()); 3599 ID.AddInteger(encodeMemSDNodeFlags(isVolatile, Alignment)); 3600 void *IP = 0; 3601 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3602 return SDValue(E, 0); 3603 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3604 new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true, 3605 SVT, SV, SVOffset, Alignment, isVolatile); 3606 CSEMap.InsertNode(N, IP); 3607 AllNodes.push_back(N); 3608 return SDValue(N, 0); 3609} 3610 3611SDValue 3612SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base, 3613 SDValue Offset, ISD::MemIndexedMode AM) { 3614 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3615 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3616 "Store is already a indexed store!"); 3617 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3618 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3619 FoldingSetNodeID ID; 3620 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3621 ID.AddInteger(AM); 3622 ID.AddInteger(ST->isTruncatingStore()); 3623 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3624 ID.AddInteger(ST->getRawFlags()); 3625 void *IP = 0; 3626 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3627 return SDValue(E, 0); 3628 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3629 new (N) StoreSDNode(Ops, VTs, AM, 3630 ST->isTruncatingStore(), ST->getMemoryVT(), 3631 ST->getSrcValue(), ST->getSrcValueOffset(), 3632 ST->getAlignment(), ST->isVolatile()); 3633 CSEMap.InsertNode(N, IP); 3634 AllNodes.push_back(N); 3635 return SDValue(N, 0); 3636} 3637 3638SDValue SelectionDAG::getVAArg(MVT VT, 3639 SDValue Chain, SDValue Ptr, 3640 SDValue SV) { 3641 SDValue Ops[] = { Chain, Ptr, SV }; 3642 return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); 3643} 3644 3645SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3646 const SDUse *Ops, unsigned NumOps) { 3647 switch (NumOps) { 3648 case 0: return getNode(Opcode, VT); 3649 case 1: return getNode(Opcode, VT, Ops[0]); 3650 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3651 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3652 default: break; 3653 } 3654 3655 // Copy from an SDUse array into an SDValue array for use with 3656 // the regular getNode logic. 3657 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3658 return getNode(Opcode, VT, &NewOps[0], NumOps); 3659} 3660 3661SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3662 const SDValue *Ops, unsigned NumOps) { 3663 switch (NumOps) { 3664 case 0: return getNode(Opcode, VT); 3665 case 1: return getNode(Opcode, VT, Ops[0]); 3666 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 3667 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 3668 default: break; 3669 } 3670 3671 switch (Opcode) { 3672 default: break; 3673 case ISD::SELECT_CC: { 3674 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3675 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3676 "LHS and RHS of condition must have same type!"); 3677 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3678 "True and False arms of SelectCC must have same type!"); 3679 assert(Ops[2].getValueType() == VT && 3680 "select_cc node must be of same type as true and false value!"); 3681 break; 3682 } 3683 case ISD::BR_CC: { 3684 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3685 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3686 "LHS/RHS of comparison should match types!"); 3687 break; 3688 } 3689 } 3690 3691 // Memoize nodes. 3692 SDNode *N; 3693 SDVTList VTs = getVTList(VT); 3694 if (VT != MVT::Flag) { 3695 FoldingSetNodeID ID; 3696 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3697 void *IP = 0; 3698 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3699 return SDValue(E, 0); 3700 N = NodeAllocator.Allocate<SDNode>(); 3701 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3702 CSEMap.InsertNode(N, IP); 3703 } else { 3704 N = NodeAllocator.Allocate<SDNode>(); 3705 new (N) SDNode(Opcode, VTs, Ops, NumOps); 3706 } 3707 AllNodes.push_back(N); 3708#ifndef NDEBUG 3709 VerifyNode(N); 3710#endif 3711 return SDValue(N, 0); 3712} 3713 3714SDValue SelectionDAG::getNode(unsigned Opcode, 3715 const std::vector<MVT> &ResultTys, 3716 const SDValue *Ops, unsigned NumOps) { 3717 return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(), 3718 Ops, NumOps); 3719} 3720 3721SDValue SelectionDAG::getNode(unsigned Opcode, 3722 const MVT *VTs, unsigned NumVTs, 3723 const SDValue *Ops, unsigned NumOps) { 3724 if (NumVTs == 1) 3725 return getNode(Opcode, VTs[0], Ops, NumOps); 3726 return getNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps); 3727} 3728 3729SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3730 const SDValue *Ops, unsigned NumOps) { 3731 if (VTList.NumVTs == 1) 3732 return getNode(Opcode, VTList.VTs[0], Ops, NumOps); 3733 3734 switch (Opcode) { 3735 // FIXME: figure out how to safely handle things like 3736 // int foo(int x) { return 1 << (x & 255); } 3737 // int bar() { return foo(256); } 3738#if 0 3739 case ISD::SRA_PARTS: 3740 case ISD::SRL_PARTS: 3741 case ISD::SHL_PARTS: 3742 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3743 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3744 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3745 else if (N3.getOpcode() == ISD::AND) 3746 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3747 // If the and is only masking out bits that cannot effect the shift, 3748 // eliminate the and. 3749 unsigned NumBits = VT.getSizeInBits()*2; 3750 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3751 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 3752 } 3753 break; 3754#endif 3755 } 3756 3757 // Memoize the node unless it returns a flag. 3758 SDNode *N; 3759 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3760 FoldingSetNodeID ID; 3761 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3762 void *IP = 0; 3763 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3764 return SDValue(E, 0); 3765 if (NumOps == 1) { 3766 N = NodeAllocator.Allocate<UnarySDNode>(); 3767 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3768 } else if (NumOps == 2) { 3769 N = NodeAllocator.Allocate<BinarySDNode>(); 3770 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3771 } else if (NumOps == 3) { 3772 N = NodeAllocator.Allocate<TernarySDNode>(); 3773 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3774 } else { 3775 N = NodeAllocator.Allocate<SDNode>(); 3776 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3777 } 3778 CSEMap.InsertNode(N, IP); 3779 } else { 3780 if (NumOps == 1) { 3781 N = NodeAllocator.Allocate<UnarySDNode>(); 3782 new (N) UnarySDNode(Opcode, VTList, Ops[0]); 3783 } else if (NumOps == 2) { 3784 N = NodeAllocator.Allocate<BinarySDNode>(); 3785 new (N) BinarySDNode(Opcode, VTList, Ops[0], Ops[1]); 3786 } else if (NumOps == 3) { 3787 N = NodeAllocator.Allocate<TernarySDNode>(); 3788 new (N) TernarySDNode(Opcode, VTList, Ops[0], Ops[1], Ops[2]); 3789 } else { 3790 N = NodeAllocator.Allocate<SDNode>(); 3791 new (N) SDNode(Opcode, VTList, Ops, NumOps); 3792 } 3793 } 3794 AllNodes.push_back(N); 3795#ifndef NDEBUG 3796 VerifyNode(N); 3797#endif 3798 return SDValue(N, 0); 3799} 3800 3801SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) { 3802 return getNode(Opcode, VTList, 0, 0); 3803} 3804 3805SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3806 SDValue N1) { 3807 SDValue Ops[] = { N1 }; 3808 return getNode(Opcode, VTList, Ops, 1); 3809} 3810 3811SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3812 SDValue N1, SDValue N2) { 3813 SDValue Ops[] = { N1, N2 }; 3814 return getNode(Opcode, VTList, Ops, 2); 3815} 3816 3817SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3818 SDValue N1, SDValue N2, SDValue N3) { 3819 SDValue Ops[] = { N1, N2, N3 }; 3820 return getNode(Opcode, VTList, Ops, 3); 3821} 3822 3823SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3824 SDValue N1, SDValue N2, SDValue N3, 3825 SDValue N4) { 3826 SDValue Ops[] = { N1, N2, N3, N4 }; 3827 return getNode(Opcode, VTList, Ops, 4); 3828} 3829 3830SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3831 SDValue N1, SDValue N2, SDValue N3, 3832 SDValue N4, SDValue N5) { 3833 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3834 return getNode(Opcode, VTList, Ops, 5); 3835} 3836 3837SDVTList SelectionDAG::getVTList(MVT VT) { 3838 return makeVTList(SDNode::getValueTypeList(VT), 1); 3839} 3840 3841SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3842 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3843 E = VTList.rend(); I != E; ++I) 3844 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3845 return *I; 3846 3847 MVT *Array = Allocator.Allocate<MVT>(2); 3848 Array[0] = VT1; 3849 Array[1] = VT2; 3850 SDVTList Result = makeVTList(Array, 2); 3851 VTList.push_back(Result); 3852 return Result; 3853} 3854 3855SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3856 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3857 E = VTList.rend(); I != E; ++I) 3858 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3859 I->VTs[2] == VT3) 3860 return *I; 3861 3862 MVT *Array = Allocator.Allocate<MVT>(3); 3863 Array[0] = VT1; 3864 Array[1] = VT2; 3865 Array[2] = VT3; 3866 SDVTList Result = makeVTList(Array, 3); 3867 VTList.push_back(Result); 3868 return Result; 3869} 3870 3871SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { 3872 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3873 E = VTList.rend(); I != E; ++I) 3874 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3875 I->VTs[2] == VT3 && I->VTs[3] == VT4) 3876 return *I; 3877 3878 MVT *Array = Allocator.Allocate<MVT>(3); 3879 Array[0] = VT1; 3880 Array[1] = VT2; 3881 Array[2] = VT3; 3882 Array[3] = VT4; 3883 SDVTList Result = makeVTList(Array, 4); 3884 VTList.push_back(Result); 3885 return Result; 3886} 3887 3888SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3889 switch (NumVTs) { 3890 case 0: assert(0 && "Cannot have nodes without results!"); 3891 case 1: return getVTList(VTs[0]); 3892 case 2: return getVTList(VTs[0], VTs[1]); 3893 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3894 default: break; 3895 } 3896 3897 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3898 E = VTList.rend(); I != E; ++I) { 3899 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3900 continue; 3901 3902 bool NoMatch = false; 3903 for (unsigned i = 2; i != NumVTs; ++i) 3904 if (VTs[i] != I->VTs[i]) { 3905 NoMatch = true; 3906 break; 3907 } 3908 if (!NoMatch) 3909 return *I; 3910 } 3911 3912 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 3913 std::copy(VTs, VTs+NumVTs, Array); 3914 SDVTList Result = makeVTList(Array, NumVTs); 3915 VTList.push_back(Result); 3916 return Result; 3917} 3918 3919 3920/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 3921/// specified operands. If the resultant node already exists in the DAG, 3922/// this does not modify the specified node, instead it returns the node that 3923/// already exists. If the resultant node does not exist in the DAG, the 3924/// input node is returned. As a degenerate case, if you specify the same 3925/// input operands as the node already has, the input node is returned. 3926SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 3927 SDNode *N = InN.getNode(); 3928 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 3929 3930 // Check to see if there is no change. 3931 if (Op == N->getOperand(0)) return InN; 3932 3933 // See if the modified node already exists. 3934 void *InsertPos = 0; 3935 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 3936 return SDValue(Existing, InN.getResNo()); 3937 3938 // Nope it doesn't. Remove the node from its current place in the maps. 3939 if (InsertPos) 3940 if (!RemoveNodeFromCSEMaps(N)) 3941 InsertPos = 0; 3942 3943 // Now we update the operands. 3944 N->OperandList[0].getVal()->removeUser(0, N); 3945 N->OperandList[0] = Op; 3946 N->OperandList[0].setUser(N); 3947 Op.getNode()->addUser(0, N); 3948 3949 // If this gets put into a CSE map, add it. 3950 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3951 return InN; 3952} 3953 3954SDValue SelectionDAG:: 3955UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 3956 SDNode *N = InN.getNode(); 3957 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 3958 3959 // Check to see if there is no change. 3960 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 3961 return InN; // No operands changed, just return the input node. 3962 3963 // See if the modified node already exists. 3964 void *InsertPos = 0; 3965 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 3966 return SDValue(Existing, InN.getResNo()); 3967 3968 // Nope it doesn't. Remove the node from its current place in the maps. 3969 if (InsertPos) 3970 if (!RemoveNodeFromCSEMaps(N)) 3971 InsertPos = 0; 3972 3973 // Now we update the operands. 3974 if (N->OperandList[0] != Op1) { 3975 N->OperandList[0].getVal()->removeUser(0, N); 3976 N->OperandList[0] = Op1; 3977 N->OperandList[0].setUser(N); 3978 Op1.getNode()->addUser(0, N); 3979 } 3980 if (N->OperandList[1] != Op2) { 3981 N->OperandList[1].getVal()->removeUser(1, N); 3982 N->OperandList[1] = Op2; 3983 N->OperandList[1].setUser(N); 3984 Op2.getNode()->addUser(1, N); 3985 } 3986 3987 // If this gets put into a CSE map, add it. 3988 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 3989 return InN; 3990} 3991 3992SDValue SelectionDAG:: 3993UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 3994 SDValue Ops[] = { Op1, Op2, Op3 }; 3995 return UpdateNodeOperands(N, Ops, 3); 3996} 3997 3998SDValue SelectionDAG:: 3999UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4000 SDValue Op3, SDValue Op4) { 4001 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 4002 return UpdateNodeOperands(N, Ops, 4); 4003} 4004 4005SDValue SelectionDAG:: 4006UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4007 SDValue Op3, SDValue Op4, SDValue Op5) { 4008 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 4009 return UpdateNodeOperands(N, Ops, 5); 4010} 4011 4012SDValue SelectionDAG:: 4013UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 4014 SDNode *N = InN.getNode(); 4015 assert(N->getNumOperands() == NumOps && 4016 "Update with wrong number of operands"); 4017 4018 // Check to see if there is no change. 4019 bool AnyChange = false; 4020 for (unsigned i = 0; i != NumOps; ++i) { 4021 if (Ops[i] != N->getOperand(i)) { 4022 AnyChange = true; 4023 break; 4024 } 4025 } 4026 4027 // No operands changed, just return the input node. 4028 if (!AnyChange) return InN; 4029 4030 // See if the modified node already exists. 4031 void *InsertPos = 0; 4032 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 4033 return SDValue(Existing, InN.getResNo()); 4034 4035 // Nope it doesn't. Remove the node from its current place in the maps. 4036 if (InsertPos) 4037 if (!RemoveNodeFromCSEMaps(N)) 4038 InsertPos = 0; 4039 4040 // Now we update the operands. 4041 for (unsigned i = 0; i != NumOps; ++i) { 4042 if (N->OperandList[i] != Ops[i]) { 4043 N->OperandList[i].getVal()->removeUser(i, N); 4044 N->OperandList[i] = Ops[i]; 4045 N->OperandList[i].setUser(N); 4046 Ops[i].getNode()->addUser(i, N); 4047 } 4048 } 4049 4050 // If this gets put into a CSE map, add it. 4051 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4052 return InN; 4053} 4054 4055/// DropOperands - Release the operands and set this node to have 4056/// zero operands. 4057void SDNode::DropOperands() { 4058 // Unlike the code in MorphNodeTo that does this, we don't need to 4059 // watch for dead nodes here. 4060 for (op_iterator I = op_begin(), E = op_end(); I != E; ++I) 4061 I->getVal()->removeUser(std::distance(op_begin(), I), this); 4062 4063 NumOperands = 0; 4064} 4065 4066/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4067/// machine opcode. 4068/// 4069SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4070 MVT VT) { 4071 SDVTList VTs = getVTList(VT); 4072 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4073} 4074 4075SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4076 MVT VT, SDValue Op1) { 4077 SDVTList VTs = getVTList(VT); 4078 SDValue Ops[] = { Op1 }; 4079 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4080} 4081 4082SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4083 MVT VT, SDValue Op1, 4084 SDValue Op2) { 4085 SDVTList VTs = getVTList(VT); 4086 SDValue Ops[] = { Op1, Op2 }; 4087 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4088} 4089 4090SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4091 MVT VT, SDValue Op1, 4092 SDValue Op2, SDValue Op3) { 4093 SDVTList VTs = getVTList(VT); 4094 SDValue Ops[] = { Op1, Op2, Op3 }; 4095 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4096} 4097 4098SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4099 MVT VT, const SDValue *Ops, 4100 unsigned NumOps) { 4101 SDVTList VTs = getVTList(VT); 4102 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4103} 4104 4105SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4106 MVT VT1, MVT VT2, const SDValue *Ops, 4107 unsigned NumOps) { 4108 SDVTList VTs = getVTList(VT1, VT2); 4109 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4110} 4111 4112SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4113 MVT VT1, MVT VT2) { 4114 SDVTList VTs = getVTList(VT1, VT2); 4115 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4116} 4117 4118SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4119 MVT VT1, MVT VT2, MVT VT3, 4120 const SDValue *Ops, unsigned NumOps) { 4121 SDVTList VTs = getVTList(VT1, VT2, VT3); 4122 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4123} 4124 4125SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4126 MVT VT1, MVT VT2, MVT VT3, MVT VT4, 4127 const SDValue *Ops, unsigned NumOps) { 4128 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4129 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4130} 4131 4132SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4133 MVT VT1, MVT VT2, 4134 SDValue Op1) { 4135 SDVTList VTs = getVTList(VT1, VT2); 4136 SDValue Ops[] = { Op1 }; 4137 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4138} 4139 4140SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4141 MVT VT1, MVT VT2, 4142 SDValue Op1, SDValue Op2) { 4143 SDVTList VTs = getVTList(VT1, VT2); 4144 SDValue Ops[] = { Op1, Op2 }; 4145 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4146} 4147 4148SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4149 MVT VT1, MVT VT2, 4150 SDValue Op1, SDValue Op2, 4151 SDValue Op3) { 4152 SDVTList VTs = getVTList(VT1, VT2); 4153 SDValue Ops[] = { Op1, Op2, Op3 }; 4154 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4155} 4156 4157SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4158 MVT VT1, MVT VT2, MVT VT3, 4159 SDValue Op1, SDValue Op2, 4160 SDValue Op3) { 4161 SDVTList VTs = getVTList(VT1, VT2, VT3); 4162 SDValue Ops[] = { Op1, Op2, Op3 }; 4163 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4164} 4165 4166SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4167 SDVTList VTs, const SDValue *Ops, 4168 unsigned NumOps) { 4169 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4170} 4171 4172SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4173 MVT VT) { 4174 SDVTList VTs = getVTList(VT); 4175 return MorphNodeTo(N, Opc, VTs, 0, 0); 4176} 4177 4178SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4179 MVT VT, SDValue Op1) { 4180 SDVTList VTs = getVTList(VT); 4181 SDValue Ops[] = { Op1 }; 4182 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4183} 4184 4185SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4186 MVT VT, SDValue Op1, 4187 SDValue Op2) { 4188 SDVTList VTs = getVTList(VT); 4189 SDValue Ops[] = { Op1, Op2 }; 4190 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4191} 4192 4193SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4194 MVT VT, SDValue Op1, 4195 SDValue Op2, SDValue Op3) { 4196 SDVTList VTs = getVTList(VT); 4197 SDValue Ops[] = { Op1, Op2, Op3 }; 4198 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4199} 4200 4201SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4202 MVT VT, const SDValue *Ops, 4203 unsigned NumOps) { 4204 SDVTList VTs = getVTList(VT); 4205 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4206} 4207 4208SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4209 MVT VT1, MVT VT2, const SDValue *Ops, 4210 unsigned NumOps) { 4211 SDVTList VTs = getVTList(VT1, VT2); 4212 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4213} 4214 4215SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4216 MVT VT1, MVT VT2) { 4217 SDVTList VTs = getVTList(VT1, VT2); 4218 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4219} 4220 4221SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4222 MVT VT1, MVT VT2, MVT VT3, 4223 const SDValue *Ops, unsigned NumOps) { 4224 SDVTList VTs = getVTList(VT1, VT2, VT3); 4225 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4226} 4227 4228SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4229 MVT VT1, MVT VT2, 4230 SDValue Op1) { 4231 SDVTList VTs = getVTList(VT1, VT2); 4232 SDValue Ops[] = { Op1 }; 4233 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4234} 4235 4236SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4237 MVT VT1, MVT VT2, 4238 SDValue Op1, SDValue Op2) { 4239 SDVTList VTs = getVTList(VT1, VT2); 4240 SDValue Ops[] = { Op1, Op2 }; 4241 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4242} 4243 4244SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4245 MVT VT1, MVT VT2, 4246 SDValue Op1, SDValue Op2, 4247 SDValue Op3) { 4248 SDVTList VTs = getVTList(VT1, VT2); 4249 SDValue Ops[] = { Op1, Op2, Op3 }; 4250 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4251} 4252 4253/// MorphNodeTo - These *mutate* the specified node to have the specified 4254/// return type, opcode, and operands. 4255/// 4256/// Note that MorphNodeTo returns the resultant node. If there is already a 4257/// node of the specified opcode and operands, it returns that node instead of 4258/// the current one. 4259/// 4260/// Using MorphNodeTo is faster than creating a new node and swapping it in 4261/// with ReplaceAllUsesWith both because it often avoids allocating a new 4262/// node, and because it doesn't require CSE recalculation for any of 4263/// the node's users. 4264/// 4265SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4266 SDVTList VTs, const SDValue *Ops, 4267 unsigned NumOps) { 4268 // If an identical node already exists, use it. 4269 void *IP = 0; 4270 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4271 FoldingSetNodeID ID; 4272 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4273 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4274 return ON; 4275 } 4276 4277 if (!RemoveNodeFromCSEMaps(N)) 4278 IP = 0; 4279 4280 // Start the morphing. 4281 N->NodeType = Opc; 4282 N->ValueList = VTs.VTs; 4283 N->NumValues = VTs.NumVTs; 4284 4285 // Clear the operands list, updating used nodes to remove this from their 4286 // use list. Keep track of any operands that become dead as a result. 4287 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4288 for (SDNode::op_iterator B = N->op_begin(), I = B, E = N->op_end(); 4289 I != E; ++I) { 4290 SDNode *Used = I->getVal(); 4291 Used->removeUser(std::distance(B, I), N); 4292 if (Used->use_empty()) 4293 DeadNodeSet.insert(Used); 4294 } 4295 4296 // If NumOps is larger than the # of operands we currently have, reallocate 4297 // the operand list. 4298 if (NumOps > N->NumOperands) { 4299 if (N->OperandsNeedDelete) 4300 delete[] N->OperandList; 4301 4302 if (N->isMachineOpcode()) { 4303 // We're creating a final node that will live unmorphed for the 4304 // remainder of the current SelectionDAG iteration, so we can allocate 4305 // the operands directly out of a pool with no recycling metadata. 4306 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4307 N->OperandsNeedDelete = false; 4308 } else { 4309 N->OperandList = new SDUse[NumOps]; 4310 N->OperandsNeedDelete = true; 4311 } 4312 } 4313 4314 // Assign the new operands. 4315 N->NumOperands = NumOps; 4316 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4317 N->OperandList[i] = Ops[i]; 4318 N->OperandList[i].setUser(N); 4319 SDNode *ToUse = N->OperandList[i].getVal(); 4320 ToUse->addUser(i, N); 4321 } 4322 4323 // Delete any nodes that are still dead after adding the uses for the 4324 // new operands. 4325 SmallVector<SDNode *, 16> DeadNodes; 4326 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4327 E = DeadNodeSet.end(); I != E; ++I) 4328 if ((*I)->use_empty()) 4329 DeadNodes.push_back(*I); 4330 RemoveDeadNodes(DeadNodes); 4331 4332 if (IP) 4333 CSEMap.InsertNode(N, IP); // Memoize the new node. 4334 return N; 4335} 4336 4337 4338/// getTargetNode - These are used for target selectors to create a new node 4339/// with specified return type(s), target opcode, and operands. 4340/// 4341/// Note that getTargetNode returns the resultant node. If there is already a 4342/// node of the specified opcode and operands, it returns that node instead of 4343/// the current one. 4344SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { 4345 return getNode(~Opcode, VT).getNode(); 4346} 4347SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) { 4348 return getNode(~Opcode, VT, Op1).getNode(); 4349} 4350SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4351 SDValue Op1, SDValue Op2) { 4352 return getNode(~Opcode, VT, Op1, Op2).getNode(); 4353} 4354SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4355 SDValue Op1, SDValue Op2, 4356 SDValue Op3) { 4357 return getNode(~Opcode, VT, Op1, Op2, Op3).getNode(); 4358} 4359SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4360 const SDValue *Ops, unsigned NumOps) { 4361 return getNode(~Opcode, VT, Ops, NumOps).getNode(); 4362} 4363SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { 4364 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4365 SDValue Op; 4366 return getNode(~Opcode, VTs, 2, &Op, 0).getNode(); 4367} 4368SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4369 MVT VT2, SDValue Op1) { 4370 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4371 return getNode(~Opcode, VTs, 2, &Op1, 1).getNode(); 4372} 4373SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4374 MVT VT2, SDValue Op1, 4375 SDValue Op2) { 4376 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4377 SDValue Ops[] = { Op1, Op2 }; 4378 return getNode(~Opcode, VTs, 2, Ops, 2).getNode(); 4379} 4380SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4381 MVT VT2, SDValue Op1, 4382 SDValue Op2, SDValue Op3) { 4383 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4384 SDValue Ops[] = { Op1, Op2, Op3 }; 4385 return getNode(~Opcode, VTs, 2, Ops, 3).getNode(); 4386} 4387SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, 4388 const SDValue *Ops, unsigned NumOps) { 4389 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4390 return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode(); 4391} 4392SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4393 SDValue Op1, SDValue Op2) { 4394 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4395 SDValue Ops[] = { Op1, Op2 }; 4396 return getNode(~Opcode, VTs, 3, Ops, 2).getNode(); 4397} 4398SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4399 SDValue Op1, SDValue Op2, 4400 SDValue Op3) { 4401 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4402 SDValue Ops[] = { Op1, Op2, Op3 }; 4403 return getNode(~Opcode, VTs, 3, Ops, 3).getNode(); 4404} 4405SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, 4406 const SDValue *Ops, unsigned NumOps) { 4407 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4408 return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode(); 4409} 4410SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4411 MVT VT2, MVT VT3, MVT VT4, 4412 const SDValue *Ops, unsigned NumOps) { 4413 std::vector<MVT> VTList; 4414 VTList.push_back(VT1); 4415 VTList.push_back(VT2); 4416 VTList.push_back(VT3); 4417 VTList.push_back(VT4); 4418 const MVT *VTs = getNodeValueTypes(VTList); 4419 return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode(); 4420} 4421SDNode *SelectionDAG::getTargetNode(unsigned Opcode, 4422 const std::vector<MVT> &ResultTys, 4423 const SDValue *Ops, unsigned NumOps) { 4424 const MVT *VTs = getNodeValueTypes(ResultTys); 4425 return getNode(~Opcode, VTs, ResultTys.size(), 4426 Ops, NumOps).getNode(); 4427} 4428 4429/// getNodeIfExists - Get the specified node if it's already available, or 4430/// else return NULL. 4431SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4432 const SDValue *Ops, unsigned NumOps) { 4433 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4434 FoldingSetNodeID ID; 4435 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4436 void *IP = 0; 4437 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4438 return E; 4439 } 4440 return NULL; 4441} 4442 4443 4444/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4445/// This can cause recursive merging of nodes in the DAG. 4446/// 4447/// This version assumes From has a single result value. 4448/// 4449void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4450 DAGUpdateListener *UpdateListener) { 4451 SDNode *From = FromN.getNode(); 4452 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4453 "Cannot replace with this method!"); 4454 assert(From != To.getNode() && "Cannot replace uses of with self"); 4455 4456 while (!From->use_empty()) { 4457 SDNode::use_iterator UI = From->use_begin(); 4458 SDNode *U = *UI; 4459 4460 // This node is about to morph, remove its old self from the CSE maps. 4461 RemoveNodeFromCSEMaps(U); 4462 int operandNum = 0; 4463 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4464 I != E; ++I, ++operandNum) 4465 if (I->getVal() == From) { 4466 From->removeUser(operandNum, U); 4467 *I = To; 4468 I->setUser(U); 4469 To.getNode()->addUser(operandNum, U); 4470 } 4471 4472 // Now that we have modified U, add it back to the CSE maps. If it already 4473 // exists there, recursively merge the results together. 4474 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4475 ReplaceAllUsesWith(U, Existing, UpdateListener); 4476 // U is now dead. Inform the listener if it exists and delete it. 4477 if (UpdateListener) 4478 UpdateListener->NodeDeleted(U, Existing); 4479 DeleteNodeNotInCSEMaps(U); 4480 } else { 4481 // If the node doesn't already exist, we updated it. Inform a listener if 4482 // it exists. 4483 if (UpdateListener) 4484 UpdateListener->NodeUpdated(U); 4485 } 4486 } 4487} 4488 4489/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4490/// This can cause recursive merging of nodes in the DAG. 4491/// 4492/// This version assumes From/To have matching types and numbers of result 4493/// values. 4494/// 4495void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4496 DAGUpdateListener *UpdateListener) { 4497 assert(From->getVTList().VTs == To->getVTList().VTs && 4498 From->getNumValues() == To->getNumValues() && 4499 "Cannot use this version of ReplaceAllUsesWith!"); 4500 4501 // Handle the trivial case. 4502 if (From == To) 4503 return; 4504 4505 while (!From->use_empty()) { 4506 SDNode::use_iterator UI = From->use_begin(); 4507 SDNode *U = *UI; 4508 4509 // This node is about to morph, remove its old self from the CSE maps. 4510 RemoveNodeFromCSEMaps(U); 4511 int operandNum = 0; 4512 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4513 I != E; ++I, ++operandNum) 4514 if (I->getVal() == From) { 4515 From->removeUser(operandNum, U); 4516 I->getSDValue().setNode(To); 4517 To->addUser(operandNum, U); 4518 } 4519 4520 // Now that we have modified U, add it back to the CSE maps. If it already 4521 // exists there, recursively merge the results together. 4522 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4523 ReplaceAllUsesWith(U, Existing, UpdateListener); 4524 // U is now dead. Inform the listener if it exists and delete it. 4525 if (UpdateListener) 4526 UpdateListener->NodeDeleted(U, Existing); 4527 DeleteNodeNotInCSEMaps(U); 4528 } else { 4529 // If the node doesn't already exist, we updated it. Inform a listener if 4530 // it exists. 4531 if (UpdateListener) 4532 UpdateListener->NodeUpdated(U); 4533 } 4534 } 4535} 4536 4537/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4538/// This can cause recursive merging of nodes in the DAG. 4539/// 4540/// This version can replace From with any result values. To must match the 4541/// number and types of values returned by From. 4542void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4543 const SDValue *To, 4544 DAGUpdateListener *UpdateListener) { 4545 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4546 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4547 4548 while (!From->use_empty()) { 4549 SDNode::use_iterator UI = From->use_begin(); 4550 SDNode *U = *UI; 4551 4552 // This node is about to morph, remove its old self from the CSE maps. 4553 RemoveNodeFromCSEMaps(U); 4554 int operandNum = 0; 4555 for (SDNode::op_iterator I = U->op_begin(), E = U->op_end(); 4556 I != E; ++I, ++operandNum) 4557 if (I->getVal() == From) { 4558 const SDValue &ToOp = To[I->getSDValue().getResNo()]; 4559 From->removeUser(operandNum, U); 4560 *I = ToOp; 4561 I->setUser(U); 4562 ToOp.getNode()->addUser(operandNum, U); 4563 } 4564 4565 // Now that we have modified U, add it back to the CSE maps. If it already 4566 // exists there, recursively merge the results together. 4567 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) { 4568 ReplaceAllUsesWith(U, Existing, UpdateListener); 4569 // U is now dead. Inform the listener if it exists and delete it. 4570 if (UpdateListener) 4571 UpdateListener->NodeDeleted(U, Existing); 4572 DeleteNodeNotInCSEMaps(U); 4573 } else { 4574 // If the node doesn't already exist, we updated it. Inform a listener if 4575 // it exists. 4576 if (UpdateListener) 4577 UpdateListener->NodeUpdated(U); 4578 } 4579 } 4580} 4581 4582/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4583/// uses of other values produced by From.getVal() alone. The Deleted vector is 4584/// handled the same way as for ReplaceAllUsesWith. 4585void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4586 DAGUpdateListener *UpdateListener){ 4587 // Handle the really simple, really trivial case efficiently. 4588 if (From == To) return; 4589 4590 // Handle the simple, trivial, case efficiently. 4591 if (From.getNode()->getNumValues() == 1) { 4592 ReplaceAllUsesWith(From, To, UpdateListener); 4593 return; 4594 } 4595 4596 // Get all of the users of From.getNode(). We want these in a nice, 4597 // deterministically ordered and uniqued set, so we use a SmallSetVector. 4598 SmallSetVector<SDNode*, 16> Users(From.getNode()->use_begin(), From.getNode()->use_end()); 4599 4600 while (!Users.empty()) { 4601 // We know that this user uses some value of From. If it is the right 4602 // value, update it. 4603 SDNode *User = Users.back(); 4604 Users.pop_back(); 4605 4606 // Scan for an operand that matches From. 4607 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4608 for (; Op != E; ++Op) 4609 if (*Op == From) break; 4610 4611 // If there are no matches, the user must use some other result of From. 4612 if (Op == E) continue; 4613 4614 // Okay, we know this user needs to be updated. Remove its old self 4615 // from the CSE maps. 4616 RemoveNodeFromCSEMaps(User); 4617 4618 // Update all operands that match "From" in case there are multiple uses. 4619 for (; Op != E; ++Op) { 4620 if (*Op == From) { 4621 From.getNode()->removeUser(Op-User->op_begin(), User); 4622 *Op = To; 4623 Op->setUser(User); 4624 To.getNode()->addUser(Op-User->op_begin(), User); 4625 } 4626 } 4627 4628 // Now that we have modified User, add it back to the CSE maps. If it 4629 // already exists there, recursively merge the results together. 4630 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4631 if (!Existing) { 4632 if (UpdateListener) UpdateListener->NodeUpdated(User); 4633 continue; // Continue on to next user. 4634 } 4635 4636 // If there was already an existing matching node, use ReplaceAllUsesWith 4637 // to replace the dead one with the existing one. This can cause 4638 // recursive merging of other unrelated nodes down the line. 4639 ReplaceAllUsesWith(User, Existing, UpdateListener); 4640 4641 // User is now dead. Notify a listener if present. 4642 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4643 DeleteNodeNotInCSEMaps(User); 4644 } 4645} 4646 4647/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4648/// uses of other values produced by From.getVal() alone. The same value may 4649/// appear in both the From and To list. The Deleted vector is 4650/// handled the same way as for ReplaceAllUsesWith. 4651void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4652 const SDValue *To, 4653 unsigned Num, 4654 DAGUpdateListener *UpdateListener){ 4655 // Handle the simple, trivial case efficiently. 4656 if (Num == 1) 4657 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4658 4659 SmallVector<std::pair<SDNode *, unsigned>, 16> Users; 4660 for (unsigned i = 0; i != Num; ++i) 4661 for (SDNode::use_iterator UI = From[i].getNode()->use_begin(), 4662 E = From[i].getNode()->use_end(); UI != E; ++UI) 4663 Users.push_back(std::make_pair(*UI, i)); 4664 4665 while (!Users.empty()) { 4666 // We know that this user uses some value of From. If it is the right 4667 // value, update it. 4668 SDNode *User = Users.back().first; 4669 unsigned i = Users.back().second; 4670 Users.pop_back(); 4671 4672 // Scan for an operand that matches From. 4673 SDNode::op_iterator Op = User->op_begin(), E = User->op_end(); 4674 for (; Op != E; ++Op) 4675 if (*Op == From[i]) break; 4676 4677 // If there are no matches, the user must use some other result of From. 4678 if (Op == E) continue; 4679 4680 // Okay, we know this user needs to be updated. Remove its old self 4681 // from the CSE maps. 4682 RemoveNodeFromCSEMaps(User); 4683 4684 // Update all operands that match "From" in case there are multiple uses. 4685 for (; Op != E; ++Op) { 4686 if (*Op == From[i]) { 4687 From[i].getNode()->removeUser(Op-User->op_begin(), User); 4688 *Op = To[i]; 4689 Op->setUser(User); 4690 To[i].getNode()->addUser(Op-User->op_begin(), User); 4691 } 4692 } 4693 4694 // Now that we have modified User, add it back to the CSE maps. If it 4695 // already exists there, recursively merge the results together. 4696 SDNode *Existing = AddNonLeafNodeToCSEMaps(User); 4697 if (!Existing) { 4698 if (UpdateListener) UpdateListener->NodeUpdated(User); 4699 continue; // Continue on to next user. 4700 } 4701 4702 // If there was already an existing matching node, use ReplaceAllUsesWith 4703 // to replace the dead one with the existing one. This can cause 4704 // recursive merging of other unrelated nodes down the line. 4705 ReplaceAllUsesWith(User, Existing, UpdateListener); 4706 4707 // User is now dead. Notify a listener if present. 4708 if (UpdateListener) UpdateListener->NodeDeleted(User, Existing); 4709 DeleteNodeNotInCSEMaps(User); 4710 } 4711} 4712 4713/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4714/// based on their topological order. It returns the maximum id and a vector 4715/// of the SDNodes* in assigned order by reference. 4716unsigned SelectionDAG::AssignTopologicalOrder() { 4717 4718 unsigned DAGSize = 0; 4719 4720 // SortedPos tracks the progress of the algorithm. Nodes before it are 4721 // sorted, nodes after it are unsorted. When the algorithm completes 4722 // it is at the end of the list. 4723 allnodes_iterator SortedPos = allnodes_begin(); 4724 4725 // Visit all the nodes. Move nodes with no operands to the front of 4726 // the list immediately. Annotate nodes that do have operands with their 4727 // operand count. Before we do this, the Node Id fields of the nodes 4728 // may contain arbitrary values. After, the Node Id fields for nodes 4729 // before SortedPos will contain the topological sort index, and the 4730 // Node Id fields for nodes At SortedPos and after will contain the 4731 // count of outstanding operands. 4732 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4733 SDNode *N = I++; 4734 unsigned Degree = N->getNumOperands(); 4735 if (Degree == 0) { 4736 // A node with no uses, add it to the result array immediately. 4737 N->setNodeId(DAGSize++); 4738 allnodes_iterator Q = N; 4739 if (Q != SortedPos) 4740 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4741 ++SortedPos; 4742 } else { 4743 // Temporarily use the Node Id as scratch space for the degree count. 4744 N->setNodeId(Degree); 4745 } 4746 } 4747 4748 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4749 // such that by the time the end is reached all nodes will be sorted. 4750 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4751 SDNode *N = I; 4752 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4753 UI != UE; ++UI) { 4754 SDNode *P = *UI; 4755 unsigned Degree = P->getNodeId(); 4756 --Degree; 4757 if (Degree == 0) { 4758 // All of P's operands are sorted, so P may sorted now. 4759 P->setNodeId(DAGSize++); 4760 if (P != SortedPos) 4761 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4762 ++SortedPos; 4763 } else { 4764 // Update P's outstanding operand count. 4765 P->setNodeId(Degree); 4766 } 4767 } 4768 } 4769 4770 assert(SortedPos == AllNodes.end() && 4771 "Topological sort incomplete!"); 4772 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4773 "First node in topological sort is not the entry token!"); 4774 assert(AllNodes.front().getNodeId() == 0 && 4775 "First node in topological sort has non-zero id!"); 4776 assert(AllNodes.front().getNumOperands() == 0 && 4777 "First node in topological sort has operands!"); 4778 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4779 "Last node in topologic sort has unexpected id!"); 4780 assert(AllNodes.back().use_empty() && 4781 "Last node in topologic sort has users!"); 4782 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 4783 return DAGSize; 4784} 4785 4786 4787 4788//===----------------------------------------------------------------------===// 4789// SDNode Class 4790//===----------------------------------------------------------------------===// 4791 4792// Out-of-line virtual method to give class a home. 4793void SDNode::ANCHOR() {} 4794void UnarySDNode::ANCHOR() {} 4795void BinarySDNode::ANCHOR() {} 4796void TernarySDNode::ANCHOR() {} 4797void HandleSDNode::ANCHOR() {} 4798void ConstantSDNode::ANCHOR() {} 4799void ConstantFPSDNode::ANCHOR() {} 4800void GlobalAddressSDNode::ANCHOR() {} 4801void FrameIndexSDNode::ANCHOR() {} 4802void JumpTableSDNode::ANCHOR() {} 4803void ConstantPoolSDNode::ANCHOR() {} 4804void BasicBlockSDNode::ANCHOR() {} 4805void SrcValueSDNode::ANCHOR() {} 4806void MemOperandSDNode::ANCHOR() {} 4807void RegisterSDNode::ANCHOR() {} 4808void DbgStopPointSDNode::ANCHOR() {} 4809void LabelSDNode::ANCHOR() {} 4810void ExternalSymbolSDNode::ANCHOR() {} 4811void CondCodeSDNode::ANCHOR() {} 4812void ARG_FLAGSSDNode::ANCHOR() {} 4813void VTSDNode::ANCHOR() {} 4814void MemSDNode::ANCHOR() {} 4815void LoadSDNode::ANCHOR() {} 4816void StoreSDNode::ANCHOR() {} 4817void AtomicSDNode::ANCHOR() {} 4818void MemIntrinsicSDNode::ANCHOR() {} 4819void CallSDNode::ANCHOR() {} 4820void CvtRndSatSDNode::ANCHOR() {} 4821 4822HandleSDNode::~HandleSDNode() { 4823 DropOperands(); 4824} 4825 4826GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4827 MVT VT, int64_t o) 4828 : SDNode(isa<GlobalVariable>(GA) && 4829 cast<GlobalVariable>(GA)->isThreadLocal() ? 4830 // Thread Local 4831 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4832 // Non Thread Local 4833 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4834 getSDVTList(VT)), Offset(o) { 4835 TheGlobal = const_cast<GlobalValue*>(GA); 4836} 4837 4838MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt, 4839 const Value *srcValue, int SVO, 4840 unsigned alignment, bool vol) 4841 : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4842 Flags(encodeMemSDNodeFlags(vol, alignment)) { 4843 4844 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4845 assert(getAlignment() == alignment && "Alignment representation error!"); 4846 assert(isVolatile() == vol && "Volatile representation error!"); 4847} 4848 4849MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, 4850 unsigned NumOps, MVT memvt, const Value *srcValue, 4851 int SVO, unsigned alignment, bool vol) 4852 : SDNode(Opc, VTs, Ops, NumOps), 4853 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO), 4854 Flags(vol | ((Log2_32(alignment) + 1) << 1)) { 4855 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4856 assert(getAlignment() == alignment && "Alignment representation error!"); 4857 assert(isVolatile() == vol && "Volatile representation error!"); 4858} 4859 4860/// getMemOperand - Return a MachineMemOperand object describing the memory 4861/// reference performed by this memory reference. 4862MachineMemOperand MemSDNode::getMemOperand() const { 4863 int Flags = 0; 4864 if (isa<LoadSDNode>(this)) 4865 Flags = MachineMemOperand::MOLoad; 4866 else if (isa<StoreSDNode>(this)) 4867 Flags = MachineMemOperand::MOStore; 4868 else if (isa<AtomicSDNode>(this)) { 4869 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4870 } 4871 else { 4872 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4873 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4874 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4875 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4876 } 4877 4878 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4879 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4880 4881 // Check if the memory reference references a frame index 4882 const FrameIndexSDNode *FI = 4883 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4884 if (!getSrcValue() && FI) 4885 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4886 Flags, 0, Size, getAlignment()); 4887 else 4888 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4889 Size, getAlignment()); 4890} 4891 4892/// Profile - Gather unique data for the node. 4893/// 4894void SDNode::Profile(FoldingSetNodeID &ID) const { 4895 AddNodeIDNode(ID, this); 4896} 4897 4898/// getValueTypeList - Return a pointer to the specified value type. 4899/// 4900const MVT *SDNode::getValueTypeList(MVT VT) { 4901 if (VT.isExtended()) { 4902 static std::set<MVT, MVT::compareRawBits> EVTs; 4903 return &(*EVTs.insert(VT).first); 4904 } else { 4905 static MVT VTs[MVT::LAST_VALUETYPE]; 4906 VTs[VT.getSimpleVT()] = VT; 4907 return &VTs[VT.getSimpleVT()]; 4908 } 4909} 4910 4911/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4912/// indicated value. This method ignores uses of other values defined by this 4913/// operation. 4914bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4915 assert(Value < getNumValues() && "Bad value!"); 4916 4917 // TODO: Only iterate over uses of a given value of the node 4918 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4919 if (UI.getUse().getSDValue().getResNo() == Value) { 4920 if (NUses == 0) 4921 return false; 4922 --NUses; 4923 } 4924 } 4925 4926 // Found exactly the right number of uses? 4927 return NUses == 0; 4928} 4929 4930 4931/// hasAnyUseOfValue - Return true if there are any use of the indicated 4932/// value. This method ignores uses of other values defined by this operation. 4933bool SDNode::hasAnyUseOfValue(unsigned Value) const { 4934 assert(Value < getNumValues() && "Bad value!"); 4935 4936 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 4937 if (UI.getUse().getSDValue().getResNo() == Value) 4938 return true; 4939 4940 return false; 4941} 4942 4943 4944/// isOnlyUserOf - Return true if this node is the only use of N. 4945/// 4946bool SDNode::isOnlyUserOf(SDNode *N) const { 4947 bool Seen = false; 4948 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 4949 SDNode *User = *I; 4950 if (User == this) 4951 Seen = true; 4952 else 4953 return false; 4954 } 4955 4956 return Seen; 4957} 4958 4959/// isOperand - Return true if this node is an operand of N. 4960/// 4961bool SDValue::isOperandOf(SDNode *N) const { 4962 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4963 if (*this == N->getOperand(i)) 4964 return true; 4965 return false; 4966} 4967 4968bool SDNode::isOperandOf(SDNode *N) const { 4969 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 4970 if (this == N->OperandList[i].getVal()) 4971 return true; 4972 return false; 4973} 4974 4975/// reachesChainWithoutSideEffects - Return true if this operand (which must 4976/// be a chain) reaches the specified operand without crossing any 4977/// side-effecting instructions. In practice, this looks through token 4978/// factors and non-volatile loads. In order to remain efficient, this only 4979/// looks a couple of nodes in, it does not do an exhaustive search. 4980bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 4981 unsigned Depth) const { 4982 if (*this == Dest) return true; 4983 4984 // Don't search too deeply, we just want to be able to see through 4985 // TokenFactor's etc. 4986 if (Depth == 0) return false; 4987 4988 // If this is a token factor, all inputs to the TF happen in parallel. If any 4989 // of the operands of the TF reach dest, then we can do the xform. 4990 if (getOpcode() == ISD::TokenFactor) { 4991 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 4992 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 4993 return true; 4994 return false; 4995 } 4996 4997 // Loads don't have side effects, look through them. 4998 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 4999 if (!Ld->isVolatile()) 5000 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 5001 } 5002 return false; 5003} 5004 5005 5006static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 5007 SmallPtrSet<SDNode *, 32> &Visited) { 5008 if (found || !Visited.insert(N)) 5009 return; 5010 5011 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 5012 SDNode *Op = N->getOperand(i).getNode(); 5013 if (Op == P) { 5014 found = true; 5015 return; 5016 } 5017 findPredecessor(Op, P, found, Visited); 5018 } 5019} 5020 5021/// isPredecessorOf - Return true if this node is a predecessor of N. This node 5022/// is either an operand of N or it can be reached by recursively traversing 5023/// up the operands. 5024/// NOTE: this is an expensive method. Use it carefully. 5025bool SDNode::isPredecessorOf(SDNode *N) const { 5026 SmallPtrSet<SDNode *, 32> Visited; 5027 bool found = false; 5028 findPredecessor(N, this, found, Visited); 5029 return found; 5030} 5031 5032uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 5033 assert(Num < NumOperands && "Invalid child # of SDNode!"); 5034 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 5035} 5036 5037std::string SDNode::getOperationName(const SelectionDAG *G) const { 5038 switch (getOpcode()) { 5039 default: 5040 if (getOpcode() < ISD::BUILTIN_OP_END) 5041 return "<<Unknown DAG Node>>"; 5042 if (isMachineOpcode()) { 5043 if (G) 5044 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 5045 if (getMachineOpcode() < TII->getNumOpcodes()) 5046 return TII->get(getMachineOpcode()).getName(); 5047 return "<<Unknown Machine Node>>"; 5048 } 5049 if (G) { 5050 TargetLowering &TLI = G->getTargetLoweringInfo(); 5051 const char *Name = TLI.getTargetNodeName(getOpcode()); 5052 if (Name) return Name; 5053 return "<<Unknown Target Node>>"; 5054 } 5055 return "<<Unknown Node>>"; 5056 5057#ifndef NDEBUG 5058 case ISD::DELETED_NODE: 5059 return "<<Deleted Node!>>"; 5060#endif 5061 case ISD::PREFETCH: return "Prefetch"; 5062 case ISD::MEMBARRIER: return "MemBarrier"; 5063 case ISD::ATOMIC_CMP_SWAP_8: return "AtomicCmpSwap8"; 5064 case ISD::ATOMIC_SWAP_8: return "AtomicSwap8"; 5065 case ISD::ATOMIC_LOAD_ADD_8: return "AtomicLoadAdd8"; 5066 case ISD::ATOMIC_LOAD_SUB_8: return "AtomicLoadSub8"; 5067 case ISD::ATOMIC_LOAD_AND_8: return "AtomicLoadAnd8"; 5068 case ISD::ATOMIC_LOAD_OR_8: return "AtomicLoadOr8"; 5069 case ISD::ATOMIC_LOAD_XOR_8: return "AtomicLoadXor8"; 5070 case ISD::ATOMIC_LOAD_NAND_8: return "AtomicLoadNand8"; 5071 case ISD::ATOMIC_LOAD_MIN_8: return "AtomicLoadMin8"; 5072 case ISD::ATOMIC_LOAD_MAX_8: return "AtomicLoadMax8"; 5073 case ISD::ATOMIC_LOAD_UMIN_8: return "AtomicLoadUMin8"; 5074 case ISD::ATOMIC_LOAD_UMAX_8: return "AtomicLoadUMax8"; 5075 case ISD::ATOMIC_CMP_SWAP_16: return "AtomicCmpSwap16"; 5076 case ISD::ATOMIC_SWAP_16: return "AtomicSwap16"; 5077 case ISD::ATOMIC_LOAD_ADD_16: return "AtomicLoadAdd16"; 5078 case ISD::ATOMIC_LOAD_SUB_16: return "AtomicLoadSub16"; 5079 case ISD::ATOMIC_LOAD_AND_16: return "AtomicLoadAnd16"; 5080 case ISD::ATOMIC_LOAD_OR_16: return "AtomicLoadOr16"; 5081 case ISD::ATOMIC_LOAD_XOR_16: return "AtomicLoadXor16"; 5082 case ISD::ATOMIC_LOAD_NAND_16: return "AtomicLoadNand16"; 5083 case ISD::ATOMIC_LOAD_MIN_16: return "AtomicLoadMin16"; 5084 case ISD::ATOMIC_LOAD_MAX_16: return "AtomicLoadMax16"; 5085 case ISD::ATOMIC_LOAD_UMIN_16: return "AtomicLoadUMin16"; 5086 case ISD::ATOMIC_LOAD_UMAX_16: return "AtomicLoadUMax16"; 5087 case ISD::ATOMIC_CMP_SWAP_32: return "AtomicCmpSwap32"; 5088 case ISD::ATOMIC_SWAP_32: return "AtomicSwap32"; 5089 case ISD::ATOMIC_LOAD_ADD_32: return "AtomicLoadAdd32"; 5090 case ISD::ATOMIC_LOAD_SUB_32: return "AtomicLoadSub32"; 5091 case ISD::ATOMIC_LOAD_AND_32: return "AtomicLoadAnd32"; 5092 case ISD::ATOMIC_LOAD_OR_32: return "AtomicLoadOr32"; 5093 case ISD::ATOMIC_LOAD_XOR_32: return "AtomicLoadXor32"; 5094 case ISD::ATOMIC_LOAD_NAND_32: return "AtomicLoadNand32"; 5095 case ISD::ATOMIC_LOAD_MIN_32: return "AtomicLoadMin32"; 5096 case ISD::ATOMIC_LOAD_MAX_32: return "AtomicLoadMax32"; 5097 case ISD::ATOMIC_LOAD_UMIN_32: return "AtomicLoadUMin32"; 5098 case ISD::ATOMIC_LOAD_UMAX_32: return "AtomicLoadUMax32"; 5099 case ISD::ATOMIC_CMP_SWAP_64: return "AtomicCmpSwap64"; 5100 case ISD::ATOMIC_SWAP_64: return "AtomicSwap64"; 5101 case ISD::ATOMIC_LOAD_ADD_64: return "AtomicLoadAdd64"; 5102 case ISD::ATOMIC_LOAD_SUB_64: return "AtomicLoadSub64"; 5103 case ISD::ATOMIC_LOAD_AND_64: return "AtomicLoadAnd64"; 5104 case ISD::ATOMIC_LOAD_OR_64: return "AtomicLoadOr64"; 5105 case ISD::ATOMIC_LOAD_XOR_64: return "AtomicLoadXor64"; 5106 case ISD::ATOMIC_LOAD_NAND_64: return "AtomicLoadNand64"; 5107 case ISD::ATOMIC_LOAD_MIN_64: return "AtomicLoadMin64"; 5108 case ISD::ATOMIC_LOAD_MAX_64: return "AtomicLoadMax64"; 5109 case ISD::ATOMIC_LOAD_UMIN_64: return "AtomicLoadUMin64"; 5110 case ISD::ATOMIC_LOAD_UMAX_64: return "AtomicLoadUMax64"; 5111 case ISD::PCMARKER: return "PCMarker"; 5112 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5113 case ISD::SRCVALUE: return "SrcValue"; 5114 case ISD::MEMOPERAND: return "MemOperand"; 5115 case ISD::EntryToken: return "EntryToken"; 5116 case ISD::TokenFactor: return "TokenFactor"; 5117 case ISD::AssertSext: return "AssertSext"; 5118 case ISD::AssertZext: return "AssertZext"; 5119 5120 case ISD::BasicBlock: return "BasicBlock"; 5121 case ISD::ARG_FLAGS: return "ArgFlags"; 5122 case ISD::VALUETYPE: return "ValueType"; 5123 case ISD::Register: return "Register"; 5124 5125 case ISD::Constant: return "Constant"; 5126 case ISD::ConstantFP: return "ConstantFP"; 5127 case ISD::GlobalAddress: return "GlobalAddress"; 5128 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5129 case ISD::FrameIndex: return "FrameIndex"; 5130 case ISD::JumpTable: return "JumpTable"; 5131 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5132 case ISD::RETURNADDR: return "RETURNADDR"; 5133 case ISD::FRAMEADDR: return "FRAMEADDR"; 5134 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5135 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5136 case ISD::EHSELECTION: return "EHSELECTION"; 5137 case ISD::EH_RETURN: return "EH_RETURN"; 5138 case ISD::ConstantPool: return "ConstantPool"; 5139 case ISD::ExternalSymbol: return "ExternalSymbol"; 5140 case ISD::INTRINSIC_WO_CHAIN: { 5141 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5142 return Intrinsic::getName((Intrinsic::ID)IID); 5143 } 5144 case ISD::INTRINSIC_VOID: 5145 case ISD::INTRINSIC_W_CHAIN: { 5146 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5147 return Intrinsic::getName((Intrinsic::ID)IID); 5148 } 5149 5150 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5151 case ISD::TargetConstant: return "TargetConstant"; 5152 case ISD::TargetConstantFP:return "TargetConstantFP"; 5153 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5154 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5155 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5156 case ISD::TargetJumpTable: return "TargetJumpTable"; 5157 case ISD::TargetConstantPool: return "TargetConstantPool"; 5158 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5159 5160 case ISD::CopyToReg: return "CopyToReg"; 5161 case ISD::CopyFromReg: return "CopyFromReg"; 5162 case ISD::UNDEF: return "undef"; 5163 case ISD::MERGE_VALUES: return "merge_values"; 5164 case ISD::INLINEASM: return "inlineasm"; 5165 case ISD::DBG_LABEL: return "dbg_label"; 5166 case ISD::EH_LABEL: return "eh_label"; 5167 case ISD::DECLARE: return "declare"; 5168 case ISD::HANDLENODE: return "handlenode"; 5169 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5170 case ISD::CALL: return "call"; 5171 5172 // Unary operators 5173 case ISD::FABS: return "fabs"; 5174 case ISD::FNEG: return "fneg"; 5175 case ISD::FSQRT: return "fsqrt"; 5176 case ISD::FSIN: return "fsin"; 5177 case ISD::FCOS: return "fcos"; 5178 case ISD::FPOWI: return "fpowi"; 5179 case ISD::FPOW: return "fpow"; 5180 case ISD::FTRUNC: return "ftrunc"; 5181 case ISD::FFLOOR: return "ffloor"; 5182 case ISD::FCEIL: return "fceil"; 5183 case ISD::FRINT: return "frint"; 5184 case ISD::FNEARBYINT: return "fnearbyint"; 5185 5186 // Binary operators 5187 case ISD::ADD: return "add"; 5188 case ISD::SUB: return "sub"; 5189 case ISD::MUL: return "mul"; 5190 case ISD::MULHU: return "mulhu"; 5191 case ISD::MULHS: return "mulhs"; 5192 case ISD::SDIV: return "sdiv"; 5193 case ISD::UDIV: return "udiv"; 5194 case ISD::SREM: return "srem"; 5195 case ISD::UREM: return "urem"; 5196 case ISD::SMUL_LOHI: return "smul_lohi"; 5197 case ISD::UMUL_LOHI: return "umul_lohi"; 5198 case ISD::SDIVREM: return "sdivrem"; 5199 case ISD::UDIVREM: return "udivrem"; 5200 case ISD::AND: return "and"; 5201 case ISD::OR: return "or"; 5202 case ISD::XOR: return "xor"; 5203 case ISD::SHL: return "shl"; 5204 case ISD::SRA: return "sra"; 5205 case ISD::SRL: return "srl"; 5206 case ISD::ROTL: return "rotl"; 5207 case ISD::ROTR: return "rotr"; 5208 case ISD::FADD: return "fadd"; 5209 case ISD::FSUB: return "fsub"; 5210 case ISD::FMUL: return "fmul"; 5211 case ISD::FDIV: return "fdiv"; 5212 case ISD::FREM: return "frem"; 5213 case ISD::FCOPYSIGN: return "fcopysign"; 5214 case ISD::FGETSIGN: return "fgetsign"; 5215 5216 case ISD::SETCC: return "setcc"; 5217 case ISD::VSETCC: return "vsetcc"; 5218 case ISD::SELECT: return "select"; 5219 case ISD::SELECT_CC: return "select_cc"; 5220 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5221 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5222 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5223 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5224 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5225 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5226 case ISD::CARRY_FALSE: return "carry_false"; 5227 case ISD::ADDC: return "addc"; 5228 case ISD::ADDE: return "adde"; 5229 case ISD::SADDO: return "saddo"; 5230 case ISD::UADDO: return "uaddo"; 5231 case ISD::SSUBO: return "ssubo"; 5232 case ISD::USUBO: return "usubo"; 5233 case ISD::SMULO: return "smulo"; 5234 case ISD::UMULO: return "umulo"; 5235 case ISD::SUBC: return "subc"; 5236 case ISD::SUBE: return "sube"; 5237 case ISD::SHL_PARTS: return "shl_parts"; 5238 case ISD::SRA_PARTS: return "sra_parts"; 5239 case ISD::SRL_PARTS: return "srl_parts"; 5240 5241 case ISD::EXTRACT_SUBREG: return "extract_subreg"; 5242 case ISD::INSERT_SUBREG: return "insert_subreg"; 5243 5244 // Conversion operators. 5245 case ISD::SIGN_EXTEND: return "sign_extend"; 5246 case ISD::ZERO_EXTEND: return "zero_extend"; 5247 case ISD::ANY_EXTEND: return "any_extend"; 5248 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5249 case ISD::TRUNCATE: return "truncate"; 5250 case ISD::FP_ROUND: return "fp_round"; 5251 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5252 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5253 case ISD::FP_EXTEND: return "fp_extend"; 5254 5255 case ISD::SINT_TO_FP: return "sint_to_fp"; 5256 case ISD::UINT_TO_FP: return "uint_to_fp"; 5257 case ISD::FP_TO_SINT: return "fp_to_sint"; 5258 case ISD::FP_TO_UINT: return "fp_to_uint"; 5259 case ISD::BIT_CONVERT: return "bit_convert"; 5260 5261 case ISD::CONVERT_RNDSAT: { 5262 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5263 default: assert(0 && "Unknown cvt code!"); 5264 case ISD::CVT_FF: return "cvt_ff"; 5265 case ISD::CVT_FS: return "cvt_fs"; 5266 case ISD::CVT_FU: return "cvt_fu"; 5267 case ISD::CVT_SF: return "cvt_sf"; 5268 case ISD::CVT_UF: return "cvt_uf"; 5269 case ISD::CVT_SS: return "cvt_ss"; 5270 case ISD::CVT_SU: return "cvt_su"; 5271 case ISD::CVT_US: return "cvt_us"; 5272 case ISD::CVT_UU: return "cvt_uu"; 5273 } 5274 } 5275 5276 // Control flow instructions 5277 case ISD::BR: return "br"; 5278 case ISD::BRIND: return "brind"; 5279 case ISD::BR_JT: return "br_jt"; 5280 case ISD::BRCOND: return "brcond"; 5281 case ISD::BR_CC: return "br_cc"; 5282 case ISD::RET: return "ret"; 5283 case ISD::CALLSEQ_START: return "callseq_start"; 5284 case ISD::CALLSEQ_END: return "callseq_end"; 5285 5286 // Other operators 5287 case ISD::LOAD: return "load"; 5288 case ISD::STORE: return "store"; 5289 case ISD::VAARG: return "vaarg"; 5290 case ISD::VACOPY: return "vacopy"; 5291 case ISD::VAEND: return "vaend"; 5292 case ISD::VASTART: return "vastart"; 5293 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5294 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5295 case ISD::BUILD_PAIR: return "build_pair"; 5296 case ISD::STACKSAVE: return "stacksave"; 5297 case ISD::STACKRESTORE: return "stackrestore"; 5298 case ISD::TRAP: return "trap"; 5299 5300 // Bit manipulation 5301 case ISD::BSWAP: return "bswap"; 5302 case ISD::CTPOP: return "ctpop"; 5303 case ISD::CTTZ: return "cttz"; 5304 case ISD::CTLZ: return "ctlz"; 5305 5306 // Debug info 5307 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5308 case ISD::DEBUG_LOC: return "debug_loc"; 5309 5310 // Trampolines 5311 case ISD::TRAMPOLINE: return "trampoline"; 5312 5313 case ISD::CONDCODE: 5314 switch (cast<CondCodeSDNode>(this)->get()) { 5315 default: assert(0 && "Unknown setcc condition!"); 5316 case ISD::SETOEQ: return "setoeq"; 5317 case ISD::SETOGT: return "setogt"; 5318 case ISD::SETOGE: return "setoge"; 5319 case ISD::SETOLT: return "setolt"; 5320 case ISD::SETOLE: return "setole"; 5321 case ISD::SETONE: return "setone"; 5322 5323 case ISD::SETO: return "seto"; 5324 case ISD::SETUO: return "setuo"; 5325 case ISD::SETUEQ: return "setue"; 5326 case ISD::SETUGT: return "setugt"; 5327 case ISD::SETUGE: return "setuge"; 5328 case ISD::SETULT: return "setult"; 5329 case ISD::SETULE: return "setule"; 5330 case ISD::SETUNE: return "setune"; 5331 5332 case ISD::SETEQ: return "seteq"; 5333 case ISD::SETGT: return "setgt"; 5334 case ISD::SETGE: return "setge"; 5335 case ISD::SETLT: return "setlt"; 5336 case ISD::SETLE: return "setle"; 5337 case ISD::SETNE: return "setne"; 5338 } 5339 } 5340} 5341 5342const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5343 switch (AM) { 5344 default: 5345 return ""; 5346 case ISD::PRE_INC: 5347 return "<pre-inc>"; 5348 case ISD::PRE_DEC: 5349 return "<pre-dec>"; 5350 case ISD::POST_INC: 5351 return "<post-inc>"; 5352 case ISD::POST_DEC: 5353 return "<post-dec>"; 5354 } 5355} 5356 5357std::string ISD::ArgFlagsTy::getArgFlagsString() { 5358 std::string S = "< "; 5359 5360 if (isZExt()) 5361 S += "zext "; 5362 if (isSExt()) 5363 S += "sext "; 5364 if (isInReg()) 5365 S += "inreg "; 5366 if (isSRet()) 5367 S += "sret "; 5368 if (isByVal()) 5369 S += "byval "; 5370 if (isNest()) 5371 S += "nest "; 5372 if (getByValAlign()) 5373 S += "byval-align:" + utostr(getByValAlign()) + " "; 5374 if (getOrigAlign()) 5375 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5376 if (getByValSize()) 5377 S += "byval-size:" + utostr(getByValSize()) + " "; 5378 return S + ">"; 5379} 5380 5381void SDNode::dump() const { dump(0); } 5382void SDNode::dump(const SelectionDAG *G) const { 5383 print(errs(), G); 5384 errs().flush(); 5385} 5386 5387void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5388 OS << (void*)this << ": "; 5389 5390 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5391 if (i) OS << ","; 5392 if (getValueType(i) == MVT::Other) 5393 OS << "ch"; 5394 else 5395 OS << getValueType(i).getMVTString(); 5396 } 5397 OS << " = " << getOperationName(G); 5398 5399 OS << " "; 5400 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5401 if (i) OS << ", "; 5402 OS << (void*)getOperand(i).getNode(); 5403 if (unsigned RN = getOperand(i).getResNo()) 5404 OS << ":" << RN; 5405 } 5406 5407 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5408 SDNode *Mask = getOperand(2).getNode(); 5409 OS << "<"; 5410 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 5411 if (i) OS << ","; 5412 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 5413 OS << "u"; 5414 else 5415 OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue(); 5416 } 5417 OS << ">"; 5418 } 5419 5420 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5421 OS << '<' << CSDN->getAPIntValue() << '>'; 5422 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5423 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5424 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5425 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5426 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5427 else { 5428 OS << "<APFloat("; 5429 CSDN->getValueAPF().bitcastToAPInt().dump(); 5430 OS << ")>"; 5431 } 5432 } else if (const GlobalAddressSDNode *GADN = 5433 dyn_cast<GlobalAddressSDNode>(this)) { 5434 int64_t offset = GADN->getOffset(); 5435 OS << '<'; 5436 WriteAsOperand(OS, GADN->getGlobal()); 5437 OS << '>'; 5438 if (offset > 0) 5439 OS << " + " << offset; 5440 else 5441 OS << " " << offset; 5442 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5443 OS << "<" << FIDN->getIndex() << ">"; 5444 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5445 OS << "<" << JTDN->getIndex() << ">"; 5446 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5447 int offset = CP->getOffset(); 5448 if (CP->isMachineConstantPoolEntry()) 5449 OS << "<" << *CP->getMachineCPVal() << ">"; 5450 else 5451 OS << "<" << *CP->getConstVal() << ">"; 5452 if (offset > 0) 5453 OS << " + " << offset; 5454 else 5455 OS << " " << offset; 5456 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5457 OS << "<"; 5458 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5459 if (LBB) 5460 OS << LBB->getName() << " "; 5461 OS << (const void*)BBDN->getBasicBlock() << ">"; 5462 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5463 if (G && R->getReg() && 5464 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5465 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5466 } else { 5467 OS << " #" << R->getReg(); 5468 } 5469 } else if (const ExternalSymbolSDNode *ES = 5470 dyn_cast<ExternalSymbolSDNode>(this)) { 5471 OS << "'" << ES->getSymbol() << "'"; 5472 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5473 if (M->getValue()) 5474 OS << "<" << M->getValue() << ">"; 5475 else 5476 OS << "<null>"; 5477 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5478 if (M->MO.getValue()) 5479 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5480 else 5481 OS << "<null:" << M->MO.getOffset() << ">"; 5482 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5483 OS << N->getArgFlags().getArgFlagsString(); 5484 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5485 OS << ":" << N->getVT().getMVTString(); 5486 } 5487 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5488 const Value *SrcValue = LD->getSrcValue(); 5489 int SrcOffset = LD->getSrcValueOffset(); 5490 OS << " <"; 5491 if (SrcValue) 5492 OS << SrcValue; 5493 else 5494 OS << "null"; 5495 OS << ":" << SrcOffset << ">"; 5496 5497 bool doExt = true; 5498 switch (LD->getExtensionType()) { 5499 default: doExt = false; break; 5500 case ISD::EXTLOAD: OS << " <anyext "; break; 5501 case ISD::SEXTLOAD: OS << " <sext "; break; 5502 case ISD::ZEXTLOAD: OS << " <zext "; break; 5503 } 5504 if (doExt) 5505 OS << LD->getMemoryVT().getMVTString() << ">"; 5506 5507 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5508 if (*AM) 5509 OS << " " << AM; 5510 if (LD->isVolatile()) 5511 OS << " <volatile>"; 5512 OS << " alignment=" << LD->getAlignment(); 5513 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5514 const Value *SrcValue = ST->getSrcValue(); 5515 int SrcOffset = ST->getSrcValueOffset(); 5516 OS << " <"; 5517 if (SrcValue) 5518 OS << SrcValue; 5519 else 5520 OS << "null"; 5521 OS << ":" << SrcOffset << ">"; 5522 5523 if (ST->isTruncatingStore()) 5524 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5525 5526 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5527 if (*AM) 5528 OS << " " << AM; 5529 if (ST->isVolatile()) 5530 OS << " <volatile>"; 5531 OS << " alignment=" << ST->getAlignment(); 5532 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5533 const Value *SrcValue = AT->getSrcValue(); 5534 int SrcOffset = AT->getSrcValueOffset(); 5535 OS << " <"; 5536 if (SrcValue) 5537 OS << SrcValue; 5538 else 5539 OS << "null"; 5540 OS << ":" << SrcOffset << ">"; 5541 if (AT->isVolatile()) 5542 OS << " <volatile>"; 5543 OS << " alignment=" << AT->getAlignment(); 5544 } 5545} 5546 5547static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5548 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5549 if (N->getOperand(i).getNode()->hasOneUse()) 5550 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5551 else 5552 cerr << "\n" << std::string(indent+2, ' ') 5553 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5554 5555 5556 cerr << "\n" << std::string(indent, ' '); 5557 N->dump(G); 5558} 5559 5560void SelectionDAG::dump() const { 5561 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5562 5563 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5564 I != E; ++I) { 5565 const SDNode *N = I; 5566 if (!N->hasOneUse() && N != getRoot().getNode()) 5567 DumpNodes(N, 2, this); 5568 } 5569 5570 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5571 5572 cerr << "\n\n"; 5573} 5574 5575const Type *ConstantPoolSDNode::getType() const { 5576 if (isMachineConstantPoolEntry()) 5577 return Val.MachineCPVal->getType(); 5578 return Val.ConstVal->getType(); 5579} 5580