TargetLowering.cpp revision 0521928ae7cc492f3f45ef0e0cedc349102489c5
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/CodeGen/Analysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineJumpTableInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31#include <cctype> 32using namespace llvm; 33 34namespace llvm { 35TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 36 bool isLocal = GV->hasLocalLinkage(); 37 bool isDeclaration = GV->isDeclaration(); 38 // FIXME: what should we do for protected and internal visibility? 39 // For variables, is internal different from hidden? 40 bool isHidden = GV->hasHiddenVisibility(); 41 42 if (reloc == Reloc::PIC_) { 43 if (isLocal || isHidden) 44 return TLSModel::LocalDynamic; 45 else 46 return TLSModel::GeneralDynamic; 47 } else { 48 if (!isDeclaration || isHidden) 49 return TLSModel::LocalExec; 50 else 51 return TLSModel::InitialExec; 52 } 53} 54} 55 56/// InitLibcallNames - Set default libcall names. 57/// 58static void InitLibcallNames(const char **Names) { 59 Names[RTLIB::SHL_I16] = "__ashlhi3"; 60 Names[RTLIB::SHL_I32] = "__ashlsi3"; 61 Names[RTLIB::SHL_I64] = "__ashldi3"; 62 Names[RTLIB::SHL_I128] = "__ashlti3"; 63 Names[RTLIB::SRL_I16] = "__lshrhi3"; 64 Names[RTLIB::SRL_I32] = "__lshrsi3"; 65 Names[RTLIB::SRL_I64] = "__lshrdi3"; 66 Names[RTLIB::SRL_I128] = "__lshrti3"; 67 Names[RTLIB::SRA_I16] = "__ashrhi3"; 68 Names[RTLIB::SRA_I32] = "__ashrsi3"; 69 Names[RTLIB::SRA_I64] = "__ashrdi3"; 70 Names[RTLIB::SRA_I128] = "__ashrti3"; 71 Names[RTLIB::MUL_I8] = "__mulqi3"; 72 Names[RTLIB::MUL_I16] = "__mulhi3"; 73 Names[RTLIB::MUL_I32] = "__mulsi3"; 74 Names[RTLIB::MUL_I64] = "__muldi3"; 75 Names[RTLIB::MUL_I128] = "__multi3"; 76 Names[RTLIB::SDIV_I8] = "__divqi3"; 77 Names[RTLIB::SDIV_I16] = "__divhi3"; 78 Names[RTLIB::SDIV_I32] = "__divsi3"; 79 Names[RTLIB::SDIV_I64] = "__divdi3"; 80 Names[RTLIB::SDIV_I128] = "__divti3"; 81 Names[RTLIB::UDIV_I8] = "__udivqi3"; 82 Names[RTLIB::UDIV_I16] = "__udivhi3"; 83 Names[RTLIB::UDIV_I32] = "__udivsi3"; 84 Names[RTLIB::UDIV_I64] = "__udivdi3"; 85 Names[RTLIB::UDIV_I128] = "__udivti3"; 86 Names[RTLIB::SREM_I8] = "__modqi3"; 87 Names[RTLIB::SREM_I16] = "__modhi3"; 88 Names[RTLIB::SREM_I32] = "__modsi3"; 89 Names[RTLIB::SREM_I64] = "__moddi3"; 90 Names[RTLIB::SREM_I128] = "__modti3"; 91 Names[RTLIB::UREM_I8] = "__umodqi3"; 92 Names[RTLIB::UREM_I16] = "__umodhi3"; 93 Names[RTLIB::UREM_I32] = "__umodsi3"; 94 Names[RTLIB::UREM_I64] = "__umoddi3"; 95 Names[RTLIB::UREM_I128] = "__umodti3"; 96 Names[RTLIB::NEG_I32] = "__negsi2"; 97 Names[RTLIB::NEG_I64] = "__negdi2"; 98 Names[RTLIB::ADD_F32] = "__addsf3"; 99 Names[RTLIB::ADD_F64] = "__adddf3"; 100 Names[RTLIB::ADD_F80] = "__addxf3"; 101 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 102 Names[RTLIB::SUB_F32] = "__subsf3"; 103 Names[RTLIB::SUB_F64] = "__subdf3"; 104 Names[RTLIB::SUB_F80] = "__subxf3"; 105 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 106 Names[RTLIB::MUL_F32] = "__mulsf3"; 107 Names[RTLIB::MUL_F64] = "__muldf3"; 108 Names[RTLIB::MUL_F80] = "__mulxf3"; 109 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 110 Names[RTLIB::DIV_F32] = "__divsf3"; 111 Names[RTLIB::DIV_F64] = "__divdf3"; 112 Names[RTLIB::DIV_F80] = "__divxf3"; 113 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 114 Names[RTLIB::REM_F32] = "fmodf"; 115 Names[RTLIB::REM_F64] = "fmod"; 116 Names[RTLIB::REM_F80] = "fmodl"; 117 Names[RTLIB::REM_PPCF128] = "fmodl"; 118 Names[RTLIB::POWI_F32] = "__powisf2"; 119 Names[RTLIB::POWI_F64] = "__powidf2"; 120 Names[RTLIB::POWI_F80] = "__powixf2"; 121 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 122 Names[RTLIB::SQRT_F32] = "sqrtf"; 123 Names[RTLIB::SQRT_F64] = "sqrt"; 124 Names[RTLIB::SQRT_F80] = "sqrtl"; 125 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 126 Names[RTLIB::LOG_F32] = "logf"; 127 Names[RTLIB::LOG_F64] = "log"; 128 Names[RTLIB::LOG_F80] = "logl"; 129 Names[RTLIB::LOG_PPCF128] = "logl"; 130 Names[RTLIB::LOG2_F32] = "log2f"; 131 Names[RTLIB::LOG2_F64] = "log2"; 132 Names[RTLIB::LOG2_F80] = "log2l"; 133 Names[RTLIB::LOG2_PPCF128] = "log2l"; 134 Names[RTLIB::LOG10_F32] = "log10f"; 135 Names[RTLIB::LOG10_F64] = "log10"; 136 Names[RTLIB::LOG10_F80] = "log10l"; 137 Names[RTLIB::LOG10_PPCF128] = "log10l"; 138 Names[RTLIB::EXP_F32] = "expf"; 139 Names[RTLIB::EXP_F64] = "exp"; 140 Names[RTLIB::EXP_F80] = "expl"; 141 Names[RTLIB::EXP_PPCF128] = "expl"; 142 Names[RTLIB::EXP2_F32] = "exp2f"; 143 Names[RTLIB::EXP2_F64] = "exp2"; 144 Names[RTLIB::EXP2_F80] = "exp2l"; 145 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 146 Names[RTLIB::SIN_F32] = "sinf"; 147 Names[RTLIB::SIN_F64] = "sin"; 148 Names[RTLIB::SIN_F80] = "sinl"; 149 Names[RTLIB::SIN_PPCF128] = "sinl"; 150 Names[RTLIB::COS_F32] = "cosf"; 151 Names[RTLIB::COS_F64] = "cos"; 152 Names[RTLIB::COS_F80] = "cosl"; 153 Names[RTLIB::COS_PPCF128] = "cosl"; 154 Names[RTLIB::POW_F32] = "powf"; 155 Names[RTLIB::POW_F64] = "pow"; 156 Names[RTLIB::POW_F80] = "powl"; 157 Names[RTLIB::POW_PPCF128] = "powl"; 158 Names[RTLIB::CEIL_F32] = "ceilf"; 159 Names[RTLIB::CEIL_F64] = "ceil"; 160 Names[RTLIB::CEIL_F80] = "ceill"; 161 Names[RTLIB::CEIL_PPCF128] = "ceill"; 162 Names[RTLIB::TRUNC_F32] = "truncf"; 163 Names[RTLIB::TRUNC_F64] = "trunc"; 164 Names[RTLIB::TRUNC_F80] = "truncl"; 165 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 166 Names[RTLIB::RINT_F32] = "rintf"; 167 Names[RTLIB::RINT_F64] = "rint"; 168 Names[RTLIB::RINT_F80] = "rintl"; 169 Names[RTLIB::RINT_PPCF128] = "rintl"; 170 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 171 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 172 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 173 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 174 Names[RTLIB::FLOOR_F32] = "floorf"; 175 Names[RTLIB::FLOOR_F64] = "floor"; 176 Names[RTLIB::FLOOR_F80] = "floorl"; 177 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 178 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 179 Names[RTLIB::COPYSIGN_F64] = "copysign"; 180 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 181 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 182 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 183 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 184 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 185 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 186 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 187 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 188 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 189 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 190 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 191 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 192 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 193 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 194 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 195 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 196 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 197 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 198 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 199 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 200 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 201 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 202 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 203 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 204 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 205 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 206 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 207 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 208 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 209 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 210 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 211 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 212 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 213 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 214 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 215 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 216 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 217 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 218 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 219 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 220 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 221 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 222 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 223 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 224 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 225 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 226 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 227 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 228 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 229 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 230 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 231 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 232 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 233 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 234 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 235 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 236 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 237 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 238 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 239 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 240 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 241 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 242 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 243 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 244 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 245 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 246 Names[RTLIB::OEQ_F32] = "__eqsf2"; 247 Names[RTLIB::OEQ_F64] = "__eqdf2"; 248 Names[RTLIB::UNE_F32] = "__nesf2"; 249 Names[RTLIB::UNE_F64] = "__nedf2"; 250 Names[RTLIB::OGE_F32] = "__gesf2"; 251 Names[RTLIB::OGE_F64] = "__gedf2"; 252 Names[RTLIB::OLT_F32] = "__ltsf2"; 253 Names[RTLIB::OLT_F64] = "__ltdf2"; 254 Names[RTLIB::OLE_F32] = "__lesf2"; 255 Names[RTLIB::OLE_F64] = "__ledf2"; 256 Names[RTLIB::OGT_F32] = "__gtsf2"; 257 Names[RTLIB::OGT_F64] = "__gtdf2"; 258 Names[RTLIB::UO_F32] = "__unordsf2"; 259 Names[RTLIB::UO_F64] = "__unorddf2"; 260 Names[RTLIB::O_F32] = "__unordsf2"; 261 Names[RTLIB::O_F64] = "__unorddf2"; 262 Names[RTLIB::MEMCPY] = "memcpy"; 263 Names[RTLIB::MEMMOVE] = "memmove"; 264 Names[RTLIB::MEMSET] = "memset"; 265 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 268 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 269 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 272 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 273 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 274 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 275 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 276 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 277 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 278 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 279 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 280 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 281 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 282 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 283 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 284 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 285 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 286 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 287 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 288 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 289 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 290 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 291 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 292 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4"; 293 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 294 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 295 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 296 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 297 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 298} 299 300/// InitLibcallCallingConvs - Set default libcall CallingConvs. 301/// 302static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 303 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 304 CCs[i] = CallingConv::C; 305 } 306} 307 308/// getFPEXT - Return the FPEXT_*_* value for the given types, or 309/// UNKNOWN_LIBCALL if there is none. 310RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 311 if (OpVT == MVT::f32) { 312 if (RetVT == MVT::f64) 313 return FPEXT_F32_F64; 314 } 315 316 return UNKNOWN_LIBCALL; 317} 318 319/// getFPROUND - Return the FPROUND_*_* value for the given types, or 320/// UNKNOWN_LIBCALL if there is none. 321RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 322 if (RetVT == MVT::f32) { 323 if (OpVT == MVT::f64) 324 return FPROUND_F64_F32; 325 if (OpVT == MVT::f80) 326 return FPROUND_F80_F32; 327 if (OpVT == MVT::ppcf128) 328 return FPROUND_PPCF128_F32; 329 } else if (RetVT == MVT::f64) { 330 if (OpVT == MVT::f80) 331 return FPROUND_F80_F64; 332 if (OpVT == MVT::ppcf128) 333 return FPROUND_PPCF128_F64; 334 } 335 336 return UNKNOWN_LIBCALL; 337} 338 339/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 340/// UNKNOWN_LIBCALL if there is none. 341RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 342 if (OpVT == MVT::f32) { 343 if (RetVT == MVT::i8) 344 return FPTOSINT_F32_I8; 345 if (RetVT == MVT::i16) 346 return FPTOSINT_F32_I16; 347 if (RetVT == MVT::i32) 348 return FPTOSINT_F32_I32; 349 if (RetVT == MVT::i64) 350 return FPTOSINT_F32_I64; 351 if (RetVT == MVT::i128) 352 return FPTOSINT_F32_I128; 353 } else if (OpVT == MVT::f64) { 354 if (RetVT == MVT::i8) 355 return FPTOSINT_F64_I8; 356 if (RetVT == MVT::i16) 357 return FPTOSINT_F64_I16; 358 if (RetVT == MVT::i32) 359 return FPTOSINT_F64_I32; 360 if (RetVT == MVT::i64) 361 return FPTOSINT_F64_I64; 362 if (RetVT == MVT::i128) 363 return FPTOSINT_F64_I128; 364 } else if (OpVT == MVT::f80) { 365 if (RetVT == MVT::i32) 366 return FPTOSINT_F80_I32; 367 if (RetVT == MVT::i64) 368 return FPTOSINT_F80_I64; 369 if (RetVT == MVT::i128) 370 return FPTOSINT_F80_I128; 371 } else if (OpVT == MVT::ppcf128) { 372 if (RetVT == MVT::i32) 373 return FPTOSINT_PPCF128_I32; 374 if (RetVT == MVT::i64) 375 return FPTOSINT_PPCF128_I64; 376 if (RetVT == MVT::i128) 377 return FPTOSINT_PPCF128_I128; 378 } 379 return UNKNOWN_LIBCALL; 380} 381 382/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 383/// UNKNOWN_LIBCALL if there is none. 384RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 385 if (OpVT == MVT::f32) { 386 if (RetVT == MVT::i8) 387 return FPTOUINT_F32_I8; 388 if (RetVT == MVT::i16) 389 return FPTOUINT_F32_I16; 390 if (RetVT == MVT::i32) 391 return FPTOUINT_F32_I32; 392 if (RetVT == MVT::i64) 393 return FPTOUINT_F32_I64; 394 if (RetVT == MVT::i128) 395 return FPTOUINT_F32_I128; 396 } else if (OpVT == MVT::f64) { 397 if (RetVT == MVT::i8) 398 return FPTOUINT_F64_I8; 399 if (RetVT == MVT::i16) 400 return FPTOUINT_F64_I16; 401 if (RetVT == MVT::i32) 402 return FPTOUINT_F64_I32; 403 if (RetVT == MVT::i64) 404 return FPTOUINT_F64_I64; 405 if (RetVT == MVT::i128) 406 return FPTOUINT_F64_I128; 407 } else if (OpVT == MVT::f80) { 408 if (RetVT == MVT::i32) 409 return FPTOUINT_F80_I32; 410 if (RetVT == MVT::i64) 411 return FPTOUINT_F80_I64; 412 if (RetVT == MVT::i128) 413 return FPTOUINT_F80_I128; 414 } else if (OpVT == MVT::ppcf128) { 415 if (RetVT == MVT::i32) 416 return FPTOUINT_PPCF128_I32; 417 if (RetVT == MVT::i64) 418 return FPTOUINT_PPCF128_I64; 419 if (RetVT == MVT::i128) 420 return FPTOUINT_PPCF128_I128; 421 } 422 return UNKNOWN_LIBCALL; 423} 424 425/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 426/// UNKNOWN_LIBCALL if there is none. 427RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 428 if (OpVT == MVT::i32) { 429 if (RetVT == MVT::f32) 430 return SINTTOFP_I32_F32; 431 else if (RetVT == MVT::f64) 432 return SINTTOFP_I32_F64; 433 else if (RetVT == MVT::f80) 434 return SINTTOFP_I32_F80; 435 else if (RetVT == MVT::ppcf128) 436 return SINTTOFP_I32_PPCF128; 437 } else if (OpVT == MVT::i64) { 438 if (RetVT == MVT::f32) 439 return SINTTOFP_I64_F32; 440 else if (RetVT == MVT::f64) 441 return SINTTOFP_I64_F64; 442 else if (RetVT == MVT::f80) 443 return SINTTOFP_I64_F80; 444 else if (RetVT == MVT::ppcf128) 445 return SINTTOFP_I64_PPCF128; 446 } else if (OpVT == MVT::i128) { 447 if (RetVT == MVT::f32) 448 return SINTTOFP_I128_F32; 449 else if (RetVT == MVT::f64) 450 return SINTTOFP_I128_F64; 451 else if (RetVT == MVT::f80) 452 return SINTTOFP_I128_F80; 453 else if (RetVT == MVT::ppcf128) 454 return SINTTOFP_I128_PPCF128; 455 } 456 return UNKNOWN_LIBCALL; 457} 458 459/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 460/// UNKNOWN_LIBCALL if there is none. 461RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 462 if (OpVT == MVT::i32) { 463 if (RetVT == MVT::f32) 464 return UINTTOFP_I32_F32; 465 else if (RetVT == MVT::f64) 466 return UINTTOFP_I32_F64; 467 else if (RetVT == MVT::f80) 468 return UINTTOFP_I32_F80; 469 else if (RetVT == MVT::ppcf128) 470 return UINTTOFP_I32_PPCF128; 471 } else if (OpVT == MVT::i64) { 472 if (RetVT == MVT::f32) 473 return UINTTOFP_I64_F32; 474 else if (RetVT == MVT::f64) 475 return UINTTOFP_I64_F64; 476 else if (RetVT == MVT::f80) 477 return UINTTOFP_I64_F80; 478 else if (RetVT == MVT::ppcf128) 479 return UINTTOFP_I64_PPCF128; 480 } else if (OpVT == MVT::i128) { 481 if (RetVT == MVT::f32) 482 return UINTTOFP_I128_F32; 483 else if (RetVT == MVT::f64) 484 return UINTTOFP_I128_F64; 485 else if (RetVT == MVT::f80) 486 return UINTTOFP_I128_F80; 487 else if (RetVT == MVT::ppcf128) 488 return UINTTOFP_I128_PPCF128; 489 } 490 return UNKNOWN_LIBCALL; 491} 492 493/// InitCmpLibcallCCs - Set default comparison libcall CC. 494/// 495static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 496 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 497 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 498 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 499 CCs[RTLIB::UNE_F32] = ISD::SETNE; 500 CCs[RTLIB::UNE_F64] = ISD::SETNE; 501 CCs[RTLIB::OGE_F32] = ISD::SETGE; 502 CCs[RTLIB::OGE_F64] = ISD::SETGE; 503 CCs[RTLIB::OLT_F32] = ISD::SETLT; 504 CCs[RTLIB::OLT_F64] = ISD::SETLT; 505 CCs[RTLIB::OLE_F32] = ISD::SETLE; 506 CCs[RTLIB::OLE_F64] = ISD::SETLE; 507 CCs[RTLIB::OGT_F32] = ISD::SETGT; 508 CCs[RTLIB::OGT_F64] = ISD::SETGT; 509 CCs[RTLIB::UO_F32] = ISD::SETNE; 510 CCs[RTLIB::UO_F64] = ISD::SETNE; 511 CCs[RTLIB::O_F32] = ISD::SETEQ; 512 CCs[RTLIB::O_F64] = ISD::SETEQ; 513} 514 515/// NOTE: The constructor takes ownership of TLOF. 516TargetLowering::TargetLowering(const TargetMachine &tm, 517 const TargetLoweringObjectFile *tlof) 518 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 519 // All operations default to being supported. 520 memset(OpActions, 0, sizeof(OpActions)); 521 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 522 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 523 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 524 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 525 526 // Set default actions for various operations. 527 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 528 // Default all indexed load / store to expand. 529 for (unsigned IM = (unsigned)ISD::PRE_INC; 530 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 531 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 532 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 533 } 534 535 // These operations default to expand. 536 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 537 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 538 } 539 540 // Most targets ignore the @llvm.prefetch intrinsic. 541 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 542 543 // ConstantFP nodes default to expand. Targets can either change this to 544 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 545 // to optimize expansions for certain constants. 546 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 547 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 548 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 549 550 // These library functions default to expand. 551 setOperationAction(ISD::FLOG , MVT::f64, Expand); 552 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 553 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 554 setOperationAction(ISD::FEXP , MVT::f64, Expand); 555 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 556 setOperationAction(ISD::FLOG , MVT::f32, Expand); 557 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 558 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 559 setOperationAction(ISD::FEXP , MVT::f32, Expand); 560 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 561 562 // Default ISD::TRAP to expand (which turns it into abort). 563 setOperationAction(ISD::TRAP, MVT::Other, Expand); 564 565 IsLittleEndian = TD->isLittleEndian(); 566 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 567 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 568 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 569 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 570 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize 571 = maxStoresPerMemmoveOptSize = 4; 572 benefitFromCodePlacementOpt = false; 573 UseUnderscoreSetJmp = false; 574 UseUnderscoreLongJmp = false; 575 SelectIsExpensive = false; 576 IntDivIsCheap = false; 577 Pow2DivIsCheap = false; 578 JumpIsExpensive = false; 579 StackPointerRegisterToSaveRestore = 0; 580 ExceptionPointerRegister = 0; 581 ExceptionSelectorRegister = 0; 582 BooleanContents = UndefinedBooleanContent; 583 SchedPreferenceInfo = Sched::Latency; 584 JumpBufSize = 0; 585 JumpBufAlignment = 0; 586 PrefLoopAlignment = 0; 587 MinStackArgumentAlignment = 1; 588 ShouldFoldAtomicFences = false; 589 590 InitLibcallNames(LibcallRoutineNames); 591 InitCmpLibcallCCs(CmpLibcallCCs); 592 InitLibcallCallingConvs(LibcallCallingConvs); 593} 594 595TargetLowering::~TargetLowering() { 596 delete &TLOF; 597} 598 599/// canOpTrap - Returns true if the operation can trap for the value type. 600/// VT must be a legal type. 601bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 602 assert(isTypeLegal(VT)); 603 switch (Op) { 604 default: 605 return false; 606 case ISD::FDIV: 607 case ISD::FREM: 608 case ISD::SDIV: 609 case ISD::UDIV: 610 case ISD::SREM: 611 case ISD::UREM: 612 return true; 613 } 614} 615 616 617static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 618 unsigned &NumIntermediates, 619 EVT &RegisterVT, 620 TargetLowering *TLI) { 621 // Figure out the right, legal destination reg to copy into. 622 unsigned NumElts = VT.getVectorNumElements(); 623 MVT EltTy = VT.getVectorElementType(); 624 625 unsigned NumVectorRegs = 1; 626 627 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 628 // could break down into LHS/RHS like LegalizeDAG does. 629 if (!isPowerOf2_32(NumElts)) { 630 NumVectorRegs = NumElts; 631 NumElts = 1; 632 } 633 634 // Divide the input until we get to a supported size. This will always 635 // end with a scalar if the target doesn't support vectors. 636 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 637 NumElts >>= 1; 638 NumVectorRegs <<= 1; 639 } 640 641 NumIntermediates = NumVectorRegs; 642 643 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 644 if (!TLI->isTypeLegal(NewVT)) 645 NewVT = EltTy; 646 IntermediateVT = NewVT; 647 648 EVT DestVT = TLI->getRegisterType(NewVT); 649 RegisterVT = DestVT; 650 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 651 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 652 653 // Otherwise, promotion or legal types use the same number of registers as 654 // the vector decimated to the appropriate level. 655 return NumVectorRegs; 656} 657 658/// isLegalRC - Return true if the value types that can be represented by the 659/// specified register class are all legal. 660bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const { 661 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 662 I != E; ++I) { 663 if (isTypeLegal(*I)) 664 return true; 665 } 666 return false; 667} 668 669/// hasLegalSuperRegRegClasses - Return true if the specified register class 670/// has one or more super-reg register classes that are legal. 671bool 672TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{ 673 if (*RC->superregclasses_begin() == 0) 674 return false; 675 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 676 E = RC->superregclasses_end(); I != E; ++I) { 677 const TargetRegisterClass *RRC = *I; 678 if (isLegalRC(RRC)) 679 return true; 680 } 681 return false; 682} 683 684/// findRepresentativeClass - Return the largest legal super-reg register class 685/// of the register class for the specified type and its associated "cost". 686std::pair<const TargetRegisterClass*, uint8_t> 687TargetLowering::findRepresentativeClass(EVT VT) const { 688 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 689 if (!RC) 690 return std::make_pair(RC, 0); 691 const TargetRegisterClass *BestRC = RC; 692 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 693 E = RC->superregclasses_end(); I != E; ++I) { 694 const TargetRegisterClass *RRC = *I; 695 if (RRC->isASubClass() || !isLegalRC(RRC)) 696 continue; 697 if (!hasLegalSuperRegRegClasses(RRC)) 698 return std::make_pair(RRC, 1); 699 BestRC = RRC; 700 } 701 return std::make_pair(BestRC, 1); 702} 703 704 705/// computeRegisterProperties - Once all of the register classes are added, 706/// this allows us to compute derived properties we expose. 707void TargetLowering::computeRegisterProperties() { 708 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 709 "Too many value types for ValueTypeActions to hold!"); 710 711 // Everything defaults to needing one register. 712 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 713 NumRegistersForVT[i] = 1; 714 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 715 } 716 // ...except isVoid, which doesn't need any registers. 717 NumRegistersForVT[MVT::isVoid] = 0; 718 719 // Find the largest integer register class. 720 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 721 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 722 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 723 724 // Every integer value type larger than this largest register takes twice as 725 // many registers to represent as the previous ValueType. 726 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 727 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 728 if (!ExpandedVT.isInteger()) 729 break; 730 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 731 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 732 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 733 ValueTypeActions.setTypeAction(ExpandedVT, Expand); 734 } 735 736 // Inspect all of the ValueType's smaller than the largest integer 737 // register to see which ones need promotion. 738 unsigned LegalIntReg = LargestIntReg; 739 for (unsigned IntReg = LargestIntReg - 1; 740 IntReg >= (unsigned)MVT::i1; --IntReg) { 741 EVT IVT = (MVT::SimpleValueType)IntReg; 742 if (isTypeLegal(IVT)) { 743 LegalIntReg = IntReg; 744 } else { 745 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 746 (MVT::SimpleValueType)LegalIntReg; 747 ValueTypeActions.setTypeAction(IVT, Promote); 748 } 749 } 750 751 // ppcf128 type is really two f64's. 752 if (!isTypeLegal(MVT::ppcf128)) { 753 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 754 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 755 TransformToType[MVT::ppcf128] = MVT::f64; 756 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 757 } 758 759 // Decide how to handle f64. If the target does not have native f64 support, 760 // expand it to i64 and we will be generating soft float library calls. 761 if (!isTypeLegal(MVT::f64)) { 762 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 763 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 764 TransformToType[MVT::f64] = MVT::i64; 765 ValueTypeActions.setTypeAction(MVT::f64, Expand); 766 } 767 768 // Decide how to handle f32. If the target does not have native support for 769 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 770 if (!isTypeLegal(MVT::f32)) { 771 if (isTypeLegal(MVT::f64)) { 772 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 773 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 774 TransformToType[MVT::f32] = MVT::f64; 775 ValueTypeActions.setTypeAction(MVT::f32, Promote); 776 } else { 777 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 778 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 779 TransformToType[MVT::f32] = MVT::i32; 780 ValueTypeActions.setTypeAction(MVT::f32, Expand); 781 } 782 } 783 784 // Loop over all of the vector value types to see which need transformations. 785 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 786 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 787 MVT VT = (MVT::SimpleValueType)i; 788 if (isTypeLegal(VT)) continue; 789 790 // Determine if there is a legal wider type. If so, we should promote to 791 // that wider vector type. 792 EVT EltVT = VT.getVectorElementType(); 793 unsigned NElts = VT.getVectorNumElements(); 794 if (NElts != 1) { 795 bool IsLegalWiderType = false; 796 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 797 EVT SVT = (MVT::SimpleValueType)nVT; 798 if (SVT.getVectorElementType() == EltVT && 799 SVT.getVectorNumElements() > NElts && 800 isTypeLegal(SVT)) { 801 TransformToType[i] = SVT; 802 RegisterTypeForVT[i] = SVT; 803 NumRegistersForVT[i] = 1; 804 ValueTypeActions.setTypeAction(VT, Promote); 805 IsLegalWiderType = true; 806 break; 807 } 808 } 809 if (IsLegalWiderType) continue; 810 } 811 812 MVT IntermediateVT; 813 EVT RegisterVT; 814 unsigned NumIntermediates; 815 NumRegistersForVT[i] = 816 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 817 RegisterVT, this); 818 RegisterTypeForVT[i] = RegisterVT; 819 820 EVT NVT = VT.getPow2VectorType(); 821 if (NVT == VT) { 822 // Type is already a power of 2. The default action is to split. 823 TransformToType[i] = MVT::Other; 824 ValueTypeActions.setTypeAction(VT, Expand); 825 } else { 826 TransformToType[i] = NVT; 827 ValueTypeActions.setTypeAction(VT, Promote); 828 } 829 } 830 831 // Determine the 'representative' register class for each value type. 832 // An representative register class is the largest (meaning one which is 833 // not a sub-register class / subreg register class) legal register class for 834 // a group of value types. For example, on i386, i8, i16, and i32 835 // representative would be GR32; while on x86_64 it's GR64. 836 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 837 const TargetRegisterClass* RRC; 838 uint8_t Cost; 839 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 840 RepRegClassForVT[i] = RRC; 841 RepRegClassCostForVT[i] = Cost; 842 } 843} 844 845const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 846 return NULL; 847} 848 849 850MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 851 return PointerTy.SimpleTy; 852} 853 854MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 855 return MVT::i32; // return the default value 856} 857 858/// getVectorTypeBreakdown - Vector types are broken down into some number of 859/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 860/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 861/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 862/// 863/// This method returns the number of registers needed, and the VT for each 864/// register. It also returns the VT and quantity of the intermediate values 865/// before they are promoted/expanded. 866/// 867unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 868 EVT &IntermediateVT, 869 unsigned &NumIntermediates, 870 EVT &RegisterVT) const { 871 unsigned NumElts = VT.getVectorNumElements(); 872 873 // If there is a wider vector type with the same element type as this one, 874 // we should widen to that legal vector type. This handles things like 875 // <2 x float> -> <4 x float>. 876 if (NumElts != 1 && getTypeAction(VT) == Promote) { 877 RegisterVT = getTypeToTransformTo(Context, VT); 878 if (isTypeLegal(RegisterVT)) { 879 IntermediateVT = RegisterVT; 880 NumIntermediates = 1; 881 return 1; 882 } 883 } 884 885 // Figure out the right, legal destination reg to copy into. 886 EVT EltTy = VT.getVectorElementType(); 887 888 unsigned NumVectorRegs = 1; 889 890 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 891 // could break down into LHS/RHS like LegalizeDAG does. 892 if (!isPowerOf2_32(NumElts)) { 893 NumVectorRegs = NumElts; 894 NumElts = 1; 895 } 896 897 // Divide the input until we get to a supported size. This will always 898 // end with a scalar if the target doesn't support vectors. 899 while (NumElts > 1 && !isTypeLegal( 900 EVT::getVectorVT(Context, EltTy, NumElts))) { 901 NumElts >>= 1; 902 NumVectorRegs <<= 1; 903 } 904 905 NumIntermediates = NumVectorRegs; 906 907 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 908 if (!isTypeLegal(NewVT)) 909 NewVT = EltTy; 910 IntermediateVT = NewVT; 911 912 EVT DestVT = getRegisterType(Context, NewVT); 913 RegisterVT = DestVT; 914 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 915 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 916 917 // Otherwise, promotion or legal types use the same number of registers as 918 // the vector decimated to the appropriate level. 919 return NumVectorRegs; 920} 921 922/// Get the EVTs and ArgFlags collections that represent the legalized return 923/// type of the given function. This does not require a DAG or a return value, 924/// and is suitable for use before any DAGs for the function are constructed. 925/// TODO: Move this out of TargetLowering.cpp. 926void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr, 927 SmallVectorImpl<ISD::OutputArg> &Outs, 928 const TargetLowering &TLI, 929 SmallVectorImpl<uint64_t> *Offsets) { 930 SmallVector<EVT, 4> ValueVTs; 931 ComputeValueVTs(TLI, ReturnType, ValueVTs); 932 unsigned NumValues = ValueVTs.size(); 933 if (NumValues == 0) return; 934 unsigned Offset = 0; 935 936 for (unsigned j = 0, f = NumValues; j != f; ++j) { 937 EVT VT = ValueVTs[j]; 938 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 939 940 if (attr & Attribute::SExt) 941 ExtendKind = ISD::SIGN_EXTEND; 942 else if (attr & Attribute::ZExt) 943 ExtendKind = ISD::ZERO_EXTEND; 944 945 // FIXME: C calling convention requires the return type to be promoted to 946 // at least 32-bit. But this is not necessary for non-C calling 947 // conventions. The frontend should mark functions whose return values 948 // require promoting with signext or zeroext attributes. 949 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 950 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 951 if (VT.bitsLT(MinVT)) 952 VT = MinVT; 953 } 954 955 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 956 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 957 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 958 PartVT.getTypeForEVT(ReturnType->getContext())); 959 960 // 'inreg' on function refers to return value 961 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 962 if (attr & Attribute::InReg) 963 Flags.setInReg(); 964 965 // Propagate extension type if any 966 if (attr & Attribute::SExt) 967 Flags.setSExt(); 968 else if (attr & Attribute::ZExt) 969 Flags.setZExt(); 970 971 for (unsigned i = 0; i < NumParts; ++i) { 972 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true)); 973 if (Offsets) { 974 Offsets->push_back(Offset); 975 Offset += PartSize; 976 } 977 } 978 } 979} 980 981/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 982/// function arguments in the caller parameter area. This is the actual 983/// alignment, not its logarithm. 984unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 985 return TD->getCallFrameTypeAlignment(Ty); 986} 987 988/// getJumpTableEncoding - Return the entry encoding for a jump table in the 989/// current function. The returned value is a member of the 990/// MachineJumpTableInfo::JTEntryKind enum. 991unsigned TargetLowering::getJumpTableEncoding() const { 992 // In non-pic modes, just use the address of a block. 993 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 994 return MachineJumpTableInfo::EK_BlockAddress; 995 996 // In PIC mode, if the target supports a GPRel32 directive, use it. 997 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 998 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 999 1000 // Otherwise, use a label difference. 1001 return MachineJumpTableInfo::EK_LabelDifference32; 1002} 1003 1004SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1005 SelectionDAG &DAG) const { 1006 // If our PIC model is GP relative, use the global offset table as the base. 1007 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 1008 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 1009 return Table; 1010} 1011 1012/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1013/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1014/// MCExpr. 1015const MCExpr * 1016TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1017 unsigned JTI,MCContext &Ctx) const{ 1018 // The normal PIC reloc base is the label at the start of the jump table. 1019 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 1020} 1021 1022bool 1023TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1024 // Assume that everything is safe in static mode. 1025 if (getTargetMachine().getRelocationModel() == Reloc::Static) 1026 return true; 1027 1028 // In dynamic-no-pic mode, assume that known defined values are safe. 1029 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 1030 GA && 1031 !GA->getGlobal()->isDeclaration() && 1032 !GA->getGlobal()->isWeakForLinker()) 1033 return true; 1034 1035 // Otherwise assume nothing is safe. 1036 return false; 1037} 1038 1039//===----------------------------------------------------------------------===// 1040// Optimization Methods 1041//===----------------------------------------------------------------------===// 1042 1043/// ShrinkDemandedConstant - Check to see if the specified operand of the 1044/// specified instruction is a constant integer. If so, check to see if there 1045/// are any bits set in the constant that are not demanded. If so, shrink the 1046/// constant and return true. 1047bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 1048 const APInt &Demanded) { 1049 DebugLoc dl = Op.getDebugLoc(); 1050 1051 // FIXME: ISD::SELECT, ISD::SELECT_CC 1052 switch (Op.getOpcode()) { 1053 default: break; 1054 case ISD::XOR: 1055 case ISD::AND: 1056 case ISD::OR: { 1057 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1058 if (!C) return false; 1059 1060 if (Op.getOpcode() == ISD::XOR && 1061 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 1062 return false; 1063 1064 // if we can expand it to have all bits set, do it 1065 if (C->getAPIntValue().intersects(~Demanded)) { 1066 EVT VT = Op.getValueType(); 1067 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 1068 DAG.getConstant(Demanded & 1069 C->getAPIntValue(), 1070 VT)); 1071 return CombineTo(Op, New); 1072 } 1073 1074 break; 1075 } 1076 } 1077 1078 return false; 1079} 1080 1081/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1082/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1083/// cast, but it could be generalized for targets with other types of 1084/// implicit widening casts. 1085bool 1086TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 1087 unsigned BitWidth, 1088 const APInt &Demanded, 1089 DebugLoc dl) { 1090 assert(Op.getNumOperands() == 2 && 1091 "ShrinkDemandedOp only supports binary operators!"); 1092 assert(Op.getNode()->getNumValues() == 1 && 1093 "ShrinkDemandedOp only supports nodes with one result!"); 1094 1095 // Don't do this if the node has another user, which may require the 1096 // full value. 1097 if (!Op.getNode()->hasOneUse()) 1098 return false; 1099 1100 // Search for the smallest integer type with free casts to and from 1101 // Op's type. For expedience, just check power-of-2 integer types. 1102 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1103 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 1104 if (!isPowerOf2_32(SmallVTBits)) 1105 SmallVTBits = NextPowerOf2(SmallVTBits); 1106 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 1107 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 1108 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 1109 TLI.isZExtFree(SmallVT, Op.getValueType())) { 1110 // We found a type with free casts. 1111 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 1112 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1113 Op.getNode()->getOperand(0)), 1114 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1115 Op.getNode()->getOperand(1))); 1116 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 1117 return CombineTo(Op, Z); 1118 } 1119 } 1120 return false; 1121} 1122 1123/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1124/// DemandedMask bits of the result of Op are ever used downstream. If we can 1125/// use this information to simplify Op, create a new simplified DAG node and 1126/// return true, returning the original and new nodes in Old and New. Otherwise, 1127/// analyze the expression and return a mask of KnownOne and KnownZero bits for 1128/// the expression (used to simplify the caller). The KnownZero/One bits may 1129/// only be accurate for those bits in the DemandedMask. 1130bool TargetLowering::SimplifyDemandedBits(SDValue Op, 1131 const APInt &DemandedMask, 1132 APInt &KnownZero, 1133 APInt &KnownOne, 1134 TargetLoweringOpt &TLO, 1135 unsigned Depth) const { 1136 unsigned BitWidth = DemandedMask.getBitWidth(); 1137 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1138 "Mask size mismatches value type size!"); 1139 APInt NewMask = DemandedMask; 1140 DebugLoc dl = Op.getDebugLoc(); 1141 1142 // Don't know anything. 1143 KnownZero = KnownOne = APInt(BitWidth, 0); 1144 1145 // Other users may use these bits. 1146 if (!Op.getNode()->hasOneUse()) { 1147 if (Depth != 0) { 1148 // If not at the root, Just compute the KnownZero/KnownOne bits to 1149 // simplify things downstream. 1150 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 1151 return false; 1152 } 1153 // If this is the root being simplified, allow it to have multiple uses, 1154 // just set the NewMask to all bits. 1155 NewMask = APInt::getAllOnesValue(BitWidth); 1156 } else if (DemandedMask == 0) { 1157 // Not demanding any bits from Op. 1158 if (Op.getOpcode() != ISD::UNDEF) 1159 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1160 return false; 1161 } else if (Depth == 6) { // Limit search depth. 1162 return false; 1163 } 1164 1165 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1166 switch (Op.getOpcode()) { 1167 case ISD::Constant: 1168 // We know all of the bits for a constant! 1169 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 1170 KnownZero = ~KnownOne & NewMask; 1171 return false; // Don't fall through, will infinitely loop. 1172 case ISD::AND: 1173 // If the RHS is a constant, check to see if the LHS would be zero without 1174 // using the bits from the RHS. Below, we use knowledge about the RHS to 1175 // simplify the LHS, here we're using information from the LHS to simplify 1176 // the RHS. 1177 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1178 APInt LHSZero, LHSOne; 1179 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1180 LHSZero, LHSOne, Depth+1); 1181 // If the LHS already has zeros where RHSC does, this and is dead. 1182 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1183 return TLO.CombineTo(Op, Op.getOperand(0)); 1184 // If any of the set bits in the RHS are known zero on the LHS, shrink 1185 // the constant. 1186 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1187 return true; 1188 } 1189 1190 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1191 KnownOne, TLO, Depth+1)) 1192 return true; 1193 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1194 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1195 KnownZero2, KnownOne2, TLO, Depth+1)) 1196 return true; 1197 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1198 1199 // If all of the demanded bits are known one on one side, return the other. 1200 // These bits cannot contribute to the result of the 'and'. 1201 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1202 return TLO.CombineTo(Op, Op.getOperand(0)); 1203 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1204 return TLO.CombineTo(Op, Op.getOperand(1)); 1205 // If all of the demanded bits in the inputs are known zeros, return zero. 1206 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1207 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1208 // If the RHS is a constant, see if we can simplify it. 1209 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1210 return true; 1211 // If the operation can be done in a smaller type, do so. 1212 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1213 return true; 1214 1215 // Output known-1 bits are only known if set in both the LHS & RHS. 1216 KnownOne &= KnownOne2; 1217 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1218 KnownZero |= KnownZero2; 1219 break; 1220 case ISD::OR: 1221 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1222 KnownOne, TLO, Depth+1)) 1223 return true; 1224 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1225 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1226 KnownZero2, KnownOne2, TLO, Depth+1)) 1227 return true; 1228 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1229 1230 // If all of the demanded bits are known zero on one side, return the other. 1231 // These bits cannot contribute to the result of the 'or'. 1232 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1233 return TLO.CombineTo(Op, Op.getOperand(0)); 1234 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1235 return TLO.CombineTo(Op, Op.getOperand(1)); 1236 // If all of the potentially set bits on one side are known to be set on 1237 // the other side, just use the 'other' side. 1238 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1239 return TLO.CombineTo(Op, Op.getOperand(0)); 1240 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1241 return TLO.CombineTo(Op, Op.getOperand(1)); 1242 // If the RHS is a constant, see if we can simplify it. 1243 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1244 return true; 1245 // If the operation can be done in a smaller type, do so. 1246 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1247 return true; 1248 1249 // Output known-0 bits are only known if clear in both the LHS & RHS. 1250 KnownZero &= KnownZero2; 1251 // Output known-1 are known to be set if set in either the LHS | RHS. 1252 KnownOne |= KnownOne2; 1253 break; 1254 case ISD::XOR: 1255 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1256 KnownOne, TLO, Depth+1)) 1257 return true; 1258 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1259 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1260 KnownOne2, TLO, Depth+1)) 1261 return true; 1262 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1263 1264 // If all of the demanded bits are known zero on one side, return the other. 1265 // These bits cannot contribute to the result of the 'xor'. 1266 if ((KnownZero & NewMask) == NewMask) 1267 return TLO.CombineTo(Op, Op.getOperand(0)); 1268 if ((KnownZero2 & NewMask) == NewMask) 1269 return TLO.CombineTo(Op, Op.getOperand(1)); 1270 // If the operation can be done in a smaller type, do so. 1271 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1272 return true; 1273 1274 // If all of the unknown bits are known to be zero on one side or the other 1275 // (but not both) turn this into an *inclusive* or. 1276 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1277 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1278 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1279 Op.getOperand(0), 1280 Op.getOperand(1))); 1281 1282 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1283 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1284 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1285 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1286 1287 // If all of the demanded bits on one side are known, and all of the set 1288 // bits on that side are also known to be set on the other side, turn this 1289 // into an AND, as we know the bits will be cleared. 1290 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1291 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1292 if ((KnownOne & KnownOne2) == KnownOne) { 1293 EVT VT = Op.getValueType(); 1294 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1295 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1296 Op.getOperand(0), ANDC)); 1297 } 1298 } 1299 1300 // If the RHS is a constant, see if we can simplify it. 1301 // for XOR, we prefer to force bits to 1 if they will make a -1. 1302 // if we can't force bits, try to shrink constant 1303 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1304 APInt Expanded = C->getAPIntValue() | (~NewMask); 1305 // if we can expand it to have all bits set, do it 1306 if (Expanded.isAllOnesValue()) { 1307 if (Expanded != C->getAPIntValue()) { 1308 EVT VT = Op.getValueType(); 1309 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1310 TLO.DAG.getConstant(Expanded, VT)); 1311 return TLO.CombineTo(Op, New); 1312 } 1313 // if it already has all the bits set, nothing to change 1314 // but don't shrink either! 1315 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1316 return true; 1317 } 1318 } 1319 1320 KnownZero = KnownZeroOut; 1321 KnownOne = KnownOneOut; 1322 break; 1323 case ISD::SELECT: 1324 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1325 KnownOne, TLO, Depth+1)) 1326 return true; 1327 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1328 KnownOne2, TLO, Depth+1)) 1329 return true; 1330 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1331 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1332 1333 // If the operands are constants, see if we can simplify them. 1334 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1335 return true; 1336 1337 // Only known if known in both the LHS and RHS. 1338 KnownOne &= KnownOne2; 1339 KnownZero &= KnownZero2; 1340 break; 1341 case ISD::SELECT_CC: 1342 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1343 KnownOne, TLO, Depth+1)) 1344 return true; 1345 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1346 KnownOne2, TLO, Depth+1)) 1347 return true; 1348 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1349 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1350 1351 // If the operands are constants, see if we can simplify them. 1352 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1353 return true; 1354 1355 // Only known if known in both the LHS and RHS. 1356 KnownOne &= KnownOne2; 1357 KnownZero &= KnownZero2; 1358 break; 1359 case ISD::SHL: 1360 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1361 unsigned ShAmt = SA->getZExtValue(); 1362 SDValue InOp = Op.getOperand(0); 1363 1364 // If the shift count is an invalid immediate, don't do anything. 1365 if (ShAmt >= BitWidth) 1366 break; 1367 1368 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1369 // single shift. We can do this if the bottom bits (which are shifted 1370 // out) are never demanded. 1371 if (InOp.getOpcode() == ISD::SRL && 1372 isa<ConstantSDNode>(InOp.getOperand(1))) { 1373 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1374 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1375 unsigned Opc = ISD::SHL; 1376 int Diff = ShAmt-C1; 1377 if (Diff < 0) { 1378 Diff = -Diff; 1379 Opc = ISD::SRL; 1380 } 1381 1382 SDValue NewSA = 1383 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1384 EVT VT = Op.getValueType(); 1385 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1386 InOp.getOperand(0), NewSA)); 1387 } 1388 } 1389 1390 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 1391 KnownZero, KnownOne, TLO, Depth+1)) 1392 return true; 1393 1394 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 1395 // are not demanded. This will likely allow the anyext to be folded away. 1396 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 1397 SDValue InnerOp = InOp.getNode()->getOperand(0); 1398 EVT InnerVT = InnerOp.getValueType(); 1399 if ((APInt::getHighBitsSet(BitWidth, 1400 BitWidth - InnerVT.getSizeInBits()) & 1401 DemandedMask) == 0 && 1402 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 1403 EVT ShTy = getShiftAmountTy(); 1404 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 1405 ShTy = InnerVT; 1406 SDValue NarrowShl = 1407 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 1408 TLO.DAG.getConstant(ShAmt, ShTy)); 1409 return 1410 TLO.CombineTo(Op, 1411 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 1412 NarrowShl)); 1413 } 1414 } 1415 1416 KnownZero <<= SA->getZExtValue(); 1417 KnownOne <<= SA->getZExtValue(); 1418 // low bits known zero. 1419 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1420 } 1421 break; 1422 case ISD::SRL: 1423 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1424 EVT VT = Op.getValueType(); 1425 unsigned ShAmt = SA->getZExtValue(); 1426 unsigned VTSize = VT.getSizeInBits(); 1427 SDValue InOp = Op.getOperand(0); 1428 1429 // If the shift count is an invalid immediate, don't do anything. 1430 if (ShAmt >= BitWidth) 1431 break; 1432 1433 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1434 // single shift. We can do this if the top bits (which are shifted out) 1435 // are never demanded. 1436 if (InOp.getOpcode() == ISD::SHL && 1437 isa<ConstantSDNode>(InOp.getOperand(1))) { 1438 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1439 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1440 unsigned Opc = ISD::SRL; 1441 int Diff = ShAmt-C1; 1442 if (Diff < 0) { 1443 Diff = -Diff; 1444 Opc = ISD::SHL; 1445 } 1446 1447 SDValue NewSA = 1448 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1449 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1450 InOp.getOperand(0), NewSA)); 1451 } 1452 } 1453 1454 // Compute the new bits that are at the top now. 1455 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1456 KnownZero, KnownOne, TLO, Depth+1)) 1457 return true; 1458 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1459 KnownZero = KnownZero.lshr(ShAmt); 1460 KnownOne = KnownOne.lshr(ShAmt); 1461 1462 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1463 KnownZero |= HighBits; // High bits known zero. 1464 } 1465 break; 1466 case ISD::SRA: 1467 // If this is an arithmetic shift right and only the low-bit is set, we can 1468 // always convert this into a logical shr, even if the shift amount is 1469 // variable. The low bit of the shift cannot be an input sign bit unless 1470 // the shift amount is >= the size of the datatype, which is undefined. 1471 if (DemandedMask == 1) 1472 return TLO.CombineTo(Op, 1473 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1474 Op.getOperand(0), Op.getOperand(1))); 1475 1476 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1477 EVT VT = Op.getValueType(); 1478 unsigned ShAmt = SA->getZExtValue(); 1479 1480 // If the shift count is an invalid immediate, don't do anything. 1481 if (ShAmt >= BitWidth) 1482 break; 1483 1484 APInt InDemandedMask = (NewMask << ShAmt); 1485 1486 // If any of the demanded bits are produced by the sign extension, we also 1487 // demand the input sign bit. 1488 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1489 if (HighBits.intersects(NewMask)) 1490 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1491 1492 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1493 KnownZero, KnownOne, TLO, Depth+1)) 1494 return true; 1495 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1496 KnownZero = KnownZero.lshr(ShAmt); 1497 KnownOne = KnownOne.lshr(ShAmt); 1498 1499 // Handle the sign bit, adjusted to where it is now in the mask. 1500 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1501 1502 // If the input sign bit is known to be zero, or if none of the top bits 1503 // are demanded, turn this into an unsigned shift right. 1504 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1505 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1506 Op.getOperand(0), 1507 Op.getOperand(1))); 1508 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1509 KnownOne |= HighBits; 1510 } 1511 } 1512 break; 1513 case ISD::SIGN_EXTEND_INREG: { 1514 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1515 1516 // Sign extension. Compute the demanded bits in the result that are not 1517 // present in the input. 1518 APInt NewBits = 1519 APInt::getHighBitsSet(BitWidth, 1520 BitWidth - EVT.getScalarType().getSizeInBits()); 1521 1522 // If none of the extended bits are demanded, eliminate the sextinreg. 1523 if ((NewBits & NewMask) == 0) 1524 return TLO.CombineTo(Op, Op.getOperand(0)); 1525 1526 APInt InSignBit = 1527 APInt::getSignBit(EVT.getScalarType().getSizeInBits()).zext(BitWidth); 1528 APInt InputDemandedBits = 1529 APInt::getLowBitsSet(BitWidth, 1530 EVT.getScalarType().getSizeInBits()) & 1531 NewMask; 1532 1533 // Since the sign extended bits are demanded, we know that the sign 1534 // bit is demanded. 1535 InputDemandedBits |= InSignBit; 1536 1537 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1538 KnownZero, KnownOne, TLO, Depth+1)) 1539 return true; 1540 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1541 1542 // If the sign bit of the input is known set or clear, then we know the 1543 // top bits of the result. 1544 1545 // If the input sign bit is known zero, convert this into a zero extension. 1546 if (KnownZero.intersects(InSignBit)) 1547 return TLO.CombineTo(Op, 1548 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1549 1550 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1551 KnownOne |= NewBits; 1552 KnownZero &= ~NewBits; 1553 } else { // Input sign bit unknown 1554 KnownZero &= ~NewBits; 1555 KnownOne &= ~NewBits; 1556 } 1557 break; 1558 } 1559 case ISD::ZERO_EXTEND: { 1560 unsigned OperandBitWidth = 1561 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1562 APInt InMask = NewMask.trunc(OperandBitWidth); 1563 1564 // If none of the top bits are demanded, convert this into an any_extend. 1565 APInt NewBits = 1566 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1567 if (!NewBits.intersects(NewMask)) 1568 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1569 Op.getValueType(), 1570 Op.getOperand(0))); 1571 1572 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1573 KnownZero, KnownOne, TLO, Depth+1)) 1574 return true; 1575 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1576 KnownZero = KnownZero.zext(BitWidth); 1577 KnownOne = KnownOne.zext(BitWidth); 1578 KnownZero |= NewBits; 1579 break; 1580 } 1581 case ISD::SIGN_EXTEND: { 1582 EVT InVT = Op.getOperand(0).getValueType(); 1583 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1584 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1585 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1586 APInt NewBits = ~InMask & NewMask; 1587 1588 // If none of the top bits are demanded, convert this into an any_extend. 1589 if (NewBits == 0) 1590 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1591 Op.getValueType(), 1592 Op.getOperand(0))); 1593 1594 // Since some of the sign extended bits are demanded, we know that the sign 1595 // bit is demanded. 1596 APInt InDemandedBits = InMask & NewMask; 1597 InDemandedBits |= InSignBit; 1598 InDemandedBits = InDemandedBits.trunc(InBits); 1599 1600 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1601 KnownOne, TLO, Depth+1)) 1602 return true; 1603 KnownZero = KnownZero.zext(BitWidth); 1604 KnownOne = KnownOne.zext(BitWidth); 1605 1606 // If the sign bit is known zero, convert this to a zero extend. 1607 if (KnownZero.intersects(InSignBit)) 1608 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1609 Op.getValueType(), 1610 Op.getOperand(0))); 1611 1612 // If the sign bit is known one, the top bits match. 1613 if (KnownOne.intersects(InSignBit)) { 1614 KnownOne |= NewBits; 1615 KnownZero &= ~NewBits; 1616 } else { // Otherwise, top bits aren't known. 1617 KnownOne &= ~NewBits; 1618 KnownZero &= ~NewBits; 1619 } 1620 break; 1621 } 1622 case ISD::ANY_EXTEND: { 1623 unsigned OperandBitWidth = 1624 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1625 APInt InMask = NewMask.trunc(OperandBitWidth); 1626 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1627 KnownZero, KnownOne, TLO, Depth+1)) 1628 return true; 1629 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1630 KnownZero = KnownZero.zext(BitWidth); 1631 KnownOne = KnownOne.zext(BitWidth); 1632 break; 1633 } 1634 case ISD::TRUNCATE: { 1635 // Simplify the input, using demanded bit information, and compute the known 1636 // zero/one bits live out. 1637 unsigned OperandBitWidth = 1638 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1639 APInt TruncMask = NewMask.zext(OperandBitWidth); 1640 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1641 KnownZero, KnownOne, TLO, Depth+1)) 1642 return true; 1643 KnownZero = KnownZero.trunc(BitWidth); 1644 KnownOne = KnownOne.trunc(BitWidth); 1645 1646 // If the input is only used by this truncate, see if we can shrink it based 1647 // on the known demanded bits. 1648 if (Op.getOperand(0).getNode()->hasOneUse()) { 1649 SDValue In = Op.getOperand(0); 1650 switch (In.getOpcode()) { 1651 default: break; 1652 case ISD::SRL: 1653 // Shrink SRL by a constant if none of the high bits shifted in are 1654 // demanded. 1655 if (TLO.LegalTypes() && 1656 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1657 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1658 // undesirable. 1659 break; 1660 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1661 if (!ShAmt) 1662 break; 1663 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1664 OperandBitWidth - BitWidth); 1665 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 1666 1667 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1668 // None of the shifted in bits are needed. Add a truncate of the 1669 // shift input, then shift it. 1670 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1671 Op.getValueType(), 1672 In.getOperand(0)); 1673 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1674 Op.getValueType(), 1675 NewTrunc, 1676 In.getOperand(1))); 1677 } 1678 break; 1679 } 1680 } 1681 1682 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1683 break; 1684 } 1685 case ISD::AssertZext: { 1686 // Demand all the bits of the input that are demanded in the output. 1687 // The low bits are obvious; the high bits are demanded because we're 1688 // asserting that they're zero here. 1689 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, 1690 KnownZero, KnownOne, TLO, Depth+1)) 1691 return true; 1692 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1693 1694 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1695 APInt InMask = APInt::getLowBitsSet(BitWidth, 1696 VT.getSizeInBits()); 1697 KnownZero |= ~InMask & NewMask; 1698 break; 1699 } 1700 case ISD::BITCAST: 1701#if 0 1702 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1703 // is demanded, turn this into a FGETSIGN. 1704 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) && 1705 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1706 !MVT::isVector(Op.getOperand(0).getValueType())) { 1707 // Only do this xform if FGETSIGN is valid or if before legalize. 1708 if (!TLO.AfterLegalize || 1709 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1710 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1711 // place. We expect the SHL to be eliminated by other optimizations. 1712 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1713 Op.getOperand(0)); 1714 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1715 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1716 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1717 Sign, ShAmt)); 1718 } 1719 } 1720#endif 1721 break; 1722 case ISD::ADD: 1723 case ISD::MUL: 1724 case ISD::SUB: { 1725 // Add, Sub, and Mul don't demand any bits in positions beyond that 1726 // of the highest bit demanded of them. 1727 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1728 BitWidth - NewMask.countLeadingZeros()); 1729 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1730 KnownOne2, TLO, Depth+1)) 1731 return true; 1732 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1733 KnownOne2, TLO, Depth+1)) 1734 return true; 1735 // See if the operation should be performed at a smaller bit width. 1736 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1737 return true; 1738 } 1739 // FALL THROUGH 1740 default: 1741 // Just use ComputeMaskedBits to compute output bits. 1742 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1743 break; 1744 } 1745 1746 // If we know the value of all of the demanded bits, return this as a 1747 // constant. 1748 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1749 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1750 1751 return false; 1752} 1753 1754/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1755/// in Mask are known to be either zero or one and return them in the 1756/// KnownZero/KnownOne bitsets. 1757void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1758 const APInt &Mask, 1759 APInt &KnownZero, 1760 APInt &KnownOne, 1761 const SelectionDAG &DAG, 1762 unsigned Depth) const { 1763 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1764 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1765 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1766 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1767 "Should use MaskedValueIsZero if you don't know whether Op" 1768 " is a target node!"); 1769 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1770} 1771 1772/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1773/// targets that want to expose additional information about sign bits to the 1774/// DAG Combiner. 1775unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1776 unsigned Depth) const { 1777 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1778 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1779 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1780 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1781 "Should use ComputeNumSignBits if you don't know whether Op" 1782 " is a target node!"); 1783 return 1; 1784} 1785 1786/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1787/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1788/// determine which bit is set. 1789/// 1790static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1791 // A left-shift of a constant one will have exactly one bit set, because 1792 // shifting the bit off the end is undefined. 1793 if (Val.getOpcode() == ISD::SHL) 1794 if (ConstantSDNode *C = 1795 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1796 if (C->getAPIntValue() == 1) 1797 return true; 1798 1799 // Similarly, a right-shift of a constant sign-bit will have exactly 1800 // one bit set. 1801 if (Val.getOpcode() == ISD::SRL) 1802 if (ConstantSDNode *C = 1803 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1804 if (C->getAPIntValue().isSignBit()) 1805 return true; 1806 1807 // More could be done here, though the above checks are enough 1808 // to handle some common cases. 1809 1810 // Fall back to ComputeMaskedBits to catch other known cases. 1811 EVT OpVT = Val.getValueType(); 1812 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1813 APInt Mask = APInt::getAllOnesValue(BitWidth); 1814 APInt KnownZero, KnownOne; 1815 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1816 return (KnownZero.countPopulation() == BitWidth - 1) && 1817 (KnownOne.countPopulation() == 1); 1818} 1819 1820/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1821/// and cc. If it is unable to simplify it, return a null SDValue. 1822SDValue 1823TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1824 ISD::CondCode Cond, bool foldBooleans, 1825 DAGCombinerInfo &DCI, DebugLoc dl) const { 1826 SelectionDAG &DAG = DCI.DAG; 1827 LLVMContext &Context = *DAG.getContext(); 1828 1829 // These setcc operations always fold. 1830 switch (Cond) { 1831 default: break; 1832 case ISD::SETFALSE: 1833 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1834 case ISD::SETTRUE: 1835 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1836 } 1837 1838 if (isa<ConstantSDNode>(N0.getNode())) { 1839 // Ensure that the constant occurs on the RHS, and fold constant 1840 // comparisons. 1841 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1842 } 1843 1844 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1845 const APInt &C1 = N1C->getAPIntValue(); 1846 1847 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1848 // equality comparison, then we're just comparing whether X itself is 1849 // zero. 1850 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1851 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1852 N0.getOperand(1).getOpcode() == ISD::Constant) { 1853 const APInt &ShAmt 1854 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1855 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1856 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1857 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1858 // (srl (ctlz x), 5) == 0 -> X != 0 1859 // (srl (ctlz x), 5) != 1 -> X != 0 1860 Cond = ISD::SETNE; 1861 } else { 1862 // (srl (ctlz x), 5) != 0 -> X == 0 1863 // (srl (ctlz x), 5) == 1 -> X == 0 1864 Cond = ISD::SETEQ; 1865 } 1866 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1867 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1868 Zero, Cond); 1869 } 1870 } 1871 1872 // If the LHS is '(and load, const)', the RHS is 0, 1873 // the test is for equality or unsigned, and all 1 bits of the const are 1874 // in the same partial word, see if we can shorten the load. 1875 if (DCI.isBeforeLegalize() && 1876 N0.getOpcode() == ISD::AND && C1 == 0 && 1877 N0.getNode()->hasOneUse() && 1878 isa<LoadSDNode>(N0.getOperand(0)) && 1879 N0.getOperand(0).getNode()->hasOneUse() && 1880 isa<ConstantSDNode>(N0.getOperand(1))) { 1881 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1882 APInt bestMask; 1883 unsigned bestWidth = 0, bestOffset = 0; 1884 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1885 unsigned origWidth = N0.getValueType().getSizeInBits(); 1886 unsigned maskWidth = origWidth; 1887 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1888 // 8 bits, but have to be careful... 1889 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1890 origWidth = Lod->getMemoryVT().getSizeInBits(); 1891 const APInt &Mask = 1892 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1893 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1894 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1895 for (unsigned offset=0; offset<origWidth/width; offset++) { 1896 if ((newMask & Mask) == Mask) { 1897 if (!TD->isLittleEndian()) 1898 bestOffset = (origWidth/width - offset - 1) * (width/8); 1899 else 1900 bestOffset = (uint64_t)offset * (width/8); 1901 bestMask = Mask.lshr(offset * (width/8) * 8); 1902 bestWidth = width; 1903 break; 1904 } 1905 newMask = newMask << width; 1906 } 1907 } 1908 } 1909 if (bestWidth) { 1910 EVT newVT = EVT::getIntegerVT(Context, bestWidth); 1911 if (newVT.isRound()) { 1912 EVT PtrType = Lod->getOperand(1).getValueType(); 1913 SDValue Ptr = Lod->getBasePtr(); 1914 if (bestOffset != 0) 1915 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1916 DAG.getConstant(bestOffset, PtrType)); 1917 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1918 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1919 Lod->getPointerInfo().getWithOffset(bestOffset), 1920 false, false, NewAlign); 1921 return DAG.getSetCC(dl, VT, 1922 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1923 DAG.getConstant(bestMask.trunc(bestWidth), 1924 newVT)), 1925 DAG.getConstant(0LL, newVT), Cond); 1926 } 1927 } 1928 } 1929 1930 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1931 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1932 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1933 1934 // If the comparison constant has bits in the upper part, the 1935 // zero-extended value could never match. 1936 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1937 C1.getBitWidth() - InSize))) { 1938 switch (Cond) { 1939 case ISD::SETUGT: 1940 case ISD::SETUGE: 1941 case ISD::SETEQ: return DAG.getConstant(0, VT); 1942 case ISD::SETULT: 1943 case ISD::SETULE: 1944 case ISD::SETNE: return DAG.getConstant(1, VT); 1945 case ISD::SETGT: 1946 case ISD::SETGE: 1947 // True if the sign bit of C1 is set. 1948 return DAG.getConstant(C1.isNegative(), VT); 1949 case ISD::SETLT: 1950 case ISD::SETLE: 1951 // True if the sign bit of C1 isn't set. 1952 return DAG.getConstant(C1.isNonNegative(), VT); 1953 default: 1954 break; 1955 } 1956 } 1957 1958 // Otherwise, we can perform the comparison with the low bits. 1959 switch (Cond) { 1960 case ISD::SETEQ: 1961 case ISD::SETNE: 1962 case ISD::SETUGT: 1963 case ISD::SETUGE: 1964 case ISD::SETULT: 1965 case ISD::SETULE: { 1966 EVT newVT = N0.getOperand(0).getValueType(); 1967 if (DCI.isBeforeLegalizeOps() || 1968 (isOperationLegal(ISD::SETCC, newVT) && 1969 getCondCodeAction(Cond, newVT)==Legal)) 1970 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1971 DAG.getConstant(C1.trunc(InSize), newVT), 1972 Cond); 1973 break; 1974 } 1975 default: 1976 break; // todo, be more careful with signed comparisons 1977 } 1978 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1979 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1980 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1981 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1982 EVT ExtDstTy = N0.getValueType(); 1983 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1984 1985 // If the constant doesn't fit into the number of bits for the source of 1986 // the sign extension, it is impossible for both sides to be equal. 1987 if (C1.getMinSignedBits() > ExtSrcTyBits) 1988 return DAG.getConstant(Cond == ISD::SETNE, VT); 1989 1990 SDValue ZextOp; 1991 EVT Op0Ty = N0.getOperand(0).getValueType(); 1992 if (Op0Ty == ExtSrcTy) { 1993 ZextOp = N0.getOperand(0); 1994 } else { 1995 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1996 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1997 DAG.getConstant(Imm, Op0Ty)); 1998 } 1999 if (!DCI.isCalledByLegalizer()) 2000 DCI.AddToWorklist(ZextOp.getNode()); 2001 // Otherwise, make this a use of a zext. 2002 return DAG.getSetCC(dl, VT, ZextOp, 2003 DAG.getConstant(C1 & APInt::getLowBitsSet( 2004 ExtDstTyBits, 2005 ExtSrcTyBits), 2006 ExtDstTy), 2007 Cond); 2008 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 2009 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2010 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 2011 if (N0.getOpcode() == ISD::SETCC && 2012 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 2013 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 2014 if (TrueWhenTrue) 2015 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 2016 // Invert the condition. 2017 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 2018 CC = ISD::getSetCCInverse(CC, 2019 N0.getOperand(0).getValueType().isInteger()); 2020 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 2021 } 2022 2023 if ((N0.getOpcode() == ISD::XOR || 2024 (N0.getOpcode() == ISD::AND && 2025 N0.getOperand(0).getOpcode() == ISD::XOR && 2026 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2027 isa<ConstantSDNode>(N0.getOperand(1)) && 2028 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 2029 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 2030 // can only do this if the top bits are known zero. 2031 unsigned BitWidth = N0.getValueSizeInBits(); 2032 if (DAG.MaskedValueIsZero(N0, 2033 APInt::getHighBitsSet(BitWidth, 2034 BitWidth-1))) { 2035 // Okay, get the un-inverted input value. 2036 SDValue Val; 2037 if (N0.getOpcode() == ISD::XOR) 2038 Val = N0.getOperand(0); 2039 else { 2040 assert(N0.getOpcode() == ISD::AND && 2041 N0.getOperand(0).getOpcode() == ISD::XOR); 2042 // ((X^1)&1)^1 -> X & 1 2043 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 2044 N0.getOperand(0).getOperand(0), 2045 N0.getOperand(1)); 2046 } 2047 2048 return DAG.getSetCC(dl, VT, Val, N1, 2049 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2050 } 2051 } else if (N1C->getAPIntValue() == 1 && 2052 (VT == MVT::i1 || 2053 getBooleanContents() == ZeroOrOneBooleanContent)) { 2054 SDValue Op0 = N0; 2055 if (Op0.getOpcode() == ISD::TRUNCATE) 2056 Op0 = Op0.getOperand(0); 2057 2058 if ((Op0.getOpcode() == ISD::XOR) && 2059 Op0.getOperand(0).getOpcode() == ISD::SETCC && 2060 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 2061 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 2062 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 2063 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 2064 Cond); 2065 } else if (Op0.getOpcode() == ISD::AND && 2066 isa<ConstantSDNode>(Op0.getOperand(1)) && 2067 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 2068 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 2069 if (Op0.getValueType().bitsGT(VT)) 2070 Op0 = DAG.getNode(ISD::AND, dl, VT, 2071 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 2072 DAG.getConstant(1, VT)); 2073 else if (Op0.getValueType().bitsLT(VT)) 2074 Op0 = DAG.getNode(ISD::AND, dl, VT, 2075 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 2076 DAG.getConstant(1, VT)); 2077 2078 return DAG.getSetCC(dl, VT, Op0, 2079 DAG.getConstant(0, Op0.getValueType()), 2080 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2081 } 2082 } 2083 } 2084 2085 APInt MinVal, MaxVal; 2086 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 2087 if (ISD::isSignedIntSetCC(Cond)) { 2088 MinVal = APInt::getSignedMinValue(OperandBitSize); 2089 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 2090 } else { 2091 MinVal = APInt::getMinValue(OperandBitSize); 2092 MaxVal = APInt::getMaxValue(OperandBitSize); 2093 } 2094 2095 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2096 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2097 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2098 // X >= C0 --> X > (C0-1) 2099 return DAG.getSetCC(dl, VT, N0, 2100 DAG.getConstant(C1-1, N1.getValueType()), 2101 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2102 } 2103 2104 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2105 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2106 // X <= C0 --> X < (C0+1) 2107 return DAG.getSetCC(dl, VT, N0, 2108 DAG.getConstant(C1+1, N1.getValueType()), 2109 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2110 } 2111 2112 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2113 return DAG.getConstant(0, VT); // X < MIN --> false 2114 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 2115 return DAG.getConstant(1, VT); // X >= MIN --> true 2116 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 2117 return DAG.getConstant(0, VT); // X > MAX --> false 2118 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 2119 return DAG.getConstant(1, VT); // X <= MAX --> true 2120 2121 // Canonicalize setgt X, Min --> setne X, Min 2122 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2123 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2124 // Canonicalize setlt X, Max --> setne X, Max 2125 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2126 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2127 2128 // If we have setult X, 1, turn it into seteq X, 0 2129 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2130 return DAG.getSetCC(dl, VT, N0, 2131 DAG.getConstant(MinVal, N0.getValueType()), 2132 ISD::SETEQ); 2133 // If we have setugt X, Max-1, turn it into seteq X, Max 2134 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2135 return DAG.getSetCC(dl, VT, N0, 2136 DAG.getConstant(MaxVal, N0.getValueType()), 2137 ISD::SETEQ); 2138 2139 // If we have "setcc X, C0", check to see if we can shrink the immediate 2140 // by changing cc. 2141 2142 // SETUGT X, SINTMAX -> SETLT X, 0 2143 if (Cond == ISD::SETUGT && 2144 C1 == APInt::getSignedMaxValue(OperandBitSize)) 2145 return DAG.getSetCC(dl, VT, N0, 2146 DAG.getConstant(0, N1.getValueType()), 2147 ISD::SETLT); 2148 2149 // SETULT X, SINTMIN -> SETGT X, -1 2150 if (Cond == ISD::SETULT && 2151 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2152 SDValue ConstMinusOne = 2153 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2154 N1.getValueType()); 2155 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2156 } 2157 2158 // Fold bit comparisons when we can. 2159 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2160 (VT == N0.getValueType() || 2161 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2162 N0.getOpcode() == ISD::AND) 2163 if (ConstantSDNode *AndRHS = 2164 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2165 EVT ShiftTy = DCI.isBeforeLegalize() ? 2166 getPointerTy() : getShiftAmountTy(); 2167 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2168 // Perform the xform if the AND RHS is a single bit. 2169 if (AndRHS->getAPIntValue().isPowerOf2()) { 2170 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2171 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2172 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2173 } 2174 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2175 // (X & 8) == 8 --> (X & 8) >> 3 2176 // Perform the xform if C1 is a single bit. 2177 if (C1.isPowerOf2()) { 2178 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2179 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2180 DAG.getConstant(C1.logBase2(), ShiftTy))); 2181 } 2182 } 2183 } 2184 } 2185 2186 if (isa<ConstantFPSDNode>(N0.getNode())) { 2187 // Constant fold or commute setcc. 2188 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2189 if (O.getNode()) return O; 2190 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2191 // If the RHS of an FP comparison is a constant, simplify it away in 2192 // some cases. 2193 if (CFP->getValueAPF().isNaN()) { 2194 // If an operand is known to be a nan, we can fold it. 2195 switch (ISD::getUnorderedFlavor(Cond)) { 2196 default: llvm_unreachable("Unknown flavor!"); 2197 case 0: // Known false. 2198 return DAG.getConstant(0, VT); 2199 case 1: // Known true. 2200 return DAG.getConstant(1, VT); 2201 case 2: // Undefined. 2202 return DAG.getUNDEF(VT); 2203 } 2204 } 2205 2206 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2207 // constant if knowing that the operand is non-nan is enough. We prefer to 2208 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2209 // materialize 0.0. 2210 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2211 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2212 2213 // If the condition is not legal, see if we can find an equivalent one 2214 // which is legal. 2215 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2216 // If the comparison was an awkward floating-point == or != and one of 2217 // the comparison operands is infinity or negative infinity, convert the 2218 // condition to a less-awkward <= or >=. 2219 if (CFP->getValueAPF().isInfinity()) { 2220 if (CFP->getValueAPF().isNegative()) { 2221 if (Cond == ISD::SETOEQ && 2222 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2223 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2224 if (Cond == ISD::SETUEQ && 2225 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2226 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2227 if (Cond == ISD::SETUNE && 2228 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2229 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2230 if (Cond == ISD::SETONE && 2231 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2232 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2233 } else { 2234 if (Cond == ISD::SETOEQ && 2235 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2236 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2237 if (Cond == ISD::SETUEQ && 2238 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2239 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2240 if (Cond == ISD::SETUNE && 2241 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2242 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2243 if (Cond == ISD::SETONE && 2244 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2245 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2246 } 2247 } 2248 } 2249 } 2250 2251 if (N0 == N1) { 2252 // We can always fold X == X for integer setcc's. 2253 if (N0.getValueType().isInteger()) 2254 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2255 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2256 if (UOF == 2) // FP operators that are undefined on NaNs. 2257 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2258 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2259 return DAG.getConstant(UOF, VT); 2260 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2261 // if it is not already. 2262 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2263 if (NewCond != Cond) 2264 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2265 } 2266 2267 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2268 N0.getValueType().isInteger()) { 2269 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2270 N0.getOpcode() == ISD::XOR) { 2271 // Simplify (X+Y) == (X+Z) --> Y == Z 2272 if (N0.getOpcode() == N1.getOpcode()) { 2273 if (N0.getOperand(0) == N1.getOperand(0)) 2274 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2275 if (N0.getOperand(1) == N1.getOperand(1)) 2276 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2277 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2278 // If X op Y == Y op X, try other combinations. 2279 if (N0.getOperand(0) == N1.getOperand(1)) 2280 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2281 Cond); 2282 if (N0.getOperand(1) == N1.getOperand(0)) 2283 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2284 Cond); 2285 } 2286 } 2287 2288 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2289 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2290 // Turn (X+C1) == C2 --> X == C2-C1 2291 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2292 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2293 DAG.getConstant(RHSC->getAPIntValue()- 2294 LHSR->getAPIntValue(), 2295 N0.getValueType()), Cond); 2296 } 2297 2298 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2299 if (N0.getOpcode() == ISD::XOR) 2300 // If we know that all of the inverted bits are zero, don't bother 2301 // performing the inversion. 2302 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2303 return 2304 DAG.getSetCC(dl, VT, N0.getOperand(0), 2305 DAG.getConstant(LHSR->getAPIntValue() ^ 2306 RHSC->getAPIntValue(), 2307 N0.getValueType()), 2308 Cond); 2309 } 2310 2311 // Turn (C1-X) == C2 --> X == C1-C2 2312 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2313 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2314 return 2315 DAG.getSetCC(dl, VT, N0.getOperand(1), 2316 DAG.getConstant(SUBC->getAPIntValue() - 2317 RHSC->getAPIntValue(), 2318 N0.getValueType()), 2319 Cond); 2320 } 2321 } 2322 } 2323 2324 // Simplify (X+Z) == X --> Z == 0 2325 if (N0.getOperand(0) == N1) 2326 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2327 DAG.getConstant(0, N0.getValueType()), Cond); 2328 if (N0.getOperand(1) == N1) { 2329 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2330 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2331 DAG.getConstant(0, N0.getValueType()), Cond); 2332 else if (N0.getNode()->hasOneUse()) { 2333 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2334 // (Z-X) == X --> Z == X<<1 2335 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2336 N1, 2337 DAG.getConstant(1, getShiftAmountTy())); 2338 if (!DCI.isCalledByLegalizer()) 2339 DCI.AddToWorklist(SH.getNode()); 2340 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2341 } 2342 } 2343 } 2344 2345 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2346 N1.getOpcode() == ISD::XOR) { 2347 // Simplify X == (X+Z) --> Z == 0 2348 if (N1.getOperand(0) == N0) { 2349 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2350 DAG.getConstant(0, N1.getValueType()), Cond); 2351 } else if (N1.getOperand(1) == N0) { 2352 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2353 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2354 DAG.getConstant(0, N1.getValueType()), Cond); 2355 } else if (N1.getNode()->hasOneUse()) { 2356 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2357 // X == (Z-X) --> X<<1 == Z 2358 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2359 DAG.getConstant(1, getShiftAmountTy())); 2360 if (!DCI.isCalledByLegalizer()) 2361 DCI.AddToWorklist(SH.getNode()); 2362 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2363 } 2364 } 2365 } 2366 2367 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2368 // Note that where y is variable and is known to have at most 2369 // one bit set (for example, if it is z&1) we cannot do this; 2370 // the expressions are not equivalent when y==0. 2371 if (N0.getOpcode() == ISD::AND) 2372 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2373 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2374 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2375 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2376 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2377 } 2378 } 2379 if (N1.getOpcode() == ISD::AND) 2380 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2381 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2382 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2383 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2384 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2385 } 2386 } 2387 } 2388 2389 // Fold away ALL boolean setcc's. 2390 SDValue Temp; 2391 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2392 switch (Cond) { 2393 default: llvm_unreachable("Unknown integer setcc!"); 2394 case ISD::SETEQ: // X == Y -> ~(X^Y) 2395 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2396 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2397 if (!DCI.isCalledByLegalizer()) 2398 DCI.AddToWorklist(Temp.getNode()); 2399 break; 2400 case ISD::SETNE: // X != Y --> (X^Y) 2401 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2402 break; 2403 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2404 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2405 Temp = DAG.getNOT(dl, N0, MVT::i1); 2406 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2407 if (!DCI.isCalledByLegalizer()) 2408 DCI.AddToWorklist(Temp.getNode()); 2409 break; 2410 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2411 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2412 Temp = DAG.getNOT(dl, N1, MVT::i1); 2413 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2414 if (!DCI.isCalledByLegalizer()) 2415 DCI.AddToWorklist(Temp.getNode()); 2416 break; 2417 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2418 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2419 Temp = DAG.getNOT(dl, N0, MVT::i1); 2420 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2421 if (!DCI.isCalledByLegalizer()) 2422 DCI.AddToWorklist(Temp.getNode()); 2423 break; 2424 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2425 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2426 Temp = DAG.getNOT(dl, N1, MVT::i1); 2427 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2428 break; 2429 } 2430 if (VT != MVT::i1) { 2431 if (!DCI.isCalledByLegalizer()) 2432 DCI.AddToWorklist(N0.getNode()); 2433 // FIXME: If running after legalize, we probably can't do this. 2434 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2435 } 2436 return N0; 2437 } 2438 2439 // Could not fold it. 2440 return SDValue(); 2441} 2442 2443/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2444/// node is a GlobalAddress + offset. 2445bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA, 2446 int64_t &Offset) const { 2447 if (isa<GlobalAddressSDNode>(N)) { 2448 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2449 GA = GASD->getGlobal(); 2450 Offset += GASD->getOffset(); 2451 return true; 2452 } 2453 2454 if (N->getOpcode() == ISD::ADD) { 2455 SDValue N1 = N->getOperand(0); 2456 SDValue N2 = N->getOperand(1); 2457 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2458 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2459 if (V) { 2460 Offset += V->getSExtValue(); 2461 return true; 2462 } 2463 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2464 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2465 if (V) { 2466 Offset += V->getSExtValue(); 2467 return true; 2468 } 2469 } 2470 } 2471 return false; 2472} 2473 2474 2475SDValue TargetLowering:: 2476PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2477 // Default implementation: no optimization. 2478 return SDValue(); 2479} 2480 2481//===----------------------------------------------------------------------===// 2482// Inline Assembler Implementation Methods 2483//===----------------------------------------------------------------------===// 2484 2485 2486TargetLowering::ConstraintType 2487TargetLowering::getConstraintType(const std::string &Constraint) const { 2488 // FIXME: lots more standard ones to handle. 2489 if (Constraint.size() == 1) { 2490 switch (Constraint[0]) { 2491 default: break; 2492 case 'r': return C_RegisterClass; 2493 case 'm': // memory 2494 case 'o': // offsetable 2495 case 'V': // not offsetable 2496 return C_Memory; 2497 case 'i': // Simple Integer or Relocatable Constant 2498 case 'n': // Simple Integer 2499 case 'E': // Floating Point Constant 2500 case 'F': // Floating Point Constant 2501 case 's': // Relocatable Constant 2502 case 'p': // Address. 2503 case 'X': // Allow ANY value. 2504 case 'I': // Target registers. 2505 case 'J': 2506 case 'K': 2507 case 'L': 2508 case 'M': 2509 case 'N': 2510 case 'O': 2511 case 'P': 2512 case '<': 2513 case '>': 2514 return C_Other; 2515 } 2516 } 2517 2518 if (Constraint.size() > 1 && Constraint[0] == '{' && 2519 Constraint[Constraint.size()-1] == '}') 2520 return C_Register; 2521 return C_Unknown; 2522} 2523 2524/// LowerXConstraint - try to replace an X constraint, which matches anything, 2525/// with another that has more specific requirements based on the type of the 2526/// corresponding operand. 2527const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2528 if (ConstraintVT.isInteger()) 2529 return "r"; 2530 if (ConstraintVT.isFloatingPoint()) 2531 return "f"; // works for many targets 2532 return 0; 2533} 2534 2535/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2536/// vector. If it is invalid, don't add anything to Ops. 2537void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2538 char ConstraintLetter, 2539 std::vector<SDValue> &Ops, 2540 SelectionDAG &DAG) const { 2541 switch (ConstraintLetter) { 2542 default: break; 2543 case 'X': // Allows any operand; labels (basic block) use this. 2544 if (Op.getOpcode() == ISD::BasicBlock) { 2545 Ops.push_back(Op); 2546 return; 2547 } 2548 // fall through 2549 case 'i': // Simple Integer or Relocatable Constant 2550 case 'n': // Simple Integer 2551 case 's': { // Relocatable Constant 2552 // These operands are interested in values of the form (GV+C), where C may 2553 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2554 // is possible and fine if either GV or C are missing. 2555 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2556 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2557 2558 // If we have "(add GV, C)", pull out GV/C 2559 if (Op.getOpcode() == ISD::ADD) { 2560 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2561 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2562 if (C == 0 || GA == 0) { 2563 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2564 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2565 } 2566 if (C == 0 || GA == 0) 2567 C = 0, GA = 0; 2568 } 2569 2570 // If we find a valid operand, map to the TargetXXX version so that the 2571 // value itself doesn't get selected. 2572 if (GA) { // Either &GV or &GV+C 2573 if (ConstraintLetter != 'n') { 2574 int64_t Offs = GA->getOffset(); 2575 if (C) Offs += C->getZExtValue(); 2576 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2577 C ? C->getDebugLoc() : DebugLoc(), 2578 Op.getValueType(), Offs)); 2579 return; 2580 } 2581 } 2582 if (C) { // just C, no GV. 2583 // Simple constants are not allowed for 's'. 2584 if (ConstraintLetter != 's') { 2585 // gcc prints these as sign extended. Sign extend value to 64 bits 2586 // now; without this it would get ZExt'd later in 2587 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2588 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2589 MVT::i64)); 2590 return; 2591 } 2592 } 2593 break; 2594 } 2595 } 2596} 2597 2598std::vector<unsigned> TargetLowering:: 2599getRegClassForInlineAsmConstraint(const std::string &Constraint, 2600 EVT VT) const { 2601 return std::vector<unsigned>(); 2602} 2603 2604 2605std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2606getRegForInlineAsmConstraint(const std::string &Constraint, 2607 EVT VT) const { 2608 if (Constraint[0] != '{') 2609 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2610 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2611 2612 // Remove the braces from around the name. 2613 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2614 2615 // Figure out which register class contains this reg. 2616 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2617 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2618 E = RI->regclass_end(); RCI != E; ++RCI) { 2619 const TargetRegisterClass *RC = *RCI; 2620 2621 // If none of the value types for this register class are valid, we 2622 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2623 bool isLegal = false; 2624 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2625 I != E; ++I) { 2626 if (isTypeLegal(*I)) { 2627 isLegal = true; 2628 break; 2629 } 2630 } 2631 2632 if (!isLegal) continue; 2633 2634 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2635 I != E; ++I) { 2636 if (RegName.equals_lower(RI->getName(*I))) 2637 return std::make_pair(*I, RC); 2638 } 2639 } 2640 2641 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2642} 2643 2644//===----------------------------------------------------------------------===// 2645// Constraint Selection. 2646 2647/// isMatchingInputConstraint - Return true of this is an input operand that is 2648/// a matching constraint like "4". 2649bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2650 assert(!ConstraintCode.empty() && "No known constraint!"); 2651 return isdigit(ConstraintCode[0]); 2652} 2653 2654/// getMatchedOperand - If this is an input matching constraint, this method 2655/// returns the output operand it matches. 2656unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2657 assert(!ConstraintCode.empty() && "No known constraint!"); 2658 return atoi(ConstraintCode.c_str()); 2659} 2660 2661 2662/// ParseConstraints - Split up the constraint string from the inline 2663/// assembly value into the specific constraints and their prefixes, 2664/// and also tie in the associated operand values. 2665/// If this returns an empty vector, and if the constraint string itself 2666/// isn't empty, there was an error parsing. 2667TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2668 ImmutableCallSite CS) const { 2669 /// ConstraintOperands - Information about all of the constraints. 2670 AsmOperandInfoVector ConstraintOperands; 2671 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2672 unsigned maCount = 0; // Largest number of multiple alternative constraints. 2673 2674 // Do a prepass over the constraints, canonicalizing them, and building up the 2675 // ConstraintOperands list. 2676 InlineAsm::ConstraintInfoVector 2677 ConstraintInfos = IA->ParseConstraints(); 2678 2679 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2680 unsigned ResNo = 0; // ResNo - The result number of the next output. 2681 2682 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 2683 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 2684 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2685 2686 // Update multiple alternative constraint count. 2687 if (OpInfo.multipleAlternatives.size() > maCount) 2688 maCount = OpInfo.multipleAlternatives.size(); 2689 2690 OpInfo.ConstraintVT = MVT::Other; 2691 2692 // Compute the value type for each operand. 2693 switch (OpInfo.Type) { 2694 case InlineAsm::isOutput: 2695 // Indirect outputs just consume an argument. 2696 if (OpInfo.isIndirect) { 2697 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2698 break; 2699 } 2700 2701 // The return value of the call is this value. As such, there is no 2702 // corresponding argument. 2703 assert(!CS.getType()->isVoidTy() && 2704 "Bad inline asm!"); 2705 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 2706 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo)); 2707 } else { 2708 assert(ResNo == 0 && "Asm only has one result!"); 2709 OpInfo.ConstraintVT = getValueType(CS.getType()); 2710 } 2711 ++ResNo; 2712 break; 2713 case InlineAsm::isInput: 2714 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2715 break; 2716 case InlineAsm::isClobber: 2717 // Nothing to do. 2718 break; 2719 } 2720 2721 if (OpInfo.CallOperandVal) { 2722 const llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2723 if (OpInfo.isIndirect) { 2724 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2725 if (!PtrTy) 2726 report_fatal_error("Indirect operand for inline asm not a pointer!"); 2727 OpTy = PtrTy->getElementType(); 2728 } 2729 // If OpTy is not a single value, it may be a struct/union that we 2730 // can tile with integers. 2731 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2732 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 2733 switch (BitSize) { 2734 default: break; 2735 case 1: 2736 case 8: 2737 case 16: 2738 case 32: 2739 case 64: 2740 case 128: 2741 OpInfo.ConstraintVT = 2742 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true); 2743 break; 2744 } 2745 } else if (dyn_cast<PointerType>(OpTy)) { 2746 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize()); 2747 } else { 2748 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true); 2749 } 2750 } 2751 } 2752 2753 // If we have multiple alternative constraints, select the best alternative. 2754 if (ConstraintInfos.size()) { 2755 if (maCount) { 2756 unsigned bestMAIndex = 0; 2757 int bestWeight = -1; 2758 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2759 int weight = -1; 2760 unsigned maIndex; 2761 // Compute the sums of the weights for each alternative, keeping track 2762 // of the best (highest weight) one so far. 2763 for (maIndex = 0; maIndex < maCount; ++maIndex) { 2764 int weightSum = 0; 2765 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2766 cIndex != eIndex; ++cIndex) { 2767 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2768 if (OpInfo.Type == InlineAsm::isClobber) 2769 continue; 2770 2771 // If this is an output operand with a matching input operand, 2772 // look up the matching input. If their types mismatch, e.g. one 2773 // is an integer, the other is floating point, or their sizes are 2774 // different, flag it as an maCantMatch. 2775 if (OpInfo.hasMatchingInput()) { 2776 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2777 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2778 if ((OpInfo.ConstraintVT.isInteger() != 2779 Input.ConstraintVT.isInteger()) || 2780 (OpInfo.ConstraintVT.getSizeInBits() != 2781 Input.ConstraintVT.getSizeInBits())) { 2782 weightSum = -1; // Can't match. 2783 break; 2784 } 2785 } 2786 } 2787 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 2788 if (weight == -1) { 2789 weightSum = -1; 2790 break; 2791 } 2792 weightSum += weight; 2793 } 2794 // Update best. 2795 if (weightSum > bestWeight) { 2796 bestWeight = weightSum; 2797 bestMAIndex = maIndex; 2798 } 2799 } 2800 2801 // Now select chosen alternative in each constraint. 2802 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2803 cIndex != eIndex; ++cIndex) { 2804 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 2805 if (cInfo.Type == InlineAsm::isClobber) 2806 continue; 2807 cInfo.selectAlternative(bestMAIndex); 2808 } 2809 } 2810 } 2811 2812 // Check and hook up tied operands, choose constraint code to use. 2813 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2814 cIndex != eIndex; ++cIndex) { 2815 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2816 2817 // If this is an output operand with a matching input operand, look up the 2818 // matching input. If their types mismatch, e.g. one is an integer, the 2819 // other is floating point, or their sizes are different, flag it as an 2820 // error. 2821 if (OpInfo.hasMatchingInput()) { 2822 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2823 2824 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2825 if ((OpInfo.ConstraintVT.isInteger() != 2826 Input.ConstraintVT.isInteger()) || 2827 (OpInfo.ConstraintVT.getSizeInBits() != 2828 Input.ConstraintVT.getSizeInBits())) { 2829 report_fatal_error("Unsupported asm: input constraint" 2830 " with a matching output constraint of" 2831 " incompatible type!"); 2832 } 2833 } 2834 2835 } 2836 } 2837 2838 return ConstraintOperands; 2839} 2840 2841 2842/// getConstraintGenerality - Return an integer indicating how general CT 2843/// is. 2844static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2845 switch (CT) { 2846 default: llvm_unreachable("Unknown constraint type!"); 2847 case TargetLowering::C_Other: 2848 case TargetLowering::C_Unknown: 2849 return 0; 2850 case TargetLowering::C_Register: 2851 return 1; 2852 case TargetLowering::C_RegisterClass: 2853 return 2; 2854 case TargetLowering::C_Memory: 2855 return 3; 2856 } 2857} 2858 2859/// Examine constraint type and operand type and determine a weight value. 2860/// This object must already have been set up with the operand type 2861/// and the current alternative constraint selected. 2862TargetLowering::ConstraintWeight 2863 TargetLowering::getMultipleConstraintMatchWeight( 2864 AsmOperandInfo &info, int maIndex) const { 2865 InlineAsm::ConstraintCodeVector *rCodes; 2866 if (maIndex >= (int)info.multipleAlternatives.size()) 2867 rCodes = &info.Codes; 2868 else 2869 rCodes = &info.multipleAlternatives[maIndex].Codes; 2870 ConstraintWeight BestWeight = CW_Invalid; 2871 2872 // Loop over the options, keeping track of the most general one. 2873 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 2874 ConstraintWeight weight = 2875 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 2876 if (weight > BestWeight) 2877 BestWeight = weight; 2878 } 2879 2880 return BestWeight; 2881} 2882 2883/// Examine constraint type and operand type and determine a weight value. 2884/// This object must already have been set up with the operand type 2885/// and the current alternative constraint selected. 2886TargetLowering::ConstraintWeight 2887 TargetLowering::getSingleConstraintMatchWeight( 2888 AsmOperandInfo &info, const char *constraint) const { 2889 ConstraintWeight weight = CW_Invalid; 2890 Value *CallOperandVal = info.CallOperandVal; 2891 // If we don't have a value, we can't do a match, 2892 // but allow it at the lowest weight. 2893 if (CallOperandVal == NULL) 2894 return CW_Default; 2895 // Look at the constraint type. 2896 switch (*constraint) { 2897 case 'i': // immediate integer. 2898 case 'n': // immediate integer with a known value. 2899 if (isa<ConstantInt>(CallOperandVal)) 2900 weight = CW_Constant; 2901 break; 2902 case 's': // non-explicit intregal immediate. 2903 if (isa<GlobalValue>(CallOperandVal)) 2904 weight = CW_Constant; 2905 break; 2906 case 'E': // immediate float if host format. 2907 case 'F': // immediate float. 2908 if (isa<ConstantFP>(CallOperandVal)) 2909 weight = CW_Constant; 2910 break; 2911 case '<': // memory operand with autodecrement. 2912 case '>': // memory operand with autoincrement. 2913 case 'm': // memory operand. 2914 case 'o': // offsettable memory operand 2915 case 'V': // non-offsettable memory operand 2916 weight = CW_Memory; 2917 break; 2918 case 'r': // general register. 2919 case 'g': // general register, memory operand or immediate integer. 2920 // note: Clang converts "g" to "imr". 2921 if (CallOperandVal->getType()->isIntegerTy()) 2922 weight = CW_Register; 2923 break; 2924 case 'X': // any operand. 2925 default: 2926 weight = CW_Default; 2927 break; 2928 } 2929 return weight; 2930} 2931 2932/// ChooseConstraint - If there are multiple different constraints that we 2933/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2934/// This is somewhat tricky: constraints fall into four classes: 2935/// Other -> immediates and magic values 2936/// Register -> one specific register 2937/// RegisterClass -> a group of regs 2938/// Memory -> memory 2939/// Ideally, we would pick the most specific constraint possible: if we have 2940/// something that fits into a register, we would pick it. The problem here 2941/// is that if we have something that could either be in a register or in 2942/// memory that use of the register could cause selection of *other* 2943/// operands to fail: they might only succeed if we pick memory. Because of 2944/// this the heuristic we use is: 2945/// 2946/// 1) If there is an 'other' constraint, and if the operand is valid for 2947/// that constraint, use it. This makes us take advantage of 'i' 2948/// constraints when available. 2949/// 2) Otherwise, pick the most general constraint present. This prefers 2950/// 'm' over 'r', for example. 2951/// 2952static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2953 const TargetLowering &TLI, 2954 SDValue Op, SelectionDAG *DAG) { 2955 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2956 unsigned BestIdx = 0; 2957 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2958 int BestGenerality = -1; 2959 2960 // Loop over the options, keeping track of the most general one. 2961 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2962 TargetLowering::ConstraintType CType = 2963 TLI.getConstraintType(OpInfo.Codes[i]); 2964 2965 // If this is an 'other' constraint, see if the operand is valid for it. 2966 // For example, on X86 we might have an 'rI' constraint. If the operand 2967 // is an integer in the range [0..31] we want to use I (saving a load 2968 // of a register), otherwise we must use 'r'. 2969 if (CType == TargetLowering::C_Other && Op.getNode()) { 2970 assert(OpInfo.Codes[i].size() == 1 && 2971 "Unhandled multi-letter 'other' constraint"); 2972 std::vector<SDValue> ResultOps; 2973 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], 2974 ResultOps, *DAG); 2975 if (!ResultOps.empty()) { 2976 BestType = CType; 2977 BestIdx = i; 2978 break; 2979 } 2980 } 2981 2982 // Things with matching constraints can only be registers, per gcc 2983 // documentation. This mainly affects "g" constraints. 2984 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 2985 continue; 2986 2987 // This constraint letter is more general than the previous one, use it. 2988 int Generality = getConstraintGenerality(CType); 2989 if (Generality > BestGenerality) { 2990 BestType = CType; 2991 BestIdx = i; 2992 BestGenerality = Generality; 2993 } 2994 } 2995 2996 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2997 OpInfo.ConstraintType = BestType; 2998} 2999 3000/// ComputeConstraintToUse - Determines the constraint code and constraint 3001/// type to use for the specific AsmOperandInfo, setting 3002/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 3003void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 3004 SDValue Op, 3005 SelectionDAG *DAG) const { 3006 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 3007 3008 // Single-letter constraints ('r') are very common. 3009 if (OpInfo.Codes.size() == 1) { 3010 OpInfo.ConstraintCode = OpInfo.Codes[0]; 3011 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3012 } else { 3013 ChooseConstraint(OpInfo, *this, Op, DAG); 3014 } 3015 3016 // 'X' matches anything. 3017 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 3018 // Labels and constants are handled elsewhere ('X' is the only thing 3019 // that matches labels). For Functions, the type here is the type of 3020 // the result, which is not what we want to look at; leave them alone. 3021 Value *v = OpInfo.CallOperandVal; 3022 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 3023 OpInfo.CallOperandVal = v; 3024 return; 3025 } 3026 3027 // Otherwise, try to resolve it to something we know about by looking at 3028 // the actual operand type. 3029 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 3030 OpInfo.ConstraintCode = Repl; 3031 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3032 } 3033 } 3034} 3035 3036//===----------------------------------------------------------------------===// 3037// Loop Strength Reduction hooks 3038//===----------------------------------------------------------------------===// 3039 3040/// isLegalAddressingMode - Return true if the addressing mode represented 3041/// by AM is legal for this target, for a load/store of the specified type. 3042bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 3043 const Type *Ty) const { 3044 // The default implementation of this implements a conservative RISCy, r+r and 3045 // r+i addr mode. 3046 3047 // Allows a sign-extended 16-bit immediate field. 3048 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3049 return false; 3050 3051 // No global is ever allowed as a base. 3052 if (AM.BaseGV) 3053 return false; 3054 3055 // Only support r+r, 3056 switch (AM.Scale) { 3057 case 0: // "r+i" or just "i", depending on HasBaseReg. 3058 break; 3059 case 1: 3060 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3061 return false; 3062 // Otherwise we have r+r or r+i. 3063 break; 3064 case 2: 3065 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3066 return false; 3067 // Allow 2*r as r+r. 3068 break; 3069 } 3070 3071 return true; 3072} 3073 3074/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3075/// return a DAG expression to select that will generate the same value by 3076/// multiplying by a magic number. See: 3077/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3078SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 3079 std::vector<SDNode*>* Created) const { 3080 EVT VT = N->getValueType(0); 3081 DebugLoc dl= N->getDebugLoc(); 3082 3083 // Check to see if we can do this. 3084 // FIXME: We should be more aggressive here. 3085 if (!isTypeLegal(VT)) 3086 return SDValue(); 3087 3088 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3089 APInt::ms magics = d.magic(); 3090 3091 // Multiply the numerator (operand 0) by the magic value 3092 // FIXME: We should support doing a MUL in a wider type 3093 SDValue Q; 3094 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 3095 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 3096 DAG.getConstant(magics.m, VT)); 3097 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 3098 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 3099 N->getOperand(0), 3100 DAG.getConstant(magics.m, VT)).getNode(), 1); 3101 else 3102 return SDValue(); // No mulhs or equvialent 3103 // If d > 0 and m < 0, add the numerator 3104 if (d.isStrictlyPositive() && magics.m.isNegative()) { 3105 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 3106 if (Created) 3107 Created->push_back(Q.getNode()); 3108 } 3109 // If d < 0 and m > 0, subtract the numerator. 3110 if (d.isNegative() && magics.m.isStrictlyPositive()) { 3111 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 3112 if (Created) 3113 Created->push_back(Q.getNode()); 3114 } 3115 // Shift right algebraic if shift value is nonzero 3116 if (magics.s > 0) { 3117 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 3118 DAG.getConstant(magics.s, getShiftAmountTy())); 3119 if (Created) 3120 Created->push_back(Q.getNode()); 3121 } 3122 // Extract the sign bit and add it to the quotient 3123 SDValue T = 3124 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 3125 getShiftAmountTy())); 3126 if (Created) 3127 Created->push_back(T.getNode()); 3128 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 3129} 3130 3131/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3132/// return a DAG expression to select that will generate the same value by 3133/// multiplying by a magic number. See: 3134/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3135SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 3136 std::vector<SDNode*>* Created) const { 3137 EVT VT = N->getValueType(0); 3138 DebugLoc dl = N->getDebugLoc(); 3139 3140 // Check to see if we can do this. 3141 // FIXME: We should be more aggressive here. 3142 if (!isTypeLegal(VT)) 3143 return SDValue(); 3144 3145 // FIXME: We should use a narrower constant when the upper 3146 // bits are known to be zero. 3147 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 3148 APInt::mu magics = N1C->getAPIntValue().magicu(); 3149 3150 // Multiply the numerator (operand 0) by the magic value 3151 // FIXME: We should support doing a MUL in a wider type 3152 SDValue Q; 3153 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 3154 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 3155 DAG.getConstant(magics.m, VT)); 3156 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 3157 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 3158 N->getOperand(0), 3159 DAG.getConstant(magics.m, VT)).getNode(), 1); 3160 else 3161 return SDValue(); // No mulhu or equvialent 3162 if (Created) 3163 Created->push_back(Q.getNode()); 3164 3165 if (magics.a == 0) { 3166 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 3167 "We shouldn't generate an undefined shift!"); 3168 return DAG.getNode(ISD::SRL, dl, VT, Q, 3169 DAG.getConstant(magics.s, getShiftAmountTy())); 3170 } else { 3171 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 3172 if (Created) 3173 Created->push_back(NPQ.getNode()); 3174 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 3175 DAG.getConstant(1, getShiftAmountTy())); 3176 if (Created) 3177 Created->push_back(NPQ.getNode()); 3178 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 3179 if (Created) 3180 Created->push_back(NPQ.getNode()); 3181 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 3182 DAG.getConstant(magics.s-1, getShiftAmountTy())); 3183 } 3184} 3185