TargetLowering.cpp revision 09ad0b6894ae4eab9837970ccd4574681097eb6e 
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/MC/MCAsmInfo.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/Target/TargetData.h"
18#include "llvm/Target/TargetLoweringObjectFile.h"
19#include "llvm/Target/TargetMachine.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21#include "llvm/GlobalVariable.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/CodeGen/Analysis.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineJumpTableInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/SelectionDAG.h"
28#include "llvm/ADT/STLExtras.h"
29#include "llvm/Support/CommandLine.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/Support/MathExtras.h"
32#include <cctype>
33using namespace llvm;
34
35/// We are in the process of implementing a new TypeLegalization action
36/// - the promotion of vector elements. This feature is disabled by default
37/// and only enabled using this flag.
38static cl::opt<bool>
39AllowPromoteIntElem("promote-elements", cl::Hidden,
40  cl::desc("Allow promotion of integer vector element types"));
41
42namespace llvm {
43TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
44  bool isLocal = GV->hasLocalLinkage();
45  bool isDeclaration = GV->isDeclaration();
46  // FIXME: what should we do for protected and internal visibility?
47  // For variables, is internal different from hidden?
48  bool isHidden = GV->hasHiddenVisibility();
49
50  if (reloc == Reloc::PIC_) {
51    if (isLocal || isHidden)
52      return TLSModel::LocalDynamic;
53    else
54      return TLSModel::GeneralDynamic;
55  } else {
56    if (!isDeclaration || isHidden)
57      return TLSModel::LocalExec;
58    else
59      return TLSModel::InitialExec;
60  }
61}
62}
63
64/// InitLibcallNames - Set default libcall names.
65///
66static void InitLibcallNames(const char **Names) {
67  Names[RTLIB::SHL_I16] = "__ashlhi3";
68  Names[RTLIB::SHL_I32] = "__ashlsi3";
69  Names[RTLIB::SHL_I64] = "__ashldi3";
70  Names[RTLIB::SHL_I128] = "__ashlti3";
71  Names[RTLIB::SRL_I16] = "__lshrhi3";
72  Names[RTLIB::SRL_I32] = "__lshrsi3";
73  Names[RTLIB::SRL_I64] = "__lshrdi3";
74  Names[RTLIB::SRL_I128] = "__lshrti3";
75  Names[RTLIB::SRA_I16] = "__ashrhi3";
76  Names[RTLIB::SRA_I32] = "__ashrsi3";
77  Names[RTLIB::SRA_I64] = "__ashrdi3";
78  Names[RTLIB::SRA_I128] = "__ashrti3";
79  Names[RTLIB::MUL_I8] = "__mulqi3";
80  Names[RTLIB::MUL_I16] = "__mulhi3";
81  Names[RTLIB::MUL_I32] = "__mulsi3";
82  Names[RTLIB::MUL_I64] = "__muldi3";
83  Names[RTLIB::MUL_I128] = "__multi3";
84  Names[RTLIB::MULO_I32] = "__mulosi4";
85  Names[RTLIB::MULO_I64] = "__mulodi4";
86  Names[RTLIB::MULO_I128] = "__muloti4";
87  Names[RTLIB::SDIV_I8] = "__divqi3";
88  Names[RTLIB::SDIV_I16] = "__divhi3";
89  Names[RTLIB::SDIV_I32] = "__divsi3";
90  Names[RTLIB::SDIV_I64] = "__divdi3";
91  Names[RTLIB::SDIV_I128] = "__divti3";
92  Names[RTLIB::UDIV_I8] = "__udivqi3";
93  Names[RTLIB::UDIV_I16] = "__udivhi3";
94  Names[RTLIB::UDIV_I32] = "__udivsi3";
95  Names[RTLIB::UDIV_I64] = "__udivdi3";
96  Names[RTLIB::UDIV_I128] = "__udivti3";
97  Names[RTLIB::SREM_I8] = "__modqi3";
98  Names[RTLIB::SREM_I16] = "__modhi3";
99  Names[RTLIB::SREM_I32] = "__modsi3";
100  Names[RTLIB::SREM_I64] = "__moddi3";
101  Names[RTLIB::SREM_I128] = "__modti3";
102  Names[RTLIB::UREM_I8] = "__umodqi3";
103  Names[RTLIB::UREM_I16] = "__umodhi3";
104  Names[RTLIB::UREM_I32] = "__umodsi3";
105  Names[RTLIB::UREM_I64] = "__umoddi3";
106  Names[RTLIB::UREM_I128] = "__umodti3";
107
108  // These are generally not available.
109  Names[RTLIB::SDIVREM_I8] = 0;
110  Names[RTLIB::SDIVREM_I16] = 0;
111  Names[RTLIB::SDIVREM_I32] = 0;
112  Names[RTLIB::SDIVREM_I64] = 0;
113  Names[RTLIB::SDIVREM_I128] = 0;
114  Names[RTLIB::UDIVREM_I8] = 0;
115  Names[RTLIB::UDIVREM_I16] = 0;
116  Names[RTLIB::UDIVREM_I32] = 0;
117  Names[RTLIB::UDIVREM_I64] = 0;
118  Names[RTLIB::UDIVREM_I128] = 0;
119
120  Names[RTLIB::NEG_I32] = "__negsi2";
121  Names[RTLIB::NEG_I64] = "__negdi2";
122  Names[RTLIB::ADD_F32] = "__addsf3";
123  Names[RTLIB::ADD_F64] = "__adddf3";
124  Names[RTLIB::ADD_F80] = "__addxf3";
125  Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
126  Names[RTLIB::SUB_F32] = "__subsf3";
127  Names[RTLIB::SUB_F64] = "__subdf3";
128  Names[RTLIB::SUB_F80] = "__subxf3";
129  Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
130  Names[RTLIB::MUL_F32] = "__mulsf3";
131  Names[RTLIB::MUL_F64] = "__muldf3";
132  Names[RTLIB::MUL_F80] = "__mulxf3";
133  Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
134  Names[RTLIB::DIV_F32] = "__divsf3";
135  Names[RTLIB::DIV_F64] = "__divdf3";
136  Names[RTLIB::DIV_F80] = "__divxf3";
137  Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
138  Names[RTLIB::REM_F32] = "fmodf";
139  Names[RTLIB::REM_F64] = "fmod";
140  Names[RTLIB::REM_F80] = "fmodl";
141  Names[RTLIB::REM_PPCF128] = "fmodl";
142  Names[RTLIB::POWI_F32] = "__powisf2";
143  Names[RTLIB::POWI_F64] = "__powidf2";
144  Names[RTLIB::POWI_F80] = "__powixf2";
145  Names[RTLIB::POWI_PPCF128] = "__powitf2";
146  Names[RTLIB::SQRT_F32] = "sqrtf";
147  Names[RTLIB::SQRT_F64] = "sqrt";
148  Names[RTLIB::SQRT_F80] = "sqrtl";
149  Names[RTLIB::SQRT_PPCF128] = "sqrtl";
150  Names[RTLIB::LOG_F32] = "logf";
151  Names[RTLIB::LOG_F64] = "log";
152  Names[RTLIB::LOG_F80] = "logl";
153  Names[RTLIB::LOG_PPCF128] = "logl";
154  Names[RTLIB::LOG2_F32] = "log2f";
155  Names[RTLIB::LOG2_F64] = "log2";
156  Names[RTLIB::LOG2_F80] = "log2l";
157  Names[RTLIB::LOG2_PPCF128] = "log2l";
158  Names[RTLIB::LOG10_F32] = "log10f";
159  Names[RTLIB::LOG10_F64] = "log10";
160  Names[RTLIB::LOG10_F80] = "log10l";
161  Names[RTLIB::LOG10_PPCF128] = "log10l";
162  Names[RTLIB::EXP_F32] = "expf";
163  Names[RTLIB::EXP_F64] = "exp";
164  Names[RTLIB::EXP_F80] = "expl";
165  Names[RTLIB::EXP_PPCF128] = "expl";
166  Names[RTLIB::EXP2_F32] = "exp2f";
167  Names[RTLIB::EXP2_F64] = "exp2";
168  Names[RTLIB::EXP2_F80] = "exp2l";
169  Names[RTLIB::EXP2_PPCF128] = "exp2l";
170  Names[RTLIB::SIN_F32] = "sinf";
171  Names[RTLIB::SIN_F64] = "sin";
172  Names[RTLIB::SIN_F80] = "sinl";
173  Names[RTLIB::SIN_PPCF128] = "sinl";
174  Names[RTLIB::COS_F32] = "cosf";
175  Names[RTLIB::COS_F64] = "cos";
176  Names[RTLIB::COS_F80] = "cosl";
177  Names[RTLIB::COS_PPCF128] = "cosl";
178  Names[RTLIB::POW_F32] = "powf";
179  Names[RTLIB::POW_F64] = "pow";
180  Names[RTLIB::POW_F80] = "powl";
181  Names[RTLIB::POW_PPCF128] = "powl";
182  Names[RTLIB::CEIL_F32] = "ceilf";
183  Names[RTLIB::CEIL_F64] = "ceil";
184  Names[RTLIB::CEIL_F80] = "ceill";
185  Names[RTLIB::CEIL_PPCF128] = "ceill";
186  Names[RTLIB::TRUNC_F32] = "truncf";
187  Names[RTLIB::TRUNC_F64] = "trunc";
188  Names[RTLIB::TRUNC_F80] = "truncl";
189  Names[RTLIB::TRUNC_PPCF128] = "truncl";
190  Names[RTLIB::RINT_F32] = "rintf";
191  Names[RTLIB::RINT_F64] = "rint";
192  Names[RTLIB::RINT_F80] = "rintl";
193  Names[RTLIB::RINT_PPCF128] = "rintl";
194  Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
195  Names[RTLIB::NEARBYINT_F64] = "nearbyint";
196  Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
197  Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
198  Names[RTLIB::FLOOR_F32] = "floorf";
199  Names[RTLIB::FLOOR_F64] = "floor";
200  Names[RTLIB::FLOOR_F80] = "floorl";
201  Names[RTLIB::FLOOR_PPCF128] = "floorl";
202  Names[RTLIB::COPYSIGN_F32] = "copysignf";
203  Names[RTLIB::COPYSIGN_F64] = "copysign";
204  Names[RTLIB::COPYSIGN_F80] = "copysignl";
205  Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
206  Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
207  Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
208  Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
209  Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
210  Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
211  Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
212  Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
213  Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
214  Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
215  Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
216  Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
217  Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
218  Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
219  Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
220  Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
221  Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
222  Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
223  Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
224  Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
225  Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
226  Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
227  Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
228  Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
229  Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
230  Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
231  Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
232  Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
233  Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
234  Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
235  Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
236  Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
237  Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
238  Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
239  Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
240  Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
241  Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
242  Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
243  Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
244  Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
245  Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
246  Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
247  Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
248  Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
249  Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
250  Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
251  Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
252  Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
253  Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
254  Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
255  Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
256  Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
257  Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
258  Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
259  Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
260  Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
261  Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
262  Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
263  Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
264  Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
265  Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
266  Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
267  Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
268  Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
269  Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
270  Names[RTLIB::OEQ_F32] = "__eqsf2";
271  Names[RTLIB::OEQ_F64] = "__eqdf2";
272  Names[RTLIB::UNE_F32] = "__nesf2";
273  Names[RTLIB::UNE_F64] = "__nedf2";
274  Names[RTLIB::OGE_F32] = "__gesf2";
275  Names[RTLIB::OGE_F64] = "__gedf2";
276  Names[RTLIB::OLT_F32] = "__ltsf2";
277  Names[RTLIB::OLT_F64] = "__ltdf2";
278  Names[RTLIB::OLE_F32] = "__lesf2";
279  Names[RTLIB::OLE_F64] = "__ledf2";
280  Names[RTLIB::OGT_F32] = "__gtsf2";
281  Names[RTLIB::OGT_F64] = "__gtdf2";
282  Names[RTLIB::UO_F32] = "__unordsf2";
283  Names[RTLIB::UO_F64] = "__unorddf2";
284  Names[RTLIB::O_F32] = "__unordsf2";
285  Names[RTLIB::O_F64] = "__unorddf2";
286  Names[RTLIB::MEMCPY] = "memcpy";
287  Names[RTLIB::MEMMOVE] = "memmove";
288  Names[RTLIB::MEMSET] = "memset";
289  Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
290  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
291  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
292  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
293  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
294  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
295  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
296  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
297  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
298  Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
299  Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
300  Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
301  Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
302  Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
303  Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
304  Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
305  Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
306  Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
307  Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
308  Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
309  Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
310  Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
311  Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
312  Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
313  Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
314  Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
315  Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
316  Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4";
317  Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
318  Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
319  Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
320  Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
321  Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
322}
323
324/// InitLibcallCallingConvs - Set default libcall CallingConvs.
325///
326static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
327  for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
328    CCs[i] = CallingConv::C;
329  }
330}
331
332/// getFPEXT - Return the FPEXT_*_* value for the given types, or
333/// UNKNOWN_LIBCALL if there is none.
334RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
335  if (OpVT == MVT::f32) {
336    if (RetVT == MVT::f64)
337      return FPEXT_F32_F64;
338  }
339
340  return UNKNOWN_LIBCALL;
341}
342
343/// getFPROUND - Return the FPROUND_*_* value for the given types, or
344/// UNKNOWN_LIBCALL if there is none.
345RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
346  if (RetVT == MVT::f32) {
347    if (OpVT == MVT::f64)
348      return FPROUND_F64_F32;
349    if (OpVT == MVT::f80)
350      return FPROUND_F80_F32;
351    if (OpVT == MVT::ppcf128)
352      return FPROUND_PPCF128_F32;
353  } else if (RetVT == MVT::f64) {
354    if (OpVT == MVT::f80)
355      return FPROUND_F80_F64;
356    if (OpVT == MVT::ppcf128)
357      return FPROUND_PPCF128_F64;
358  }
359
360  return UNKNOWN_LIBCALL;
361}
362
363/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
364/// UNKNOWN_LIBCALL if there is none.
365RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
366  if (OpVT == MVT::f32) {
367    if (RetVT == MVT::i8)
368      return FPTOSINT_F32_I8;
369    if (RetVT == MVT::i16)
370      return FPTOSINT_F32_I16;
371    if (RetVT == MVT::i32)
372      return FPTOSINT_F32_I32;
373    if (RetVT == MVT::i64)
374      return FPTOSINT_F32_I64;
375    if (RetVT == MVT::i128)
376      return FPTOSINT_F32_I128;
377  } else if (OpVT == MVT::f64) {
378    if (RetVT == MVT::i8)
379      return FPTOSINT_F64_I8;
380    if (RetVT == MVT::i16)
381      return FPTOSINT_F64_I16;
382    if (RetVT == MVT::i32)
383      return FPTOSINT_F64_I32;
384    if (RetVT == MVT::i64)
385      return FPTOSINT_F64_I64;
386    if (RetVT == MVT::i128)
387      return FPTOSINT_F64_I128;
388  } else if (OpVT == MVT::f80) {
389    if (RetVT == MVT::i32)
390      return FPTOSINT_F80_I32;
391    if (RetVT == MVT::i64)
392      return FPTOSINT_F80_I64;
393    if (RetVT == MVT::i128)
394      return FPTOSINT_F80_I128;
395  } else if (OpVT == MVT::ppcf128) {
396    if (RetVT == MVT::i32)
397      return FPTOSINT_PPCF128_I32;
398    if (RetVT == MVT::i64)
399      return FPTOSINT_PPCF128_I64;
400    if (RetVT == MVT::i128)
401      return FPTOSINT_PPCF128_I128;
402  }
403  return UNKNOWN_LIBCALL;
404}
405
406/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
407/// UNKNOWN_LIBCALL if there is none.
408RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
409  if (OpVT == MVT::f32) {
410    if (RetVT == MVT::i8)
411      return FPTOUINT_F32_I8;
412    if (RetVT == MVT::i16)
413      return FPTOUINT_F32_I16;
414    if (RetVT == MVT::i32)
415      return FPTOUINT_F32_I32;
416    if (RetVT == MVT::i64)
417      return FPTOUINT_F32_I64;
418    if (RetVT == MVT::i128)
419      return FPTOUINT_F32_I128;
420  } else if (OpVT == MVT::f64) {
421    if (RetVT == MVT::i8)
422      return FPTOUINT_F64_I8;
423    if (RetVT == MVT::i16)
424      return FPTOUINT_F64_I16;
425    if (RetVT == MVT::i32)
426      return FPTOUINT_F64_I32;
427    if (RetVT == MVT::i64)
428      return FPTOUINT_F64_I64;
429    if (RetVT == MVT::i128)
430      return FPTOUINT_F64_I128;
431  } else if (OpVT == MVT::f80) {
432    if (RetVT == MVT::i32)
433      return FPTOUINT_F80_I32;
434    if (RetVT == MVT::i64)
435      return FPTOUINT_F80_I64;
436    if (RetVT == MVT::i128)
437      return FPTOUINT_F80_I128;
438  } else if (OpVT == MVT::ppcf128) {
439    if (RetVT == MVT::i32)
440      return FPTOUINT_PPCF128_I32;
441    if (RetVT == MVT::i64)
442      return FPTOUINT_PPCF128_I64;
443    if (RetVT == MVT::i128)
444      return FPTOUINT_PPCF128_I128;
445  }
446  return UNKNOWN_LIBCALL;
447}
448
449/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
450/// UNKNOWN_LIBCALL if there is none.
451RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
452  if (OpVT == MVT::i32) {
453    if (RetVT == MVT::f32)
454      return SINTTOFP_I32_F32;
455    else if (RetVT == MVT::f64)
456      return SINTTOFP_I32_F64;
457    else if (RetVT == MVT::f80)
458      return SINTTOFP_I32_F80;
459    else if (RetVT == MVT::ppcf128)
460      return SINTTOFP_I32_PPCF128;
461  } else if (OpVT == MVT::i64) {
462    if (RetVT == MVT::f32)
463      return SINTTOFP_I64_F32;
464    else if (RetVT == MVT::f64)
465      return SINTTOFP_I64_F64;
466    else if (RetVT == MVT::f80)
467      return SINTTOFP_I64_F80;
468    else if (RetVT == MVT::ppcf128)
469      return SINTTOFP_I64_PPCF128;
470  } else if (OpVT == MVT::i128) {
471    if (RetVT == MVT::f32)
472      return SINTTOFP_I128_F32;
473    else if (RetVT == MVT::f64)
474      return SINTTOFP_I128_F64;
475    else if (RetVT == MVT::f80)
476      return SINTTOFP_I128_F80;
477    else if (RetVT == MVT::ppcf128)
478      return SINTTOFP_I128_PPCF128;
479  }
480  return UNKNOWN_LIBCALL;
481}
482
483/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
484/// UNKNOWN_LIBCALL if there is none.
485RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
486  if (OpVT == MVT::i32) {
487    if (RetVT == MVT::f32)
488      return UINTTOFP_I32_F32;
489    else if (RetVT == MVT::f64)
490      return UINTTOFP_I32_F64;
491    else if (RetVT == MVT::f80)
492      return UINTTOFP_I32_F80;
493    else if (RetVT == MVT::ppcf128)
494      return UINTTOFP_I32_PPCF128;
495  } else if (OpVT == MVT::i64) {
496    if (RetVT == MVT::f32)
497      return UINTTOFP_I64_F32;
498    else if (RetVT == MVT::f64)
499      return UINTTOFP_I64_F64;
500    else if (RetVT == MVT::f80)
501      return UINTTOFP_I64_F80;
502    else if (RetVT == MVT::ppcf128)
503      return UINTTOFP_I64_PPCF128;
504  } else if (OpVT == MVT::i128) {
505    if (RetVT == MVT::f32)
506      return UINTTOFP_I128_F32;
507    else if (RetVT == MVT::f64)
508      return UINTTOFP_I128_F64;
509    else if (RetVT == MVT::f80)
510      return UINTTOFP_I128_F80;
511    else if (RetVT == MVT::ppcf128)
512      return UINTTOFP_I128_PPCF128;
513  }
514  return UNKNOWN_LIBCALL;
515}
516
517/// InitCmpLibcallCCs - Set default comparison libcall CC.
518///
519static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
520  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
521  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
522  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
523  CCs[RTLIB::UNE_F32] = ISD::SETNE;
524  CCs[RTLIB::UNE_F64] = ISD::SETNE;
525  CCs[RTLIB::OGE_F32] = ISD::SETGE;
526  CCs[RTLIB::OGE_F64] = ISD::SETGE;
527  CCs[RTLIB::OLT_F32] = ISD::SETLT;
528  CCs[RTLIB::OLT_F64] = ISD::SETLT;
529  CCs[RTLIB::OLE_F32] = ISD::SETLE;
530  CCs[RTLIB::OLE_F64] = ISD::SETLE;
531  CCs[RTLIB::OGT_F32] = ISD::SETGT;
532  CCs[RTLIB::OGT_F64] = ISD::SETGT;
533  CCs[RTLIB::UO_F32] = ISD::SETNE;
534  CCs[RTLIB::UO_F64] = ISD::SETNE;
535  CCs[RTLIB::O_F32] = ISD::SETEQ;
536  CCs[RTLIB::O_F64] = ISD::SETEQ;
537}
538
539/// NOTE: The constructor takes ownership of TLOF.
540TargetLowering::TargetLowering(const TargetMachine &tm,
541                               const TargetLoweringObjectFile *tlof)
542  : TM(tm), TD(TM.getTargetData()), TLOF(*tlof),
543  mayPromoteElements(AllowPromoteIntElem) {
544  // All operations default to being supported.
545  memset(OpActions, 0, sizeof(OpActions));
546  memset(LoadExtActions, 0, sizeof(LoadExtActions));
547  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
548  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
549  memset(CondCodeActions, 0, sizeof(CondCodeActions));
550
551  // Set default actions for various operations.
552  for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
553    // Default all indexed load / store to expand.
554    for (unsigned IM = (unsigned)ISD::PRE_INC;
555         IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
556      setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
557      setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
558    }
559
560    // These operations default to expand.
561    setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
562    setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
563  }
564
565  // Most targets ignore the @llvm.prefetch intrinsic.
566  setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
567
568  // ConstantFP nodes default to expand.  Targets can either change this to
569  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
570  // to optimize expansions for certain constants.
571  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
572  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
573  setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
574
575  // These library functions default to expand.
576  setOperationAction(ISD::FLOG , MVT::f64, Expand);
577  setOperationAction(ISD::FLOG2, MVT::f64, Expand);
578  setOperationAction(ISD::FLOG10,MVT::f64, Expand);
579  setOperationAction(ISD::FEXP , MVT::f64, Expand);
580  setOperationAction(ISD::FEXP2, MVT::f64, Expand);
581  setOperationAction(ISD::FLOG , MVT::f32, Expand);
582  setOperationAction(ISD::FLOG2, MVT::f32, Expand);
583  setOperationAction(ISD::FLOG10,MVT::f32, Expand);
584  setOperationAction(ISD::FEXP , MVT::f32, Expand);
585  setOperationAction(ISD::FEXP2, MVT::f32, Expand);
586
587  // Default ISD::TRAP to expand (which turns it into abort).
588  setOperationAction(ISD::TRAP, MVT::Other, Expand);
589
590  IsLittleEndian = TD->isLittleEndian();
591  PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
592  memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
593  memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
594  maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
595  maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
596    = maxStoresPerMemmoveOptSize = 4;
597  benefitFromCodePlacementOpt = false;
598  UseUnderscoreSetJmp = false;
599  UseUnderscoreLongJmp = false;
600  SelectIsExpensive = false;
601  IntDivIsCheap = false;
602  Pow2DivIsCheap = false;
603  JumpIsExpensive = false;
604  StackPointerRegisterToSaveRestore = 0;
605  ExceptionPointerRegister = 0;
606  ExceptionSelectorRegister = 0;
607  BooleanContents = UndefinedBooleanContent;
608  SchedPreferenceInfo = Sched::Latency;
609  JumpBufSize = 0;
610  JumpBufAlignment = 0;
611  MinFunctionAlignment = 0;
612  PrefFunctionAlignment = 0;
613  PrefLoopAlignment = 0;
614  MinStackArgumentAlignment = 1;
615  ShouldFoldAtomicFences = false;
616
617  InitLibcallNames(LibcallRoutineNames);
618  InitCmpLibcallCCs(CmpLibcallCCs);
619  InitLibcallCallingConvs(LibcallCallingConvs);
620}
621
622TargetLowering::~TargetLowering() {
623  delete &TLOF;
624}
625
626MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
627  return MVT::getIntegerVT(8*TD->getPointerSize());
628}
629
630/// canOpTrap - Returns true if the operation can trap for the value type.
631/// VT must be a legal type.
632bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
633  assert(isTypeLegal(VT));
634  switch (Op) {
635  default:
636    return false;
637  case ISD::FDIV:
638  case ISD::FREM:
639  case ISD::SDIV:
640  case ISD::UDIV:
641  case ISD::SREM:
642  case ISD::UREM:
643    return true;
644  }
645}
646
647
648static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
649                                          unsigned &NumIntermediates,
650                                          EVT &RegisterVT,
651                                          TargetLowering *TLI) {
652  // Figure out the right, legal destination reg to copy into.
653  unsigned NumElts = VT.getVectorNumElements();
654  MVT EltTy = VT.getVectorElementType();
655
656  unsigned NumVectorRegs = 1;
657
658  // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally we
659  // could break down into LHS/RHS like LegalizeDAG does.
660  if (!isPowerOf2_32(NumElts)) {
661    NumVectorRegs = NumElts;
662    NumElts = 1;
663  }
664
665  // Divide the input until we get to a supported size.  This will always
666  // end with a scalar if the target doesn't support vectors.
667  while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
668    NumElts >>= 1;
669    NumVectorRegs <<= 1;
670  }
671
672  NumIntermediates = NumVectorRegs;
673
674  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
675  if (!TLI->isTypeLegal(NewVT))
676    NewVT = EltTy;
677  IntermediateVT = NewVT;
678
679  unsigned NewVTSize = NewVT.getSizeInBits();
680
681  // Convert sizes such as i33 to i64.
682  if (!isPowerOf2_32(NewVTSize))
683    NewVTSize = NextPowerOf2(NewVTSize);
684
685  EVT DestVT = TLI->getRegisterType(NewVT);
686  RegisterVT = DestVT;
687  if (EVT(DestVT).bitsLT(NewVT))    // Value is expanded, e.g. i64 -> i16.
688    return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
689
690  // Otherwise, promotion or legal types use the same number of registers as
691  // the vector decimated to the appropriate level.
692  return NumVectorRegs;
693}
694
695/// isLegalRC - Return true if the value types that can be represented by the
696/// specified register class are all legal.
697bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
698  for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
699       I != E; ++I) {
700    if (isTypeLegal(*I))
701      return true;
702  }
703  return false;
704}
705
706/// hasLegalSuperRegRegClasses - Return true if the specified register class
707/// has one or more super-reg register classes that are legal.
708bool
709TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
710  if (*RC->superregclasses_begin() == 0)
711    return false;
712  for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
713         E = RC->superregclasses_end(); I != E; ++I) {
714    const TargetRegisterClass *RRC = *I;
715    if (isLegalRC(RRC))
716      return true;
717  }
718  return false;
719}
720
721/// findRepresentativeClass - Return the largest legal super-reg register class
722/// of the register class for the specified type and its associated "cost".
723std::pair<const TargetRegisterClass*, uint8_t>
724TargetLowering::findRepresentativeClass(EVT VT) const {
725  const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
726  if (!RC)
727    return std::make_pair(RC, 0);
728  const TargetRegisterClass *BestRC = RC;
729  for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
730         E = RC->superregclasses_end(); I != E; ++I) {
731    const TargetRegisterClass *RRC = *I;
732    if (RRC->isASubClass() || !isLegalRC(RRC))
733      continue;
734    if (!hasLegalSuperRegRegClasses(RRC))
735      return std::make_pair(RRC, 1);
736    BestRC = RRC;
737  }
738  return std::make_pair(BestRC, 1);
739}
740
741
742/// computeRegisterProperties - Once all of the register classes are added,
743/// this allows us to compute derived properties we expose.
744void TargetLowering::computeRegisterProperties() {
745  assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
746         "Too many value types for ValueTypeActions to hold!");
747
748  // Everything defaults to needing one register.
749  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
750    NumRegistersForVT[i] = 1;
751    RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
752  }
753  // ...except isVoid, which doesn't need any registers.
754  NumRegistersForVT[MVT::isVoid] = 0;
755
756  // Find the largest integer register class.
757  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
758  for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
759    assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
760
761  // Every integer value type larger than this largest register takes twice as
762  // many registers to represent as the previous ValueType.
763  for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
764    EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
765    if (!ExpandedVT.isInteger())
766      break;
767    NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
768    RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
769    TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
770    ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger);
771  }
772
773  // Inspect all of the ValueType's smaller than the largest integer
774  // register to see which ones need promotion.
775  unsigned LegalIntReg = LargestIntReg;
776  for (unsigned IntReg = LargestIntReg - 1;
777       IntReg >= (unsigned)MVT::i1; --IntReg) {
778    EVT IVT = (MVT::SimpleValueType)IntReg;
779    if (isTypeLegal(IVT)) {
780      LegalIntReg = IntReg;
781    } else {
782      RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
783        (MVT::SimpleValueType)LegalIntReg;
784      ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
785    }
786  }
787
788  // ppcf128 type is really two f64's.
789  if (!isTypeLegal(MVT::ppcf128)) {
790    NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
791    RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
792    TransformToType[MVT::ppcf128] = MVT::f64;
793    ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
794  }
795
796  // Decide how to handle f64. If the target does not have native f64 support,
797  // expand it to i64 and we will be generating soft float library calls.
798  if (!isTypeLegal(MVT::f64)) {
799    NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
800    RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
801    TransformToType[MVT::f64] = MVT::i64;
802    ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
803  }
804
805  // Decide how to handle f32. If the target does not have native support for
806  // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
807  if (!isTypeLegal(MVT::f32)) {
808    if (isTypeLegal(MVT::f64)) {
809      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
810      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
811      TransformToType[MVT::f32] = MVT::f64;
812      ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
813    } else {
814      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
815      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
816      TransformToType[MVT::f32] = MVT::i32;
817      ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
818    }
819  }
820
821  // Loop over all of the vector value types to see which need transformations.
822  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
823       i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
824    MVT VT = (MVT::SimpleValueType)i;
825    if (isTypeLegal(VT)) continue;
826
827    // Determine if there is a legal wider type.  If so, we should promote to
828    // that wider vector type.
829    EVT EltVT = VT.getVectorElementType();
830    unsigned NElts = VT.getVectorNumElements();
831    if (NElts != 1) {
832      bool IsLegalWiderType = false;
833      // If we allow the promotion of vector elements using a flag,
834      // then return TypePromoteInteger on vector elements.
835      // First try to promote the elements of integer vectors. If no legal
836      // promotion was found, fallback to the widen-vector method.
837      if (mayPromoteElements)
838      for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
839        EVT SVT = (MVT::SimpleValueType)nVT;
840        // Promote vectors of integers to vectors with the same number
841        // of elements, with a wider element type.
842        if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
843            && SVT.getVectorNumElements() == NElts &&
844            isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
845          TransformToType[i] = SVT;
846          RegisterTypeForVT[i] = SVT;
847          NumRegistersForVT[i] = 1;
848          ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
849          IsLegalWiderType = true;
850          break;
851        }
852      }
853
854      if (IsLegalWiderType) continue;
855
856      // Try to widen the vector.
857      for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
858        EVT SVT = (MVT::SimpleValueType)nVT;
859        if (SVT.getVectorElementType() == EltVT &&
860            SVT.getVectorNumElements() > NElts &&
861            isTypeLegal(SVT)) {
862          TransformToType[i] = SVT;
863          RegisterTypeForVT[i] = SVT;
864          NumRegistersForVT[i] = 1;
865          ValueTypeActions.setTypeAction(VT, TypeWidenVector);
866          IsLegalWiderType = true;
867          break;
868        }
869      }
870      if (IsLegalWiderType) continue;
871    }
872
873    MVT IntermediateVT;
874    EVT RegisterVT;
875    unsigned NumIntermediates;
876    NumRegistersForVT[i] =
877      getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
878                                RegisterVT, this);
879    RegisterTypeForVT[i] = RegisterVT;
880
881    EVT NVT = VT.getPow2VectorType();
882    if (NVT == VT) {
883      // Type is already a power of 2.  The default action is to split.
884      TransformToType[i] = MVT::Other;
885      unsigned NumElts = VT.getVectorNumElements();
886      ValueTypeActions.setTypeAction(VT,
887            NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
888    } else {
889      TransformToType[i] = NVT;
890      ValueTypeActions.setTypeAction(VT, TypeWidenVector);
891    }
892  }
893
894  // Determine the 'representative' register class for each value type.
895  // An representative register class is the largest (meaning one which is
896  // not a sub-register class / subreg register class) legal register class for
897  // a group of value types. For example, on i386, i8, i16, and i32
898  // representative would be GR32; while on x86_64 it's GR64.
899  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
900    const TargetRegisterClass* RRC;
901    uint8_t Cost;
902    tie(RRC, Cost) =  findRepresentativeClass((MVT::SimpleValueType)i);
903    RepRegClassForVT[i] = RRC;
904    RepRegClassCostForVT[i] = Cost;
905  }
906}
907
908const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
909  return NULL;
910}
911
912
913MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
914  return PointerTy.SimpleTy;
915}
916
917MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
918  return MVT::i32; // return the default value
919}
920
921/// getVectorTypeBreakdown - Vector types are broken down into some number of
922/// legal first class types.  For example, MVT::v8f32 maps to 2 MVT::v4f32
923/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
924/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
925///
926/// This method returns the number of registers needed, and the VT for each
927/// register.  It also returns the VT and quantity of the intermediate values
928/// before they are promoted/expanded.
929///
930unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
931                                                EVT &IntermediateVT,
932                                                unsigned &NumIntermediates,
933                                                EVT &RegisterVT) const {
934  unsigned NumElts = VT.getVectorNumElements();
935
936  // If there is a wider vector type with the same element type as this one,
937  // we should widen to that legal vector type.  This handles things like
938  // <2 x float> -> <4 x float>.
939  if (NumElts != 1 && getTypeAction(Context, VT) == TypeWidenVector) {
940    RegisterVT = getTypeToTransformTo(Context, VT);
941    if (isTypeLegal(RegisterVT)) {
942      IntermediateVT = RegisterVT;
943      NumIntermediates = 1;
944      return 1;
945    }
946  }
947
948  // Figure out the right, legal destination reg to copy into.
949  EVT EltTy = VT.getVectorElementType();
950
951  unsigned NumVectorRegs = 1;
952
953  // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally we
954  // could break down into LHS/RHS like LegalizeDAG does.
955  if (!isPowerOf2_32(NumElts)) {
956    NumVectorRegs = NumElts;
957    NumElts = 1;
958  }
959
960  // Divide the input until we get to a supported size.  This will always
961  // end with a scalar if the target doesn't support vectors.
962  while (NumElts > 1 && !isTypeLegal(
963                                   EVT::getVectorVT(Context, EltTy, NumElts))) {
964    NumElts >>= 1;
965    NumVectorRegs <<= 1;
966  }
967
968  NumIntermediates = NumVectorRegs;
969
970  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
971  if (!isTypeLegal(NewVT))
972    NewVT = EltTy;
973  IntermediateVT = NewVT;
974
975  EVT DestVT = getRegisterType(Context, NewVT);
976  RegisterVT = DestVT;
977  unsigned NewVTSize = NewVT.getSizeInBits();
978
979  // Convert sizes such as i33 to i64.
980  if (!isPowerOf2_32(NewVTSize))
981    NewVTSize = NextPowerOf2(NewVTSize);
982
983  if (DestVT.bitsLT(NewVT))   // Value is expanded, e.g. i64 -> i16.
984    return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
985
986  // Otherwise, promotion or legal types use the same number of registers as
987  // the vector decimated to the appropriate level.
988  return NumVectorRegs;
989}
990
991/// Get the EVTs and ArgFlags collections that represent the legalized return
992/// type of the given function.  This does not require a DAG or a return value,
993/// and is suitable for use before any DAGs for the function are constructed.
994/// TODO: Move this out of TargetLowering.cpp.
995void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr,
996                         SmallVectorImpl<ISD::OutputArg> &Outs,
997                         const TargetLowering &TLI,
998                         SmallVectorImpl<uint64_t> *Offsets) {
999  SmallVector<EVT, 4> ValueVTs;
1000  ComputeValueVTs(TLI, ReturnType, ValueVTs);
1001  unsigned NumValues = ValueVTs.size();
1002  if (NumValues == 0) return;
1003  unsigned Offset = 0;
1004
1005  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1006    EVT VT = ValueVTs[j];
1007    ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1008
1009    if (attr & Attribute::SExt)
1010      ExtendKind = ISD::SIGN_EXTEND;
1011    else if (attr & Attribute::ZExt)
1012      ExtendKind = ISD::ZERO_EXTEND;
1013
1014    // FIXME: C calling convention requires the return type to be promoted to
1015    // at least 32-bit. But this is not necessary for non-C calling
1016    // conventions. The frontend should mark functions whose return values
1017    // require promoting with signext or zeroext attributes.
1018    if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1019      EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1020      if (VT.bitsLT(MinVT))
1021        VT = MinVT;
1022    }
1023
1024    unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1025    EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1026    unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
1027                        PartVT.getTypeForEVT(ReturnType->getContext()));
1028
1029    // 'inreg' on function refers to return value
1030    ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1031    if (attr & Attribute::InReg)
1032      Flags.setInReg();
1033
1034    // Propagate extension type if any
1035    if (attr & Attribute::SExt)
1036      Flags.setSExt();
1037    else if (attr & Attribute::ZExt)
1038      Flags.setZExt();
1039
1040    for (unsigned i = 0; i < NumParts; ++i) {
1041      Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
1042      if (Offsets) {
1043        Offsets->push_back(Offset);
1044        Offset += PartSize;
1045      }
1046    }
1047  }
1048}
1049
1050/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1051/// function arguments in the caller parameter area.  This is the actual
1052/// alignment, not its logarithm.
1053unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1054  return TD->getCallFrameTypeAlignment(Ty);
1055}
1056
1057/// getJumpTableEncoding - Return the entry encoding for a jump table in the
1058/// current function.  The returned value is a member of the
1059/// MachineJumpTableInfo::JTEntryKind enum.
1060unsigned TargetLowering::getJumpTableEncoding() const {
1061  // In non-pic modes, just use the address of a block.
1062  if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1063    return MachineJumpTableInfo::EK_BlockAddress;
1064
1065  // In PIC mode, if the target supports a GPRel32 directive, use it.
1066  if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1067    return MachineJumpTableInfo::EK_GPRel32BlockAddress;
1068
1069  // Otherwise, use a label difference.
1070  return MachineJumpTableInfo::EK_LabelDifference32;
1071}
1072
1073SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1074                                                 SelectionDAG &DAG) const {
1075  // If our PIC model is GP relative, use the global offset table as the base.
1076  if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
1077    return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1078  return Table;
1079}
1080
1081/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1082/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1083/// MCExpr.
1084const MCExpr *
1085TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1086                                             unsigned JTI,MCContext &Ctx) const{
1087  // The normal PIC reloc base is the label at the start of the jump table.
1088  return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
1089}
1090
1091bool
1092TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1093  // Assume that everything is safe in static mode.
1094  if (getTargetMachine().getRelocationModel() == Reloc::Static)
1095    return true;
1096
1097  // In dynamic-no-pic mode, assume that known defined values are safe.
1098  if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1099      GA &&
1100      !GA->getGlobal()->isDeclaration() &&
1101      !GA->getGlobal()->isWeakForLinker())
1102    return true;
1103
1104  // Otherwise assume nothing is safe.
1105  return false;
1106}
1107
1108//===----------------------------------------------------------------------===//
1109//  Optimization Methods
1110//===----------------------------------------------------------------------===//
1111
1112/// ShrinkDemandedConstant - Check to see if the specified operand of the
1113/// specified instruction is a constant integer.  If so, check to see if there
1114/// are any bits set in the constant that are not demanded.  If so, shrink the
1115/// constant and return true.
1116bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
1117                                                        const APInt &Demanded) {
1118  DebugLoc dl = Op.getDebugLoc();
1119
1120  // FIXME: ISD::SELECT, ISD::SELECT_CC
1121  switch (Op.getOpcode()) {
1122  default: break;
1123  case ISD::XOR:
1124  case ISD::AND:
1125  case ISD::OR: {
1126    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1127    if (!C) return false;
1128
1129    if (Op.getOpcode() == ISD::XOR &&
1130        (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1131      return false;
1132
1133    // if we can expand it to have all bits set, do it
1134    if (C->getAPIntValue().intersects(~Demanded)) {
1135      EVT VT = Op.getValueType();
1136      SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1137                                DAG.getConstant(Demanded &
1138                                                C->getAPIntValue(),
1139                                                VT));
1140      return CombineTo(Op, New);
1141    }
1142
1143    break;
1144  }
1145  }
1146
1147  return false;
1148}
1149
1150/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1151/// casts are free.  This uses isZExtFree and ZERO_EXTEND for the widening
1152/// cast, but it could be generalized for targets with other types of
1153/// implicit widening casts.
1154bool
1155TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1156                                                    unsigned BitWidth,
1157                                                    const APInt &Demanded,
1158                                                    DebugLoc dl) {
1159  assert(Op.getNumOperands() == 2 &&
1160         "ShrinkDemandedOp only supports binary operators!");
1161  assert(Op.getNode()->getNumValues() == 1 &&
1162         "ShrinkDemandedOp only supports nodes with one result!");
1163
1164  // Don't do this if the node has another user, which may require the
1165  // full value.
1166  if (!Op.getNode()->hasOneUse())
1167    return false;
1168
1169  // Search for the smallest integer type with free casts to and from
1170  // Op's type. For expedience, just check power-of-2 integer types.
1171  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1172  unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1173  if (!isPowerOf2_32(SmallVTBits))
1174    SmallVTBits = NextPowerOf2(SmallVTBits);
1175  for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
1176    EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
1177    if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1178        TLI.isZExtFree(SmallVT, Op.getValueType())) {
1179      // We found a type with free casts.
1180      SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1181                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1182                                          Op.getNode()->getOperand(0)),
1183                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1184                                          Op.getNode()->getOperand(1)));
1185      SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1186      return CombineTo(Op, Z);
1187    }
1188  }
1189  return false;
1190}
1191
1192/// SimplifyDemandedBits - Look at Op.  At this point, we know that only the
1193/// DemandedMask bits of the result of Op are ever used downstream.  If we can
1194/// use this information to simplify Op, create a new simplified DAG node and
1195/// return true, returning the original and new nodes in Old and New. Otherwise,
1196/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1197/// the expression (used to simplify the caller).  The KnownZero/One bits may
1198/// only be accurate for those bits in the DemandedMask.
1199bool TargetLowering::SimplifyDemandedBits(SDValue Op,
1200                                          const APInt &DemandedMask,
1201                                          APInt &KnownZero,
1202                                          APInt &KnownOne,
1203                                          TargetLoweringOpt &TLO,
1204                                          unsigned Depth) const {
1205  unsigned BitWidth = DemandedMask.getBitWidth();
1206  assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
1207         "Mask size mismatches value type size!");
1208  APInt NewMask = DemandedMask;
1209  DebugLoc dl = Op.getDebugLoc();
1210
1211  // Don't know anything.
1212  KnownZero = KnownOne = APInt(BitWidth, 0);
1213
1214  // Other users may use these bits.
1215  if (!Op.getNode()->hasOneUse()) {
1216    if (Depth != 0) {
1217      // If not at the root, Just compute the KnownZero/KnownOne bits to
1218      // simplify things downstream.
1219      TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
1220      return false;
1221    }
1222    // If this is the root being simplified, allow it to have multiple uses,
1223    // just set the NewMask to all bits.
1224    NewMask = APInt::getAllOnesValue(BitWidth);
1225  } else if (DemandedMask == 0) {
1226    // Not demanding any bits from Op.
1227    if (Op.getOpcode() != ISD::UNDEF)
1228      return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
1229    return false;
1230  } else if (Depth == 6) {        // Limit search depth.
1231    return false;
1232  }
1233
1234  APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1235  switch (Op.getOpcode()) {
1236  case ISD::Constant:
1237    // We know all of the bits for a constant!
1238    KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1239    KnownZero = ~KnownOne & NewMask;
1240    return false;   // Don't fall through, will infinitely loop.
1241  case ISD::AND:
1242    // If the RHS is a constant, check to see if the LHS would be zero without
1243    // using the bits from the RHS.  Below, we use knowledge about the RHS to
1244    // simplify the LHS, here we're using information from the LHS to simplify
1245    // the RHS.
1246    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1247      APInt LHSZero, LHSOne;
1248      // Do not increment Depth here; that can cause an infinite loop.
1249      TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
1250                                LHSZero, LHSOne, Depth);
1251      // If the LHS already has zeros where RHSC does, this and is dead.
1252      if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1253        return TLO.CombineTo(Op, Op.getOperand(0));
1254      // If any of the set bits in the RHS are known zero on the LHS, shrink
1255      // the constant.
1256      if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1257        return true;
1258    }
1259
1260    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1261                             KnownOne, TLO, Depth+1))
1262      return true;
1263    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1264    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1265                             KnownZero2, KnownOne2, TLO, Depth+1))
1266      return true;
1267    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1268
1269    // If all of the demanded bits are known one on one side, return the other.
1270    // These bits cannot contribute to the result of the 'and'.
1271    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1272      return TLO.CombineTo(Op, Op.getOperand(0));
1273    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1274      return TLO.CombineTo(Op, Op.getOperand(1));
1275    // If all of the demanded bits in the inputs are known zeros, return zero.
1276    if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1277      return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1278    // If the RHS is a constant, see if we can simplify it.
1279    if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1280      return true;
1281    // If the operation can be done in a smaller type, do so.
1282    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1283      return true;
1284
1285    // Output known-1 bits are only known if set in both the LHS & RHS.
1286    KnownOne &= KnownOne2;
1287    // Output known-0 are known to be clear if zero in either the LHS | RHS.
1288    KnownZero |= KnownZero2;
1289    break;
1290  case ISD::OR:
1291    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1292                             KnownOne, TLO, Depth+1))
1293      return true;
1294    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1295    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1296                             KnownZero2, KnownOne2, TLO, Depth+1))
1297      return true;
1298    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1299
1300    // If all of the demanded bits are known zero on one side, return the other.
1301    // These bits cannot contribute to the result of the 'or'.
1302    if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1303      return TLO.CombineTo(Op, Op.getOperand(0));
1304    if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1305      return TLO.CombineTo(Op, Op.getOperand(1));
1306    // If all of the potentially set bits on one side are known to be set on
1307    // the other side, just use the 'other' side.
1308    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1309      return TLO.CombineTo(Op, Op.getOperand(0));
1310    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1311      return TLO.CombineTo(Op, Op.getOperand(1));
1312    // If the RHS is a constant, see if we can simplify it.
1313    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1314      return true;
1315    // If the operation can be done in a smaller type, do so.
1316    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1317      return true;
1318
1319    // Output known-0 bits are only known if clear in both the LHS & RHS.
1320    KnownZero &= KnownZero2;
1321    // Output known-1 are known to be set if set in either the LHS | RHS.
1322    KnownOne |= KnownOne2;
1323    break;
1324  case ISD::XOR:
1325    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1326                             KnownOne, TLO, Depth+1))
1327      return true;
1328    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1329    if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1330                             KnownOne2, TLO, Depth+1))
1331      return true;
1332    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1333
1334    // If all of the demanded bits are known zero on one side, return the other.
1335    // These bits cannot contribute to the result of the 'xor'.
1336    if ((KnownZero & NewMask) == NewMask)
1337      return TLO.CombineTo(Op, Op.getOperand(0));
1338    if ((KnownZero2 & NewMask) == NewMask)
1339      return TLO.CombineTo(Op, Op.getOperand(1));
1340    // If the operation can be done in a smaller type, do so.
1341    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1342      return true;
1343
1344    // If all of the unknown bits are known to be zero on one side or the other
1345    // (but not both) turn this into an *inclusive* or.
1346    //    e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1347    if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1348      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1349                                               Op.getOperand(0),
1350                                               Op.getOperand(1)));
1351
1352    // Output known-0 bits are known if clear or set in both the LHS & RHS.
1353    KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1354    // Output known-1 are known to be set if set in only one of the LHS, RHS.
1355    KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1356
1357    // If all of the demanded bits on one side are known, and all of the set
1358    // bits on that side are also known to be set on the other side, turn this
1359    // into an AND, as we know the bits will be cleared.
1360    //    e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1361    if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1362      if ((KnownOne & KnownOne2) == KnownOne) {
1363        EVT VT = Op.getValueType();
1364        SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1365        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1366                                                 Op.getOperand(0), ANDC));
1367      }
1368    }
1369
1370    // If the RHS is a constant, see if we can simplify it.
1371    // for XOR, we prefer to force bits to 1 if they will make a -1.
1372    // if we can't force bits, try to shrink constant
1373    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1374      APInt Expanded = C->getAPIntValue() | (~NewMask);
1375      // if we can expand it to have all bits set, do it
1376      if (Expanded.isAllOnesValue()) {
1377        if (Expanded != C->getAPIntValue()) {
1378          EVT VT = Op.getValueType();
1379          SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1380                                          TLO.DAG.getConstant(Expanded, VT));
1381          return TLO.CombineTo(Op, New);
1382        }
1383        // if it already has all the bits set, nothing to change
1384        // but don't shrink either!
1385      } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1386        return true;
1387      }
1388    }
1389
1390    KnownZero = KnownZeroOut;
1391    KnownOne  = KnownOneOut;
1392    break;
1393  case ISD::SELECT:
1394    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1395                             KnownOne, TLO, Depth+1))
1396      return true;
1397    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1398                             KnownOne2, TLO, Depth+1))
1399      return true;
1400    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1401    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1402
1403    // If the operands are constants, see if we can simplify them.
1404    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1405      return true;
1406
1407    // Only known if known in both the LHS and RHS.
1408    KnownOne &= KnownOne2;
1409    KnownZero &= KnownZero2;
1410    break;
1411  case ISD::SELECT_CC:
1412    if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1413                             KnownOne, TLO, Depth+1))
1414      return true;
1415    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1416                             KnownOne2, TLO, Depth+1))
1417      return true;
1418    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1419    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1420
1421    // If the operands are constants, see if we can simplify them.
1422    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1423      return true;
1424
1425    // Only known if known in both the LHS and RHS.
1426    KnownOne &= KnownOne2;
1427    KnownZero &= KnownZero2;
1428    break;
1429  case ISD::SHL:
1430    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1431      unsigned ShAmt = SA->getZExtValue();
1432      SDValue InOp = Op.getOperand(0);
1433
1434      // If the shift count is an invalid immediate, don't do anything.
1435      if (ShAmt >= BitWidth)
1436        break;
1437
1438      // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1439      // single shift.  We can do this if the bottom bits (which are shifted
1440      // out) are never demanded.
1441      if (InOp.getOpcode() == ISD::SRL &&
1442          isa<ConstantSDNode>(InOp.getOperand(1))) {
1443        if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1444          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1445          unsigned Opc = ISD::SHL;
1446          int Diff = ShAmt-C1;
1447          if (Diff < 0) {
1448            Diff = -Diff;
1449            Opc = ISD::SRL;
1450          }
1451
1452          SDValue NewSA =
1453            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1454          EVT VT = Op.getValueType();
1455          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1456                                                   InOp.getOperand(0), NewSA));
1457        }
1458      }
1459
1460      if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
1461                               KnownZero, KnownOne, TLO, Depth+1))
1462        return true;
1463
1464      // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1465      // are not demanded. This will likely allow the anyext to be folded away.
1466      if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1467        SDValue InnerOp = InOp.getNode()->getOperand(0);
1468        EVT InnerVT = InnerOp.getValueType();
1469        if ((APInt::getHighBitsSet(BitWidth,
1470                                   BitWidth - InnerVT.getSizeInBits()) &
1471               DemandedMask) == 0 &&
1472            isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1473          EVT ShTy = getShiftAmountTy(InnerVT);
1474          if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1475            ShTy = InnerVT;
1476          SDValue NarrowShl =
1477            TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1478                            TLO.DAG.getConstant(ShAmt, ShTy));
1479          return
1480            TLO.CombineTo(Op,
1481                          TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1482                                          NarrowShl));
1483        }
1484      }
1485
1486      KnownZero <<= SA->getZExtValue();
1487      KnownOne  <<= SA->getZExtValue();
1488      // low bits known zero.
1489      KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1490    }
1491    break;
1492  case ISD::SRL:
1493    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1494      EVT VT = Op.getValueType();
1495      unsigned ShAmt = SA->getZExtValue();
1496      unsigned VTSize = VT.getSizeInBits();
1497      SDValue InOp = Op.getOperand(0);
1498
1499      // If the shift count is an invalid immediate, don't do anything.
1500      if (ShAmt >= BitWidth)
1501        break;
1502
1503      // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1504      // single shift.  We can do this if the top bits (which are shifted out)
1505      // are never demanded.
1506      if (InOp.getOpcode() == ISD::SHL &&
1507          isa<ConstantSDNode>(InOp.getOperand(1))) {
1508        if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1509          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1510          unsigned Opc = ISD::SRL;
1511          int Diff = ShAmt-C1;
1512          if (Diff < 0) {
1513            Diff = -Diff;
1514            Opc = ISD::SHL;
1515          }
1516
1517          SDValue NewSA =
1518            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1519          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1520                                                   InOp.getOperand(0), NewSA));
1521        }
1522      }
1523
1524      // Compute the new bits that are at the top now.
1525      if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1526                               KnownZero, KnownOne, TLO, Depth+1))
1527        return true;
1528      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1529      KnownZero = KnownZero.lshr(ShAmt);
1530      KnownOne  = KnownOne.lshr(ShAmt);
1531
1532      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1533      KnownZero |= HighBits;  // High bits known zero.
1534    }
1535    break;
1536  case ISD::SRA:
1537    // If this is an arithmetic shift right and only the low-bit is set, we can
1538    // always convert this into a logical shr, even if the shift amount is
1539    // variable.  The low bit of the shift cannot be an input sign bit unless
1540    // the shift amount is >= the size of the datatype, which is undefined.
1541    if (DemandedMask == 1)
1542      return TLO.CombineTo(Op,
1543                           TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1544                                           Op.getOperand(0), Op.getOperand(1)));
1545
1546    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1547      EVT VT = Op.getValueType();
1548      unsigned ShAmt = SA->getZExtValue();
1549
1550      // If the shift count is an invalid immediate, don't do anything.
1551      if (ShAmt >= BitWidth)
1552        break;
1553
1554      APInt InDemandedMask = (NewMask << ShAmt);
1555
1556      // If any of the demanded bits are produced by the sign extension, we also
1557      // demand the input sign bit.
1558      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1559      if (HighBits.intersects(NewMask))
1560        InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1561
1562      if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1563                               KnownZero, KnownOne, TLO, Depth+1))
1564        return true;
1565      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1566      KnownZero = KnownZero.lshr(ShAmt);
1567      KnownOne  = KnownOne.lshr(ShAmt);
1568
1569      // Handle the sign bit, adjusted to where it is now in the mask.
1570      APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1571
1572      // If the input sign bit is known to be zero, or if none of the top bits
1573      // are demanded, turn this into an unsigned shift right.
1574      if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1575        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1576                                                 Op.getOperand(0),
1577                                                 Op.getOperand(1)));
1578      } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1579        KnownOne |= HighBits;
1580      }
1581    }
1582    break;
1583  case ISD::SIGN_EXTEND_INREG: {
1584    EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1585
1586    // Sign extension.  Compute the demanded bits in the result that are not
1587    // present in the input.
1588    APInt NewBits =
1589      APInt::getHighBitsSet(BitWidth,
1590                            BitWidth - EVT.getScalarType().getSizeInBits());
1591
1592    // If none of the extended bits are demanded, eliminate the sextinreg.
1593    if ((NewBits & NewMask) == 0)
1594      return TLO.CombineTo(Op, Op.getOperand(0));
1595
1596    APInt InSignBit =
1597      APInt::getSignBit(EVT.getScalarType().getSizeInBits()).zext(BitWidth);
1598    APInt InputDemandedBits =
1599      APInt::getLowBitsSet(BitWidth,
1600                           EVT.getScalarType().getSizeInBits()) &
1601      NewMask;
1602
1603    // Since the sign extended bits are demanded, we know that the sign
1604    // bit is demanded.
1605    InputDemandedBits |= InSignBit;
1606
1607    if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1608                             KnownZero, KnownOne, TLO, Depth+1))
1609      return true;
1610    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1611
1612    // If the sign bit of the input is known set or clear, then we know the
1613    // top bits of the result.
1614
1615    // If the input sign bit is known zero, convert this into a zero extension.
1616    if (KnownZero.intersects(InSignBit))
1617      return TLO.CombineTo(Op,
1618                           TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1619
1620    if (KnownOne.intersects(InSignBit)) {    // Input sign bit known set
1621      KnownOne |= NewBits;
1622      KnownZero &= ~NewBits;
1623    } else {                       // Input sign bit unknown
1624      KnownZero &= ~NewBits;
1625      KnownOne &= ~NewBits;
1626    }
1627    break;
1628  }
1629  case ISD::ZERO_EXTEND: {
1630    unsigned OperandBitWidth =
1631      Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1632    APInt InMask = NewMask.trunc(OperandBitWidth);
1633
1634    // If none of the top bits are demanded, convert this into an any_extend.
1635    APInt NewBits =
1636      APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1637    if (!NewBits.intersects(NewMask))
1638      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1639                                               Op.getValueType(),
1640                                               Op.getOperand(0)));
1641
1642    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1643                             KnownZero, KnownOne, TLO, Depth+1))
1644      return true;
1645    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1646    KnownZero = KnownZero.zext(BitWidth);
1647    KnownOne = KnownOne.zext(BitWidth);
1648    KnownZero |= NewBits;
1649    break;
1650  }
1651  case ISD::SIGN_EXTEND: {
1652    EVT InVT = Op.getOperand(0).getValueType();
1653    unsigned InBits = InVT.getScalarType().getSizeInBits();
1654    APInt InMask    = APInt::getLowBitsSet(BitWidth, InBits);
1655    APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1656    APInt NewBits   = ~InMask & NewMask;
1657
1658    // If none of the top bits are demanded, convert this into an any_extend.
1659    if (NewBits == 0)
1660      return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1661                                              Op.getValueType(),
1662                                              Op.getOperand(0)));
1663
1664    // Since some of the sign extended bits are demanded, we know that the sign
1665    // bit is demanded.
1666    APInt InDemandedBits = InMask & NewMask;
1667    InDemandedBits |= InSignBit;
1668    InDemandedBits = InDemandedBits.trunc(InBits);
1669
1670    if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1671                             KnownOne, TLO, Depth+1))
1672      return true;
1673    KnownZero = KnownZero.zext(BitWidth);
1674    KnownOne = KnownOne.zext(BitWidth);
1675
1676    // If the sign bit is known zero, convert this to a zero extend.
1677    if (KnownZero.intersects(InSignBit))
1678      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1679                                               Op.getValueType(),
1680                                               Op.getOperand(0)));
1681
1682    // If the sign bit is known one, the top bits match.
1683    if (KnownOne.intersects(InSignBit)) {
1684      KnownOne  |= NewBits;
1685      KnownZero &= ~NewBits;
1686    } else {   // Otherwise, top bits aren't known.
1687      KnownOne  &= ~NewBits;
1688      KnownZero &= ~NewBits;
1689    }
1690    break;
1691  }
1692  case ISD::ANY_EXTEND: {
1693    unsigned OperandBitWidth =
1694      Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1695    APInt InMask = NewMask.trunc(OperandBitWidth);
1696    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1697                             KnownZero, KnownOne, TLO, Depth+1))
1698      return true;
1699    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1700    KnownZero = KnownZero.zext(BitWidth);
1701    KnownOne = KnownOne.zext(BitWidth);
1702    break;
1703  }
1704  case ISD::TRUNCATE: {
1705    // Simplify the input, using demanded bit information, and compute the known
1706    // zero/one bits live out.
1707    unsigned OperandBitWidth =
1708      Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1709    APInt TruncMask = NewMask.zext(OperandBitWidth);
1710    if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1711                             KnownZero, KnownOne, TLO, Depth+1))
1712      return true;
1713    KnownZero = KnownZero.trunc(BitWidth);
1714    KnownOne = KnownOne.trunc(BitWidth);
1715
1716    // If the input is only used by this truncate, see if we can shrink it based
1717    // on the known demanded bits.
1718    if (Op.getOperand(0).getNode()->hasOneUse()) {
1719      SDValue In = Op.getOperand(0);
1720      switch (In.getOpcode()) {
1721      default: break;
1722      case ISD::SRL:
1723        // Shrink SRL by a constant if none of the high bits shifted in are
1724        // demanded.
1725        if (TLO.LegalTypes() &&
1726            !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1727          // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1728          // undesirable.
1729          break;
1730        ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1731        if (!ShAmt)
1732          break;
1733        SDValue Shift = In.getOperand(1);
1734        if (TLO.LegalTypes()) {
1735          uint64_t ShVal = ShAmt->getZExtValue();
1736          Shift =
1737            TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1738        }
1739
1740        APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1741                                               OperandBitWidth - BitWidth);
1742        HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1743
1744        if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1745          // None of the shifted in bits are needed.  Add a truncate of the
1746          // shift input, then shift it.
1747          SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1748                                             Op.getValueType(),
1749                                             In.getOperand(0));
1750          return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1751                                                   Op.getValueType(),
1752                                                   NewTrunc,
1753                                                   Shift));
1754        }
1755        break;
1756      }
1757    }
1758
1759    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1760    break;
1761  }
1762  case ISD::AssertZext: {
1763    // Demand all the bits of the input that are demanded in the output.
1764    // The low bits are obvious; the high bits are demanded because we're
1765    // asserting that they're zero here.
1766    if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
1767                             KnownZero, KnownOne, TLO, Depth+1))
1768      return true;
1769    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1770
1771    EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1772    APInt InMask = APInt::getLowBitsSet(BitWidth,
1773                                        VT.getSizeInBits());
1774    KnownZero |= ~InMask & NewMask;
1775    break;
1776  }
1777  case ISD::BITCAST:
1778    // If this is an FP->Int bitcast and if the sign bit is the only
1779    // thing demanded, turn this into a FGETSIGN.
1780    if (!Op.getOperand(0).getValueType().isVector() &&
1781        NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1782        Op.getOperand(0).getValueType().isFloatingPoint()) {
1783      bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1784      bool i32Legal  = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1785      if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1786        EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1787        // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1788        // place.  We expect the SHL to be eliminated by other optimizations.
1789        SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1790        unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1791        if (!OpVTLegal && OpVTSizeInBits > 32)
1792          Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1793        unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1794        SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1795        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1796                                                 Op.getValueType(),
1797                                                 Sign, ShAmt));
1798      }
1799    }
1800    break;
1801  case ISD::ADD:
1802  case ISD::MUL:
1803  case ISD::SUB: {
1804    // Add, Sub, and Mul don't demand any bits in positions beyond that
1805    // of the highest bit demanded of them.
1806    APInt LoMask = APInt::getLowBitsSet(BitWidth,
1807                                        BitWidth - NewMask.countLeadingZeros());
1808    if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1809                             KnownOne2, TLO, Depth+1))
1810      return true;
1811    if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1812                             KnownOne2, TLO, Depth+1))
1813      return true;
1814    // See if the operation should be performed at a smaller bit width.
1815    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1816      return true;
1817  }
1818  // FALL THROUGH
1819  default:
1820    // Just use ComputeMaskedBits to compute output bits.
1821    TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1822    break;
1823  }
1824
1825  // If we know the value of all of the demanded bits, return this as a
1826  // constant.
1827  if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1828    return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1829
1830  return false;
1831}
1832
1833/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1834/// in Mask are known to be either zero or one and return them in the
1835/// KnownZero/KnownOne bitsets.
1836void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1837                                                    const APInt &Mask,
1838                                                    APInt &KnownZero,
1839                                                    APInt &KnownOne,
1840                                                    const SelectionDAG &DAG,
1841                                                    unsigned Depth) const {
1842  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1843          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1844          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1845          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1846         "Should use MaskedValueIsZero if you don't know whether Op"
1847         " is a target node!");
1848  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1849}
1850
1851/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1852/// targets that want to expose additional information about sign bits to the
1853/// DAG Combiner.
1854unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1855                                                         unsigned Depth) const {
1856  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1857          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1858          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1859          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1860         "Should use ComputeNumSignBits if you don't know whether Op"
1861         " is a target node!");
1862  return 1;
1863}
1864
1865/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1866/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1867/// determine which bit is set.
1868///
1869static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1870  // A left-shift of a constant one will have exactly one bit set, because
1871  // shifting the bit off the end is undefined.
1872  if (Val.getOpcode() == ISD::SHL)
1873    if (ConstantSDNode *C =
1874         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1875      if (C->getAPIntValue() == 1)
1876        return true;
1877
1878  // Similarly, a right-shift of a constant sign-bit will have exactly
1879  // one bit set.
1880  if (Val.getOpcode() == ISD::SRL)
1881    if (ConstantSDNode *C =
1882         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1883      if (C->getAPIntValue().isSignBit())
1884        return true;
1885
1886  // More could be done here, though the above checks are enough
1887  // to handle some common cases.
1888
1889  // Fall back to ComputeMaskedBits to catch other known cases.
1890  EVT OpVT = Val.getValueType();
1891  unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1892  APInt Mask = APInt::getAllOnesValue(BitWidth);
1893  APInt KnownZero, KnownOne;
1894  DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1895  return (KnownZero.countPopulation() == BitWidth - 1) &&
1896         (KnownOne.countPopulation() == 1);
1897}
1898
1899/// SimplifySetCC - Try to simplify a setcc built with the specified operands
1900/// and cc. If it is unable to simplify it, return a null SDValue.
1901SDValue
1902TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1903                              ISD::CondCode Cond, bool foldBooleans,
1904                              DAGCombinerInfo &DCI, DebugLoc dl) const {
1905  SelectionDAG &DAG = DCI.DAG;
1906
1907  // These setcc operations always fold.
1908  switch (Cond) {
1909  default: break;
1910  case ISD::SETFALSE:
1911  case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1912  case ISD::SETTRUE:
1913  case ISD::SETTRUE2:  return DAG.getConstant(1, VT);
1914  }
1915
1916  // Ensure that the constant occurs on the RHS, and fold constant
1917  // comparisons.
1918  if (isa<ConstantSDNode>(N0.getNode()))
1919    return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1920
1921  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1922    const APInt &C1 = N1C->getAPIntValue();
1923
1924    // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1925    // equality comparison, then we're just comparing whether X itself is
1926    // zero.
1927    if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1928        N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1929        N0.getOperand(1).getOpcode() == ISD::Constant) {
1930      const APInt &ShAmt
1931        = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1932      if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1933          ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1934        if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1935          // (srl (ctlz x), 5) == 0  -> X != 0
1936          // (srl (ctlz x), 5) != 1  -> X != 0
1937          Cond = ISD::SETNE;
1938        } else {
1939          // (srl (ctlz x), 5) != 0  -> X == 0
1940          // (srl (ctlz x), 5) == 1  -> X == 0
1941          Cond = ISD::SETEQ;
1942        }
1943        SDValue Zero = DAG.getConstant(0, N0.getValueType());
1944        return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1945                            Zero, Cond);
1946      }
1947    }
1948
1949    SDValue CTPOP = N0;
1950    // Look through truncs that don't change the value of a ctpop.
1951    if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1952      CTPOP = N0.getOperand(0);
1953
1954    if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1955        (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1956                        Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1957      EVT CTVT = CTPOP.getValueType();
1958      SDValue CTOp = CTPOP.getOperand(0);
1959
1960      // (ctpop x) u< 2 -> (x & x-1) == 0
1961      // (ctpop x) u> 1 -> (x & x-1) != 0
1962      if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1963        SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1964                                  DAG.getConstant(1, CTVT));
1965        SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1966        ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1967        return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1968      }
1969
1970      // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1971    }
1972
1973    // (zext x) == C --> x == (trunc C)
1974    if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1975        (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1976      unsigned MinBits = N0.getValueSizeInBits();
1977      SDValue PreZExt;
1978      if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1979        // ZExt
1980        MinBits = N0->getOperand(0).getValueSizeInBits();
1981        PreZExt = N0->getOperand(0);
1982      } else if (N0->getOpcode() == ISD::AND) {
1983        // DAGCombine turns costly ZExts into ANDs
1984        if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1985          if ((C->getAPIntValue()+1).isPowerOf2()) {
1986            MinBits = C->getAPIntValue().countTrailingOnes();
1987            PreZExt = N0->getOperand(0);
1988          }
1989      } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1990        // ZEXTLOAD
1991        if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1992          MinBits = LN0->getMemoryVT().getSizeInBits();
1993          PreZExt = N0;
1994        }
1995      }
1996
1997      // Make sure we're not loosing bits from the constant.
1998      if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
1999        EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2000        if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2001          // Will get folded away.
2002          SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2003          SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2004          return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2005        }
2006      }
2007    }
2008
2009    // If the LHS is '(and load, const)', the RHS is 0,
2010    // the test is for equality or unsigned, and all 1 bits of the const are
2011    // in the same partial word, see if we can shorten the load.
2012    if (DCI.isBeforeLegalize() &&
2013        N0.getOpcode() == ISD::AND && C1 == 0 &&
2014        N0.getNode()->hasOneUse() &&
2015        isa<LoadSDNode>(N0.getOperand(0)) &&
2016        N0.getOperand(0).getNode()->hasOneUse() &&
2017        isa<ConstantSDNode>(N0.getOperand(1))) {
2018      LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
2019      APInt bestMask;
2020      unsigned bestWidth = 0, bestOffset = 0;
2021      if (!Lod->isVolatile() && Lod->isUnindexed()) {
2022        unsigned origWidth = N0.getValueType().getSizeInBits();
2023        unsigned maskWidth = origWidth;
2024        // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
2025        // 8 bits, but have to be careful...
2026        if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2027          origWidth = Lod->getMemoryVT().getSizeInBits();
2028        const APInt &Mask =
2029          cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2030        for (unsigned width = origWidth / 2; width>=8; width /= 2) {
2031          APInt newMask = APInt::getLowBitsSet(maskWidth, width);
2032          for (unsigned offset=0; offset<origWidth/width; offset++) {
2033            if ((newMask & Mask) == Mask) {
2034              if (!TD->isLittleEndian())
2035                bestOffset = (origWidth/width - offset - 1) * (width/8);
2036              else
2037                bestOffset = (uint64_t)offset * (width/8);
2038              bestMask = Mask.lshr(offset * (width/8) * 8);
2039              bestWidth = width;
2040              break;
2041            }
2042            newMask = newMask << width;
2043          }
2044        }
2045      }
2046      if (bestWidth) {
2047        EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
2048        if (newVT.isRound()) {
2049          EVT PtrType = Lod->getOperand(1).getValueType();
2050          SDValue Ptr = Lod->getBasePtr();
2051          if (bestOffset != 0)
2052            Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2053                              DAG.getConstant(bestOffset, PtrType));
2054          unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2055          SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
2056                                Lod->getPointerInfo().getWithOffset(bestOffset),
2057                                        false, false, NewAlign);
2058          return DAG.getSetCC(dl, VT,
2059                              DAG.getNode(ISD::AND, dl, newVT, NewLoad,
2060                                      DAG.getConstant(bestMask.trunc(bestWidth),
2061                                                      newVT)),
2062                              DAG.getConstant(0LL, newVT), Cond);
2063        }
2064      }
2065    }
2066
2067    // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2068    if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2069      unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2070
2071      // If the comparison constant has bits in the upper part, the
2072      // zero-extended value could never match.
2073      if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2074                                              C1.getBitWidth() - InSize))) {
2075        switch (Cond) {
2076        case ISD::SETUGT:
2077        case ISD::SETUGE:
2078        case ISD::SETEQ: return DAG.getConstant(0, VT);
2079        case ISD::SETULT:
2080        case ISD::SETULE:
2081        case ISD::SETNE: return DAG.getConstant(1, VT);
2082        case ISD::SETGT:
2083        case ISD::SETGE:
2084          // True if the sign bit of C1 is set.
2085          return DAG.getConstant(C1.isNegative(), VT);
2086        case ISD::SETLT:
2087        case ISD::SETLE:
2088          // True if the sign bit of C1 isn't set.
2089          return DAG.getConstant(C1.isNonNegative(), VT);
2090        default:
2091          break;
2092        }
2093      }
2094
2095      // Otherwise, we can perform the comparison with the low bits.
2096      switch (Cond) {
2097      case ISD::SETEQ:
2098      case ISD::SETNE:
2099      case ISD::SETUGT:
2100      case ISD::SETUGE:
2101      case ISD::SETULT:
2102      case ISD::SETULE: {
2103        EVT newVT = N0.getOperand(0).getValueType();
2104        if (DCI.isBeforeLegalizeOps() ||
2105            (isOperationLegal(ISD::SETCC, newVT) &&
2106              getCondCodeAction(Cond, newVT)==Legal))
2107          return DAG.getSetCC(dl, VT, N0.getOperand(0),
2108                              DAG.getConstant(C1.trunc(InSize), newVT),
2109                              Cond);
2110        break;
2111      }
2112      default:
2113        break;   // todo, be more careful with signed comparisons
2114      }
2115    } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2116               (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2117      EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2118      unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
2119      EVT ExtDstTy = N0.getValueType();
2120      unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2121
2122      // If the constant doesn't fit into the number of bits for the source of
2123      // the sign extension, it is impossible for both sides to be equal.
2124      if (C1.getMinSignedBits() > ExtSrcTyBits)
2125        return DAG.getConstant(Cond == ISD::SETNE, VT);
2126
2127      SDValue ZextOp;
2128      EVT Op0Ty = N0.getOperand(0).getValueType();
2129      if (Op0Ty == ExtSrcTy) {
2130        ZextOp = N0.getOperand(0);
2131      } else {
2132        APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2133        ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2134                              DAG.getConstant(Imm, Op0Ty));
2135      }
2136      if (!DCI.isCalledByLegalizer())
2137        DCI.AddToWorklist(ZextOp.getNode());
2138      // Otherwise, make this a use of a zext.
2139      return DAG.getSetCC(dl, VT, ZextOp,
2140                          DAG.getConstant(C1 & APInt::getLowBitsSet(
2141                                                              ExtDstTyBits,
2142                                                              ExtSrcTyBits),
2143                                          ExtDstTy),
2144                          Cond);
2145    } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2146                (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2147      // SETCC (SETCC), [0|1], [EQ|NE]  -> SETCC
2148      if (N0.getOpcode() == ISD::SETCC &&
2149          isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2150        bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
2151        if (TrueWhenTrue)
2152          return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2153        // Invert the condition.
2154        ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2155        CC = ISD::getSetCCInverse(CC,
2156                                  N0.getOperand(0).getValueType().isInteger());
2157        return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2158      }
2159
2160      if ((N0.getOpcode() == ISD::XOR ||
2161           (N0.getOpcode() == ISD::AND &&
2162            N0.getOperand(0).getOpcode() == ISD::XOR &&
2163            N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2164          isa<ConstantSDNode>(N0.getOperand(1)) &&
2165          cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2166        // If this is (X^1) == 0/1, swap the RHS and eliminate the xor.  We
2167        // can only do this if the top bits are known zero.
2168        unsigned BitWidth = N0.getValueSizeInBits();
2169        if (DAG.MaskedValueIsZero(N0,
2170                                  APInt::getHighBitsSet(BitWidth,
2171                                                        BitWidth-1))) {
2172          // Okay, get the un-inverted input value.
2173          SDValue Val;
2174          if (N0.getOpcode() == ISD::XOR)
2175            Val = N0.getOperand(0);
2176          else {
2177            assert(N0.getOpcode() == ISD::AND &&
2178                    N0.getOperand(0).getOpcode() == ISD::XOR);
2179            // ((X^1)&1)^1 -> X & 1
2180            Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2181                              N0.getOperand(0).getOperand(0),
2182                              N0.getOperand(1));
2183          }
2184
2185          return DAG.getSetCC(dl, VT, Val, N1,
2186                              Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2187        }
2188      } else if (N1C->getAPIntValue() == 1 &&
2189                 (VT == MVT::i1 ||
2190                  getBooleanContents() == ZeroOrOneBooleanContent)) {
2191        SDValue Op0 = N0;
2192        if (Op0.getOpcode() == ISD::TRUNCATE)
2193          Op0 = Op0.getOperand(0);
2194
2195        if ((Op0.getOpcode() == ISD::XOR) &&
2196            Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2197            Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2198          // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2199          Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2200          return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2201                              Cond);
2202        } else if (Op0.getOpcode() == ISD::AND &&
2203                isa<ConstantSDNode>(Op0.getOperand(1)) &&
2204                cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2205          // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
2206          if (Op0.getValueType().bitsGT(VT))
2207            Op0 = DAG.getNode(ISD::AND, dl, VT,
2208                          DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2209                          DAG.getConstant(1, VT));
2210          else if (Op0.getValueType().bitsLT(VT))
2211            Op0 = DAG.getNode(ISD::AND, dl, VT,
2212                        DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2213                        DAG.getConstant(1, VT));
2214
2215          return DAG.getSetCC(dl, VT, Op0,
2216                              DAG.getConstant(0, Op0.getValueType()),
2217                              Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2218        }
2219      }
2220    }
2221
2222    APInt MinVal, MaxVal;
2223    unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2224    if (ISD::isSignedIntSetCC(Cond)) {
2225      MinVal = APInt::getSignedMinValue(OperandBitSize);
2226      MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2227    } else {
2228      MinVal = APInt::getMinValue(OperandBitSize);
2229      MaxVal = APInt::getMaxValue(OperandBitSize);
2230    }
2231
2232    // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2233    if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2234      if (C1 == MinVal) return DAG.getConstant(1, VT);   // X >= MIN --> true
2235      // X >= C0 --> X > (C0-1)
2236      return DAG.getSetCC(dl, VT, N0,
2237                          DAG.getConstant(C1-1, N1.getValueType()),
2238                          (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2239    }
2240
2241    if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2242      if (C1 == MaxVal) return DAG.getConstant(1, VT);   // X <= MAX --> true
2243      // X <= C0 --> X < (C0+1)
2244      return DAG.getSetCC(dl, VT, N0,
2245                          DAG.getConstant(C1+1, N1.getValueType()),
2246                          (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2247    }
2248
2249    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2250      return DAG.getConstant(0, VT);      // X < MIN --> false
2251    if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2252      return DAG.getConstant(1, VT);      // X >= MIN --> true
2253    if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2254      return DAG.getConstant(0, VT);      // X > MAX --> false
2255    if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2256      return DAG.getConstant(1, VT);      // X <= MAX --> true
2257
2258    // Canonicalize setgt X, Min --> setne X, Min
2259    if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2260      return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2261    // Canonicalize setlt X, Max --> setne X, Max
2262    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2263      return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2264
2265    // If we have setult X, 1, turn it into seteq X, 0
2266    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2267      return DAG.getSetCC(dl, VT, N0,
2268                          DAG.getConstant(MinVal, N0.getValueType()),
2269                          ISD::SETEQ);
2270    // If we have setugt X, Max-1, turn it into seteq X, Max
2271    else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2272      return DAG.getSetCC(dl, VT, N0,
2273                          DAG.getConstant(MaxVal, N0.getValueType()),
2274                          ISD::SETEQ);
2275
2276    // If we have "setcc X, C0", check to see if we can shrink the immediate
2277    // by changing cc.
2278
2279    // SETUGT X, SINTMAX  -> SETLT X, 0
2280    if (Cond == ISD::SETUGT &&
2281        C1 == APInt::getSignedMaxValue(OperandBitSize))
2282      return DAG.getSetCC(dl, VT, N0,
2283                          DAG.getConstant(0, N1.getValueType()),
2284                          ISD::SETLT);
2285
2286    // SETULT X, SINTMIN  -> SETGT X, -1
2287    if (Cond == ISD::SETULT &&
2288        C1 == APInt::getSignedMinValue(OperandBitSize)) {
2289      SDValue ConstMinusOne =
2290          DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2291                          N1.getValueType());
2292      return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2293    }
2294
2295    // Fold bit comparisons when we can.
2296    if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2297        (VT == N0.getValueType() ||
2298         (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2299        N0.getOpcode() == ISD::AND)
2300      if (ConstantSDNode *AndRHS =
2301                  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2302        EVT ShiftTy = DCI.isBeforeLegalize() ?
2303          getPointerTy() : getShiftAmountTy(N0.getValueType());
2304        if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
2305          // Perform the xform if the AND RHS is a single bit.
2306          if (AndRHS->getAPIntValue().isPowerOf2()) {
2307            return DAG.getNode(ISD::TRUNCATE, dl, VT,
2308                              DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2309                   DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
2310          }
2311        } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2312          // (X & 8) == 8  -->  (X & 8) >> 3
2313          // Perform the xform if C1 is a single bit.
2314          if (C1.isPowerOf2()) {
2315            return DAG.getNode(ISD::TRUNCATE, dl, VT,
2316                               DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2317                                      DAG.getConstant(C1.logBase2(), ShiftTy)));
2318          }
2319        }
2320      }
2321  }
2322
2323  if (isa<ConstantFPSDNode>(N0.getNode())) {
2324    // Constant fold or commute setcc.
2325    SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2326    if (O.getNode()) return O;
2327  } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2328    // If the RHS of an FP comparison is a constant, simplify it away in
2329    // some cases.
2330    if (CFP->getValueAPF().isNaN()) {
2331      // If an operand is known to be a nan, we can fold it.
2332      switch (ISD::getUnorderedFlavor(Cond)) {
2333      default: llvm_unreachable("Unknown flavor!");
2334      case 0:  // Known false.
2335        return DAG.getConstant(0, VT);
2336      case 1:  // Known true.
2337        return DAG.getConstant(1, VT);
2338      case 2:  // Undefined.
2339        return DAG.getUNDEF(VT);
2340      }
2341    }
2342
2343    // Otherwise, we know the RHS is not a NaN.  Simplify the node to drop the
2344    // constant if knowing that the operand is non-nan is enough.  We prefer to
2345    // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2346    // materialize 0.0.
2347    if (Cond == ISD::SETO || Cond == ISD::SETUO)
2348      return DAG.getSetCC(dl, VT, N0, N0, Cond);
2349
2350    // If the condition is not legal, see if we can find an equivalent one
2351    // which is legal.
2352    if (!isCondCodeLegal(Cond, N0.getValueType())) {
2353      // If the comparison was an awkward floating-point == or != and one of
2354      // the comparison operands is infinity or negative infinity, convert the
2355      // condition to a less-awkward <= or >=.
2356      if (CFP->getValueAPF().isInfinity()) {
2357        if (CFP->getValueAPF().isNegative()) {
2358          if (Cond == ISD::SETOEQ &&
2359              isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2360            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2361          if (Cond == ISD::SETUEQ &&
2362              isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2363            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2364          if (Cond == ISD::SETUNE &&
2365              isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2366            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2367          if (Cond == ISD::SETONE &&
2368              isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2369            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2370        } else {
2371          if (Cond == ISD::SETOEQ &&
2372              isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2373            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2374          if (Cond == ISD::SETUEQ &&
2375              isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2376            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2377          if (Cond == ISD::SETUNE &&
2378              isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2379            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2380          if (Cond == ISD::SETONE &&
2381              isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2382            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2383        }
2384      }
2385    }
2386  }
2387
2388  if (N0 == N1) {
2389    // We can always fold X == X for integer setcc's.
2390    if (N0.getValueType().isInteger())
2391      return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2392    unsigned UOF = ISD::getUnorderedFlavor(Cond);
2393    if (UOF == 2)   // FP operators that are undefined on NaNs.
2394      return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2395    if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2396      return DAG.getConstant(UOF, VT);
2397    // Otherwise, we can't fold it.  However, we can simplify it to SETUO/SETO
2398    // if it is not already.
2399    ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2400    if (NewCond != Cond)
2401      return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2402  }
2403
2404  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2405      N0.getValueType().isInteger()) {
2406    if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2407        N0.getOpcode() == ISD::XOR) {
2408      // Simplify (X+Y) == (X+Z) -->  Y == Z
2409      if (N0.getOpcode() == N1.getOpcode()) {
2410        if (N0.getOperand(0) == N1.getOperand(0))
2411          return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2412        if (N0.getOperand(1) == N1.getOperand(1))
2413          return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2414        if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2415          // If X op Y == Y op X, try other combinations.
2416          if (N0.getOperand(0) == N1.getOperand(1))
2417            return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2418                                Cond);
2419          if (N0.getOperand(1) == N1.getOperand(0))
2420            return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2421                                Cond);
2422        }
2423      }
2424
2425      if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2426        if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2427          // Turn (X+C1) == C2 --> X == C2-C1
2428          if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2429            return DAG.getSetCC(dl, VT, N0.getOperand(0),
2430                                DAG.getConstant(RHSC->getAPIntValue()-
2431                                                LHSR->getAPIntValue(),
2432                                N0.getValueType()), Cond);
2433          }
2434
2435          // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2436          if (N0.getOpcode() == ISD::XOR)
2437            // If we know that all of the inverted bits are zero, don't bother
2438            // performing the inversion.
2439            if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2440              return
2441                DAG.getSetCC(dl, VT, N0.getOperand(0),
2442                             DAG.getConstant(LHSR->getAPIntValue() ^
2443                                               RHSC->getAPIntValue(),
2444                                             N0.getValueType()),
2445                             Cond);
2446        }
2447
2448        // Turn (C1-X) == C2 --> X == C1-C2
2449        if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2450          if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2451            return
2452              DAG.getSetCC(dl, VT, N0.getOperand(1),
2453                           DAG.getConstant(SUBC->getAPIntValue() -
2454                                             RHSC->getAPIntValue(),
2455                                           N0.getValueType()),
2456                           Cond);
2457          }
2458        }
2459      }
2460
2461      // Simplify (X+Z) == X -->  Z == 0
2462      if (N0.getOperand(0) == N1)
2463        return DAG.getSetCC(dl, VT, N0.getOperand(1),
2464                        DAG.getConstant(0, N0.getValueType()), Cond);
2465      if (N0.getOperand(1) == N1) {
2466        if (DAG.isCommutativeBinOp(N0.getOpcode()))
2467          return DAG.getSetCC(dl, VT, N0.getOperand(0),
2468                          DAG.getConstant(0, N0.getValueType()), Cond);
2469        else if (N0.getNode()->hasOneUse()) {
2470          assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2471          // (Z-X) == X  --> Z == X<<1
2472          SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
2473                                     N1,
2474                       DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
2475          if (!DCI.isCalledByLegalizer())
2476            DCI.AddToWorklist(SH.getNode());
2477          return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2478        }
2479      }
2480    }
2481
2482    if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2483        N1.getOpcode() == ISD::XOR) {
2484      // Simplify  X == (X+Z) -->  Z == 0
2485      if (N1.getOperand(0) == N0) {
2486        return DAG.getSetCC(dl, VT, N1.getOperand(1),
2487                        DAG.getConstant(0, N1.getValueType()), Cond);
2488      } else if (N1.getOperand(1) == N0) {
2489        if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2490          return DAG.getSetCC(dl, VT, N1.getOperand(0),
2491                          DAG.getConstant(0, N1.getValueType()), Cond);
2492        } else if (N1.getNode()->hasOneUse()) {
2493          assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2494          // X == (Z-X)  --> X<<1 == Z
2495          SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2496                       DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
2497          if (!DCI.isCalledByLegalizer())
2498            DCI.AddToWorklist(SH.getNode());
2499          return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2500        }
2501      }
2502    }
2503
2504    // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2505    // Note that where y is variable and is known to have at most
2506    // one bit set (for example, if it is z&1) we cannot do this;
2507    // the expressions are not equivalent when y==0.
2508    if (N0.getOpcode() == ISD::AND)
2509      if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2510        if (ValueHasExactlyOneBitSet(N1, DAG)) {
2511          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2512          SDValue Zero = DAG.getConstant(0, N1.getValueType());
2513          return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2514        }
2515      }
2516    if (N1.getOpcode() == ISD::AND)
2517      if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2518        if (ValueHasExactlyOneBitSet(N0, DAG)) {
2519          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2520          SDValue Zero = DAG.getConstant(0, N0.getValueType());
2521          return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2522        }
2523      }
2524  }
2525
2526  // Fold away ALL boolean setcc's.
2527  SDValue Temp;
2528  if (N0.getValueType() == MVT::i1 && foldBooleans) {
2529    switch (Cond) {
2530    default: llvm_unreachable("Unknown integer setcc!");
2531    case ISD::SETEQ:  // X == Y  -> ~(X^Y)
2532      Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2533      N0 = DAG.getNOT(dl, Temp, MVT::i1);
2534      if (!DCI.isCalledByLegalizer())
2535        DCI.AddToWorklist(Temp.getNode());
2536      break;
2537    case ISD::SETNE:  // X != Y   -->  (X^Y)
2538      N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2539      break;
2540    case ISD::SETGT:  // X >s Y   -->  X == 0 & Y == 1  -->  ~X & Y
2541    case ISD::SETULT: // X <u Y   -->  X == 0 & Y == 1  -->  ~X & Y
2542      Temp = DAG.getNOT(dl, N0, MVT::i1);
2543      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2544      if (!DCI.isCalledByLegalizer())
2545        DCI.AddToWorklist(Temp.getNode());
2546      break;
2547    case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  ~Y & X
2548    case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  ~Y & X
2549      Temp = DAG.getNOT(dl, N1, MVT::i1);
2550      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2551      if (!DCI.isCalledByLegalizer())
2552        DCI.AddToWorklist(Temp.getNode());
2553      break;
2554    case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  ~X | Y
2555    case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  ~X | Y
2556      Temp = DAG.getNOT(dl, N0, MVT::i1);
2557      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2558      if (!DCI.isCalledByLegalizer())
2559        DCI.AddToWorklist(Temp.getNode());
2560      break;
2561    case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  ~Y | X
2562    case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  ~Y | X
2563      Temp = DAG.getNOT(dl, N1, MVT::i1);
2564      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2565      break;
2566    }
2567    if (VT != MVT::i1) {
2568      if (!DCI.isCalledByLegalizer())
2569        DCI.AddToWorklist(N0.getNode());
2570      // FIXME: If running after legalize, we probably can't do this.
2571      N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2572    }
2573    return N0;
2574  }
2575
2576  // Could not fold it.
2577  return SDValue();
2578}
2579
2580/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2581/// node is a GlobalAddress + offset.
2582bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2583                                    int64_t &Offset) const {
2584  if (isa<GlobalAddressSDNode>(N)) {
2585    GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2586    GA = GASD->getGlobal();
2587    Offset += GASD->getOffset();
2588    return true;
2589  }
2590
2591  if (N->getOpcode() == ISD::ADD) {
2592    SDValue N1 = N->getOperand(0);
2593    SDValue N2 = N->getOperand(1);
2594    if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2595      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2596      if (V) {
2597        Offset += V->getSExtValue();
2598        return true;
2599      }
2600    } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2601      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2602      if (V) {
2603        Offset += V->getSExtValue();
2604        return true;
2605      }
2606    }
2607  }
2608
2609  return false;
2610}
2611
2612
2613SDValue TargetLowering::
2614PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2615  // Default implementation: no optimization.
2616  return SDValue();
2617}
2618
2619//===----------------------------------------------------------------------===//
2620//  Inline Assembler Implementation Methods
2621//===----------------------------------------------------------------------===//
2622
2623
2624TargetLowering::ConstraintType
2625TargetLowering::getConstraintType(const std::string &Constraint) const {
2626  if (Constraint.size() == 1) {
2627    switch (Constraint[0]) {
2628    default: break;
2629    case 'r': return C_RegisterClass;
2630    case 'm':    // memory
2631    case 'o':    // offsetable
2632    case 'V':    // not offsetable
2633      return C_Memory;
2634    case 'i':    // Simple Integer or Relocatable Constant
2635    case 'n':    // Simple Integer
2636    case 'E':    // Floating Point Constant
2637    case 'F':    // Floating Point Constant
2638    case 's':    // Relocatable Constant
2639    case 'p':    // Address.
2640    case 'X':    // Allow ANY value.
2641    case 'I':    // Target registers.
2642    case 'J':
2643    case 'K':
2644    case 'L':
2645    case 'M':
2646    case 'N':
2647    case 'O':
2648    case 'P':
2649    case '<':
2650    case '>':
2651      return C_Other;
2652    }
2653  }
2654
2655  if (Constraint.size() > 1 && Constraint[0] == '{' &&
2656      Constraint[Constraint.size()-1] == '}')
2657    return C_Register;
2658  return C_Unknown;
2659}
2660
2661/// LowerXConstraint - try to replace an X constraint, which matches anything,
2662/// with another that has more specific requirements based on the type of the
2663/// corresponding operand.
2664const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2665  if (ConstraintVT.isInteger())
2666    return "r";
2667  if (ConstraintVT.isFloatingPoint())
2668    return "f";      // works for many targets
2669  return 0;
2670}
2671
2672/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2673/// vector.  If it is invalid, don't add anything to Ops.
2674void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2675                                                  std::string &Constraint,
2676                                                  std::vector<SDValue> &Ops,
2677                                                  SelectionDAG &DAG) const {
2678
2679  if (Constraint.length() > 1) return;
2680
2681  char ConstraintLetter = Constraint[0];
2682  switch (ConstraintLetter) {
2683  default: break;
2684  case 'X':     // Allows any operand; labels (basic block) use this.
2685    if (Op.getOpcode() == ISD::BasicBlock) {
2686      Ops.push_back(Op);
2687      return;
2688    }
2689    // fall through
2690  case 'i':    // Simple Integer or Relocatable Constant
2691  case 'n':    // Simple Integer
2692  case 's': {  // Relocatable Constant
2693    // These operands are interested in values of the form (GV+C), where C may
2694    // be folded in as an offset of GV, or it may be explicitly added.  Also, it
2695    // is possible and fine if either GV or C are missing.
2696    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2697    GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2698
2699    // If we have "(add GV, C)", pull out GV/C
2700    if (Op.getOpcode() == ISD::ADD) {
2701      C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2702      GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2703      if (C == 0 || GA == 0) {
2704        C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2705        GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2706      }
2707      if (C == 0 || GA == 0)
2708        C = 0, GA = 0;
2709    }
2710
2711    // If we find a valid operand, map to the TargetXXX version so that the
2712    // value itself doesn't get selected.
2713    if (GA) {   // Either &GV   or   &GV+C
2714      if (ConstraintLetter != 'n') {
2715        int64_t Offs = GA->getOffset();
2716        if (C) Offs += C->getZExtValue();
2717        Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2718                                                 C ? C->getDebugLoc() : DebugLoc(),
2719                                                 Op.getValueType(), Offs));
2720        return;
2721      }
2722    }
2723    if (C) {   // just C, no GV.
2724      // Simple constants are not allowed for 's'.
2725      if (ConstraintLetter != 's') {
2726        // gcc prints these as sign extended.  Sign extend value to 64 bits
2727        // now; without this it would get ZExt'd later in
2728        // ScheduleDAGSDNodes::EmitNode, which is very generic.
2729        Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2730                                            MVT::i64));
2731        return;
2732      }
2733    }
2734    break;
2735  }
2736  }
2737}
2738
2739std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2740getRegForInlineAsmConstraint(const std::string &Constraint,
2741                             EVT VT) const {
2742  if (Constraint[0] != '{')
2743    return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
2744  assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2745
2746  // Remove the braces from around the name.
2747  StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2748
2749  // Figure out which register class contains this reg.
2750  const TargetRegisterInfo *RI = TM.getRegisterInfo();
2751  for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2752       E = RI->regclass_end(); RCI != E; ++RCI) {
2753    const TargetRegisterClass *RC = *RCI;
2754
2755    // If none of the value types for this register class are valid, we
2756    // can't use it.  For example, 64-bit reg classes on 32-bit targets.
2757    bool isLegal = false;
2758    for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2759         I != E; ++I) {
2760      if (isTypeLegal(*I)) {
2761        isLegal = true;
2762        break;
2763      }
2764    }
2765
2766    if (!isLegal) continue;
2767
2768    for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2769         I != E; ++I) {
2770      if (RegName.equals_lower(RI->getName(*I)))
2771        return std::make_pair(*I, RC);
2772    }
2773  }
2774
2775  return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2776}
2777
2778//===----------------------------------------------------------------------===//
2779// Constraint Selection.
2780
2781/// isMatchingInputConstraint - Return true of this is an input operand that is
2782/// a matching constraint like "4".
2783bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2784  assert(!ConstraintCode.empty() && "No known constraint!");
2785  return isdigit(ConstraintCode[0]);
2786}
2787
2788/// getMatchedOperand - If this is an input matching constraint, this method
2789/// returns the output operand it matches.
2790unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2791  assert(!ConstraintCode.empty() && "No known constraint!");
2792  return atoi(ConstraintCode.c_str());
2793}
2794
2795
2796/// ParseConstraints - Split up the constraint string from the inline
2797/// assembly value into the specific constraints and their prefixes,
2798/// and also tie in the associated operand values.
2799/// If this returns an empty vector, and if the constraint string itself
2800/// isn't empty, there was an error parsing.
2801TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2802    ImmutableCallSite CS) const {
2803  /// ConstraintOperands - Information about all of the constraints.
2804  AsmOperandInfoVector ConstraintOperands;
2805  const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2806  unsigned maCount = 0; // Largest number of multiple alternative constraints.
2807
2808  // Do a prepass over the constraints, canonicalizing them, and building up the
2809  // ConstraintOperands list.
2810  InlineAsm::ConstraintInfoVector
2811    ConstraintInfos = IA->ParseConstraints();
2812
2813  unsigned ArgNo = 0;   // ArgNo - The argument of the CallInst.
2814  unsigned ResNo = 0;   // ResNo - The result number of the next output.
2815
2816  for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2817    ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2818    AsmOperandInfo &OpInfo = ConstraintOperands.back();
2819
2820    // Update multiple alternative constraint count.
2821    if (OpInfo.multipleAlternatives.size() > maCount)
2822      maCount = OpInfo.multipleAlternatives.size();
2823
2824    OpInfo.ConstraintVT = MVT::Other;
2825
2826    // Compute the value type for each operand.
2827    switch (OpInfo.Type) {
2828    case InlineAsm::isOutput:
2829      // Indirect outputs just consume an argument.
2830      if (OpInfo.isIndirect) {
2831        OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2832        break;
2833      }
2834
2835      // The return value of the call is this value.  As such, there is no
2836      // corresponding argument.
2837      assert(!CS.getType()->isVoidTy() &&
2838             "Bad inline asm!");
2839      if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
2840        OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
2841      } else {
2842        assert(ResNo == 0 && "Asm only has one result!");
2843        OpInfo.ConstraintVT = getValueType(CS.getType());
2844      }
2845      ++ResNo;
2846      break;
2847    case InlineAsm::isInput:
2848      OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2849      break;
2850    case InlineAsm::isClobber:
2851      // Nothing to do.
2852      break;
2853    }
2854
2855    if (OpInfo.CallOperandVal) {
2856      const llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2857      if (OpInfo.isIndirect) {
2858        const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2859        if (!PtrTy)
2860          report_fatal_error("Indirect operand for inline asm not a pointer!");
2861        OpTy = PtrTy->getElementType();
2862      }
2863
2864      // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2865      if (const StructType *STy = dyn_cast<StructType>(OpTy))
2866        if (STy->getNumElements() == 1)
2867          OpTy = STy->getElementType(0);
2868
2869      // If OpTy is not a single value, it may be a struct/union that we
2870      // can tile with integers.
2871      if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2872        unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2873        switch (BitSize) {
2874        default: break;
2875        case 1:
2876        case 8:
2877        case 16:
2878        case 32:
2879        case 64:
2880        case 128:
2881          OpInfo.ConstraintVT =
2882              EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2883          break;
2884        }
2885      } else if (dyn_cast<PointerType>(OpTy)) {
2886        OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2887      } else {
2888        OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2889      }
2890    }
2891  }
2892
2893  // If we have multiple alternative constraints, select the best alternative.
2894  if (ConstraintInfos.size()) {
2895    if (maCount) {
2896      unsigned bestMAIndex = 0;
2897      int bestWeight = -1;
2898      // weight:  -1 = invalid match, and 0 = so-so match to 5 = good match.
2899      int weight = -1;
2900      unsigned maIndex;
2901      // Compute the sums of the weights for each alternative, keeping track
2902      // of the best (highest weight) one so far.
2903      for (maIndex = 0; maIndex < maCount; ++maIndex) {
2904        int weightSum = 0;
2905        for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2906            cIndex != eIndex; ++cIndex) {
2907          AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2908          if (OpInfo.Type == InlineAsm::isClobber)
2909            continue;
2910
2911          // If this is an output operand with a matching input operand,
2912          // look up the matching input. If their types mismatch, e.g. one
2913          // is an integer, the other is floating point, or their sizes are
2914          // different, flag it as an maCantMatch.
2915          if (OpInfo.hasMatchingInput()) {
2916            AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2917            if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2918              if ((OpInfo.ConstraintVT.isInteger() !=
2919                   Input.ConstraintVT.isInteger()) ||
2920                  (OpInfo.ConstraintVT.getSizeInBits() !=
2921                   Input.ConstraintVT.getSizeInBits())) {
2922                weightSum = -1;  // Can't match.
2923                break;
2924              }
2925            }
2926          }
2927          weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2928          if (weight == -1) {
2929            weightSum = -1;
2930            break;
2931          }
2932          weightSum += weight;
2933        }
2934        // Update best.
2935        if (weightSum > bestWeight) {
2936          bestWeight = weightSum;
2937          bestMAIndex = maIndex;
2938        }
2939      }
2940
2941      // Now select chosen alternative in each constraint.
2942      for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2943          cIndex != eIndex; ++cIndex) {
2944        AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2945        if (cInfo.Type == InlineAsm::isClobber)
2946          continue;
2947        cInfo.selectAlternative(bestMAIndex);
2948      }
2949    }
2950  }
2951
2952  // Check and hook up tied operands, choose constraint code to use.
2953  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2954      cIndex != eIndex; ++cIndex) {
2955    AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2956
2957    // If this is an output operand with a matching input operand, look up the
2958    // matching input. If their types mismatch, e.g. one is an integer, the
2959    // other is floating point, or their sizes are different, flag it as an
2960    // error.
2961    if (OpInfo.hasMatchingInput()) {
2962      AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2963
2964      if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2965        if ((OpInfo.ConstraintVT.isInteger() !=
2966             Input.ConstraintVT.isInteger()) ||
2967            (OpInfo.ConstraintVT.getSizeInBits() !=
2968             Input.ConstraintVT.getSizeInBits())) {
2969          report_fatal_error("Unsupported asm: input constraint"
2970                             " with a matching output constraint of"
2971                             " incompatible type!");
2972        }
2973      }
2974
2975    }
2976  }
2977
2978  return ConstraintOperands;
2979}
2980
2981
2982/// getConstraintGenerality - Return an integer indicating how general CT
2983/// is.
2984static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2985  switch (CT) {
2986  default: llvm_unreachable("Unknown constraint type!");
2987  case TargetLowering::C_Other:
2988  case TargetLowering::C_Unknown:
2989    return 0;
2990  case TargetLowering::C_Register:
2991    return 1;
2992  case TargetLowering::C_RegisterClass:
2993    return 2;
2994  case TargetLowering::C_Memory:
2995    return 3;
2996  }
2997}
2998
2999/// Examine constraint type and operand type and determine a weight value.
3000/// This object must already have been set up with the operand type
3001/// and the current alternative constraint selected.
3002TargetLowering::ConstraintWeight
3003  TargetLowering::getMultipleConstraintMatchWeight(
3004    AsmOperandInfo &info, int maIndex) const {
3005  InlineAsm::ConstraintCodeVector *rCodes;
3006  if (maIndex >= (int)info.multipleAlternatives.size())
3007    rCodes = &info.Codes;
3008  else
3009    rCodes = &info.multipleAlternatives[maIndex].Codes;
3010  ConstraintWeight BestWeight = CW_Invalid;
3011
3012  // Loop over the options, keeping track of the most general one.
3013  for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
3014    ConstraintWeight weight =
3015      getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
3016    if (weight > BestWeight)
3017      BestWeight = weight;
3018  }
3019
3020  return BestWeight;
3021}
3022
3023/// Examine constraint type and operand type and determine a weight value.
3024/// This object must already have been set up with the operand type
3025/// and the current alternative constraint selected.
3026TargetLowering::ConstraintWeight
3027  TargetLowering::getSingleConstraintMatchWeight(
3028    AsmOperandInfo &info, const char *constraint) const {
3029  ConstraintWeight weight = CW_Invalid;
3030  Value *CallOperandVal = info.CallOperandVal;
3031    // If we don't have a value, we can't do a match,
3032    // but allow it at the lowest weight.
3033  if (CallOperandVal == NULL)
3034    return CW_Default;
3035  // Look at the constraint type.
3036  switch (*constraint) {
3037    case 'i': // immediate integer.
3038    case 'n': // immediate integer with a known value.
3039      if (isa<ConstantInt>(CallOperandVal))
3040        weight = CW_Constant;
3041      break;
3042    case 's': // non-explicit intregal immediate.
3043      if (isa<GlobalValue>(CallOperandVal))
3044        weight = CW_Constant;
3045      break;
3046    case 'E': // immediate float if host format.
3047    case 'F': // immediate float.
3048      if (isa<ConstantFP>(CallOperandVal))
3049        weight = CW_Constant;
3050      break;
3051    case '<': // memory operand with autodecrement.
3052    case '>': // memory operand with autoincrement.
3053    case 'm': // memory operand.
3054    case 'o': // offsettable memory operand
3055    case 'V': // non-offsettable memory operand
3056      weight = CW_Memory;
3057      break;
3058    case 'r': // general register.
3059    case 'g': // general register, memory operand or immediate integer.
3060              // note: Clang converts "g" to "imr".
3061      if (CallOperandVal->getType()->isIntegerTy())
3062        weight = CW_Register;
3063      break;
3064    case 'X': // any operand.
3065    default:
3066      weight = CW_Default;
3067      break;
3068  }
3069  return weight;
3070}
3071
3072/// ChooseConstraint - If there are multiple different constraints that we
3073/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
3074/// This is somewhat tricky: constraints fall into four classes:
3075///    Other         -> immediates and magic values
3076///    Register      -> one specific register
3077///    RegisterClass -> a group of regs
3078///    Memory        -> memory
3079/// Ideally, we would pick the most specific constraint possible: if we have
3080/// something that fits into a register, we would pick it.  The problem here
3081/// is that if we have something that could either be in a register or in
3082/// memory that use of the register could cause selection of *other*
3083/// operands to fail: they might only succeed if we pick memory.  Because of
3084/// this the heuristic we use is:
3085///
3086///  1) If there is an 'other' constraint, and if the operand is valid for
3087///     that constraint, use it.  This makes us take advantage of 'i'
3088///     constraints when available.
3089///  2) Otherwise, pick the most general constraint present.  This prefers
3090///     'm' over 'r', for example.
3091///
3092static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
3093                             const TargetLowering &TLI,
3094                             SDValue Op, SelectionDAG *DAG) {
3095  assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3096  unsigned BestIdx = 0;
3097  TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3098  int BestGenerality = -1;
3099
3100  // Loop over the options, keeping track of the most general one.
3101  for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3102    TargetLowering::ConstraintType CType =
3103      TLI.getConstraintType(OpInfo.Codes[i]);
3104
3105    // If this is an 'other' constraint, see if the operand is valid for it.
3106    // For example, on X86 we might have an 'rI' constraint.  If the operand
3107    // is an integer in the range [0..31] we want to use I (saving a load
3108    // of a register), otherwise we must use 'r'.
3109    if (CType == TargetLowering::C_Other && Op.getNode()) {
3110      assert(OpInfo.Codes[i].size() == 1 &&
3111             "Unhandled multi-letter 'other' constraint");
3112      std::vector<SDValue> ResultOps;
3113      TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
3114                                       ResultOps, *DAG);
3115      if (!ResultOps.empty()) {
3116        BestType = CType;
3117        BestIdx = i;
3118        break;
3119      }
3120    }
3121
3122    // Things with matching constraints can only be registers, per gcc
3123    // documentation.  This mainly affects "g" constraints.
3124    if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3125      continue;
3126
3127    // This constraint letter is more general than the previous one, use it.
3128    int Generality = getConstraintGenerality(CType);
3129    if (Generality > BestGenerality) {
3130      BestType = CType;
3131      BestIdx = i;
3132      BestGenerality = Generality;
3133    }
3134  }
3135
3136  OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3137  OpInfo.ConstraintType = BestType;
3138}
3139
3140/// ComputeConstraintToUse - Determines the constraint code and constraint
3141/// type to use for the specific AsmOperandInfo, setting
3142/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
3143void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3144                                            SDValue Op,
3145                                            SelectionDAG *DAG) const {
3146  assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
3147
3148  // Single-letter constraints ('r') are very common.
3149  if (OpInfo.Codes.size() == 1) {
3150    OpInfo.ConstraintCode = OpInfo.Codes[0];
3151    OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3152  } else {
3153    ChooseConstraint(OpInfo, *this, Op, DAG);
3154  }
3155
3156  // 'X' matches anything.
3157  if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3158    // Labels and constants are handled elsewhere ('X' is the only thing
3159    // that matches labels).  For Functions, the type here is the type of
3160    // the result, which is not what we want to look at; leave them alone.
3161    Value *v = OpInfo.CallOperandVal;
3162    if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3163      OpInfo.CallOperandVal = v;
3164      return;
3165    }
3166
3167    // Otherwise, try to resolve it to something we know about by looking at
3168    // the actual operand type.
3169    if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3170      OpInfo.ConstraintCode = Repl;
3171      OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3172    }
3173  }
3174}
3175
3176//===----------------------------------------------------------------------===//
3177//  Loop Strength Reduction hooks
3178//===----------------------------------------------------------------------===//
3179
3180/// isLegalAddressingMode - Return true if the addressing mode represented
3181/// by AM is legal for this target, for a load/store of the specified type.
3182bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
3183                                           const Type *Ty) const {
3184  // The default implementation of this implements a conservative RISCy, r+r and
3185  // r+i addr mode.
3186
3187  // Allows a sign-extended 16-bit immediate field.
3188  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3189    return false;
3190
3191  // No global is ever allowed as a base.
3192  if (AM.BaseGV)
3193    return false;
3194
3195  // Only support r+r,
3196  switch (AM.Scale) {
3197  case 0:  // "r+i" or just "i", depending on HasBaseReg.
3198    break;
3199  case 1:
3200    if (AM.HasBaseReg && AM.BaseOffs)  // "r+r+i" is not allowed.
3201      return false;
3202    // Otherwise we have r+r or r+i.
3203    break;
3204  case 2:
3205    if (AM.HasBaseReg || AM.BaseOffs)  // 2*r+r  or  2*r+i is not allowed.
3206      return false;
3207    // Allow 2*r as r+r.
3208    break;
3209  }
3210
3211  return true;
3212}
3213
3214/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3215/// return a DAG expression to select that will generate the same value by
3216/// multiplying by a magic number.  See:
3217/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3218SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
3219                                  std::vector<SDNode*>* Created) const {
3220  EVT VT = N->getValueType(0);
3221  DebugLoc dl= N->getDebugLoc();
3222
3223  // Check to see if we can do this.
3224  // FIXME: We should be more aggressive here.
3225  if (!isTypeLegal(VT))
3226    return SDValue();
3227
3228  APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3229  APInt::ms magics = d.magic();
3230
3231  // Multiply the numerator (operand 0) by the magic value
3232  // FIXME: We should support doing a MUL in a wider type
3233  SDValue Q;
3234  if (isOperationLegalOrCustom(ISD::MULHS, VT))
3235    Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
3236                    DAG.getConstant(magics.m, VT));
3237  else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
3238    Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
3239                              N->getOperand(0),
3240                              DAG.getConstant(magics.m, VT)).getNode(), 1);
3241  else
3242    return SDValue();       // No mulhs or equvialent
3243  // If d > 0 and m < 0, add the numerator
3244  if (d.isStrictlyPositive() && magics.m.isNegative()) {
3245    Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
3246    if (Created)
3247      Created->push_back(Q.getNode());
3248  }
3249  // If d < 0 and m > 0, subtract the numerator.
3250  if (d.isNegative() && magics.m.isStrictlyPositive()) {
3251    Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
3252    if (Created)
3253      Created->push_back(Q.getNode());
3254  }
3255  // Shift right algebraic if shift value is nonzero
3256  if (magics.s > 0) {
3257    Q = DAG.getNode(ISD::SRA, dl, VT, Q,
3258                 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3259    if (Created)
3260      Created->push_back(Q.getNode());
3261  }
3262  // Extract the sign bit and add it to the quotient
3263  SDValue T =
3264    DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
3265                                           getShiftAmountTy(Q.getValueType())));
3266  if (Created)
3267    Created->push_back(T.getNode());
3268  return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3269}
3270
3271/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3272/// return a DAG expression to select that will generate the same value by
3273/// multiplying by a magic number.  See:
3274/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3275SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
3276                                  std::vector<SDNode*>* Created) const {
3277  EVT VT = N->getValueType(0);
3278  DebugLoc dl = N->getDebugLoc();
3279
3280  // Check to see if we can do this.
3281  // FIXME: We should be more aggressive here.
3282  if (!isTypeLegal(VT))
3283    return SDValue();
3284
3285  // FIXME: We should use a narrower constant when the upper
3286  // bits are known to be zero.
3287  const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3288  APInt::mu magics = N1C.magicu();
3289
3290  SDValue Q = N->getOperand(0);
3291
3292  // If the divisor is even, we can avoid using the expensive fixup by shifting
3293  // the divided value upfront.
3294  if (magics.a != 0 && !N1C[0]) {
3295    unsigned Shift = N1C.countTrailingZeros();
3296    Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3297                    DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3298    if (Created)
3299      Created->push_back(Q.getNode());
3300
3301    // Get magic number for the shifted divisor.
3302    magics = N1C.lshr(Shift).magicu(Shift);
3303    assert(magics.a == 0 && "Should use cheap fixup now");
3304  }
3305
3306  // Multiply the numerator (operand 0) by the magic value
3307  // FIXME: We should support doing a MUL in a wider type
3308  if (isOperationLegalOrCustom(ISD::MULHU, VT))
3309    Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
3310  else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
3311    Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3312                            DAG.getConstant(magics.m, VT)).getNode(), 1);
3313  else
3314    return SDValue();       // No mulhu or equvialent
3315  if (Created)
3316    Created->push_back(Q.getNode());
3317
3318  if (magics.a == 0) {
3319    assert(magics.s < N1C.getBitWidth() &&
3320           "We shouldn't generate an undefined shift!");
3321    return DAG.getNode(ISD::SRL, dl, VT, Q,
3322                 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3323  } else {
3324    SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3325    if (Created)
3326      Created->push_back(NPQ.getNode());
3327    NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
3328                      DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
3329    if (Created)
3330      Created->push_back(NPQ.getNode());
3331    NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3332    if (Created)
3333      Created->push_back(NPQ.getNode());
3334    return DAG.getNode(ISD::SRL, dl, VT, NPQ,
3335             DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
3336  }
3337}
3338