TargetLowering.cpp revision 0a9481f44fe4fc76e59109992940a76b2a3f9b3b
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/CodeGen/Analysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineJumpTableInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31#include <cctype> 32using namespace llvm; 33 34namespace llvm { 35TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 36 bool isLocal = GV->hasLocalLinkage(); 37 bool isDeclaration = GV->isDeclaration(); 38 // FIXME: what should we do for protected and internal visibility? 39 // For variables, is internal different from hidden? 40 bool isHidden = GV->hasHiddenVisibility(); 41 42 if (reloc == Reloc::PIC_) { 43 if (isLocal || isHidden) 44 return TLSModel::LocalDynamic; 45 else 46 return TLSModel::GeneralDynamic; 47 } else { 48 if (!isDeclaration || isHidden) 49 return TLSModel::LocalExec; 50 else 51 return TLSModel::InitialExec; 52 } 53} 54} 55 56/// InitLibcallNames - Set default libcall names. 57/// 58static void InitLibcallNames(const char **Names) { 59 Names[RTLIB::SHL_I16] = "__ashlhi3"; 60 Names[RTLIB::SHL_I32] = "__ashlsi3"; 61 Names[RTLIB::SHL_I64] = "__ashldi3"; 62 Names[RTLIB::SHL_I128] = "__ashlti3"; 63 Names[RTLIB::SRL_I16] = "__lshrhi3"; 64 Names[RTLIB::SRL_I32] = "__lshrsi3"; 65 Names[RTLIB::SRL_I64] = "__lshrdi3"; 66 Names[RTLIB::SRL_I128] = "__lshrti3"; 67 Names[RTLIB::SRA_I16] = "__ashrhi3"; 68 Names[RTLIB::SRA_I32] = "__ashrsi3"; 69 Names[RTLIB::SRA_I64] = "__ashrdi3"; 70 Names[RTLIB::SRA_I128] = "__ashrti3"; 71 Names[RTLIB::MUL_I8] = "__mulqi3"; 72 Names[RTLIB::MUL_I16] = "__mulhi3"; 73 Names[RTLIB::MUL_I32] = "__mulsi3"; 74 Names[RTLIB::MUL_I64] = "__muldi3"; 75 Names[RTLIB::MUL_I128] = "__multi3"; 76 Names[RTLIB::SDIV_I8] = "__divqi3"; 77 Names[RTLIB::SDIV_I16] = "__divhi3"; 78 Names[RTLIB::SDIV_I32] = "__divsi3"; 79 Names[RTLIB::SDIV_I64] = "__divdi3"; 80 Names[RTLIB::SDIV_I128] = "__divti3"; 81 Names[RTLIB::UDIV_I8] = "__udivqi3"; 82 Names[RTLIB::UDIV_I16] = "__udivhi3"; 83 Names[RTLIB::UDIV_I32] = "__udivsi3"; 84 Names[RTLIB::UDIV_I64] = "__udivdi3"; 85 Names[RTLIB::UDIV_I128] = "__udivti3"; 86 Names[RTLIB::SREM_I8] = "__modqi3"; 87 Names[RTLIB::SREM_I16] = "__modhi3"; 88 Names[RTLIB::SREM_I32] = "__modsi3"; 89 Names[RTLIB::SREM_I64] = "__moddi3"; 90 Names[RTLIB::SREM_I128] = "__modti3"; 91 Names[RTLIB::UREM_I8] = "__umodqi3"; 92 Names[RTLIB::UREM_I16] = "__umodhi3"; 93 Names[RTLIB::UREM_I32] = "__umodsi3"; 94 Names[RTLIB::UREM_I64] = "__umoddi3"; 95 Names[RTLIB::UREM_I128] = "__umodti3"; 96 Names[RTLIB::NEG_I32] = "__negsi2"; 97 Names[RTLIB::NEG_I64] = "__negdi2"; 98 Names[RTLIB::ADD_F32] = "__addsf3"; 99 Names[RTLIB::ADD_F64] = "__adddf3"; 100 Names[RTLIB::ADD_F80] = "__addxf3"; 101 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 102 Names[RTLIB::SUB_F32] = "__subsf3"; 103 Names[RTLIB::SUB_F64] = "__subdf3"; 104 Names[RTLIB::SUB_F80] = "__subxf3"; 105 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 106 Names[RTLIB::MUL_F32] = "__mulsf3"; 107 Names[RTLIB::MUL_F64] = "__muldf3"; 108 Names[RTLIB::MUL_F80] = "__mulxf3"; 109 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 110 Names[RTLIB::DIV_F32] = "__divsf3"; 111 Names[RTLIB::DIV_F64] = "__divdf3"; 112 Names[RTLIB::DIV_F80] = "__divxf3"; 113 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 114 Names[RTLIB::REM_F32] = "fmodf"; 115 Names[RTLIB::REM_F64] = "fmod"; 116 Names[RTLIB::REM_F80] = "fmodl"; 117 Names[RTLIB::REM_PPCF128] = "fmodl"; 118 Names[RTLIB::POWI_F32] = "__powisf2"; 119 Names[RTLIB::POWI_F64] = "__powidf2"; 120 Names[RTLIB::POWI_F80] = "__powixf2"; 121 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 122 Names[RTLIB::SQRT_F32] = "sqrtf"; 123 Names[RTLIB::SQRT_F64] = "sqrt"; 124 Names[RTLIB::SQRT_F80] = "sqrtl"; 125 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 126 Names[RTLIB::LOG_F32] = "logf"; 127 Names[RTLIB::LOG_F64] = "log"; 128 Names[RTLIB::LOG_F80] = "logl"; 129 Names[RTLIB::LOG_PPCF128] = "logl"; 130 Names[RTLIB::LOG2_F32] = "log2f"; 131 Names[RTLIB::LOG2_F64] = "log2"; 132 Names[RTLIB::LOG2_F80] = "log2l"; 133 Names[RTLIB::LOG2_PPCF128] = "log2l"; 134 Names[RTLIB::LOG10_F32] = "log10f"; 135 Names[RTLIB::LOG10_F64] = "log10"; 136 Names[RTLIB::LOG10_F80] = "log10l"; 137 Names[RTLIB::LOG10_PPCF128] = "log10l"; 138 Names[RTLIB::EXP_F32] = "expf"; 139 Names[RTLIB::EXP_F64] = "exp"; 140 Names[RTLIB::EXP_F80] = "expl"; 141 Names[RTLIB::EXP_PPCF128] = "expl"; 142 Names[RTLIB::EXP2_F32] = "exp2f"; 143 Names[RTLIB::EXP2_F64] = "exp2"; 144 Names[RTLIB::EXP2_F80] = "exp2l"; 145 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 146 Names[RTLIB::SIN_F32] = "sinf"; 147 Names[RTLIB::SIN_F64] = "sin"; 148 Names[RTLIB::SIN_F80] = "sinl"; 149 Names[RTLIB::SIN_PPCF128] = "sinl"; 150 Names[RTLIB::COS_F32] = "cosf"; 151 Names[RTLIB::COS_F64] = "cos"; 152 Names[RTLIB::COS_F80] = "cosl"; 153 Names[RTLIB::COS_PPCF128] = "cosl"; 154 Names[RTLIB::POW_F32] = "powf"; 155 Names[RTLIB::POW_F64] = "pow"; 156 Names[RTLIB::POW_F80] = "powl"; 157 Names[RTLIB::POW_PPCF128] = "powl"; 158 Names[RTLIB::CEIL_F32] = "ceilf"; 159 Names[RTLIB::CEIL_F64] = "ceil"; 160 Names[RTLIB::CEIL_F80] = "ceill"; 161 Names[RTLIB::CEIL_PPCF128] = "ceill"; 162 Names[RTLIB::TRUNC_F32] = "truncf"; 163 Names[RTLIB::TRUNC_F64] = "trunc"; 164 Names[RTLIB::TRUNC_F80] = "truncl"; 165 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 166 Names[RTLIB::RINT_F32] = "rintf"; 167 Names[RTLIB::RINT_F64] = "rint"; 168 Names[RTLIB::RINT_F80] = "rintl"; 169 Names[RTLIB::RINT_PPCF128] = "rintl"; 170 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 171 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 172 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 173 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 174 Names[RTLIB::FLOOR_F32] = "floorf"; 175 Names[RTLIB::FLOOR_F64] = "floor"; 176 Names[RTLIB::FLOOR_F80] = "floorl"; 177 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 178 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 179 Names[RTLIB::COPYSIGN_F64] = "copysign"; 180 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 181 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 182 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 183 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 184 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 185 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 186 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 187 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 188 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 189 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 190 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 191 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 192 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 193 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 194 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 195 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 196 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 197 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 198 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 199 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 200 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 201 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 202 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 203 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 204 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 205 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 206 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 207 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 208 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 209 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 210 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 211 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 212 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 213 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 214 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 215 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 216 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 217 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 218 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 219 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 220 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 221 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 222 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 223 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 224 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 225 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 226 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 227 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 228 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 229 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 230 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 231 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 232 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 233 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 234 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 235 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 236 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 237 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 238 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 239 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 240 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 241 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 242 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 243 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 244 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 245 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 246 Names[RTLIB::OEQ_F32] = "__eqsf2"; 247 Names[RTLIB::OEQ_F64] = "__eqdf2"; 248 Names[RTLIB::UNE_F32] = "__nesf2"; 249 Names[RTLIB::UNE_F64] = "__nedf2"; 250 Names[RTLIB::OGE_F32] = "__gesf2"; 251 Names[RTLIB::OGE_F64] = "__gedf2"; 252 Names[RTLIB::OLT_F32] = "__ltsf2"; 253 Names[RTLIB::OLT_F64] = "__ltdf2"; 254 Names[RTLIB::OLE_F32] = "__lesf2"; 255 Names[RTLIB::OLE_F64] = "__ledf2"; 256 Names[RTLIB::OGT_F32] = "__gtsf2"; 257 Names[RTLIB::OGT_F64] = "__gtdf2"; 258 Names[RTLIB::UO_F32] = "__unordsf2"; 259 Names[RTLIB::UO_F64] = "__unorddf2"; 260 Names[RTLIB::O_F32] = "__unordsf2"; 261 Names[RTLIB::O_F64] = "__unorddf2"; 262 Names[RTLIB::MEMCPY] = "memcpy"; 263 Names[RTLIB::MEMMOVE] = "memmove"; 264 Names[RTLIB::MEMSET] = "memset"; 265 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 268 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 269 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 272 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 273 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 274 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 275 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 276 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 277 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 278 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 279 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 280 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 281 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 282 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 283 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 284 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 285 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 286 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 287 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 288 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 289 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 290 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 291 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 292 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4"; 293 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 294 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 295 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 296 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 297 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 298} 299 300/// InitLibcallCallingConvs - Set default libcall CallingConvs. 301/// 302static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 303 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 304 CCs[i] = CallingConv::C; 305 } 306} 307 308/// getFPEXT - Return the FPEXT_*_* value for the given types, or 309/// UNKNOWN_LIBCALL if there is none. 310RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 311 if (OpVT == MVT::f32) { 312 if (RetVT == MVT::f64) 313 return FPEXT_F32_F64; 314 } 315 316 return UNKNOWN_LIBCALL; 317} 318 319/// getFPROUND - Return the FPROUND_*_* value for the given types, or 320/// UNKNOWN_LIBCALL if there is none. 321RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 322 if (RetVT == MVT::f32) { 323 if (OpVT == MVT::f64) 324 return FPROUND_F64_F32; 325 if (OpVT == MVT::f80) 326 return FPROUND_F80_F32; 327 if (OpVT == MVT::ppcf128) 328 return FPROUND_PPCF128_F32; 329 } else if (RetVT == MVT::f64) { 330 if (OpVT == MVT::f80) 331 return FPROUND_F80_F64; 332 if (OpVT == MVT::ppcf128) 333 return FPROUND_PPCF128_F64; 334 } 335 336 return UNKNOWN_LIBCALL; 337} 338 339/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 340/// UNKNOWN_LIBCALL if there is none. 341RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 342 if (OpVT == MVT::f32) { 343 if (RetVT == MVT::i8) 344 return FPTOSINT_F32_I8; 345 if (RetVT == MVT::i16) 346 return FPTOSINT_F32_I16; 347 if (RetVT == MVT::i32) 348 return FPTOSINT_F32_I32; 349 if (RetVT == MVT::i64) 350 return FPTOSINT_F32_I64; 351 if (RetVT == MVT::i128) 352 return FPTOSINT_F32_I128; 353 } else if (OpVT == MVT::f64) { 354 if (RetVT == MVT::i8) 355 return FPTOSINT_F64_I8; 356 if (RetVT == MVT::i16) 357 return FPTOSINT_F64_I16; 358 if (RetVT == MVT::i32) 359 return FPTOSINT_F64_I32; 360 if (RetVT == MVT::i64) 361 return FPTOSINT_F64_I64; 362 if (RetVT == MVT::i128) 363 return FPTOSINT_F64_I128; 364 } else if (OpVT == MVT::f80) { 365 if (RetVT == MVT::i32) 366 return FPTOSINT_F80_I32; 367 if (RetVT == MVT::i64) 368 return FPTOSINT_F80_I64; 369 if (RetVT == MVT::i128) 370 return FPTOSINT_F80_I128; 371 } else if (OpVT == MVT::ppcf128) { 372 if (RetVT == MVT::i32) 373 return FPTOSINT_PPCF128_I32; 374 if (RetVT == MVT::i64) 375 return FPTOSINT_PPCF128_I64; 376 if (RetVT == MVT::i128) 377 return FPTOSINT_PPCF128_I128; 378 } 379 return UNKNOWN_LIBCALL; 380} 381 382/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 383/// UNKNOWN_LIBCALL if there is none. 384RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 385 if (OpVT == MVT::f32) { 386 if (RetVT == MVT::i8) 387 return FPTOUINT_F32_I8; 388 if (RetVT == MVT::i16) 389 return FPTOUINT_F32_I16; 390 if (RetVT == MVT::i32) 391 return FPTOUINT_F32_I32; 392 if (RetVT == MVT::i64) 393 return FPTOUINT_F32_I64; 394 if (RetVT == MVT::i128) 395 return FPTOUINT_F32_I128; 396 } else if (OpVT == MVT::f64) { 397 if (RetVT == MVT::i8) 398 return FPTOUINT_F64_I8; 399 if (RetVT == MVT::i16) 400 return FPTOUINT_F64_I16; 401 if (RetVT == MVT::i32) 402 return FPTOUINT_F64_I32; 403 if (RetVT == MVT::i64) 404 return FPTOUINT_F64_I64; 405 if (RetVT == MVT::i128) 406 return FPTOUINT_F64_I128; 407 } else if (OpVT == MVT::f80) { 408 if (RetVT == MVT::i32) 409 return FPTOUINT_F80_I32; 410 if (RetVT == MVT::i64) 411 return FPTOUINT_F80_I64; 412 if (RetVT == MVT::i128) 413 return FPTOUINT_F80_I128; 414 } else if (OpVT == MVT::ppcf128) { 415 if (RetVT == MVT::i32) 416 return FPTOUINT_PPCF128_I32; 417 if (RetVT == MVT::i64) 418 return FPTOUINT_PPCF128_I64; 419 if (RetVT == MVT::i128) 420 return FPTOUINT_PPCF128_I128; 421 } 422 return UNKNOWN_LIBCALL; 423} 424 425/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 426/// UNKNOWN_LIBCALL if there is none. 427RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 428 if (OpVT == MVT::i32) { 429 if (RetVT == MVT::f32) 430 return SINTTOFP_I32_F32; 431 else if (RetVT == MVT::f64) 432 return SINTTOFP_I32_F64; 433 else if (RetVT == MVT::f80) 434 return SINTTOFP_I32_F80; 435 else if (RetVT == MVT::ppcf128) 436 return SINTTOFP_I32_PPCF128; 437 } else if (OpVT == MVT::i64) { 438 if (RetVT == MVT::f32) 439 return SINTTOFP_I64_F32; 440 else if (RetVT == MVT::f64) 441 return SINTTOFP_I64_F64; 442 else if (RetVT == MVT::f80) 443 return SINTTOFP_I64_F80; 444 else if (RetVT == MVT::ppcf128) 445 return SINTTOFP_I64_PPCF128; 446 } else if (OpVT == MVT::i128) { 447 if (RetVT == MVT::f32) 448 return SINTTOFP_I128_F32; 449 else if (RetVT == MVT::f64) 450 return SINTTOFP_I128_F64; 451 else if (RetVT == MVT::f80) 452 return SINTTOFP_I128_F80; 453 else if (RetVT == MVT::ppcf128) 454 return SINTTOFP_I128_PPCF128; 455 } 456 return UNKNOWN_LIBCALL; 457} 458 459/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 460/// UNKNOWN_LIBCALL if there is none. 461RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 462 if (OpVT == MVT::i32) { 463 if (RetVT == MVT::f32) 464 return UINTTOFP_I32_F32; 465 else if (RetVT == MVT::f64) 466 return UINTTOFP_I32_F64; 467 else if (RetVT == MVT::f80) 468 return UINTTOFP_I32_F80; 469 else if (RetVT == MVT::ppcf128) 470 return UINTTOFP_I32_PPCF128; 471 } else if (OpVT == MVT::i64) { 472 if (RetVT == MVT::f32) 473 return UINTTOFP_I64_F32; 474 else if (RetVT == MVT::f64) 475 return UINTTOFP_I64_F64; 476 else if (RetVT == MVT::f80) 477 return UINTTOFP_I64_F80; 478 else if (RetVT == MVT::ppcf128) 479 return UINTTOFP_I64_PPCF128; 480 } else if (OpVT == MVT::i128) { 481 if (RetVT == MVT::f32) 482 return UINTTOFP_I128_F32; 483 else if (RetVT == MVT::f64) 484 return UINTTOFP_I128_F64; 485 else if (RetVT == MVT::f80) 486 return UINTTOFP_I128_F80; 487 else if (RetVT == MVT::ppcf128) 488 return UINTTOFP_I128_PPCF128; 489 } 490 return UNKNOWN_LIBCALL; 491} 492 493/// InitCmpLibcallCCs - Set default comparison libcall CC. 494/// 495static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 496 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 497 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 498 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 499 CCs[RTLIB::UNE_F32] = ISD::SETNE; 500 CCs[RTLIB::UNE_F64] = ISD::SETNE; 501 CCs[RTLIB::OGE_F32] = ISD::SETGE; 502 CCs[RTLIB::OGE_F64] = ISD::SETGE; 503 CCs[RTLIB::OLT_F32] = ISD::SETLT; 504 CCs[RTLIB::OLT_F64] = ISD::SETLT; 505 CCs[RTLIB::OLE_F32] = ISD::SETLE; 506 CCs[RTLIB::OLE_F64] = ISD::SETLE; 507 CCs[RTLIB::OGT_F32] = ISD::SETGT; 508 CCs[RTLIB::OGT_F64] = ISD::SETGT; 509 CCs[RTLIB::UO_F32] = ISD::SETNE; 510 CCs[RTLIB::UO_F64] = ISD::SETNE; 511 CCs[RTLIB::O_F32] = ISD::SETEQ; 512 CCs[RTLIB::O_F64] = ISD::SETEQ; 513} 514 515/// NOTE: The constructor takes ownership of TLOF. 516TargetLowering::TargetLowering(const TargetMachine &tm, 517 const TargetLoweringObjectFile *tlof) 518 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 519 // All operations default to being supported. 520 memset(OpActions, 0, sizeof(OpActions)); 521 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 522 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 523 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 524 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 525 526 // Set default actions for various operations. 527 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 528 // Default all indexed load / store to expand. 529 for (unsigned IM = (unsigned)ISD::PRE_INC; 530 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 531 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 532 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 533 } 534 535 // These operations default to expand. 536 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 537 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 538 } 539 540 // Most targets ignore the @llvm.prefetch intrinsic. 541 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 542 543 // ConstantFP nodes default to expand. Targets can either change this to 544 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 545 // to optimize expansions for certain constants. 546 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 547 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 548 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 549 550 // These library functions default to expand. 551 setOperationAction(ISD::FLOG , MVT::f64, Expand); 552 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 553 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 554 setOperationAction(ISD::FEXP , MVT::f64, Expand); 555 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 556 setOperationAction(ISD::FLOG , MVT::f32, Expand); 557 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 558 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 559 setOperationAction(ISD::FEXP , MVT::f32, Expand); 560 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 561 562 // Default ISD::TRAP to expand (which turns it into abort). 563 setOperationAction(ISD::TRAP, MVT::Other, Expand); 564 565 IsLittleEndian = TD->isLittleEndian(); 566 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 567 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 568 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 569 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 570 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize 571 = maxStoresPerMemmoveOptSize = 4; 572 benefitFromCodePlacementOpt = false; 573 UseUnderscoreSetJmp = false; 574 UseUnderscoreLongJmp = false; 575 SelectIsExpensive = false; 576 IntDivIsCheap = false; 577 Pow2DivIsCheap = false; 578 JumpIsExpensive = false; 579 StackPointerRegisterToSaveRestore = 0; 580 ExceptionPointerRegister = 0; 581 ExceptionSelectorRegister = 0; 582 BooleanContents = UndefinedBooleanContent; 583 SchedPreferenceInfo = Sched::Latency; 584 JumpBufSize = 0; 585 JumpBufAlignment = 0; 586 PrefLoopAlignment = 0; 587 MinStackArgumentAlignment = 1; 588 ShouldFoldAtomicFences = false; 589 590 InitLibcallNames(LibcallRoutineNames); 591 InitCmpLibcallCCs(CmpLibcallCCs); 592 InitLibcallCallingConvs(LibcallCallingConvs); 593} 594 595TargetLowering::~TargetLowering() { 596 delete &TLOF; 597} 598 599/// canOpTrap - Returns true if the operation can trap for the value type. 600/// VT must be a legal type. 601bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 602 assert(isTypeLegal(VT)); 603 switch (Op) { 604 default: 605 return false; 606 case ISD::FDIV: 607 case ISD::FREM: 608 case ISD::SDIV: 609 case ISD::UDIV: 610 case ISD::SREM: 611 case ISD::UREM: 612 return true; 613 } 614} 615 616 617static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 618 unsigned &NumIntermediates, 619 EVT &RegisterVT, 620 TargetLowering *TLI) { 621 // Figure out the right, legal destination reg to copy into. 622 unsigned NumElts = VT.getVectorNumElements(); 623 MVT EltTy = VT.getVectorElementType(); 624 625 unsigned NumVectorRegs = 1; 626 627 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 628 // could break down into LHS/RHS like LegalizeDAG does. 629 if (!isPowerOf2_32(NumElts)) { 630 NumVectorRegs = NumElts; 631 NumElts = 1; 632 } 633 634 // Divide the input until we get to a supported size. This will always 635 // end with a scalar if the target doesn't support vectors. 636 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 637 NumElts >>= 1; 638 NumVectorRegs <<= 1; 639 } 640 641 NumIntermediates = NumVectorRegs; 642 643 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 644 if (!TLI->isTypeLegal(NewVT)) 645 NewVT = EltTy; 646 IntermediateVT = NewVT; 647 648 EVT DestVT = TLI->getRegisterType(NewVT); 649 RegisterVT = DestVT; 650 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 651 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 652 653 // Otherwise, promotion or legal types use the same number of registers as 654 // the vector decimated to the appropriate level. 655 return NumVectorRegs; 656} 657 658/// isLegalRC - Return true if the value types that can be represented by the 659/// specified register class are all legal. 660bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const { 661 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 662 I != E; ++I) { 663 if (isTypeLegal(*I)) 664 return true; 665 } 666 return false; 667} 668 669/// hasLegalSuperRegRegClasses - Return true if the specified register class 670/// has one or more super-reg register classes that are legal. 671bool 672TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{ 673 if (*RC->superregclasses_begin() == 0) 674 return false; 675 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 676 E = RC->superregclasses_end(); I != E; ++I) { 677 const TargetRegisterClass *RRC = *I; 678 if (isLegalRC(RRC)) 679 return true; 680 } 681 return false; 682} 683 684/// findRepresentativeClass - Return the largest legal super-reg register class 685/// of the register class for the specified type and its associated "cost". 686std::pair<const TargetRegisterClass*, uint8_t> 687TargetLowering::findRepresentativeClass(EVT VT) const { 688 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 689 if (!RC) 690 return std::make_pair(RC, 0); 691 const TargetRegisterClass *BestRC = RC; 692 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 693 E = RC->superregclasses_end(); I != E; ++I) { 694 const TargetRegisterClass *RRC = *I; 695 if (RRC->isASubClass() || !isLegalRC(RRC)) 696 continue; 697 if (!hasLegalSuperRegRegClasses(RRC)) 698 return std::make_pair(RRC, 1); 699 BestRC = RRC; 700 } 701 return std::make_pair(BestRC, 1); 702} 703 704 705/// computeRegisterProperties - Once all of the register classes are added, 706/// this allows us to compute derived properties we expose. 707void TargetLowering::computeRegisterProperties() { 708 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 709 "Too many value types for ValueTypeActions to hold!"); 710 711 // Everything defaults to needing one register. 712 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 713 NumRegistersForVT[i] = 1; 714 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 715 } 716 // ...except isVoid, which doesn't need any registers. 717 NumRegistersForVT[MVT::isVoid] = 0; 718 719 // Find the largest integer register class. 720 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 721 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 722 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 723 724 // Every integer value type larger than this largest register takes twice as 725 // many registers to represent as the previous ValueType. 726 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 727 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 728 if (!ExpandedVT.isInteger()) 729 break; 730 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 731 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 732 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 733 ValueTypeActions.setTypeAction(ExpandedVT, Expand); 734 } 735 736 // Inspect all of the ValueType's smaller than the largest integer 737 // register to see which ones need promotion. 738 unsigned LegalIntReg = LargestIntReg; 739 for (unsigned IntReg = LargestIntReg - 1; 740 IntReg >= (unsigned)MVT::i1; --IntReg) { 741 EVT IVT = (MVT::SimpleValueType)IntReg; 742 if (isTypeLegal(IVT)) { 743 LegalIntReg = IntReg; 744 } else { 745 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 746 (MVT::SimpleValueType)LegalIntReg; 747 ValueTypeActions.setTypeAction(IVT, Promote); 748 } 749 } 750 751 // ppcf128 type is really two f64's. 752 if (!isTypeLegal(MVT::ppcf128)) { 753 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 754 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 755 TransformToType[MVT::ppcf128] = MVT::f64; 756 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 757 } 758 759 // Decide how to handle f64. If the target does not have native f64 support, 760 // expand it to i64 and we will be generating soft float library calls. 761 if (!isTypeLegal(MVT::f64)) { 762 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 763 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 764 TransformToType[MVT::f64] = MVT::i64; 765 ValueTypeActions.setTypeAction(MVT::f64, Expand); 766 } 767 768 // Decide how to handle f32. If the target does not have native support for 769 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 770 if (!isTypeLegal(MVT::f32)) { 771 if (isTypeLegal(MVT::f64)) { 772 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 773 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 774 TransformToType[MVT::f32] = MVT::f64; 775 ValueTypeActions.setTypeAction(MVT::f32, Promote); 776 } else { 777 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 778 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 779 TransformToType[MVT::f32] = MVT::i32; 780 ValueTypeActions.setTypeAction(MVT::f32, Expand); 781 } 782 } 783 784 // Loop over all of the vector value types to see which need transformations. 785 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 786 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 787 MVT VT = (MVT::SimpleValueType)i; 788 if (isTypeLegal(VT)) continue; 789 790 // Determine if there is a legal wider type. If so, we should promote to 791 // that wider vector type. 792 EVT EltVT = VT.getVectorElementType(); 793 unsigned NElts = VT.getVectorNumElements(); 794 if (NElts != 1) { 795 bool IsLegalWiderType = false; 796 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 797 EVT SVT = (MVT::SimpleValueType)nVT; 798 if (SVT.getVectorElementType() == EltVT && 799 SVT.getVectorNumElements() > NElts && 800 isTypeLegal(SVT)) { 801 TransformToType[i] = SVT; 802 RegisterTypeForVT[i] = SVT; 803 NumRegistersForVT[i] = 1; 804 ValueTypeActions.setTypeAction(VT, Promote); 805 IsLegalWiderType = true; 806 break; 807 } 808 } 809 if (IsLegalWiderType) continue; 810 } 811 812 MVT IntermediateVT; 813 EVT RegisterVT; 814 unsigned NumIntermediates; 815 NumRegistersForVT[i] = 816 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 817 RegisterVT, this); 818 RegisterTypeForVT[i] = RegisterVT; 819 820 EVT NVT = VT.getPow2VectorType(); 821 if (NVT == VT) { 822 // Type is already a power of 2. The default action is to split. 823 TransformToType[i] = MVT::Other; 824 ValueTypeActions.setTypeAction(VT, Expand); 825 } else { 826 TransformToType[i] = NVT; 827 ValueTypeActions.setTypeAction(VT, Promote); 828 } 829 } 830 831 // Determine the 'representative' register class for each value type. 832 // An representative register class is the largest (meaning one which is 833 // not a sub-register class / subreg register class) legal register class for 834 // a group of value types. For example, on i386, i8, i16, and i32 835 // representative would be GR32; while on x86_64 it's GR64. 836 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 837 const TargetRegisterClass* RRC; 838 uint8_t Cost; 839 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 840 RepRegClassForVT[i] = RRC; 841 RepRegClassCostForVT[i] = Cost; 842 } 843} 844 845const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 846 return NULL; 847} 848 849 850MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 851 return PointerTy.SimpleTy; 852} 853 854MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 855 return MVT::i32; // return the default value 856} 857 858/// getVectorTypeBreakdown - Vector types are broken down into some number of 859/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 860/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 861/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 862/// 863/// This method returns the number of registers needed, and the VT for each 864/// register. It also returns the VT and quantity of the intermediate values 865/// before they are promoted/expanded. 866/// 867unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 868 EVT &IntermediateVT, 869 unsigned &NumIntermediates, 870 EVT &RegisterVT) const { 871 unsigned NumElts = VT.getVectorNumElements(); 872 873 // If there is a wider vector type with the same element type as this one, 874 // we should widen to that legal vector type. This handles things like 875 // <2 x float> -> <4 x float>. 876 if (NumElts != 1 && getTypeAction(VT) == Promote) { 877 RegisterVT = getTypeToTransformTo(Context, VT); 878 if (isTypeLegal(RegisterVT)) { 879 IntermediateVT = RegisterVT; 880 NumIntermediates = 1; 881 return 1; 882 } 883 } 884 885 // Figure out the right, legal destination reg to copy into. 886 EVT EltTy = VT.getVectorElementType(); 887 888 unsigned NumVectorRegs = 1; 889 890 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 891 // could break down into LHS/RHS like LegalizeDAG does. 892 if (!isPowerOf2_32(NumElts)) { 893 NumVectorRegs = NumElts; 894 NumElts = 1; 895 } 896 897 // Divide the input until we get to a supported size. This will always 898 // end with a scalar if the target doesn't support vectors. 899 while (NumElts > 1 && !isTypeLegal( 900 EVT::getVectorVT(Context, EltTy, NumElts))) { 901 NumElts >>= 1; 902 NumVectorRegs <<= 1; 903 } 904 905 NumIntermediates = NumVectorRegs; 906 907 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 908 if (!isTypeLegal(NewVT)) 909 NewVT = EltTy; 910 IntermediateVT = NewVT; 911 912 EVT DestVT = getRegisterType(Context, NewVT); 913 RegisterVT = DestVT; 914 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 915 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 916 917 // Otherwise, promotion or legal types use the same number of registers as 918 // the vector decimated to the appropriate level. 919 return NumVectorRegs; 920} 921 922/// Get the EVTs and ArgFlags collections that represent the legalized return 923/// type of the given function. This does not require a DAG or a return value, 924/// and is suitable for use before any DAGs for the function are constructed. 925/// TODO: Move this out of TargetLowering.cpp. 926void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr, 927 SmallVectorImpl<ISD::OutputArg> &Outs, 928 const TargetLowering &TLI, 929 SmallVectorImpl<uint64_t> *Offsets) { 930 SmallVector<EVT, 4> ValueVTs; 931 ComputeValueVTs(TLI, ReturnType, ValueVTs); 932 unsigned NumValues = ValueVTs.size(); 933 if (NumValues == 0) return; 934 unsigned Offset = 0; 935 936 for (unsigned j = 0, f = NumValues; j != f; ++j) { 937 EVT VT = ValueVTs[j]; 938 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 939 940 if (attr & Attribute::SExt) 941 ExtendKind = ISD::SIGN_EXTEND; 942 else if (attr & Attribute::ZExt) 943 ExtendKind = ISD::ZERO_EXTEND; 944 945 // FIXME: C calling convention requires the return type to be promoted to 946 // at least 32-bit. But this is not necessary for non-C calling 947 // conventions. The frontend should mark functions whose return values 948 // require promoting with signext or zeroext attributes. 949 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 950 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 951 if (VT.bitsLT(MinVT)) 952 VT = MinVT; 953 } 954 955 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 956 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 957 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 958 PartVT.getTypeForEVT(ReturnType->getContext())); 959 960 // 'inreg' on function refers to return value 961 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 962 if (attr & Attribute::InReg) 963 Flags.setInReg(); 964 965 // Propagate extension type if any 966 if (attr & Attribute::SExt) 967 Flags.setSExt(); 968 else if (attr & Attribute::ZExt) 969 Flags.setZExt(); 970 971 for (unsigned i = 0; i < NumParts; ++i) { 972 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true)); 973 if (Offsets) { 974 Offsets->push_back(Offset); 975 Offset += PartSize; 976 } 977 } 978 } 979} 980 981/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 982/// function arguments in the caller parameter area. This is the actual 983/// alignment, not its logarithm. 984unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 985 return TD->getCallFrameTypeAlignment(Ty); 986} 987 988/// getJumpTableEncoding - Return the entry encoding for a jump table in the 989/// current function. The returned value is a member of the 990/// MachineJumpTableInfo::JTEntryKind enum. 991unsigned TargetLowering::getJumpTableEncoding() const { 992 // In non-pic modes, just use the address of a block. 993 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 994 return MachineJumpTableInfo::EK_BlockAddress; 995 996 // In PIC mode, if the target supports a GPRel32 directive, use it. 997 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 998 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 999 1000 // Otherwise, use a label difference. 1001 return MachineJumpTableInfo::EK_LabelDifference32; 1002} 1003 1004SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1005 SelectionDAG &DAG) const { 1006 // If our PIC model is GP relative, use the global offset table as the base. 1007 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 1008 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 1009 return Table; 1010} 1011 1012/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1013/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1014/// MCExpr. 1015const MCExpr * 1016TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1017 unsigned JTI,MCContext &Ctx) const{ 1018 // The normal PIC reloc base is the label at the start of the jump table. 1019 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 1020} 1021 1022bool 1023TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1024 // Assume that everything is safe in static mode. 1025 if (getTargetMachine().getRelocationModel() == Reloc::Static) 1026 return true; 1027 1028 // In dynamic-no-pic mode, assume that known defined values are safe. 1029 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 1030 GA && 1031 !GA->getGlobal()->isDeclaration() && 1032 !GA->getGlobal()->isWeakForLinker()) 1033 return true; 1034 1035 // Otherwise assume nothing is safe. 1036 return false; 1037} 1038 1039//===----------------------------------------------------------------------===// 1040// Optimization Methods 1041//===----------------------------------------------------------------------===// 1042 1043/// ShrinkDemandedConstant - Check to see if the specified operand of the 1044/// specified instruction is a constant integer. If so, check to see if there 1045/// are any bits set in the constant that are not demanded. If so, shrink the 1046/// constant and return true. 1047bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 1048 const APInt &Demanded) { 1049 DebugLoc dl = Op.getDebugLoc(); 1050 1051 // FIXME: ISD::SELECT, ISD::SELECT_CC 1052 switch (Op.getOpcode()) { 1053 default: break; 1054 case ISD::XOR: 1055 case ISD::AND: 1056 case ISD::OR: { 1057 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1058 if (!C) return false; 1059 1060 if (Op.getOpcode() == ISD::XOR && 1061 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 1062 return false; 1063 1064 // if we can expand it to have all bits set, do it 1065 if (C->getAPIntValue().intersects(~Demanded)) { 1066 EVT VT = Op.getValueType(); 1067 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 1068 DAG.getConstant(Demanded & 1069 C->getAPIntValue(), 1070 VT)); 1071 return CombineTo(Op, New); 1072 } 1073 1074 break; 1075 } 1076 } 1077 1078 return false; 1079} 1080 1081/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1082/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1083/// cast, but it could be generalized for targets with other types of 1084/// implicit widening casts. 1085bool 1086TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 1087 unsigned BitWidth, 1088 const APInt &Demanded, 1089 DebugLoc dl) { 1090 assert(Op.getNumOperands() == 2 && 1091 "ShrinkDemandedOp only supports binary operators!"); 1092 assert(Op.getNode()->getNumValues() == 1 && 1093 "ShrinkDemandedOp only supports nodes with one result!"); 1094 1095 // Don't do this if the node has another user, which may require the 1096 // full value. 1097 if (!Op.getNode()->hasOneUse()) 1098 return false; 1099 1100 // Search for the smallest integer type with free casts to and from 1101 // Op's type. For expedience, just check power-of-2 integer types. 1102 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1103 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 1104 if (!isPowerOf2_32(SmallVTBits)) 1105 SmallVTBits = NextPowerOf2(SmallVTBits); 1106 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 1107 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 1108 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 1109 TLI.isZExtFree(SmallVT, Op.getValueType())) { 1110 // We found a type with free casts. 1111 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 1112 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1113 Op.getNode()->getOperand(0)), 1114 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1115 Op.getNode()->getOperand(1))); 1116 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 1117 return CombineTo(Op, Z); 1118 } 1119 } 1120 return false; 1121} 1122 1123/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1124/// DemandedMask bits of the result of Op are ever used downstream. If we can 1125/// use this information to simplify Op, create a new simplified DAG node and 1126/// return true, returning the original and new nodes in Old and New. Otherwise, 1127/// analyze the expression and return a mask of KnownOne and KnownZero bits for 1128/// the expression (used to simplify the caller). The KnownZero/One bits may 1129/// only be accurate for those bits in the DemandedMask. 1130bool TargetLowering::SimplifyDemandedBits(SDValue Op, 1131 const APInt &DemandedMask, 1132 APInt &KnownZero, 1133 APInt &KnownOne, 1134 TargetLoweringOpt &TLO, 1135 unsigned Depth) const { 1136 unsigned BitWidth = DemandedMask.getBitWidth(); 1137 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1138 "Mask size mismatches value type size!"); 1139 APInt NewMask = DemandedMask; 1140 DebugLoc dl = Op.getDebugLoc(); 1141 1142 // Don't know anything. 1143 KnownZero = KnownOne = APInt(BitWidth, 0); 1144 1145 // Other users may use these bits. 1146 if (!Op.getNode()->hasOneUse()) { 1147 if (Depth != 0) { 1148 // If not at the root, Just compute the KnownZero/KnownOne bits to 1149 // simplify things downstream. 1150 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 1151 return false; 1152 } 1153 // If this is the root being simplified, allow it to have multiple uses, 1154 // just set the NewMask to all bits. 1155 NewMask = APInt::getAllOnesValue(BitWidth); 1156 } else if (DemandedMask == 0) { 1157 // Not demanding any bits from Op. 1158 if (Op.getOpcode() != ISD::UNDEF) 1159 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1160 return false; 1161 } else if (Depth == 6) { // Limit search depth. 1162 return false; 1163 } 1164 1165 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1166 switch (Op.getOpcode()) { 1167 case ISD::Constant: 1168 // We know all of the bits for a constant! 1169 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 1170 KnownZero = ~KnownOne & NewMask; 1171 return false; // Don't fall through, will infinitely loop. 1172 case ISD::AND: 1173 // If the RHS is a constant, check to see if the LHS would be zero without 1174 // using the bits from the RHS. Below, we use knowledge about the RHS to 1175 // simplify the LHS, here we're using information from the LHS to simplify 1176 // the RHS. 1177 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1178 APInt LHSZero, LHSOne; 1179 // Do not increment Depth here; that can cause an infinite loop. 1180 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1181 LHSZero, LHSOne, Depth); 1182 // If the LHS already has zeros where RHSC does, this and is dead. 1183 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1184 return TLO.CombineTo(Op, Op.getOperand(0)); 1185 // If any of the set bits in the RHS are known zero on the LHS, shrink 1186 // the constant. 1187 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1188 return true; 1189 } 1190 1191 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1192 KnownOne, TLO, Depth+1)) 1193 return true; 1194 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1195 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1196 KnownZero2, KnownOne2, TLO, Depth+1)) 1197 return true; 1198 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1199 1200 // If all of the demanded bits are known one on one side, return the other. 1201 // These bits cannot contribute to the result of the 'and'. 1202 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1203 return TLO.CombineTo(Op, Op.getOperand(0)); 1204 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1205 return TLO.CombineTo(Op, Op.getOperand(1)); 1206 // If all of the demanded bits in the inputs are known zeros, return zero. 1207 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1208 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1209 // If the RHS is a constant, see if we can simplify it. 1210 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1211 return true; 1212 // If the operation can be done in a smaller type, do so. 1213 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1214 return true; 1215 1216 // Output known-1 bits are only known if set in both the LHS & RHS. 1217 KnownOne &= KnownOne2; 1218 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1219 KnownZero |= KnownZero2; 1220 break; 1221 case ISD::OR: 1222 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1223 KnownOne, TLO, Depth+1)) 1224 return true; 1225 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1226 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1227 KnownZero2, KnownOne2, TLO, Depth+1)) 1228 return true; 1229 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1230 1231 // If all of the demanded bits are known zero on one side, return the other. 1232 // These bits cannot contribute to the result of the 'or'. 1233 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1234 return TLO.CombineTo(Op, Op.getOperand(0)); 1235 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1236 return TLO.CombineTo(Op, Op.getOperand(1)); 1237 // If all of the potentially set bits on one side are known to be set on 1238 // the other side, just use the 'other' side. 1239 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1240 return TLO.CombineTo(Op, Op.getOperand(0)); 1241 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1242 return TLO.CombineTo(Op, Op.getOperand(1)); 1243 // If the RHS is a constant, see if we can simplify it. 1244 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1245 return true; 1246 // If the operation can be done in a smaller type, do so. 1247 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1248 return true; 1249 1250 // Output known-0 bits are only known if clear in both the LHS & RHS. 1251 KnownZero &= KnownZero2; 1252 // Output known-1 are known to be set if set in either the LHS | RHS. 1253 KnownOne |= KnownOne2; 1254 break; 1255 case ISD::XOR: 1256 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1257 KnownOne, TLO, Depth+1)) 1258 return true; 1259 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1260 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1261 KnownOne2, TLO, Depth+1)) 1262 return true; 1263 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1264 1265 // If all of the demanded bits are known zero on one side, return the other. 1266 // These bits cannot contribute to the result of the 'xor'. 1267 if ((KnownZero & NewMask) == NewMask) 1268 return TLO.CombineTo(Op, Op.getOperand(0)); 1269 if ((KnownZero2 & NewMask) == NewMask) 1270 return TLO.CombineTo(Op, Op.getOperand(1)); 1271 // If the operation can be done in a smaller type, do so. 1272 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1273 return true; 1274 1275 // If all of the unknown bits are known to be zero on one side or the other 1276 // (but not both) turn this into an *inclusive* or. 1277 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1278 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1279 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1280 Op.getOperand(0), 1281 Op.getOperand(1))); 1282 1283 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1284 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1285 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1286 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1287 1288 // If all of the demanded bits on one side are known, and all of the set 1289 // bits on that side are also known to be set on the other side, turn this 1290 // into an AND, as we know the bits will be cleared. 1291 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1292 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1293 if ((KnownOne & KnownOne2) == KnownOne) { 1294 EVT VT = Op.getValueType(); 1295 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1296 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1297 Op.getOperand(0), ANDC)); 1298 } 1299 } 1300 1301 // If the RHS is a constant, see if we can simplify it. 1302 // for XOR, we prefer to force bits to 1 if they will make a -1. 1303 // if we can't force bits, try to shrink constant 1304 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1305 APInt Expanded = C->getAPIntValue() | (~NewMask); 1306 // if we can expand it to have all bits set, do it 1307 if (Expanded.isAllOnesValue()) { 1308 if (Expanded != C->getAPIntValue()) { 1309 EVT VT = Op.getValueType(); 1310 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1311 TLO.DAG.getConstant(Expanded, VT)); 1312 return TLO.CombineTo(Op, New); 1313 } 1314 // if it already has all the bits set, nothing to change 1315 // but don't shrink either! 1316 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1317 return true; 1318 } 1319 } 1320 1321 KnownZero = KnownZeroOut; 1322 KnownOne = KnownOneOut; 1323 break; 1324 case ISD::SELECT: 1325 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1326 KnownOne, TLO, Depth+1)) 1327 return true; 1328 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1329 KnownOne2, TLO, Depth+1)) 1330 return true; 1331 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1332 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1333 1334 // If the operands are constants, see if we can simplify them. 1335 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1336 return true; 1337 1338 // Only known if known in both the LHS and RHS. 1339 KnownOne &= KnownOne2; 1340 KnownZero &= KnownZero2; 1341 break; 1342 case ISD::SELECT_CC: 1343 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1344 KnownOne, TLO, Depth+1)) 1345 return true; 1346 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1347 KnownOne2, TLO, Depth+1)) 1348 return true; 1349 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1350 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1351 1352 // If the operands are constants, see if we can simplify them. 1353 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1354 return true; 1355 1356 // Only known if known in both the LHS and RHS. 1357 KnownOne &= KnownOne2; 1358 KnownZero &= KnownZero2; 1359 break; 1360 case ISD::SHL: 1361 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1362 unsigned ShAmt = SA->getZExtValue(); 1363 SDValue InOp = Op.getOperand(0); 1364 1365 // If the shift count is an invalid immediate, don't do anything. 1366 if (ShAmt >= BitWidth) 1367 break; 1368 1369 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1370 // single shift. We can do this if the bottom bits (which are shifted 1371 // out) are never demanded. 1372 if (InOp.getOpcode() == ISD::SRL && 1373 isa<ConstantSDNode>(InOp.getOperand(1))) { 1374 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1375 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1376 unsigned Opc = ISD::SHL; 1377 int Diff = ShAmt-C1; 1378 if (Diff < 0) { 1379 Diff = -Diff; 1380 Opc = ISD::SRL; 1381 } 1382 1383 SDValue NewSA = 1384 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1385 EVT VT = Op.getValueType(); 1386 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1387 InOp.getOperand(0), NewSA)); 1388 } 1389 } 1390 1391 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 1392 KnownZero, KnownOne, TLO, Depth+1)) 1393 return true; 1394 1395 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 1396 // are not demanded. This will likely allow the anyext to be folded away. 1397 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 1398 SDValue InnerOp = InOp.getNode()->getOperand(0); 1399 EVT InnerVT = InnerOp.getValueType(); 1400 if ((APInt::getHighBitsSet(BitWidth, 1401 BitWidth - InnerVT.getSizeInBits()) & 1402 DemandedMask) == 0 && 1403 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 1404 EVT ShTy = getShiftAmountTy(); 1405 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 1406 ShTy = InnerVT; 1407 SDValue NarrowShl = 1408 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 1409 TLO.DAG.getConstant(ShAmt, ShTy)); 1410 return 1411 TLO.CombineTo(Op, 1412 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 1413 NarrowShl)); 1414 } 1415 } 1416 1417 KnownZero <<= SA->getZExtValue(); 1418 KnownOne <<= SA->getZExtValue(); 1419 // low bits known zero. 1420 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1421 } 1422 break; 1423 case ISD::SRL: 1424 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1425 EVT VT = Op.getValueType(); 1426 unsigned ShAmt = SA->getZExtValue(); 1427 unsigned VTSize = VT.getSizeInBits(); 1428 SDValue InOp = Op.getOperand(0); 1429 1430 // If the shift count is an invalid immediate, don't do anything. 1431 if (ShAmt >= BitWidth) 1432 break; 1433 1434 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1435 // single shift. We can do this if the top bits (which are shifted out) 1436 // are never demanded. 1437 if (InOp.getOpcode() == ISD::SHL && 1438 isa<ConstantSDNode>(InOp.getOperand(1))) { 1439 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1440 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1441 unsigned Opc = ISD::SRL; 1442 int Diff = ShAmt-C1; 1443 if (Diff < 0) { 1444 Diff = -Diff; 1445 Opc = ISD::SHL; 1446 } 1447 1448 SDValue NewSA = 1449 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1450 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1451 InOp.getOperand(0), NewSA)); 1452 } 1453 } 1454 1455 // Compute the new bits that are at the top now. 1456 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1457 KnownZero, KnownOne, TLO, Depth+1)) 1458 return true; 1459 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1460 KnownZero = KnownZero.lshr(ShAmt); 1461 KnownOne = KnownOne.lshr(ShAmt); 1462 1463 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1464 KnownZero |= HighBits; // High bits known zero. 1465 } 1466 break; 1467 case ISD::SRA: 1468 // If this is an arithmetic shift right and only the low-bit is set, we can 1469 // always convert this into a logical shr, even if the shift amount is 1470 // variable. The low bit of the shift cannot be an input sign bit unless 1471 // the shift amount is >= the size of the datatype, which is undefined. 1472 if (DemandedMask == 1) 1473 return TLO.CombineTo(Op, 1474 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1475 Op.getOperand(0), Op.getOperand(1))); 1476 1477 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1478 EVT VT = Op.getValueType(); 1479 unsigned ShAmt = SA->getZExtValue(); 1480 1481 // If the shift count is an invalid immediate, don't do anything. 1482 if (ShAmt >= BitWidth) 1483 break; 1484 1485 APInt InDemandedMask = (NewMask << ShAmt); 1486 1487 // If any of the demanded bits are produced by the sign extension, we also 1488 // demand the input sign bit. 1489 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1490 if (HighBits.intersects(NewMask)) 1491 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1492 1493 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1494 KnownZero, KnownOne, TLO, Depth+1)) 1495 return true; 1496 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1497 KnownZero = KnownZero.lshr(ShAmt); 1498 KnownOne = KnownOne.lshr(ShAmt); 1499 1500 // Handle the sign bit, adjusted to where it is now in the mask. 1501 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1502 1503 // If the input sign bit is known to be zero, or if none of the top bits 1504 // are demanded, turn this into an unsigned shift right. 1505 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1506 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1507 Op.getOperand(0), 1508 Op.getOperand(1))); 1509 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1510 KnownOne |= HighBits; 1511 } 1512 } 1513 break; 1514 case ISD::SIGN_EXTEND_INREG: { 1515 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1516 1517 // Sign extension. Compute the demanded bits in the result that are not 1518 // present in the input. 1519 APInt NewBits = 1520 APInt::getHighBitsSet(BitWidth, 1521 BitWidth - EVT.getScalarType().getSizeInBits()); 1522 1523 // If none of the extended bits are demanded, eliminate the sextinreg. 1524 if ((NewBits & NewMask) == 0) 1525 return TLO.CombineTo(Op, Op.getOperand(0)); 1526 1527 APInt InSignBit = 1528 APInt::getSignBit(EVT.getScalarType().getSizeInBits()).zext(BitWidth); 1529 APInt InputDemandedBits = 1530 APInt::getLowBitsSet(BitWidth, 1531 EVT.getScalarType().getSizeInBits()) & 1532 NewMask; 1533 1534 // Since the sign extended bits are demanded, we know that the sign 1535 // bit is demanded. 1536 InputDemandedBits |= InSignBit; 1537 1538 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1539 KnownZero, KnownOne, TLO, Depth+1)) 1540 return true; 1541 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1542 1543 // If the sign bit of the input is known set or clear, then we know the 1544 // top bits of the result. 1545 1546 // If the input sign bit is known zero, convert this into a zero extension. 1547 if (KnownZero.intersects(InSignBit)) 1548 return TLO.CombineTo(Op, 1549 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1550 1551 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1552 KnownOne |= NewBits; 1553 KnownZero &= ~NewBits; 1554 } else { // Input sign bit unknown 1555 KnownZero &= ~NewBits; 1556 KnownOne &= ~NewBits; 1557 } 1558 break; 1559 } 1560 case ISD::ZERO_EXTEND: { 1561 unsigned OperandBitWidth = 1562 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1563 APInt InMask = NewMask.trunc(OperandBitWidth); 1564 1565 // If none of the top bits are demanded, convert this into an any_extend. 1566 APInt NewBits = 1567 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1568 if (!NewBits.intersects(NewMask)) 1569 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1570 Op.getValueType(), 1571 Op.getOperand(0))); 1572 1573 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1574 KnownZero, KnownOne, TLO, Depth+1)) 1575 return true; 1576 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1577 KnownZero = KnownZero.zext(BitWidth); 1578 KnownOne = KnownOne.zext(BitWidth); 1579 KnownZero |= NewBits; 1580 break; 1581 } 1582 case ISD::SIGN_EXTEND: { 1583 EVT InVT = Op.getOperand(0).getValueType(); 1584 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1585 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1586 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1587 APInt NewBits = ~InMask & NewMask; 1588 1589 // If none of the top bits are demanded, convert this into an any_extend. 1590 if (NewBits == 0) 1591 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1592 Op.getValueType(), 1593 Op.getOperand(0))); 1594 1595 // Since some of the sign extended bits are demanded, we know that the sign 1596 // bit is demanded. 1597 APInt InDemandedBits = InMask & NewMask; 1598 InDemandedBits |= InSignBit; 1599 InDemandedBits = InDemandedBits.trunc(InBits); 1600 1601 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1602 KnownOne, TLO, Depth+1)) 1603 return true; 1604 KnownZero = KnownZero.zext(BitWidth); 1605 KnownOne = KnownOne.zext(BitWidth); 1606 1607 // If the sign bit is known zero, convert this to a zero extend. 1608 if (KnownZero.intersects(InSignBit)) 1609 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1610 Op.getValueType(), 1611 Op.getOperand(0))); 1612 1613 // If the sign bit is known one, the top bits match. 1614 if (KnownOne.intersects(InSignBit)) { 1615 KnownOne |= NewBits; 1616 KnownZero &= ~NewBits; 1617 } else { // Otherwise, top bits aren't known. 1618 KnownOne &= ~NewBits; 1619 KnownZero &= ~NewBits; 1620 } 1621 break; 1622 } 1623 case ISD::ANY_EXTEND: { 1624 unsigned OperandBitWidth = 1625 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1626 APInt InMask = NewMask.trunc(OperandBitWidth); 1627 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1628 KnownZero, KnownOne, TLO, Depth+1)) 1629 return true; 1630 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1631 KnownZero = KnownZero.zext(BitWidth); 1632 KnownOne = KnownOne.zext(BitWidth); 1633 break; 1634 } 1635 case ISD::TRUNCATE: { 1636 // Simplify the input, using demanded bit information, and compute the known 1637 // zero/one bits live out. 1638 unsigned OperandBitWidth = 1639 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1640 APInt TruncMask = NewMask.zext(OperandBitWidth); 1641 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1642 KnownZero, KnownOne, TLO, Depth+1)) 1643 return true; 1644 KnownZero = KnownZero.trunc(BitWidth); 1645 KnownOne = KnownOne.trunc(BitWidth); 1646 1647 // If the input is only used by this truncate, see if we can shrink it based 1648 // on the known demanded bits. 1649 if (Op.getOperand(0).getNode()->hasOneUse()) { 1650 SDValue In = Op.getOperand(0); 1651 switch (In.getOpcode()) { 1652 default: break; 1653 case ISD::SRL: 1654 // Shrink SRL by a constant if none of the high bits shifted in are 1655 // demanded. 1656 if (TLO.LegalTypes() && 1657 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1658 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1659 // undesirable. 1660 break; 1661 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1662 if (!ShAmt) 1663 break; 1664 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1665 OperandBitWidth - BitWidth); 1666 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 1667 1668 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1669 // None of the shifted in bits are needed. Add a truncate of the 1670 // shift input, then shift it. 1671 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1672 Op.getValueType(), 1673 In.getOperand(0)); 1674 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1675 Op.getValueType(), 1676 NewTrunc, 1677 In.getOperand(1))); 1678 } 1679 break; 1680 } 1681 } 1682 1683 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1684 break; 1685 } 1686 case ISD::AssertZext: { 1687 // Demand all the bits of the input that are demanded in the output. 1688 // The low bits are obvious; the high bits are demanded because we're 1689 // asserting that they're zero here. 1690 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, 1691 KnownZero, KnownOne, TLO, Depth+1)) 1692 return true; 1693 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1694 1695 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1696 APInt InMask = APInt::getLowBitsSet(BitWidth, 1697 VT.getSizeInBits()); 1698 KnownZero |= ~InMask & NewMask; 1699 break; 1700 } 1701 case ISD::BITCAST: 1702#if 0 1703 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1704 // is demanded, turn this into a FGETSIGN. 1705 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) && 1706 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1707 !MVT::isVector(Op.getOperand(0).getValueType())) { 1708 // Only do this xform if FGETSIGN is valid or if before legalize. 1709 if (!TLO.AfterLegalize || 1710 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1711 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1712 // place. We expect the SHL to be eliminated by other optimizations. 1713 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1714 Op.getOperand(0)); 1715 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1716 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1717 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1718 Sign, ShAmt)); 1719 } 1720 } 1721#endif 1722 break; 1723 case ISD::ADD: 1724 case ISD::MUL: 1725 case ISD::SUB: { 1726 // Add, Sub, and Mul don't demand any bits in positions beyond that 1727 // of the highest bit demanded of them. 1728 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1729 BitWidth - NewMask.countLeadingZeros()); 1730 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1731 KnownOne2, TLO, Depth+1)) 1732 return true; 1733 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1734 KnownOne2, TLO, Depth+1)) 1735 return true; 1736 // See if the operation should be performed at a smaller bit width. 1737 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1738 return true; 1739 } 1740 // FALL THROUGH 1741 default: 1742 // Just use ComputeMaskedBits to compute output bits. 1743 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1744 break; 1745 } 1746 1747 // If we know the value of all of the demanded bits, return this as a 1748 // constant. 1749 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1750 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1751 1752 return false; 1753} 1754 1755/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1756/// in Mask are known to be either zero or one and return them in the 1757/// KnownZero/KnownOne bitsets. 1758void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1759 const APInt &Mask, 1760 APInt &KnownZero, 1761 APInt &KnownOne, 1762 const SelectionDAG &DAG, 1763 unsigned Depth) const { 1764 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1765 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1766 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1767 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1768 "Should use MaskedValueIsZero if you don't know whether Op" 1769 " is a target node!"); 1770 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1771} 1772 1773/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1774/// targets that want to expose additional information about sign bits to the 1775/// DAG Combiner. 1776unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1777 unsigned Depth) const { 1778 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1779 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1780 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1781 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1782 "Should use ComputeNumSignBits if you don't know whether Op" 1783 " is a target node!"); 1784 return 1; 1785} 1786 1787/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1788/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1789/// determine which bit is set. 1790/// 1791static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1792 // A left-shift of a constant one will have exactly one bit set, because 1793 // shifting the bit off the end is undefined. 1794 if (Val.getOpcode() == ISD::SHL) 1795 if (ConstantSDNode *C = 1796 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1797 if (C->getAPIntValue() == 1) 1798 return true; 1799 1800 // Similarly, a right-shift of a constant sign-bit will have exactly 1801 // one bit set. 1802 if (Val.getOpcode() == ISD::SRL) 1803 if (ConstantSDNode *C = 1804 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1805 if (C->getAPIntValue().isSignBit()) 1806 return true; 1807 1808 // More could be done here, though the above checks are enough 1809 // to handle some common cases. 1810 1811 // Fall back to ComputeMaskedBits to catch other known cases. 1812 EVT OpVT = Val.getValueType(); 1813 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1814 APInt Mask = APInt::getAllOnesValue(BitWidth); 1815 APInt KnownZero, KnownOne; 1816 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1817 return (KnownZero.countPopulation() == BitWidth - 1) && 1818 (KnownOne.countPopulation() == 1); 1819} 1820 1821/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1822/// and cc. If it is unable to simplify it, return a null SDValue. 1823SDValue 1824TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1825 ISD::CondCode Cond, bool foldBooleans, 1826 DAGCombinerInfo &DCI, DebugLoc dl) const { 1827 SelectionDAG &DAG = DCI.DAG; 1828 LLVMContext &Context = *DAG.getContext(); 1829 1830 // These setcc operations always fold. 1831 switch (Cond) { 1832 default: break; 1833 case ISD::SETFALSE: 1834 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1835 case ISD::SETTRUE: 1836 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1837 } 1838 1839 if (isa<ConstantSDNode>(N0.getNode())) { 1840 // Ensure that the constant occurs on the RHS, and fold constant 1841 // comparisons. 1842 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1843 } 1844 1845 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1846 const APInt &C1 = N1C->getAPIntValue(); 1847 1848 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1849 // equality comparison, then we're just comparing whether X itself is 1850 // zero. 1851 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1852 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1853 N0.getOperand(1).getOpcode() == ISD::Constant) { 1854 const APInt &ShAmt 1855 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1856 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1857 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1858 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1859 // (srl (ctlz x), 5) == 0 -> X != 0 1860 // (srl (ctlz x), 5) != 1 -> X != 0 1861 Cond = ISD::SETNE; 1862 } else { 1863 // (srl (ctlz x), 5) != 0 -> X == 0 1864 // (srl (ctlz x), 5) == 1 -> X == 0 1865 Cond = ISD::SETEQ; 1866 } 1867 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1868 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1869 Zero, Cond); 1870 } 1871 } 1872 1873 SDValue CTPOP = N0; 1874 // Look through truncs that don't change the value of a ctpop. 1875 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) 1876 CTPOP = N0.getOperand(0); 1877 1878 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && 1879 (N0 == CTPOP || N0.getValueType().getSizeInBits() > 1880 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { 1881 EVT CTVT = CTPOP.getValueType(); 1882 SDValue CTOp = CTPOP.getOperand(0); 1883 1884 // (ctpop x) u< 2 -> (x & x-1) == 0 1885 // (ctpop x) u> 1 -> (x & x-1) != 0 1886 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 1887 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 1888 DAG.getConstant(1, CTVT)); 1889 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); 1890 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1891 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC); 1892 } 1893 1894 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal. 1895 } 1896 1897 // If the LHS is '(and load, const)', the RHS is 0, 1898 // the test is for equality or unsigned, and all 1 bits of the const are 1899 // in the same partial word, see if we can shorten the load. 1900 if (DCI.isBeforeLegalize() && 1901 N0.getOpcode() == ISD::AND && C1 == 0 && 1902 N0.getNode()->hasOneUse() && 1903 isa<LoadSDNode>(N0.getOperand(0)) && 1904 N0.getOperand(0).getNode()->hasOneUse() && 1905 isa<ConstantSDNode>(N0.getOperand(1))) { 1906 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1907 APInt bestMask; 1908 unsigned bestWidth = 0, bestOffset = 0; 1909 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1910 unsigned origWidth = N0.getValueType().getSizeInBits(); 1911 unsigned maskWidth = origWidth; 1912 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1913 // 8 bits, but have to be careful... 1914 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1915 origWidth = Lod->getMemoryVT().getSizeInBits(); 1916 const APInt &Mask = 1917 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1918 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1919 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1920 for (unsigned offset=0; offset<origWidth/width; offset++) { 1921 if ((newMask & Mask) == Mask) { 1922 if (!TD->isLittleEndian()) 1923 bestOffset = (origWidth/width - offset - 1) * (width/8); 1924 else 1925 bestOffset = (uint64_t)offset * (width/8); 1926 bestMask = Mask.lshr(offset * (width/8) * 8); 1927 bestWidth = width; 1928 break; 1929 } 1930 newMask = newMask << width; 1931 } 1932 } 1933 } 1934 if (bestWidth) { 1935 EVT newVT = EVT::getIntegerVT(Context, bestWidth); 1936 if (newVT.isRound()) { 1937 EVT PtrType = Lod->getOperand(1).getValueType(); 1938 SDValue Ptr = Lod->getBasePtr(); 1939 if (bestOffset != 0) 1940 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1941 DAG.getConstant(bestOffset, PtrType)); 1942 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1943 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1944 Lod->getPointerInfo().getWithOffset(bestOffset), 1945 false, false, NewAlign); 1946 return DAG.getSetCC(dl, VT, 1947 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1948 DAG.getConstant(bestMask.trunc(bestWidth), 1949 newVT)), 1950 DAG.getConstant(0LL, newVT), Cond); 1951 } 1952 } 1953 } 1954 1955 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1956 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1957 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1958 1959 // If the comparison constant has bits in the upper part, the 1960 // zero-extended value could never match. 1961 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1962 C1.getBitWidth() - InSize))) { 1963 switch (Cond) { 1964 case ISD::SETUGT: 1965 case ISD::SETUGE: 1966 case ISD::SETEQ: return DAG.getConstant(0, VT); 1967 case ISD::SETULT: 1968 case ISD::SETULE: 1969 case ISD::SETNE: return DAG.getConstant(1, VT); 1970 case ISD::SETGT: 1971 case ISD::SETGE: 1972 // True if the sign bit of C1 is set. 1973 return DAG.getConstant(C1.isNegative(), VT); 1974 case ISD::SETLT: 1975 case ISD::SETLE: 1976 // True if the sign bit of C1 isn't set. 1977 return DAG.getConstant(C1.isNonNegative(), VT); 1978 default: 1979 break; 1980 } 1981 } 1982 1983 // Otherwise, we can perform the comparison with the low bits. 1984 switch (Cond) { 1985 case ISD::SETEQ: 1986 case ISD::SETNE: 1987 case ISD::SETUGT: 1988 case ISD::SETUGE: 1989 case ISD::SETULT: 1990 case ISD::SETULE: { 1991 EVT newVT = N0.getOperand(0).getValueType(); 1992 if (DCI.isBeforeLegalizeOps() || 1993 (isOperationLegal(ISD::SETCC, newVT) && 1994 getCondCodeAction(Cond, newVT)==Legal)) 1995 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1996 DAG.getConstant(C1.trunc(InSize), newVT), 1997 Cond); 1998 break; 1999 } 2000 default: 2001 break; // todo, be more careful with signed comparisons 2002 } 2003 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2004 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2005 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2006 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 2007 EVT ExtDstTy = N0.getValueType(); 2008 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 2009 2010 // If the constant doesn't fit into the number of bits for the source of 2011 // the sign extension, it is impossible for both sides to be equal. 2012 if (C1.getMinSignedBits() > ExtSrcTyBits) 2013 return DAG.getConstant(Cond == ISD::SETNE, VT); 2014 2015 SDValue ZextOp; 2016 EVT Op0Ty = N0.getOperand(0).getValueType(); 2017 if (Op0Ty == ExtSrcTy) { 2018 ZextOp = N0.getOperand(0); 2019 } else { 2020 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 2021 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 2022 DAG.getConstant(Imm, Op0Ty)); 2023 } 2024 if (!DCI.isCalledByLegalizer()) 2025 DCI.AddToWorklist(ZextOp.getNode()); 2026 // Otherwise, make this a use of a zext. 2027 return DAG.getSetCC(dl, VT, ZextOp, 2028 DAG.getConstant(C1 & APInt::getLowBitsSet( 2029 ExtDstTyBits, 2030 ExtSrcTyBits), 2031 ExtDstTy), 2032 Cond); 2033 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 2034 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2035 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 2036 if (N0.getOpcode() == ISD::SETCC && 2037 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 2038 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 2039 if (TrueWhenTrue) 2040 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 2041 // Invert the condition. 2042 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 2043 CC = ISD::getSetCCInverse(CC, 2044 N0.getOperand(0).getValueType().isInteger()); 2045 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 2046 } 2047 2048 if ((N0.getOpcode() == ISD::XOR || 2049 (N0.getOpcode() == ISD::AND && 2050 N0.getOperand(0).getOpcode() == ISD::XOR && 2051 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2052 isa<ConstantSDNode>(N0.getOperand(1)) && 2053 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 2054 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 2055 // can only do this if the top bits are known zero. 2056 unsigned BitWidth = N0.getValueSizeInBits(); 2057 if (DAG.MaskedValueIsZero(N0, 2058 APInt::getHighBitsSet(BitWidth, 2059 BitWidth-1))) { 2060 // Okay, get the un-inverted input value. 2061 SDValue Val; 2062 if (N0.getOpcode() == ISD::XOR) 2063 Val = N0.getOperand(0); 2064 else { 2065 assert(N0.getOpcode() == ISD::AND && 2066 N0.getOperand(0).getOpcode() == ISD::XOR); 2067 // ((X^1)&1)^1 -> X & 1 2068 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 2069 N0.getOperand(0).getOperand(0), 2070 N0.getOperand(1)); 2071 } 2072 2073 return DAG.getSetCC(dl, VT, Val, N1, 2074 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2075 } 2076 } else if (N1C->getAPIntValue() == 1 && 2077 (VT == MVT::i1 || 2078 getBooleanContents() == ZeroOrOneBooleanContent)) { 2079 SDValue Op0 = N0; 2080 if (Op0.getOpcode() == ISD::TRUNCATE) 2081 Op0 = Op0.getOperand(0); 2082 2083 if ((Op0.getOpcode() == ISD::XOR) && 2084 Op0.getOperand(0).getOpcode() == ISD::SETCC && 2085 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 2086 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 2087 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 2088 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 2089 Cond); 2090 } else if (Op0.getOpcode() == ISD::AND && 2091 isa<ConstantSDNode>(Op0.getOperand(1)) && 2092 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 2093 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 2094 if (Op0.getValueType().bitsGT(VT)) 2095 Op0 = DAG.getNode(ISD::AND, dl, VT, 2096 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 2097 DAG.getConstant(1, VT)); 2098 else if (Op0.getValueType().bitsLT(VT)) 2099 Op0 = DAG.getNode(ISD::AND, dl, VT, 2100 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 2101 DAG.getConstant(1, VT)); 2102 2103 return DAG.getSetCC(dl, VT, Op0, 2104 DAG.getConstant(0, Op0.getValueType()), 2105 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2106 } 2107 } 2108 } 2109 2110 APInt MinVal, MaxVal; 2111 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 2112 if (ISD::isSignedIntSetCC(Cond)) { 2113 MinVal = APInt::getSignedMinValue(OperandBitSize); 2114 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 2115 } else { 2116 MinVal = APInt::getMinValue(OperandBitSize); 2117 MaxVal = APInt::getMaxValue(OperandBitSize); 2118 } 2119 2120 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2121 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2122 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2123 // X >= C0 --> X > (C0-1) 2124 return DAG.getSetCC(dl, VT, N0, 2125 DAG.getConstant(C1-1, N1.getValueType()), 2126 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2127 } 2128 2129 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2130 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2131 // X <= C0 --> X < (C0+1) 2132 return DAG.getSetCC(dl, VT, N0, 2133 DAG.getConstant(C1+1, N1.getValueType()), 2134 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2135 } 2136 2137 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2138 return DAG.getConstant(0, VT); // X < MIN --> false 2139 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 2140 return DAG.getConstant(1, VT); // X >= MIN --> true 2141 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 2142 return DAG.getConstant(0, VT); // X > MAX --> false 2143 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 2144 return DAG.getConstant(1, VT); // X <= MAX --> true 2145 2146 // Canonicalize setgt X, Min --> setne X, Min 2147 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2148 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2149 // Canonicalize setlt X, Max --> setne X, Max 2150 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2151 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2152 2153 // If we have setult X, 1, turn it into seteq X, 0 2154 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2155 return DAG.getSetCC(dl, VT, N0, 2156 DAG.getConstant(MinVal, N0.getValueType()), 2157 ISD::SETEQ); 2158 // If we have setugt X, Max-1, turn it into seteq X, Max 2159 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2160 return DAG.getSetCC(dl, VT, N0, 2161 DAG.getConstant(MaxVal, N0.getValueType()), 2162 ISD::SETEQ); 2163 2164 // If we have "setcc X, C0", check to see if we can shrink the immediate 2165 // by changing cc. 2166 2167 // SETUGT X, SINTMAX -> SETLT X, 0 2168 if (Cond == ISD::SETUGT && 2169 C1 == APInt::getSignedMaxValue(OperandBitSize)) 2170 return DAG.getSetCC(dl, VT, N0, 2171 DAG.getConstant(0, N1.getValueType()), 2172 ISD::SETLT); 2173 2174 // SETULT X, SINTMIN -> SETGT X, -1 2175 if (Cond == ISD::SETULT && 2176 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2177 SDValue ConstMinusOne = 2178 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2179 N1.getValueType()); 2180 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2181 } 2182 2183 // Fold bit comparisons when we can. 2184 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2185 (VT == N0.getValueType() || 2186 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2187 N0.getOpcode() == ISD::AND) 2188 if (ConstantSDNode *AndRHS = 2189 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2190 EVT ShiftTy = DCI.isBeforeLegalize() ? 2191 getPointerTy() : getShiftAmountTy(); 2192 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2193 // Perform the xform if the AND RHS is a single bit. 2194 if (AndRHS->getAPIntValue().isPowerOf2()) { 2195 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2196 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2197 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2198 } 2199 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2200 // (X & 8) == 8 --> (X & 8) >> 3 2201 // Perform the xform if C1 is a single bit. 2202 if (C1.isPowerOf2()) { 2203 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2204 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2205 DAG.getConstant(C1.logBase2(), ShiftTy))); 2206 } 2207 } 2208 } 2209 } 2210 2211 if (isa<ConstantFPSDNode>(N0.getNode())) { 2212 // Constant fold or commute setcc. 2213 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2214 if (O.getNode()) return O; 2215 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2216 // If the RHS of an FP comparison is a constant, simplify it away in 2217 // some cases. 2218 if (CFP->getValueAPF().isNaN()) { 2219 // If an operand is known to be a nan, we can fold it. 2220 switch (ISD::getUnorderedFlavor(Cond)) { 2221 default: llvm_unreachable("Unknown flavor!"); 2222 case 0: // Known false. 2223 return DAG.getConstant(0, VT); 2224 case 1: // Known true. 2225 return DAG.getConstant(1, VT); 2226 case 2: // Undefined. 2227 return DAG.getUNDEF(VT); 2228 } 2229 } 2230 2231 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2232 // constant if knowing that the operand is non-nan is enough. We prefer to 2233 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2234 // materialize 0.0. 2235 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2236 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2237 2238 // If the condition is not legal, see if we can find an equivalent one 2239 // which is legal. 2240 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2241 // If the comparison was an awkward floating-point == or != and one of 2242 // the comparison operands is infinity or negative infinity, convert the 2243 // condition to a less-awkward <= or >=. 2244 if (CFP->getValueAPF().isInfinity()) { 2245 if (CFP->getValueAPF().isNegative()) { 2246 if (Cond == ISD::SETOEQ && 2247 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2248 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2249 if (Cond == ISD::SETUEQ && 2250 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2251 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2252 if (Cond == ISD::SETUNE && 2253 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2254 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2255 if (Cond == ISD::SETONE && 2256 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2257 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2258 } else { 2259 if (Cond == ISD::SETOEQ && 2260 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2261 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2262 if (Cond == ISD::SETUEQ && 2263 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2264 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2265 if (Cond == ISD::SETUNE && 2266 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2267 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2268 if (Cond == ISD::SETONE && 2269 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2270 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2271 } 2272 } 2273 } 2274 } 2275 2276 if (N0 == N1) { 2277 // We can always fold X == X for integer setcc's. 2278 if (N0.getValueType().isInteger()) 2279 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2280 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2281 if (UOF == 2) // FP operators that are undefined on NaNs. 2282 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2283 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2284 return DAG.getConstant(UOF, VT); 2285 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2286 // if it is not already. 2287 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2288 if (NewCond != Cond) 2289 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2290 } 2291 2292 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2293 N0.getValueType().isInteger()) { 2294 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2295 N0.getOpcode() == ISD::XOR) { 2296 // Simplify (X+Y) == (X+Z) --> Y == Z 2297 if (N0.getOpcode() == N1.getOpcode()) { 2298 if (N0.getOperand(0) == N1.getOperand(0)) 2299 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2300 if (N0.getOperand(1) == N1.getOperand(1)) 2301 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2302 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2303 // If X op Y == Y op X, try other combinations. 2304 if (N0.getOperand(0) == N1.getOperand(1)) 2305 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2306 Cond); 2307 if (N0.getOperand(1) == N1.getOperand(0)) 2308 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2309 Cond); 2310 } 2311 } 2312 2313 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2314 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2315 // Turn (X+C1) == C2 --> X == C2-C1 2316 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2317 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2318 DAG.getConstant(RHSC->getAPIntValue()- 2319 LHSR->getAPIntValue(), 2320 N0.getValueType()), Cond); 2321 } 2322 2323 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2324 if (N0.getOpcode() == ISD::XOR) 2325 // If we know that all of the inverted bits are zero, don't bother 2326 // performing the inversion. 2327 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2328 return 2329 DAG.getSetCC(dl, VT, N0.getOperand(0), 2330 DAG.getConstant(LHSR->getAPIntValue() ^ 2331 RHSC->getAPIntValue(), 2332 N0.getValueType()), 2333 Cond); 2334 } 2335 2336 // Turn (C1-X) == C2 --> X == C1-C2 2337 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2338 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2339 return 2340 DAG.getSetCC(dl, VT, N0.getOperand(1), 2341 DAG.getConstant(SUBC->getAPIntValue() - 2342 RHSC->getAPIntValue(), 2343 N0.getValueType()), 2344 Cond); 2345 } 2346 } 2347 } 2348 2349 // Simplify (X+Z) == X --> Z == 0 2350 if (N0.getOperand(0) == N1) 2351 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2352 DAG.getConstant(0, N0.getValueType()), Cond); 2353 if (N0.getOperand(1) == N1) { 2354 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2355 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2356 DAG.getConstant(0, N0.getValueType()), Cond); 2357 else if (N0.getNode()->hasOneUse()) { 2358 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2359 // (Z-X) == X --> Z == X<<1 2360 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2361 N1, 2362 DAG.getConstant(1, getShiftAmountTy())); 2363 if (!DCI.isCalledByLegalizer()) 2364 DCI.AddToWorklist(SH.getNode()); 2365 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2366 } 2367 } 2368 } 2369 2370 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2371 N1.getOpcode() == ISD::XOR) { 2372 // Simplify X == (X+Z) --> Z == 0 2373 if (N1.getOperand(0) == N0) { 2374 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2375 DAG.getConstant(0, N1.getValueType()), Cond); 2376 } else if (N1.getOperand(1) == N0) { 2377 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2378 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2379 DAG.getConstant(0, N1.getValueType()), Cond); 2380 } else if (N1.getNode()->hasOneUse()) { 2381 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2382 // X == (Z-X) --> X<<1 == Z 2383 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2384 DAG.getConstant(1, getShiftAmountTy())); 2385 if (!DCI.isCalledByLegalizer()) 2386 DCI.AddToWorklist(SH.getNode()); 2387 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2388 } 2389 } 2390 } 2391 2392 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2393 // Note that where y is variable and is known to have at most 2394 // one bit set (for example, if it is z&1) we cannot do this; 2395 // the expressions are not equivalent when y==0. 2396 if (N0.getOpcode() == ISD::AND) 2397 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2398 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2399 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2400 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2401 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2402 } 2403 } 2404 if (N1.getOpcode() == ISD::AND) 2405 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2406 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2407 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2408 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2409 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2410 } 2411 } 2412 } 2413 2414 // Fold away ALL boolean setcc's. 2415 SDValue Temp; 2416 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2417 switch (Cond) { 2418 default: llvm_unreachable("Unknown integer setcc!"); 2419 case ISD::SETEQ: // X == Y -> ~(X^Y) 2420 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2421 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2422 if (!DCI.isCalledByLegalizer()) 2423 DCI.AddToWorklist(Temp.getNode()); 2424 break; 2425 case ISD::SETNE: // X != Y --> (X^Y) 2426 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2427 break; 2428 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2429 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2430 Temp = DAG.getNOT(dl, N0, MVT::i1); 2431 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2432 if (!DCI.isCalledByLegalizer()) 2433 DCI.AddToWorklist(Temp.getNode()); 2434 break; 2435 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2436 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2437 Temp = DAG.getNOT(dl, N1, MVT::i1); 2438 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2439 if (!DCI.isCalledByLegalizer()) 2440 DCI.AddToWorklist(Temp.getNode()); 2441 break; 2442 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2443 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2444 Temp = DAG.getNOT(dl, N0, MVT::i1); 2445 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2446 if (!DCI.isCalledByLegalizer()) 2447 DCI.AddToWorklist(Temp.getNode()); 2448 break; 2449 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2450 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2451 Temp = DAG.getNOT(dl, N1, MVT::i1); 2452 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2453 break; 2454 } 2455 if (VT != MVT::i1) { 2456 if (!DCI.isCalledByLegalizer()) 2457 DCI.AddToWorklist(N0.getNode()); 2458 // FIXME: If running after legalize, we probably can't do this. 2459 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2460 } 2461 return N0; 2462 } 2463 2464 // Could not fold it. 2465 return SDValue(); 2466} 2467 2468/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2469/// node is a GlobalAddress + offset. 2470bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA, 2471 int64_t &Offset) const { 2472 if (isa<GlobalAddressSDNode>(N)) { 2473 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2474 GA = GASD->getGlobal(); 2475 Offset += GASD->getOffset(); 2476 return true; 2477 } 2478 2479 if (N->getOpcode() == ISD::ADD) { 2480 SDValue N1 = N->getOperand(0); 2481 SDValue N2 = N->getOperand(1); 2482 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2483 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2484 if (V) { 2485 Offset += V->getSExtValue(); 2486 return true; 2487 } 2488 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2489 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2490 if (V) { 2491 Offset += V->getSExtValue(); 2492 return true; 2493 } 2494 } 2495 } 2496 2497 return false; 2498} 2499 2500 2501SDValue TargetLowering:: 2502PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2503 // Default implementation: no optimization. 2504 return SDValue(); 2505} 2506 2507//===----------------------------------------------------------------------===// 2508// Inline Assembler Implementation Methods 2509//===----------------------------------------------------------------------===// 2510 2511 2512TargetLowering::ConstraintType 2513TargetLowering::getConstraintType(const std::string &Constraint) const { 2514 // FIXME: lots more standard ones to handle. 2515 if (Constraint.size() == 1) { 2516 switch (Constraint[0]) { 2517 default: break; 2518 case 'r': return C_RegisterClass; 2519 case 'm': // memory 2520 case 'o': // offsetable 2521 case 'V': // not offsetable 2522 return C_Memory; 2523 case 'i': // Simple Integer or Relocatable Constant 2524 case 'n': // Simple Integer 2525 case 'E': // Floating Point Constant 2526 case 'F': // Floating Point Constant 2527 case 's': // Relocatable Constant 2528 case 'p': // Address. 2529 case 'X': // Allow ANY value. 2530 case 'I': // Target registers. 2531 case 'J': 2532 case 'K': 2533 case 'L': 2534 case 'M': 2535 case 'N': 2536 case 'O': 2537 case 'P': 2538 case '<': 2539 case '>': 2540 return C_Other; 2541 } 2542 } 2543 2544 if (Constraint.size() > 1 && Constraint[0] == '{' && 2545 Constraint[Constraint.size()-1] == '}') 2546 return C_Register; 2547 return C_Unknown; 2548} 2549 2550/// LowerXConstraint - try to replace an X constraint, which matches anything, 2551/// with another that has more specific requirements based on the type of the 2552/// corresponding operand. 2553const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2554 if (ConstraintVT.isInteger()) 2555 return "r"; 2556 if (ConstraintVT.isFloatingPoint()) 2557 return "f"; // works for many targets 2558 return 0; 2559} 2560 2561/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2562/// vector. If it is invalid, don't add anything to Ops. 2563void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2564 char ConstraintLetter, 2565 std::vector<SDValue> &Ops, 2566 SelectionDAG &DAG) const { 2567 switch (ConstraintLetter) { 2568 default: break; 2569 case 'X': // Allows any operand; labels (basic block) use this. 2570 if (Op.getOpcode() == ISD::BasicBlock) { 2571 Ops.push_back(Op); 2572 return; 2573 } 2574 // fall through 2575 case 'i': // Simple Integer or Relocatable Constant 2576 case 'n': // Simple Integer 2577 case 's': { // Relocatable Constant 2578 // These operands are interested in values of the form (GV+C), where C may 2579 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2580 // is possible and fine if either GV or C are missing. 2581 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2582 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2583 2584 // If we have "(add GV, C)", pull out GV/C 2585 if (Op.getOpcode() == ISD::ADD) { 2586 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2587 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2588 if (C == 0 || GA == 0) { 2589 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2590 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2591 } 2592 if (C == 0 || GA == 0) 2593 C = 0, GA = 0; 2594 } 2595 2596 // If we find a valid operand, map to the TargetXXX version so that the 2597 // value itself doesn't get selected. 2598 if (GA) { // Either &GV or &GV+C 2599 if (ConstraintLetter != 'n') { 2600 int64_t Offs = GA->getOffset(); 2601 if (C) Offs += C->getZExtValue(); 2602 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2603 C ? C->getDebugLoc() : DebugLoc(), 2604 Op.getValueType(), Offs)); 2605 return; 2606 } 2607 } 2608 if (C) { // just C, no GV. 2609 // Simple constants are not allowed for 's'. 2610 if (ConstraintLetter != 's') { 2611 // gcc prints these as sign extended. Sign extend value to 64 bits 2612 // now; without this it would get ZExt'd later in 2613 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2614 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2615 MVT::i64)); 2616 return; 2617 } 2618 } 2619 break; 2620 } 2621 } 2622} 2623 2624std::vector<unsigned> TargetLowering:: 2625getRegClassForInlineAsmConstraint(const std::string &Constraint, 2626 EVT VT) const { 2627 return std::vector<unsigned>(); 2628} 2629 2630 2631std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2632getRegForInlineAsmConstraint(const std::string &Constraint, 2633 EVT VT) const { 2634 if (Constraint[0] != '{') 2635 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2636 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2637 2638 // Remove the braces from around the name. 2639 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2640 2641 // Figure out which register class contains this reg. 2642 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2643 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2644 E = RI->regclass_end(); RCI != E; ++RCI) { 2645 const TargetRegisterClass *RC = *RCI; 2646 2647 // If none of the value types for this register class are valid, we 2648 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2649 bool isLegal = false; 2650 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2651 I != E; ++I) { 2652 if (isTypeLegal(*I)) { 2653 isLegal = true; 2654 break; 2655 } 2656 } 2657 2658 if (!isLegal) continue; 2659 2660 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2661 I != E; ++I) { 2662 if (RegName.equals_lower(RI->getName(*I))) 2663 return std::make_pair(*I, RC); 2664 } 2665 } 2666 2667 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2668} 2669 2670//===----------------------------------------------------------------------===// 2671// Constraint Selection. 2672 2673/// isMatchingInputConstraint - Return true of this is an input operand that is 2674/// a matching constraint like "4". 2675bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2676 assert(!ConstraintCode.empty() && "No known constraint!"); 2677 return isdigit(ConstraintCode[0]); 2678} 2679 2680/// getMatchedOperand - If this is an input matching constraint, this method 2681/// returns the output operand it matches. 2682unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2683 assert(!ConstraintCode.empty() && "No known constraint!"); 2684 return atoi(ConstraintCode.c_str()); 2685} 2686 2687 2688/// ParseConstraints - Split up the constraint string from the inline 2689/// assembly value into the specific constraints and their prefixes, 2690/// and also tie in the associated operand values. 2691/// If this returns an empty vector, and if the constraint string itself 2692/// isn't empty, there was an error parsing. 2693TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2694 ImmutableCallSite CS) const { 2695 /// ConstraintOperands - Information about all of the constraints. 2696 AsmOperandInfoVector ConstraintOperands; 2697 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2698 unsigned maCount = 0; // Largest number of multiple alternative constraints. 2699 2700 // Do a prepass over the constraints, canonicalizing them, and building up the 2701 // ConstraintOperands list. 2702 InlineAsm::ConstraintInfoVector 2703 ConstraintInfos = IA->ParseConstraints(); 2704 2705 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2706 unsigned ResNo = 0; // ResNo - The result number of the next output. 2707 2708 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 2709 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 2710 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2711 2712 // Update multiple alternative constraint count. 2713 if (OpInfo.multipleAlternatives.size() > maCount) 2714 maCount = OpInfo.multipleAlternatives.size(); 2715 2716 OpInfo.ConstraintVT = MVT::Other; 2717 2718 // Compute the value type for each operand. 2719 switch (OpInfo.Type) { 2720 case InlineAsm::isOutput: 2721 // Indirect outputs just consume an argument. 2722 if (OpInfo.isIndirect) { 2723 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2724 break; 2725 } 2726 2727 // The return value of the call is this value. As such, there is no 2728 // corresponding argument. 2729 assert(!CS.getType()->isVoidTy() && 2730 "Bad inline asm!"); 2731 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 2732 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo)); 2733 } else { 2734 assert(ResNo == 0 && "Asm only has one result!"); 2735 OpInfo.ConstraintVT = getValueType(CS.getType()); 2736 } 2737 ++ResNo; 2738 break; 2739 case InlineAsm::isInput: 2740 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2741 break; 2742 case InlineAsm::isClobber: 2743 // Nothing to do. 2744 break; 2745 } 2746 2747 if (OpInfo.CallOperandVal) { 2748 const llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2749 if (OpInfo.isIndirect) { 2750 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2751 if (!PtrTy) 2752 report_fatal_error("Indirect operand for inline asm not a pointer!"); 2753 OpTy = PtrTy->getElementType(); 2754 } 2755 // If OpTy is not a single value, it may be a struct/union that we 2756 // can tile with integers. 2757 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2758 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 2759 switch (BitSize) { 2760 default: break; 2761 case 1: 2762 case 8: 2763 case 16: 2764 case 32: 2765 case 64: 2766 case 128: 2767 OpInfo.ConstraintVT = 2768 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true); 2769 break; 2770 } 2771 } else if (dyn_cast<PointerType>(OpTy)) { 2772 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize()); 2773 } else { 2774 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true); 2775 } 2776 } 2777 } 2778 2779 // If we have multiple alternative constraints, select the best alternative. 2780 if (ConstraintInfos.size()) { 2781 if (maCount) { 2782 unsigned bestMAIndex = 0; 2783 int bestWeight = -1; 2784 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2785 int weight = -1; 2786 unsigned maIndex; 2787 // Compute the sums of the weights for each alternative, keeping track 2788 // of the best (highest weight) one so far. 2789 for (maIndex = 0; maIndex < maCount; ++maIndex) { 2790 int weightSum = 0; 2791 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2792 cIndex != eIndex; ++cIndex) { 2793 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2794 if (OpInfo.Type == InlineAsm::isClobber) 2795 continue; 2796 2797 // If this is an output operand with a matching input operand, 2798 // look up the matching input. If their types mismatch, e.g. one 2799 // is an integer, the other is floating point, or their sizes are 2800 // different, flag it as an maCantMatch. 2801 if (OpInfo.hasMatchingInput()) { 2802 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2803 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2804 if ((OpInfo.ConstraintVT.isInteger() != 2805 Input.ConstraintVT.isInteger()) || 2806 (OpInfo.ConstraintVT.getSizeInBits() != 2807 Input.ConstraintVT.getSizeInBits())) { 2808 weightSum = -1; // Can't match. 2809 break; 2810 } 2811 } 2812 } 2813 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 2814 if (weight == -1) { 2815 weightSum = -1; 2816 break; 2817 } 2818 weightSum += weight; 2819 } 2820 // Update best. 2821 if (weightSum > bestWeight) { 2822 bestWeight = weightSum; 2823 bestMAIndex = maIndex; 2824 } 2825 } 2826 2827 // Now select chosen alternative in each constraint. 2828 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2829 cIndex != eIndex; ++cIndex) { 2830 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 2831 if (cInfo.Type == InlineAsm::isClobber) 2832 continue; 2833 cInfo.selectAlternative(bestMAIndex); 2834 } 2835 } 2836 } 2837 2838 // Check and hook up tied operands, choose constraint code to use. 2839 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2840 cIndex != eIndex; ++cIndex) { 2841 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2842 2843 // If this is an output operand with a matching input operand, look up the 2844 // matching input. If their types mismatch, e.g. one is an integer, the 2845 // other is floating point, or their sizes are different, flag it as an 2846 // error. 2847 if (OpInfo.hasMatchingInput()) { 2848 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2849 2850 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2851 if ((OpInfo.ConstraintVT.isInteger() != 2852 Input.ConstraintVT.isInteger()) || 2853 (OpInfo.ConstraintVT.getSizeInBits() != 2854 Input.ConstraintVT.getSizeInBits())) { 2855 report_fatal_error("Unsupported asm: input constraint" 2856 " with a matching output constraint of" 2857 " incompatible type!"); 2858 } 2859 } 2860 2861 } 2862 } 2863 2864 return ConstraintOperands; 2865} 2866 2867 2868/// getConstraintGenerality - Return an integer indicating how general CT 2869/// is. 2870static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2871 switch (CT) { 2872 default: llvm_unreachable("Unknown constraint type!"); 2873 case TargetLowering::C_Other: 2874 case TargetLowering::C_Unknown: 2875 return 0; 2876 case TargetLowering::C_Register: 2877 return 1; 2878 case TargetLowering::C_RegisterClass: 2879 return 2; 2880 case TargetLowering::C_Memory: 2881 return 3; 2882 } 2883} 2884 2885/// Examine constraint type and operand type and determine a weight value. 2886/// This object must already have been set up with the operand type 2887/// and the current alternative constraint selected. 2888TargetLowering::ConstraintWeight 2889 TargetLowering::getMultipleConstraintMatchWeight( 2890 AsmOperandInfo &info, int maIndex) const { 2891 InlineAsm::ConstraintCodeVector *rCodes; 2892 if (maIndex >= (int)info.multipleAlternatives.size()) 2893 rCodes = &info.Codes; 2894 else 2895 rCodes = &info.multipleAlternatives[maIndex].Codes; 2896 ConstraintWeight BestWeight = CW_Invalid; 2897 2898 // Loop over the options, keeping track of the most general one. 2899 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 2900 ConstraintWeight weight = 2901 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 2902 if (weight > BestWeight) 2903 BestWeight = weight; 2904 } 2905 2906 return BestWeight; 2907} 2908 2909/// Examine constraint type and operand type and determine a weight value. 2910/// This object must already have been set up with the operand type 2911/// and the current alternative constraint selected. 2912TargetLowering::ConstraintWeight 2913 TargetLowering::getSingleConstraintMatchWeight( 2914 AsmOperandInfo &info, const char *constraint) const { 2915 ConstraintWeight weight = CW_Invalid; 2916 Value *CallOperandVal = info.CallOperandVal; 2917 // If we don't have a value, we can't do a match, 2918 // but allow it at the lowest weight. 2919 if (CallOperandVal == NULL) 2920 return CW_Default; 2921 // Look at the constraint type. 2922 switch (*constraint) { 2923 case 'i': // immediate integer. 2924 case 'n': // immediate integer with a known value. 2925 if (isa<ConstantInt>(CallOperandVal)) 2926 weight = CW_Constant; 2927 break; 2928 case 's': // non-explicit intregal immediate. 2929 if (isa<GlobalValue>(CallOperandVal)) 2930 weight = CW_Constant; 2931 break; 2932 case 'E': // immediate float if host format. 2933 case 'F': // immediate float. 2934 if (isa<ConstantFP>(CallOperandVal)) 2935 weight = CW_Constant; 2936 break; 2937 case '<': // memory operand with autodecrement. 2938 case '>': // memory operand with autoincrement. 2939 case 'm': // memory operand. 2940 case 'o': // offsettable memory operand 2941 case 'V': // non-offsettable memory operand 2942 weight = CW_Memory; 2943 break; 2944 case 'r': // general register. 2945 case 'g': // general register, memory operand or immediate integer. 2946 // note: Clang converts "g" to "imr". 2947 if (CallOperandVal->getType()->isIntegerTy()) 2948 weight = CW_Register; 2949 break; 2950 case 'X': // any operand. 2951 default: 2952 weight = CW_Default; 2953 break; 2954 } 2955 return weight; 2956} 2957 2958/// ChooseConstraint - If there are multiple different constraints that we 2959/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2960/// This is somewhat tricky: constraints fall into four classes: 2961/// Other -> immediates and magic values 2962/// Register -> one specific register 2963/// RegisterClass -> a group of regs 2964/// Memory -> memory 2965/// Ideally, we would pick the most specific constraint possible: if we have 2966/// something that fits into a register, we would pick it. The problem here 2967/// is that if we have something that could either be in a register or in 2968/// memory that use of the register could cause selection of *other* 2969/// operands to fail: they might only succeed if we pick memory. Because of 2970/// this the heuristic we use is: 2971/// 2972/// 1) If there is an 'other' constraint, and if the operand is valid for 2973/// that constraint, use it. This makes us take advantage of 'i' 2974/// constraints when available. 2975/// 2) Otherwise, pick the most general constraint present. This prefers 2976/// 'm' over 'r', for example. 2977/// 2978static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2979 const TargetLowering &TLI, 2980 SDValue Op, SelectionDAG *DAG) { 2981 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2982 unsigned BestIdx = 0; 2983 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2984 int BestGenerality = -1; 2985 2986 // Loop over the options, keeping track of the most general one. 2987 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2988 TargetLowering::ConstraintType CType = 2989 TLI.getConstraintType(OpInfo.Codes[i]); 2990 2991 // If this is an 'other' constraint, see if the operand is valid for it. 2992 // For example, on X86 we might have an 'rI' constraint. If the operand 2993 // is an integer in the range [0..31] we want to use I (saving a load 2994 // of a register), otherwise we must use 'r'. 2995 if (CType == TargetLowering::C_Other && Op.getNode()) { 2996 assert(OpInfo.Codes[i].size() == 1 && 2997 "Unhandled multi-letter 'other' constraint"); 2998 std::vector<SDValue> ResultOps; 2999 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], 3000 ResultOps, *DAG); 3001 if (!ResultOps.empty()) { 3002 BestType = CType; 3003 BestIdx = i; 3004 break; 3005 } 3006 } 3007 3008 // Things with matching constraints can only be registers, per gcc 3009 // documentation. This mainly affects "g" constraints. 3010 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 3011 continue; 3012 3013 // This constraint letter is more general than the previous one, use it. 3014 int Generality = getConstraintGenerality(CType); 3015 if (Generality > BestGenerality) { 3016 BestType = CType; 3017 BestIdx = i; 3018 BestGenerality = Generality; 3019 } 3020 } 3021 3022 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 3023 OpInfo.ConstraintType = BestType; 3024} 3025 3026/// ComputeConstraintToUse - Determines the constraint code and constraint 3027/// type to use for the specific AsmOperandInfo, setting 3028/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 3029void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 3030 SDValue Op, 3031 SelectionDAG *DAG) const { 3032 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 3033 3034 // Single-letter constraints ('r') are very common. 3035 if (OpInfo.Codes.size() == 1) { 3036 OpInfo.ConstraintCode = OpInfo.Codes[0]; 3037 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3038 } else { 3039 ChooseConstraint(OpInfo, *this, Op, DAG); 3040 } 3041 3042 // 'X' matches anything. 3043 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 3044 // Labels and constants are handled elsewhere ('X' is the only thing 3045 // that matches labels). For Functions, the type here is the type of 3046 // the result, which is not what we want to look at; leave them alone. 3047 Value *v = OpInfo.CallOperandVal; 3048 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 3049 OpInfo.CallOperandVal = v; 3050 return; 3051 } 3052 3053 // Otherwise, try to resolve it to something we know about by looking at 3054 // the actual operand type. 3055 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 3056 OpInfo.ConstraintCode = Repl; 3057 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3058 } 3059 } 3060} 3061 3062//===----------------------------------------------------------------------===// 3063// Loop Strength Reduction hooks 3064//===----------------------------------------------------------------------===// 3065 3066/// isLegalAddressingMode - Return true if the addressing mode represented 3067/// by AM is legal for this target, for a load/store of the specified type. 3068bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 3069 const Type *Ty) const { 3070 // The default implementation of this implements a conservative RISCy, r+r and 3071 // r+i addr mode. 3072 3073 // Allows a sign-extended 16-bit immediate field. 3074 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3075 return false; 3076 3077 // No global is ever allowed as a base. 3078 if (AM.BaseGV) 3079 return false; 3080 3081 // Only support r+r, 3082 switch (AM.Scale) { 3083 case 0: // "r+i" or just "i", depending on HasBaseReg. 3084 break; 3085 case 1: 3086 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3087 return false; 3088 // Otherwise we have r+r or r+i. 3089 break; 3090 case 2: 3091 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3092 return false; 3093 // Allow 2*r as r+r. 3094 break; 3095 } 3096 3097 return true; 3098} 3099 3100/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3101/// return a DAG expression to select that will generate the same value by 3102/// multiplying by a magic number. See: 3103/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3104SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 3105 std::vector<SDNode*>* Created) const { 3106 EVT VT = N->getValueType(0); 3107 DebugLoc dl= N->getDebugLoc(); 3108 3109 // Check to see if we can do this. 3110 // FIXME: We should be more aggressive here. 3111 if (!isTypeLegal(VT)) 3112 return SDValue(); 3113 3114 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3115 APInt::ms magics = d.magic(); 3116 3117 // Multiply the numerator (operand 0) by the magic value 3118 // FIXME: We should support doing a MUL in a wider type 3119 SDValue Q; 3120 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 3121 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 3122 DAG.getConstant(magics.m, VT)); 3123 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 3124 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 3125 N->getOperand(0), 3126 DAG.getConstant(magics.m, VT)).getNode(), 1); 3127 else 3128 return SDValue(); // No mulhs or equvialent 3129 // If d > 0 and m < 0, add the numerator 3130 if (d.isStrictlyPositive() && magics.m.isNegative()) { 3131 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 3132 if (Created) 3133 Created->push_back(Q.getNode()); 3134 } 3135 // If d < 0 and m > 0, subtract the numerator. 3136 if (d.isNegative() && magics.m.isStrictlyPositive()) { 3137 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 3138 if (Created) 3139 Created->push_back(Q.getNode()); 3140 } 3141 // Shift right algebraic if shift value is nonzero 3142 if (magics.s > 0) { 3143 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 3144 DAG.getConstant(magics.s, getShiftAmountTy())); 3145 if (Created) 3146 Created->push_back(Q.getNode()); 3147 } 3148 // Extract the sign bit and add it to the quotient 3149 SDValue T = 3150 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 3151 getShiftAmountTy())); 3152 if (Created) 3153 Created->push_back(T.getNode()); 3154 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 3155} 3156 3157/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3158/// return a DAG expression to select that will generate the same value by 3159/// multiplying by a magic number. See: 3160/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3161SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 3162 std::vector<SDNode*>* Created) const { 3163 EVT VT = N->getValueType(0); 3164 DebugLoc dl = N->getDebugLoc(); 3165 3166 // Check to see if we can do this. 3167 // FIXME: We should be more aggressive here. 3168 if (!isTypeLegal(VT)) 3169 return SDValue(); 3170 3171 // FIXME: We should use a narrower constant when the upper 3172 // bits are known to be zero. 3173 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 3174 APInt::mu magics = N1C->getAPIntValue().magicu(); 3175 3176 // Multiply the numerator (operand 0) by the magic value 3177 // FIXME: We should support doing a MUL in a wider type 3178 SDValue Q; 3179 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 3180 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 3181 DAG.getConstant(magics.m, VT)); 3182 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 3183 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 3184 N->getOperand(0), 3185 DAG.getConstant(magics.m, VT)).getNode(), 1); 3186 else 3187 return SDValue(); // No mulhu or equvialent 3188 if (Created) 3189 Created->push_back(Q.getNode()); 3190 3191 if (magics.a == 0) { 3192 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 3193 "We shouldn't generate an undefined shift!"); 3194 return DAG.getNode(ISD::SRL, dl, VT, Q, 3195 DAG.getConstant(magics.s, getShiftAmountTy())); 3196 } else { 3197 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 3198 if (Created) 3199 Created->push_back(NPQ.getNode()); 3200 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 3201 DAG.getConstant(1, getShiftAmountTy())); 3202 if (Created) 3203 Created->push_back(NPQ.getNode()); 3204 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 3205 if (Created) 3206 Created->push_back(NPQ.getNode()); 3207 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 3208 DAG.getConstant(magics.s-1, getShiftAmountTy())); 3209 } 3210} 3211