TargetLowering.cpp revision 11eab02b770086c119a18aae0fe214fbe5eed0d0 
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/MC/MCAsmInfo.h"
16#include "llvm/Target/TargetData.h"
17#include "llvm/Target/TargetLoweringObjectFile.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetRegisterInfo.h"
20#include "llvm/Target/TargetSubtarget.h"
21#include "llvm/GlobalVariable.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/SelectionDAG.h"
25#include "llvm/ADT/StringExtras.h"
26#include "llvm/ADT/STLExtras.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/MathExtras.h"
29using namespace llvm;
30
31namespace llvm {
32TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
33  bool isLocal = GV->hasLocalLinkage();
34  bool isDeclaration = GV->isDeclaration();
35  // FIXME: what should we do for protected and internal visibility?
36  // For variables, is internal different from hidden?
37  bool isHidden = GV->hasHiddenVisibility();
38
39  if (reloc == Reloc::PIC_) {
40    if (isLocal || isHidden)
41      return TLSModel::LocalDynamic;
42    else
43      return TLSModel::GeneralDynamic;
44  } else {
45    if (!isDeclaration || isHidden)
46      return TLSModel::LocalExec;
47    else
48      return TLSModel::InitialExec;
49  }
50}
51}
52
53/// InitLibcallNames - Set default libcall names.
54///
55static void InitLibcallNames(const char **Names) {
56  Names[RTLIB::SHL_I16] = "__ashlhi3";
57  Names[RTLIB::SHL_I32] = "__ashlsi3";
58  Names[RTLIB::SHL_I64] = "__ashldi3";
59  Names[RTLIB::SHL_I128] = "__ashlti3";
60  Names[RTLIB::SRL_I16] = "__lshrhi3";
61  Names[RTLIB::SRL_I32] = "__lshrsi3";
62  Names[RTLIB::SRL_I64] = "__lshrdi3";
63  Names[RTLIB::SRL_I128] = "__lshrti3";
64  Names[RTLIB::SRA_I16] = "__ashrhi3";
65  Names[RTLIB::SRA_I32] = "__ashrsi3";
66  Names[RTLIB::SRA_I64] = "__ashrdi3";
67  Names[RTLIB::SRA_I128] = "__ashrti3";
68  Names[RTLIB::MUL_I16] = "__mulhi3";
69  Names[RTLIB::MUL_I32] = "__mulsi3";
70  Names[RTLIB::MUL_I64] = "__muldi3";
71  Names[RTLIB::MUL_I128] = "__multi3";
72  Names[RTLIB::SDIV_I16] = "__divhi3";
73  Names[RTLIB::SDIV_I32] = "__divsi3";
74  Names[RTLIB::SDIV_I64] = "__divdi3";
75  Names[RTLIB::SDIV_I128] = "__divti3";
76  Names[RTLIB::UDIV_I16] = "__udivhi3";
77  Names[RTLIB::UDIV_I32] = "__udivsi3";
78  Names[RTLIB::UDIV_I64] = "__udivdi3";
79  Names[RTLIB::UDIV_I128] = "__udivti3";
80  Names[RTLIB::SREM_I16] = "__modhi3";
81  Names[RTLIB::SREM_I32] = "__modsi3";
82  Names[RTLIB::SREM_I64] = "__moddi3";
83  Names[RTLIB::SREM_I128] = "__modti3";
84  Names[RTLIB::UREM_I16] = "__umodhi3";
85  Names[RTLIB::UREM_I32] = "__umodsi3";
86  Names[RTLIB::UREM_I64] = "__umoddi3";
87  Names[RTLIB::UREM_I128] = "__umodti3";
88  Names[RTLIB::NEG_I32] = "__negsi2";
89  Names[RTLIB::NEG_I64] = "__negdi2";
90  Names[RTLIB::ADD_F32] = "__addsf3";
91  Names[RTLIB::ADD_F64] = "__adddf3";
92  Names[RTLIB::ADD_F80] = "__addxf3";
93  Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
94  Names[RTLIB::SUB_F32] = "__subsf3";
95  Names[RTLIB::SUB_F64] = "__subdf3";
96  Names[RTLIB::SUB_F80] = "__subxf3";
97  Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
98  Names[RTLIB::MUL_F32] = "__mulsf3";
99  Names[RTLIB::MUL_F64] = "__muldf3";
100  Names[RTLIB::MUL_F80] = "__mulxf3";
101  Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
102  Names[RTLIB::DIV_F32] = "__divsf3";
103  Names[RTLIB::DIV_F64] = "__divdf3";
104  Names[RTLIB::DIV_F80] = "__divxf3";
105  Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
106  Names[RTLIB::REM_F32] = "fmodf";
107  Names[RTLIB::REM_F64] = "fmod";
108  Names[RTLIB::REM_F80] = "fmodl";
109  Names[RTLIB::REM_PPCF128] = "fmodl";
110  Names[RTLIB::POWI_F32] = "__powisf2";
111  Names[RTLIB::POWI_F64] = "__powidf2";
112  Names[RTLIB::POWI_F80] = "__powixf2";
113  Names[RTLIB::POWI_PPCF128] = "__powitf2";
114  Names[RTLIB::SQRT_F32] = "sqrtf";
115  Names[RTLIB::SQRT_F64] = "sqrt";
116  Names[RTLIB::SQRT_F80] = "sqrtl";
117  Names[RTLIB::SQRT_PPCF128] = "sqrtl";
118  Names[RTLIB::LOG_F32] = "logf";
119  Names[RTLIB::LOG_F64] = "log";
120  Names[RTLIB::LOG_F80] = "logl";
121  Names[RTLIB::LOG_PPCF128] = "logl";
122  Names[RTLIB::LOG2_F32] = "log2f";
123  Names[RTLIB::LOG2_F64] = "log2";
124  Names[RTLIB::LOG2_F80] = "log2l";
125  Names[RTLIB::LOG2_PPCF128] = "log2l";
126  Names[RTLIB::LOG10_F32] = "log10f";
127  Names[RTLIB::LOG10_F64] = "log10";
128  Names[RTLIB::LOG10_F80] = "log10l";
129  Names[RTLIB::LOG10_PPCF128] = "log10l";
130  Names[RTLIB::EXP_F32] = "expf";
131  Names[RTLIB::EXP_F64] = "exp";
132  Names[RTLIB::EXP_F80] = "expl";
133  Names[RTLIB::EXP_PPCF128] = "expl";
134  Names[RTLIB::EXP2_F32] = "exp2f";
135  Names[RTLIB::EXP2_F64] = "exp2";
136  Names[RTLIB::EXP2_F80] = "exp2l";
137  Names[RTLIB::EXP2_PPCF128] = "exp2l";
138  Names[RTLIB::SIN_F32] = "sinf";
139  Names[RTLIB::SIN_F64] = "sin";
140  Names[RTLIB::SIN_F80] = "sinl";
141  Names[RTLIB::SIN_PPCF128] = "sinl";
142  Names[RTLIB::COS_F32] = "cosf";
143  Names[RTLIB::COS_F64] = "cos";
144  Names[RTLIB::COS_F80] = "cosl";
145  Names[RTLIB::COS_PPCF128] = "cosl";
146  Names[RTLIB::POW_F32] = "powf";
147  Names[RTLIB::POW_F64] = "pow";
148  Names[RTLIB::POW_F80] = "powl";
149  Names[RTLIB::POW_PPCF128] = "powl";
150  Names[RTLIB::CEIL_F32] = "ceilf";
151  Names[RTLIB::CEIL_F64] = "ceil";
152  Names[RTLIB::CEIL_F80] = "ceill";
153  Names[RTLIB::CEIL_PPCF128] = "ceill";
154  Names[RTLIB::TRUNC_F32] = "truncf";
155  Names[RTLIB::TRUNC_F64] = "trunc";
156  Names[RTLIB::TRUNC_F80] = "truncl";
157  Names[RTLIB::TRUNC_PPCF128] = "truncl";
158  Names[RTLIB::RINT_F32] = "rintf";
159  Names[RTLIB::RINT_F64] = "rint";
160  Names[RTLIB::RINT_F80] = "rintl";
161  Names[RTLIB::RINT_PPCF128] = "rintl";
162  Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
163  Names[RTLIB::NEARBYINT_F64] = "nearbyint";
164  Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
165  Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
166  Names[RTLIB::FLOOR_F32] = "floorf";
167  Names[RTLIB::FLOOR_F64] = "floor";
168  Names[RTLIB::FLOOR_F80] = "floorl";
169  Names[RTLIB::FLOOR_PPCF128] = "floorl";
170  Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
171  Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
172  Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
173  Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
174  Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
175  Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
176  Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfi8";
177  Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfi16";
178  Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
179  Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
180  Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
181  Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
182  Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
183  Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
184  Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
185  Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
186  Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
187  Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
188  Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
189  Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
190  Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfi8";
191  Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfi16";
192  Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
193  Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
194  Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
195  Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
196  Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
197  Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
198  Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
199  Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
200  Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
201  Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
202  Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
203  Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
204  Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
205  Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
206  Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
207  Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
208  Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
209  Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
210  Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
211  Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
212  Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
213  Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
214  Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
215  Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
216  Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
217  Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
218  Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
219  Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
220  Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
221  Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
222  Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
223  Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
224  Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
225  Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
226  Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
227  Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
228  Names[RTLIB::OEQ_F32] = "__eqsf2";
229  Names[RTLIB::OEQ_F64] = "__eqdf2";
230  Names[RTLIB::UNE_F32] = "__nesf2";
231  Names[RTLIB::UNE_F64] = "__nedf2";
232  Names[RTLIB::OGE_F32] = "__gesf2";
233  Names[RTLIB::OGE_F64] = "__gedf2";
234  Names[RTLIB::OLT_F32] = "__ltsf2";
235  Names[RTLIB::OLT_F64] = "__ltdf2";
236  Names[RTLIB::OLE_F32] = "__lesf2";
237  Names[RTLIB::OLE_F64] = "__ledf2";
238  Names[RTLIB::OGT_F32] = "__gtsf2";
239  Names[RTLIB::OGT_F64] = "__gtdf2";
240  Names[RTLIB::UO_F32] = "__unordsf2";
241  Names[RTLIB::UO_F64] = "__unorddf2";
242  Names[RTLIB::O_F32] = "__unordsf2";
243  Names[RTLIB::O_F64] = "__unorddf2";
244  Names[RTLIB::MEMCPY] = "memcpy";
245  Names[RTLIB::MEMMOVE] = "memmove";
246  Names[RTLIB::MEMSET] = "memset";
247  Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
248}
249
250/// InitLibcallCallingConvs - Set default libcall CallingConvs.
251///
252static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
253  for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
254    CCs[i] = CallingConv::C;
255  }
256}
257
258/// getFPEXT - Return the FPEXT_*_* value for the given types, or
259/// UNKNOWN_LIBCALL if there is none.
260RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
261  if (OpVT == MVT::f32) {
262    if (RetVT == MVT::f64)
263      return FPEXT_F32_F64;
264  }
265  return UNKNOWN_LIBCALL;
266}
267
268/// getFPROUND - Return the FPROUND_*_* value for the given types, or
269/// UNKNOWN_LIBCALL if there is none.
270RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
271  if (RetVT == MVT::f32) {
272    if (OpVT == MVT::f64)
273      return FPROUND_F64_F32;
274    if (OpVT == MVT::f80)
275      return FPROUND_F80_F32;
276    if (OpVT == MVT::ppcf128)
277      return FPROUND_PPCF128_F32;
278  } else if (RetVT == MVT::f64) {
279    if (OpVT == MVT::f80)
280      return FPROUND_F80_F64;
281    if (OpVT == MVT::ppcf128)
282      return FPROUND_PPCF128_F64;
283  }
284  return UNKNOWN_LIBCALL;
285}
286
287/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
288/// UNKNOWN_LIBCALL if there is none.
289RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
290  if (OpVT == MVT::f32) {
291    if (RetVT == MVT::i8)
292      return FPTOSINT_F32_I8;
293    if (RetVT == MVT::i16)
294      return FPTOSINT_F32_I16;
295    if (RetVT == MVT::i32)
296      return FPTOSINT_F32_I32;
297    if (RetVT == MVT::i64)
298      return FPTOSINT_F32_I64;
299    if (RetVT == MVT::i128)
300      return FPTOSINT_F32_I128;
301  } else if (OpVT == MVT::f64) {
302    if (RetVT == MVT::i32)
303      return FPTOSINT_F64_I32;
304    if (RetVT == MVT::i64)
305      return FPTOSINT_F64_I64;
306    if (RetVT == MVT::i128)
307      return FPTOSINT_F64_I128;
308  } else if (OpVT == MVT::f80) {
309    if (RetVT == MVT::i32)
310      return FPTOSINT_F80_I32;
311    if (RetVT == MVT::i64)
312      return FPTOSINT_F80_I64;
313    if (RetVT == MVT::i128)
314      return FPTOSINT_F80_I128;
315  } else if (OpVT == MVT::ppcf128) {
316    if (RetVT == MVT::i32)
317      return FPTOSINT_PPCF128_I32;
318    if (RetVT == MVT::i64)
319      return FPTOSINT_PPCF128_I64;
320    if (RetVT == MVT::i128)
321      return FPTOSINT_PPCF128_I128;
322  }
323  return UNKNOWN_LIBCALL;
324}
325
326/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
327/// UNKNOWN_LIBCALL if there is none.
328RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
329  if (OpVT == MVT::f32) {
330    if (RetVT == MVT::i8)
331      return FPTOUINT_F32_I8;
332    if (RetVT == MVT::i16)
333      return FPTOUINT_F32_I16;
334    if (RetVT == MVT::i32)
335      return FPTOUINT_F32_I32;
336    if (RetVT == MVT::i64)
337      return FPTOUINT_F32_I64;
338    if (RetVT == MVT::i128)
339      return FPTOUINT_F32_I128;
340  } else if (OpVT == MVT::f64) {
341    if (RetVT == MVT::i32)
342      return FPTOUINT_F64_I32;
343    if (RetVT == MVT::i64)
344      return FPTOUINT_F64_I64;
345    if (RetVT == MVT::i128)
346      return FPTOUINT_F64_I128;
347  } else if (OpVT == MVT::f80) {
348    if (RetVT == MVT::i32)
349      return FPTOUINT_F80_I32;
350    if (RetVT == MVT::i64)
351      return FPTOUINT_F80_I64;
352    if (RetVT == MVT::i128)
353      return FPTOUINT_F80_I128;
354  } else if (OpVT == MVT::ppcf128) {
355    if (RetVT == MVT::i32)
356      return FPTOUINT_PPCF128_I32;
357    if (RetVT == MVT::i64)
358      return FPTOUINT_PPCF128_I64;
359    if (RetVT == MVT::i128)
360      return FPTOUINT_PPCF128_I128;
361  }
362  return UNKNOWN_LIBCALL;
363}
364
365/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
366/// UNKNOWN_LIBCALL if there is none.
367RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
368  if (OpVT == MVT::i32) {
369    if (RetVT == MVT::f32)
370      return SINTTOFP_I32_F32;
371    else if (RetVT == MVT::f64)
372      return SINTTOFP_I32_F64;
373    else if (RetVT == MVT::f80)
374      return SINTTOFP_I32_F80;
375    else if (RetVT == MVT::ppcf128)
376      return SINTTOFP_I32_PPCF128;
377  } else if (OpVT == MVT::i64) {
378    if (RetVT == MVT::f32)
379      return SINTTOFP_I64_F32;
380    else if (RetVT == MVT::f64)
381      return SINTTOFP_I64_F64;
382    else if (RetVT == MVT::f80)
383      return SINTTOFP_I64_F80;
384    else if (RetVT == MVT::ppcf128)
385      return SINTTOFP_I64_PPCF128;
386  } else if (OpVT == MVT::i128) {
387    if (RetVT == MVT::f32)
388      return SINTTOFP_I128_F32;
389    else if (RetVT == MVT::f64)
390      return SINTTOFP_I128_F64;
391    else if (RetVT == MVT::f80)
392      return SINTTOFP_I128_F80;
393    else if (RetVT == MVT::ppcf128)
394      return SINTTOFP_I128_PPCF128;
395  }
396  return UNKNOWN_LIBCALL;
397}
398
399/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
400/// UNKNOWN_LIBCALL if there is none.
401RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
402  if (OpVT == MVT::i32) {
403    if (RetVT == MVT::f32)
404      return UINTTOFP_I32_F32;
405    else if (RetVT == MVT::f64)
406      return UINTTOFP_I32_F64;
407    else if (RetVT == MVT::f80)
408      return UINTTOFP_I32_F80;
409    else if (RetVT == MVT::ppcf128)
410      return UINTTOFP_I32_PPCF128;
411  } else if (OpVT == MVT::i64) {
412    if (RetVT == MVT::f32)
413      return UINTTOFP_I64_F32;
414    else if (RetVT == MVT::f64)
415      return UINTTOFP_I64_F64;
416    else if (RetVT == MVT::f80)
417      return UINTTOFP_I64_F80;
418    else if (RetVT == MVT::ppcf128)
419      return UINTTOFP_I64_PPCF128;
420  } else if (OpVT == MVT::i128) {
421    if (RetVT == MVT::f32)
422      return UINTTOFP_I128_F32;
423    else if (RetVT == MVT::f64)
424      return UINTTOFP_I128_F64;
425    else if (RetVT == MVT::f80)
426      return UINTTOFP_I128_F80;
427    else if (RetVT == MVT::ppcf128)
428      return UINTTOFP_I128_PPCF128;
429  }
430  return UNKNOWN_LIBCALL;
431}
432
433/// InitCmpLibcallCCs - Set default comparison libcall CC.
434///
435static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
436  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
437  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
438  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
439  CCs[RTLIB::UNE_F32] = ISD::SETNE;
440  CCs[RTLIB::UNE_F64] = ISD::SETNE;
441  CCs[RTLIB::OGE_F32] = ISD::SETGE;
442  CCs[RTLIB::OGE_F64] = ISD::SETGE;
443  CCs[RTLIB::OLT_F32] = ISD::SETLT;
444  CCs[RTLIB::OLT_F64] = ISD::SETLT;
445  CCs[RTLIB::OLE_F32] = ISD::SETLE;
446  CCs[RTLIB::OLE_F64] = ISD::SETLE;
447  CCs[RTLIB::OGT_F32] = ISD::SETGT;
448  CCs[RTLIB::OGT_F64] = ISD::SETGT;
449  CCs[RTLIB::UO_F32] = ISD::SETNE;
450  CCs[RTLIB::UO_F64] = ISD::SETNE;
451  CCs[RTLIB::O_F32] = ISD::SETEQ;
452  CCs[RTLIB::O_F64] = ISD::SETEQ;
453}
454
455/// NOTE: The constructor takes ownership of TLOF.
456TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof)
457  : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
458  // All operations default to being supported.
459  memset(OpActions, 0, sizeof(OpActions));
460  memset(LoadExtActions, 0, sizeof(LoadExtActions));
461  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
462  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
463  memset(ConvertActions, 0, sizeof(ConvertActions));
464  memset(CondCodeActions, 0, sizeof(CondCodeActions));
465
466  // Set default actions for various operations.
467  for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
468    // Default all indexed load / store to expand.
469    for (unsigned IM = (unsigned)ISD::PRE_INC;
470         IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
471      setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
472      setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
473    }
474
475    // These operations default to expand.
476    setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
477    setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
478  }
479
480  // Most targets ignore the @llvm.prefetch intrinsic.
481  setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
482
483  // ConstantFP nodes default to expand.  Targets can either change this to
484  // Legal, in which case all fp constants are legal, or use addLegalFPImmediate
485  // to optimize expansions for certain constants.
486  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
487  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
488  setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
489
490  // These library functions default to expand.
491  setOperationAction(ISD::FLOG , MVT::f64, Expand);
492  setOperationAction(ISD::FLOG2, MVT::f64, Expand);
493  setOperationAction(ISD::FLOG10,MVT::f64, Expand);
494  setOperationAction(ISD::FEXP , MVT::f64, Expand);
495  setOperationAction(ISD::FEXP2, MVT::f64, Expand);
496  setOperationAction(ISD::FLOG , MVT::f32, Expand);
497  setOperationAction(ISD::FLOG2, MVT::f32, Expand);
498  setOperationAction(ISD::FLOG10,MVT::f32, Expand);
499  setOperationAction(ISD::FEXP , MVT::f32, Expand);
500  setOperationAction(ISD::FEXP2, MVT::f32, Expand);
501
502  // Default ISD::TRAP to expand (which turns it into abort).
503  setOperationAction(ISD::TRAP, MVT::Other, Expand);
504
505  IsLittleEndian = TD->isLittleEndian();
506  UsesGlobalOffsetTable = false;
507  ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
508  memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
509  memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
510  maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
511  benefitFromCodePlacementOpt = false;
512  UseUnderscoreSetJmp = false;
513  UseUnderscoreLongJmp = false;
514  SelectIsExpensive = false;
515  IntDivIsCheap = false;
516  Pow2DivIsCheap = false;
517  StackPointerRegisterToSaveRestore = 0;
518  ExceptionPointerRegister = 0;
519  ExceptionSelectorRegister = 0;
520  BooleanContents = UndefinedBooleanContent;
521  SchedPreferenceInfo = SchedulingForLatency;
522  JumpBufSize = 0;
523  JumpBufAlignment = 0;
524  IfCvtBlockSizeLimit = 2;
525  IfCvtDupBlockSizeLimit = 0;
526  PrefLoopAlignment = 0;
527
528  InitLibcallNames(LibcallRoutineNames);
529  InitCmpLibcallCCs(CmpLibcallCCs);
530  InitLibcallCallingConvs(LibcallCallingConvs);
531
532  // Tell Legalize whether the assembler supports DEBUG_LOC.
533  const MCAsmInfo *TASM = TM.getMCAsmInfo();
534  if (!TASM || !TASM->hasDotLocAndDotFile())
535    setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
536}
537
538TargetLowering::~TargetLowering() {
539  delete &TLOF;
540}
541
542static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
543                                       unsigned &NumIntermediates,
544                                       EVT &RegisterVT,
545                                       TargetLowering* TLI) {
546  // Figure out the right, legal destination reg to copy into.
547  unsigned NumElts = VT.getVectorNumElements();
548  MVT EltTy = VT.getVectorElementType();
549
550  unsigned NumVectorRegs = 1;
551
552  // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally we
553  // could break down into LHS/RHS like LegalizeDAG does.
554  if (!isPowerOf2_32(NumElts)) {
555    NumVectorRegs = NumElts;
556    NumElts = 1;
557  }
558
559  // Divide the input until we get to a supported size.  This will always
560  // end with a scalar if the target doesn't support vectors.
561  while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
562    NumElts >>= 1;
563    NumVectorRegs <<= 1;
564  }
565
566  NumIntermediates = NumVectorRegs;
567
568  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
569  if (!TLI->isTypeLegal(NewVT))
570    NewVT = EltTy;
571  IntermediateVT = NewVT;
572
573  EVT DestVT = TLI->getRegisterType(NewVT);
574  RegisterVT = DestVT;
575  if (EVT(DestVT).bitsLT(NewVT)) {
576    // Value is expanded, e.g. i64 -> i16.
577    return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
578  } else {
579    // Otherwise, promotion or legal types use the same number of registers as
580    // the vector decimated to the appropriate level.
581    return NumVectorRegs;
582  }
583
584  return 1;
585}
586
587/// computeRegisterProperties - Once all of the register classes are added,
588/// this allows us to compute derived properties we expose.
589void TargetLowering::computeRegisterProperties() {
590  assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
591         "Too many value types for ValueTypeActions to hold!");
592
593  // Everything defaults to needing one register.
594  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
595    NumRegistersForVT[i] = 1;
596    RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
597  }
598  // ...except isVoid, which doesn't need any registers.
599  NumRegistersForVT[MVT::isVoid] = 0;
600
601  // Find the largest integer register class.
602  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
603  for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
604    assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
605
606  // Every integer value type larger than this largest register takes twice as
607  // many registers to represent as the previous ValueType.
608  for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
609    EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
610    if (!ExpandedVT.isInteger())
611      break;
612    NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
613    RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
614    TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
615    ValueTypeActions.setTypeAction(ExpandedVT, Expand);
616  }
617
618  // Inspect all of the ValueType's smaller than the largest integer
619  // register to see which ones need promotion.
620  unsigned LegalIntReg = LargestIntReg;
621  for (unsigned IntReg = LargestIntReg - 1;
622       IntReg >= (unsigned)MVT::i1; --IntReg) {
623    EVT IVT = (MVT::SimpleValueType)IntReg;
624    if (isTypeLegal(IVT)) {
625      LegalIntReg = IntReg;
626    } else {
627      RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
628        (MVT::SimpleValueType)LegalIntReg;
629      ValueTypeActions.setTypeAction(IVT, Promote);
630    }
631  }
632
633  // ppcf128 type is really two f64's.
634  if (!isTypeLegal(MVT::ppcf128)) {
635    NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
636    RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
637    TransformToType[MVT::ppcf128] = MVT::f64;
638    ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
639  }
640
641  // Decide how to handle f64. If the target does not have native f64 support,
642  // expand it to i64 and we will be generating soft float library calls.
643  if (!isTypeLegal(MVT::f64)) {
644    NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
645    RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
646    TransformToType[MVT::f64] = MVT::i64;
647    ValueTypeActions.setTypeAction(MVT::f64, Expand);
648  }
649
650  // Decide how to handle f32. If the target does not have native support for
651  // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
652  if (!isTypeLegal(MVT::f32)) {
653    if (isTypeLegal(MVT::f64)) {
654      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
655      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
656      TransformToType[MVT::f32] = MVT::f64;
657      ValueTypeActions.setTypeAction(MVT::f32, Promote);
658    } else {
659      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
660      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
661      TransformToType[MVT::f32] = MVT::i32;
662      ValueTypeActions.setTypeAction(MVT::f32, Expand);
663    }
664  }
665
666  // Loop over all of the vector value types to see which need transformations.
667  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
668       i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
669    MVT VT = (MVT::SimpleValueType)i;
670    if (!isTypeLegal(VT)) {
671      MVT IntermediateVT;
672      EVT RegisterVT;
673      unsigned NumIntermediates;
674      NumRegistersForVT[i] =
675        getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
676                                  RegisterVT, this);
677      RegisterTypeForVT[i] = RegisterVT;
678
679      // Determine if there is a legal wider type.
680      bool IsLegalWiderType = false;
681      EVT EltVT = VT.getVectorElementType();
682      unsigned NElts = VT.getVectorNumElements();
683      for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
684        EVT SVT = (MVT::SimpleValueType)nVT;
685        if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
686            SVT.getVectorNumElements() > NElts) {
687          TransformToType[i] = SVT;
688          ValueTypeActions.setTypeAction(VT, Promote);
689          IsLegalWiderType = true;
690          break;
691        }
692      }
693      if (!IsLegalWiderType) {
694        EVT NVT = VT.getPow2VectorType();
695        if (NVT == VT) {
696          // Type is already a power of 2.  The default action is to split.
697          TransformToType[i] = MVT::Other;
698          ValueTypeActions.setTypeAction(VT, Expand);
699        } else {
700          TransformToType[i] = NVT;
701          ValueTypeActions.setTypeAction(VT, Promote);
702        }
703      }
704    }
705  }
706}
707
708const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
709  return NULL;
710}
711
712
713MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
714  return PointerTy.SimpleTy;
715}
716
717/// getVectorTypeBreakdown - Vector types are broken down into some number of
718/// legal first class types.  For example, MVT::v8f32 maps to 2 MVT::v4f32
719/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
720/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
721///
722/// This method returns the number of registers needed, and the VT for each
723/// register.  It also returns the VT and quantity of the intermediate values
724/// before they are promoted/expanded.
725///
726unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
727                                                EVT &IntermediateVT,
728                                                unsigned &NumIntermediates,
729                                                EVT &RegisterVT) const {
730  // Figure out the right, legal destination reg to copy into.
731  unsigned NumElts = VT.getVectorNumElements();
732  EVT EltTy = VT.getVectorElementType();
733
734  unsigned NumVectorRegs = 1;
735
736  // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally we
737  // could break down into LHS/RHS like LegalizeDAG does.
738  if (!isPowerOf2_32(NumElts)) {
739    NumVectorRegs = NumElts;
740    NumElts = 1;
741  }
742
743  // Divide the input until we get to a supported size.  This will always
744  // end with a scalar if the target doesn't support vectors.
745  while (NumElts > 1 && !isTypeLegal(
746                                   EVT::getVectorVT(Context, EltTy, NumElts))) {
747    NumElts >>= 1;
748    NumVectorRegs <<= 1;
749  }
750
751  NumIntermediates = NumVectorRegs;
752
753  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
754  if (!isTypeLegal(NewVT))
755    NewVT = EltTy;
756  IntermediateVT = NewVT;
757
758  EVT DestVT = getRegisterType(Context, NewVT);
759  RegisterVT = DestVT;
760  if (DestVT.bitsLT(NewVT)) {
761    // Value is expanded, e.g. i64 -> i16.
762    return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
763  } else {
764    // Otherwise, promotion or legal types use the same number of registers as
765    // the vector decimated to the appropriate level.
766    return NumVectorRegs;
767  }
768
769  return 1;
770}
771
772/// getWidenVectorType: given a vector type, returns the type to widen to
773/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
774/// If there is no vector type that we want to widen to, returns MVT::Other
775/// When and where to widen is target dependent based on the cost of
776/// scalarizing vs using the wider vector type.
777EVT TargetLowering::getWidenVectorType(EVT VT) const {
778  assert(VT.isVector());
779  if (isTypeLegal(VT))
780    return VT;
781
782  // Default is not to widen until moved to LegalizeTypes
783  return MVT::Other;
784}
785
786/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
787/// function arguments in the caller parameter area.  This is the actual
788/// alignment, not its logarithm.
789unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
790  return TD->getCallFrameTypeAlignment(Ty);
791}
792
793SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
794                                                 SelectionDAG &DAG) const {
795  if (usesGlobalOffsetTable())
796    return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
797  return Table;
798}
799
800bool
801TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
802  // Assume that everything is safe in static mode.
803  if (getTargetMachine().getRelocationModel() == Reloc::Static)
804    return true;
805
806  // In dynamic-no-pic mode, assume that known defined values are safe.
807  if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
808      GA &&
809      !GA->getGlobal()->isDeclaration() &&
810      !GA->getGlobal()->isWeakForLinker())
811    return true;
812
813  // Otherwise assume nothing is safe.
814  return false;
815}
816
817//===----------------------------------------------------------------------===//
818//  Optimization Methods
819//===----------------------------------------------------------------------===//
820
821/// ShrinkDemandedConstant - Check to see if the specified operand of the
822/// specified instruction is a constant integer.  If so, check to see if there
823/// are any bits set in the constant that are not demanded.  If so, shrink the
824/// constant and return true.
825bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
826                                                        const APInt &Demanded) {
827  DebugLoc dl = Op.getDebugLoc();
828
829  // FIXME: ISD::SELECT, ISD::SELECT_CC
830  switch (Op.getOpcode()) {
831  default: break;
832  case ISD::XOR:
833  case ISD::AND:
834  case ISD::OR: {
835    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
836    if (!C) return false;
837
838    if (Op.getOpcode() == ISD::XOR &&
839        (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
840      return false;
841
842    // if we can expand it to have all bits set, do it
843    if (C->getAPIntValue().intersects(~Demanded)) {
844      EVT VT = Op.getValueType();
845      SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
846                                DAG.getConstant(Demanded &
847                                                C->getAPIntValue(),
848                                                VT));
849      return CombineTo(Op, New);
850    }
851
852    break;
853  }
854  }
855
856  return false;
857}
858
859/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
860/// casts are free.  This uses isZExtFree and ZERO_EXTEND for the widening
861/// cast, but it could be generalized for targets with other types of
862/// implicit widening casts.
863bool
864TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
865                                                    unsigned BitWidth,
866                                                    const APInt &Demanded,
867                                                    DebugLoc dl) {
868  assert(Op.getNumOperands() == 2 &&
869         "ShrinkDemandedOp only supports binary operators!");
870  assert(Op.getNode()->getNumValues() == 1 &&
871         "ShrinkDemandedOp only supports nodes with one result!");
872
873  // Don't do this if the node has another user, which may require the
874  // full value.
875  if (!Op.getNode()->hasOneUse())
876    return false;
877
878  // Search for the smallest integer type with free casts to and from
879  // Op's type. For expedience, just check power-of-2 integer types.
880  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
881  unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
882  if (!isPowerOf2_32(SmallVTBits))
883    SmallVTBits = NextPowerOf2(SmallVTBits);
884  for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
885    EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
886    if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
887        TLI.isZExtFree(SmallVT, Op.getValueType())) {
888      // We found a type with free casts.
889      SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
890                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
891                                          Op.getNode()->getOperand(0)),
892                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
893                                          Op.getNode()->getOperand(1)));
894      SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
895      return CombineTo(Op, Z);
896    }
897  }
898  return false;
899}
900
901/// SimplifyDemandedBits - Look at Op.  At this point, we know that only the
902/// DemandedMask bits of the result of Op are ever used downstream.  If we can
903/// use this information to simplify Op, create a new simplified DAG node and
904/// return true, returning the original and new nodes in Old and New. Otherwise,
905/// analyze the expression and return a mask of KnownOne and KnownZero bits for
906/// the expression (used to simplify the caller).  The KnownZero/One bits may
907/// only be accurate for those bits in the DemandedMask.
908bool TargetLowering::SimplifyDemandedBits(SDValue Op,
909                                          const APInt &DemandedMask,
910                                          APInt &KnownZero,
911                                          APInt &KnownOne,
912                                          TargetLoweringOpt &TLO,
913                                          unsigned Depth) const {
914  unsigned BitWidth = DemandedMask.getBitWidth();
915  assert(Op.getValueSizeInBits() == BitWidth &&
916         "Mask size mismatches value type size!");
917  APInt NewMask = DemandedMask;
918  DebugLoc dl = Op.getDebugLoc();
919
920  // Don't know anything.
921  KnownZero = KnownOne = APInt(BitWidth, 0);
922
923  // Other users may use these bits.
924  if (!Op.getNode()->hasOneUse()) {
925    if (Depth != 0) {
926      // If not at the root, Just compute the KnownZero/KnownOne bits to
927      // simplify things downstream.
928      TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
929      return false;
930    }
931    // If this is the root being simplified, allow it to have multiple uses,
932    // just set the NewMask to all bits.
933    NewMask = APInt::getAllOnesValue(BitWidth);
934  } else if (DemandedMask == 0) {
935    // Not demanding any bits from Op.
936    if (Op.getOpcode() != ISD::UNDEF)
937      return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
938    return false;
939  } else if (Depth == 6) {        // Limit search depth.
940    return false;
941  }
942
943  APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
944  switch (Op.getOpcode()) {
945  case ISD::Constant:
946    // We know all of the bits for a constant!
947    KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
948    KnownZero = ~KnownOne & NewMask;
949    return false;   // Don't fall through, will infinitely loop.
950  case ISD::AND:
951    // If the RHS is a constant, check to see if the LHS would be zero without
952    // using the bits from the RHS.  Below, we use knowledge about the RHS to
953    // simplify the LHS, here we're using information from the LHS to simplify
954    // the RHS.
955    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
956      APInt LHSZero, LHSOne;
957      TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
958                                LHSZero, LHSOne, Depth+1);
959      // If the LHS already has zeros where RHSC does, this and is dead.
960      if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
961        return TLO.CombineTo(Op, Op.getOperand(0));
962      // If any of the set bits in the RHS are known zero on the LHS, shrink
963      // the constant.
964      if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
965        return true;
966    }
967
968    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
969                             KnownOne, TLO, Depth+1))
970      return true;
971    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
972    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
973                             KnownZero2, KnownOne2, TLO, Depth+1))
974      return true;
975    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
976
977    // If all of the demanded bits are known one on one side, return the other.
978    // These bits cannot contribute to the result of the 'and'.
979    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
980      return TLO.CombineTo(Op, Op.getOperand(0));
981    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
982      return TLO.CombineTo(Op, Op.getOperand(1));
983    // If all of the demanded bits in the inputs are known zeros, return zero.
984    if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
985      return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
986    // If the RHS is a constant, see if we can simplify it.
987    if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
988      return true;
989    // If the operation can be done in a smaller type, do so.
990    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
991      return true;
992
993    // Output known-1 bits are only known if set in both the LHS & RHS.
994    KnownOne &= KnownOne2;
995    // Output known-0 are known to be clear if zero in either the LHS | RHS.
996    KnownZero |= KnownZero2;
997    break;
998  case ISD::OR:
999    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1000                             KnownOne, TLO, Depth+1))
1001      return true;
1002    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1003    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1004                             KnownZero2, KnownOne2, TLO, Depth+1))
1005      return true;
1006    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1007
1008    // If all of the demanded bits are known zero on one side, return the other.
1009    // These bits cannot contribute to the result of the 'or'.
1010    if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1011      return TLO.CombineTo(Op, Op.getOperand(0));
1012    if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1013      return TLO.CombineTo(Op, Op.getOperand(1));
1014    // If all of the potentially set bits on one side are known to be set on
1015    // the other side, just use the 'other' side.
1016    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1017      return TLO.CombineTo(Op, Op.getOperand(0));
1018    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1019      return TLO.CombineTo(Op, Op.getOperand(1));
1020    // If the RHS is a constant, see if we can simplify it.
1021    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1022      return true;
1023    // If the operation can be done in a smaller type, do so.
1024    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1025      return true;
1026
1027    // Output known-0 bits are only known if clear in both the LHS & RHS.
1028    KnownZero &= KnownZero2;
1029    // Output known-1 are known to be set if set in either the LHS | RHS.
1030    KnownOne |= KnownOne2;
1031    break;
1032  case ISD::XOR:
1033    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1034                             KnownOne, TLO, Depth+1))
1035      return true;
1036    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1037    if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1038                             KnownOne2, TLO, Depth+1))
1039      return true;
1040    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1041
1042    // If all of the demanded bits are known zero on one side, return the other.
1043    // These bits cannot contribute to the result of the 'xor'.
1044    if ((KnownZero & NewMask) == NewMask)
1045      return TLO.CombineTo(Op, Op.getOperand(0));
1046    if ((KnownZero2 & NewMask) == NewMask)
1047      return TLO.CombineTo(Op, Op.getOperand(1));
1048    // If the operation can be done in a smaller type, do so.
1049    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1050      return true;
1051
1052    // If all of the unknown bits are known to be zero on one side or the other
1053    // (but not both) turn this into an *inclusive* or.
1054    //    e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1055    if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1056      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1057                                               Op.getOperand(0),
1058                                               Op.getOperand(1)));
1059
1060    // Output known-0 bits are known if clear or set in both the LHS & RHS.
1061    KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1062    // Output known-1 are known to be set if set in only one of the LHS, RHS.
1063    KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1064
1065    // If all of the demanded bits on one side are known, and all of the set
1066    // bits on that side are also known to be set on the other side, turn this
1067    // into an AND, as we know the bits will be cleared.
1068    //    e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1069    if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1070      if ((KnownOne & KnownOne2) == KnownOne) {
1071        EVT VT = Op.getValueType();
1072        SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1073        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1074                                                 Op.getOperand(0), ANDC));
1075      }
1076    }
1077
1078    // If the RHS is a constant, see if we can simplify it.
1079    // for XOR, we prefer to force bits to 1 if they will make a -1.
1080    // if we can't force bits, try to shrink constant
1081    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1082      APInt Expanded = C->getAPIntValue() | (~NewMask);
1083      // if we can expand it to have all bits set, do it
1084      if (Expanded.isAllOnesValue()) {
1085        if (Expanded != C->getAPIntValue()) {
1086          EVT VT = Op.getValueType();
1087          SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1088                                          TLO.DAG.getConstant(Expanded, VT));
1089          return TLO.CombineTo(Op, New);
1090        }
1091        // if it already has all the bits set, nothing to change
1092        // but don't shrink either!
1093      } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1094        return true;
1095      }
1096    }
1097
1098    KnownZero = KnownZeroOut;
1099    KnownOne  = KnownOneOut;
1100    break;
1101  case ISD::SELECT:
1102    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1103                             KnownOne, TLO, Depth+1))
1104      return true;
1105    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1106                             KnownOne2, TLO, Depth+1))
1107      return true;
1108    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1109    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1110
1111    // If the operands are constants, see if we can simplify them.
1112    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1113      return true;
1114
1115    // Only known if known in both the LHS and RHS.
1116    KnownOne &= KnownOne2;
1117    KnownZero &= KnownZero2;
1118    break;
1119  case ISD::SELECT_CC:
1120    if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1121                             KnownOne, TLO, Depth+1))
1122      return true;
1123    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1124                             KnownOne2, TLO, Depth+1))
1125      return true;
1126    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1127    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1128
1129    // If the operands are constants, see if we can simplify them.
1130    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1131      return true;
1132
1133    // Only known if known in both the LHS and RHS.
1134    KnownOne &= KnownOne2;
1135    KnownZero &= KnownZero2;
1136    break;
1137  case ISD::SHL:
1138    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1139      unsigned ShAmt = SA->getZExtValue();
1140      SDValue InOp = Op.getOperand(0);
1141
1142      // If the shift count is an invalid immediate, don't do anything.
1143      if (ShAmt >= BitWidth)
1144        break;
1145
1146      // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1147      // single shift.  We can do this if the bottom bits (which are shifted
1148      // out) are never demanded.
1149      if (InOp.getOpcode() == ISD::SRL &&
1150          isa<ConstantSDNode>(InOp.getOperand(1))) {
1151        if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1152          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1153          unsigned Opc = ISD::SHL;
1154          int Diff = ShAmt-C1;
1155          if (Diff < 0) {
1156            Diff = -Diff;
1157            Opc = ISD::SRL;
1158          }
1159
1160          SDValue NewSA =
1161            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1162          EVT VT = Op.getValueType();
1163          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1164                                                   InOp.getOperand(0), NewSA));
1165        }
1166      }
1167
1168      if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
1169                               KnownZero, KnownOne, TLO, Depth+1))
1170        return true;
1171      KnownZero <<= SA->getZExtValue();
1172      KnownOne  <<= SA->getZExtValue();
1173      // low bits known zero.
1174      KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1175    }
1176    break;
1177  case ISD::SRL:
1178    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1179      EVT VT = Op.getValueType();
1180      unsigned ShAmt = SA->getZExtValue();
1181      unsigned VTSize = VT.getSizeInBits();
1182      SDValue InOp = Op.getOperand(0);
1183
1184      // If the shift count is an invalid immediate, don't do anything.
1185      if (ShAmt >= BitWidth)
1186        break;
1187
1188      // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1189      // single shift.  We can do this if the top bits (which are shifted out)
1190      // are never demanded.
1191      if (InOp.getOpcode() == ISD::SHL &&
1192          isa<ConstantSDNode>(InOp.getOperand(1))) {
1193        if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1194          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1195          unsigned Opc = ISD::SRL;
1196          int Diff = ShAmt-C1;
1197          if (Diff < 0) {
1198            Diff = -Diff;
1199            Opc = ISD::SHL;
1200          }
1201
1202          SDValue NewSA =
1203            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1204          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1205                                                   InOp.getOperand(0), NewSA));
1206        }
1207      }
1208
1209      // Compute the new bits that are at the top now.
1210      if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1211                               KnownZero, KnownOne, TLO, Depth+1))
1212        return true;
1213      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1214      KnownZero = KnownZero.lshr(ShAmt);
1215      KnownOne  = KnownOne.lshr(ShAmt);
1216
1217      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1218      KnownZero |= HighBits;  // High bits known zero.
1219    }
1220    break;
1221  case ISD::SRA:
1222    // If this is an arithmetic shift right and only the low-bit is set, we can
1223    // always convert this into a logical shr, even if the shift amount is
1224    // variable.  The low bit of the shift cannot be an input sign bit unless
1225    // the shift amount is >= the size of the datatype, which is undefined.
1226    if (DemandedMask == 1)
1227      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1228                                               Op.getOperand(0), Op.getOperand(1)));
1229
1230    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1231      EVT VT = Op.getValueType();
1232      unsigned ShAmt = SA->getZExtValue();
1233
1234      // If the shift count is an invalid immediate, don't do anything.
1235      if (ShAmt >= BitWidth)
1236        break;
1237
1238      APInt InDemandedMask = (NewMask << ShAmt);
1239
1240      // If any of the demanded bits are produced by the sign extension, we also
1241      // demand the input sign bit.
1242      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1243      if (HighBits.intersects(NewMask))
1244        InDemandedMask |= APInt::getSignBit(VT.getSizeInBits());
1245
1246      if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1247                               KnownZero, KnownOne, TLO, Depth+1))
1248        return true;
1249      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1250      KnownZero = KnownZero.lshr(ShAmt);
1251      KnownOne  = KnownOne.lshr(ShAmt);
1252
1253      // Handle the sign bit, adjusted to where it is now in the mask.
1254      APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1255
1256      // If the input sign bit is known to be zero, or if none of the top bits
1257      // are demanded, turn this into an unsigned shift right.
1258      if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1259        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1260                                                 Op.getOperand(0),
1261                                                 Op.getOperand(1)));
1262      } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1263        KnownOne |= HighBits;
1264      }
1265    }
1266    break;
1267  case ISD::SIGN_EXTEND_INREG: {
1268    EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1269
1270    // Sign extension.  Compute the demanded bits in the result that are not
1271    // present in the input.
1272    APInt NewBits = APInt::getHighBitsSet(BitWidth,
1273                                          BitWidth - EVT.getSizeInBits()) &
1274                    NewMask;
1275
1276    // If none of the extended bits are demanded, eliminate the sextinreg.
1277    if (NewBits == 0)
1278      return TLO.CombineTo(Op, Op.getOperand(0));
1279
1280    APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits());
1281    InSignBit.zext(BitWidth);
1282    APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth,
1283                                                   EVT.getSizeInBits()) &
1284                              NewMask;
1285
1286    // Since the sign extended bits are demanded, we know that the sign
1287    // bit is demanded.
1288    InputDemandedBits |= InSignBit;
1289
1290    if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1291                             KnownZero, KnownOne, TLO, Depth+1))
1292      return true;
1293    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1294
1295    // If the sign bit of the input is known set or clear, then we know the
1296    // top bits of the result.
1297
1298    // If the input sign bit is known zero, convert this into a zero extension.
1299    if (KnownZero.intersects(InSignBit))
1300      return TLO.CombineTo(Op,
1301                           TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1302
1303    if (KnownOne.intersects(InSignBit)) {    // Input sign bit known set
1304      KnownOne |= NewBits;
1305      KnownZero &= ~NewBits;
1306    } else {                       // Input sign bit unknown
1307      KnownZero &= ~NewBits;
1308      KnownOne &= ~NewBits;
1309    }
1310    break;
1311  }
1312  case ISD::ZERO_EXTEND: {
1313    unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1314    APInt InMask = NewMask;
1315    InMask.trunc(OperandBitWidth);
1316
1317    // If none of the top bits are demanded, convert this into an any_extend.
1318    APInt NewBits =
1319      APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1320    if (!NewBits.intersects(NewMask))
1321      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1322                                               Op.getValueType(),
1323                                               Op.getOperand(0)));
1324
1325    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1326                             KnownZero, KnownOne, TLO, Depth+1))
1327      return true;
1328    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1329    KnownZero.zext(BitWidth);
1330    KnownOne.zext(BitWidth);
1331    KnownZero |= NewBits;
1332    break;
1333  }
1334  case ISD::SIGN_EXTEND: {
1335    EVT InVT = Op.getOperand(0).getValueType();
1336    unsigned InBits = InVT.getSizeInBits();
1337    APInt InMask    = APInt::getLowBitsSet(BitWidth, InBits);
1338    APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1339    APInt NewBits   = ~InMask & NewMask;
1340
1341    // If none of the top bits are demanded, convert this into an any_extend.
1342    if (NewBits == 0)
1343      return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1344                                              Op.getValueType(),
1345                                              Op.getOperand(0)));
1346
1347    // Since some of the sign extended bits are demanded, we know that the sign
1348    // bit is demanded.
1349    APInt InDemandedBits = InMask & NewMask;
1350    InDemandedBits |= InSignBit;
1351    InDemandedBits.trunc(InBits);
1352
1353    if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1354                             KnownOne, TLO, Depth+1))
1355      return true;
1356    KnownZero.zext(BitWidth);
1357    KnownOne.zext(BitWidth);
1358
1359    // If the sign bit is known zero, convert this to a zero extend.
1360    if (KnownZero.intersects(InSignBit))
1361      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1362                                               Op.getValueType(),
1363                                               Op.getOperand(0)));
1364
1365    // If the sign bit is known one, the top bits match.
1366    if (KnownOne.intersects(InSignBit)) {
1367      KnownOne  |= NewBits;
1368      KnownZero &= ~NewBits;
1369    } else {   // Otherwise, top bits aren't known.
1370      KnownOne  &= ~NewBits;
1371      KnownZero &= ~NewBits;
1372    }
1373    break;
1374  }
1375  case ISD::ANY_EXTEND: {
1376    unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1377    APInt InMask = NewMask;
1378    InMask.trunc(OperandBitWidth);
1379    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1380                             KnownZero, KnownOne, TLO, Depth+1))
1381      return true;
1382    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1383    KnownZero.zext(BitWidth);
1384    KnownOne.zext(BitWidth);
1385    break;
1386  }
1387  case ISD::TRUNCATE: {
1388    // Simplify the input, using demanded bit information, and compute the known
1389    // zero/one bits live out.
1390    APInt TruncMask = NewMask;
1391    TruncMask.zext(Op.getOperand(0).getValueSizeInBits());
1392    if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1393                             KnownZero, KnownOne, TLO, Depth+1))
1394      return true;
1395    KnownZero.trunc(BitWidth);
1396    KnownOne.trunc(BitWidth);
1397
1398    // If the input is only used by this truncate, see if we can shrink it based
1399    // on the known demanded bits.
1400    if (Op.getOperand(0).getNode()->hasOneUse()) {
1401      SDValue In = Op.getOperand(0);
1402      unsigned InBitWidth = In.getValueSizeInBits();
1403      switch (In.getOpcode()) {
1404      default: break;
1405      case ISD::SRL:
1406        // Shrink SRL by a constant if none of the high bits shifted in are
1407        // demanded.
1408        if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
1409          APInt HighBits = APInt::getHighBitsSet(InBitWidth,
1410                                                 InBitWidth - BitWidth);
1411          HighBits = HighBits.lshr(ShAmt->getZExtValue());
1412          HighBits.trunc(BitWidth);
1413
1414          if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1415            // None of the shifted in bits are needed.  Add a truncate of the
1416            // shift input, then shift it.
1417            SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1418                                                 Op.getValueType(),
1419                                                 In.getOperand(0));
1420            return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1421                                                     Op.getValueType(),
1422                                                     NewTrunc,
1423                                                     In.getOperand(1)));
1424          }
1425        }
1426        break;
1427      }
1428    }
1429
1430    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1431    break;
1432  }
1433  case ISD::AssertZext: {
1434    EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1435    APInt InMask = APInt::getLowBitsSet(BitWidth,
1436                                        VT.getSizeInBits());
1437    if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
1438                             KnownZero, KnownOne, TLO, Depth+1))
1439      return true;
1440    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1441    KnownZero |= ~InMask & NewMask;
1442    break;
1443  }
1444  case ISD::BIT_CONVERT:
1445#if 0
1446    // If this is an FP->Int bitcast and if the sign bit is the only thing that
1447    // is demanded, turn this into a FGETSIGN.
1448    if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
1449        MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1450        !MVT::isVector(Op.getOperand(0).getValueType())) {
1451      // Only do this xform if FGETSIGN is valid or if before legalize.
1452      if (!TLO.AfterLegalize ||
1453          isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1454        // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1455        // place.  We expect the SHL to be eliminated by other optimizations.
1456        SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1457                                         Op.getOperand(0));
1458        unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1459        SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1460        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1461                                                 Sign, ShAmt));
1462      }
1463    }
1464#endif
1465    break;
1466  case ISD::ADD:
1467  case ISD::MUL:
1468  case ISD::SUB: {
1469    // Add, Sub, and Mul don't demand any bits in positions beyond that
1470    // of the highest bit demanded of them.
1471    APInt LoMask = APInt::getLowBitsSet(BitWidth,
1472                                        BitWidth - NewMask.countLeadingZeros());
1473    if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1474                             KnownOne2, TLO, Depth+1))
1475      return true;
1476    if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1477                             KnownOne2, TLO, Depth+1))
1478      return true;
1479    // See if the operation should be performed at a smaller bit width.
1480    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1481      return true;
1482  }
1483  // FALL THROUGH
1484  default:
1485    // Just use ComputeMaskedBits to compute output bits.
1486    TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1487    break;
1488  }
1489
1490  // If we know the value of all of the demanded bits, return this as a
1491  // constant.
1492  if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1493    return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1494
1495  return false;
1496}
1497
1498/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1499/// in Mask are known to be either zero or one and return them in the
1500/// KnownZero/KnownOne bitsets.
1501void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1502                                                    const APInt &Mask,
1503                                                    APInt &KnownZero,
1504                                                    APInt &KnownOne,
1505                                                    const SelectionDAG &DAG,
1506                                                    unsigned Depth) const {
1507  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1508          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1509          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1510          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1511         "Should use MaskedValueIsZero if you don't know whether Op"
1512         " is a target node!");
1513  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1514}
1515
1516/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1517/// targets that want to expose additional information about sign bits to the
1518/// DAG Combiner.
1519unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1520                                                         unsigned Depth) const {
1521  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1522          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1523          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1524          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1525         "Should use ComputeNumSignBits if you don't know whether Op"
1526         " is a target node!");
1527  return 1;
1528}
1529
1530/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1531/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1532/// determine which bit is set.
1533///
1534static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1535  // A left-shift of a constant one will have exactly one bit set, because
1536  // shifting the bit off the end is undefined.
1537  if (Val.getOpcode() == ISD::SHL)
1538    if (ConstantSDNode *C =
1539         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1540      if (C->getAPIntValue() == 1)
1541        return true;
1542
1543  // Similarly, a right-shift of a constant sign-bit will have exactly
1544  // one bit set.
1545  if (Val.getOpcode() == ISD::SRL)
1546    if (ConstantSDNode *C =
1547         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1548      if (C->getAPIntValue().isSignBit())
1549        return true;
1550
1551  // More could be done here, though the above checks are enough
1552  // to handle some common cases.
1553
1554  // Fall back to ComputeMaskedBits to catch other known cases.
1555  EVT OpVT = Val.getValueType();
1556  unsigned BitWidth = OpVT.getSizeInBits();
1557  APInt Mask = APInt::getAllOnesValue(BitWidth);
1558  APInt KnownZero, KnownOne;
1559  DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1560  return (KnownZero.countPopulation() == BitWidth - 1) &&
1561         (KnownOne.countPopulation() == 1);
1562}
1563
1564/// SimplifySetCC - Try to simplify a setcc built with the specified operands
1565/// and cc. If it is unable to simplify it, return a null SDValue.
1566SDValue
1567TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1568                              ISD::CondCode Cond, bool foldBooleans,
1569                              DAGCombinerInfo &DCI, DebugLoc dl) const {
1570  SelectionDAG &DAG = DCI.DAG;
1571  LLVMContext &Context = *DAG.getContext();
1572
1573  // These setcc operations always fold.
1574  switch (Cond) {
1575  default: break;
1576  case ISD::SETFALSE:
1577  case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1578  case ISD::SETTRUE:
1579  case ISD::SETTRUE2:  return DAG.getConstant(1, VT);
1580  }
1581
1582  if (isa<ConstantSDNode>(N0.getNode())) {
1583    // Ensure that the constant occurs on the RHS, and fold constant
1584    // comparisons.
1585    return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1586  }
1587
1588  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1589    const APInt &C1 = N1C->getAPIntValue();
1590
1591    // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1592    // equality comparison, then we're just comparing whether X itself is
1593    // zero.
1594    if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1595        N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1596        N0.getOperand(1).getOpcode() == ISD::Constant) {
1597      unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
1598      if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1599          ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1600        if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1601          // (srl (ctlz x), 5) == 0  -> X != 0
1602          // (srl (ctlz x), 5) != 1  -> X != 0
1603          Cond = ISD::SETNE;
1604        } else {
1605          // (srl (ctlz x), 5) != 0  -> X == 0
1606          // (srl (ctlz x), 5) == 1  -> X == 0
1607          Cond = ISD::SETEQ;
1608        }
1609        SDValue Zero = DAG.getConstant(0, N0.getValueType());
1610        return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1611                            Zero, Cond);
1612      }
1613    }
1614
1615    // If the LHS is '(and load, const)', the RHS is 0,
1616    // the test is for equality or unsigned, and all 1 bits of the const are
1617    // in the same partial word, see if we can shorten the load.
1618    if (DCI.isBeforeLegalize() &&
1619        N0.getOpcode() == ISD::AND && C1 == 0 &&
1620        N0.getNode()->hasOneUse() &&
1621        isa<LoadSDNode>(N0.getOperand(0)) &&
1622        N0.getOperand(0).getNode()->hasOneUse() &&
1623        isa<ConstantSDNode>(N0.getOperand(1))) {
1624      LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1625      uint64_t bestMask = 0;
1626      unsigned bestWidth = 0, bestOffset = 0;
1627      if (!Lod->isVolatile() && Lod->isUnindexed() &&
1628          // FIXME: This uses getZExtValue() below so it only works on i64 and
1629          // below.
1630          N0.getValueType().getSizeInBits() <= 64) {
1631        unsigned origWidth = N0.getValueType().getSizeInBits();
1632        // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1633        // 8 bits, but have to be careful...
1634        if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1635          origWidth = Lod->getMemoryVT().getSizeInBits();
1636        uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
1637        for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1638          uint64_t newMask = (1ULL << width) - 1;
1639          for (unsigned offset=0; offset<origWidth/width; offset++) {
1640            if ((newMask & Mask) == Mask) {
1641              if (!TD->isLittleEndian())
1642                bestOffset = (origWidth/width - offset - 1) * (width/8);
1643              else
1644                bestOffset = (uint64_t)offset * (width/8);
1645              bestMask = Mask >> (offset * (width/8) * 8);
1646              bestWidth = width;
1647              break;
1648            }
1649            newMask = newMask << width;
1650          }
1651        }
1652      }
1653      if (bestWidth) {
1654        EVT newVT = EVT::getIntegerVT(Context, bestWidth);
1655        if (newVT.isRound()) {
1656          EVT PtrType = Lod->getOperand(1).getValueType();
1657          SDValue Ptr = Lod->getBasePtr();
1658          if (bestOffset != 0)
1659            Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1660                              DAG.getConstant(bestOffset, PtrType));
1661          unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1662          SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1663                                        Lod->getSrcValue(),
1664                                        Lod->getSrcValueOffset() + bestOffset,
1665                                        false, NewAlign);
1666          return DAG.getSetCC(dl, VT,
1667                              DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1668                                          DAG.getConstant(bestMask, newVT)),
1669                              DAG.getConstant(0LL, newVT), Cond);
1670        }
1671      }
1672    }
1673
1674    // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1675    if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1676      unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1677
1678      // If the comparison constant has bits in the upper part, the
1679      // zero-extended value could never match.
1680      if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1681                                              C1.getBitWidth() - InSize))) {
1682        switch (Cond) {
1683        case ISD::SETUGT:
1684        case ISD::SETUGE:
1685        case ISD::SETEQ: return DAG.getConstant(0, VT);
1686        case ISD::SETULT:
1687        case ISD::SETULE:
1688        case ISD::SETNE: return DAG.getConstant(1, VT);
1689        case ISD::SETGT:
1690        case ISD::SETGE:
1691          // True if the sign bit of C1 is set.
1692          return DAG.getConstant(C1.isNegative(), VT);
1693        case ISD::SETLT:
1694        case ISD::SETLE:
1695          // True if the sign bit of C1 isn't set.
1696          return DAG.getConstant(C1.isNonNegative(), VT);
1697        default:
1698          break;
1699        }
1700      }
1701
1702      // Otherwise, we can perform the comparison with the low bits.
1703      switch (Cond) {
1704      case ISD::SETEQ:
1705      case ISD::SETNE:
1706      case ISD::SETUGT:
1707      case ISD::SETUGE:
1708      case ISD::SETULT:
1709      case ISD::SETULE: {
1710        EVT newVT = N0.getOperand(0).getValueType();
1711        if (DCI.isBeforeLegalizeOps() ||
1712            (isOperationLegal(ISD::SETCC, newVT) &&
1713              getCondCodeAction(Cond, newVT)==Legal))
1714          return DAG.getSetCC(dl, VT, N0.getOperand(0),
1715                              DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1716                              Cond);
1717        break;
1718      }
1719      default:
1720        break;   // todo, be more careful with signed comparisons
1721      }
1722    } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1723                (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1724      EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1725      unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1726      EVT ExtDstTy = N0.getValueType();
1727      unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1728
1729      // If the extended part has any inconsistent bits, it cannot ever
1730      // compare equal.  In other words, they have to be all ones or all
1731      // zeros.
1732      APInt ExtBits =
1733        APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1734      if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1735        return DAG.getConstant(Cond == ISD::SETNE, VT);
1736
1737      SDValue ZextOp;
1738      EVT Op0Ty = N0.getOperand(0).getValueType();
1739      if (Op0Ty == ExtSrcTy) {
1740        ZextOp = N0.getOperand(0);
1741      } else {
1742        APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1743        ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1744                              DAG.getConstant(Imm, Op0Ty));
1745      }
1746      if (!DCI.isCalledByLegalizer())
1747        DCI.AddToWorklist(ZextOp.getNode());
1748      // Otherwise, make this a use of a zext.
1749      return DAG.getSetCC(dl, VT, ZextOp,
1750                          DAG.getConstant(C1 & APInt::getLowBitsSet(
1751                                                              ExtDstTyBits,
1752                                                              ExtSrcTyBits),
1753                                          ExtDstTy),
1754                          Cond);
1755    } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1756                (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1757
1758      // SETCC (SETCC), [0|1], [EQ|NE]  -> SETCC
1759      if (N0.getOpcode() == ISD::SETCC) {
1760        bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1);
1761        if (TrueWhenTrue)
1762          return N0;
1763
1764        // Invert the condition.
1765        ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1766        CC = ISD::getSetCCInverse(CC,
1767                                  N0.getOperand(0).getValueType().isInteger());
1768        return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1769      }
1770
1771      if ((N0.getOpcode() == ISD::XOR ||
1772            (N0.getOpcode() == ISD::AND &&
1773            N0.getOperand(0).getOpcode() == ISD::XOR &&
1774            N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1775          isa<ConstantSDNode>(N0.getOperand(1)) &&
1776          cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1777        // If this is (X^1) == 0/1, swap the RHS and eliminate the xor.  We
1778        // can only do this if the top bits are known zero.
1779        unsigned BitWidth = N0.getValueSizeInBits();
1780        if (DAG.MaskedValueIsZero(N0,
1781                                  APInt::getHighBitsSet(BitWidth,
1782                                                        BitWidth-1))) {
1783          // Okay, get the un-inverted input value.
1784          SDValue Val;
1785          if (N0.getOpcode() == ISD::XOR)
1786            Val = N0.getOperand(0);
1787          else {
1788            assert(N0.getOpcode() == ISD::AND &&
1789                    N0.getOperand(0).getOpcode() == ISD::XOR);
1790            // ((X^1)&1)^1 -> X & 1
1791            Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1792                              N0.getOperand(0).getOperand(0),
1793                              N0.getOperand(1));
1794          }
1795          return DAG.getSetCC(dl, VT, Val, N1,
1796                              Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1797        }
1798      }
1799    }
1800
1801    APInt MinVal, MaxVal;
1802    unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1803    if (ISD::isSignedIntSetCC(Cond)) {
1804      MinVal = APInt::getSignedMinValue(OperandBitSize);
1805      MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1806    } else {
1807      MinVal = APInt::getMinValue(OperandBitSize);
1808      MaxVal = APInt::getMaxValue(OperandBitSize);
1809    }
1810
1811    // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1812    if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1813      if (C1 == MinVal) return DAG.getConstant(1, VT);   // X >= MIN --> true
1814      // X >= C0 --> X > (C0-1)
1815      return DAG.getSetCC(dl, VT, N0,
1816                          DAG.getConstant(C1-1, N1.getValueType()),
1817                          (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1818    }
1819
1820    if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1821      if (C1 == MaxVal) return DAG.getConstant(1, VT);   // X <= MAX --> true
1822      // X <= C0 --> X < (C0+1)
1823      return DAG.getSetCC(dl, VT, N0,
1824                          DAG.getConstant(C1+1, N1.getValueType()),
1825                          (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1826    }
1827
1828    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1829      return DAG.getConstant(0, VT);      // X < MIN --> false
1830    if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1831      return DAG.getConstant(1, VT);      // X >= MIN --> true
1832    if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1833      return DAG.getConstant(0, VT);      // X > MAX --> false
1834    if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1835      return DAG.getConstant(1, VT);      // X <= MAX --> true
1836
1837    // Canonicalize setgt X, Min --> setne X, Min
1838    if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1839      return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1840    // Canonicalize setlt X, Max --> setne X, Max
1841    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1842      return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1843
1844    // If we have setult X, 1, turn it into seteq X, 0
1845    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1846      return DAG.getSetCC(dl, VT, N0,
1847                          DAG.getConstant(MinVal, N0.getValueType()),
1848                          ISD::SETEQ);
1849    // If we have setugt X, Max-1, turn it into seteq X, Max
1850    else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1851      return DAG.getSetCC(dl, VT, N0,
1852                          DAG.getConstant(MaxVal, N0.getValueType()),
1853                          ISD::SETEQ);
1854
1855    // If we have "setcc X, C0", check to see if we can shrink the immediate
1856    // by changing cc.
1857
1858    // SETUGT X, SINTMAX  -> SETLT X, 0
1859    if (Cond == ISD::SETUGT &&
1860        C1 == APInt::getSignedMaxValue(OperandBitSize))
1861      return DAG.getSetCC(dl, VT, N0,
1862                          DAG.getConstant(0, N1.getValueType()),
1863                          ISD::SETLT);
1864
1865    // SETULT X, SINTMIN  -> SETGT X, -1
1866    if (Cond == ISD::SETULT &&
1867        C1 == APInt::getSignedMinValue(OperandBitSize)) {
1868      SDValue ConstMinusOne =
1869          DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1870                          N1.getValueType());
1871      return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1872    }
1873
1874    // Fold bit comparisons when we can.
1875    if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1876        VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1877      if (ConstantSDNode *AndRHS =
1878                  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1879        EVT ShiftTy = DCI.isBeforeLegalize() ?
1880          getPointerTy() : getShiftAmountTy();
1881        if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
1882          // Perform the xform if the AND RHS is a single bit.
1883          if (isPowerOf2_64(AndRHS->getZExtValue())) {
1884            return DAG.getNode(ISD::SRL, dl, VT, N0,
1885                                DAG.getConstant(Log2_64(AndRHS->getZExtValue()),
1886                                                ShiftTy));
1887          }
1888        } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) {
1889          // (X & 8) == 8  -->  (X & 8) >> 3
1890          // Perform the xform if C1 is a single bit.
1891          if (C1.isPowerOf2()) {
1892            return DAG.getNode(ISD::SRL, dl, VT, N0,
1893                                DAG.getConstant(C1.logBase2(), ShiftTy));
1894          }
1895        }
1896      }
1897  }
1898
1899  if (isa<ConstantFPSDNode>(N0.getNode())) {
1900    // Constant fold or commute setcc.
1901    SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1902    if (O.getNode()) return O;
1903  } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1904    // If the RHS of an FP comparison is a constant, simplify it away in
1905    // some cases.
1906    if (CFP->getValueAPF().isNaN()) {
1907      // If an operand is known to be a nan, we can fold it.
1908      switch (ISD::getUnorderedFlavor(Cond)) {
1909      default: llvm_unreachable("Unknown flavor!");
1910      case 0:  // Known false.
1911        return DAG.getConstant(0, VT);
1912      case 1:  // Known true.
1913        return DAG.getConstant(1, VT);
1914      case 2:  // Undefined.
1915        return DAG.getUNDEF(VT);
1916      }
1917    }
1918
1919    // Otherwise, we know the RHS is not a NaN.  Simplify the node to drop the
1920    // constant if knowing that the operand is non-nan is enough.  We prefer to
1921    // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1922    // materialize 0.0.
1923    if (Cond == ISD::SETO || Cond == ISD::SETUO)
1924      return DAG.getSetCC(dl, VT, N0, N0, Cond);
1925
1926    // If the condition is not legal, see if we can find an equivalent one
1927    // which is legal.
1928    if (!isCondCodeLegal(Cond, N0.getValueType())) {
1929      // If the comparison was an awkward floating-point == or != and one of
1930      // the comparison operands is infinity or negative infinity, convert the
1931      // condition to a less-awkward <= or >=.
1932      if (CFP->getValueAPF().isInfinity()) {
1933        if (CFP->getValueAPF().isNegative()) {
1934          if (Cond == ISD::SETOEQ &&
1935              isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
1936            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1937          if (Cond == ISD::SETUEQ &&
1938              isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
1939            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1940          if (Cond == ISD::SETUNE &&
1941              isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
1942            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1943          if (Cond == ISD::SETONE &&
1944              isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
1945            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1946        } else {
1947          if (Cond == ISD::SETOEQ &&
1948              isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
1949            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1950          if (Cond == ISD::SETUEQ &&
1951              isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
1952            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1953          if (Cond == ISD::SETUNE &&
1954              isCondCodeLegal(ISD::SETULT, N0.getValueType()))
1955            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1956          if (Cond == ISD::SETONE &&
1957              isCondCodeLegal(ISD::SETULT, N0.getValueType()))
1958            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1959        }
1960      }
1961    }
1962  }
1963
1964  if (N0 == N1) {
1965    // We can always fold X == X for integer setcc's.
1966    if (N0.getValueType().isInteger())
1967      return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1968    unsigned UOF = ISD::getUnorderedFlavor(Cond);
1969    if (UOF == 2)   // FP operators that are undefined on NaNs.
1970      return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1971    if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1972      return DAG.getConstant(UOF, VT);
1973    // Otherwise, we can't fold it.  However, we can simplify it to SETUO/SETO
1974    // if it is not already.
1975    ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1976    if (NewCond != Cond)
1977      return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1978  }
1979
1980  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1981      N0.getValueType().isInteger()) {
1982    if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1983        N0.getOpcode() == ISD::XOR) {
1984      // Simplify (X+Y) == (X+Z) -->  Y == Z
1985      if (N0.getOpcode() == N1.getOpcode()) {
1986        if (N0.getOperand(0) == N1.getOperand(0))
1987          return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1988        if (N0.getOperand(1) == N1.getOperand(1))
1989          return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1990        if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1991          // If X op Y == Y op X, try other combinations.
1992          if (N0.getOperand(0) == N1.getOperand(1))
1993            return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1994                                Cond);
1995          if (N0.getOperand(1) == N1.getOperand(0))
1996            return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1997                                Cond);
1998        }
1999      }
2000
2001      if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2002        if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2003          // Turn (X+C1) == C2 --> X == C2-C1
2004          if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2005            return DAG.getSetCC(dl, VT, N0.getOperand(0),
2006                                DAG.getConstant(RHSC->getAPIntValue()-
2007                                                LHSR->getAPIntValue(),
2008                                N0.getValueType()), Cond);
2009          }
2010
2011          // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2012          if (N0.getOpcode() == ISD::XOR)
2013            // If we know that all of the inverted bits are zero, don't bother
2014            // performing the inversion.
2015            if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2016              return
2017                DAG.getSetCC(dl, VT, N0.getOperand(0),
2018                             DAG.getConstant(LHSR->getAPIntValue() ^
2019                                               RHSC->getAPIntValue(),
2020                                             N0.getValueType()),
2021                             Cond);
2022        }
2023
2024        // Turn (C1-X) == C2 --> X == C1-C2
2025        if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2026          if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2027            return
2028              DAG.getSetCC(dl, VT, N0.getOperand(1),
2029                           DAG.getConstant(SUBC->getAPIntValue() -
2030                                             RHSC->getAPIntValue(),
2031                                           N0.getValueType()),
2032                           Cond);
2033          }
2034        }
2035      }
2036
2037      // Simplify (X+Z) == X -->  Z == 0
2038      if (N0.getOperand(0) == N1)
2039        return DAG.getSetCC(dl, VT, N0.getOperand(1),
2040                        DAG.getConstant(0, N0.getValueType()), Cond);
2041      if (N0.getOperand(1) == N1) {
2042        if (DAG.isCommutativeBinOp(N0.getOpcode()))
2043          return DAG.getSetCC(dl, VT, N0.getOperand(0),
2044                          DAG.getConstant(0, N0.getValueType()), Cond);
2045        else if (N0.getNode()->hasOneUse()) {
2046          assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2047          // (Z-X) == X  --> Z == X<<1
2048          SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
2049                                     N1,
2050                                     DAG.getConstant(1, getShiftAmountTy()));
2051          if (!DCI.isCalledByLegalizer())
2052            DCI.AddToWorklist(SH.getNode());
2053          return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2054        }
2055      }
2056    }
2057
2058    if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2059        N1.getOpcode() == ISD::XOR) {
2060      // Simplify  X == (X+Z) -->  Z == 0
2061      if (N1.getOperand(0) == N0) {
2062        return DAG.getSetCC(dl, VT, N1.getOperand(1),
2063                        DAG.getConstant(0, N1.getValueType()), Cond);
2064      } else if (N1.getOperand(1) == N0) {
2065        if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2066          return DAG.getSetCC(dl, VT, N1.getOperand(0),
2067                          DAG.getConstant(0, N1.getValueType()), Cond);
2068        } else if (N1.getNode()->hasOneUse()) {
2069          assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2070          // X == (Z-X)  --> X<<1 == Z
2071          SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2072                                     DAG.getConstant(1, getShiftAmountTy()));
2073          if (!DCI.isCalledByLegalizer())
2074            DCI.AddToWorklist(SH.getNode());
2075          return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2076        }
2077      }
2078    }
2079
2080    // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2081    // Note that where y is variable and is known to have at most
2082    // one bit set (for example, if it is z&1) we cannot do this;
2083    // the expressions are not equivalent when y==0.
2084    if (N0.getOpcode() == ISD::AND)
2085      if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2086        if (ValueHasExactlyOneBitSet(N1, DAG)) {
2087          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2088          SDValue Zero = DAG.getConstant(0, N1.getValueType());
2089          return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2090        }
2091      }
2092    if (N1.getOpcode() == ISD::AND)
2093      if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2094        if (ValueHasExactlyOneBitSet(N0, DAG)) {
2095          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2096          SDValue Zero = DAG.getConstant(0, N0.getValueType());
2097          return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2098        }
2099      }
2100  }
2101
2102  // Fold away ALL boolean setcc's.
2103  SDValue Temp;
2104  if (N0.getValueType() == MVT::i1 && foldBooleans) {
2105    switch (Cond) {
2106    default: llvm_unreachable("Unknown integer setcc!");
2107    case ISD::SETEQ:  // X == Y  -> ~(X^Y)
2108      Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2109      N0 = DAG.getNOT(dl, Temp, MVT::i1);
2110      if (!DCI.isCalledByLegalizer())
2111        DCI.AddToWorklist(Temp.getNode());
2112      break;
2113    case ISD::SETNE:  // X != Y   -->  (X^Y)
2114      N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2115      break;
2116    case ISD::SETGT:  // X >s Y   -->  X == 0 & Y == 1  -->  ~X & Y
2117    case ISD::SETULT: // X <u Y   -->  X == 0 & Y == 1  -->  ~X & Y
2118      Temp = DAG.getNOT(dl, N0, MVT::i1);
2119      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2120      if (!DCI.isCalledByLegalizer())
2121        DCI.AddToWorklist(Temp.getNode());
2122      break;
2123    case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  ~Y & X
2124    case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  ~Y & X
2125      Temp = DAG.getNOT(dl, N1, MVT::i1);
2126      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2127      if (!DCI.isCalledByLegalizer())
2128        DCI.AddToWorklist(Temp.getNode());
2129      break;
2130    case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  ~X | Y
2131    case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  ~X | Y
2132      Temp = DAG.getNOT(dl, N0, MVT::i1);
2133      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2134      if (!DCI.isCalledByLegalizer())
2135        DCI.AddToWorklist(Temp.getNode());
2136      break;
2137    case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  ~Y | X
2138    case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  ~Y | X
2139      Temp = DAG.getNOT(dl, N1, MVT::i1);
2140      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2141      break;
2142    }
2143    if (VT != MVT::i1) {
2144      if (!DCI.isCalledByLegalizer())
2145        DCI.AddToWorklist(N0.getNode());
2146      // FIXME: If running after legalize, we probably can't do this.
2147      N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2148    }
2149    return N0;
2150  }
2151
2152  // Could not fold it.
2153  return SDValue();
2154}
2155
2156/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2157/// node is a GlobalAddress + offset.
2158bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
2159                                    int64_t &Offset) const {
2160  if (isa<GlobalAddressSDNode>(N)) {
2161    GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2162    GA = GASD->getGlobal();
2163    Offset += GASD->getOffset();
2164    return true;
2165  }
2166
2167  if (N->getOpcode() == ISD::ADD) {
2168    SDValue N1 = N->getOperand(0);
2169    SDValue N2 = N->getOperand(1);
2170    if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2171      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2172      if (V) {
2173        Offset += V->getSExtValue();
2174        return true;
2175      }
2176    } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2177      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2178      if (V) {
2179        Offset += V->getSExtValue();
2180        return true;
2181      }
2182    }
2183  }
2184  return false;
2185}
2186
2187
2188/// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a
2189/// location that is 'Dist' units away from the location that the 'Base' load
2190/// is loading from.
2191bool TargetLowering::isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base,
2192                                       unsigned Bytes, int Dist,
2193                                       const MachineFrameInfo *MFI) const {
2194  if (LD->getChain() != Base->getChain())
2195    return false;
2196  EVT VT = LD->getValueType(0);
2197  if (VT.getSizeInBits() / 8 != Bytes)
2198    return false;
2199
2200  SDValue Loc = LD->getOperand(1);
2201  SDValue BaseLoc = Base->getOperand(1);
2202  if (Loc.getOpcode() == ISD::FrameIndex) {
2203    if (BaseLoc.getOpcode() != ISD::FrameIndex)
2204      return false;
2205    int FI  = cast<FrameIndexSDNode>(Loc)->getIndex();
2206    int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
2207    int FS  = MFI->getObjectSize(FI);
2208    int BFS = MFI->getObjectSize(BFI);
2209    if (FS != BFS || FS != (int)Bytes) return false;
2210    return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
2211  }
2212  if (Loc.getOpcode() == ISD::ADD && Loc.getOperand(0) == BaseLoc) {
2213    ConstantSDNode *V = dyn_cast<ConstantSDNode>(Loc.getOperand(1));
2214    if (V && (V->getSExtValue() == Dist*Bytes))
2215      return true;
2216  }
2217
2218  GlobalValue *GV1 = NULL;
2219  GlobalValue *GV2 = NULL;
2220  int64_t Offset1 = 0;
2221  int64_t Offset2 = 0;
2222  bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1);
2223  bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
2224  if (isGA1 && isGA2 && GV1 == GV2)
2225    return Offset1 == (Offset2 + Dist*Bytes);
2226  return false;
2227}
2228
2229
2230SDValue TargetLowering::
2231PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2232  // Default implementation: no optimization.
2233  return SDValue();
2234}
2235
2236//===----------------------------------------------------------------------===//
2237//  Inline Assembler Implementation Methods
2238//===----------------------------------------------------------------------===//
2239
2240
2241TargetLowering::ConstraintType
2242TargetLowering::getConstraintType(const std::string &Constraint) const {
2243  // FIXME: lots more standard ones to handle.
2244  if (Constraint.size() == 1) {
2245    switch (Constraint[0]) {
2246    default: break;
2247    case 'r': return C_RegisterClass;
2248    case 'm':    // memory
2249    case 'o':    // offsetable
2250    case 'V':    // not offsetable
2251      return C_Memory;
2252    case 'i':    // Simple Integer or Relocatable Constant
2253    case 'n':    // Simple Integer
2254    case 's':    // Relocatable Constant
2255    case 'X':    // Allow ANY value.
2256    case 'I':    // Target registers.
2257    case 'J':
2258    case 'K':
2259    case 'L':
2260    case 'M':
2261    case 'N':
2262    case 'O':
2263    case 'P':
2264      return C_Other;
2265    }
2266  }
2267
2268  if (Constraint.size() > 1 && Constraint[0] == '{' &&
2269      Constraint[Constraint.size()-1] == '}')
2270    return C_Register;
2271  return C_Unknown;
2272}
2273
2274/// LowerXConstraint - try to replace an X constraint, which matches anything,
2275/// with another that has more specific requirements based on the type of the
2276/// corresponding operand.
2277const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2278  if (ConstraintVT.isInteger())
2279    return "r";
2280  if (ConstraintVT.isFloatingPoint())
2281    return "f";      // works for many targets
2282  return 0;
2283}
2284
2285/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2286/// vector.  If it is invalid, don't add anything to Ops.
2287void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2288                                                  char ConstraintLetter,
2289                                                  bool hasMemory,
2290                                                  std::vector<SDValue> &Ops,
2291                                                  SelectionDAG &DAG) const {
2292  switch (ConstraintLetter) {
2293  default: break;
2294  case 'X':     // Allows any operand; labels (basic block) use this.
2295    if (Op.getOpcode() == ISD::BasicBlock) {
2296      Ops.push_back(Op);
2297      return;
2298    }
2299    // fall through
2300  case 'i':    // Simple Integer or Relocatable Constant
2301  case 'n':    // Simple Integer
2302  case 's': {  // Relocatable Constant
2303    // These operands are interested in values of the form (GV+C), where C may
2304    // be folded in as an offset of GV, or it may be explicitly added.  Also, it
2305    // is possible and fine if either GV or C are missing.
2306    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2307    GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2308
2309    // If we have "(add GV, C)", pull out GV/C
2310    if (Op.getOpcode() == ISD::ADD) {
2311      C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2312      GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2313      if (C == 0 || GA == 0) {
2314        C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2315        GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2316      }
2317      if (C == 0 || GA == 0)
2318        C = 0, GA = 0;
2319    }
2320
2321    // If we find a valid operand, map to the TargetXXX version so that the
2322    // value itself doesn't get selected.
2323    if (GA) {   // Either &GV   or   &GV+C
2324      if (ConstraintLetter != 'n') {
2325        int64_t Offs = GA->getOffset();
2326        if (C) Offs += C->getZExtValue();
2327        Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2328                                                 Op.getValueType(), Offs));
2329        return;
2330      }
2331    }
2332    if (C) {   // just C, no GV.
2333      // Simple constants are not allowed for 's'.
2334      if (ConstraintLetter != 's') {
2335        // gcc prints these as sign extended.  Sign extend value to 64 bits
2336        // now; without this it would get ZExt'd later in
2337        // ScheduleDAGSDNodes::EmitNode, which is very generic.
2338        Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2339                                            MVT::i64));
2340        return;
2341      }
2342    }
2343    break;
2344  }
2345  }
2346}
2347
2348std::vector<unsigned> TargetLowering::
2349getRegClassForInlineAsmConstraint(const std::string &Constraint,
2350                                  EVT VT) const {
2351  return std::vector<unsigned>();
2352}
2353
2354
2355std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2356getRegForInlineAsmConstraint(const std::string &Constraint,
2357                             EVT VT) const {
2358  if (Constraint[0] != '{')
2359    return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2360  assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2361
2362  // Remove the braces from around the name.
2363  std::string RegName(Constraint.begin()+1, Constraint.end()-1);
2364
2365  // Figure out which register class contains this reg.
2366  const TargetRegisterInfo *RI = TM.getRegisterInfo();
2367  for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2368       E = RI->regclass_end(); RCI != E; ++RCI) {
2369    const TargetRegisterClass *RC = *RCI;
2370
2371    // If none of the the value types for this register class are valid, we
2372    // can't use it.  For example, 64-bit reg classes on 32-bit targets.
2373    bool isLegal = false;
2374    for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2375         I != E; ++I) {
2376      if (isTypeLegal(*I)) {
2377        isLegal = true;
2378        break;
2379      }
2380    }
2381
2382    if (!isLegal) continue;
2383
2384    for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2385         I != E; ++I) {
2386      if (StringsEqualNoCase(RegName, RI->getName(*I)))
2387        return std::make_pair(*I, RC);
2388    }
2389  }
2390
2391  return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2392}
2393
2394//===----------------------------------------------------------------------===//
2395// Constraint Selection.
2396
2397/// isMatchingInputConstraint - Return true of this is an input operand that is
2398/// a matching constraint like "4".
2399bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2400  assert(!ConstraintCode.empty() && "No known constraint!");
2401  return isdigit(ConstraintCode[0]);
2402}
2403
2404/// getMatchedOperand - If this is an input matching constraint, this method
2405/// returns the output operand it matches.
2406unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2407  assert(!ConstraintCode.empty() && "No known constraint!");
2408  return atoi(ConstraintCode.c_str());
2409}
2410
2411
2412/// getConstraintGenerality - Return an integer indicating how general CT
2413/// is.
2414static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2415  switch (CT) {
2416  default: llvm_unreachable("Unknown constraint type!");
2417  case TargetLowering::C_Other:
2418  case TargetLowering::C_Unknown:
2419    return 0;
2420  case TargetLowering::C_Register:
2421    return 1;
2422  case TargetLowering::C_RegisterClass:
2423    return 2;
2424  case TargetLowering::C_Memory:
2425    return 3;
2426  }
2427}
2428
2429/// ChooseConstraint - If there are multiple different constraints that we
2430/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2431/// This is somewhat tricky: constraints fall into four classes:
2432///    Other         -> immediates and magic values
2433///    Register      -> one specific register
2434///    RegisterClass -> a group of regs
2435///    Memory        -> memory
2436/// Ideally, we would pick the most specific constraint possible: if we have
2437/// something that fits into a register, we would pick it.  The problem here
2438/// is that if we have something that could either be in a register or in
2439/// memory that use of the register could cause selection of *other*
2440/// operands to fail: they might only succeed if we pick memory.  Because of
2441/// this the heuristic we use is:
2442///
2443///  1) If there is an 'other' constraint, and if the operand is valid for
2444///     that constraint, use it.  This makes us take advantage of 'i'
2445///     constraints when available.
2446///  2) Otherwise, pick the most general constraint present.  This prefers
2447///     'm' over 'r', for example.
2448///
2449static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2450                             bool hasMemory,  const TargetLowering &TLI,
2451                             SDValue Op, SelectionDAG *DAG) {
2452  assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2453  unsigned BestIdx = 0;
2454  TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2455  int BestGenerality = -1;
2456
2457  // Loop over the options, keeping track of the most general one.
2458  for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2459    TargetLowering::ConstraintType CType =
2460      TLI.getConstraintType(OpInfo.Codes[i]);
2461
2462    // If this is an 'other' constraint, see if the operand is valid for it.
2463    // For example, on X86 we might have an 'rI' constraint.  If the operand
2464    // is an integer in the range [0..31] we want to use I (saving a load
2465    // of a register), otherwise we must use 'r'.
2466    if (CType == TargetLowering::C_Other && Op.getNode()) {
2467      assert(OpInfo.Codes[i].size() == 1 &&
2468             "Unhandled multi-letter 'other' constraint");
2469      std::vector<SDValue> ResultOps;
2470      TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
2471                                       ResultOps, *DAG);
2472      if (!ResultOps.empty()) {
2473        BestType = CType;
2474        BestIdx = i;
2475        break;
2476      }
2477    }
2478
2479    // This constraint letter is more general than the previous one, use it.
2480    int Generality = getConstraintGenerality(CType);
2481    if (Generality > BestGenerality) {
2482      BestType = CType;
2483      BestIdx = i;
2484      BestGenerality = Generality;
2485    }
2486  }
2487
2488  OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2489  OpInfo.ConstraintType = BestType;
2490}
2491
2492/// ComputeConstraintToUse - Determines the constraint code and constraint
2493/// type to use for the specific AsmOperandInfo, setting
2494/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2495void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2496                                            SDValue Op,
2497                                            bool hasMemory,
2498                                            SelectionDAG *DAG) const {
2499  assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2500
2501  // Single-letter constraints ('r') are very common.
2502  if (OpInfo.Codes.size() == 1) {
2503    OpInfo.ConstraintCode = OpInfo.Codes[0];
2504    OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2505  } else {
2506    ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
2507  }
2508
2509  // 'X' matches anything.
2510  if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2511    // Labels and constants are handled elsewhere ('X' is the only thing
2512    // that matches labels).  For Functions, the type here is the type of
2513    // the result, which is not what we want to look at; leave them alone.
2514    Value *v = OpInfo.CallOperandVal;
2515    if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2516      OpInfo.CallOperandVal = v;
2517      return;
2518    }
2519
2520    // Otherwise, try to resolve it to something we know about by looking at
2521    // the actual operand type.
2522    if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2523      OpInfo.ConstraintCode = Repl;
2524      OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2525    }
2526  }
2527}
2528
2529//===----------------------------------------------------------------------===//
2530//  Loop Strength Reduction hooks
2531//===----------------------------------------------------------------------===//
2532
2533/// isLegalAddressingMode - Return true if the addressing mode represented
2534/// by AM is legal for this target, for a load/store of the specified type.
2535bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2536                                           const Type *Ty) const {
2537  // The default implementation of this implements a conservative RISCy, r+r and
2538  // r+i addr mode.
2539
2540  // Allows a sign-extended 16-bit immediate field.
2541  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2542    return false;
2543
2544  // No global is ever allowed as a base.
2545  if (AM.BaseGV)
2546    return false;
2547
2548  // Only support r+r,
2549  switch (AM.Scale) {
2550  case 0:  // "r+i" or just "i", depending on HasBaseReg.
2551    break;
2552  case 1:
2553    if (AM.HasBaseReg && AM.BaseOffs)  // "r+r+i" is not allowed.
2554      return false;
2555    // Otherwise we have r+r or r+i.
2556    break;
2557  case 2:
2558    if (AM.HasBaseReg || AM.BaseOffs)  // 2*r+r  or  2*r+i is not allowed.
2559      return false;
2560    // Allow 2*r as r+r.
2561    break;
2562  }
2563
2564  return true;
2565}
2566
2567/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2568/// return a DAG expression to select that will generate the same value by
2569/// multiplying by a magic number.  See:
2570/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2571SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2572                                  std::vector<SDNode*>* Created) const {
2573  EVT VT = N->getValueType(0);
2574  DebugLoc dl= N->getDebugLoc();
2575
2576  // Check to see if we can do this.
2577  // FIXME: We should be more aggressive here.
2578  if (!isTypeLegal(VT))
2579    return SDValue();
2580
2581  APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2582  APInt::ms magics = d.magic();
2583
2584  // Multiply the numerator (operand 0) by the magic value
2585  // FIXME: We should support doing a MUL in a wider type
2586  SDValue Q;
2587  if (isOperationLegalOrCustom(ISD::MULHS, VT))
2588    Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2589                    DAG.getConstant(magics.m, VT));
2590  else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2591    Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2592                              N->getOperand(0),
2593                              DAG.getConstant(magics.m, VT)).getNode(), 1);
2594  else
2595    return SDValue();       // No mulhs or equvialent
2596  // If d > 0 and m < 0, add the numerator
2597  if (d.isStrictlyPositive() && magics.m.isNegative()) {
2598    Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2599    if (Created)
2600      Created->push_back(Q.getNode());
2601  }
2602  // If d < 0 and m > 0, subtract the numerator.
2603  if (d.isNegative() && magics.m.isStrictlyPositive()) {
2604    Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2605    if (Created)
2606      Created->push_back(Q.getNode());
2607  }
2608  // Shift right algebraic if shift value is nonzero
2609  if (magics.s > 0) {
2610    Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2611                    DAG.getConstant(magics.s, getShiftAmountTy()));
2612    if (Created)
2613      Created->push_back(Q.getNode());
2614  }
2615  // Extract the sign bit and add it to the quotient
2616  SDValue T =
2617    DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2618                                                 getShiftAmountTy()));
2619  if (Created)
2620    Created->push_back(T.getNode());
2621  return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2622}
2623
2624/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2625/// return a DAG expression to select that will generate the same value by
2626/// multiplying by a magic number.  See:
2627/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2628SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2629                                  std::vector<SDNode*>* Created) const {
2630  EVT VT = N->getValueType(0);
2631  DebugLoc dl = N->getDebugLoc();
2632
2633  // Check to see if we can do this.
2634  // FIXME: We should be more aggressive here.
2635  if (!isTypeLegal(VT))
2636    return SDValue();
2637
2638  // FIXME: We should use a narrower constant when the upper
2639  // bits are known to be zero.
2640  ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
2641  APInt::mu magics = N1C->getAPIntValue().magicu();
2642
2643  // Multiply the numerator (operand 0) by the magic value
2644  // FIXME: We should support doing a MUL in a wider type
2645  SDValue Q;
2646  if (isOperationLegalOrCustom(ISD::MULHU, VT))
2647    Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
2648                    DAG.getConstant(magics.m, VT));
2649  else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2650    Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
2651                              N->getOperand(0),
2652                              DAG.getConstant(magics.m, VT)).getNode(), 1);
2653  else
2654    return SDValue();       // No mulhu or equvialent
2655  if (Created)
2656    Created->push_back(Q.getNode());
2657
2658  if (magics.a == 0) {
2659    assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2660           "We shouldn't generate an undefined shift!");
2661    return DAG.getNode(ISD::SRL, dl, VT, Q,
2662                       DAG.getConstant(magics.s, getShiftAmountTy()));
2663  } else {
2664    SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2665    if (Created)
2666      Created->push_back(NPQ.getNode());
2667    NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2668                      DAG.getConstant(1, getShiftAmountTy()));
2669    if (Created)
2670      Created->push_back(NPQ.getNode());
2671    NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2672    if (Created)
2673      Created->push_back(NPQ.getNode());
2674    return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2675                       DAG.getConstant(magics.s-1, getShiftAmountTy()));
2676  }
2677}
2678