TargetLowering.cpp revision 24e1a9d3115a5bf4e1c21092ede0f6dfc0a810ad
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetAsmInfo.h" 15#include "llvm/Target/TargetLowering.h" 16#include "llvm/Target/TargetSubtarget.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "llvm/GlobalVariable.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/ADT/StringExtras.h" 24#include "llvm/ADT/STLExtras.h" 25#include "llvm/Support/MathExtras.h" 26using namespace llvm; 27 28/// InitLibcallNames - Set default libcall names. 29/// 30static void InitLibcallNames(const char **Names) { 31 Names[RTLIB::SHL_I32] = "__ashlsi3"; 32 Names[RTLIB::SHL_I64] = "__ashldi3"; 33 Names[RTLIB::SRL_I32] = "__lshrsi3"; 34 Names[RTLIB::SRL_I64] = "__lshrdi3"; 35 Names[RTLIB::SRA_I32] = "__ashrsi3"; 36 Names[RTLIB::SRA_I64] = "__ashrdi3"; 37 Names[RTLIB::MUL_I32] = "__mulsi3"; 38 Names[RTLIB::MUL_I64] = "__muldi3"; 39 Names[RTLIB::SDIV_I32] = "__divsi3"; 40 Names[RTLIB::SDIV_I64] = "__divdi3"; 41 Names[RTLIB::UDIV_I32] = "__udivsi3"; 42 Names[RTLIB::UDIV_I64] = "__udivdi3"; 43 Names[RTLIB::SREM_I32] = "__modsi3"; 44 Names[RTLIB::SREM_I64] = "__moddi3"; 45 Names[RTLIB::UREM_I32] = "__umodsi3"; 46 Names[RTLIB::UREM_I64] = "__umoddi3"; 47 Names[RTLIB::NEG_I32] = "__negsi2"; 48 Names[RTLIB::NEG_I64] = "__negdi2"; 49 Names[RTLIB::ADD_F32] = "__addsf3"; 50 Names[RTLIB::ADD_F64] = "__adddf3"; 51 Names[RTLIB::ADD_F80] = "__addxf3"; 52 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 53 Names[RTLIB::SUB_F32] = "__subsf3"; 54 Names[RTLIB::SUB_F64] = "__subdf3"; 55 Names[RTLIB::SUB_F80] = "__subxf3"; 56 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 57 Names[RTLIB::MUL_F32] = "__mulsf3"; 58 Names[RTLIB::MUL_F64] = "__muldf3"; 59 Names[RTLIB::MUL_F80] = "__mulxf3"; 60 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 61 Names[RTLIB::DIV_F32] = "__divsf3"; 62 Names[RTLIB::DIV_F64] = "__divdf3"; 63 Names[RTLIB::DIV_F80] = "__divxf3"; 64 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 65 Names[RTLIB::REM_F32] = "fmodf"; 66 Names[RTLIB::REM_F64] = "fmod"; 67 Names[RTLIB::REM_F80] = "fmodl"; 68 Names[RTLIB::REM_PPCF128] = "fmodl"; 69 Names[RTLIB::POWI_F32] = "__powisf2"; 70 Names[RTLIB::POWI_F64] = "__powidf2"; 71 Names[RTLIB::POWI_F80] = "__powixf2"; 72 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 73 Names[RTLIB::SQRT_F32] = "sqrtf"; 74 Names[RTLIB::SQRT_F64] = "sqrt"; 75 Names[RTLIB::SQRT_F80] = "sqrtl"; 76 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 77 Names[RTLIB::SIN_F32] = "sinf"; 78 Names[RTLIB::SIN_F64] = "sin"; 79 Names[RTLIB::SIN_F80] = "sinl"; 80 Names[RTLIB::SIN_PPCF128] = "sinl"; 81 Names[RTLIB::COS_F32] = "cosf"; 82 Names[RTLIB::COS_F64] = "cos"; 83 Names[RTLIB::COS_F80] = "cosl"; 84 Names[RTLIB::COS_PPCF128] = "cosl"; 85 Names[RTLIB::POW_F32] = "powf"; 86 Names[RTLIB::POW_F64] = "pow"; 87 Names[RTLIB::POW_F80] = "powl"; 88 Names[RTLIB::POW_PPCF128] = "powl"; 89 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 90 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 91 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 92 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 93 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 94 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 95 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 96 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 97 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 98 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 99 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 100 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 101 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 102 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 103 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 104 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 105 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 106 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 107 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 108 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 109 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 110 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 111 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 112 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 113 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 114 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 115 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 116 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 117 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 118 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 119 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 120 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 121 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 122 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 123 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 124 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 125 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 126 Names[RTLIB::OEQ_F32] = "__eqsf2"; 127 Names[RTLIB::OEQ_F64] = "__eqdf2"; 128 Names[RTLIB::UNE_F32] = "__nesf2"; 129 Names[RTLIB::UNE_F64] = "__nedf2"; 130 Names[RTLIB::OGE_F32] = "__gesf2"; 131 Names[RTLIB::OGE_F64] = "__gedf2"; 132 Names[RTLIB::OLT_F32] = "__ltsf2"; 133 Names[RTLIB::OLT_F64] = "__ltdf2"; 134 Names[RTLIB::OLE_F32] = "__lesf2"; 135 Names[RTLIB::OLE_F64] = "__ledf2"; 136 Names[RTLIB::OGT_F32] = "__gtsf2"; 137 Names[RTLIB::OGT_F64] = "__gtdf2"; 138 Names[RTLIB::UO_F32] = "__unordsf2"; 139 Names[RTLIB::UO_F64] = "__unorddf2"; 140 Names[RTLIB::O_F32] = "__unordsf2"; 141 Names[RTLIB::O_F64] = "__unorddf2"; 142} 143 144/// InitCmpLibcallCCs - Set default comparison libcall CC. 145/// 146static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 147 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 148 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 149 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 150 CCs[RTLIB::UNE_F32] = ISD::SETNE; 151 CCs[RTLIB::UNE_F64] = ISD::SETNE; 152 CCs[RTLIB::OGE_F32] = ISD::SETGE; 153 CCs[RTLIB::OGE_F64] = ISD::SETGE; 154 CCs[RTLIB::OLT_F32] = ISD::SETLT; 155 CCs[RTLIB::OLT_F64] = ISD::SETLT; 156 CCs[RTLIB::OLE_F32] = ISD::SETLE; 157 CCs[RTLIB::OLE_F64] = ISD::SETLE; 158 CCs[RTLIB::OGT_F32] = ISD::SETGT; 159 CCs[RTLIB::OGT_F64] = ISD::SETGT; 160 CCs[RTLIB::UO_F32] = ISD::SETNE; 161 CCs[RTLIB::UO_F64] = ISD::SETNE; 162 CCs[RTLIB::O_F32] = ISD::SETEQ; 163 CCs[RTLIB::O_F64] = ISD::SETEQ; 164} 165 166TargetLowering::TargetLowering(TargetMachine &tm) 167 : TM(tm), TD(TM.getTargetData()) { 168 assert(ISD::BUILTIN_OP_END <= 156 && 169 "Fixed size array in TargetLowering is not large enough!"); 170 // All operations default to being supported. 171 memset(OpActions, 0, sizeof(OpActions)); 172 memset(LoadXActions, 0, sizeof(LoadXActions)); 173 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 174 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 175 memset(ConvertActions, 0, sizeof(ConvertActions)); 176 177 // Set default actions for various operations. 178 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 179 // Default all indexed load / store to expand. 180 for (unsigned IM = (unsigned)ISD::PRE_INC; 181 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 182 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand); 183 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand); 184 } 185 186 // These operations default to expand. 187 setOperationAction(ISD::FGETSIGN, (MVT::ValueType)VT, Expand); 188 } 189 190 // Most targets ignore the @llvm.prefetch intrinsic. 191 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 192 193 // ConstantFP nodes default to expand. Targets can either change this to 194 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 195 // to optimize expansions for certain constants. 196 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 197 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 198 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 199 200 // Default ISD::TRAP to expand (which turns it into abort). 201 setOperationAction(ISD::TRAP, MVT::Other, Expand); 202 203 IsLittleEndian = TD->isLittleEndian(); 204 UsesGlobalOffsetTable = false; 205 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()); 206 ShiftAmtHandling = Undefined; 207 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 208 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 209 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 210 allowUnalignedMemoryAccesses = false; 211 UseUnderscoreSetJmp = false; 212 UseUnderscoreLongJmp = false; 213 SelectIsExpensive = false; 214 IntDivIsCheap = false; 215 Pow2DivIsCheap = false; 216 StackPointerRegisterToSaveRestore = 0; 217 ExceptionPointerRegister = 0; 218 ExceptionSelectorRegister = 0; 219 SetCCResultContents = UndefinedSetCCResult; 220 SchedPreferenceInfo = SchedulingForLatency; 221 JumpBufSize = 0; 222 JumpBufAlignment = 0; 223 IfCvtBlockSizeLimit = 2; 224 IfCvtDupBlockSizeLimit = 0; 225 PrefLoopAlignment = 0; 226 227 InitLibcallNames(LibcallRoutineNames); 228 InitCmpLibcallCCs(CmpLibcallCCs); 229 230 // Tell Legalize whether the assembler supports DEBUG_LOC. 231 if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile()) 232 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 233} 234 235TargetLowering::~TargetLowering() {} 236 237/// computeRegisterProperties - Once all of the register classes are added, 238/// this allows us to compute derived properties we expose. 239void TargetLowering::computeRegisterProperties() { 240 assert(MVT::LAST_VALUETYPE <= 32 && 241 "Too many value types for ValueTypeActions to hold!"); 242 243 // Everything defaults to needing one register. 244 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 245 NumRegistersForVT[i] = 1; 246 RegisterTypeForVT[i] = TransformToType[i] = i; 247 } 248 // ...except isVoid, which doesn't need any registers. 249 NumRegistersForVT[MVT::isVoid] = 0; 250 251 // Find the largest integer register class. 252 unsigned LargestIntReg = MVT::i128; 253 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 254 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 255 256 // Every integer value type larger than this largest register takes twice as 257 // many registers to represent as the previous ValueType. 258 for (MVT::ValueType ExpandedReg = LargestIntReg + 1; 259 MVT::isInteger(ExpandedReg); ++ExpandedReg) { 260 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 261 RegisterTypeForVT[ExpandedReg] = LargestIntReg; 262 TransformToType[ExpandedReg] = ExpandedReg - 1; 263 ValueTypeActions.setTypeAction(ExpandedReg, Expand); 264 } 265 266 // Inspect all of the ValueType's smaller than the largest integer 267 // register to see which ones need promotion. 268 MVT::ValueType LegalIntReg = LargestIntReg; 269 for (MVT::ValueType IntReg = LargestIntReg - 1; 270 IntReg >= MVT::i1; --IntReg) { 271 if (isTypeLegal(IntReg)) { 272 LegalIntReg = IntReg; 273 } else { 274 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg; 275 ValueTypeActions.setTypeAction(IntReg, Promote); 276 } 277 } 278 279 // ppcf128 type is really two f64's. 280 if (!isTypeLegal(MVT::ppcf128)) { 281 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 282 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 283 TransformToType[MVT::ppcf128] = MVT::f64; 284 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 285 } 286 287 // Decide how to handle f64. If the target does not have native f64 support, 288 // expand it to i64 and we will be generating soft float library calls. 289 if (!isTypeLegal(MVT::f64)) { 290 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 291 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 292 TransformToType[MVT::f64] = MVT::i64; 293 ValueTypeActions.setTypeAction(MVT::f64, Expand); 294 } 295 296 // Decide how to handle f32. If the target does not have native support for 297 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 298 if (!isTypeLegal(MVT::f32)) { 299 if (isTypeLegal(MVT::f64)) { 300 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 301 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 302 TransformToType[MVT::f32] = MVT::f64; 303 ValueTypeActions.setTypeAction(MVT::f32, Promote); 304 } else { 305 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 306 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 307 TransformToType[MVT::f32] = MVT::i32; 308 ValueTypeActions.setTypeAction(MVT::f32, Expand); 309 } 310 } 311 312 // Loop over all of the vector value types to see which need transformations. 313 for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE; 314 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 315 if (!isTypeLegal(i)) { 316 MVT::ValueType IntermediateVT, RegisterVT; 317 unsigned NumIntermediates; 318 NumRegistersForVT[i] = 319 getVectorTypeBreakdown(i, 320 IntermediateVT, NumIntermediates, 321 RegisterVT); 322 RegisterTypeForVT[i] = RegisterVT; 323 TransformToType[i] = MVT::Other; // this isn't actually used 324 ValueTypeActions.setTypeAction(i, Expand); 325 } 326 } 327} 328 329const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 330 return NULL; 331} 332 333 334MVT::ValueType 335TargetLowering::getSetCCResultType(const SDOperand &) const { 336 return getValueType(TD->getIntPtrType()); 337} 338 339 340/// getVectorTypeBreakdown - Vector types are broken down into some number of 341/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 342/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 343/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 344/// 345/// This method returns the number of registers needed, and the VT for each 346/// register. It also returns the VT and quantity of the intermediate values 347/// before they are promoted/expanded. 348/// 349unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT, 350 MVT::ValueType &IntermediateVT, 351 unsigned &NumIntermediates, 352 MVT::ValueType &RegisterVT) const { 353 // Figure out the right, legal destination reg to copy into. 354 unsigned NumElts = MVT::getVectorNumElements(VT); 355 MVT::ValueType EltTy = MVT::getVectorElementType(VT); 356 357 unsigned NumVectorRegs = 1; 358 359 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 360 // could break down into LHS/RHS like LegalizeDAG does. 361 if (!isPowerOf2_32(NumElts)) { 362 NumVectorRegs = NumElts; 363 NumElts = 1; 364 } 365 366 // Divide the input until we get to a supported size. This will always 367 // end with a scalar if the target doesn't support vectors. 368 while (NumElts > 1 && 369 !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) { 370 NumElts >>= 1; 371 NumVectorRegs <<= 1; 372 } 373 374 NumIntermediates = NumVectorRegs; 375 376 MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts); 377 if (!isTypeLegal(NewVT)) 378 NewVT = EltTy; 379 IntermediateVT = NewVT; 380 381 MVT::ValueType DestVT = getTypeToTransformTo(NewVT); 382 RegisterVT = DestVT; 383 if (DestVT < NewVT) { 384 // Value is expanded, e.g. i64 -> i16. 385 return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT)); 386 } else { 387 // Otherwise, promotion or legal types use the same number of registers as 388 // the vector decimated to the appropriate level. 389 return NumVectorRegs; 390 } 391 392 return 1; 393} 394 395/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 396/// function arguments in the caller parameter area. This is the actual 397/// alignment, not its logarithm. 398unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 399 return TD->getCallFrameTypeAlignment(Ty); 400} 401 402SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table, 403 SelectionDAG &DAG) const { 404 if (usesGlobalOffsetTable()) 405 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 406 return Table; 407} 408 409//===----------------------------------------------------------------------===// 410// Optimization Methods 411//===----------------------------------------------------------------------===// 412 413/// ShrinkDemandedConstant - Check to see if the specified operand of the 414/// specified instruction is a constant integer. If so, check to see if there 415/// are any bits set in the constant that are not demanded. If so, shrink the 416/// constant and return true. 417bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, 418 const APInt &Demanded) { 419 // FIXME: ISD::SELECT, ISD::SELECT_CC 420 switch(Op.getOpcode()) { 421 default: break; 422 case ISD::AND: 423 case ISD::OR: 424 case ISD::XOR: 425 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 426 if (C->getAPIntValue().intersects(~Demanded)) { 427 MVT::ValueType VT = Op.getValueType(); 428 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 429 DAG.getConstant(Demanded & 430 C->getAPIntValue(), 431 VT)); 432 return CombineTo(Op, New); 433 } 434 break; 435 } 436 return false; 437} 438 439/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 440/// DemandedMask bits of the result of Op are ever used downstream. If we can 441/// use this information to simplify Op, create a new simplified DAG node and 442/// return true, returning the original and new nodes in Old and New. Otherwise, 443/// analyze the expression and return a mask of KnownOne and KnownZero bits for 444/// the expression (used to simplify the caller). The KnownZero/One bits may 445/// only be accurate for those bits in the DemandedMask. 446bool TargetLowering::SimplifyDemandedBits(SDOperand Op, 447 const APInt &DemandedMask, 448 APInt &KnownZero, 449 APInt &KnownOne, 450 TargetLoweringOpt &TLO, 451 unsigned Depth) const { 452 unsigned BitWidth = DemandedMask.getBitWidth(); 453 assert(Op.getValueSizeInBits() == BitWidth && 454 "Mask size mismatches value type size!"); 455 APInt NewMask = DemandedMask; 456 457 // Don't know anything. 458 KnownZero = KnownOne = APInt(BitWidth, 0); 459 460 // Other users may use these bits. 461 if (!Op.Val->hasOneUse()) { 462 if (Depth != 0) { 463 // If not at the root, Just compute the KnownZero/KnownOne bits to 464 // simplify things downstream. 465 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 466 return false; 467 } 468 // If this is the root being simplified, allow it to have multiple uses, 469 // just set the NewMask to all bits. 470 NewMask = APInt::getAllOnesValue(BitWidth); 471 } else if (DemandedMask == 0) { 472 // Not demanding any bits from Op. 473 if (Op.getOpcode() != ISD::UNDEF) 474 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 475 return false; 476 } else if (Depth == 6) { // Limit search depth. 477 return false; 478 } 479 480 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 481 switch (Op.getOpcode()) { 482 case ISD::Constant: 483 // We know all of the bits for a constant! 484 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 485 KnownZero = ~KnownOne & NewMask; 486 return false; // Don't fall through, will infinitely loop. 487 case ISD::AND: 488 // If the RHS is a constant, check to see if the LHS would be zero without 489 // using the bits from the RHS. Below, we use knowledge about the RHS to 490 // simplify the LHS, here we're using information from the LHS to simplify 491 // the RHS. 492 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 493 APInt LHSZero, LHSOne; 494 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 495 LHSZero, LHSOne, Depth+1); 496 // If the LHS already has zeros where RHSC does, this and is dead. 497 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 498 return TLO.CombineTo(Op, Op.getOperand(0)); 499 // If any of the set bits in the RHS are known zero on the LHS, shrink 500 // the constant. 501 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 502 return true; 503 } 504 505 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 506 KnownOne, TLO, Depth+1)) 507 return true; 508 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 509 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 510 KnownZero2, KnownOne2, TLO, Depth+1)) 511 return true; 512 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 513 514 // If all of the demanded bits are known one on one side, return the other. 515 // These bits cannot contribute to the result of the 'and'. 516 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 517 return TLO.CombineTo(Op, Op.getOperand(0)); 518 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 519 return TLO.CombineTo(Op, Op.getOperand(1)); 520 // If all of the demanded bits in the inputs are known zeros, return zero. 521 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 522 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 523 // If the RHS is a constant, see if we can simplify it. 524 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 525 return true; 526 527 // Output known-1 bits are only known if set in both the LHS & RHS. 528 KnownOne &= KnownOne2; 529 // Output known-0 are known to be clear if zero in either the LHS | RHS. 530 KnownZero |= KnownZero2; 531 break; 532 case ISD::OR: 533 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 534 KnownOne, TLO, Depth+1)) 535 return true; 536 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 537 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 538 KnownZero2, KnownOne2, TLO, Depth+1)) 539 return true; 540 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 541 542 // If all of the demanded bits are known zero on one side, return the other. 543 // These bits cannot contribute to the result of the 'or'. 544 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 545 return TLO.CombineTo(Op, Op.getOperand(0)); 546 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 547 return TLO.CombineTo(Op, Op.getOperand(1)); 548 // If all of the potentially set bits on one side are known to be set on 549 // the other side, just use the 'other' side. 550 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 551 return TLO.CombineTo(Op, Op.getOperand(0)); 552 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 553 return TLO.CombineTo(Op, Op.getOperand(1)); 554 // If the RHS is a constant, see if we can simplify it. 555 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 556 return true; 557 558 // Output known-0 bits are only known if clear in both the LHS & RHS. 559 KnownZero &= KnownZero2; 560 // Output known-1 are known to be set if set in either the LHS | RHS. 561 KnownOne |= KnownOne2; 562 break; 563 case ISD::XOR: 564 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 565 KnownOne, TLO, Depth+1)) 566 return true; 567 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 568 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 569 KnownOne2, TLO, Depth+1)) 570 return true; 571 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 572 573 // If all of the demanded bits are known zero on one side, return the other. 574 // These bits cannot contribute to the result of the 'xor'. 575 if ((KnownZero & NewMask) == NewMask) 576 return TLO.CombineTo(Op, Op.getOperand(0)); 577 if ((KnownZero2 & NewMask) == NewMask) 578 return TLO.CombineTo(Op, Op.getOperand(1)); 579 580 // If all of the unknown bits are known to be zero on one side or the other 581 // (but not both) turn this into an *inclusive* or. 582 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 583 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 584 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 585 Op.getOperand(0), 586 Op.getOperand(1))); 587 588 // Output known-0 bits are known if clear or set in both the LHS & RHS. 589 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 590 // Output known-1 are known to be set if set in only one of the LHS, RHS. 591 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 592 593 // If all of the demanded bits on one side are known, and all of the set 594 // bits on that side are also known to be set on the other side, turn this 595 // into an AND, as we know the bits will be cleared. 596 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 597 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 598 if ((KnownOne & KnownOne2) == KnownOne) { 599 MVT::ValueType VT = Op.getValueType(); 600 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 601 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 602 ANDC)); 603 } 604 } 605 606 // If the RHS is a constant, see if we can simplify it. 607 // for XOR, we prefer to force bits to 1 if they will make a -1. 608 // if we can't force bits, try to shrink constant 609 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 610 APInt Expanded = C->getAPIntValue() | (~NewMask); 611 // if we can expand it to have all bits set, do it 612 if (Expanded.isAllOnesValue()) { 613 if (Expanded != C->getAPIntValue()) { 614 MVT::ValueType VT = Op.getValueType(); 615 SDOperand New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 616 TLO.DAG.getConstant(Expanded, VT)); 617 return TLO.CombineTo(Op, New); 618 } 619 // if it already has all the bits set, nothing to change 620 // but don't shrink either! 621 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 622 return true; 623 } 624 } 625 626 KnownZero = KnownZeroOut; 627 KnownOne = KnownOneOut; 628 break; 629 case ISD::SELECT: 630 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 631 KnownOne, TLO, Depth+1)) 632 return true; 633 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 634 KnownOne2, TLO, Depth+1)) 635 return true; 636 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 637 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 638 639 // If the operands are constants, see if we can simplify them. 640 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 641 return true; 642 643 // Only known if known in both the LHS and RHS. 644 KnownOne &= KnownOne2; 645 KnownZero &= KnownZero2; 646 break; 647 case ISD::SELECT_CC: 648 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 649 KnownOne, TLO, Depth+1)) 650 return true; 651 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 652 KnownOne2, TLO, Depth+1)) 653 return true; 654 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 655 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 656 657 // If the operands are constants, see if we can simplify them. 658 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 659 return true; 660 661 // Only known if known in both the LHS and RHS. 662 KnownOne &= KnownOne2; 663 KnownZero &= KnownZero2; 664 break; 665 case ISD::SHL: 666 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 667 unsigned ShAmt = SA->getValue(); 668 SDOperand InOp = Op.getOperand(0); 669 670 // If the shift count is an invalid immediate, don't do anything. 671 if (ShAmt >= BitWidth) 672 break; 673 674 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 675 // single shift. We can do this if the bottom bits (which are shifted 676 // out) are never demanded. 677 if (InOp.getOpcode() == ISD::SRL && 678 isa<ConstantSDNode>(InOp.getOperand(1))) { 679 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 680 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 681 unsigned Opc = ISD::SHL; 682 int Diff = ShAmt-C1; 683 if (Diff < 0) { 684 Diff = -Diff; 685 Opc = ISD::SRL; 686 } 687 688 SDOperand NewSA = 689 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 690 MVT::ValueType VT = Op.getValueType(); 691 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 692 InOp.getOperand(0), NewSA)); 693 } 694 } 695 696 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 697 KnownZero, KnownOne, TLO, Depth+1)) 698 return true; 699 KnownZero <<= SA->getValue(); 700 KnownOne <<= SA->getValue(); 701 // low bits known zero. 702 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getValue()); 703 } 704 break; 705 case ISD::SRL: 706 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 707 MVT::ValueType VT = Op.getValueType(); 708 unsigned ShAmt = SA->getValue(); 709 unsigned VTSize = MVT::getSizeInBits(VT); 710 SDOperand InOp = Op.getOperand(0); 711 712 // If the shift count is an invalid immediate, don't do anything. 713 if (ShAmt >= BitWidth) 714 break; 715 716 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 717 // single shift. We can do this if the top bits (which are shifted out) 718 // are never demanded. 719 if (InOp.getOpcode() == ISD::SHL && 720 isa<ConstantSDNode>(InOp.getOperand(1))) { 721 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 722 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 723 unsigned Opc = ISD::SRL; 724 int Diff = ShAmt-C1; 725 if (Diff < 0) { 726 Diff = -Diff; 727 Opc = ISD::SHL; 728 } 729 730 SDOperand NewSA = 731 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 732 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 733 InOp.getOperand(0), NewSA)); 734 } 735 } 736 737 // Compute the new bits that are at the top now. 738 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 739 KnownZero, KnownOne, TLO, Depth+1)) 740 return true; 741 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 742 KnownZero = KnownZero.lshr(ShAmt); 743 KnownOne = KnownOne.lshr(ShAmt); 744 745 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 746 KnownZero |= HighBits; // High bits known zero. 747 } 748 break; 749 case ISD::SRA: 750 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 751 MVT::ValueType VT = Op.getValueType(); 752 unsigned ShAmt = SA->getValue(); 753 754 // If the shift count is an invalid immediate, don't do anything. 755 if (ShAmt >= BitWidth) 756 break; 757 758 APInt InDemandedMask = (NewMask << ShAmt); 759 760 // If any of the demanded bits are produced by the sign extension, we also 761 // demand the input sign bit. 762 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 763 if (HighBits.intersects(NewMask)) 764 InDemandedMask |= APInt::getSignBit(MVT::getSizeInBits(VT)); 765 766 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 767 KnownZero, KnownOne, TLO, Depth+1)) 768 return true; 769 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 770 KnownZero = KnownZero.lshr(ShAmt); 771 KnownOne = KnownOne.lshr(ShAmt); 772 773 // Handle the sign bit, adjusted to where it is now in the mask. 774 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 775 776 // If the input sign bit is known to be zero, or if none of the top bits 777 // are demanded, turn this into an unsigned shift right. 778 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 779 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 780 Op.getOperand(1))); 781 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 782 KnownOne |= HighBits; 783 } 784 } 785 break; 786 case ISD::SIGN_EXTEND_INREG: { 787 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 788 789 // Sign extension. Compute the demanded bits in the result that are not 790 // present in the input. 791 APInt NewBits = APInt::getHighBitsSet(BitWidth, 792 BitWidth - MVT::getSizeInBits(EVT)) & 793 NewMask; 794 795 // If none of the extended bits are demanded, eliminate the sextinreg. 796 if (NewBits == 0) 797 return TLO.CombineTo(Op, Op.getOperand(0)); 798 799 APInt InSignBit = APInt::getSignBit(MVT::getSizeInBits(EVT)); 800 InSignBit.zext(BitWidth); 801 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 802 MVT::getSizeInBits(EVT)) & 803 NewMask; 804 805 // Since the sign extended bits are demanded, we know that the sign 806 // bit is demanded. 807 InputDemandedBits |= InSignBit; 808 809 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 810 KnownZero, KnownOne, TLO, Depth+1)) 811 return true; 812 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 813 814 // If the sign bit of the input is known set or clear, then we know the 815 // top bits of the result. 816 817 // If the input sign bit is known zero, convert this into a zero extension. 818 if (KnownZero.intersects(InSignBit)) 819 return TLO.CombineTo(Op, 820 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 821 822 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 823 KnownOne |= NewBits; 824 KnownZero &= ~NewBits; 825 } else { // Input sign bit unknown 826 KnownZero &= ~NewBits; 827 KnownOne &= ~NewBits; 828 } 829 break; 830 } 831 case ISD::ZERO_EXTEND: { 832 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 833 APInt InMask = NewMask; 834 InMask.trunc(OperandBitWidth); 835 836 // If none of the top bits are demanded, convert this into an any_extend. 837 APInt NewBits = 838 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 839 if (!NewBits.intersects(NewMask)) 840 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 841 Op.getValueType(), 842 Op.getOperand(0))); 843 844 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 845 KnownZero, KnownOne, TLO, Depth+1)) 846 return true; 847 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 848 KnownZero.zext(BitWidth); 849 KnownOne.zext(BitWidth); 850 KnownZero |= NewBits; 851 break; 852 } 853 case ISD::SIGN_EXTEND: { 854 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 855 unsigned InBits = MVT::getSizeInBits(InVT); 856 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 857 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 858 APInt NewBits = ~InMask & NewMask; 859 860 // If none of the top bits are demanded, convert this into an any_extend. 861 if (NewBits == 0) 862 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 863 Op.getOperand(0))); 864 865 // Since some of the sign extended bits are demanded, we know that the sign 866 // bit is demanded. 867 APInt InDemandedBits = InMask & NewMask; 868 InDemandedBits |= InSignBit; 869 InDemandedBits.trunc(InBits); 870 871 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 872 KnownOne, TLO, Depth+1)) 873 return true; 874 KnownZero.zext(BitWidth); 875 KnownOne.zext(BitWidth); 876 877 // If the sign bit is known zero, convert this to a zero extend. 878 if (KnownZero.intersects(InSignBit)) 879 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 880 Op.getValueType(), 881 Op.getOperand(0))); 882 883 // If the sign bit is known one, the top bits match. 884 if (KnownOne.intersects(InSignBit)) { 885 KnownOne |= NewBits; 886 KnownZero &= ~NewBits; 887 } else { // Otherwise, top bits aren't known. 888 KnownOne &= ~NewBits; 889 KnownZero &= ~NewBits; 890 } 891 break; 892 } 893 case ISD::ANY_EXTEND: { 894 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 895 APInt InMask = NewMask; 896 InMask.trunc(OperandBitWidth); 897 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 898 KnownZero, KnownOne, TLO, Depth+1)) 899 return true; 900 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 901 KnownZero.zext(BitWidth); 902 KnownOne.zext(BitWidth); 903 break; 904 } 905 case ISD::TRUNCATE: { 906 // Simplify the input, using demanded bit information, and compute the known 907 // zero/one bits live out. 908 APInt TruncMask = NewMask; 909 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 910 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 911 KnownZero, KnownOne, TLO, Depth+1)) 912 return true; 913 KnownZero.trunc(BitWidth); 914 KnownOne.trunc(BitWidth); 915 916 // If the input is only used by this truncate, see if we can shrink it based 917 // on the known demanded bits. 918 if (Op.getOperand(0).Val->hasOneUse()) { 919 SDOperand In = Op.getOperand(0); 920 unsigned InBitWidth = In.getValueSizeInBits(); 921 switch (In.getOpcode()) { 922 default: break; 923 case ISD::SRL: 924 // Shrink SRL by a constant if none of the high bits shifted in are 925 // demanded. 926 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 927 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 928 InBitWidth - BitWidth); 929 HighBits = HighBits.lshr(ShAmt->getValue()); 930 HighBits.trunc(BitWidth); 931 932 if (ShAmt->getValue() < BitWidth && !(HighBits & NewMask)) { 933 // None of the shifted in bits are needed. Add a truncate of the 934 // shift input, then shift it. 935 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 936 Op.getValueType(), 937 In.getOperand(0)); 938 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), 939 NewTrunc, In.getOperand(1))); 940 } 941 } 942 break; 943 } 944 } 945 946 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 947 break; 948 } 949 case ISD::AssertZext: { 950 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 951 APInt InMask = APInt::getLowBitsSet(BitWidth, 952 MVT::getSizeInBits(VT)); 953 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 954 KnownZero, KnownOne, TLO, Depth+1)) 955 return true; 956 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 957 KnownZero |= ~InMask & NewMask; 958 break; 959 } 960 case ISD::BIT_CONVERT: 961#if 0 962 // If this is an FP->Int bitcast and if the sign bit is the only thing that 963 // is demanded, turn this into a FGETSIGN. 964 if (NewMask == MVT::getIntVTSignBit(Op.getValueType()) && 965 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 966 !MVT::isVector(Op.getOperand(0).getValueType())) { 967 // Only do this xform if FGETSIGN is valid or if before legalize. 968 if (!TLO.AfterLegalize || 969 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 970 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 971 // place. We expect the SHL to be eliminated by other optimizations. 972 SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 973 Op.getOperand(0)); 974 unsigned ShVal = MVT::getSizeInBits(Op.getValueType())-1; 975 SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 976 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 977 Sign, ShAmt)); 978 } 979 } 980#endif 981 break; 982 case ISD::ADD: 983 case ISD::SUB: 984 case ISD::INTRINSIC_WO_CHAIN: 985 case ISD::INTRINSIC_W_CHAIN: 986 case ISD::INTRINSIC_VOID: 987 case ISD::CTTZ: 988 case ISD::CTLZ: 989 case ISD::CTPOP: 990 case ISD::LOAD: 991 case ISD::SETCC: 992 case ISD::FGETSIGN: 993 // Just use ComputeMaskedBits to compute output bits. 994 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 995 break; 996 } 997 998 // If we know the value of all of the demanded bits, return this as a 999 // constant. 1000 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1001 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1002 1003 return false; 1004} 1005 1006/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1007/// in Mask are known to be either zero or one and return them in the 1008/// KnownZero/KnownOne bitsets. 1009void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 1010 const APInt &Mask, 1011 APInt &KnownZero, 1012 APInt &KnownOne, 1013 const SelectionDAG &DAG, 1014 unsigned Depth) const { 1015 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1016 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1017 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1018 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1019 "Should use MaskedValueIsZero if you don't know whether Op" 1020 " is a target node!"); 1021 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1022} 1023 1024/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1025/// targets that want to expose additional information about sign bits to the 1026/// DAG Combiner. 1027unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op, 1028 unsigned Depth) const { 1029 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1030 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1031 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1032 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1033 "Should use ComputeNumSignBits if you don't know whether Op" 1034 " is a target node!"); 1035 return 1; 1036} 1037 1038 1039/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1040/// and cc. If it is unable to simplify it, return a null SDOperand. 1041SDOperand 1042TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 1043 ISD::CondCode Cond, bool foldBooleans, 1044 DAGCombinerInfo &DCI) const { 1045 SelectionDAG &DAG = DCI.DAG; 1046 1047 // These setcc operations always fold. 1048 switch (Cond) { 1049 default: break; 1050 case ISD::SETFALSE: 1051 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1052 case ISD::SETTRUE: 1053 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1054 } 1055 1056 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 1057 const APInt &C1 = N1C->getAPIntValue(); 1058 if (isa<ConstantSDNode>(N0.Val)) { 1059 return DAG.FoldSetCC(VT, N0, N1, Cond); 1060 } else { 1061 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1062 // equality comparison, then we're just comparing whether X itself is 1063 // zero. 1064 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1065 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1066 N0.getOperand(1).getOpcode() == ISD::Constant) { 1067 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1068 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1069 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) { 1070 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1071 // (srl (ctlz x), 5) == 0 -> X != 0 1072 // (srl (ctlz x), 5) != 1 -> X != 0 1073 Cond = ISD::SETNE; 1074 } else { 1075 // (srl (ctlz x), 5) != 0 -> X == 0 1076 // (srl (ctlz x), 5) == 1 -> X == 0 1077 Cond = ISD::SETEQ; 1078 } 1079 SDOperand Zero = DAG.getConstant(0, N0.getValueType()); 1080 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 1081 Zero, Cond); 1082 } 1083 } 1084 1085 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1086 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1087 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 1088 1089 // If the comparison constant has bits in the upper part, the 1090 // zero-extended value could never match. 1091 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1092 C1.getBitWidth() - InSize))) { 1093 switch (Cond) { 1094 case ISD::SETUGT: 1095 case ISD::SETUGE: 1096 case ISD::SETEQ: return DAG.getConstant(0, VT); 1097 case ISD::SETULT: 1098 case ISD::SETULE: 1099 case ISD::SETNE: return DAG.getConstant(1, VT); 1100 case ISD::SETGT: 1101 case ISD::SETGE: 1102 // True if the sign bit of C1 is set. 1103 return DAG.getConstant(C1.isNegative(), VT); 1104 case ISD::SETLT: 1105 case ISD::SETLE: 1106 // True if the sign bit of C1 isn't set. 1107 return DAG.getConstant(C1.isNonNegative(), VT); 1108 default: 1109 break; 1110 } 1111 } 1112 1113 // Otherwise, we can perform the comparison with the low bits. 1114 switch (Cond) { 1115 case ISD::SETEQ: 1116 case ISD::SETNE: 1117 case ISD::SETUGT: 1118 case ISD::SETUGE: 1119 case ISD::SETULT: 1120 case ISD::SETULE: 1121 return DAG.getSetCC(VT, N0.getOperand(0), 1122 DAG.getConstant(APInt(C1).trunc(InSize), 1123 N0.getOperand(0).getValueType()), 1124 Cond); 1125 default: 1126 break; // todo, be more careful with signed comparisons 1127 } 1128 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1129 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1130 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1131 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 1132 MVT::ValueType ExtDstTy = N0.getValueType(); 1133 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 1134 1135 // If the extended part has any inconsistent bits, it cannot ever 1136 // compare equal. In other words, they have to be all ones or all 1137 // zeros. 1138 APInt ExtBits = 1139 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1140 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1141 return DAG.getConstant(Cond == ISD::SETNE, VT); 1142 1143 SDOperand ZextOp; 1144 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 1145 if (Op0Ty == ExtSrcTy) { 1146 ZextOp = N0.getOperand(0); 1147 } else { 1148 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1149 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1150 DAG.getConstant(Imm, Op0Ty)); 1151 } 1152 if (!DCI.isCalledByLegalizer()) 1153 DCI.AddToWorklist(ZextOp.Val); 1154 // Otherwise, make this a use of a zext. 1155 return DAG.getSetCC(VT, ZextOp, 1156 DAG.getConstant(C1 & APInt::getLowBitsSet( 1157 ExtDstTyBits, 1158 ExtSrcTyBits), 1159 ExtDstTy), 1160 Cond); 1161 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1162 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1163 1164 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1165 if (N0.getOpcode() == ISD::SETCC) { 1166 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1); 1167 if (TrueWhenTrue) 1168 return N0; 1169 1170 // Invert the condition. 1171 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1172 CC = ISD::getSetCCInverse(CC, 1173 MVT::isInteger(N0.getOperand(0).getValueType())); 1174 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); 1175 } 1176 1177 if ((N0.getOpcode() == ISD::XOR || 1178 (N0.getOpcode() == ISD::AND && 1179 N0.getOperand(0).getOpcode() == ISD::XOR && 1180 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1181 isa<ConstantSDNode>(N0.getOperand(1)) && 1182 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1183 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1184 // can only do this if the top bits are known zero. 1185 unsigned BitWidth = N0.getValueSizeInBits(); 1186 if (DAG.MaskedValueIsZero(N0, 1187 APInt::getHighBitsSet(BitWidth, 1188 BitWidth-1))) { 1189 // Okay, get the un-inverted input value. 1190 SDOperand Val; 1191 if (N0.getOpcode() == ISD::XOR) 1192 Val = N0.getOperand(0); 1193 else { 1194 assert(N0.getOpcode() == ISD::AND && 1195 N0.getOperand(0).getOpcode() == ISD::XOR); 1196 // ((X^1)&1)^1 -> X & 1 1197 Val = DAG.getNode(ISD::AND, N0.getValueType(), 1198 N0.getOperand(0).getOperand(0), 1199 N0.getOperand(1)); 1200 } 1201 return DAG.getSetCC(VT, Val, N1, 1202 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1203 } 1204 } 1205 } 1206 1207 APInt MinVal, MaxVal; 1208 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 1209 if (ISD::isSignedIntSetCC(Cond)) { 1210 MinVal = APInt::getSignedMinValue(OperandBitSize); 1211 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1212 } else { 1213 MinVal = APInt::getMinValue(OperandBitSize); 1214 MaxVal = APInt::getMaxValue(OperandBitSize); 1215 } 1216 1217 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1218 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1219 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1220 // X >= C0 --> X > (C0-1) 1221 return DAG.getSetCC(VT, N0, DAG.getConstant(C1-1, N1.getValueType()), 1222 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1223 } 1224 1225 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1226 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1227 // X <= C0 --> X < (C0+1) 1228 return DAG.getSetCC(VT, N0, DAG.getConstant(C1+1, N1.getValueType()), 1229 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1230 } 1231 1232 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1233 return DAG.getConstant(0, VT); // X < MIN --> false 1234 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1235 return DAG.getConstant(1, VT); // X >= MIN --> true 1236 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1237 return DAG.getConstant(0, VT); // X > MAX --> false 1238 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1239 return DAG.getConstant(1, VT); // X <= MAX --> true 1240 1241 // Canonicalize setgt X, Min --> setne X, Min 1242 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1243 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1244 // Canonicalize setlt X, Max --> setne X, Max 1245 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1246 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1247 1248 // If we have setult X, 1, turn it into seteq X, 0 1249 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1250 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 1251 ISD::SETEQ); 1252 // If we have setugt X, Max-1, turn it into seteq X, Max 1253 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1254 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 1255 ISD::SETEQ); 1256 1257 // If we have "setcc X, C0", check to see if we can shrink the immediate 1258 // by changing cc. 1259 1260 // SETUGT X, SINTMAX -> SETLT X, 0 1261 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 1262 C1 == (~0ULL >> (65-OperandBitSize))) 1263 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 1264 ISD::SETLT); 1265 1266 // FIXME: Implement the rest of these. 1267 1268 // Fold bit comparisons when we can. 1269 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1270 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1271 if (ConstantSDNode *AndRHS = 1272 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1273 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1274 // Perform the xform if the AND RHS is a single bit. 1275 if (isPowerOf2_64(AndRHS->getValue())) { 1276 return DAG.getNode(ISD::SRL, VT, N0, 1277 DAG.getConstant(Log2_64(AndRHS->getValue()), 1278 getShiftAmountTy())); 1279 } 1280 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 1281 // (X & 8) == 8 --> (X & 8) >> 3 1282 // Perform the xform if C1 is a single bit. 1283 if (C1.isPowerOf2()) { 1284 return DAG.getNode(ISD::SRL, VT, N0, 1285 DAG.getConstant(C1.logBase2(), getShiftAmountTy())); 1286 } 1287 } 1288 } 1289 } 1290 } else if (isa<ConstantSDNode>(N0.Val)) { 1291 // Ensure that the constant occurs on the RHS. 1292 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1293 } 1294 1295 if (isa<ConstantFPSDNode>(N0.Val)) { 1296 // Constant fold or commute setcc. 1297 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond); 1298 if (O.Val) return O; 1299 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.Val)) { 1300 // If the RHS of an FP comparison is a constant, simplify it away in 1301 // some cases. 1302 if (CFP->getValueAPF().isNaN()) { 1303 // If an operand is known to be a nan, we can fold it. 1304 switch (ISD::getUnorderedFlavor(Cond)) { 1305 default: assert(0 && "Unknown flavor!"); 1306 case 0: // Known false. 1307 return DAG.getConstant(0, VT); 1308 case 1: // Known true. 1309 return DAG.getConstant(1, VT); 1310 case 2: // Undefined. 1311 return DAG.getNode(ISD::UNDEF, VT); 1312 } 1313 } 1314 1315 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1316 // constant if knowing that the operand is non-nan is enough. We prefer to 1317 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1318 // materialize 0.0. 1319 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1320 return DAG.getSetCC(VT, N0, N0, Cond); 1321 } 1322 1323 if (N0 == N1) { 1324 // We can always fold X == X for integer setcc's. 1325 if (MVT::isInteger(N0.getValueType())) 1326 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1327 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1328 if (UOF == 2) // FP operators that are undefined on NaNs. 1329 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1330 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1331 return DAG.getConstant(UOF, VT); 1332 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1333 // if it is not already. 1334 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1335 if (NewCond != Cond) 1336 return DAG.getSetCC(VT, N0, N1, NewCond); 1337 } 1338 1339 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1340 MVT::isInteger(N0.getValueType())) { 1341 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1342 N0.getOpcode() == ISD::XOR) { 1343 // Simplify (X+Y) == (X+Z) --> Y == Z 1344 if (N0.getOpcode() == N1.getOpcode()) { 1345 if (N0.getOperand(0) == N1.getOperand(0)) 1346 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 1347 if (N0.getOperand(1) == N1.getOperand(1)) 1348 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 1349 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1350 // If X op Y == Y op X, try other combinations. 1351 if (N0.getOperand(0) == N1.getOperand(1)) 1352 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 1353 if (N0.getOperand(1) == N1.getOperand(0)) 1354 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 1355 } 1356 } 1357 1358 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1359 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1360 // Turn (X+C1) == C2 --> X == C2-C1 1361 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 1362 return DAG.getSetCC(VT, N0.getOperand(0), 1363 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 1364 N0.getValueType()), Cond); 1365 } 1366 1367 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1368 if (N0.getOpcode() == ISD::XOR) 1369 // If we know that all of the inverted bits are zero, don't bother 1370 // performing the inversion. 1371 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1372 return 1373 DAG.getSetCC(VT, N0.getOperand(0), 1374 DAG.getConstant(LHSR->getAPIntValue() ^ 1375 RHSC->getAPIntValue(), 1376 N0.getValueType()), 1377 Cond); 1378 } 1379 1380 // Turn (C1-X) == C2 --> X == C1-C2 1381 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1382 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 1383 return 1384 DAG.getSetCC(VT, N0.getOperand(1), 1385 DAG.getConstant(SUBC->getAPIntValue() - 1386 RHSC->getAPIntValue(), 1387 N0.getValueType()), 1388 Cond); 1389 } 1390 } 1391 } 1392 1393 // Simplify (X+Z) == X --> Z == 0 1394 if (N0.getOperand(0) == N1) 1395 return DAG.getSetCC(VT, N0.getOperand(1), 1396 DAG.getConstant(0, N0.getValueType()), Cond); 1397 if (N0.getOperand(1) == N1) { 1398 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1399 return DAG.getSetCC(VT, N0.getOperand(0), 1400 DAG.getConstant(0, N0.getValueType()), Cond); 1401 else if (N0.Val->hasOneUse()) { 1402 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1403 // (Z-X) == X --> Z == X<<1 1404 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 1405 N1, 1406 DAG.getConstant(1, getShiftAmountTy())); 1407 if (!DCI.isCalledByLegalizer()) 1408 DCI.AddToWorklist(SH.Val); 1409 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 1410 } 1411 } 1412 } 1413 1414 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1415 N1.getOpcode() == ISD::XOR) { 1416 // Simplify X == (X+Z) --> Z == 0 1417 if (N1.getOperand(0) == N0) { 1418 return DAG.getSetCC(VT, N1.getOperand(1), 1419 DAG.getConstant(0, N1.getValueType()), Cond); 1420 } else if (N1.getOperand(1) == N0) { 1421 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1422 return DAG.getSetCC(VT, N1.getOperand(0), 1423 DAG.getConstant(0, N1.getValueType()), Cond); 1424 } else if (N1.Val->hasOneUse()) { 1425 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1426 // X == (Z-X) --> X<<1 == Z 1427 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 1428 DAG.getConstant(1, getShiftAmountTy())); 1429 if (!DCI.isCalledByLegalizer()) 1430 DCI.AddToWorklist(SH.Val); 1431 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 1432 } 1433 } 1434 } 1435 } 1436 1437 // Fold away ALL boolean setcc's. 1438 SDOperand Temp; 1439 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1440 switch (Cond) { 1441 default: assert(0 && "Unknown integer setcc!"); 1442 case ISD::SETEQ: // X == Y -> (X^Y)^1 1443 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1444 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 1445 if (!DCI.isCalledByLegalizer()) 1446 DCI.AddToWorklist(Temp.Val); 1447 break; 1448 case ISD::SETNE: // X != Y --> (X^Y) 1449 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1450 break; 1451 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 1452 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 1453 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1454 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 1455 if (!DCI.isCalledByLegalizer()) 1456 DCI.AddToWorklist(Temp.Val); 1457 break; 1458 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 1459 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 1460 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1461 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 1462 if (!DCI.isCalledByLegalizer()) 1463 DCI.AddToWorklist(Temp.Val); 1464 break; 1465 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 1466 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 1467 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1468 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 1469 if (!DCI.isCalledByLegalizer()) 1470 DCI.AddToWorklist(Temp.Val); 1471 break; 1472 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 1473 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 1474 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1475 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 1476 break; 1477 } 1478 if (VT != MVT::i1) { 1479 if (!DCI.isCalledByLegalizer()) 1480 DCI.AddToWorklist(N0.Val); 1481 // FIXME: If running after legalize, we probably can't do this. 1482 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1483 } 1484 return N0; 1485 } 1486 1487 // Could not fold it. 1488 return SDOperand(); 1489} 1490 1491SDOperand TargetLowering:: 1492PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1493 // Default implementation: no optimization. 1494 return SDOperand(); 1495} 1496 1497//===----------------------------------------------------------------------===// 1498// Inline Assembler Implementation Methods 1499//===----------------------------------------------------------------------===// 1500 1501 1502TargetLowering::ConstraintType 1503TargetLowering::getConstraintType(const std::string &Constraint) const { 1504 // FIXME: lots more standard ones to handle. 1505 if (Constraint.size() == 1) { 1506 switch (Constraint[0]) { 1507 default: break; 1508 case 'r': return C_RegisterClass; 1509 case 'm': // memory 1510 case 'o': // offsetable 1511 case 'V': // not offsetable 1512 return C_Memory; 1513 case 'i': // Simple Integer or Relocatable Constant 1514 case 'n': // Simple Integer 1515 case 's': // Relocatable Constant 1516 case 'X': // Allow ANY value. 1517 case 'I': // Target registers. 1518 case 'J': 1519 case 'K': 1520 case 'L': 1521 case 'M': 1522 case 'N': 1523 case 'O': 1524 case 'P': 1525 return C_Other; 1526 } 1527 } 1528 1529 if (Constraint.size() > 1 && Constraint[0] == '{' && 1530 Constraint[Constraint.size()-1] == '}') 1531 return C_Register; 1532 return C_Unknown; 1533} 1534 1535/// LowerXConstraint - try to replace an X constraint, which matches anything, 1536/// with another that has more specific requirements based on the type of the 1537/// corresponding operand. 1538const char *TargetLowering::LowerXConstraint(MVT::ValueType ConstraintVT) const{ 1539 if (MVT::isInteger(ConstraintVT)) 1540 return "r"; 1541 if (MVT::isFloatingPoint(ConstraintVT)) 1542 return "f"; // works for many targets 1543 return 0; 1544} 1545 1546/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1547/// vector. If it is invalid, don't add anything to Ops. 1548void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op, 1549 char ConstraintLetter, 1550 std::vector<SDOperand> &Ops, 1551 SelectionDAG &DAG) const { 1552 switch (ConstraintLetter) { 1553 default: break; 1554 case 'X': // Allows any operand; labels (basic block) use this. 1555 if (Op.getOpcode() == ISD::BasicBlock) { 1556 Ops.push_back(Op); 1557 return; 1558 } 1559 // fall through 1560 case 'i': // Simple Integer or Relocatable Constant 1561 case 'n': // Simple Integer 1562 case 's': { // Relocatable Constant 1563 // These operands are interested in values of the form (GV+C), where C may 1564 // be folded in as an offset of GV, or it may be explicitly added. Also, it 1565 // is possible and fine if either GV or C are missing. 1566 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1567 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 1568 1569 // If we have "(add GV, C)", pull out GV/C 1570 if (Op.getOpcode() == ISD::ADD) { 1571 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1572 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 1573 if (C == 0 || GA == 0) { 1574 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 1575 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 1576 } 1577 if (C == 0 || GA == 0) 1578 C = 0, GA = 0; 1579 } 1580 1581 // If we find a valid operand, map to the TargetXXX version so that the 1582 // value itself doesn't get selected. 1583 if (GA) { // Either &GV or &GV+C 1584 if (ConstraintLetter != 'n') { 1585 int64_t Offs = GA->getOffset(); 1586 if (C) Offs += C->getValue(); 1587 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 1588 Op.getValueType(), Offs)); 1589 return; 1590 } 1591 } 1592 if (C) { // just C, no GV. 1593 // Simple constants are not allowed for 's'. 1594 if (ConstraintLetter != 's') { 1595 Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType())); 1596 return; 1597 } 1598 } 1599 break; 1600 } 1601 } 1602} 1603 1604std::vector<unsigned> TargetLowering:: 1605getRegClassForInlineAsmConstraint(const std::string &Constraint, 1606 MVT::ValueType VT) const { 1607 return std::vector<unsigned>(); 1608} 1609 1610 1611std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 1612getRegForInlineAsmConstraint(const std::string &Constraint, 1613 MVT::ValueType VT) const { 1614 if (Constraint[0] != '{') 1615 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1616 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 1617 1618 // Remove the braces from around the name. 1619 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 1620 1621 // Figure out which register class contains this reg. 1622 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 1623 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 1624 E = RI->regclass_end(); RCI != E; ++RCI) { 1625 const TargetRegisterClass *RC = *RCI; 1626 1627 // If none of the the value types for this register class are valid, we 1628 // can't use it. For example, 64-bit reg classes on 32-bit targets. 1629 bool isLegal = false; 1630 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1631 I != E; ++I) { 1632 if (isTypeLegal(*I)) { 1633 isLegal = true; 1634 break; 1635 } 1636 } 1637 1638 if (!isLegal) continue; 1639 1640 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 1641 I != E; ++I) { 1642 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName)) 1643 return std::make_pair(*I, RC); 1644 } 1645 } 1646 1647 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1648} 1649 1650//===----------------------------------------------------------------------===// 1651// Constraint Selection. 1652 1653/// getConstraintGenerality - Return an integer indicating how general CT 1654/// is. 1655static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 1656 switch (CT) { 1657 default: assert(0 && "Unknown constraint type!"); 1658 case TargetLowering::C_Other: 1659 case TargetLowering::C_Unknown: 1660 return 0; 1661 case TargetLowering::C_Register: 1662 return 1; 1663 case TargetLowering::C_RegisterClass: 1664 return 2; 1665 case TargetLowering::C_Memory: 1666 return 3; 1667 } 1668} 1669 1670/// ChooseConstraint - If there are multiple different constraints that we 1671/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 1672/// This is somewhat tricky: constraints fall into four classes: 1673/// Other -> immediates and magic values 1674/// Register -> one specific register 1675/// RegisterClass -> a group of regs 1676/// Memory -> memory 1677/// Ideally, we would pick the most specific constraint possible: if we have 1678/// something that fits into a register, we would pick it. The problem here 1679/// is that if we have something that could either be in a register or in 1680/// memory that use of the register could cause selection of *other* 1681/// operands to fail: they might only succeed if we pick memory. Because of 1682/// this the heuristic we use is: 1683/// 1684/// 1) If there is an 'other' constraint, and if the operand is valid for 1685/// that constraint, use it. This makes us take advantage of 'i' 1686/// constraints when available. 1687/// 2) Otherwise, pick the most general constraint present. This prefers 1688/// 'm' over 'r', for example. 1689/// 1690static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 1691 const TargetLowering &TLI, 1692 SDOperand Op, SelectionDAG *DAG) { 1693 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 1694 unsigned BestIdx = 0; 1695 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 1696 int BestGenerality = -1; 1697 1698 // Loop over the options, keeping track of the most general one. 1699 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 1700 TargetLowering::ConstraintType CType = 1701 TLI.getConstraintType(OpInfo.Codes[i]); 1702 1703 // If this is an 'other' constraint, see if the operand is valid for it. 1704 // For example, on X86 we might have an 'rI' constraint. If the operand 1705 // is an integer in the range [0..31] we want to use I (saving a load 1706 // of a register), otherwise we must use 'r'. 1707 if (CType == TargetLowering::C_Other && Op.Val) { 1708 assert(OpInfo.Codes[i].size() == 1 && 1709 "Unhandled multi-letter 'other' constraint"); 1710 std::vector<SDOperand> ResultOps; 1711 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], 1712 ResultOps, *DAG); 1713 if (!ResultOps.empty()) { 1714 BestType = CType; 1715 BestIdx = i; 1716 break; 1717 } 1718 } 1719 1720 // This constraint letter is more general than the previous one, use it. 1721 int Generality = getConstraintGenerality(CType); 1722 if (Generality > BestGenerality) { 1723 BestType = CType; 1724 BestIdx = i; 1725 BestGenerality = Generality; 1726 } 1727 } 1728 1729 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 1730 OpInfo.ConstraintType = BestType; 1731} 1732 1733/// ComputeConstraintToUse - Determines the constraint code and constraint 1734/// type to use for the specific AsmOperandInfo, setting 1735/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 1736void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1737 SDOperand Op, 1738 SelectionDAG *DAG) const { 1739 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 1740 1741 // Single-letter constraints ('r') are very common. 1742 if (OpInfo.Codes.size() == 1) { 1743 OpInfo.ConstraintCode = OpInfo.Codes[0]; 1744 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 1745 } else { 1746 ChooseConstraint(OpInfo, *this, Op, DAG); 1747 } 1748 1749 // 'X' matches anything. 1750 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 1751 // Labels and constants are handled elsewhere ('X' is the only thing 1752 // that matches labels). 1753 if (isa<BasicBlock>(OpInfo.CallOperandVal) || 1754 isa<ConstantInt>(OpInfo.CallOperandVal)) 1755 return; 1756 1757 // Otherwise, try to resolve it to something we know about by looking at 1758 // the actual operand type. 1759 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 1760 OpInfo.ConstraintCode = Repl; 1761 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 1762 } 1763 } 1764} 1765 1766//===----------------------------------------------------------------------===// 1767// Loop Strength Reduction hooks 1768//===----------------------------------------------------------------------===// 1769 1770/// isLegalAddressingMode - Return true if the addressing mode represented 1771/// by AM is legal for this target, for a load/store of the specified type. 1772bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 1773 const Type *Ty) const { 1774 // The default implementation of this implements a conservative RISCy, r+r and 1775 // r+i addr mode. 1776 1777 // Allows a sign-extended 16-bit immediate field. 1778 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1779 return false; 1780 1781 // No global is ever allowed as a base. 1782 if (AM.BaseGV) 1783 return false; 1784 1785 // Only support r+r, 1786 switch (AM.Scale) { 1787 case 0: // "r+i" or just "i", depending on HasBaseReg. 1788 break; 1789 case 1: 1790 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1791 return false; 1792 // Otherwise we have r+r or r+i. 1793 break; 1794 case 2: 1795 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1796 return false; 1797 // Allow 2*r as r+r. 1798 break; 1799 } 1800 1801 return true; 1802} 1803 1804// Magic for divide replacement 1805 1806struct ms { 1807 int64_t m; // magic number 1808 int64_t s; // shift amount 1809}; 1810 1811struct mu { 1812 uint64_t m; // magic number 1813 int64_t a; // add indicator 1814 int64_t s; // shift amount 1815}; 1816 1817/// magic - calculate the magic numbers required to codegen an integer sdiv as 1818/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1819/// or -1. 1820static ms magic32(int32_t d) { 1821 int32_t p; 1822 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 1823 const uint32_t two31 = 0x80000000U; 1824 struct ms mag; 1825 1826 ad = abs(d); 1827 t = two31 + ((uint32_t)d >> 31); 1828 anc = t - 1 - t%ad; // absolute value of nc 1829 p = 31; // initialize p 1830 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 1831 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1832 q2 = two31/ad; // initialize q2 = 2p/abs(d) 1833 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1834 do { 1835 p = p + 1; 1836 q1 = 2*q1; // update q1 = 2p/abs(nc) 1837 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1838 if (r1 >= anc) { // must be unsigned comparison 1839 q1 = q1 + 1; 1840 r1 = r1 - anc; 1841 } 1842 q2 = 2*q2; // update q2 = 2p/abs(d) 1843 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1844 if (r2 >= ad) { // must be unsigned comparison 1845 q2 = q2 + 1; 1846 r2 = r2 - ad; 1847 } 1848 delta = ad - r2; 1849 } while (q1 < delta || (q1 == delta && r1 == 0)); 1850 1851 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 1852 if (d < 0) mag.m = -mag.m; // resulting magic number 1853 mag.s = p - 32; // resulting shift 1854 return mag; 1855} 1856 1857/// magicu - calculate the magic numbers required to codegen an integer udiv as 1858/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1859static mu magicu32(uint32_t d) { 1860 int32_t p; 1861 uint32_t nc, delta, q1, r1, q2, r2; 1862 struct mu magu; 1863 magu.a = 0; // initialize "add" indicator 1864 nc = - 1 - (-d)%d; 1865 p = 31; // initialize p 1866 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 1867 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 1868 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 1869 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 1870 do { 1871 p = p + 1; 1872 if (r1 >= nc - r1 ) { 1873 q1 = 2*q1 + 1; // update q1 1874 r1 = 2*r1 - nc; // update r1 1875 } 1876 else { 1877 q1 = 2*q1; // update q1 1878 r1 = 2*r1; // update r1 1879 } 1880 if (r2 + 1 >= d - r2) { 1881 if (q2 >= 0x7FFFFFFF) magu.a = 1; 1882 q2 = 2*q2 + 1; // update q2 1883 r2 = 2*r2 + 1 - d; // update r2 1884 } 1885 else { 1886 if (q2 >= 0x80000000) magu.a = 1; 1887 q2 = 2*q2; // update q2 1888 r2 = 2*r2 + 1; // update r2 1889 } 1890 delta = d - 1 - r2; 1891 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 1892 magu.m = q2 + 1; // resulting magic number 1893 magu.s = p - 32; // resulting shift 1894 return magu; 1895} 1896 1897/// magic - calculate the magic numbers required to codegen an integer sdiv as 1898/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1899/// or -1. 1900static ms magic64(int64_t d) { 1901 int64_t p; 1902 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 1903 const uint64_t two63 = 9223372036854775808ULL; // 2^63 1904 struct ms mag; 1905 1906 ad = d >= 0 ? d : -d; 1907 t = two63 + ((uint64_t)d >> 63); 1908 anc = t - 1 - t%ad; // absolute value of nc 1909 p = 63; // initialize p 1910 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 1911 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1912 q2 = two63/ad; // initialize q2 = 2p/abs(d) 1913 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1914 do { 1915 p = p + 1; 1916 q1 = 2*q1; // update q1 = 2p/abs(nc) 1917 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1918 if (r1 >= anc) { // must be unsigned comparison 1919 q1 = q1 + 1; 1920 r1 = r1 - anc; 1921 } 1922 q2 = 2*q2; // update q2 = 2p/abs(d) 1923 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1924 if (r2 >= ad) { // must be unsigned comparison 1925 q2 = q2 + 1; 1926 r2 = r2 - ad; 1927 } 1928 delta = ad - r2; 1929 } while (q1 < delta || (q1 == delta && r1 == 0)); 1930 1931 mag.m = q2 + 1; 1932 if (d < 0) mag.m = -mag.m; // resulting magic number 1933 mag.s = p - 64; // resulting shift 1934 return mag; 1935} 1936 1937/// magicu - calculate the magic numbers required to codegen an integer udiv as 1938/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1939static mu magicu64(uint64_t d) 1940{ 1941 int64_t p; 1942 uint64_t nc, delta, q1, r1, q2, r2; 1943 struct mu magu; 1944 magu.a = 0; // initialize "add" indicator 1945 nc = - 1 - (-d)%d; 1946 p = 63; // initialize p 1947 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 1948 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 1949 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 1950 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 1951 do { 1952 p = p + 1; 1953 if (r1 >= nc - r1 ) { 1954 q1 = 2*q1 + 1; // update q1 1955 r1 = 2*r1 - nc; // update r1 1956 } 1957 else { 1958 q1 = 2*q1; // update q1 1959 r1 = 2*r1; // update r1 1960 } 1961 if (r2 + 1 >= d - r2) { 1962 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 1963 q2 = 2*q2 + 1; // update q2 1964 r2 = 2*r2 + 1 - d; // update r2 1965 } 1966 else { 1967 if (q2 >= 0x8000000000000000ull) magu.a = 1; 1968 q2 = 2*q2; // update q2 1969 r2 = 2*r2 + 1; // update r2 1970 } 1971 delta = d - 1 - r2; 1972 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0))); 1973 magu.m = q2 + 1; // resulting magic number 1974 magu.s = p - 64; // resulting shift 1975 return magu; 1976} 1977 1978/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 1979/// return a DAG expression to select that will generate the same value by 1980/// multiplying by a magic number. See: 1981/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 1982SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 1983 std::vector<SDNode*>* Created) const { 1984 MVT::ValueType VT = N->getValueType(0); 1985 1986 // Check to see if we can do this. 1987 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 1988 return SDOperand(); // BuildSDIV only operates on i32 or i64 1989 1990 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 1991 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 1992 1993 // Multiply the numerator (operand 0) by the magic value 1994 SDOperand Q; 1995 if (isOperationLegal(ISD::MULHS, VT)) 1996 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 1997 DAG.getConstant(magics.m, VT)); 1998 else if (isOperationLegal(ISD::SMUL_LOHI, VT)) 1999 Q = SDOperand(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), 2000 N->getOperand(0), 2001 DAG.getConstant(magics.m, VT)).Val, 1); 2002 else 2003 return SDOperand(); // No mulhs or equvialent 2004 // If d > 0 and m < 0, add the numerator 2005 if (d > 0 && magics.m < 0) { 2006 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2007 if (Created) 2008 Created->push_back(Q.Val); 2009 } 2010 // If d < 0 and m > 0, subtract the numerator. 2011 if (d < 0 && magics.m > 0) { 2012 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2013 if (Created) 2014 Created->push_back(Q.Val); 2015 } 2016 // Shift right algebraic if shift value is nonzero 2017 if (magics.s > 0) { 2018 Q = DAG.getNode(ISD::SRA, VT, Q, 2019 DAG.getConstant(magics.s, getShiftAmountTy())); 2020 if (Created) 2021 Created->push_back(Q.Val); 2022 } 2023 // Extract the sign bit and add it to the quotient 2024 SDOperand T = 2025 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 2026 getShiftAmountTy())); 2027 if (Created) 2028 Created->push_back(T.Val); 2029 return DAG.getNode(ISD::ADD, VT, Q, T); 2030} 2031 2032/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2033/// return a DAG expression to select that will generate the same value by 2034/// multiplying by a magic number. See: 2035/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2036SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2037 std::vector<SDNode*>* Created) const { 2038 MVT::ValueType VT = N->getValueType(0); 2039 2040 // Check to see if we can do this. 2041 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2042 return SDOperand(); // BuildUDIV only operates on i32 or i64 2043 2044 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 2045 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2046 2047 // Multiply the numerator (operand 0) by the magic value 2048 SDOperand Q; 2049 if (isOperationLegal(ISD::MULHU, VT)) 2050 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2051 DAG.getConstant(magics.m, VT)); 2052 else if (isOperationLegal(ISD::UMUL_LOHI, VT)) 2053 Q = SDOperand(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), 2054 N->getOperand(0), 2055 DAG.getConstant(magics.m, VT)).Val, 1); 2056 else 2057 return SDOperand(); // No mulhu or equvialent 2058 if (Created) 2059 Created->push_back(Q.Val); 2060 2061 if (magics.a == 0) { 2062 return DAG.getNode(ISD::SRL, VT, Q, 2063 DAG.getConstant(magics.s, getShiftAmountTy())); 2064 } else { 2065 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2066 if (Created) 2067 Created->push_back(NPQ.Val); 2068 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2069 DAG.getConstant(1, getShiftAmountTy())); 2070 if (Created) 2071 Created->push_back(NPQ.Val); 2072 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2073 if (Created) 2074 Created->push_back(NPQ.Val); 2075 return DAG.getNode(ISD::SRL, VT, NPQ, 2076 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2077 } 2078} 2079