TargetLowering.cpp revision 2b7401e28e0c3c18ef027345560f9ce5abeef4d2
18d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 28d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// 38d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// The LLVM Compiler Infrastructure 48d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// 5c5ec7f57ead87efa365800228aa0b09a12d9e6c4Dmitry Shmidt// This file was developed by the LLVM research group and is distributed under 6c5ec7f57ead87efa365800228aa0b09a12d9e6c4Dmitry Shmidt// the University of Illinois Open Source License. See LICENSE.TXT for details. 78d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// 88d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt//===----------------------------------------------------------------------===// 98d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// 108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// This implements the TargetLowering class. 118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// 128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt//===----------------------------------------------------------------------===// 138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/Target/TargetLowering.h" 158d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/Target/TargetMachine.h" 168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/Target/MRegisterInfo.h" 178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/CodeGen/SelectionDAG.h" 188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/ADT/StringExtras.h" 198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/Support/MathExtras.h" 208d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtusing namespace llvm; 218d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 228d520ff1dc2da35cdca849e982051b86468016d8Dmitry ShmidtTargetLowering::TargetLowering(TargetMachine &tm) 238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt : TM(tm), TD(TM.getTargetData()) { 248d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(ISD::BUILTIN_OP_END <= 128 && 258d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt "Fixed size array in TargetLowering is not large enough!"); 268d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // All operations default to being supported. 278d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt memset(OpActions, 0, sizeof(OpActions)); 288d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 298d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt IsLittleEndian = TD.isLittleEndian(); 308d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType()); 318d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ShiftAmtHandling = Undefined; 328d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 338d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 348d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt allowUnalignedMemoryAccesses = false; 358d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt UseUnderscoreSetJmpLongJmp = false; 368d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt IntDivIsCheap = false; 378d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Pow2DivIsCheap = false; 388d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt StackPointerRegisterToSaveRestore = 0; 398d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SchedPreferenceInfo = SchedulingForLatency; 408d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 418d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 428d520ff1dc2da35cdca849e982051b86468016d8Dmitry ShmidtTargetLowering::~TargetLowering() {} 438d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 448d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// setValueTypeAction - Set the action for a particular value type. This 458d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// assumes an action has not already been set for this value type. 468d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic void SetValueTypeAction(MVT::ValueType VT, 478d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt TargetLowering::LegalizeAction Action, 488d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt TargetLowering &TLI, 498d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::ValueType *TransformToType, 508d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt TargetLowering::ValueTypeActionImpl &ValueTypeActions) { 518d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ValueTypeActions.setTypeAction(VT, Action); 528d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (Action == TargetLowering::Promote) { 538d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::ValueType PromoteTo; 548d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (VT == MVT::f32) 558d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt PromoteTo = MVT::f64; 568d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt else { 578d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned LargerReg = VT+1; 588d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) { 598d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ++LargerReg; 608d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(MVT::isInteger((MVT::ValueType)LargerReg) && 618d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt "Nothing to promote to??"); 628d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 638d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt PromoteTo = (MVT::ValueType)LargerReg; 648d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 658d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 668d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) && 678d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) && 688d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt "Can only promote from int->int or fp->fp!"); 698d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(VT < PromoteTo && "Must promote to a larger type!"); 708d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt TransformToType[VT] = PromoteTo; 718d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } else if (Action == TargetLowering::Expand) { 728d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 && 738d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt "Cannot expand this type: target must support SOME integer reg!"); 748d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Expand to the next smaller integer type! 758d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt TransformToType[VT] = (MVT::ValueType)(VT-1); 768d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 778d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 788d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 798d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 808d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// computeRegisterProperties - Once all of the register classes are added, 818d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// this allows us to compute derived properties we expose. 828d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtvoid TargetLowering::computeRegisterProperties() { 838d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(MVT::LAST_VALUETYPE <= 32 && 848d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt "Too many value types for ValueTypeActions to hold!"); 858d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 868d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Everything defaults to one. 878d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) 888d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt NumElementsForVT[i] = 1; 898d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 908d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Find the largest integer register class. 918d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned LargestIntReg = MVT::i128; 928d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 938d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 948d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 958d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Every integer value type larger than this largest register takes twice as 968d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // many registers to represent as the previous ValueType. 978d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned ExpandedReg = LargestIntReg; ++LargestIntReg; 988d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg) 998d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1]; 1008d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1018d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Inspect all of the ValueType's possible, deciding how to process them. 1028d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg) 1038d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If we are expanding this type, expand it! 1048d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (getNumElements((MVT::ValueType)IntReg) != 1) 1058d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType, 1068d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ValueTypeActions); 1078d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt else if (!isTypeLegal((MVT::ValueType)IntReg)) 1088d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Otherwise, if we don't have native support, we must promote to a 1098d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // larger type. 1108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this, 1118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt TransformToType, ValueTypeActions); 1128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt else 1138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg; 1148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1158d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If the target does not have native support for F32, promote it to F64. 1168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!isTypeLegal(MVT::f32)) 1178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SetValueTypeAction(MVT::f32, Promote, *this, 1188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt TransformToType, ValueTypeActions); 1198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt else 1208d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt TransformToType[MVT::f32] = MVT::f32; 1218d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1228d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Set MVT::Vector to always be Expanded 1238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType, 1248d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ValueTypeActions); 1258d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1268d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(isTypeLegal(MVT::f64) && "Target does not support FP?"); 1278d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt TransformToType[MVT::f64] = MVT::f64; 1288d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 1298d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1308d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtconst char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 1318d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return NULL; 1328d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 1338d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1348d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt//===----------------------------------------------------------------------===// 1358d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// Optimization Methods 1368d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt//===----------------------------------------------------------------------===// 1378d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1388d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// ShrinkDemandedConstant - Check to see if the specified operand of the 1398d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// specified instruction is a constant integer. If so, check to see if there 1408d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// are any bits set in the constant that are not demanded. If so, shrink the 1418d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// constant and return true. 1428d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtbool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, 1438d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint64_t Demanded) { 1448d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // FIXME: ISD::SELECT 1458d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt switch(Op.getOpcode()) { 1468d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt default: break; 1478d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::AND: 1488d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::OR: 1498d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::XOR: 1508d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 1518d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((~Demanded & C->getValue()) != 0) { 1528d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::ValueType VT = Op.getValueType(); 1538d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 1548d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(Demanded & C->getValue(), 1558d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt VT)); 1568d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return CombineTo(Op, New); 1578d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 1588d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt break; 1598d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 1608d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; 1618d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 1628d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1638d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1648d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// DemandedMask bits of the result of Op are ever used downstream. If we can 1658d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// use this information to simplify Op, create a new simplified DAG node and 1668d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// return true, returning the original and new nodes in Old and New. Otherwise, 1678d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// analyze the expression and return a mask of KnownOne and KnownZero bits for 1688d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// the expression (used to simplify the caller). The KnownZero/One bits may 1698d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// only be accurate for those bits in the DemandedMask. 1708d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtbool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 1718d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint64_t &KnownZero, 1728d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint64_t &KnownOne, 1738d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt TargetLoweringOpt &TLO, 1748d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned Depth) const { 1758d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownZero = KnownOne = 0; // Don't know anything. 1768d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Other users may use these bits. 1778d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!Op.Val->hasOneUse()) { 1788d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (Depth != 0) { 1798d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If not at the root, Just compute the KnownZero/KnownOne bits to 1808d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // simplify things downstream. 1818d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 1828d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; 1838d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 1848d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If this is the root being simplified, allow it to have multiple uses, 1858d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // just set the DemandedMask to all bits. 1868d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DemandedMask = MVT::getIntVTBitMask(Op.getValueType()); 1878d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } else if (DemandedMask == 0) { 1888d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Not demanding any bits from Op. 1898d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (Op.getOpcode() != ISD::UNDEF) 1908d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 1918d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; 1928d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } else if (Depth == 6) { // Limit search depth. 1938d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; 1948d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 1958d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1968d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1978d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt switch (Op.getOpcode()) { 1988d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::Constant: 1998d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // We know all of the bits for a constant! 2008d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask; 2018d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownZero = ~KnownOne & DemandedMask; 2028d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; 2038d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::AND: 2048d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If either the LHS or the RHS are Zero, the result is zero. 2058d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 2068d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownOne, TLO, Depth+1)) 2078d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 2088d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 2098d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If something is known zero on the RHS, the bits aren't demanded on the 2108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // LHS. 2118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero, 2128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownZero2, KnownOne2, TLO, Depth+1)) 2138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 2148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 2158d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If all of the demanded bits are known one on one side, return the other. 2178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // These bits cannot contribute to the result of the 'and'. 2188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2)) 2198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return TLO.CombineTo(Op, Op.getOperand(0)); 220c28170251eb54dbf64a9074a07fee377587425b2Dmitry Shmidt if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero)) 2218d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return TLO.CombineTo(Op, Op.getOperand(1)); 2228d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If all of the demanded bits in the inputs are known zeros, return zero. 2238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask) 2248d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 2258d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If the RHS is a constant, see if we can simplify it. 2268d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2)) 2278d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 2288d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2298d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Output known-1 bits are only known if set in both the LHS & RHS. 2308d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownOne &= KnownOne2; 2318d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Output known-0 are known to be clear if zero in either the LHS | RHS. 2328d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownZero |= KnownZero2; 2338d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt break; 2348d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::OR: 2358d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 2368d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownOne, TLO, Depth+1)) 2378d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 2388d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 2398d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne, 2408d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownZero2, KnownOne2, TLO, Depth+1)) 2418d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 2428d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 2438d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2448d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If all of the demanded bits are known zero on one side, return the other. 2458d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // These bits cannot contribute to the result of the 'or'. 2468d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2)) 2478d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return TLO.CombineTo(Op, Op.getOperand(0)); 2488d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne)) 2498d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return TLO.CombineTo(Op, Op.getOperand(1)); 2508d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If all of the potentially set bits on one side are known to be set on 2518d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // the other side, just use the 'other' side. 2528d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((DemandedMask & (~KnownZero) & KnownOne2) == 2538d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt (DemandedMask & (~KnownZero))) 2548d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return TLO.CombineTo(Op, Op.getOperand(0)); 2558d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((DemandedMask & (~KnownZero2) & KnownOne) == 2568d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt (DemandedMask & (~KnownZero2))) 2578d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return TLO.CombineTo(Op, Op.getOperand(1)); 2588d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If the RHS is a constant, see if we can simplify it. 2598d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 2608d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 2618d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2628d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Output known-0 bits are only known if clear in both the LHS & RHS. 2638d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownZero &= KnownZero2; 2648d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Output known-1 are known to be set if set in either the LHS | RHS. 2658d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownOne |= KnownOne2; 2668d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt break; 2678d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::XOR: 2688d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 2698d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownOne, TLO, Depth+1)) 2708d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 2718d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 2728d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2, 2738d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownOne2, TLO, Depth+1)) 2748d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 2758d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 2768d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2778d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If all of the demanded bits are known zero on one side, return the other. 2788d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // These bits cannot contribute to the result of the 'xor'. 2798d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((DemandedMask & KnownZero) == DemandedMask) 2808d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return TLO.CombineTo(Op, Op.getOperand(0)); 2818d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((DemandedMask & KnownZero2) == DemandedMask) 2828d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return TLO.CombineTo(Op, Op.getOperand(1)); 2838d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2848d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Output known-0 bits are known if clear or set in both the LHS & RHS. 2858d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 2868d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Output known-1 are known to be set if set in only one of the LHS, RHS. 2878d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 2888d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2898d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If all of the unknown bits are known to be zero on one side or the other 2908d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // (but not both) turn this into an *inclusive* or. 2918d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 2928d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (uint64_t UnknownBits = DemandedMask & ~(KnownZeroOut|KnownOneOut)) 2938d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((UnknownBits & (KnownZero|KnownZero2)) == UnknownBits) 2948d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 2958d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Op.getOperand(0), 2968d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Op.getOperand(1))); 2978d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If all of the demanded bits on one side are known, and all of the set 2988d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // bits on that side are also known to be set on the other side, turn this 2998d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // into an AND, as we know the bits will be cleared. 3008d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 3018d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known 3028d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((KnownOne & KnownOne2) == KnownOne) { 3038d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::ValueType VT = Op.getValueType(); 3048d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT); 3058d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 3068d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ANDC)); 3078d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 3088d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 3098d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 3108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If the RHS is a constant, see if we can simplify it. 3118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. 3128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 3138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 3148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 315c28170251eb54dbf64a9074a07fee377587425b2Dmitry Shmidt KnownZero = KnownZeroOut; 3168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownOne = KnownOneOut; 3178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt break; 3188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::SETCC: 3198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If we know the result of a setcc has the top bits zero, use this info. 3208d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 3218d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 3228d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt break; 3238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::SELECT: 324 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero, 325 KnownOne, TLO, Depth+1)) 326 return true; 327 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2, 328 KnownOne2, TLO, Depth+1)) 329 return true; 330 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 331 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 332 333 // If the operands are constants, see if we can simplify them. 334 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 335 return true; 336 337 // Only known if known in both the LHS and RHS. 338 KnownOne &= KnownOne2; 339 KnownZero &= KnownZero2; 340 break; 341 case ISD::SHL: 342 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 343 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> SA->getValue(), 344 KnownZero, KnownOne, TLO, Depth+1)) 345 return true; 346 KnownZero <<= SA->getValue(); 347 KnownOne <<= SA->getValue(); 348 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 349 } 350 break; 351 case ISD::SRL: 352 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 353 MVT::ValueType VT = Op.getValueType(); 354 unsigned ShAmt = SA->getValue(); 355 356 // Compute the new bits that are at the top now. 357 uint64_t HighBits = (1ULL << ShAmt)-1; 358 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 359 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 360 361 if (SimplifyDemandedBits(Op.getOperand(0), 362 (DemandedMask << ShAmt) & TypeMask, 363 KnownZero, KnownOne, TLO, Depth+1)) 364 return true; 365 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 366 KnownZero &= TypeMask; 367 KnownOne &= TypeMask; 368 KnownZero >>= ShAmt; 369 KnownOne >>= ShAmt; 370 KnownZero |= HighBits; // high bits known zero. 371 } 372 break; 373 case ISD::SRA: 374 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 375 MVT::ValueType VT = Op.getValueType(); 376 unsigned ShAmt = SA->getValue(); 377 378 // Compute the new bits that are at the top now. 379 uint64_t HighBits = (1ULL << ShAmt)-1; 380 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 381 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 382 383 if (SimplifyDemandedBits(Op.getOperand(0), 384 (DemandedMask << ShAmt) & TypeMask, 385 KnownZero, KnownOne, TLO, Depth+1)) 386 return true; 387 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 388 KnownZero &= TypeMask; 389 KnownOne &= TypeMask; 390 KnownZero >>= SA->getValue(); 391 KnownOne >>= SA->getValue(); 392 393 // Handle the sign bits. 394 uint64_t SignBit = MVT::getIntVTSignBit(VT); 395 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask. 396 397 // If the input sign bit is known to be zero, or if none of the top bits 398 // are demanded, turn this into an unsigned shift right. 399 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) { 400 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 401 Op.getOperand(1))); 402 } else if (KnownOne & SignBit) { // New bits are known one. 403 KnownOne |= HighBits; 404 } 405 } 406 break; 407 case ISD::SIGN_EXTEND_INREG: { 408 MVT::ValueType VT = Op.getValueType(); 409 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 410 411 // Sign or Zero extension. Compute the bits in the result that are not 412 // present in the input. 413 uint64_t NotIn = ~MVT::getIntVTBitMask(EVT); 414 uint64_t NewBits = MVT::getIntVTBitMask(VT) & NotIn; 415 416 // Sign extension. 417 uint64_t InSignBit = MVT::getIntVTSignBit(EVT); 418 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT); 419 420 // If any of the sign extended bits are demanded, we know that the sign 421 // bit is demanded. 422 if (NewBits & DemandedMask) 423 InputDemandedBits |= InSignBit; 424 425 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 426 KnownZero, KnownOne, TLO, Depth+1)) 427 return true; 428 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 429 430 // If the sign bit of the input is known set or clear, then we know the 431 // top bits of the result. 432 433 // If the input sign bit is known zero, or if the NewBits are not demanded 434 // convert this into a zero extension. 435 if ((KnownZero & InSignBit) || (NewBits & ~DemandedMask) == NewBits) { 436 return TLO.CombineTo(Op, Op.getOperand(0)); 437 } else if (KnownOne & InSignBit) { // Input sign bit known set 438 KnownOne |= NewBits; 439 KnownZero &= ~NewBits; 440 } else { // Input sign bit unknown 441 KnownZero &= ~NewBits; 442 KnownOne &= ~NewBits; 443 } 444 break; 445 } 446 case ISD::ADD: 447 if (ConstantSDNode *AA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 448 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero, 449 KnownOne, TLO, Depth+1)) 450 return true; 451 // Compute the KnownOne/KnownZero masks for the constant, so we can set 452 // KnownZero appropriately if we're adding a constant that has all low 453 // bits cleared. 454 ComputeMaskedBits(Op.getOperand(1), 455 MVT::getIntVTBitMask(Op.getValueType()), 456 KnownZero2, KnownOne2, Depth+1); 457 458 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero), 459 CountTrailingZeros_64(~KnownZero2)); 460 KnownZero = (1ULL << KnownZeroOut) - 1; 461 KnownOne = 0; 462 463 SDOperand SH = Op.getOperand(0); 464 // fold (add (shl x, c1), (shl c2, c1)) -> (shl (add x, c2), c1) 465 if (KnownZero && SH.getOpcode() == ISD::SHL && SH.Val->hasOneUse() && 466 Op.Val->hasOneUse()) { 467 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(SH.getOperand(1))) { 468 MVT::ValueType VT = Op.getValueType(); 469 unsigned ShiftAmt = SA->getValue(); 470 uint64_t AddAmt = AA->getValue(); 471 uint64_t AddShr = AddAmt >> ShiftAmt; 472 if (AddAmt == (AddShr << ShiftAmt)) { 473 SDOperand ADD = TLO.DAG.getNode(ISD::ADD, VT, SH.getOperand(0), 474 TLO.DAG.getConstant(AddShr, VT)); 475 SDOperand SHL = TLO.DAG.getNode(ISD::SHL, VT, ADD,SH.getOperand(1)); 476 return TLO.CombineTo(Op, SHL); 477 } 478 } 479 } 480 } 481 break; 482 case ISD::CTTZ: 483 case ISD::CTLZ: 484 case ISD::CTPOP: { 485 MVT::ValueType VT = Op.getValueType(); 486 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 487 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 488 KnownOne = 0; 489 break; 490 } 491 } 492 return false; 493} 494 495/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 496/// this predicate to simplify operations downstream. Mask is known to be zero 497/// for bits that V cannot have. 498bool TargetLowering::MaskedValueIsZero(SDOperand Op, uint64_t Mask, 499 unsigned Depth) const { 500 uint64_t KnownZero, KnownOne; 501 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 502 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 503 return (KnownZero & Mask) == Mask; 504} 505 506/// ComputeMaskedBits - Determine which of the bits specified in Mask are 507/// known to be either zero or one and return them in the KnownZero/KnownOne 508/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 509/// processing. 510void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask, 511 uint64_t &KnownZero, uint64_t &KnownOne, 512 unsigned Depth) const { 513 KnownZero = KnownOne = 0; // Don't know anything. 514 if (Depth == 6 || Mask == 0) 515 return; // Limit search depth. 516 517 uint64_t KnownZero2, KnownOne2; 518 519 switch (Op.getOpcode()) { 520 case ISD::Constant: 521 // We know all of the bits for a constant! 522 KnownOne = cast<ConstantSDNode>(Op)->getValue() & Mask; 523 KnownZero = ~KnownOne & Mask; 524 return; 525 case ISD::AND: 526 // If either the LHS or the RHS are Zero, the result is zero. 527 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 528 Mask &= ~KnownZero; 529 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 530 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 531 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 532 533 // Output known-1 bits are only known if set in both the LHS & RHS. 534 KnownOne &= KnownOne2; 535 // Output known-0 are known to be clear if zero in either the LHS | RHS. 536 KnownZero |= KnownZero2; 537 return; 538 case ISD::OR: 539 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 540 Mask &= ~KnownOne; 541 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 542 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 543 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 544 545 // Output known-0 bits are only known if clear in both the LHS & RHS. 546 KnownZero &= KnownZero2; 547 // Output known-1 are known to be set if set in either the LHS | RHS. 548 KnownOne |= KnownOne2; 549 return; 550 case ISD::XOR: { 551 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 552 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 553 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 554 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 555 556 // Output known-0 bits are known if clear or set in both the LHS & RHS. 557 uint64_t KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 558 // Output known-1 are known to be set if set in only one of the LHS, RHS. 559 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 560 KnownZero = KnownZeroOut; 561 return; 562 } 563 case ISD::SELECT: 564 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 565 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 566 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 567 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 568 569 // Only known if known in both the LHS and RHS. 570 KnownOne &= KnownOne2; 571 KnownZero &= KnownZero2; 572 return; 573 case ISD::SELECT_CC: 574 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 575 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 576 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 577 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 578 579 // Only known if known in both the LHS and RHS. 580 KnownOne &= KnownOne2; 581 KnownZero &= KnownZero2; 582 return; 583 case ISD::SETCC: 584 // If we know the result of a setcc has the top bits zero, use this info. 585 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 586 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 587 return; 588 case ISD::SHL: 589 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 590 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 591 Mask >>= SA->getValue(); 592 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 593 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 594 KnownZero <<= SA->getValue(); 595 KnownOne <<= SA->getValue(); 596 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 597 } 598 return; 599 case ISD::SRL: 600 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 601 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 602 uint64_t HighBits = (1ULL << SA->getValue())-1; 603 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue(); 604 Mask <<= SA->getValue(); 605 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 606 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 607 KnownZero >>= SA->getValue(); 608 KnownOne >>= SA->getValue(); 609 KnownZero |= HighBits; // high bits known zero. 610 } 611 return; 612 case ISD::SRA: 613 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 614 uint64_t HighBits = (1ULL << SA->getValue())-1; 615 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue(); 616 Mask <<= SA->getValue(); 617 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 618 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 619 KnownZero >>= SA->getValue(); 620 KnownOne >>= SA->getValue(); 621 622 // Handle the sign bits. 623 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(Op.getValueType())-1); 624 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask. 625 626 if (KnownZero & SignBit) { // New bits are known zero. 627 KnownZero |= HighBits; 628 } else if (KnownOne & SignBit) { // New bits are known one. 629 KnownOne |= HighBits; 630 } 631 } 632 return; 633 case ISD::CTTZ: 634 case ISD::CTLZ: 635 case ISD::CTPOP: { 636 MVT::ValueType VT = Op.getValueType(); 637 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 638 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 639 KnownOne = 0; 640 return; 641 } 642 case ISD::ZEXTLOAD: { 643 unsigned SrcBits = 644 MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 645 KnownZero |= ~((1ULL << SrcBits)-1); 646 return; 647 } 648 case ISD::ZERO_EXTEND: { 649 unsigned SrcBits = 650 MVT::getSizeInBits(Op.getOperand(0).getValueType()); 651 KnownZero |= ~((1ULL << SrcBits)-1); 652 return; 653 } 654 case ISD::ANY_EXTEND: { 655 unsigned SrcBits = 656 MVT::getSizeInBits(Op.getOperand(0).getValueType()); 657 KnownZero &= ((1ULL << SrcBits)-1); 658 KnownOne &= ((1ULL << SrcBits)-1); 659 return; 660 } 661 case ISD::AssertZext: { 662 unsigned SrcBits = 663 MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 664 KnownZero |= ~((1ULL << SrcBits)-1); 665 return; 666 } 667 case ISD::ADD: { 668 // If either the LHS or the RHS are Zero, the result is zero. 669 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 670 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 671 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 672 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 673 674 // Output known-0 bits are known if clear or set in both the low clear bits 675 // common to both LHS & RHS; 676 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero), 677 CountTrailingZeros_64(~KnownZero2)); 678 679 KnownZero = (1ULL << KnownZeroOut) - 1; 680 KnownOne = 0; 681 return; 682 } 683 case ISD::SUB: 684 // We know that the top bits of C-X are clear if X contains less bits 685 // than C (i.e. no wrap-around can happen). For example, 20-X is 686 // positive if we can prove that X is >= 0 and < 16. 687 return; 688 default: 689 // Allow the target to implement this method for its nodes. 690 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) 691 computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne); 692 return; 693 } 694} 695 696/// computeMaskedBitsForTargetNode - Determine which of the bits specified 697/// in Mask are known to be either zero or one and return them in the 698/// KnownZero/KnownOne bitsets. 699void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 700 uint64_t Mask, 701 uint64_t &KnownZero, 702 uint64_t &KnownOne, 703 unsigned Depth) const { 704 assert(Op.getOpcode() >= ISD::BUILTIN_OP_END && 705 "Should use MaskedValueIsZero if you don't know whether Op" 706 " is a target node!"); 707 KnownZero = 0; 708 KnownOne = 0; 709} 710 711//===----------------------------------------------------------------------===// 712// Inline Assembler Implementation Methods 713//===----------------------------------------------------------------------===// 714 715TargetLowering::ConstraintType 716TargetLowering::getConstraintType(char ConstraintLetter) const { 717 // FIXME: lots more standard ones to handle. 718 switch (ConstraintLetter) { 719 default: return C_Unknown; 720 case 'r': return C_RegisterClass; 721 case 'm': // memory 722 case 'o': // offsetable 723 case 'V': // not offsetable 724 return C_Memory; 725 case 'i': // Simple Integer or Relocatable Constant 726 case 'n': // Simple Integer 727 case 's': // Relocatable Constant 728 case 'I': // Target registers. 729 case 'J': 730 case 'K': 731 case 'L': 732 case 'M': 733 case 'N': 734 case 'O': 735 case 'P': 736 return C_Other; 737 } 738} 739 740bool TargetLowering::isOperandValidForConstraint(SDOperand Op, 741 char ConstraintLetter) { 742 switch (ConstraintLetter) { 743 default: return false; 744 case 'i': // Simple Integer or Relocatable Constant 745 case 'n': // Simple Integer 746 case 's': // Relocatable Constant 747 return true; // FIXME: not right. 748 } 749} 750 751 752std::vector<unsigned> TargetLowering:: 753getRegClassForInlineAsmConstraint(const std::string &Constraint, 754 MVT::ValueType VT) const { 755 return std::vector<unsigned>(); 756} 757 758 759std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 760getRegForInlineAsmConstraint(const std::string &Constraint, 761 MVT::ValueType VT) const { 762 if (Constraint[0] != '{') 763 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 764 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 765 766 // Remove the braces from around the name. 767 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 768 769 // Figure out which register class contains this reg. 770 const MRegisterInfo *RI = TM.getRegisterInfo(); 771 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 772 E = RI->regclass_end(); RCI != E; ++RCI) { 773 const TargetRegisterClass *RC = *RCI; 774 775 // If none of the the value types for this register class are valid, we 776 // can't use it. For example, 64-bit reg classes on 32-bit targets. 777 bool isLegal = false; 778 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 779 I != E; ++I) { 780 if (isTypeLegal(*I)) { 781 isLegal = true; 782 break; 783 } 784 } 785 786 if (!isLegal) continue; 787 788 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 789 I != E; ++I) { 790 if (StringsEqualNoCase(RegName, RI->get(*I).Name)) 791 return std::make_pair(*I, RC); 792 } 793 } 794 795 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 796} 797