TargetLowering.cpp revision 2dfdefd282a04785c4d7b43e37782ace65af2ba6
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/Target/TargetSubtarget.h" 16#include "llvm/Target/TargetData.h" 17#include "llvm/Target/TargetMachine.h" 18#include "llvm/Target/MRegisterInfo.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/ADT/StringExtras.h" 22#include "llvm/ADT/STLExtras.h" 23#include "llvm/Support/MathExtras.h" 24#include "llvm/Target/TargetAsmInfo.h" 25#include "llvm/CallingConv.h" 26using namespace llvm; 27 28/// InitLibcallNames - Set default libcall names. 29/// 30static void InitLibcallNames(const char **Names) { 31 Names[RTLIB::SHL_I32] = "__ashlsi3"; 32 Names[RTLIB::SHL_I64] = "__ashldi3"; 33 Names[RTLIB::SRL_I32] = "__lshrsi3"; 34 Names[RTLIB::SRL_I64] = "__lshrdi3"; 35 Names[RTLIB::SRA_I32] = "__ashrsi3"; 36 Names[RTLIB::SRA_I64] = "__ashrdi3"; 37 Names[RTLIB::MUL_I32] = "__mulsi3"; 38 Names[RTLIB::MUL_I64] = "__muldi3"; 39 Names[RTLIB::SDIV_I32] = "__divsi3"; 40 Names[RTLIB::SDIV_I64] = "__divdi3"; 41 Names[RTLIB::UDIV_I32] = "__udivsi3"; 42 Names[RTLIB::UDIV_I64] = "__udivdi3"; 43 Names[RTLIB::SREM_I32] = "__modsi3"; 44 Names[RTLIB::SREM_I64] = "__moddi3"; 45 Names[RTLIB::UREM_I32] = "__umodsi3"; 46 Names[RTLIB::UREM_I64] = "__umoddi3"; 47 Names[RTLIB::NEG_I32] = "__negsi2"; 48 Names[RTLIB::NEG_I64] = "__negdi2"; 49 Names[RTLIB::ADD_F32] = "__addsf3"; 50 Names[RTLIB::ADD_F64] = "__adddf3"; 51 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 52 Names[RTLIB::SUB_F32] = "__subsf3"; 53 Names[RTLIB::SUB_F64] = "__subdf3"; 54 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 55 Names[RTLIB::MUL_F32] = "__mulsf3"; 56 Names[RTLIB::MUL_F64] = "__muldf3"; 57 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 58 Names[RTLIB::DIV_F32] = "__divsf3"; 59 Names[RTLIB::DIV_F64] = "__divdf3"; 60 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 61 Names[RTLIB::REM_F32] = "fmodf"; 62 Names[RTLIB::REM_F64] = "fmod"; 63 Names[RTLIB::REM_PPCF128] = "fmodl"; 64 Names[RTLIB::NEG_F32] = "__negsf2"; 65 Names[RTLIB::NEG_F64] = "__negdf2"; 66 Names[RTLIB::POWI_F32] = "__powisf2"; 67 Names[RTLIB::POWI_F64] = "__powidf2"; 68 Names[RTLIB::POWI_F80] = "__powixf2"; 69 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 70 Names[RTLIB::SQRT_F32] = "sqrtf"; 71 Names[RTLIB::SQRT_F64] = "sqrt"; 72 Names[RTLIB::SQRT_F80] = "sqrtl"; 73 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 74 Names[RTLIB::SIN_F32] = "sinf"; 75 Names[RTLIB::SIN_F64] = "sin"; 76 Names[RTLIB::COS_F32] = "cosf"; 77 Names[RTLIB::COS_F64] = "cos"; 78 Names[RTLIB::POW_F32] = "powf"; 79 Names[RTLIB::POW_F64] = "pow"; 80 Names[RTLIB::POW_F80] = "powl"; 81 Names[RTLIB::POW_PPCF128] = "powl"; 82 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 83 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 84 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 85 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 86 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 87 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 88 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 89 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 90 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 91 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 92 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 93 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 94 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 95 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 96 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 97 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 98 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 99 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 100 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 101 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 102 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 103 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 104 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 105 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 106 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 107 Names[RTLIB::OEQ_F32] = "__eqsf2"; 108 Names[RTLIB::OEQ_F64] = "__eqdf2"; 109 Names[RTLIB::UNE_F32] = "__nesf2"; 110 Names[RTLIB::UNE_F64] = "__nedf2"; 111 Names[RTLIB::OGE_F32] = "__gesf2"; 112 Names[RTLIB::OGE_F64] = "__gedf2"; 113 Names[RTLIB::OLT_F32] = "__ltsf2"; 114 Names[RTLIB::OLT_F64] = "__ltdf2"; 115 Names[RTLIB::OLE_F32] = "__lesf2"; 116 Names[RTLIB::OLE_F64] = "__ledf2"; 117 Names[RTLIB::OGT_F32] = "__gtsf2"; 118 Names[RTLIB::OGT_F64] = "__gtdf2"; 119 Names[RTLIB::UO_F32] = "__unordsf2"; 120 Names[RTLIB::UO_F64] = "__unorddf2"; 121 Names[RTLIB::O_F32] = "__unordsf2"; 122 Names[RTLIB::O_F64] = "__unorddf2"; 123} 124 125/// InitCmpLibcallCCs - Set default comparison libcall CC. 126/// 127static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 128 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 129 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 130 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 131 CCs[RTLIB::UNE_F32] = ISD::SETNE; 132 CCs[RTLIB::UNE_F64] = ISD::SETNE; 133 CCs[RTLIB::OGE_F32] = ISD::SETGE; 134 CCs[RTLIB::OGE_F64] = ISD::SETGE; 135 CCs[RTLIB::OLT_F32] = ISD::SETLT; 136 CCs[RTLIB::OLT_F64] = ISD::SETLT; 137 CCs[RTLIB::OLE_F32] = ISD::SETLE; 138 CCs[RTLIB::OLE_F64] = ISD::SETLE; 139 CCs[RTLIB::OGT_F32] = ISD::SETGT; 140 CCs[RTLIB::OGT_F64] = ISD::SETGT; 141 CCs[RTLIB::UO_F32] = ISD::SETNE; 142 CCs[RTLIB::UO_F64] = ISD::SETNE; 143 CCs[RTLIB::O_F32] = ISD::SETEQ; 144 CCs[RTLIB::O_F64] = ISD::SETEQ; 145} 146 147TargetLowering::TargetLowering(TargetMachine &tm) 148 : TM(tm), TD(TM.getTargetData()) { 149 assert(ISD::BUILTIN_OP_END <= 156 && 150 "Fixed size array in TargetLowering is not large enough!"); 151 // All operations default to being supported. 152 memset(OpActions, 0, sizeof(OpActions)); 153 memset(LoadXActions, 0, sizeof(LoadXActions)); 154 memset(&StoreXActions, 0, sizeof(StoreXActions)); 155 memset(&IndexedModeActions, 0, sizeof(IndexedModeActions)); 156 memset(&ConvertActions, 0, sizeof(ConvertActions)); 157 158 // Set all indexed load / store to expand. 159 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 160 for (unsigned IM = (unsigned)ISD::PRE_INC; 161 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 162 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand); 163 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand); 164 } 165 } 166 167 IsLittleEndian = TD->isLittleEndian(); 168 UsesGlobalOffsetTable = false; 169 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType()); 170 ShiftAmtHandling = Undefined; 171 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 172 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 173 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 174 allowUnalignedMemoryAccesses = false; 175 UseUnderscoreSetJmp = false; 176 UseUnderscoreLongJmp = false; 177 SelectIsExpensive = false; 178 IntDivIsCheap = false; 179 Pow2DivIsCheap = false; 180 StackPointerRegisterToSaveRestore = 0; 181 ExceptionPointerRegister = 0; 182 ExceptionSelectorRegister = 0; 183 SetCCResultContents = UndefinedSetCCResult; 184 SchedPreferenceInfo = SchedulingForLatency; 185 JumpBufSize = 0; 186 JumpBufAlignment = 0; 187 IfCvtBlockSizeLimit = 2; 188 189 InitLibcallNames(LibcallRoutineNames); 190 InitCmpLibcallCCs(CmpLibcallCCs); 191 192 // Tell Legalize whether the assembler supports DEBUG_LOC. 193 if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile()) 194 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 195} 196 197TargetLowering::~TargetLowering() {} 198 199 200SDOperand TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) { 201 assert(getSubtarget() && "Subtarget not defined"); 202 SDOperand ChainOp = Op.getOperand(0); 203 SDOperand DestOp = Op.getOperand(1); 204 SDOperand SourceOp = Op.getOperand(2); 205 SDOperand CountOp = Op.getOperand(3); 206 SDOperand AlignOp = Op.getOperand(4); 207 SDOperand AlwaysInlineOp = Op.getOperand(5); 208 209 bool AlwaysInline = (bool)cast<ConstantSDNode>(AlwaysInlineOp)->getValue(); 210 unsigned Align = (unsigned)cast<ConstantSDNode>(AlignOp)->getValue(); 211 if (Align == 0) Align = 1; 212 213 // If size is unknown, call memcpy. 214 ConstantSDNode *I = dyn_cast<ConstantSDNode>(CountOp); 215 if (!I) { 216 assert(!AlwaysInline && "Cannot inline copy of unknown size"); 217 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG); 218 } 219 220 // If not DWORD aligned or if size is more than threshold, then call memcpy. 221 // The libc version is likely to be faster for the following cases. It can 222 // use the address value and run time information about the CPU. 223 // With glibc 2.6.1 on a core 2, coping an array of 100M longs was 30% faster 224 unsigned Size = I->getValue(); 225 if (AlwaysInline || 226 (Size <= getSubtarget()->getMaxInlineSizeThreshold() && 227 (Align & 3) == 0)) 228 return LowerMEMCPYInline(ChainOp, DestOp, SourceOp, Size, Align, DAG); 229 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG); 230} 231 232 233SDOperand TargetLowering::LowerMEMCPYCall(SDOperand Chain, 234 SDOperand Dest, 235 SDOperand Source, 236 SDOperand Count, 237 SelectionDAG &DAG) { 238 MVT::ValueType IntPtr = getPointerTy(); 239 TargetLowering::ArgListTy Args; 240 TargetLowering::ArgListEntry Entry; 241 Entry.Ty = getTargetData()->getIntPtrType(); 242 Entry.Node = Dest; Args.push_back(Entry); 243 Entry.Node = Source; Args.push_back(Entry); 244 Entry.Node = Count; Args.push_back(Entry); 245 std::pair<SDOperand,SDOperand> CallResult = 246 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false, 247 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG); 248 return CallResult.second; 249} 250 251 252/// computeRegisterProperties - Once all of the register classes are added, 253/// this allows us to compute derived properties we expose. 254void TargetLowering::computeRegisterProperties() { 255 assert(MVT::LAST_VALUETYPE <= 32 && 256 "Too many value types for ValueTypeActions to hold!"); 257 258 // Everything defaults to needing one register. 259 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 260 NumRegistersForVT[i] = 1; 261 RegisterTypeForVT[i] = TransformToType[i] = i; 262 } 263 // ...except isVoid, which doesn't need any registers. 264 NumRegistersForVT[MVT::isVoid] = 0; 265 266 // Find the largest integer register class. 267 unsigned LargestIntReg = MVT::i128; 268 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 269 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 270 271 // Every integer value type larger than this largest register takes twice as 272 // many registers to represent as the previous ValueType. 273 for (MVT::ValueType ExpandedReg = LargestIntReg + 1; 274 MVT::isInteger(ExpandedReg); ++ExpandedReg) { 275 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 276 RegisterTypeForVT[ExpandedReg] = LargestIntReg; 277 TransformToType[ExpandedReg] = ExpandedReg - 1; 278 ValueTypeActions.setTypeAction(ExpandedReg, Expand); 279 } 280 281 // Inspect all of the ValueType's smaller than the largest integer 282 // register to see which ones need promotion. 283 MVT::ValueType LegalIntReg = LargestIntReg; 284 for (MVT::ValueType IntReg = LargestIntReg - 1; 285 IntReg >= MVT::i1; --IntReg) { 286 if (isTypeLegal(IntReg)) { 287 LegalIntReg = IntReg; 288 } else { 289 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg; 290 ValueTypeActions.setTypeAction(IntReg, Promote); 291 } 292 } 293 294 // ppcf128 type is really two f64's. 295 if (!isTypeLegal(MVT::ppcf128)) { 296 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 297 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 298 TransformToType[MVT::ppcf128] = MVT::f64; 299 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 300 } 301 302 // Decide how to handle f64. If the target does not have native f64 support, 303 // expand it to i64 and we will be generating soft float library calls. 304 if (!isTypeLegal(MVT::f64)) { 305 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 306 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 307 TransformToType[MVT::f64] = MVT::i64; 308 ValueTypeActions.setTypeAction(MVT::f64, Expand); 309 } 310 311 // Decide how to handle f32. If the target does not have native support for 312 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 313 if (!isTypeLegal(MVT::f32)) { 314 if (isTypeLegal(MVT::f64)) { 315 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 316 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 317 TransformToType[MVT::f32] = MVT::f64; 318 ValueTypeActions.setTypeAction(MVT::f32, Promote); 319 } else { 320 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 321 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 322 TransformToType[MVT::f32] = MVT::i32; 323 ValueTypeActions.setTypeAction(MVT::f32, Expand); 324 } 325 } 326 327 // Loop over all of the vector value types to see which need transformations. 328 for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE; 329 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 330 if (!isTypeLegal(i)) { 331 MVT::ValueType IntermediateVT, RegisterVT; 332 unsigned NumIntermediates; 333 NumRegistersForVT[i] = 334 getVectorTypeBreakdown(i, 335 IntermediateVT, NumIntermediates, 336 RegisterVT); 337 RegisterTypeForVT[i] = RegisterVT; 338 TransformToType[i] = MVT::Other; // this isn't actually used 339 ValueTypeActions.setTypeAction(i, Expand); 340 } 341 } 342} 343 344const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 345 return NULL; 346} 347 348/// getVectorTypeBreakdown - Vector types are broken down into some number of 349/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 350/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 351/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 352/// 353/// This method returns the number of registers needed, and the VT for each 354/// register. It also returns the VT and quantity of the intermediate values 355/// before they are promoted/expanded. 356/// 357unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT, 358 MVT::ValueType &IntermediateVT, 359 unsigned &NumIntermediates, 360 MVT::ValueType &RegisterVT) const { 361 // Figure out the right, legal destination reg to copy into. 362 unsigned NumElts = MVT::getVectorNumElements(VT); 363 MVT::ValueType EltTy = MVT::getVectorElementType(VT); 364 365 unsigned NumVectorRegs = 1; 366 367 // Divide the input until we get to a supported size. This will always 368 // end with a scalar if the target doesn't support vectors. 369 while (NumElts > 1 && 370 !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) { 371 NumElts >>= 1; 372 NumVectorRegs <<= 1; 373 } 374 375 NumIntermediates = NumVectorRegs; 376 377 MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts); 378 if (!isTypeLegal(NewVT)) 379 NewVT = EltTy; 380 IntermediateVT = NewVT; 381 382 MVT::ValueType DestVT = getTypeToTransformTo(NewVT); 383 RegisterVT = DestVT; 384 if (DestVT < NewVT) { 385 // Value is expanded, e.g. i64 -> i16. 386 return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT)); 387 } else { 388 // Otherwise, promotion or legal types use the same number of registers as 389 // the vector decimated to the appropriate level. 390 return NumVectorRegs; 391 } 392 393 return 1; 394} 395 396//===----------------------------------------------------------------------===// 397// Optimization Methods 398//===----------------------------------------------------------------------===// 399 400/// ShrinkDemandedConstant - Check to see if the specified operand of the 401/// specified instruction is a constant integer. If so, check to see if there 402/// are any bits set in the constant that are not demanded. If so, shrink the 403/// constant and return true. 404bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, 405 uint64_t Demanded) { 406 // FIXME: ISD::SELECT, ISD::SELECT_CC 407 switch(Op.getOpcode()) { 408 default: break; 409 case ISD::AND: 410 case ISD::OR: 411 case ISD::XOR: 412 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 413 if ((~Demanded & C->getValue()) != 0) { 414 MVT::ValueType VT = Op.getValueType(); 415 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 416 DAG.getConstant(Demanded & C->getValue(), 417 VT)); 418 return CombineTo(Op, New); 419 } 420 break; 421 } 422 return false; 423} 424 425/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 426/// DemandedMask bits of the result of Op are ever used downstream. If we can 427/// use this information to simplify Op, create a new simplified DAG node and 428/// return true, returning the original and new nodes in Old and New. Otherwise, 429/// analyze the expression and return a mask of KnownOne and KnownZero bits for 430/// the expression (used to simplify the caller). The KnownZero/One bits may 431/// only be accurate for those bits in the DemandedMask. 432bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 433 uint64_t &KnownZero, 434 uint64_t &KnownOne, 435 TargetLoweringOpt &TLO, 436 unsigned Depth) const { 437 KnownZero = KnownOne = 0; // Don't know anything. 438 439 // The masks are not wide enough to represent this type! Should use APInt. 440 if (Op.getValueType() == MVT::i128) 441 return false; 442 443 // Other users may use these bits. 444 if (!Op.Val->hasOneUse()) { 445 if (Depth != 0) { 446 // If not at the root, Just compute the KnownZero/KnownOne bits to 447 // simplify things downstream. 448 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 449 return false; 450 } 451 // If this is the root being simplified, allow it to have multiple uses, 452 // just set the DemandedMask to all bits. 453 DemandedMask = MVT::getIntVTBitMask(Op.getValueType()); 454 } else if (DemandedMask == 0) { 455 // Not demanding any bits from Op. 456 if (Op.getOpcode() != ISD::UNDEF) 457 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 458 return false; 459 } else if (Depth == 6) { // Limit search depth. 460 return false; 461 } 462 463 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 464 switch (Op.getOpcode()) { 465 case ISD::Constant: 466 // We know all of the bits for a constant! 467 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask; 468 KnownZero = ~KnownOne & DemandedMask; 469 return false; // Don't fall through, will infinitely loop. 470 case ISD::AND: 471 // If the RHS is a constant, check to see if the LHS would be zero without 472 // using the bits from the RHS. Below, we use knowledge about the RHS to 473 // simplify the LHS, here we're using information from the LHS to simplify 474 // the RHS. 475 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 476 uint64_t LHSZero, LHSOne; 477 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), DemandedMask, 478 LHSZero, LHSOne, Depth+1); 479 // If the LHS already has zeros where RHSC does, this and is dead. 480 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask)) 481 return TLO.CombineTo(Op, Op.getOperand(0)); 482 // If any of the set bits in the RHS are known zero on the LHS, shrink 483 // the constant. 484 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask)) 485 return true; 486 } 487 488 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 489 KnownOne, TLO, Depth+1)) 490 return true; 491 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 492 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero, 493 KnownZero2, KnownOne2, TLO, Depth+1)) 494 return true; 495 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 496 497 // If all of the demanded bits are known one on one side, return the other. 498 // These bits cannot contribute to the result of the 'and'. 499 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2)) 500 return TLO.CombineTo(Op, Op.getOperand(0)); 501 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero)) 502 return TLO.CombineTo(Op, Op.getOperand(1)); 503 // If all of the demanded bits in the inputs are known zeros, return zero. 504 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask) 505 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 506 // If the RHS is a constant, see if we can simplify it. 507 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2)) 508 return true; 509 510 // Output known-1 bits are only known if set in both the LHS & RHS. 511 KnownOne &= KnownOne2; 512 // Output known-0 are known to be clear if zero in either the LHS | RHS. 513 KnownZero |= KnownZero2; 514 break; 515 case ISD::OR: 516 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 517 KnownOne, TLO, Depth+1)) 518 return true; 519 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 520 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne, 521 KnownZero2, KnownOne2, TLO, Depth+1)) 522 return true; 523 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 524 525 // If all of the demanded bits are known zero on one side, return the other. 526 // These bits cannot contribute to the result of the 'or'. 527 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2)) 528 return TLO.CombineTo(Op, Op.getOperand(0)); 529 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne)) 530 return TLO.CombineTo(Op, Op.getOperand(1)); 531 // If all of the potentially set bits on one side are known to be set on 532 // the other side, just use the 'other' side. 533 if ((DemandedMask & (~KnownZero) & KnownOne2) == 534 (DemandedMask & (~KnownZero))) 535 return TLO.CombineTo(Op, Op.getOperand(0)); 536 if ((DemandedMask & (~KnownZero2) & KnownOne) == 537 (DemandedMask & (~KnownZero2))) 538 return TLO.CombineTo(Op, Op.getOperand(1)); 539 // If the RHS is a constant, see if we can simplify it. 540 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 541 return true; 542 543 // Output known-0 bits are only known if clear in both the LHS & RHS. 544 KnownZero &= KnownZero2; 545 // Output known-1 are known to be set if set in either the LHS | RHS. 546 KnownOne |= KnownOne2; 547 break; 548 case ISD::XOR: 549 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 550 KnownOne, TLO, Depth+1)) 551 return true; 552 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 553 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2, 554 KnownOne2, TLO, Depth+1)) 555 return true; 556 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 557 558 // If all of the demanded bits are known zero on one side, return the other. 559 // These bits cannot contribute to the result of the 'xor'. 560 if ((DemandedMask & KnownZero) == DemandedMask) 561 return TLO.CombineTo(Op, Op.getOperand(0)); 562 if ((DemandedMask & KnownZero2) == DemandedMask) 563 return TLO.CombineTo(Op, Op.getOperand(1)); 564 565 // If all of the unknown bits are known to be zero on one side or the other 566 // (but not both) turn this into an *inclusive* or. 567 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 568 if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0) 569 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 570 Op.getOperand(0), 571 Op.getOperand(1))); 572 573 // Output known-0 bits are known if clear or set in both the LHS & RHS. 574 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 575 // Output known-1 are known to be set if set in only one of the LHS, RHS. 576 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 577 578 // If all of the demanded bits on one side are known, and all of the set 579 // bits on that side are also known to be set on the other side, turn this 580 // into an AND, as we know the bits will be cleared. 581 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 582 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known 583 if ((KnownOne & KnownOne2) == KnownOne) { 584 MVT::ValueType VT = Op.getValueType(); 585 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT); 586 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 587 ANDC)); 588 } 589 } 590 591 // If the RHS is a constant, see if we can simplify it. 592 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. 593 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 594 return true; 595 596 KnownZero = KnownZeroOut; 597 KnownOne = KnownOneOut; 598 break; 599 case ISD::SETCC: 600 // If we know the result of a setcc has the top bits zero, use this info. 601 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 602 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 603 break; 604 case ISD::SELECT: 605 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero, 606 KnownOne, TLO, Depth+1)) 607 return true; 608 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2, 609 KnownOne2, TLO, Depth+1)) 610 return true; 611 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 612 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 613 614 // If the operands are constants, see if we can simplify them. 615 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 616 return true; 617 618 // Only known if known in both the LHS and RHS. 619 KnownOne &= KnownOne2; 620 KnownZero &= KnownZero2; 621 break; 622 case ISD::SELECT_CC: 623 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero, 624 KnownOne, TLO, Depth+1)) 625 return true; 626 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2, 627 KnownOne2, TLO, Depth+1)) 628 return true; 629 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 630 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 631 632 // If the operands are constants, see if we can simplify them. 633 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 634 return true; 635 636 // Only known if known in both the LHS and RHS. 637 KnownOne &= KnownOne2; 638 KnownZero &= KnownZero2; 639 break; 640 case ISD::SHL: 641 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 642 unsigned ShAmt = SA->getValue(); 643 SDOperand InOp = Op.getOperand(0); 644 645 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 646 // single shift. We can do this if the bottom bits (which are shifted 647 // out) are never demanded. 648 if (InOp.getOpcode() == ISD::SRL && 649 isa<ConstantSDNode>(InOp.getOperand(1))) { 650 if (ShAmt && (DemandedMask & ((1ULL << ShAmt)-1)) == 0) { 651 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 652 unsigned Opc = ISD::SHL; 653 int Diff = ShAmt-C1; 654 if (Diff < 0) { 655 Diff = -Diff; 656 Opc = ISD::SRL; 657 } 658 659 SDOperand NewSA = 660 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 661 MVT::ValueType VT = Op.getValueType(); 662 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 663 InOp.getOperand(0), NewSA)); 664 } 665 } 666 667 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> ShAmt, 668 KnownZero, KnownOne, TLO, Depth+1)) 669 return true; 670 KnownZero <<= SA->getValue(); 671 KnownOne <<= SA->getValue(); 672 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 673 } 674 break; 675 case ISD::SRL: 676 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 677 MVT::ValueType VT = Op.getValueType(); 678 unsigned ShAmt = SA->getValue(); 679 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 680 unsigned VTSize = MVT::getSizeInBits(VT); 681 SDOperand InOp = Op.getOperand(0); 682 683 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 684 // single shift. We can do this if the top bits (which are shifted out) 685 // are never demanded. 686 if (InOp.getOpcode() == ISD::SHL && 687 isa<ConstantSDNode>(InOp.getOperand(1))) { 688 if (ShAmt && (DemandedMask & (~0ULL << (VTSize-ShAmt))) == 0) { 689 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 690 unsigned Opc = ISD::SRL; 691 int Diff = ShAmt-C1; 692 if (Diff < 0) { 693 Diff = -Diff; 694 Opc = ISD::SHL; 695 } 696 697 SDOperand NewSA = 698 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 699 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 700 InOp.getOperand(0), NewSA)); 701 } 702 } 703 704 // Compute the new bits that are at the top now. 705 if (SimplifyDemandedBits(InOp, (DemandedMask << ShAmt) & TypeMask, 706 KnownZero, KnownOne, TLO, Depth+1)) 707 return true; 708 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 709 KnownZero &= TypeMask; 710 KnownOne &= TypeMask; 711 KnownZero >>= ShAmt; 712 KnownOne >>= ShAmt; 713 714 uint64_t HighBits = (1ULL << ShAmt)-1; 715 HighBits <<= VTSize - ShAmt; 716 KnownZero |= HighBits; // High bits known zero. 717 } 718 break; 719 case ISD::SRA: 720 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 721 MVT::ValueType VT = Op.getValueType(); 722 unsigned ShAmt = SA->getValue(); 723 724 // Compute the new bits that are at the top now. 725 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 726 727 uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask; 728 729 // If any of the demanded bits are produced by the sign extension, we also 730 // demand the input sign bit. 731 uint64_t HighBits = (1ULL << ShAmt)-1; 732 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 733 if (HighBits & DemandedMask) 734 InDemandedMask |= MVT::getIntVTSignBit(VT); 735 736 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 737 KnownZero, KnownOne, TLO, Depth+1)) 738 return true; 739 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 740 KnownZero &= TypeMask; 741 KnownOne &= TypeMask; 742 KnownZero >>= ShAmt; 743 KnownOne >>= ShAmt; 744 745 // Handle the sign bits. 746 uint64_t SignBit = MVT::getIntVTSignBit(VT); 747 SignBit >>= ShAmt; // Adjust to where it is now in the mask. 748 749 // If the input sign bit is known to be zero, or if none of the top bits 750 // are demanded, turn this into an unsigned shift right. 751 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) { 752 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 753 Op.getOperand(1))); 754 } else if (KnownOne & SignBit) { // New bits are known one. 755 KnownOne |= HighBits; 756 } 757 } 758 break; 759 case ISD::SIGN_EXTEND_INREG: { 760 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 761 762 // Sign extension. Compute the demanded bits in the result that are not 763 // present in the input. 764 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask; 765 766 // If none of the extended bits are demanded, eliminate the sextinreg. 767 if (NewBits == 0) 768 return TLO.CombineTo(Op, Op.getOperand(0)); 769 770 uint64_t InSignBit = MVT::getIntVTSignBit(EVT); 771 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT); 772 773 // Since the sign extended bits are demanded, we know that the sign 774 // bit is demanded. 775 InputDemandedBits |= InSignBit; 776 777 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 778 KnownZero, KnownOne, TLO, Depth+1)) 779 return true; 780 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 781 782 // If the sign bit of the input is known set or clear, then we know the 783 // top bits of the result. 784 785 // If the input sign bit is known zero, convert this into a zero extension. 786 if (KnownZero & InSignBit) 787 return TLO.CombineTo(Op, 788 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 789 790 if (KnownOne & InSignBit) { // Input sign bit known set 791 KnownOne |= NewBits; 792 KnownZero &= ~NewBits; 793 } else { // Input sign bit unknown 794 KnownZero &= ~NewBits; 795 KnownOne &= ~NewBits; 796 } 797 break; 798 } 799 case ISD::CTTZ: 800 case ISD::CTLZ: 801 case ISD::CTPOP: { 802 MVT::ValueType VT = Op.getValueType(); 803 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 804 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 805 KnownOne = 0; 806 break; 807 } 808 case ISD::LOAD: { 809 if (ISD::isZEXTLoad(Op.Val)) { 810 LoadSDNode *LD = cast<LoadSDNode>(Op); 811 MVT::ValueType VT = LD->getLoadedVT(); 812 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask; 813 } 814 break; 815 } 816 case ISD::ZERO_EXTEND: { 817 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 818 819 // If none of the top bits are demanded, convert this into an any_extend. 820 uint64_t NewBits = (~InMask) & DemandedMask; 821 if (NewBits == 0) 822 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 823 Op.getValueType(), 824 Op.getOperand(0))); 825 826 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 827 KnownZero, KnownOne, TLO, Depth+1)) 828 return true; 829 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 830 KnownZero |= NewBits; 831 break; 832 } 833 case ISD::SIGN_EXTEND: { 834 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 835 uint64_t InMask = MVT::getIntVTBitMask(InVT); 836 uint64_t InSignBit = MVT::getIntVTSignBit(InVT); 837 uint64_t NewBits = (~InMask) & DemandedMask; 838 839 // If none of the top bits are demanded, convert this into an any_extend. 840 if (NewBits == 0) 841 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 842 Op.getOperand(0))); 843 844 // Since some of the sign extended bits are demanded, we know that the sign 845 // bit is demanded. 846 uint64_t InDemandedBits = DemandedMask & InMask; 847 InDemandedBits |= InSignBit; 848 849 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 850 KnownOne, TLO, Depth+1)) 851 return true; 852 853 // If the sign bit is known zero, convert this to a zero extend. 854 if (KnownZero & InSignBit) 855 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 856 Op.getValueType(), 857 Op.getOperand(0))); 858 859 // If the sign bit is known one, the top bits match. 860 if (KnownOne & InSignBit) { 861 KnownOne |= NewBits; 862 KnownZero &= ~NewBits; 863 } else { // Otherwise, top bits aren't known. 864 KnownOne &= ~NewBits; 865 KnownZero &= ~NewBits; 866 } 867 break; 868 } 869 case ISD::ANY_EXTEND: { 870 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 871 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 872 KnownZero, KnownOne, TLO, Depth+1)) 873 return true; 874 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 875 break; 876 } 877 case ISD::TRUNCATE: { 878 // Simplify the input, using demanded bit information, and compute the known 879 // zero/one bits live out. 880 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, 881 KnownZero, KnownOne, TLO, Depth+1)) 882 return true; 883 884 // If the input is only used by this truncate, see if we can shrink it based 885 // on the known demanded bits. 886 if (Op.getOperand(0).Val->hasOneUse()) { 887 SDOperand In = Op.getOperand(0); 888 switch (In.getOpcode()) { 889 default: break; 890 case ISD::SRL: 891 // Shrink SRL by a constant if none of the high bits shifted in are 892 // demanded. 893 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 894 uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType()); 895 HighBits &= ~MVT::getIntVTBitMask(Op.getValueType()); 896 HighBits >>= ShAmt->getValue(); 897 898 if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) && 899 (DemandedMask & HighBits) == 0) { 900 // None of the shifted in bits are needed. Add a truncate of the 901 // shift input, then shift it. 902 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 903 Op.getValueType(), 904 In.getOperand(0)); 905 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), 906 NewTrunc, In.getOperand(1))); 907 } 908 } 909 break; 910 } 911 } 912 913 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 914 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType()); 915 KnownZero &= OutMask; 916 KnownOne &= OutMask; 917 break; 918 } 919 case ISD::AssertZext: { 920 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 921 uint64_t InMask = MVT::getIntVTBitMask(VT); 922 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 923 KnownZero, KnownOne, TLO, Depth+1)) 924 return true; 925 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 926 KnownZero |= ~InMask & DemandedMask; 927 break; 928 } 929 case ISD::ADD: 930 case ISD::SUB: 931 case ISD::INTRINSIC_WO_CHAIN: 932 case ISD::INTRINSIC_W_CHAIN: 933 case ISD::INTRINSIC_VOID: 934 // Just use ComputeMaskedBits to compute output bits. 935 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 936 break; 937 } 938 939 // If we know the value of all of the demanded bits, return this as a 940 // constant. 941 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) 942 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 943 944 return false; 945} 946 947/// computeMaskedBitsForTargetNode - Determine which of the bits specified 948/// in Mask are known to be either zero or one and return them in the 949/// KnownZero/KnownOne bitsets. 950void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 951 uint64_t Mask, 952 uint64_t &KnownZero, 953 uint64_t &KnownOne, 954 const SelectionDAG &DAG, 955 unsigned Depth) const { 956 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 957 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 958 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 959 Op.getOpcode() == ISD::INTRINSIC_VOID) && 960 "Should use MaskedValueIsZero if you don't know whether Op" 961 " is a target node!"); 962 KnownZero = 0; 963 KnownOne = 0; 964} 965 966/// ComputeNumSignBitsForTargetNode - This method can be implemented by 967/// targets that want to expose additional information about sign bits to the 968/// DAG Combiner. 969unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op, 970 unsigned Depth) const { 971 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 972 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 973 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 974 Op.getOpcode() == ISD::INTRINSIC_VOID) && 975 "Should use ComputeNumSignBits if you don't know whether Op" 976 " is a target node!"); 977 return 1; 978} 979 980 981/// SimplifySetCC - Try to simplify a setcc built with the specified operands 982/// and cc. If it is unable to simplify it, return a null SDOperand. 983SDOperand 984TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 985 ISD::CondCode Cond, bool foldBooleans, 986 DAGCombinerInfo &DCI) const { 987 SelectionDAG &DAG = DCI.DAG; 988 989 // These setcc operations always fold. 990 switch (Cond) { 991 default: break; 992 case ISD::SETFALSE: 993 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 994 case ISD::SETTRUE: 995 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 996 } 997 998 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 999 uint64_t C1 = N1C->getValue(); 1000 if (isa<ConstantSDNode>(N0.Val)) { 1001 return DAG.FoldSetCC(VT, N0, N1, Cond); 1002 } else { 1003 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1004 // equality comparison, then we're just comparing whether X itself is 1005 // zero. 1006 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1007 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1008 N0.getOperand(1).getOpcode() == ISD::Constant) { 1009 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1010 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1011 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) { 1012 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1013 // (srl (ctlz x), 5) == 0 -> X != 0 1014 // (srl (ctlz x), 5) != 1 -> X != 0 1015 Cond = ISD::SETNE; 1016 } else { 1017 // (srl (ctlz x), 5) != 0 -> X == 0 1018 // (srl (ctlz x), 5) == 1 -> X == 0 1019 Cond = ISD::SETEQ; 1020 } 1021 SDOperand Zero = DAG.getConstant(0, N0.getValueType()); 1022 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 1023 Zero, Cond); 1024 } 1025 } 1026 1027 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1028 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1029 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 1030 1031 // If the comparison constant has bits in the upper part, the 1032 // zero-extended value could never match. 1033 if (C1 & (~0ULL << InSize)) { 1034 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 1035 switch (Cond) { 1036 case ISD::SETUGT: 1037 case ISD::SETUGE: 1038 case ISD::SETEQ: return DAG.getConstant(0, VT); 1039 case ISD::SETULT: 1040 case ISD::SETULE: 1041 case ISD::SETNE: return DAG.getConstant(1, VT); 1042 case ISD::SETGT: 1043 case ISD::SETGE: 1044 // True if the sign bit of C1 is set. 1045 return DAG.getConstant((C1 & (1ULL << (VSize-1))) != 0, VT); 1046 case ISD::SETLT: 1047 case ISD::SETLE: 1048 // True if the sign bit of C1 isn't set. 1049 return DAG.getConstant((C1 & (1ULL << (VSize-1))) == 0, VT); 1050 default: 1051 break; 1052 } 1053 } 1054 1055 // Otherwise, we can perform the comparison with the low bits. 1056 switch (Cond) { 1057 case ISD::SETEQ: 1058 case ISD::SETNE: 1059 case ISD::SETUGT: 1060 case ISD::SETUGE: 1061 case ISD::SETULT: 1062 case ISD::SETULE: 1063 return DAG.getSetCC(VT, N0.getOperand(0), 1064 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 1065 Cond); 1066 default: 1067 break; // todo, be more careful with signed comparisons 1068 } 1069 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1070 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1071 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1072 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 1073 MVT::ValueType ExtDstTy = N0.getValueType(); 1074 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 1075 1076 // If the extended part has any inconsistent bits, it cannot ever 1077 // compare equal. In other words, they have to be all ones or all 1078 // zeros. 1079 uint64_t ExtBits = 1080 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 1081 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1082 return DAG.getConstant(Cond == ISD::SETNE, VT); 1083 1084 SDOperand ZextOp; 1085 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 1086 if (Op0Ty == ExtSrcTy) { 1087 ZextOp = N0.getOperand(0); 1088 } else { 1089 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 1090 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1091 DAG.getConstant(Imm, Op0Ty)); 1092 } 1093 if (!DCI.isCalledByLegalizer()) 1094 DCI.AddToWorklist(ZextOp.Val); 1095 // Otherwise, make this a use of a zext. 1096 return DAG.getSetCC(VT, ZextOp, 1097 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 1098 ExtDstTy), 1099 Cond); 1100 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 1101 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1102 1103 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1104 if (N0.getOpcode() == ISD::SETCC) { 1105 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1); 1106 if (TrueWhenTrue) 1107 return N0; 1108 1109 // Invert the condition. 1110 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1111 CC = ISD::getSetCCInverse(CC, 1112 MVT::isInteger(N0.getOperand(0).getValueType())); 1113 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); 1114 } 1115 1116 if ((N0.getOpcode() == ISD::XOR || 1117 (N0.getOpcode() == ISD::AND && 1118 N0.getOperand(0).getOpcode() == ISD::XOR && 1119 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1120 isa<ConstantSDNode>(N0.getOperand(1)) && 1121 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 1122 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1123 // can only do this if the top bits are known zero. 1124 if (DAG.MaskedValueIsZero(N0, 1125 MVT::getIntVTBitMask(N0.getValueType())-1)){ 1126 // Okay, get the un-inverted input value. 1127 SDOperand Val; 1128 if (N0.getOpcode() == ISD::XOR) 1129 Val = N0.getOperand(0); 1130 else { 1131 assert(N0.getOpcode() == ISD::AND && 1132 N0.getOperand(0).getOpcode() == ISD::XOR); 1133 // ((X^1)&1)^1 -> X & 1 1134 Val = DAG.getNode(ISD::AND, N0.getValueType(), 1135 N0.getOperand(0).getOperand(0), 1136 N0.getOperand(1)); 1137 } 1138 return DAG.getSetCC(VT, Val, N1, 1139 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1140 } 1141 } 1142 } 1143 1144 uint64_t MinVal, MaxVal; 1145 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 1146 if (ISD::isSignedIntSetCC(Cond)) { 1147 MinVal = 1ULL << (OperandBitSize-1); 1148 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 1149 MaxVal = ~0ULL >> (65-OperandBitSize); 1150 else 1151 MaxVal = 0; 1152 } else { 1153 MinVal = 0; 1154 MaxVal = ~0ULL >> (64-OperandBitSize); 1155 } 1156 1157 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1158 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1159 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1160 --C1; // X >= C0 --> X > (C0-1) 1161 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 1162 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1163 } 1164 1165 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1166 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1167 ++C1; // X <= C0 --> X < (C0+1) 1168 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 1169 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1170 } 1171 1172 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1173 return DAG.getConstant(0, VT); // X < MIN --> false 1174 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1175 return DAG.getConstant(1, VT); // X >= MIN --> true 1176 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1177 return DAG.getConstant(0, VT); // X > MAX --> false 1178 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1179 return DAG.getConstant(1, VT); // X <= MAX --> true 1180 1181 // Canonicalize setgt X, Min --> setne X, Min 1182 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1183 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1184 // Canonicalize setlt X, Max --> setne X, Max 1185 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1186 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1187 1188 // If we have setult X, 1, turn it into seteq X, 0 1189 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1190 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 1191 ISD::SETEQ); 1192 // If we have setugt X, Max-1, turn it into seteq X, Max 1193 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1194 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 1195 ISD::SETEQ); 1196 1197 // If we have "setcc X, C0", check to see if we can shrink the immediate 1198 // by changing cc. 1199 1200 // SETUGT X, SINTMAX -> SETLT X, 0 1201 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 1202 C1 == (~0ULL >> (65-OperandBitSize))) 1203 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 1204 ISD::SETLT); 1205 1206 // FIXME: Implement the rest of these. 1207 1208 // Fold bit comparisons when we can. 1209 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1210 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1211 if (ConstantSDNode *AndRHS = 1212 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1213 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1214 // Perform the xform if the AND RHS is a single bit. 1215 if (isPowerOf2_64(AndRHS->getValue())) { 1216 return DAG.getNode(ISD::SRL, VT, N0, 1217 DAG.getConstant(Log2_64(AndRHS->getValue()), 1218 getShiftAmountTy())); 1219 } 1220 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 1221 // (X & 8) == 8 --> (X & 8) >> 3 1222 // Perform the xform if C1 is a single bit. 1223 if (isPowerOf2_64(C1)) { 1224 return DAG.getNode(ISD::SRL, VT, N0, 1225 DAG.getConstant(Log2_64(C1), getShiftAmountTy())); 1226 } 1227 } 1228 } 1229 } 1230 } else if (isa<ConstantSDNode>(N0.Val)) { 1231 // Ensure that the constant occurs on the RHS. 1232 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1233 } 1234 1235 if (isa<ConstantFPSDNode>(N0.Val)) { 1236 // Constant fold or commute setcc. 1237 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond); 1238 if (O.Val) return O; 1239 } 1240 1241 if (N0 == N1) { 1242 // We can always fold X == X for integer setcc's. 1243 if (MVT::isInteger(N0.getValueType())) 1244 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1245 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1246 if (UOF == 2) // FP operators that are undefined on NaNs. 1247 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1248 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1249 return DAG.getConstant(UOF, VT); 1250 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1251 // if it is not already. 1252 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1253 if (NewCond != Cond) 1254 return DAG.getSetCC(VT, N0, N1, NewCond); 1255 } 1256 1257 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1258 MVT::isInteger(N0.getValueType())) { 1259 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1260 N0.getOpcode() == ISD::XOR) { 1261 // Simplify (X+Y) == (X+Z) --> Y == Z 1262 if (N0.getOpcode() == N1.getOpcode()) { 1263 if (N0.getOperand(0) == N1.getOperand(0)) 1264 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 1265 if (N0.getOperand(1) == N1.getOperand(1)) 1266 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 1267 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1268 // If X op Y == Y op X, try other combinations. 1269 if (N0.getOperand(0) == N1.getOperand(1)) 1270 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 1271 if (N0.getOperand(1) == N1.getOperand(0)) 1272 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 1273 } 1274 } 1275 1276 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1277 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1278 // Turn (X+C1) == C2 --> X == C2-C1 1279 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 1280 return DAG.getSetCC(VT, N0.getOperand(0), 1281 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 1282 N0.getValueType()), Cond); 1283 } 1284 1285 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1286 if (N0.getOpcode() == ISD::XOR) 1287 // If we know that all of the inverted bits are zero, don't bother 1288 // performing the inversion. 1289 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 1290 return DAG.getSetCC(VT, N0.getOperand(0), 1291 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 1292 N0.getValueType()), Cond); 1293 } 1294 1295 // Turn (C1-X) == C2 --> X == C1-C2 1296 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1297 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 1298 return DAG.getSetCC(VT, N0.getOperand(1), 1299 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 1300 N0.getValueType()), Cond); 1301 } 1302 } 1303 } 1304 1305 // Simplify (X+Z) == X --> Z == 0 1306 if (N0.getOperand(0) == N1) 1307 return DAG.getSetCC(VT, N0.getOperand(1), 1308 DAG.getConstant(0, N0.getValueType()), Cond); 1309 if (N0.getOperand(1) == N1) { 1310 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1311 return DAG.getSetCC(VT, N0.getOperand(0), 1312 DAG.getConstant(0, N0.getValueType()), Cond); 1313 else if (N0.Val->hasOneUse()) { 1314 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1315 // (Z-X) == X --> Z == X<<1 1316 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 1317 N1, 1318 DAG.getConstant(1, getShiftAmountTy())); 1319 if (!DCI.isCalledByLegalizer()) 1320 DCI.AddToWorklist(SH.Val); 1321 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 1322 } 1323 } 1324 } 1325 1326 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1327 N1.getOpcode() == ISD::XOR) { 1328 // Simplify X == (X+Z) --> Z == 0 1329 if (N1.getOperand(0) == N0) { 1330 return DAG.getSetCC(VT, N1.getOperand(1), 1331 DAG.getConstant(0, N1.getValueType()), Cond); 1332 } else if (N1.getOperand(1) == N0) { 1333 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1334 return DAG.getSetCC(VT, N1.getOperand(0), 1335 DAG.getConstant(0, N1.getValueType()), Cond); 1336 } else if (N1.Val->hasOneUse()) { 1337 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1338 // X == (Z-X) --> X<<1 == Z 1339 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 1340 DAG.getConstant(1, getShiftAmountTy())); 1341 if (!DCI.isCalledByLegalizer()) 1342 DCI.AddToWorklist(SH.Val); 1343 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 1344 } 1345 } 1346 } 1347 } 1348 1349 // Fold away ALL boolean setcc's. 1350 SDOperand Temp; 1351 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1352 switch (Cond) { 1353 default: assert(0 && "Unknown integer setcc!"); 1354 case ISD::SETEQ: // X == Y -> (X^Y)^1 1355 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1356 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 1357 if (!DCI.isCalledByLegalizer()) 1358 DCI.AddToWorklist(Temp.Val); 1359 break; 1360 case ISD::SETNE: // X != Y --> (X^Y) 1361 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1362 break; 1363 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 1364 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 1365 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1366 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 1367 if (!DCI.isCalledByLegalizer()) 1368 DCI.AddToWorklist(Temp.Val); 1369 break; 1370 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 1371 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 1372 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1373 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 1374 if (!DCI.isCalledByLegalizer()) 1375 DCI.AddToWorklist(Temp.Val); 1376 break; 1377 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 1378 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 1379 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1380 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 1381 if (!DCI.isCalledByLegalizer()) 1382 DCI.AddToWorklist(Temp.Val); 1383 break; 1384 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 1385 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 1386 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1387 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 1388 break; 1389 } 1390 if (VT != MVT::i1) { 1391 if (!DCI.isCalledByLegalizer()) 1392 DCI.AddToWorklist(N0.Val); 1393 // FIXME: If running after legalize, we probably can't do this. 1394 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1395 } 1396 return N0; 1397 } 1398 1399 // Could not fold it. 1400 return SDOperand(); 1401} 1402 1403SDOperand TargetLowering:: 1404PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1405 // Default implementation: no optimization. 1406 return SDOperand(); 1407} 1408 1409//===----------------------------------------------------------------------===// 1410// Inline Assembler Implementation Methods 1411//===----------------------------------------------------------------------===// 1412 1413TargetLowering::ConstraintType 1414TargetLowering::getConstraintType(const std::string &Constraint) const { 1415 // FIXME: lots more standard ones to handle. 1416 if (Constraint.size() == 1) { 1417 switch (Constraint[0]) { 1418 default: break; 1419 case 'r': return C_RegisterClass; 1420 case 'm': // memory 1421 case 'o': // offsetable 1422 case 'V': // not offsetable 1423 return C_Memory; 1424 case 'i': // Simple Integer or Relocatable Constant 1425 case 'n': // Simple Integer 1426 case 's': // Relocatable Constant 1427 case 'X': // Allow ANY value. 1428 case 'I': // Target registers. 1429 case 'J': 1430 case 'K': 1431 case 'L': 1432 case 'M': 1433 case 'N': 1434 case 'O': 1435 case 'P': 1436 return C_Other; 1437 } 1438 } 1439 1440 if (Constraint.size() > 1 && Constraint[0] == '{' && 1441 Constraint[Constraint.size()-1] == '}') 1442 return C_Register; 1443 return C_Unknown; 1444} 1445 1446/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1447/// vector. If it is invalid, don't add anything to Ops. 1448void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op, 1449 char ConstraintLetter, 1450 std::vector<SDOperand> &Ops, 1451 SelectionDAG &DAG) { 1452 switch (ConstraintLetter) { 1453 default: break; 1454 case 'X': // Allows any operand; labels (basic block) use this. 1455 if (Op.getOpcode() == ISD::BasicBlock) { 1456 Ops.push_back(Op); 1457 return; 1458 } 1459 // fall through 1460 case 'i': // Simple Integer or Relocatable Constant 1461 case 'n': // Simple Integer 1462 case 's': { // Relocatable Constant 1463 // These operands are interested in values of the form (GV+C), where C may 1464 // be folded in as an offset of GV, or it may be explicitly added. Also, it 1465 // is possible and fine if either GV or C are missing. 1466 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1467 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 1468 1469 // If we have "(add GV, C)", pull out GV/C 1470 if (Op.getOpcode() == ISD::ADD) { 1471 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1472 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 1473 if (C == 0 || GA == 0) { 1474 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 1475 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 1476 } 1477 if (C == 0 || GA == 0) 1478 C = 0, GA = 0; 1479 } 1480 1481 // If we find a valid operand, map to the TargetXXX version so that the 1482 // value itself doesn't get selected. 1483 if (GA) { // Either &GV or &GV+C 1484 if (ConstraintLetter != 'n') { 1485 int64_t Offs = GA->getOffset(); 1486 if (C) Offs += C->getValue(); 1487 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 1488 Op.getValueType(), Offs)); 1489 return; 1490 } 1491 } 1492 if (C) { // just C, no GV. 1493 // Simple constants are not allowed for 's'. 1494 if (ConstraintLetter != 's') { 1495 Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType())); 1496 return; 1497 } 1498 } 1499 break; 1500 } 1501 } 1502} 1503 1504std::vector<unsigned> TargetLowering:: 1505getRegClassForInlineAsmConstraint(const std::string &Constraint, 1506 MVT::ValueType VT) const { 1507 return std::vector<unsigned>(); 1508} 1509 1510 1511std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 1512getRegForInlineAsmConstraint(const std::string &Constraint, 1513 MVT::ValueType VT) const { 1514 if (Constraint[0] != '{') 1515 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1516 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 1517 1518 // Remove the braces from around the name. 1519 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 1520 1521 // Figure out which register class contains this reg. 1522 const MRegisterInfo *RI = TM.getRegisterInfo(); 1523 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 1524 E = RI->regclass_end(); RCI != E; ++RCI) { 1525 const TargetRegisterClass *RC = *RCI; 1526 1527 // If none of the the value types for this register class are valid, we 1528 // can't use it. For example, 64-bit reg classes on 32-bit targets. 1529 bool isLegal = false; 1530 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1531 I != E; ++I) { 1532 if (isTypeLegal(*I)) { 1533 isLegal = true; 1534 break; 1535 } 1536 } 1537 1538 if (!isLegal) continue; 1539 1540 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 1541 I != E; ++I) { 1542 if (StringsEqualNoCase(RegName, RI->get(*I).Name)) 1543 return std::make_pair(*I, RC); 1544 } 1545 } 1546 1547 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1548} 1549 1550//===----------------------------------------------------------------------===// 1551// Loop Strength Reduction hooks 1552//===----------------------------------------------------------------------===// 1553 1554/// isLegalAddressingMode - Return true if the addressing mode represented 1555/// by AM is legal for this target, for a load/store of the specified type. 1556bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 1557 const Type *Ty) const { 1558 // The default implementation of this implements a conservative RISCy, r+r and 1559 // r+i addr mode. 1560 1561 // Allows a sign-extended 16-bit immediate field. 1562 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1563 return false; 1564 1565 // No global is ever allowed as a base. 1566 if (AM.BaseGV) 1567 return false; 1568 1569 // Only support r+r, 1570 switch (AM.Scale) { 1571 case 0: // "r+i" or just "i", depending on HasBaseReg. 1572 break; 1573 case 1: 1574 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1575 return false; 1576 // Otherwise we have r+r or r+i. 1577 break; 1578 case 2: 1579 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1580 return false; 1581 // Allow 2*r as r+r. 1582 break; 1583 } 1584 1585 return true; 1586} 1587 1588// Magic for divide replacement 1589 1590struct ms { 1591 int64_t m; // magic number 1592 int64_t s; // shift amount 1593}; 1594 1595struct mu { 1596 uint64_t m; // magic number 1597 int64_t a; // add indicator 1598 int64_t s; // shift amount 1599}; 1600 1601/// magic - calculate the magic numbers required to codegen an integer sdiv as 1602/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1603/// or -1. 1604static ms magic32(int32_t d) { 1605 int32_t p; 1606 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 1607 const uint32_t two31 = 0x80000000U; 1608 struct ms mag; 1609 1610 ad = abs(d); 1611 t = two31 + ((uint32_t)d >> 31); 1612 anc = t - 1 - t%ad; // absolute value of nc 1613 p = 31; // initialize p 1614 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 1615 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1616 q2 = two31/ad; // initialize q2 = 2p/abs(d) 1617 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1618 do { 1619 p = p + 1; 1620 q1 = 2*q1; // update q1 = 2p/abs(nc) 1621 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1622 if (r1 >= anc) { // must be unsigned comparison 1623 q1 = q1 + 1; 1624 r1 = r1 - anc; 1625 } 1626 q2 = 2*q2; // update q2 = 2p/abs(d) 1627 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1628 if (r2 >= ad) { // must be unsigned comparison 1629 q2 = q2 + 1; 1630 r2 = r2 - ad; 1631 } 1632 delta = ad - r2; 1633 } while (q1 < delta || (q1 == delta && r1 == 0)); 1634 1635 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 1636 if (d < 0) mag.m = -mag.m; // resulting magic number 1637 mag.s = p - 32; // resulting shift 1638 return mag; 1639} 1640 1641/// magicu - calculate the magic numbers required to codegen an integer udiv as 1642/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1643static mu magicu32(uint32_t d) { 1644 int32_t p; 1645 uint32_t nc, delta, q1, r1, q2, r2; 1646 struct mu magu; 1647 magu.a = 0; // initialize "add" indicator 1648 nc = - 1 - (-d)%d; 1649 p = 31; // initialize p 1650 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 1651 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 1652 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 1653 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 1654 do { 1655 p = p + 1; 1656 if (r1 >= nc - r1 ) { 1657 q1 = 2*q1 + 1; // update q1 1658 r1 = 2*r1 - nc; // update r1 1659 } 1660 else { 1661 q1 = 2*q1; // update q1 1662 r1 = 2*r1; // update r1 1663 } 1664 if (r2 + 1 >= d - r2) { 1665 if (q2 >= 0x7FFFFFFF) magu.a = 1; 1666 q2 = 2*q2 + 1; // update q2 1667 r2 = 2*r2 + 1 - d; // update r2 1668 } 1669 else { 1670 if (q2 >= 0x80000000) magu.a = 1; 1671 q2 = 2*q2; // update q2 1672 r2 = 2*r2 + 1; // update r2 1673 } 1674 delta = d - 1 - r2; 1675 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 1676 magu.m = q2 + 1; // resulting magic number 1677 magu.s = p - 32; // resulting shift 1678 return magu; 1679} 1680 1681/// magic - calculate the magic numbers required to codegen an integer sdiv as 1682/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1683/// or -1. 1684static ms magic64(int64_t d) { 1685 int64_t p; 1686 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 1687 const uint64_t two63 = 9223372036854775808ULL; // 2^63 1688 struct ms mag; 1689 1690 ad = d >= 0 ? d : -d; 1691 t = two63 + ((uint64_t)d >> 63); 1692 anc = t - 1 - t%ad; // absolute value of nc 1693 p = 63; // initialize p 1694 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 1695 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1696 q2 = two63/ad; // initialize q2 = 2p/abs(d) 1697 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1698 do { 1699 p = p + 1; 1700 q1 = 2*q1; // update q1 = 2p/abs(nc) 1701 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1702 if (r1 >= anc) { // must be unsigned comparison 1703 q1 = q1 + 1; 1704 r1 = r1 - anc; 1705 } 1706 q2 = 2*q2; // update q2 = 2p/abs(d) 1707 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1708 if (r2 >= ad) { // must be unsigned comparison 1709 q2 = q2 + 1; 1710 r2 = r2 - ad; 1711 } 1712 delta = ad - r2; 1713 } while (q1 < delta || (q1 == delta && r1 == 0)); 1714 1715 mag.m = q2 + 1; 1716 if (d < 0) mag.m = -mag.m; // resulting magic number 1717 mag.s = p - 64; // resulting shift 1718 return mag; 1719} 1720 1721/// magicu - calculate the magic numbers required to codegen an integer udiv as 1722/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1723static mu magicu64(uint64_t d) 1724{ 1725 int64_t p; 1726 uint64_t nc, delta, q1, r1, q2, r2; 1727 struct mu magu; 1728 magu.a = 0; // initialize "add" indicator 1729 nc = - 1 - (-d)%d; 1730 p = 63; // initialize p 1731 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 1732 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 1733 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 1734 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 1735 do { 1736 p = p + 1; 1737 if (r1 >= nc - r1 ) { 1738 q1 = 2*q1 + 1; // update q1 1739 r1 = 2*r1 - nc; // update r1 1740 } 1741 else { 1742 q1 = 2*q1; // update q1 1743 r1 = 2*r1; // update r1 1744 } 1745 if (r2 + 1 >= d - r2) { 1746 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 1747 q2 = 2*q2 + 1; // update q2 1748 r2 = 2*r2 + 1 - d; // update r2 1749 } 1750 else { 1751 if (q2 >= 0x8000000000000000ull) magu.a = 1; 1752 q2 = 2*q2; // update q2 1753 r2 = 2*r2 + 1; // update r2 1754 } 1755 delta = d - 1 - r2; 1756 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0))); 1757 magu.m = q2 + 1; // resulting magic number 1758 magu.s = p - 64; // resulting shift 1759 return magu; 1760} 1761 1762/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 1763/// return a DAG expression to select that will generate the same value by 1764/// multiplying by a magic number. See: 1765/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 1766SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 1767 std::vector<SDNode*>* Created) const { 1768 MVT::ValueType VT = N->getValueType(0); 1769 1770 // Check to see if we can do this. 1771 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 1772 return SDOperand(); // BuildSDIV only operates on i32 or i64 1773 1774 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 1775 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 1776 1777 // Multiply the numerator (operand 0) by the magic value 1778 SDOperand Q; 1779 if (isOperationLegal(ISD::MULHS, VT)) 1780 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 1781 DAG.getConstant(magics.m, VT)); 1782 else if (isOperationLegal(ISD::SMUL_LOHI, VT)) 1783 Q = SDOperand(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), 1784 N->getOperand(0), 1785 DAG.getConstant(magics.m, VT)).Val, 1); 1786 else 1787 return SDOperand(); // No mulhs or equvialent 1788 // If d > 0 and m < 0, add the numerator 1789 if (d > 0 && magics.m < 0) { 1790 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 1791 if (Created) 1792 Created->push_back(Q.Val); 1793 } 1794 // If d < 0 and m > 0, subtract the numerator. 1795 if (d < 0 && magics.m > 0) { 1796 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 1797 if (Created) 1798 Created->push_back(Q.Val); 1799 } 1800 // Shift right algebraic if shift value is nonzero 1801 if (magics.s > 0) { 1802 Q = DAG.getNode(ISD::SRA, VT, Q, 1803 DAG.getConstant(magics.s, getShiftAmountTy())); 1804 if (Created) 1805 Created->push_back(Q.Val); 1806 } 1807 // Extract the sign bit and add it to the quotient 1808 SDOperand T = 1809 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 1810 getShiftAmountTy())); 1811 if (Created) 1812 Created->push_back(T.Val); 1813 return DAG.getNode(ISD::ADD, VT, Q, T); 1814} 1815 1816/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 1817/// return a DAG expression to select that will generate the same value by 1818/// multiplying by a magic number. See: 1819/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 1820SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 1821 std::vector<SDNode*>* Created) const { 1822 MVT::ValueType VT = N->getValueType(0); 1823 1824 // Check to see if we can do this. 1825 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 1826 return SDOperand(); // BuildUDIV only operates on i32 or i64 1827 1828 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 1829 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 1830 1831 // Multiply the numerator (operand 0) by the magic value 1832 SDOperand Q; 1833 if (isOperationLegal(ISD::MULHU, VT)) 1834 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 1835 DAG.getConstant(magics.m, VT)); 1836 else if (isOperationLegal(ISD::UMUL_LOHI, VT)) 1837 Q = SDOperand(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), 1838 N->getOperand(0), 1839 DAG.getConstant(magics.m, VT)).Val, 1); 1840 else 1841 return SDOperand(); // No mulhu or equvialent 1842 if (Created) 1843 Created->push_back(Q.Val); 1844 1845 if (magics.a == 0) { 1846 return DAG.getNode(ISD::SRL, VT, Q, 1847 DAG.getConstant(magics.s, getShiftAmountTy())); 1848 } else { 1849 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 1850 if (Created) 1851 Created->push_back(NPQ.Val); 1852 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 1853 DAG.getConstant(1, getShiftAmountTy())); 1854 if (Created) 1855 Created->push_back(NPQ.Val); 1856 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 1857 if (Created) 1858 Created->push_back(NPQ.Val); 1859 return DAG.getNode(ISD::SRL, VT, NPQ, 1860 DAG.getConstant(magics.s-1, getShiftAmountTy())); 1861 } 1862} 1863