TargetLowering.cpp revision 2e68b6f52d0979575b2f02ed29717d907ba0684c
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/Target/TargetSubtarget.h" 16#include "llvm/Target/TargetData.h" 17#include "llvm/Target/TargetMachine.h" 18#include "llvm/Target/TargetRegisterInfo.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/ADT/StringExtras.h" 22#include "llvm/ADT/STLExtras.h" 23#include "llvm/Support/MathExtras.h" 24#include "llvm/Target/TargetAsmInfo.h" 25#include "llvm/CallingConv.h" 26using namespace llvm; 27 28/// InitLibcallNames - Set default libcall names. 29/// 30static void InitLibcallNames(const char **Names) { 31 Names[RTLIB::SHL_I32] = "__ashlsi3"; 32 Names[RTLIB::SHL_I64] = "__ashldi3"; 33 Names[RTLIB::SRL_I32] = "__lshrsi3"; 34 Names[RTLIB::SRL_I64] = "__lshrdi3"; 35 Names[RTLIB::SRA_I32] = "__ashrsi3"; 36 Names[RTLIB::SRA_I64] = "__ashrdi3"; 37 Names[RTLIB::MUL_I32] = "__mulsi3"; 38 Names[RTLIB::MUL_I64] = "__muldi3"; 39 Names[RTLIB::SDIV_I32] = "__divsi3"; 40 Names[RTLIB::SDIV_I64] = "__divdi3"; 41 Names[RTLIB::UDIV_I32] = "__udivsi3"; 42 Names[RTLIB::UDIV_I64] = "__udivdi3"; 43 Names[RTLIB::SREM_I32] = "__modsi3"; 44 Names[RTLIB::SREM_I64] = "__moddi3"; 45 Names[RTLIB::UREM_I32] = "__umodsi3"; 46 Names[RTLIB::UREM_I64] = "__umoddi3"; 47 Names[RTLIB::NEG_I32] = "__negsi2"; 48 Names[RTLIB::NEG_I64] = "__negdi2"; 49 Names[RTLIB::ADD_F32] = "__addsf3"; 50 Names[RTLIB::ADD_F64] = "__adddf3"; 51 Names[RTLIB::ADD_F80] = "__addxf3"; 52 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 53 Names[RTLIB::SUB_F32] = "__subsf3"; 54 Names[RTLIB::SUB_F64] = "__subdf3"; 55 Names[RTLIB::SUB_F80] = "__subxf3"; 56 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 57 Names[RTLIB::MUL_F32] = "__mulsf3"; 58 Names[RTLIB::MUL_F64] = "__muldf3"; 59 Names[RTLIB::MUL_F80] = "__mulxf3"; 60 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 61 Names[RTLIB::DIV_F32] = "__divsf3"; 62 Names[RTLIB::DIV_F64] = "__divdf3"; 63 Names[RTLIB::DIV_F80] = "__divxf3"; 64 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 65 Names[RTLIB::REM_F32] = "fmodf"; 66 Names[RTLIB::REM_F64] = "fmod"; 67 Names[RTLIB::REM_F80] = "fmodl"; 68 Names[RTLIB::REM_PPCF128] = "fmodl"; 69 Names[RTLIB::POWI_F32] = "__powisf2"; 70 Names[RTLIB::POWI_F64] = "__powidf2"; 71 Names[RTLIB::POWI_F80] = "__powixf2"; 72 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 73 Names[RTLIB::SQRT_F32] = "sqrtf"; 74 Names[RTLIB::SQRT_F64] = "sqrt"; 75 Names[RTLIB::SQRT_F80] = "sqrtl"; 76 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 77 Names[RTLIB::SIN_F32] = "sinf"; 78 Names[RTLIB::SIN_F64] = "sin"; 79 Names[RTLIB::SIN_F80] = "sinl"; 80 Names[RTLIB::SIN_PPCF128] = "sinl"; 81 Names[RTLIB::COS_F32] = "cosf"; 82 Names[RTLIB::COS_F64] = "cos"; 83 Names[RTLIB::COS_F80] = "cosl"; 84 Names[RTLIB::COS_PPCF128] = "cosl"; 85 Names[RTLIB::POW_F32] = "powf"; 86 Names[RTLIB::POW_F64] = "pow"; 87 Names[RTLIB::POW_F80] = "powl"; 88 Names[RTLIB::POW_PPCF128] = "powl"; 89 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 90 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 91 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 92 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 93 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 94 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 95 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 96 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 97 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 98 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 99 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 100 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 101 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 102 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 103 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 104 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 105 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 106 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 107 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 108 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 109 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 110 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 111 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 112 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 113 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 114 Names[RTLIB::OEQ_F32] = "__eqsf2"; 115 Names[RTLIB::OEQ_F64] = "__eqdf2"; 116 Names[RTLIB::UNE_F32] = "__nesf2"; 117 Names[RTLIB::UNE_F64] = "__nedf2"; 118 Names[RTLIB::OGE_F32] = "__gesf2"; 119 Names[RTLIB::OGE_F64] = "__gedf2"; 120 Names[RTLIB::OLT_F32] = "__ltsf2"; 121 Names[RTLIB::OLT_F64] = "__ltdf2"; 122 Names[RTLIB::OLE_F32] = "__lesf2"; 123 Names[RTLIB::OLE_F64] = "__ledf2"; 124 Names[RTLIB::OGT_F32] = "__gtsf2"; 125 Names[RTLIB::OGT_F64] = "__gtdf2"; 126 Names[RTLIB::UO_F32] = "__unordsf2"; 127 Names[RTLIB::UO_F64] = "__unorddf2"; 128 Names[RTLIB::O_F32] = "__unordsf2"; 129 Names[RTLIB::O_F64] = "__unorddf2"; 130} 131 132/// InitCmpLibcallCCs - Set default comparison libcall CC. 133/// 134static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 135 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 136 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 137 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 138 CCs[RTLIB::UNE_F32] = ISD::SETNE; 139 CCs[RTLIB::UNE_F64] = ISD::SETNE; 140 CCs[RTLIB::OGE_F32] = ISD::SETGE; 141 CCs[RTLIB::OGE_F64] = ISD::SETGE; 142 CCs[RTLIB::OLT_F32] = ISD::SETLT; 143 CCs[RTLIB::OLT_F64] = ISD::SETLT; 144 CCs[RTLIB::OLE_F32] = ISD::SETLE; 145 CCs[RTLIB::OLE_F64] = ISD::SETLE; 146 CCs[RTLIB::OGT_F32] = ISD::SETGT; 147 CCs[RTLIB::OGT_F64] = ISD::SETGT; 148 CCs[RTLIB::UO_F32] = ISD::SETNE; 149 CCs[RTLIB::UO_F64] = ISD::SETNE; 150 CCs[RTLIB::O_F32] = ISD::SETEQ; 151 CCs[RTLIB::O_F64] = ISD::SETEQ; 152} 153 154TargetLowering::TargetLowering(TargetMachine &tm) 155 : TM(tm), TD(TM.getTargetData()) { 156 assert(ISD::BUILTIN_OP_END <= 156 && 157 "Fixed size array in TargetLowering is not large enough!"); 158 // All operations default to being supported. 159 memset(OpActions, 0, sizeof(OpActions)); 160 memset(LoadXActions, 0, sizeof(LoadXActions)); 161 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 162 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 163 memset(ConvertActions, 0, sizeof(ConvertActions)); 164 165 // Set default actions for various operations. 166 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 167 // Default all indexed load / store to expand. 168 for (unsigned IM = (unsigned)ISD::PRE_INC; 169 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 170 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand); 171 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand); 172 } 173 174 // These operations default to expand. 175 setOperationAction(ISD::FGETSIGN, (MVT::ValueType)VT, Expand); 176 } 177 178 // ConstantFP nodes default to expand. Targets can either change this to 179 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 180 // to optimize expansions for certain constants. 181 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 182 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 183 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 184 185 // Default ISD::TRAP to expand (which turns it into abort). 186 setOperationAction(ISD::TRAP, MVT::Other, Expand); 187 188 IsLittleEndian = TD->isLittleEndian(); 189 UsesGlobalOffsetTable = false; 190 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType()); 191 ShiftAmtHandling = Undefined; 192 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 193 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 194 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 195 allowUnalignedMemoryAccesses = false; 196 UseUnderscoreSetJmp = false; 197 UseUnderscoreLongJmp = false; 198 SelectIsExpensive = false; 199 IntDivIsCheap = false; 200 Pow2DivIsCheap = false; 201 StackPointerRegisterToSaveRestore = 0; 202 ExceptionPointerRegister = 0; 203 ExceptionSelectorRegister = 0; 204 SetCCResultContents = UndefinedSetCCResult; 205 SchedPreferenceInfo = SchedulingForLatency; 206 JumpBufSize = 0; 207 JumpBufAlignment = 0; 208 IfCvtBlockSizeLimit = 2; 209 210 InitLibcallNames(LibcallRoutineNames); 211 InitCmpLibcallCCs(CmpLibcallCCs); 212 213 // Tell Legalize whether the assembler supports DEBUG_LOC. 214 if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile()) 215 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 216} 217 218TargetLowering::~TargetLowering() {} 219 220 221SDOperand TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) { 222 assert(getSubtarget() && "Subtarget not defined"); 223 SDOperand ChainOp = Op.getOperand(0); 224 SDOperand DestOp = Op.getOperand(1); 225 SDOperand SourceOp = Op.getOperand(2); 226 SDOperand CountOp = Op.getOperand(3); 227 SDOperand AlignOp = Op.getOperand(4); 228 SDOperand AlwaysInlineOp = Op.getOperand(5); 229 230 bool AlwaysInline = (bool)cast<ConstantSDNode>(AlwaysInlineOp)->getValue(); 231 unsigned Align = (unsigned)cast<ConstantSDNode>(AlignOp)->getValue(); 232 if (Align == 0) Align = 1; 233 234 // If size is unknown, call memcpy. 235 ConstantSDNode *I = dyn_cast<ConstantSDNode>(CountOp); 236 if (!I) { 237 assert(!AlwaysInline && "Cannot inline copy of unknown size"); 238 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG); 239 } 240 241 // If not DWORD aligned or if size is more than threshold, then call memcpy. 242 // The libc version is likely to be faster for the following cases. It can 243 // use the address value and run time information about the CPU. 244 // With glibc 2.6.1 on a core 2, coping an array of 100M longs was 30% faster 245 unsigned Size = I->getValue(); 246 if (AlwaysInline || 247 (Size <= getSubtarget()->getMaxInlineSizeThreshold() && 248 (Align & 3) == 0)) 249 return LowerMEMCPYInline(ChainOp, DestOp, SourceOp, Size, Align, DAG); 250 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG); 251} 252 253 254SDOperand TargetLowering::LowerMEMCPYCall(SDOperand Chain, 255 SDOperand Dest, 256 SDOperand Source, 257 SDOperand Count, 258 SelectionDAG &DAG) { 259 MVT::ValueType IntPtr = getPointerTy(); 260 TargetLowering::ArgListTy Args; 261 TargetLowering::ArgListEntry Entry; 262 Entry.Ty = getTargetData()->getIntPtrType(); 263 Entry.Node = Dest; Args.push_back(Entry); 264 Entry.Node = Source; Args.push_back(Entry); 265 Entry.Node = Count; Args.push_back(Entry); 266 std::pair<SDOperand,SDOperand> CallResult = 267 LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C, 268 false, DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG); 269 return CallResult.second; 270} 271 272 273/// computeRegisterProperties - Once all of the register classes are added, 274/// this allows us to compute derived properties we expose. 275void TargetLowering::computeRegisterProperties() { 276 assert(MVT::LAST_VALUETYPE <= 32 && 277 "Too many value types for ValueTypeActions to hold!"); 278 279 // Everything defaults to needing one register. 280 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 281 NumRegistersForVT[i] = 1; 282 RegisterTypeForVT[i] = TransformToType[i] = i; 283 } 284 // ...except isVoid, which doesn't need any registers. 285 NumRegistersForVT[MVT::isVoid] = 0; 286 287 // Find the largest integer register class. 288 unsigned LargestIntReg = MVT::i128; 289 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 290 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 291 292 // Every integer value type larger than this largest register takes twice as 293 // many registers to represent as the previous ValueType. 294 for (MVT::ValueType ExpandedReg = LargestIntReg + 1; 295 MVT::isInteger(ExpandedReg); ++ExpandedReg) { 296 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 297 RegisterTypeForVT[ExpandedReg] = LargestIntReg; 298 TransformToType[ExpandedReg] = ExpandedReg - 1; 299 ValueTypeActions.setTypeAction(ExpandedReg, Expand); 300 } 301 302 // Inspect all of the ValueType's smaller than the largest integer 303 // register to see which ones need promotion. 304 MVT::ValueType LegalIntReg = LargestIntReg; 305 for (MVT::ValueType IntReg = LargestIntReg - 1; 306 IntReg >= MVT::i1; --IntReg) { 307 if (isTypeLegal(IntReg)) { 308 LegalIntReg = IntReg; 309 } else { 310 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg; 311 ValueTypeActions.setTypeAction(IntReg, Promote); 312 } 313 } 314 315 // ppcf128 type is really two f64's. 316 if (!isTypeLegal(MVT::ppcf128)) { 317 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 318 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 319 TransformToType[MVT::ppcf128] = MVT::f64; 320 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 321 } 322 323 // Decide how to handle f64. If the target does not have native f64 support, 324 // expand it to i64 and we will be generating soft float library calls. 325 if (!isTypeLegal(MVT::f64)) { 326 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 327 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 328 TransformToType[MVT::f64] = MVT::i64; 329 ValueTypeActions.setTypeAction(MVT::f64, Expand); 330 } 331 332 // Decide how to handle f32. If the target does not have native support for 333 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 334 if (!isTypeLegal(MVT::f32)) { 335 if (isTypeLegal(MVT::f64)) { 336 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 337 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 338 TransformToType[MVT::f32] = MVT::f64; 339 ValueTypeActions.setTypeAction(MVT::f32, Promote); 340 } else { 341 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 342 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 343 TransformToType[MVT::f32] = MVT::i32; 344 ValueTypeActions.setTypeAction(MVT::f32, Expand); 345 } 346 } 347 348 // Loop over all of the vector value types to see which need transformations. 349 for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE; 350 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 351 if (!isTypeLegal(i)) { 352 MVT::ValueType IntermediateVT, RegisterVT; 353 unsigned NumIntermediates; 354 NumRegistersForVT[i] = 355 getVectorTypeBreakdown(i, 356 IntermediateVT, NumIntermediates, 357 RegisterVT); 358 RegisterTypeForVT[i] = RegisterVT; 359 TransformToType[i] = MVT::Other; // this isn't actually used 360 ValueTypeActions.setTypeAction(i, Expand); 361 } 362 } 363} 364 365const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 366 return NULL; 367} 368 369/// getVectorTypeBreakdown - Vector types are broken down into some number of 370/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 371/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 372/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 373/// 374/// This method returns the number of registers needed, and the VT for each 375/// register. It also returns the VT and quantity of the intermediate values 376/// before they are promoted/expanded. 377/// 378unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT, 379 MVT::ValueType &IntermediateVT, 380 unsigned &NumIntermediates, 381 MVT::ValueType &RegisterVT) const { 382 // Figure out the right, legal destination reg to copy into. 383 unsigned NumElts = MVT::getVectorNumElements(VT); 384 MVT::ValueType EltTy = MVT::getVectorElementType(VT); 385 386 unsigned NumVectorRegs = 1; 387 388 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 389 // could break down into LHS/RHS like LegalizeDAG does. 390 if (!isPowerOf2_32(NumElts)) { 391 NumVectorRegs = NumElts; 392 NumElts = 1; 393 } 394 395 // Divide the input until we get to a supported size. This will always 396 // end with a scalar if the target doesn't support vectors. 397 while (NumElts > 1 && 398 !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) { 399 NumElts >>= 1; 400 NumVectorRegs <<= 1; 401 } 402 403 NumIntermediates = NumVectorRegs; 404 405 MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts); 406 if (!isTypeLegal(NewVT)) 407 NewVT = EltTy; 408 IntermediateVT = NewVT; 409 410 MVT::ValueType DestVT = getTypeToTransformTo(NewVT); 411 RegisterVT = DestVT; 412 if (DestVT < NewVT) { 413 // Value is expanded, e.g. i64 -> i16. 414 return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT)); 415 } else { 416 // Otherwise, promotion or legal types use the same number of registers as 417 // the vector decimated to the appropriate level. 418 return NumVectorRegs; 419 } 420 421 return 1; 422} 423 424/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 425/// function arguments in the caller parameter area. 426unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 427 return Log2_32(TD->getCallFrameTypeAlignment(Ty)); 428} 429 430SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table, 431 SelectionDAG &DAG) const { 432 if (usesGlobalOffsetTable()) 433 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 434 return Table; 435} 436 437//===----------------------------------------------------------------------===// 438// Optimization Methods 439//===----------------------------------------------------------------------===// 440 441/// ShrinkDemandedConstant - Check to see if the specified operand of the 442/// specified instruction is a constant integer. If so, check to see if there 443/// are any bits set in the constant that are not demanded. If so, shrink the 444/// constant and return true. 445bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, 446 uint64_t Demanded) { 447 // FIXME: ISD::SELECT, ISD::SELECT_CC 448 switch(Op.getOpcode()) { 449 default: break; 450 case ISD::AND: 451 case ISD::OR: 452 case ISD::XOR: 453 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 454 if ((~Demanded & C->getValue()) != 0) { 455 MVT::ValueType VT = Op.getValueType(); 456 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 457 DAG.getConstant(Demanded & C->getValue(), 458 VT)); 459 return CombineTo(Op, New); 460 } 461 break; 462 } 463 return false; 464} 465 466/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 467/// DemandedMask bits of the result of Op are ever used downstream. If we can 468/// use this information to simplify Op, create a new simplified DAG node and 469/// return true, returning the original and new nodes in Old and New. Otherwise, 470/// analyze the expression and return a mask of KnownOne and KnownZero bits for 471/// the expression (used to simplify the caller). The KnownZero/One bits may 472/// only be accurate for those bits in the DemandedMask. 473bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 474 uint64_t &KnownZero, 475 uint64_t &KnownOne, 476 TargetLoweringOpt &TLO, 477 unsigned Depth) const { 478 KnownZero = KnownOne = 0; // Don't know anything. 479 480 // The masks are not wide enough to represent this type! Should use APInt. 481 if (Op.getValueType() == MVT::i128) 482 return false; 483 484 // Other users may use these bits. 485 if (!Op.Val->hasOneUse()) { 486 if (Depth != 0) { 487 // If not at the root, Just compute the KnownZero/KnownOne bits to 488 // simplify things downstream. 489 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 490 return false; 491 } 492 // If this is the root being simplified, allow it to have multiple uses, 493 // just set the DemandedMask to all bits. 494 DemandedMask = MVT::getIntVTBitMask(Op.getValueType()); 495 } else if (DemandedMask == 0) { 496 // Not demanding any bits from Op. 497 if (Op.getOpcode() != ISD::UNDEF) 498 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 499 return false; 500 } else if (Depth == 6) { // Limit search depth. 501 return false; 502 } 503 504 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 505 switch (Op.getOpcode()) { 506 case ISD::Constant: 507 // We know all of the bits for a constant! 508 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask; 509 KnownZero = ~KnownOne & DemandedMask; 510 return false; // Don't fall through, will infinitely loop. 511 case ISD::AND: 512 // If the RHS is a constant, check to see if the LHS would be zero without 513 // using the bits from the RHS. Below, we use knowledge about the RHS to 514 // simplify the LHS, here we're using information from the LHS to simplify 515 // the RHS. 516 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 517 uint64_t LHSZero, LHSOne; 518 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), DemandedMask, 519 LHSZero, LHSOne, Depth+1); 520 // If the LHS already has zeros where RHSC does, this and is dead. 521 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask)) 522 return TLO.CombineTo(Op, Op.getOperand(0)); 523 // If any of the set bits in the RHS are known zero on the LHS, shrink 524 // the constant. 525 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask)) 526 return true; 527 } 528 529 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 530 KnownOne, TLO, Depth+1)) 531 return true; 532 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 533 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero, 534 KnownZero2, KnownOne2, TLO, Depth+1)) 535 return true; 536 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 537 538 // If all of the demanded bits are known one on one side, return the other. 539 // These bits cannot contribute to the result of the 'and'. 540 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2)) 541 return TLO.CombineTo(Op, Op.getOperand(0)); 542 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero)) 543 return TLO.CombineTo(Op, Op.getOperand(1)); 544 // If all of the demanded bits in the inputs are known zeros, return zero. 545 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask) 546 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 547 // If the RHS is a constant, see if we can simplify it. 548 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2)) 549 return true; 550 551 // Output known-1 bits are only known if set in both the LHS & RHS. 552 KnownOne &= KnownOne2; 553 // Output known-0 are known to be clear if zero in either the LHS | RHS. 554 KnownZero |= KnownZero2; 555 break; 556 case ISD::OR: 557 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 558 KnownOne, TLO, Depth+1)) 559 return true; 560 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 561 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne, 562 KnownZero2, KnownOne2, TLO, Depth+1)) 563 return true; 564 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 565 566 // If all of the demanded bits are known zero on one side, return the other. 567 // These bits cannot contribute to the result of the 'or'. 568 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2)) 569 return TLO.CombineTo(Op, Op.getOperand(0)); 570 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne)) 571 return TLO.CombineTo(Op, Op.getOperand(1)); 572 // If all of the potentially set bits on one side are known to be set on 573 // the other side, just use the 'other' side. 574 if ((DemandedMask & (~KnownZero) & KnownOne2) == 575 (DemandedMask & (~KnownZero))) 576 return TLO.CombineTo(Op, Op.getOperand(0)); 577 if ((DemandedMask & (~KnownZero2) & KnownOne) == 578 (DemandedMask & (~KnownZero2))) 579 return TLO.CombineTo(Op, Op.getOperand(1)); 580 // If the RHS is a constant, see if we can simplify it. 581 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 582 return true; 583 584 // Output known-0 bits are only known if clear in both the LHS & RHS. 585 KnownZero &= KnownZero2; 586 // Output known-1 are known to be set if set in either the LHS | RHS. 587 KnownOne |= KnownOne2; 588 break; 589 case ISD::XOR: 590 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 591 KnownOne, TLO, Depth+1)) 592 return true; 593 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 594 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2, 595 KnownOne2, TLO, Depth+1)) 596 return true; 597 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 598 599 // If all of the demanded bits are known zero on one side, return the other. 600 // These bits cannot contribute to the result of the 'xor'. 601 if ((DemandedMask & KnownZero) == DemandedMask) 602 return TLO.CombineTo(Op, Op.getOperand(0)); 603 if ((DemandedMask & KnownZero2) == DemandedMask) 604 return TLO.CombineTo(Op, Op.getOperand(1)); 605 606 // If all of the unknown bits are known to be zero on one side or the other 607 // (but not both) turn this into an *inclusive* or. 608 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 609 if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0) 610 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 611 Op.getOperand(0), 612 Op.getOperand(1))); 613 614 // Output known-0 bits are known if clear or set in both the LHS & RHS. 615 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 616 // Output known-1 are known to be set if set in only one of the LHS, RHS. 617 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 618 619 // If all of the demanded bits on one side are known, and all of the set 620 // bits on that side are also known to be set on the other side, turn this 621 // into an AND, as we know the bits will be cleared. 622 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 623 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known 624 if ((KnownOne & KnownOne2) == KnownOne) { 625 MVT::ValueType VT = Op.getValueType(); 626 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT); 627 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 628 ANDC)); 629 } 630 } 631 632 // If the RHS is a constant, see if we can simplify it. 633 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. 634 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 635 return true; 636 637 KnownZero = KnownZeroOut; 638 KnownOne = KnownOneOut; 639 break; 640 case ISD::SETCC: 641 // If we know the result of a setcc has the top bits zero, use this info. 642 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 643 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 644 break; 645 case ISD::SELECT: 646 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero, 647 KnownOne, TLO, Depth+1)) 648 return true; 649 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2, 650 KnownOne2, TLO, Depth+1)) 651 return true; 652 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 653 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 654 655 // If the operands are constants, see if we can simplify them. 656 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 657 return true; 658 659 // Only known if known in both the LHS and RHS. 660 KnownOne &= KnownOne2; 661 KnownZero &= KnownZero2; 662 break; 663 case ISD::SELECT_CC: 664 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero, 665 KnownOne, TLO, Depth+1)) 666 return true; 667 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2, 668 KnownOne2, TLO, Depth+1)) 669 return true; 670 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 671 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 672 673 // If the operands are constants, see if we can simplify them. 674 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 675 return true; 676 677 // Only known if known in both the LHS and RHS. 678 KnownOne &= KnownOne2; 679 KnownZero &= KnownZero2; 680 break; 681 case ISD::SHL: 682 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 683 unsigned ShAmt = SA->getValue(); 684 SDOperand InOp = Op.getOperand(0); 685 686 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 687 // single shift. We can do this if the bottom bits (which are shifted 688 // out) are never demanded. 689 if (InOp.getOpcode() == ISD::SRL && 690 isa<ConstantSDNode>(InOp.getOperand(1))) { 691 if (ShAmt && (DemandedMask & ((1ULL << ShAmt)-1)) == 0) { 692 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 693 unsigned Opc = ISD::SHL; 694 int Diff = ShAmt-C1; 695 if (Diff < 0) { 696 Diff = -Diff; 697 Opc = ISD::SRL; 698 } 699 700 SDOperand NewSA = 701 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 702 MVT::ValueType VT = Op.getValueType(); 703 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 704 InOp.getOperand(0), NewSA)); 705 } 706 } 707 708 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> ShAmt, 709 KnownZero, KnownOne, TLO, Depth+1)) 710 return true; 711 KnownZero <<= SA->getValue(); 712 KnownOne <<= SA->getValue(); 713 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 714 } 715 break; 716 case ISD::SRL: 717 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 718 MVT::ValueType VT = Op.getValueType(); 719 unsigned ShAmt = SA->getValue(); 720 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 721 unsigned VTSize = MVT::getSizeInBits(VT); 722 SDOperand InOp = Op.getOperand(0); 723 724 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 725 // single shift. We can do this if the top bits (which are shifted out) 726 // are never demanded. 727 if (InOp.getOpcode() == ISD::SHL && 728 isa<ConstantSDNode>(InOp.getOperand(1))) { 729 if (ShAmt && (DemandedMask & (~0ULL << (VTSize-ShAmt))) == 0) { 730 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 731 unsigned Opc = ISD::SRL; 732 int Diff = ShAmt-C1; 733 if (Diff < 0) { 734 Diff = -Diff; 735 Opc = ISD::SHL; 736 } 737 738 SDOperand NewSA = 739 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 740 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 741 InOp.getOperand(0), NewSA)); 742 } 743 } 744 745 // Compute the new bits that are at the top now. 746 if (SimplifyDemandedBits(InOp, (DemandedMask << ShAmt) & TypeMask, 747 KnownZero, KnownOne, TLO, Depth+1)) 748 return true; 749 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 750 KnownZero &= TypeMask; 751 KnownOne &= TypeMask; 752 KnownZero >>= ShAmt; 753 KnownOne >>= ShAmt; 754 755 uint64_t HighBits = (1ULL << ShAmt)-1; 756 HighBits <<= VTSize - ShAmt; 757 KnownZero |= HighBits; // High bits known zero. 758 } 759 break; 760 case ISD::SRA: 761 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 762 MVT::ValueType VT = Op.getValueType(); 763 unsigned ShAmt = SA->getValue(); 764 765 // Compute the new bits that are at the top now. 766 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 767 768 uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask; 769 770 // If any of the demanded bits are produced by the sign extension, we also 771 // demand the input sign bit. 772 uint64_t HighBits = (1ULL << ShAmt)-1; 773 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 774 if (HighBits & DemandedMask) 775 InDemandedMask |= MVT::getIntVTSignBit(VT); 776 777 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 778 KnownZero, KnownOne, TLO, Depth+1)) 779 return true; 780 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 781 KnownZero &= TypeMask; 782 KnownOne &= TypeMask; 783 KnownZero >>= ShAmt; 784 KnownOne >>= ShAmt; 785 786 // Handle the sign bits. 787 uint64_t SignBit = MVT::getIntVTSignBit(VT); 788 SignBit >>= ShAmt; // Adjust to where it is now in the mask. 789 790 // If the input sign bit is known to be zero, or if none of the top bits 791 // are demanded, turn this into an unsigned shift right. 792 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) { 793 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 794 Op.getOperand(1))); 795 } else if (KnownOne & SignBit) { // New bits are known one. 796 KnownOne |= HighBits; 797 } 798 } 799 break; 800 case ISD::SIGN_EXTEND_INREG: { 801 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 802 803 // Sign extension. Compute the demanded bits in the result that are not 804 // present in the input. 805 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask; 806 807 // If none of the extended bits are demanded, eliminate the sextinreg. 808 if (NewBits == 0) 809 return TLO.CombineTo(Op, Op.getOperand(0)); 810 811 uint64_t InSignBit = MVT::getIntVTSignBit(EVT); 812 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT); 813 814 // Since the sign extended bits are demanded, we know that the sign 815 // bit is demanded. 816 InputDemandedBits |= InSignBit; 817 818 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 819 KnownZero, KnownOne, TLO, Depth+1)) 820 return true; 821 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 822 823 // If the sign bit of the input is known set or clear, then we know the 824 // top bits of the result. 825 826 // If the input sign bit is known zero, convert this into a zero extension. 827 if (KnownZero & InSignBit) 828 return TLO.CombineTo(Op, 829 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 830 831 if (KnownOne & InSignBit) { // Input sign bit known set 832 KnownOne |= NewBits; 833 KnownZero &= ~NewBits; 834 } else { // Input sign bit unknown 835 KnownZero &= ~NewBits; 836 KnownOne &= ~NewBits; 837 } 838 break; 839 } 840 case ISD::CTTZ: 841 case ISD::CTLZ: 842 case ISD::CTPOP: { 843 MVT::ValueType VT = Op.getValueType(); 844 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 845 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 846 KnownOne = 0; 847 break; 848 } 849 case ISD::LOAD: { 850 if (ISD::isZEXTLoad(Op.Val)) { 851 LoadSDNode *LD = cast<LoadSDNode>(Op); 852 MVT::ValueType VT = LD->getMemoryVT(); 853 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask; 854 } 855 break; 856 } 857 case ISD::ZERO_EXTEND: { 858 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 859 860 // If none of the top bits are demanded, convert this into an any_extend. 861 uint64_t NewBits = (~InMask) & DemandedMask; 862 if (NewBits == 0) 863 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 864 Op.getValueType(), 865 Op.getOperand(0))); 866 867 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 868 KnownZero, KnownOne, TLO, Depth+1)) 869 return true; 870 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 871 KnownZero |= NewBits; 872 break; 873 } 874 case ISD::SIGN_EXTEND: { 875 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 876 uint64_t InMask = MVT::getIntVTBitMask(InVT); 877 uint64_t InSignBit = MVT::getIntVTSignBit(InVT); 878 uint64_t NewBits = (~InMask) & DemandedMask; 879 880 // If none of the top bits are demanded, convert this into an any_extend. 881 if (NewBits == 0) 882 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 883 Op.getOperand(0))); 884 885 // Since some of the sign extended bits are demanded, we know that the sign 886 // bit is demanded. 887 uint64_t InDemandedBits = DemandedMask & InMask; 888 InDemandedBits |= InSignBit; 889 890 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 891 KnownOne, TLO, Depth+1)) 892 return true; 893 894 // If the sign bit is known zero, convert this to a zero extend. 895 if (KnownZero & InSignBit) 896 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 897 Op.getValueType(), 898 Op.getOperand(0))); 899 900 // If the sign bit is known one, the top bits match. 901 if (KnownOne & InSignBit) { 902 KnownOne |= NewBits; 903 KnownZero &= ~NewBits; 904 } else { // Otherwise, top bits aren't known. 905 KnownOne &= ~NewBits; 906 KnownZero &= ~NewBits; 907 } 908 break; 909 } 910 case ISD::ANY_EXTEND: { 911 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 912 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 913 KnownZero, KnownOne, TLO, Depth+1)) 914 return true; 915 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 916 break; 917 } 918 case ISD::TRUNCATE: { 919 // Simplify the input, using demanded bit information, and compute the known 920 // zero/one bits live out. 921 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, 922 KnownZero, KnownOne, TLO, Depth+1)) 923 return true; 924 925 // If the input is only used by this truncate, see if we can shrink it based 926 // on the known demanded bits. 927 if (Op.getOperand(0).Val->hasOneUse()) { 928 SDOperand In = Op.getOperand(0); 929 switch (In.getOpcode()) { 930 default: break; 931 case ISD::SRL: 932 // Shrink SRL by a constant if none of the high bits shifted in are 933 // demanded. 934 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 935 uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType()); 936 HighBits &= ~MVT::getIntVTBitMask(Op.getValueType()); 937 HighBits >>= ShAmt->getValue(); 938 939 if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) && 940 (DemandedMask & HighBits) == 0) { 941 // None of the shifted in bits are needed. Add a truncate of the 942 // shift input, then shift it. 943 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 944 Op.getValueType(), 945 In.getOperand(0)); 946 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), 947 NewTrunc, In.getOperand(1))); 948 } 949 } 950 break; 951 } 952 } 953 954 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 955 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType()); 956 KnownZero &= OutMask; 957 KnownOne &= OutMask; 958 break; 959 } 960 case ISD::AssertZext: { 961 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 962 uint64_t InMask = MVT::getIntVTBitMask(VT); 963 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 964 KnownZero, KnownOne, TLO, Depth+1)) 965 return true; 966 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 967 KnownZero |= ~InMask & DemandedMask; 968 break; 969 } 970 case ISD::FGETSIGN: 971 // All bits are zero except the low bit. 972 KnownZero = MVT::getIntVTBitMask(Op.getValueType()) ^ 1; 973 break; 974 case ISD::BIT_CONVERT: 975#if 0 976 // If this is an FP->Int bitcast and if the sign bit is the only thing that 977 // is demanded, turn this into a FGETSIGN. 978 if (DemandedMask == MVT::getIntVTSignBit(Op.getValueType()) && 979 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 980 !MVT::isVector(Op.getOperand(0).getValueType())) { 981 // Only do this xform if FGETSIGN is valid or if before legalize. 982 if (!TLO.AfterLegalize || 983 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 984 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 985 // place. We expect the SHL to be eliminated by other optimizations. 986 SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 987 Op.getOperand(0)); 988 unsigned ShVal = MVT::getSizeInBits(Op.getValueType())-1; 989 SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 990 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 991 Sign, ShAmt)); 992 } 993 } 994#endif 995 break; 996 case ISD::ADD: 997 case ISD::SUB: 998 case ISD::INTRINSIC_WO_CHAIN: 999 case ISD::INTRINSIC_W_CHAIN: 1000 case ISD::INTRINSIC_VOID: 1001 // Just use ComputeMaskedBits to compute output bits. 1002 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 1003 break; 1004 } 1005 1006 // If we know the value of all of the demanded bits, return this as a 1007 // constant. 1008 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) 1009 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1010 1011 return false; 1012} 1013 1014/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1015/// in Mask are known to be either zero or one and return them in the 1016/// KnownZero/KnownOne bitsets. 1017void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 1018 const APInt &Mask, 1019 APInt &KnownZero, 1020 APInt &KnownOne, 1021 const SelectionDAG &DAG, 1022 unsigned Depth) const { 1023 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1024 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1025 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1026 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1027 "Should use MaskedValueIsZero if you don't know whether Op" 1028 " is a target node!"); 1029 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1030} 1031 1032/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1033/// targets that want to expose additional information about sign bits to the 1034/// DAG Combiner. 1035unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op, 1036 unsigned Depth) const { 1037 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1038 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1039 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1040 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1041 "Should use ComputeNumSignBits if you don't know whether Op" 1042 " is a target node!"); 1043 return 1; 1044} 1045 1046 1047/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1048/// and cc. If it is unable to simplify it, return a null SDOperand. 1049SDOperand 1050TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 1051 ISD::CondCode Cond, bool foldBooleans, 1052 DAGCombinerInfo &DCI) const { 1053 SelectionDAG &DAG = DCI.DAG; 1054 1055 // These setcc operations always fold. 1056 switch (Cond) { 1057 default: break; 1058 case ISD::SETFALSE: 1059 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1060 case ISD::SETTRUE: 1061 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1062 } 1063 1064 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 1065 uint64_t C1 = N1C->getValue(); 1066 if (isa<ConstantSDNode>(N0.Val)) { 1067 return DAG.FoldSetCC(VT, N0, N1, Cond); 1068 } else { 1069 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1070 // equality comparison, then we're just comparing whether X itself is 1071 // zero. 1072 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1073 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1074 N0.getOperand(1).getOpcode() == ISD::Constant) { 1075 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1076 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1077 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) { 1078 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1079 // (srl (ctlz x), 5) == 0 -> X != 0 1080 // (srl (ctlz x), 5) != 1 -> X != 0 1081 Cond = ISD::SETNE; 1082 } else { 1083 // (srl (ctlz x), 5) != 0 -> X == 0 1084 // (srl (ctlz x), 5) == 1 -> X == 0 1085 Cond = ISD::SETEQ; 1086 } 1087 SDOperand Zero = DAG.getConstant(0, N0.getValueType()); 1088 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 1089 Zero, Cond); 1090 } 1091 } 1092 1093 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1094 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1095 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 1096 1097 // If the comparison constant has bits in the upper part, the 1098 // zero-extended value could never match. 1099 if (C1 & (~0ULL << InSize)) { 1100 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 1101 switch (Cond) { 1102 case ISD::SETUGT: 1103 case ISD::SETUGE: 1104 case ISD::SETEQ: return DAG.getConstant(0, VT); 1105 case ISD::SETULT: 1106 case ISD::SETULE: 1107 case ISD::SETNE: return DAG.getConstant(1, VT); 1108 case ISD::SETGT: 1109 case ISD::SETGE: 1110 // True if the sign bit of C1 is set. 1111 return DAG.getConstant((C1 & (1ULL << (VSize-1))) != 0, VT); 1112 case ISD::SETLT: 1113 case ISD::SETLE: 1114 // True if the sign bit of C1 isn't set. 1115 return DAG.getConstant((C1 & (1ULL << (VSize-1))) == 0, VT); 1116 default: 1117 break; 1118 } 1119 } 1120 1121 // Otherwise, we can perform the comparison with the low bits. 1122 switch (Cond) { 1123 case ISD::SETEQ: 1124 case ISD::SETNE: 1125 case ISD::SETUGT: 1126 case ISD::SETUGE: 1127 case ISD::SETULT: 1128 case ISD::SETULE: 1129 return DAG.getSetCC(VT, N0.getOperand(0), 1130 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 1131 Cond); 1132 default: 1133 break; // todo, be more careful with signed comparisons 1134 } 1135 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1136 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1137 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1138 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 1139 MVT::ValueType ExtDstTy = N0.getValueType(); 1140 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 1141 1142 // If the extended part has any inconsistent bits, it cannot ever 1143 // compare equal. In other words, they have to be all ones or all 1144 // zeros. 1145 uint64_t ExtBits = 1146 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 1147 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1148 return DAG.getConstant(Cond == ISD::SETNE, VT); 1149 1150 SDOperand ZextOp; 1151 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 1152 if (Op0Ty == ExtSrcTy) { 1153 ZextOp = N0.getOperand(0); 1154 } else { 1155 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 1156 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1157 DAG.getConstant(Imm, Op0Ty)); 1158 } 1159 if (!DCI.isCalledByLegalizer()) 1160 DCI.AddToWorklist(ZextOp.Val); 1161 // Otherwise, make this a use of a zext. 1162 return DAG.getSetCC(VT, ZextOp, 1163 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 1164 ExtDstTy), 1165 Cond); 1166 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 1167 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1168 1169 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1170 if (N0.getOpcode() == ISD::SETCC) { 1171 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1); 1172 if (TrueWhenTrue) 1173 return N0; 1174 1175 // Invert the condition. 1176 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1177 CC = ISD::getSetCCInverse(CC, 1178 MVT::isInteger(N0.getOperand(0).getValueType())); 1179 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); 1180 } 1181 1182 if ((N0.getOpcode() == ISD::XOR || 1183 (N0.getOpcode() == ISD::AND && 1184 N0.getOperand(0).getOpcode() == ISD::XOR && 1185 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1186 isa<ConstantSDNode>(N0.getOperand(1)) && 1187 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 1188 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1189 // can only do this if the top bits are known zero. 1190 unsigned BitWidth = N0.getValueSizeInBits(); 1191 if (DAG.MaskedValueIsZero(N0, 1192 APInt::getHighBitsSet(BitWidth, 1193 BitWidth-1))) { 1194 // Okay, get the un-inverted input value. 1195 SDOperand Val; 1196 if (N0.getOpcode() == ISD::XOR) 1197 Val = N0.getOperand(0); 1198 else { 1199 assert(N0.getOpcode() == ISD::AND && 1200 N0.getOperand(0).getOpcode() == ISD::XOR); 1201 // ((X^1)&1)^1 -> X & 1 1202 Val = DAG.getNode(ISD::AND, N0.getValueType(), 1203 N0.getOperand(0).getOperand(0), 1204 N0.getOperand(1)); 1205 } 1206 return DAG.getSetCC(VT, Val, N1, 1207 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1208 } 1209 } 1210 } 1211 1212 uint64_t MinVal, MaxVal; 1213 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 1214 if (ISD::isSignedIntSetCC(Cond)) { 1215 MinVal = 1ULL << (OperandBitSize-1); 1216 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 1217 MaxVal = ~0ULL >> (65-OperandBitSize); 1218 else 1219 MaxVal = 0; 1220 } else { 1221 MinVal = 0; 1222 MaxVal = ~0ULL >> (64-OperandBitSize); 1223 } 1224 1225 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1226 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1227 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1228 --C1; // X >= C0 --> X > (C0-1) 1229 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 1230 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1231 } 1232 1233 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1234 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1235 ++C1; // X <= C0 --> X < (C0+1) 1236 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 1237 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1238 } 1239 1240 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1241 return DAG.getConstant(0, VT); // X < MIN --> false 1242 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1243 return DAG.getConstant(1, VT); // X >= MIN --> true 1244 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1245 return DAG.getConstant(0, VT); // X > MAX --> false 1246 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1247 return DAG.getConstant(1, VT); // X <= MAX --> true 1248 1249 // Canonicalize setgt X, Min --> setne X, Min 1250 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1251 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1252 // Canonicalize setlt X, Max --> setne X, Max 1253 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1254 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1255 1256 // If we have setult X, 1, turn it into seteq X, 0 1257 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1258 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 1259 ISD::SETEQ); 1260 // If we have setugt X, Max-1, turn it into seteq X, Max 1261 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1262 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 1263 ISD::SETEQ); 1264 1265 // If we have "setcc X, C0", check to see if we can shrink the immediate 1266 // by changing cc. 1267 1268 // SETUGT X, SINTMAX -> SETLT X, 0 1269 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 1270 C1 == (~0ULL >> (65-OperandBitSize))) 1271 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 1272 ISD::SETLT); 1273 1274 // FIXME: Implement the rest of these. 1275 1276 // Fold bit comparisons when we can. 1277 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1278 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1279 if (ConstantSDNode *AndRHS = 1280 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1281 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1282 // Perform the xform if the AND RHS is a single bit. 1283 if (isPowerOf2_64(AndRHS->getValue())) { 1284 return DAG.getNode(ISD::SRL, VT, N0, 1285 DAG.getConstant(Log2_64(AndRHS->getValue()), 1286 getShiftAmountTy())); 1287 } 1288 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 1289 // (X & 8) == 8 --> (X & 8) >> 3 1290 // Perform the xform if C1 is a single bit. 1291 if (isPowerOf2_64(C1)) { 1292 return DAG.getNode(ISD::SRL, VT, N0, 1293 DAG.getConstant(Log2_64(C1), getShiftAmountTy())); 1294 } 1295 } 1296 } 1297 } 1298 } else if (isa<ConstantSDNode>(N0.Val)) { 1299 // Ensure that the constant occurs on the RHS. 1300 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1301 } 1302 1303 if (isa<ConstantFPSDNode>(N0.Val)) { 1304 // Constant fold or commute setcc. 1305 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond); 1306 if (O.Val) return O; 1307 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.Val)) { 1308 // If the RHS of an FP comparison is a constant, simplify it away in 1309 // some cases. 1310 if (CFP->getValueAPF().isNaN()) { 1311 // If an operand is known to be a nan, we can fold it. 1312 switch (ISD::getUnorderedFlavor(Cond)) { 1313 default: assert(0 && "Unknown flavor!"); 1314 case 0: // Known false. 1315 return DAG.getConstant(0, VT); 1316 case 1: // Known true. 1317 return DAG.getConstant(1, VT); 1318 case 2: // Undefined. 1319 return DAG.getNode(ISD::UNDEF, VT); 1320 } 1321 } 1322 1323 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1324 // constant if knowing that the operand is non-nan is enough. We prefer to 1325 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1326 // materialize 0.0. 1327 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1328 return DAG.getSetCC(VT, N0, N0, Cond); 1329 } 1330 1331 if (N0 == N1) { 1332 // We can always fold X == X for integer setcc's. 1333 if (MVT::isInteger(N0.getValueType())) 1334 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1335 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1336 if (UOF == 2) // FP operators that are undefined on NaNs. 1337 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1338 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1339 return DAG.getConstant(UOF, VT); 1340 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1341 // if it is not already. 1342 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1343 if (NewCond != Cond) 1344 return DAG.getSetCC(VT, N0, N1, NewCond); 1345 } 1346 1347 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1348 MVT::isInteger(N0.getValueType())) { 1349 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1350 N0.getOpcode() == ISD::XOR) { 1351 // Simplify (X+Y) == (X+Z) --> Y == Z 1352 if (N0.getOpcode() == N1.getOpcode()) { 1353 if (N0.getOperand(0) == N1.getOperand(0)) 1354 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 1355 if (N0.getOperand(1) == N1.getOperand(1)) 1356 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 1357 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1358 // If X op Y == Y op X, try other combinations. 1359 if (N0.getOperand(0) == N1.getOperand(1)) 1360 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 1361 if (N0.getOperand(1) == N1.getOperand(0)) 1362 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 1363 } 1364 } 1365 1366 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1367 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1368 // Turn (X+C1) == C2 --> X == C2-C1 1369 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 1370 return DAG.getSetCC(VT, N0.getOperand(0), 1371 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 1372 N0.getValueType()), Cond); 1373 } 1374 1375 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1376 if (N0.getOpcode() == ISD::XOR) 1377 // If we know that all of the inverted bits are zero, don't bother 1378 // performing the inversion. 1379 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1380 return 1381 DAG.getSetCC(VT, N0.getOperand(0), 1382 DAG.getConstant(LHSR->getAPIntValue() ^ 1383 RHSC->getAPIntValue(), 1384 N0.getValueType()), 1385 Cond); 1386 } 1387 1388 // Turn (C1-X) == C2 --> X == C1-C2 1389 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1390 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 1391 return 1392 DAG.getSetCC(VT, N0.getOperand(1), 1393 DAG.getConstant(SUBC->getAPIntValue() - 1394 RHSC->getAPIntValue(), 1395 N0.getValueType()), 1396 Cond); 1397 } 1398 } 1399 } 1400 1401 // Simplify (X+Z) == X --> Z == 0 1402 if (N0.getOperand(0) == N1) 1403 return DAG.getSetCC(VT, N0.getOperand(1), 1404 DAG.getConstant(0, N0.getValueType()), Cond); 1405 if (N0.getOperand(1) == N1) { 1406 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1407 return DAG.getSetCC(VT, N0.getOperand(0), 1408 DAG.getConstant(0, N0.getValueType()), Cond); 1409 else if (N0.Val->hasOneUse()) { 1410 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1411 // (Z-X) == X --> Z == X<<1 1412 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 1413 N1, 1414 DAG.getConstant(1, getShiftAmountTy())); 1415 if (!DCI.isCalledByLegalizer()) 1416 DCI.AddToWorklist(SH.Val); 1417 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 1418 } 1419 } 1420 } 1421 1422 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1423 N1.getOpcode() == ISD::XOR) { 1424 // Simplify X == (X+Z) --> Z == 0 1425 if (N1.getOperand(0) == N0) { 1426 return DAG.getSetCC(VT, N1.getOperand(1), 1427 DAG.getConstant(0, N1.getValueType()), Cond); 1428 } else if (N1.getOperand(1) == N0) { 1429 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1430 return DAG.getSetCC(VT, N1.getOperand(0), 1431 DAG.getConstant(0, N1.getValueType()), Cond); 1432 } else if (N1.Val->hasOneUse()) { 1433 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1434 // X == (Z-X) --> X<<1 == Z 1435 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 1436 DAG.getConstant(1, getShiftAmountTy())); 1437 if (!DCI.isCalledByLegalizer()) 1438 DCI.AddToWorklist(SH.Val); 1439 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 1440 } 1441 } 1442 } 1443 } 1444 1445 // Fold away ALL boolean setcc's. 1446 SDOperand Temp; 1447 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1448 switch (Cond) { 1449 default: assert(0 && "Unknown integer setcc!"); 1450 case ISD::SETEQ: // X == Y -> (X^Y)^1 1451 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1452 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 1453 if (!DCI.isCalledByLegalizer()) 1454 DCI.AddToWorklist(Temp.Val); 1455 break; 1456 case ISD::SETNE: // X != Y --> (X^Y) 1457 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1458 break; 1459 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 1460 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 1461 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1462 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 1463 if (!DCI.isCalledByLegalizer()) 1464 DCI.AddToWorklist(Temp.Val); 1465 break; 1466 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 1467 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 1468 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1469 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 1470 if (!DCI.isCalledByLegalizer()) 1471 DCI.AddToWorklist(Temp.Val); 1472 break; 1473 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 1474 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 1475 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1476 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 1477 if (!DCI.isCalledByLegalizer()) 1478 DCI.AddToWorklist(Temp.Val); 1479 break; 1480 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 1481 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 1482 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1483 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 1484 break; 1485 } 1486 if (VT != MVT::i1) { 1487 if (!DCI.isCalledByLegalizer()) 1488 DCI.AddToWorklist(N0.Val); 1489 // FIXME: If running after legalize, we probably can't do this. 1490 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1491 } 1492 return N0; 1493 } 1494 1495 // Could not fold it. 1496 return SDOperand(); 1497} 1498 1499SDOperand TargetLowering:: 1500PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1501 // Default implementation: no optimization. 1502 return SDOperand(); 1503} 1504 1505//===----------------------------------------------------------------------===// 1506// Inline Assembler Implementation Methods 1507//===----------------------------------------------------------------------===// 1508 1509TargetLowering::ConstraintType 1510TargetLowering::getConstraintType(const std::string &Constraint) const { 1511 // FIXME: lots more standard ones to handle. 1512 if (Constraint.size() == 1) { 1513 switch (Constraint[0]) { 1514 default: break; 1515 case 'r': return C_RegisterClass; 1516 case 'm': // memory 1517 case 'o': // offsetable 1518 case 'V': // not offsetable 1519 return C_Memory; 1520 case 'i': // Simple Integer or Relocatable Constant 1521 case 'n': // Simple Integer 1522 case 's': // Relocatable Constant 1523 case 'X': // Allow ANY value. 1524 case 'I': // Target registers. 1525 case 'J': 1526 case 'K': 1527 case 'L': 1528 case 'M': 1529 case 'N': 1530 case 'O': 1531 case 'P': 1532 return C_Other; 1533 } 1534 } 1535 1536 if (Constraint.size() > 1 && Constraint[0] == '{' && 1537 Constraint[Constraint.size()-1] == '}') 1538 return C_Register; 1539 return C_Unknown; 1540} 1541 1542/// LowerXConstraint - try to replace an X constraint, which matches anything, 1543/// with another that has more specific requirements based on the type of the 1544/// corresponding operand. 1545void TargetLowering::lowerXConstraint(MVT::ValueType ConstraintVT, 1546 std::string& s) const { 1547 if (MVT::isInteger(ConstraintVT)) 1548 s = "r"; 1549 else if (MVT::isFloatingPoint(ConstraintVT)) 1550 s = "f"; // works for many targets 1551 else 1552 s = ""; 1553} 1554 1555/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1556/// vector. If it is invalid, don't add anything to Ops. 1557void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op, 1558 char ConstraintLetter, 1559 std::vector<SDOperand> &Ops, 1560 SelectionDAG &DAG) { 1561 switch (ConstraintLetter) { 1562 default: break; 1563 case 'X': // Allows any operand; labels (basic block) use this. 1564 if (Op.getOpcode() == ISD::BasicBlock) { 1565 Ops.push_back(Op); 1566 return; 1567 } 1568 // fall through 1569 case 'i': // Simple Integer or Relocatable Constant 1570 case 'n': // Simple Integer 1571 case 's': { // Relocatable Constant 1572 // These operands are interested in values of the form (GV+C), where C may 1573 // be folded in as an offset of GV, or it may be explicitly added. Also, it 1574 // is possible and fine if either GV or C are missing. 1575 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1576 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 1577 1578 // If we have "(add GV, C)", pull out GV/C 1579 if (Op.getOpcode() == ISD::ADD) { 1580 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1581 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 1582 if (C == 0 || GA == 0) { 1583 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 1584 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 1585 } 1586 if (C == 0 || GA == 0) 1587 C = 0, GA = 0; 1588 } 1589 1590 // If we find a valid operand, map to the TargetXXX version so that the 1591 // value itself doesn't get selected. 1592 if (GA) { // Either &GV or &GV+C 1593 if (ConstraintLetter != 'n') { 1594 int64_t Offs = GA->getOffset(); 1595 if (C) Offs += C->getValue(); 1596 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 1597 Op.getValueType(), Offs)); 1598 return; 1599 } 1600 } 1601 if (C) { // just C, no GV. 1602 // Simple constants are not allowed for 's'. 1603 if (ConstraintLetter != 's') { 1604 Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType())); 1605 return; 1606 } 1607 } 1608 break; 1609 } 1610 } 1611} 1612 1613std::vector<unsigned> TargetLowering:: 1614getRegClassForInlineAsmConstraint(const std::string &Constraint, 1615 MVT::ValueType VT) const { 1616 return std::vector<unsigned>(); 1617} 1618 1619 1620std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 1621getRegForInlineAsmConstraint(const std::string &Constraint, 1622 MVT::ValueType VT) const { 1623 if (Constraint[0] != '{') 1624 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1625 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 1626 1627 // Remove the braces from around the name. 1628 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 1629 1630 // Figure out which register class contains this reg. 1631 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 1632 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 1633 E = RI->regclass_end(); RCI != E; ++RCI) { 1634 const TargetRegisterClass *RC = *RCI; 1635 1636 // If none of the the value types for this register class are valid, we 1637 // can't use it. For example, 64-bit reg classes on 32-bit targets. 1638 bool isLegal = false; 1639 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1640 I != E; ++I) { 1641 if (isTypeLegal(*I)) { 1642 isLegal = true; 1643 break; 1644 } 1645 } 1646 1647 if (!isLegal) continue; 1648 1649 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 1650 I != E; ++I) { 1651 if (StringsEqualNoCase(RegName, RI->get(*I).Name)) 1652 return std::make_pair(*I, RC); 1653 } 1654 } 1655 1656 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1657} 1658 1659//===----------------------------------------------------------------------===// 1660// Loop Strength Reduction hooks 1661//===----------------------------------------------------------------------===// 1662 1663/// isLegalAddressingMode - Return true if the addressing mode represented 1664/// by AM is legal for this target, for a load/store of the specified type. 1665bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 1666 const Type *Ty) const { 1667 // The default implementation of this implements a conservative RISCy, r+r and 1668 // r+i addr mode. 1669 1670 // Allows a sign-extended 16-bit immediate field. 1671 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1672 return false; 1673 1674 // No global is ever allowed as a base. 1675 if (AM.BaseGV) 1676 return false; 1677 1678 // Only support r+r, 1679 switch (AM.Scale) { 1680 case 0: // "r+i" or just "i", depending on HasBaseReg. 1681 break; 1682 case 1: 1683 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1684 return false; 1685 // Otherwise we have r+r or r+i. 1686 break; 1687 case 2: 1688 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1689 return false; 1690 // Allow 2*r as r+r. 1691 break; 1692 } 1693 1694 return true; 1695} 1696 1697// Magic for divide replacement 1698 1699struct ms { 1700 int64_t m; // magic number 1701 int64_t s; // shift amount 1702}; 1703 1704struct mu { 1705 uint64_t m; // magic number 1706 int64_t a; // add indicator 1707 int64_t s; // shift amount 1708}; 1709 1710/// magic - calculate the magic numbers required to codegen an integer sdiv as 1711/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1712/// or -1. 1713static ms magic32(int32_t d) { 1714 int32_t p; 1715 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 1716 const uint32_t two31 = 0x80000000U; 1717 struct ms mag; 1718 1719 ad = abs(d); 1720 t = two31 + ((uint32_t)d >> 31); 1721 anc = t - 1 - t%ad; // absolute value of nc 1722 p = 31; // initialize p 1723 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 1724 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1725 q2 = two31/ad; // initialize q2 = 2p/abs(d) 1726 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1727 do { 1728 p = p + 1; 1729 q1 = 2*q1; // update q1 = 2p/abs(nc) 1730 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1731 if (r1 >= anc) { // must be unsigned comparison 1732 q1 = q1 + 1; 1733 r1 = r1 - anc; 1734 } 1735 q2 = 2*q2; // update q2 = 2p/abs(d) 1736 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1737 if (r2 >= ad) { // must be unsigned comparison 1738 q2 = q2 + 1; 1739 r2 = r2 - ad; 1740 } 1741 delta = ad - r2; 1742 } while (q1 < delta || (q1 == delta && r1 == 0)); 1743 1744 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 1745 if (d < 0) mag.m = -mag.m; // resulting magic number 1746 mag.s = p - 32; // resulting shift 1747 return mag; 1748} 1749 1750/// magicu - calculate the magic numbers required to codegen an integer udiv as 1751/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1752static mu magicu32(uint32_t d) { 1753 int32_t p; 1754 uint32_t nc, delta, q1, r1, q2, r2; 1755 struct mu magu; 1756 magu.a = 0; // initialize "add" indicator 1757 nc = - 1 - (-d)%d; 1758 p = 31; // initialize p 1759 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 1760 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 1761 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 1762 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 1763 do { 1764 p = p + 1; 1765 if (r1 >= nc - r1 ) { 1766 q1 = 2*q1 + 1; // update q1 1767 r1 = 2*r1 - nc; // update r1 1768 } 1769 else { 1770 q1 = 2*q1; // update q1 1771 r1 = 2*r1; // update r1 1772 } 1773 if (r2 + 1 >= d - r2) { 1774 if (q2 >= 0x7FFFFFFF) magu.a = 1; 1775 q2 = 2*q2 + 1; // update q2 1776 r2 = 2*r2 + 1 - d; // update r2 1777 } 1778 else { 1779 if (q2 >= 0x80000000) magu.a = 1; 1780 q2 = 2*q2; // update q2 1781 r2 = 2*r2 + 1; // update r2 1782 } 1783 delta = d - 1 - r2; 1784 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 1785 magu.m = q2 + 1; // resulting magic number 1786 magu.s = p - 32; // resulting shift 1787 return magu; 1788} 1789 1790/// magic - calculate the magic numbers required to codegen an integer sdiv as 1791/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1792/// or -1. 1793static ms magic64(int64_t d) { 1794 int64_t p; 1795 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 1796 const uint64_t two63 = 9223372036854775808ULL; // 2^63 1797 struct ms mag; 1798 1799 ad = d >= 0 ? d : -d; 1800 t = two63 + ((uint64_t)d >> 63); 1801 anc = t - 1 - t%ad; // absolute value of nc 1802 p = 63; // initialize p 1803 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 1804 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1805 q2 = two63/ad; // initialize q2 = 2p/abs(d) 1806 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1807 do { 1808 p = p + 1; 1809 q1 = 2*q1; // update q1 = 2p/abs(nc) 1810 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1811 if (r1 >= anc) { // must be unsigned comparison 1812 q1 = q1 + 1; 1813 r1 = r1 - anc; 1814 } 1815 q2 = 2*q2; // update q2 = 2p/abs(d) 1816 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1817 if (r2 >= ad) { // must be unsigned comparison 1818 q2 = q2 + 1; 1819 r2 = r2 - ad; 1820 } 1821 delta = ad - r2; 1822 } while (q1 < delta || (q1 == delta && r1 == 0)); 1823 1824 mag.m = q2 + 1; 1825 if (d < 0) mag.m = -mag.m; // resulting magic number 1826 mag.s = p - 64; // resulting shift 1827 return mag; 1828} 1829 1830/// magicu - calculate the magic numbers required to codegen an integer udiv as 1831/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1832static mu magicu64(uint64_t d) 1833{ 1834 int64_t p; 1835 uint64_t nc, delta, q1, r1, q2, r2; 1836 struct mu magu; 1837 magu.a = 0; // initialize "add" indicator 1838 nc = - 1 - (-d)%d; 1839 p = 63; // initialize p 1840 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 1841 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 1842 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 1843 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 1844 do { 1845 p = p + 1; 1846 if (r1 >= nc - r1 ) { 1847 q1 = 2*q1 + 1; // update q1 1848 r1 = 2*r1 - nc; // update r1 1849 } 1850 else { 1851 q1 = 2*q1; // update q1 1852 r1 = 2*r1; // update r1 1853 } 1854 if (r2 + 1 >= d - r2) { 1855 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 1856 q2 = 2*q2 + 1; // update q2 1857 r2 = 2*r2 + 1 - d; // update r2 1858 } 1859 else { 1860 if (q2 >= 0x8000000000000000ull) magu.a = 1; 1861 q2 = 2*q2; // update q2 1862 r2 = 2*r2 + 1; // update r2 1863 } 1864 delta = d - 1 - r2; 1865 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0))); 1866 magu.m = q2 + 1; // resulting magic number 1867 magu.s = p - 64; // resulting shift 1868 return magu; 1869} 1870 1871/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 1872/// return a DAG expression to select that will generate the same value by 1873/// multiplying by a magic number. See: 1874/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 1875SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 1876 std::vector<SDNode*>* Created) const { 1877 MVT::ValueType VT = N->getValueType(0); 1878 1879 // Check to see if we can do this. 1880 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 1881 return SDOperand(); // BuildSDIV only operates on i32 or i64 1882 1883 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 1884 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 1885 1886 // Multiply the numerator (operand 0) by the magic value 1887 SDOperand Q; 1888 if (isOperationLegal(ISD::MULHS, VT)) 1889 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 1890 DAG.getConstant(magics.m, VT)); 1891 else if (isOperationLegal(ISD::SMUL_LOHI, VT)) 1892 Q = SDOperand(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), 1893 N->getOperand(0), 1894 DAG.getConstant(magics.m, VT)).Val, 1); 1895 else 1896 return SDOperand(); // No mulhs or equvialent 1897 // If d > 0 and m < 0, add the numerator 1898 if (d > 0 && magics.m < 0) { 1899 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 1900 if (Created) 1901 Created->push_back(Q.Val); 1902 } 1903 // If d < 0 and m > 0, subtract the numerator. 1904 if (d < 0 && magics.m > 0) { 1905 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 1906 if (Created) 1907 Created->push_back(Q.Val); 1908 } 1909 // Shift right algebraic if shift value is nonzero 1910 if (magics.s > 0) { 1911 Q = DAG.getNode(ISD::SRA, VT, Q, 1912 DAG.getConstant(magics.s, getShiftAmountTy())); 1913 if (Created) 1914 Created->push_back(Q.Val); 1915 } 1916 // Extract the sign bit and add it to the quotient 1917 SDOperand T = 1918 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 1919 getShiftAmountTy())); 1920 if (Created) 1921 Created->push_back(T.Val); 1922 return DAG.getNode(ISD::ADD, VT, Q, T); 1923} 1924 1925/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 1926/// return a DAG expression to select that will generate the same value by 1927/// multiplying by a magic number. See: 1928/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 1929SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 1930 std::vector<SDNode*>* Created) const { 1931 MVT::ValueType VT = N->getValueType(0); 1932 1933 // Check to see if we can do this. 1934 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 1935 return SDOperand(); // BuildUDIV only operates on i32 or i64 1936 1937 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 1938 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 1939 1940 // Multiply the numerator (operand 0) by the magic value 1941 SDOperand Q; 1942 if (isOperationLegal(ISD::MULHU, VT)) 1943 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 1944 DAG.getConstant(magics.m, VT)); 1945 else if (isOperationLegal(ISD::UMUL_LOHI, VT)) 1946 Q = SDOperand(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), 1947 N->getOperand(0), 1948 DAG.getConstant(magics.m, VT)).Val, 1); 1949 else 1950 return SDOperand(); // No mulhu or equvialent 1951 if (Created) 1952 Created->push_back(Q.Val); 1953 1954 if (magics.a == 0) { 1955 return DAG.getNode(ISD::SRL, VT, Q, 1956 DAG.getConstant(magics.s, getShiftAmountTy())); 1957 } else { 1958 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 1959 if (Created) 1960 Created->push_back(NPQ.Val); 1961 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 1962 DAG.getConstant(1, getShiftAmountTy())); 1963 if (Created) 1964 Created->push_back(NPQ.Val); 1965 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 1966 if (Created) 1967 Created->push_back(NPQ.Val); 1968 return DAG.getNode(ISD::SRL, VT, NPQ, 1969 DAG.getConstant(magics.s-1, getShiftAmountTy())); 1970 } 1971} 1972