TargetLowering.cpp revision 34525f9ac098c1c6bc9002886d6da3039a284fd2 
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/CodeGen/Analysis.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineJumpTableInfo.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/DataLayout.h"
23#include "llvm/DerivedTypes.h"
24#include "llvm/GlobalVariable.h"
25#include "llvm/MC/MCAsmInfo.h"
26#include "llvm/MC/MCExpr.h"
27#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/ErrorHandling.h"
29#include "llvm/Support/MathExtras.h"
30#include "llvm/Target/TargetLoweringObjectFile.h"
31#include "llvm/Target/TargetMachine.h"
32#include "llvm/Target/TargetRegisterInfo.h"
33#include <cctype>
34using namespace llvm;
35
36/// InitLibcallNames - Set default libcall names.
37///
38static void InitLibcallNames(const char **Names) {
39  Names[RTLIB::SHL_I16] = "__ashlhi3";
40  Names[RTLIB::SHL_I32] = "__ashlsi3";
41  Names[RTLIB::SHL_I64] = "__ashldi3";
42  Names[RTLIB::SHL_I128] = "__ashlti3";
43  Names[RTLIB::SRL_I16] = "__lshrhi3";
44  Names[RTLIB::SRL_I32] = "__lshrsi3";
45  Names[RTLIB::SRL_I64] = "__lshrdi3";
46  Names[RTLIB::SRL_I128] = "__lshrti3";
47  Names[RTLIB::SRA_I16] = "__ashrhi3";
48  Names[RTLIB::SRA_I32] = "__ashrsi3";
49  Names[RTLIB::SRA_I64] = "__ashrdi3";
50  Names[RTLIB::SRA_I128] = "__ashrti3";
51  Names[RTLIB::MUL_I8] = "__mulqi3";
52  Names[RTLIB::MUL_I16] = "__mulhi3";
53  Names[RTLIB::MUL_I32] = "__mulsi3";
54  Names[RTLIB::MUL_I64] = "__muldi3";
55  Names[RTLIB::MUL_I128] = "__multi3";
56  Names[RTLIB::MULO_I32] = "__mulosi4";
57  Names[RTLIB::MULO_I64] = "__mulodi4";
58  Names[RTLIB::MULO_I128] = "__muloti4";
59  Names[RTLIB::SDIV_I8] = "__divqi3";
60  Names[RTLIB::SDIV_I16] = "__divhi3";
61  Names[RTLIB::SDIV_I32] = "__divsi3";
62  Names[RTLIB::SDIV_I64] = "__divdi3";
63  Names[RTLIB::SDIV_I128] = "__divti3";
64  Names[RTLIB::UDIV_I8] = "__udivqi3";
65  Names[RTLIB::UDIV_I16] = "__udivhi3";
66  Names[RTLIB::UDIV_I32] = "__udivsi3";
67  Names[RTLIB::UDIV_I64] = "__udivdi3";
68  Names[RTLIB::UDIV_I128] = "__udivti3";
69  Names[RTLIB::SREM_I8] = "__modqi3";
70  Names[RTLIB::SREM_I16] = "__modhi3";
71  Names[RTLIB::SREM_I32] = "__modsi3";
72  Names[RTLIB::SREM_I64] = "__moddi3";
73  Names[RTLIB::SREM_I128] = "__modti3";
74  Names[RTLIB::UREM_I8] = "__umodqi3";
75  Names[RTLIB::UREM_I16] = "__umodhi3";
76  Names[RTLIB::UREM_I32] = "__umodsi3";
77  Names[RTLIB::UREM_I64] = "__umoddi3";
78  Names[RTLIB::UREM_I128] = "__umodti3";
79
80  // These are generally not available.
81  Names[RTLIB::SDIVREM_I8] = 0;
82  Names[RTLIB::SDIVREM_I16] = 0;
83  Names[RTLIB::SDIVREM_I32] = 0;
84  Names[RTLIB::SDIVREM_I64] = 0;
85  Names[RTLIB::SDIVREM_I128] = 0;
86  Names[RTLIB::UDIVREM_I8] = 0;
87  Names[RTLIB::UDIVREM_I16] = 0;
88  Names[RTLIB::UDIVREM_I32] = 0;
89  Names[RTLIB::UDIVREM_I64] = 0;
90  Names[RTLIB::UDIVREM_I128] = 0;
91
92  Names[RTLIB::NEG_I32] = "__negsi2";
93  Names[RTLIB::NEG_I64] = "__negdi2";
94  Names[RTLIB::ADD_F32] = "__addsf3";
95  Names[RTLIB::ADD_F64] = "__adddf3";
96  Names[RTLIB::ADD_F80] = "__addxf3";
97  Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
98  Names[RTLIB::SUB_F32] = "__subsf3";
99  Names[RTLIB::SUB_F64] = "__subdf3";
100  Names[RTLIB::SUB_F80] = "__subxf3";
101  Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
102  Names[RTLIB::MUL_F32] = "__mulsf3";
103  Names[RTLIB::MUL_F64] = "__muldf3";
104  Names[RTLIB::MUL_F80] = "__mulxf3";
105  Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
106  Names[RTLIB::DIV_F32] = "__divsf3";
107  Names[RTLIB::DIV_F64] = "__divdf3";
108  Names[RTLIB::DIV_F80] = "__divxf3";
109  Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
110  Names[RTLIB::REM_F32] = "fmodf";
111  Names[RTLIB::REM_F64] = "fmod";
112  Names[RTLIB::REM_F80] = "fmodl";
113  Names[RTLIB::REM_PPCF128] = "fmodl";
114  Names[RTLIB::FMA_F32] = "fmaf";
115  Names[RTLIB::FMA_F64] = "fma";
116  Names[RTLIB::FMA_F80] = "fmal";
117  Names[RTLIB::FMA_PPCF128] = "fmal";
118  Names[RTLIB::POWI_F32] = "__powisf2";
119  Names[RTLIB::POWI_F64] = "__powidf2";
120  Names[RTLIB::POWI_F80] = "__powixf2";
121  Names[RTLIB::POWI_PPCF128] = "__powitf2";
122  Names[RTLIB::SQRT_F32] = "sqrtf";
123  Names[RTLIB::SQRT_F64] = "sqrt";
124  Names[RTLIB::SQRT_F80] = "sqrtl";
125  Names[RTLIB::SQRT_PPCF128] = "sqrtl";
126  Names[RTLIB::LOG_F32] = "logf";
127  Names[RTLIB::LOG_F64] = "log";
128  Names[RTLIB::LOG_F80] = "logl";
129  Names[RTLIB::LOG_PPCF128] = "logl";
130  Names[RTLIB::LOG2_F32] = "log2f";
131  Names[RTLIB::LOG2_F64] = "log2";
132  Names[RTLIB::LOG2_F80] = "log2l";
133  Names[RTLIB::LOG2_PPCF128] = "log2l";
134  Names[RTLIB::LOG10_F32] = "log10f";
135  Names[RTLIB::LOG10_F64] = "log10";
136  Names[RTLIB::LOG10_F80] = "log10l";
137  Names[RTLIB::LOG10_PPCF128] = "log10l";
138  Names[RTLIB::EXP_F32] = "expf";
139  Names[RTLIB::EXP_F64] = "exp";
140  Names[RTLIB::EXP_F80] = "expl";
141  Names[RTLIB::EXP_PPCF128] = "expl";
142  Names[RTLIB::EXP2_F32] = "exp2f";
143  Names[RTLIB::EXP2_F64] = "exp2";
144  Names[RTLIB::EXP2_F80] = "exp2l";
145  Names[RTLIB::EXP2_PPCF128] = "exp2l";
146  Names[RTLIB::SIN_F32] = "sinf";
147  Names[RTLIB::SIN_F64] = "sin";
148  Names[RTLIB::SIN_F80] = "sinl";
149  Names[RTLIB::SIN_PPCF128] = "sinl";
150  Names[RTLIB::COS_F32] = "cosf";
151  Names[RTLIB::COS_F64] = "cos";
152  Names[RTLIB::COS_F80] = "cosl";
153  Names[RTLIB::COS_PPCF128] = "cosl";
154  Names[RTLIB::POW_F32] = "powf";
155  Names[RTLIB::POW_F64] = "pow";
156  Names[RTLIB::POW_F80] = "powl";
157  Names[RTLIB::POW_PPCF128] = "powl";
158  Names[RTLIB::CEIL_F32] = "ceilf";
159  Names[RTLIB::CEIL_F64] = "ceil";
160  Names[RTLIB::CEIL_F80] = "ceill";
161  Names[RTLIB::CEIL_PPCF128] = "ceill";
162  Names[RTLIB::TRUNC_F32] = "truncf";
163  Names[RTLIB::TRUNC_F64] = "trunc";
164  Names[RTLIB::TRUNC_F80] = "truncl";
165  Names[RTLIB::TRUNC_PPCF128] = "truncl";
166  Names[RTLIB::RINT_F32] = "rintf";
167  Names[RTLIB::RINT_F64] = "rint";
168  Names[RTLIB::RINT_F80] = "rintl";
169  Names[RTLIB::RINT_PPCF128] = "rintl";
170  Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
171  Names[RTLIB::NEARBYINT_F64] = "nearbyint";
172  Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
173  Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
174  Names[RTLIB::FLOOR_F32] = "floorf";
175  Names[RTLIB::FLOOR_F64] = "floor";
176  Names[RTLIB::FLOOR_F80] = "floorl";
177  Names[RTLIB::FLOOR_PPCF128] = "floorl";
178  Names[RTLIB::COPYSIGN_F32] = "copysignf";
179  Names[RTLIB::COPYSIGN_F64] = "copysign";
180  Names[RTLIB::COPYSIGN_F80] = "copysignl";
181  Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
182  Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
183  Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
184  Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
185  Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
186  Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
187  Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
188  Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
189  Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
190  Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
191  Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
192  Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
193  Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
194  Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
195  Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
196  Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
197  Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
198  Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
199  Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
200  Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
201  Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
202  Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
203  Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
204  Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
205  Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
206  Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
207  Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
208  Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
209  Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
210  Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
211  Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
212  Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
213  Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
214  Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
215  Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
216  Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
217  Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
218  Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
219  Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
220  Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
221  Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
222  Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
223  Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
224  Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
225  Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
226  Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
227  Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
228  Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
229  Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
230  Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
231  Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
232  Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
233  Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
234  Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
235  Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
236  Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
237  Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
238  Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
239  Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
240  Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
241  Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
242  Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
243  Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
244  Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
245  Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
246  Names[RTLIB::OEQ_F32] = "__eqsf2";
247  Names[RTLIB::OEQ_F64] = "__eqdf2";
248  Names[RTLIB::UNE_F32] = "__nesf2";
249  Names[RTLIB::UNE_F64] = "__nedf2";
250  Names[RTLIB::OGE_F32] = "__gesf2";
251  Names[RTLIB::OGE_F64] = "__gedf2";
252  Names[RTLIB::OLT_F32] = "__ltsf2";
253  Names[RTLIB::OLT_F64] = "__ltdf2";
254  Names[RTLIB::OLE_F32] = "__lesf2";
255  Names[RTLIB::OLE_F64] = "__ledf2";
256  Names[RTLIB::OGT_F32] = "__gtsf2";
257  Names[RTLIB::OGT_F64] = "__gtdf2";
258  Names[RTLIB::UO_F32] = "__unordsf2";
259  Names[RTLIB::UO_F64] = "__unorddf2";
260  Names[RTLIB::O_F32] = "__unordsf2";
261  Names[RTLIB::O_F64] = "__unorddf2";
262  Names[RTLIB::MEMCPY] = "memcpy";
263  Names[RTLIB::MEMMOVE] = "memmove";
264  Names[RTLIB::MEMSET] = "memset";
265  Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
266  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
267  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
268  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
269  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
270  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
271  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
272  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
273  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
274  Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
275  Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
276  Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
277  Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
278  Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
279  Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
280  Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
281  Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
282  Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
283  Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
284  Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
285  Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
286  Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
287  Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
288  Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
289  Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
290  Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
291  Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
292  Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
293  Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
294  Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
295  Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
296  Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
297  Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
298}
299
300/// InitLibcallCallingConvs - Set default libcall CallingConvs.
301///
302static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
303  for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
304    CCs[i] = CallingConv::C;
305  }
306}
307
308/// getFPEXT - Return the FPEXT_*_* value for the given types, or
309/// UNKNOWN_LIBCALL if there is none.
310RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
311  if (OpVT == MVT::f32) {
312    if (RetVT == MVT::f64)
313      return FPEXT_F32_F64;
314  }
315
316  return UNKNOWN_LIBCALL;
317}
318
319/// getFPROUND - Return the FPROUND_*_* value for the given types, or
320/// UNKNOWN_LIBCALL if there is none.
321RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
322  if (RetVT == MVT::f32) {
323    if (OpVT == MVT::f64)
324      return FPROUND_F64_F32;
325    if (OpVT == MVT::f80)
326      return FPROUND_F80_F32;
327    if (OpVT == MVT::ppcf128)
328      return FPROUND_PPCF128_F32;
329  } else if (RetVT == MVT::f64) {
330    if (OpVT == MVT::f80)
331      return FPROUND_F80_F64;
332    if (OpVT == MVT::ppcf128)
333      return FPROUND_PPCF128_F64;
334  }
335
336  return UNKNOWN_LIBCALL;
337}
338
339/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
340/// UNKNOWN_LIBCALL if there is none.
341RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
342  if (OpVT == MVT::f32) {
343    if (RetVT == MVT::i8)
344      return FPTOSINT_F32_I8;
345    if (RetVT == MVT::i16)
346      return FPTOSINT_F32_I16;
347    if (RetVT == MVT::i32)
348      return FPTOSINT_F32_I32;
349    if (RetVT == MVT::i64)
350      return FPTOSINT_F32_I64;
351    if (RetVT == MVT::i128)
352      return FPTOSINT_F32_I128;
353  } else if (OpVT == MVT::f64) {
354    if (RetVT == MVT::i8)
355      return FPTOSINT_F64_I8;
356    if (RetVT == MVT::i16)
357      return FPTOSINT_F64_I16;
358    if (RetVT == MVT::i32)
359      return FPTOSINT_F64_I32;
360    if (RetVT == MVT::i64)
361      return FPTOSINT_F64_I64;
362    if (RetVT == MVT::i128)
363      return FPTOSINT_F64_I128;
364  } else if (OpVT == MVT::f80) {
365    if (RetVT == MVT::i32)
366      return FPTOSINT_F80_I32;
367    if (RetVT == MVT::i64)
368      return FPTOSINT_F80_I64;
369    if (RetVT == MVT::i128)
370      return FPTOSINT_F80_I128;
371  } else if (OpVT == MVT::ppcf128) {
372    if (RetVT == MVT::i32)
373      return FPTOSINT_PPCF128_I32;
374    if (RetVT == MVT::i64)
375      return FPTOSINT_PPCF128_I64;
376    if (RetVT == MVT::i128)
377      return FPTOSINT_PPCF128_I128;
378  }
379  return UNKNOWN_LIBCALL;
380}
381
382/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
383/// UNKNOWN_LIBCALL if there is none.
384RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
385  if (OpVT == MVT::f32) {
386    if (RetVT == MVT::i8)
387      return FPTOUINT_F32_I8;
388    if (RetVT == MVT::i16)
389      return FPTOUINT_F32_I16;
390    if (RetVT == MVT::i32)
391      return FPTOUINT_F32_I32;
392    if (RetVT == MVT::i64)
393      return FPTOUINT_F32_I64;
394    if (RetVT == MVT::i128)
395      return FPTOUINT_F32_I128;
396  } else if (OpVT == MVT::f64) {
397    if (RetVT == MVT::i8)
398      return FPTOUINT_F64_I8;
399    if (RetVT == MVT::i16)
400      return FPTOUINT_F64_I16;
401    if (RetVT == MVT::i32)
402      return FPTOUINT_F64_I32;
403    if (RetVT == MVT::i64)
404      return FPTOUINT_F64_I64;
405    if (RetVT == MVT::i128)
406      return FPTOUINT_F64_I128;
407  } else if (OpVT == MVT::f80) {
408    if (RetVT == MVT::i32)
409      return FPTOUINT_F80_I32;
410    if (RetVT == MVT::i64)
411      return FPTOUINT_F80_I64;
412    if (RetVT == MVT::i128)
413      return FPTOUINT_F80_I128;
414  } else if (OpVT == MVT::ppcf128) {
415    if (RetVT == MVT::i32)
416      return FPTOUINT_PPCF128_I32;
417    if (RetVT == MVT::i64)
418      return FPTOUINT_PPCF128_I64;
419    if (RetVT == MVT::i128)
420      return FPTOUINT_PPCF128_I128;
421  }
422  return UNKNOWN_LIBCALL;
423}
424
425/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
426/// UNKNOWN_LIBCALL if there is none.
427RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
428  if (OpVT == MVT::i32) {
429    if (RetVT == MVT::f32)
430      return SINTTOFP_I32_F32;
431    else if (RetVT == MVT::f64)
432      return SINTTOFP_I32_F64;
433    else if (RetVT == MVT::f80)
434      return SINTTOFP_I32_F80;
435    else if (RetVT == MVT::ppcf128)
436      return SINTTOFP_I32_PPCF128;
437  } else if (OpVT == MVT::i64) {
438    if (RetVT == MVT::f32)
439      return SINTTOFP_I64_F32;
440    else if (RetVT == MVT::f64)
441      return SINTTOFP_I64_F64;
442    else if (RetVT == MVT::f80)
443      return SINTTOFP_I64_F80;
444    else if (RetVT == MVT::ppcf128)
445      return SINTTOFP_I64_PPCF128;
446  } else if (OpVT == MVT::i128) {
447    if (RetVT == MVT::f32)
448      return SINTTOFP_I128_F32;
449    else if (RetVT == MVT::f64)
450      return SINTTOFP_I128_F64;
451    else if (RetVT == MVT::f80)
452      return SINTTOFP_I128_F80;
453    else if (RetVT == MVT::ppcf128)
454      return SINTTOFP_I128_PPCF128;
455  }
456  return UNKNOWN_LIBCALL;
457}
458
459/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
460/// UNKNOWN_LIBCALL if there is none.
461RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
462  if (OpVT == MVT::i32) {
463    if (RetVT == MVT::f32)
464      return UINTTOFP_I32_F32;
465    else if (RetVT == MVT::f64)
466      return UINTTOFP_I32_F64;
467    else if (RetVT == MVT::f80)
468      return UINTTOFP_I32_F80;
469    else if (RetVT == MVT::ppcf128)
470      return UINTTOFP_I32_PPCF128;
471  } else if (OpVT == MVT::i64) {
472    if (RetVT == MVT::f32)
473      return UINTTOFP_I64_F32;
474    else if (RetVT == MVT::f64)
475      return UINTTOFP_I64_F64;
476    else if (RetVT == MVT::f80)
477      return UINTTOFP_I64_F80;
478    else if (RetVT == MVT::ppcf128)
479      return UINTTOFP_I64_PPCF128;
480  } else if (OpVT == MVT::i128) {
481    if (RetVT == MVT::f32)
482      return UINTTOFP_I128_F32;
483    else if (RetVT == MVT::f64)
484      return UINTTOFP_I128_F64;
485    else if (RetVT == MVT::f80)
486      return UINTTOFP_I128_F80;
487    else if (RetVT == MVT::ppcf128)
488      return UINTTOFP_I128_PPCF128;
489  }
490  return UNKNOWN_LIBCALL;
491}
492
493/// InitCmpLibcallCCs - Set default comparison libcall CC.
494///
495static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
496  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
497  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
498  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
499  CCs[RTLIB::UNE_F32] = ISD::SETNE;
500  CCs[RTLIB::UNE_F64] = ISD::SETNE;
501  CCs[RTLIB::OGE_F32] = ISD::SETGE;
502  CCs[RTLIB::OGE_F64] = ISD::SETGE;
503  CCs[RTLIB::OLT_F32] = ISD::SETLT;
504  CCs[RTLIB::OLT_F64] = ISD::SETLT;
505  CCs[RTLIB::OLE_F32] = ISD::SETLE;
506  CCs[RTLIB::OLE_F64] = ISD::SETLE;
507  CCs[RTLIB::OGT_F32] = ISD::SETGT;
508  CCs[RTLIB::OGT_F64] = ISD::SETGT;
509  CCs[RTLIB::UO_F32] = ISD::SETNE;
510  CCs[RTLIB::UO_F64] = ISD::SETNE;
511  CCs[RTLIB::O_F32] = ISD::SETEQ;
512  CCs[RTLIB::O_F64] = ISD::SETEQ;
513}
514
515/// NOTE: The constructor takes ownership of TLOF.
516TargetLowering::TargetLowering(const TargetMachine &tm,
517                               const TargetLoweringObjectFile *tlof)
518  : TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) {
519  // All operations default to being supported.
520  memset(OpActions, 0, sizeof(OpActions));
521  memset(LoadExtActions, 0, sizeof(LoadExtActions));
522  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
523  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
524  memset(CondCodeActions, 0, sizeof(CondCodeActions));
525
526  // Set default actions for various operations.
527  for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
528    // Default all indexed load / store to expand.
529    for (unsigned IM = (unsigned)ISD::PRE_INC;
530         IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
531      setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
532      setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
533    }
534
535    // These operations default to expand.
536    setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
537    setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
538  }
539
540  // Most targets ignore the @llvm.prefetch intrinsic.
541  setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
542
543  // ConstantFP nodes default to expand.  Targets can either change this to
544  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
545  // to optimize expansions for certain constants.
546  setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
547  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
548  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
549  setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
550
551  // These library functions default to expand.
552  setOperationAction(ISD::FLOG ,  MVT::f16, Expand);
553  setOperationAction(ISD::FLOG2,  MVT::f16, Expand);
554  setOperationAction(ISD::FLOG10, MVT::f16, Expand);
555  setOperationAction(ISD::FEXP ,  MVT::f16, Expand);
556  setOperationAction(ISD::FEXP2,  MVT::f16, Expand);
557  setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
558  setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
559  setOperationAction(ISD::FCEIL,  MVT::f16, Expand);
560  setOperationAction(ISD::FRINT,  MVT::f16, Expand);
561  setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
562  setOperationAction(ISD::FLOG ,  MVT::f32, Expand);
563  setOperationAction(ISD::FLOG2,  MVT::f32, Expand);
564  setOperationAction(ISD::FLOG10, MVT::f32, Expand);
565  setOperationAction(ISD::FEXP ,  MVT::f32, Expand);
566  setOperationAction(ISD::FEXP2,  MVT::f32, Expand);
567  setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
568  setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
569  setOperationAction(ISD::FCEIL,  MVT::f32, Expand);
570  setOperationAction(ISD::FRINT,  MVT::f32, Expand);
571  setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
572  setOperationAction(ISD::FLOG ,  MVT::f64, Expand);
573  setOperationAction(ISD::FLOG2,  MVT::f64, Expand);
574  setOperationAction(ISD::FLOG10, MVT::f64, Expand);
575  setOperationAction(ISD::FEXP ,  MVT::f64, Expand);
576  setOperationAction(ISD::FEXP2,  MVT::f64, Expand);
577  setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
578  setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
579  setOperationAction(ISD::FCEIL,  MVT::f64, Expand);
580  setOperationAction(ISD::FRINT,  MVT::f64, Expand);
581  setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
582
583  // Default ISD::TRAP to expand (which turns it into abort).
584  setOperationAction(ISD::TRAP, MVT::Other, Expand);
585
586  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
587  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
588  //
589  setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
590
591  IsLittleEndian = TD->isLittleEndian();
592  PointerTy = MVT::getIntegerVT(8*TD->getPointerSize(0));
593  memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
594  memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
595  maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
596  maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
597    = maxStoresPerMemmoveOptSize = 4;
598  benefitFromCodePlacementOpt = false;
599  UseUnderscoreSetJmp = false;
600  UseUnderscoreLongJmp = false;
601  SelectIsExpensive = false;
602  IntDivIsCheap = false;
603  Pow2DivIsCheap = false;
604  JumpIsExpensive = false;
605  predictableSelectIsExpensive = false;
606  StackPointerRegisterToSaveRestore = 0;
607  ExceptionPointerRegister = 0;
608  ExceptionSelectorRegister = 0;
609  BooleanContents = UndefinedBooleanContent;
610  BooleanVectorContents = UndefinedBooleanContent;
611  SchedPreferenceInfo = Sched::ILP;
612  JumpBufSize = 0;
613  JumpBufAlignment = 0;
614  MinFunctionAlignment = 0;
615  PrefFunctionAlignment = 0;
616  PrefLoopAlignment = 0;
617  MinStackArgumentAlignment = 1;
618  ShouldFoldAtomicFences = false;
619  InsertFencesForAtomic = false;
620  SupportJumpTables = true;
621  MinimumJumpTableEntries = 4;
622
623  InitLibcallNames(LibcallRoutineNames);
624  InitCmpLibcallCCs(CmpLibcallCCs);
625  InitLibcallCallingConvs(LibcallCallingConvs);
626}
627
628TargetLowering::~TargetLowering() {
629  delete &TLOF;
630}
631
632MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
633  return MVT::getIntegerVT(8*TD->getPointerSize(0));
634}
635
636/// canOpTrap - Returns true if the operation can trap for the value type.
637/// VT must be a legal type.
638bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
639  assert(isTypeLegal(VT));
640  switch (Op) {
641  default:
642    return false;
643  case ISD::FDIV:
644  case ISD::FREM:
645  case ISD::SDIV:
646  case ISD::UDIV:
647  case ISD::SREM:
648  case ISD::UREM:
649    return true;
650  }
651}
652
653
654static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
655                                          unsigned &NumIntermediates,
656                                          EVT &RegisterVT,
657                                          TargetLowering *TLI) {
658  // Figure out the right, legal destination reg to copy into.
659  unsigned NumElts = VT.getVectorNumElements();
660  MVT EltTy = VT.getVectorElementType();
661
662  unsigned NumVectorRegs = 1;
663
664  // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally we
665  // could break down into LHS/RHS like LegalizeDAG does.
666  if (!isPowerOf2_32(NumElts)) {
667    NumVectorRegs = NumElts;
668    NumElts = 1;
669  }
670
671  // Divide the input until we get to a supported size.  This will always
672  // end with a scalar if the target doesn't support vectors.
673  while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
674    NumElts >>= 1;
675    NumVectorRegs <<= 1;
676  }
677
678  NumIntermediates = NumVectorRegs;
679
680  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
681  if (!TLI->isTypeLegal(NewVT))
682    NewVT = EltTy;
683  IntermediateVT = NewVT;
684
685  unsigned NewVTSize = NewVT.getSizeInBits();
686
687  // Convert sizes such as i33 to i64.
688  if (!isPowerOf2_32(NewVTSize))
689    NewVTSize = NextPowerOf2(NewVTSize);
690
691  EVT DestVT = TLI->getRegisterType(NewVT);
692  RegisterVT = DestVT;
693  if (EVT(DestVT).bitsLT(NewVT))    // Value is expanded, e.g. i64 -> i16.
694    return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
695
696  // Otherwise, promotion or legal types use the same number of registers as
697  // the vector decimated to the appropriate level.
698  return NumVectorRegs;
699}
700
701/// isLegalRC - Return true if the value types that can be represented by the
702/// specified register class are all legal.
703bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
704  for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
705       I != E; ++I) {
706    if (isTypeLegal(*I))
707      return true;
708  }
709  return false;
710}
711
712/// findRepresentativeClass - Return the largest legal super-reg register class
713/// of the register class for the specified type and its associated "cost".
714std::pair<const TargetRegisterClass*, uint8_t>
715TargetLowering::findRepresentativeClass(EVT VT) const {
716  const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
717  const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
718  if (!RC)
719    return std::make_pair(RC, 0);
720
721  // Compute the set of all super-register classes.
722  BitVector SuperRegRC(TRI->getNumRegClasses());
723  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
724    SuperRegRC.setBitsInMask(RCI.getMask());
725
726  // Find the first legal register class with the largest spill size.
727  const TargetRegisterClass *BestRC = RC;
728  for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
729    const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
730    // We want the largest possible spill size.
731    if (SuperRC->getSize() <= BestRC->getSize())
732      continue;
733    if (!isLegalRC(SuperRC))
734      continue;
735    BestRC = SuperRC;
736  }
737  return std::make_pair(BestRC, 1);
738}
739
740/// computeRegisterProperties - Once all of the register classes are added,
741/// this allows us to compute derived properties we expose.
742void TargetLowering::computeRegisterProperties() {
743  assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
744         "Too many value types for ValueTypeActions to hold!");
745
746  // Everything defaults to needing one register.
747  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
748    NumRegistersForVT[i] = 1;
749    RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
750  }
751  // ...except isVoid, which doesn't need any registers.
752  NumRegistersForVT[MVT::isVoid] = 0;
753
754  // Find the largest integer register class.
755  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
756  for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
757    assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
758
759  // Every integer value type larger than this largest register takes twice as
760  // many registers to represent as the previous ValueType.
761  for (unsigned ExpandedReg = LargestIntReg + 1;
762       ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
763    NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
764    RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
765    TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
766    ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
767                                   TypeExpandInteger);
768  }
769
770  // Inspect all of the ValueType's smaller than the largest integer
771  // register to see which ones need promotion.
772  unsigned LegalIntReg = LargestIntReg;
773  for (unsigned IntReg = LargestIntReg - 1;
774       IntReg >= (unsigned)MVT::i1; --IntReg) {
775    EVT IVT = (MVT::SimpleValueType)IntReg;
776    if (isTypeLegal(IVT)) {
777      LegalIntReg = IntReg;
778    } else {
779      RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
780        (const MVT::SimpleValueType)LegalIntReg;
781      ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
782    }
783  }
784
785  // ppcf128 type is really two f64's.
786  if (!isTypeLegal(MVT::ppcf128)) {
787    NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
788    RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
789    TransformToType[MVT::ppcf128] = MVT::f64;
790    ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
791  }
792
793  // Decide how to handle f64. If the target does not have native f64 support,
794  // expand it to i64 and we will be generating soft float library calls.
795  if (!isTypeLegal(MVT::f64)) {
796    NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
797    RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
798    TransformToType[MVT::f64] = MVT::i64;
799    ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
800  }
801
802  // Decide how to handle f32. If the target does not have native support for
803  // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
804  if (!isTypeLegal(MVT::f32)) {
805    if (isTypeLegal(MVT::f64)) {
806      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
807      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
808      TransformToType[MVT::f32] = MVT::f64;
809      ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
810    } else {
811      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
812      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
813      TransformToType[MVT::f32] = MVT::i32;
814      ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
815    }
816  }
817
818  // Loop over all of the vector value types to see which need transformations.
819  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
820       i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
821    MVT VT = (MVT::SimpleValueType)i;
822    if (isTypeLegal(VT)) continue;
823
824    // Determine if there is a legal wider type.  If so, we should promote to
825    // that wider vector type.
826    EVT EltVT = VT.getVectorElementType();
827    unsigned NElts = VT.getVectorNumElements();
828    if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) {
829      bool IsLegalWiderType = false;
830      // First try to promote the elements of integer vectors. If no legal
831      // promotion was found, fallback to the widen-vector method.
832      for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
833        EVT SVT = (MVT::SimpleValueType)nVT;
834        // Promote vectors of integers to vectors with the same number
835        // of elements, with a wider element type.
836        if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
837            && SVT.getVectorNumElements() == NElts &&
838            isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
839          TransformToType[i] = SVT;
840          RegisterTypeForVT[i] = SVT;
841          NumRegistersForVT[i] = 1;
842          ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
843          IsLegalWiderType = true;
844          break;
845        }
846      }
847
848      if (IsLegalWiderType) continue;
849
850      // Try to widen the vector.
851      for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
852        EVT SVT = (MVT::SimpleValueType)nVT;
853        if (SVT.getVectorElementType() == EltVT &&
854            SVT.getVectorNumElements() > NElts &&
855            isTypeLegal(SVT)) {
856          TransformToType[i] = SVT;
857          RegisterTypeForVT[i] = SVT;
858          NumRegistersForVT[i] = 1;
859          ValueTypeActions.setTypeAction(VT, TypeWidenVector);
860          IsLegalWiderType = true;
861          break;
862        }
863      }
864      if (IsLegalWiderType) continue;
865    }
866
867    MVT IntermediateVT;
868    EVT RegisterVT;
869    unsigned NumIntermediates;
870    NumRegistersForVT[i] =
871      getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
872                                RegisterVT, this);
873    RegisterTypeForVT[i] = RegisterVT;
874
875    EVT NVT = VT.getPow2VectorType();
876    if (NVT == VT) {
877      // Type is already a power of 2.  The default action is to split.
878      TransformToType[i] = MVT::Other;
879      unsigned NumElts = VT.getVectorNumElements();
880      ValueTypeActions.setTypeAction(VT,
881            NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
882    } else {
883      TransformToType[i] = NVT;
884      ValueTypeActions.setTypeAction(VT, TypeWidenVector);
885    }
886  }
887
888  // Determine the 'representative' register class for each value type.
889  // An representative register class is the largest (meaning one which is
890  // not a sub-register class / subreg register class) legal register class for
891  // a group of value types. For example, on i386, i8, i16, and i32
892  // representative would be GR32; while on x86_64 it's GR64.
893  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
894    const TargetRegisterClass* RRC;
895    uint8_t Cost;
896    tie(RRC, Cost) =  findRepresentativeClass((MVT::SimpleValueType)i);
897    RepRegClassForVT[i] = RRC;
898    RepRegClassCostForVT[i] = Cost;
899  }
900}
901
902const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
903  return NULL;
904}
905
906EVT TargetLowering::getSetCCResultType(EVT VT) const {
907  assert(!VT.isVector() && "No default SetCC type for vectors!");
908  return getPointerTy(0).SimpleTy;
909}
910
911MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
912  return MVT::i32; // return the default value
913}
914
915/// getVectorTypeBreakdown - Vector types are broken down into some number of
916/// legal first class types.  For example, MVT::v8f32 maps to 2 MVT::v4f32
917/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
918/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
919///
920/// This method returns the number of registers needed, and the VT for each
921/// register.  It also returns the VT and quantity of the intermediate values
922/// before they are promoted/expanded.
923///
924unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
925                                                EVT &IntermediateVT,
926                                                unsigned &NumIntermediates,
927                                                EVT &RegisterVT) const {
928  unsigned NumElts = VT.getVectorNumElements();
929
930  // If there is a wider vector type with the same element type as this one,
931  // or a promoted vector type that has the same number of elements which
932  // are wider, then we should convert to that legal vector type.
933  // This handles things like <2 x float> -> <4 x float> and
934  // <4 x i1> -> <4 x i32>.
935  LegalizeTypeAction TA = getTypeAction(Context, VT);
936  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
937    RegisterVT = getTypeToTransformTo(Context, VT);
938    if (isTypeLegal(RegisterVT)) {
939      IntermediateVT = RegisterVT;
940      NumIntermediates = 1;
941      return 1;
942    }
943  }
944
945  // Figure out the right, legal destination reg to copy into.
946  EVT EltTy = VT.getVectorElementType();
947
948  unsigned NumVectorRegs = 1;
949
950  // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally we
951  // could break down into LHS/RHS like LegalizeDAG does.
952  if (!isPowerOf2_32(NumElts)) {
953    NumVectorRegs = NumElts;
954    NumElts = 1;
955  }
956
957  // Divide the input until we get to a supported size.  This will always
958  // end with a scalar if the target doesn't support vectors.
959  while (NumElts > 1 && !isTypeLegal(
960                                   EVT::getVectorVT(Context, EltTy, NumElts))) {
961    NumElts >>= 1;
962    NumVectorRegs <<= 1;
963  }
964
965  NumIntermediates = NumVectorRegs;
966
967  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
968  if (!isTypeLegal(NewVT))
969    NewVT = EltTy;
970  IntermediateVT = NewVT;
971
972  EVT DestVT = getRegisterType(Context, NewVT);
973  RegisterVT = DestVT;
974  unsigned NewVTSize = NewVT.getSizeInBits();
975
976  // Convert sizes such as i33 to i64.
977  if (!isPowerOf2_32(NewVTSize))
978    NewVTSize = NextPowerOf2(NewVTSize);
979
980  if (DestVT.bitsLT(NewVT))   // Value is expanded, e.g. i64 -> i16.
981    return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
982
983  // Otherwise, promotion or legal types use the same number of registers as
984  // the vector decimated to the appropriate level.
985  return NumVectorRegs;
986}
987
988/// Get the EVTs and ArgFlags collections that represent the legalized return
989/// type of the given function.  This does not require a DAG or a return value,
990/// and is suitable for use before any DAGs for the function are constructed.
991/// TODO: Move this out of TargetLowering.cpp.
992void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
993                         SmallVectorImpl<ISD::OutputArg> &Outs,
994                         const TargetLowering &TLI) {
995  SmallVector<EVT, 4> ValueVTs;
996  ComputeValueVTs(TLI, ReturnType, ValueVTs);
997  unsigned NumValues = ValueVTs.size();
998  if (NumValues == 0) return;
999
1000  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1001    EVT VT = ValueVTs[j];
1002    ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1003
1004    if (attr.hasAttribute(Attributes::SExt))
1005      ExtendKind = ISD::SIGN_EXTEND;
1006    else if (attr.hasAttribute(Attributes::ZExt))
1007      ExtendKind = ISD::ZERO_EXTEND;
1008
1009    // FIXME: C calling convention requires the return type to be promoted to
1010    // at least 32-bit. But this is not necessary for non-C calling
1011    // conventions. The frontend should mark functions whose return values
1012    // require promoting with signext or zeroext attributes.
1013    if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1014      EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1015      if (VT.bitsLT(MinVT))
1016        VT = MinVT;
1017    }
1018
1019    unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1020    EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1021
1022    // 'inreg' on function refers to return value
1023    ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1024    if (attr.hasAttribute(Attributes::InReg))
1025      Flags.setInReg();
1026
1027    // Propagate extension type if any
1028    if (attr.hasAttribute(Attributes::SExt))
1029      Flags.setSExt();
1030    else if (attr.hasAttribute(Attributes::ZExt))
1031      Flags.setZExt();
1032
1033    for (unsigned i = 0; i < NumParts; ++i)
1034      Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true, 0, 0));
1035  }
1036}
1037
1038/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1039/// function arguments in the caller parameter area.  This is the actual
1040/// alignment, not its logarithm.
1041unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
1042  return TD->getCallFrameTypeAlignment(Ty);
1043}
1044
1045/// getJumpTableEncoding - Return the entry encoding for a jump table in the
1046/// current function.  The returned value is a member of the
1047/// MachineJumpTableInfo::JTEntryKind enum.
1048unsigned TargetLowering::getJumpTableEncoding() const {
1049  // In non-pic modes, just use the address of a block.
1050  if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1051    return MachineJumpTableInfo::EK_BlockAddress;
1052
1053  // In PIC mode, if the target supports a GPRel32 directive, use it.
1054  if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1055    return MachineJumpTableInfo::EK_GPRel32BlockAddress;
1056
1057  // Otherwise, use a label difference.
1058  return MachineJumpTableInfo::EK_LabelDifference32;
1059}
1060
1061SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1062                                                 SelectionDAG &DAG) const {
1063  // If our PIC model is GP relative, use the global offset table as the base.
1064  unsigned JTEncoding = getJumpTableEncoding();
1065
1066  if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
1067      (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
1068    return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
1069
1070  return Table;
1071}
1072
1073/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1074/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1075/// MCExpr.
1076const MCExpr *
1077TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1078                                             unsigned JTI,MCContext &Ctx) const{
1079  // The normal PIC reloc base is the label at the start of the jump table.
1080  return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
1081}
1082
1083bool
1084TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1085  // Assume that everything is safe in static mode.
1086  if (getTargetMachine().getRelocationModel() == Reloc::Static)
1087    return true;
1088
1089  // In dynamic-no-pic mode, assume that known defined values are safe.
1090  if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1091      GA &&
1092      !GA->getGlobal()->isDeclaration() &&
1093      !GA->getGlobal()->isWeakForLinker())
1094    return true;
1095
1096  // Otherwise assume nothing is safe.
1097  return false;
1098}
1099
1100//===----------------------------------------------------------------------===//
1101//  Optimization Methods
1102//===----------------------------------------------------------------------===//
1103
1104/// ShrinkDemandedConstant - Check to see if the specified operand of the
1105/// specified instruction is a constant integer.  If so, check to see if there
1106/// are any bits set in the constant that are not demanded.  If so, shrink the
1107/// constant and return true.
1108bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
1109                                                        const APInt &Demanded) {
1110  DebugLoc dl = Op.getDebugLoc();
1111
1112  // FIXME: ISD::SELECT, ISD::SELECT_CC
1113  switch (Op.getOpcode()) {
1114  default: break;
1115  case ISD::XOR:
1116  case ISD::AND:
1117  case ISD::OR: {
1118    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1119    if (!C) return false;
1120
1121    if (Op.getOpcode() == ISD::XOR &&
1122        (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1123      return false;
1124
1125    // if we can expand it to have all bits set, do it
1126    if (C->getAPIntValue().intersects(~Demanded)) {
1127      EVT VT = Op.getValueType();
1128      SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1129                                DAG.getConstant(Demanded &
1130                                                C->getAPIntValue(),
1131                                                VT));
1132      return CombineTo(Op, New);
1133    }
1134
1135    break;
1136  }
1137  }
1138
1139  return false;
1140}
1141
1142/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1143/// casts are free.  This uses isZExtFree and ZERO_EXTEND for the widening
1144/// cast, but it could be generalized for targets with other types of
1145/// implicit widening casts.
1146bool
1147TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1148                                                    unsigned BitWidth,
1149                                                    const APInt &Demanded,
1150                                                    DebugLoc dl) {
1151  assert(Op.getNumOperands() == 2 &&
1152         "ShrinkDemandedOp only supports binary operators!");
1153  assert(Op.getNode()->getNumValues() == 1 &&
1154         "ShrinkDemandedOp only supports nodes with one result!");
1155
1156  // Don't do this if the node has another user, which may require the
1157  // full value.
1158  if (!Op.getNode()->hasOneUse())
1159    return false;
1160
1161  // Search for the smallest integer type with free casts to and from
1162  // Op's type. For expedience, just check power-of-2 integer types.
1163  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1164  unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1165  if (!isPowerOf2_32(SmallVTBits))
1166    SmallVTBits = NextPowerOf2(SmallVTBits);
1167  for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
1168    EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
1169    if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1170        TLI.isZExtFree(SmallVT, Op.getValueType())) {
1171      // We found a type with free casts.
1172      SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1173                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1174                                          Op.getNode()->getOperand(0)),
1175                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1176                                          Op.getNode()->getOperand(1)));
1177      SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1178      return CombineTo(Op, Z);
1179    }
1180  }
1181  return false;
1182}
1183
1184/// SimplifyDemandedBits - Look at Op.  At this point, we know that only the
1185/// DemandedMask bits of the result of Op are ever used downstream.  If we can
1186/// use this information to simplify Op, create a new simplified DAG node and
1187/// return true, returning the original and new nodes in Old and New. Otherwise,
1188/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1189/// the expression (used to simplify the caller).  The KnownZero/One bits may
1190/// only be accurate for those bits in the DemandedMask.
1191bool TargetLowering::SimplifyDemandedBits(SDValue Op,
1192                                          const APInt &DemandedMask,
1193                                          APInt &KnownZero,
1194                                          APInt &KnownOne,
1195                                          TargetLoweringOpt &TLO,
1196                                          unsigned Depth) const {
1197  unsigned BitWidth = DemandedMask.getBitWidth();
1198  assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
1199         "Mask size mismatches value type size!");
1200  APInt NewMask = DemandedMask;
1201  DebugLoc dl = Op.getDebugLoc();
1202
1203  // Don't know anything.
1204  KnownZero = KnownOne = APInt(BitWidth, 0);
1205
1206  // Other users may use these bits.
1207  if (!Op.getNode()->hasOneUse()) {
1208    if (Depth != 0) {
1209      // If not at the root, Just compute the KnownZero/KnownOne bits to
1210      // simplify things downstream.
1211      TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1212      return false;
1213    }
1214    // If this is the root being simplified, allow it to have multiple uses,
1215    // just set the NewMask to all bits.
1216    NewMask = APInt::getAllOnesValue(BitWidth);
1217  } else if (DemandedMask == 0) {
1218    // Not demanding any bits from Op.
1219    if (Op.getOpcode() != ISD::UNDEF)
1220      return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
1221    return false;
1222  } else if (Depth == 6) {        // Limit search depth.
1223    return false;
1224  }
1225
1226  APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1227  switch (Op.getOpcode()) {
1228  case ISD::Constant:
1229    // We know all of the bits for a constant!
1230    KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
1231    KnownZero = ~KnownOne;
1232    return false;   // Don't fall through, will infinitely loop.
1233  case ISD::AND:
1234    // If the RHS is a constant, check to see if the LHS would be zero without
1235    // using the bits from the RHS.  Below, we use knowledge about the RHS to
1236    // simplify the LHS, here we're using information from the LHS to simplify
1237    // the RHS.
1238    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1239      APInt LHSZero, LHSOne;
1240      // Do not increment Depth here; that can cause an infinite loop.
1241      TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
1242      // If the LHS already has zeros where RHSC does, this and is dead.
1243      if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1244        return TLO.CombineTo(Op, Op.getOperand(0));
1245      // If any of the set bits in the RHS are known zero on the LHS, shrink
1246      // the constant.
1247      if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1248        return true;
1249    }
1250
1251    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1252                             KnownOne, TLO, Depth+1))
1253      return true;
1254    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1255    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1256                             KnownZero2, KnownOne2, TLO, Depth+1))
1257      return true;
1258    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1259
1260    // If all of the demanded bits are known one on one side, return the other.
1261    // These bits cannot contribute to the result of the 'and'.
1262    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1263      return TLO.CombineTo(Op, Op.getOperand(0));
1264    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1265      return TLO.CombineTo(Op, Op.getOperand(1));
1266    // If all of the demanded bits in the inputs are known zeros, return zero.
1267    if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1268      return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1269    // If the RHS is a constant, see if we can simplify it.
1270    if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1271      return true;
1272    // If the operation can be done in a smaller type, do so.
1273    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1274      return true;
1275
1276    // Output known-1 bits are only known if set in both the LHS & RHS.
1277    KnownOne &= KnownOne2;
1278    // Output known-0 are known to be clear if zero in either the LHS | RHS.
1279    KnownZero |= KnownZero2;
1280    break;
1281  case ISD::OR:
1282    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1283                             KnownOne, TLO, Depth+1))
1284      return true;
1285    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1286    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1287                             KnownZero2, KnownOne2, TLO, Depth+1))
1288      return true;
1289    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1290
1291    // If all of the demanded bits are known zero on one side, return the other.
1292    // These bits cannot contribute to the result of the 'or'.
1293    if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1294      return TLO.CombineTo(Op, Op.getOperand(0));
1295    if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1296      return TLO.CombineTo(Op, Op.getOperand(1));
1297    // If all of the potentially set bits on one side are known to be set on
1298    // the other side, just use the 'other' side.
1299    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1300      return TLO.CombineTo(Op, Op.getOperand(0));
1301    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1302      return TLO.CombineTo(Op, Op.getOperand(1));
1303    // If the RHS is a constant, see if we can simplify it.
1304    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1305      return true;
1306    // If the operation can be done in a smaller type, do so.
1307    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1308      return true;
1309
1310    // Output known-0 bits are only known if clear in both the LHS & RHS.
1311    KnownZero &= KnownZero2;
1312    // Output known-1 are known to be set if set in either the LHS | RHS.
1313    KnownOne |= KnownOne2;
1314    break;
1315  case ISD::XOR:
1316    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1317                             KnownOne, TLO, Depth+1))
1318      return true;
1319    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1320    if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1321                             KnownOne2, TLO, Depth+1))
1322      return true;
1323    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1324
1325    // If all of the demanded bits are known zero on one side, return the other.
1326    // These bits cannot contribute to the result of the 'xor'.
1327    if ((KnownZero & NewMask) == NewMask)
1328      return TLO.CombineTo(Op, Op.getOperand(0));
1329    if ((KnownZero2 & NewMask) == NewMask)
1330      return TLO.CombineTo(Op, Op.getOperand(1));
1331    // If the operation can be done in a smaller type, do so.
1332    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1333      return true;
1334
1335    // If all of the unknown bits are known to be zero on one side or the other
1336    // (but not both) turn this into an *inclusive* or.
1337    //    e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1338    if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1339      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1340                                               Op.getOperand(0),
1341                                               Op.getOperand(1)));
1342
1343    // Output known-0 bits are known if clear or set in both the LHS & RHS.
1344    KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1345    // Output known-1 are known to be set if set in only one of the LHS, RHS.
1346    KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1347
1348    // If all of the demanded bits on one side are known, and all of the set
1349    // bits on that side are also known to be set on the other side, turn this
1350    // into an AND, as we know the bits will be cleared.
1351    //    e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1352    // NB: it is okay if more bits are known than are requested
1353    if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
1354      if (KnownOne == KnownOne2) { // set bits are the same on both sides
1355        EVT VT = Op.getValueType();
1356        SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1357        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1358                                                 Op.getOperand(0), ANDC));
1359      }
1360    }
1361
1362    // If the RHS is a constant, see if we can simplify it.
1363    // for XOR, we prefer to force bits to 1 if they will make a -1.
1364    // if we can't force bits, try to shrink constant
1365    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1366      APInt Expanded = C->getAPIntValue() | (~NewMask);
1367      // if we can expand it to have all bits set, do it
1368      if (Expanded.isAllOnesValue()) {
1369        if (Expanded != C->getAPIntValue()) {
1370          EVT VT = Op.getValueType();
1371          SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1372                                          TLO.DAG.getConstant(Expanded, VT));
1373          return TLO.CombineTo(Op, New);
1374        }
1375        // if it already has all the bits set, nothing to change
1376        // but don't shrink either!
1377      } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1378        return true;
1379      }
1380    }
1381
1382    KnownZero = KnownZeroOut;
1383    KnownOne  = KnownOneOut;
1384    break;
1385  case ISD::SELECT:
1386    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1387                             KnownOne, TLO, Depth+1))
1388      return true;
1389    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1390                             KnownOne2, TLO, Depth+1))
1391      return true;
1392    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1393    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1394
1395    // If the operands are constants, see if we can simplify them.
1396    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1397      return true;
1398
1399    // Only known if known in both the LHS and RHS.
1400    KnownOne &= KnownOne2;
1401    KnownZero &= KnownZero2;
1402    break;
1403  case ISD::SELECT_CC:
1404    if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1405                             KnownOne, TLO, Depth+1))
1406      return true;
1407    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1408                             KnownOne2, TLO, Depth+1))
1409      return true;
1410    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1411    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1412
1413    // If the operands are constants, see if we can simplify them.
1414    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1415      return true;
1416
1417    // Only known if known in both the LHS and RHS.
1418    KnownOne &= KnownOne2;
1419    KnownZero &= KnownZero2;
1420    break;
1421  case ISD::SHL:
1422    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1423      unsigned ShAmt = SA->getZExtValue();
1424      SDValue InOp = Op.getOperand(0);
1425
1426      // If the shift count is an invalid immediate, don't do anything.
1427      if (ShAmt >= BitWidth)
1428        break;
1429
1430      // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1431      // single shift.  We can do this if the bottom bits (which are shifted
1432      // out) are never demanded.
1433      if (InOp.getOpcode() == ISD::SRL &&
1434          isa<ConstantSDNode>(InOp.getOperand(1))) {
1435        if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1436          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1437          unsigned Opc = ISD::SHL;
1438          int Diff = ShAmt-C1;
1439          if (Diff < 0) {
1440            Diff = -Diff;
1441            Opc = ISD::SRL;
1442          }
1443
1444          SDValue NewSA =
1445            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1446          EVT VT = Op.getValueType();
1447          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1448                                                   InOp.getOperand(0), NewSA));
1449        }
1450      }
1451
1452      if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
1453                               KnownZero, KnownOne, TLO, Depth+1))
1454        return true;
1455
1456      // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1457      // are not demanded. This will likely allow the anyext to be folded away.
1458      if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1459        SDValue InnerOp = InOp.getNode()->getOperand(0);
1460        EVT InnerVT = InnerOp.getValueType();
1461        unsigned InnerBits = InnerVT.getSizeInBits();
1462        if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
1463            isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1464          EVT ShTy = getShiftAmountTy(InnerVT);
1465          if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1466            ShTy = InnerVT;
1467          SDValue NarrowShl =
1468            TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1469                            TLO.DAG.getConstant(ShAmt, ShTy));
1470          return
1471            TLO.CombineTo(Op,
1472                          TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1473                                          NarrowShl));
1474        }
1475      }
1476
1477      KnownZero <<= SA->getZExtValue();
1478      KnownOne  <<= SA->getZExtValue();
1479      // low bits known zero.
1480      KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1481    }
1482    break;
1483  case ISD::SRL:
1484    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1485      EVT VT = Op.getValueType();
1486      unsigned ShAmt = SA->getZExtValue();
1487      unsigned VTSize = VT.getSizeInBits();
1488      SDValue InOp = Op.getOperand(0);
1489
1490      // If the shift count is an invalid immediate, don't do anything.
1491      if (ShAmt >= BitWidth)
1492        break;
1493
1494      // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1495      // single shift.  We can do this if the top bits (which are shifted out)
1496      // are never demanded.
1497      if (InOp.getOpcode() == ISD::SHL &&
1498          isa<ConstantSDNode>(InOp.getOperand(1))) {
1499        if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1500          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1501          unsigned Opc = ISD::SRL;
1502          int Diff = ShAmt-C1;
1503          if (Diff < 0) {
1504            Diff = -Diff;
1505            Opc = ISD::SHL;
1506          }
1507
1508          SDValue NewSA =
1509            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1510          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1511                                                   InOp.getOperand(0), NewSA));
1512        }
1513      }
1514
1515      // Compute the new bits that are at the top now.
1516      if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1517                               KnownZero, KnownOne, TLO, Depth+1))
1518        return true;
1519      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1520      KnownZero = KnownZero.lshr(ShAmt);
1521      KnownOne  = KnownOne.lshr(ShAmt);
1522
1523      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1524      KnownZero |= HighBits;  // High bits known zero.
1525    }
1526    break;
1527  case ISD::SRA:
1528    // If this is an arithmetic shift right and only the low-bit is set, we can
1529    // always convert this into a logical shr, even if the shift amount is
1530    // variable.  The low bit of the shift cannot be an input sign bit unless
1531    // the shift amount is >= the size of the datatype, which is undefined.
1532    if (NewMask == 1)
1533      return TLO.CombineTo(Op,
1534                           TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1535                                           Op.getOperand(0), Op.getOperand(1)));
1536
1537    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1538      EVT VT = Op.getValueType();
1539      unsigned ShAmt = SA->getZExtValue();
1540
1541      // If the shift count is an invalid immediate, don't do anything.
1542      if (ShAmt >= BitWidth)
1543        break;
1544
1545      APInt InDemandedMask = (NewMask << ShAmt);
1546
1547      // If any of the demanded bits are produced by the sign extension, we also
1548      // demand the input sign bit.
1549      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1550      if (HighBits.intersects(NewMask))
1551        InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1552
1553      if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1554                               KnownZero, KnownOne, TLO, Depth+1))
1555        return true;
1556      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1557      KnownZero = KnownZero.lshr(ShAmt);
1558      KnownOne  = KnownOne.lshr(ShAmt);
1559
1560      // Handle the sign bit, adjusted to where it is now in the mask.
1561      APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1562
1563      // If the input sign bit is known to be zero, or if none of the top bits
1564      // are demanded, turn this into an unsigned shift right.
1565      if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1566        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1567                                                 Op.getOperand(0),
1568                                                 Op.getOperand(1)));
1569      } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1570        KnownOne |= HighBits;
1571      }
1572    }
1573    break;
1574  case ISD::SIGN_EXTEND_INREG: {
1575    EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1576
1577    APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
1578    // If we only care about the highest bit, don't bother shifting right.
1579    if (MsbMask == DemandedMask) {
1580      unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
1581      SDValue InOp = Op.getOperand(0);
1582
1583      // Compute the correct shift amount type, which must be getShiftAmountTy
1584      // for scalar types after legalization.
1585      EVT ShiftAmtTy = Op.getValueType();
1586      if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1587        ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
1588
1589      SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
1590      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1591                                            Op.getValueType(), InOp, ShiftAmt));
1592    }
1593
1594    // Sign extension.  Compute the demanded bits in the result that are not
1595    // present in the input.
1596    APInt NewBits =
1597      APInt::getHighBitsSet(BitWidth,
1598                            BitWidth - ExVT.getScalarType().getSizeInBits());
1599
1600    // If none of the extended bits are demanded, eliminate the sextinreg.
1601    if ((NewBits & NewMask) == 0)
1602      return TLO.CombineTo(Op, Op.getOperand(0));
1603
1604    APInt InSignBit =
1605      APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
1606    APInt InputDemandedBits =
1607      APInt::getLowBitsSet(BitWidth,
1608                           ExVT.getScalarType().getSizeInBits()) &
1609      NewMask;
1610
1611    // Since the sign extended bits are demanded, we know that the sign
1612    // bit is demanded.
1613    InputDemandedBits |= InSignBit;
1614
1615    if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1616                             KnownZero, KnownOne, TLO, Depth+1))
1617      return true;
1618    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1619
1620    // If the sign bit of the input is known set or clear, then we know the
1621    // top bits of the result.
1622
1623    // If the input sign bit is known zero, convert this into a zero extension.
1624    if (KnownZero.intersects(InSignBit))
1625      return TLO.CombineTo(Op,
1626                          TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
1627
1628    if (KnownOne.intersects(InSignBit)) {    // Input sign bit known set
1629      KnownOne |= NewBits;
1630      KnownZero &= ~NewBits;
1631    } else {                       // Input sign bit unknown
1632      KnownZero &= ~NewBits;
1633      KnownOne &= ~NewBits;
1634    }
1635    break;
1636  }
1637  case ISD::ZERO_EXTEND: {
1638    unsigned OperandBitWidth =
1639      Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1640    APInt InMask = NewMask.trunc(OperandBitWidth);
1641
1642    // If none of the top bits are demanded, convert this into an any_extend.
1643    APInt NewBits =
1644      APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1645    if (!NewBits.intersects(NewMask))
1646      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1647                                               Op.getValueType(),
1648                                               Op.getOperand(0)));
1649
1650    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1651                             KnownZero, KnownOne, TLO, Depth+1))
1652      return true;
1653    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1654    KnownZero = KnownZero.zext(BitWidth);
1655    KnownOne = KnownOne.zext(BitWidth);
1656    KnownZero |= NewBits;
1657    break;
1658  }
1659  case ISD::SIGN_EXTEND: {
1660    EVT InVT = Op.getOperand(0).getValueType();
1661    unsigned InBits = InVT.getScalarType().getSizeInBits();
1662    APInt InMask    = APInt::getLowBitsSet(BitWidth, InBits);
1663    APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1664    APInt NewBits   = ~InMask & NewMask;
1665
1666    // If none of the top bits are demanded, convert this into an any_extend.
1667    if (NewBits == 0)
1668      return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1669                                              Op.getValueType(),
1670                                              Op.getOperand(0)));
1671
1672    // Since some of the sign extended bits are demanded, we know that the sign
1673    // bit is demanded.
1674    APInt InDemandedBits = InMask & NewMask;
1675    InDemandedBits |= InSignBit;
1676    InDemandedBits = InDemandedBits.trunc(InBits);
1677
1678    if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1679                             KnownOne, TLO, Depth+1))
1680      return true;
1681    KnownZero = KnownZero.zext(BitWidth);
1682    KnownOne = KnownOne.zext(BitWidth);
1683
1684    // If the sign bit is known zero, convert this to a zero extend.
1685    if (KnownZero.intersects(InSignBit))
1686      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1687                                               Op.getValueType(),
1688                                               Op.getOperand(0)));
1689
1690    // If the sign bit is known one, the top bits match.
1691    if (KnownOne.intersects(InSignBit)) {
1692      KnownOne |= NewBits;
1693      assert((KnownZero & NewBits) == 0);
1694    } else {   // Otherwise, top bits aren't known.
1695      assert((KnownOne & NewBits) == 0);
1696      assert((KnownZero & NewBits) == 0);
1697    }
1698    break;
1699  }
1700  case ISD::ANY_EXTEND: {
1701    unsigned OperandBitWidth =
1702      Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1703    APInt InMask = NewMask.trunc(OperandBitWidth);
1704    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1705                             KnownZero, KnownOne, TLO, Depth+1))
1706      return true;
1707    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1708    KnownZero = KnownZero.zext(BitWidth);
1709    KnownOne = KnownOne.zext(BitWidth);
1710    break;
1711  }
1712  case ISD::TRUNCATE: {
1713    // Simplify the input, using demanded bit information, and compute the known
1714    // zero/one bits live out.
1715    unsigned OperandBitWidth =
1716      Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1717    APInt TruncMask = NewMask.zext(OperandBitWidth);
1718    if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1719                             KnownZero, KnownOne, TLO, Depth+1))
1720      return true;
1721    KnownZero = KnownZero.trunc(BitWidth);
1722    KnownOne = KnownOne.trunc(BitWidth);
1723
1724    // If the input is only used by this truncate, see if we can shrink it based
1725    // on the known demanded bits.
1726    if (Op.getOperand(0).getNode()->hasOneUse()) {
1727      SDValue In = Op.getOperand(0);
1728      switch (In.getOpcode()) {
1729      default: break;
1730      case ISD::SRL:
1731        // Shrink SRL by a constant if none of the high bits shifted in are
1732        // demanded.
1733        if (TLO.LegalTypes() &&
1734            !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1735          // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1736          // undesirable.
1737          break;
1738        ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1739        if (!ShAmt)
1740          break;
1741        SDValue Shift = In.getOperand(1);
1742        if (TLO.LegalTypes()) {
1743          uint64_t ShVal = ShAmt->getZExtValue();
1744          Shift =
1745            TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1746        }
1747
1748        APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1749                                               OperandBitWidth - BitWidth);
1750        HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1751
1752        if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1753          // None of the shifted in bits are needed.  Add a truncate of the
1754          // shift input, then shift it.
1755          SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1756                                             Op.getValueType(),
1757                                             In.getOperand(0));
1758          return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1759                                                   Op.getValueType(),
1760                                                   NewTrunc,
1761                                                   Shift));
1762        }
1763        break;
1764      }
1765    }
1766
1767    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1768    break;
1769  }
1770  case ISD::AssertZext: {
1771    // AssertZext demands all of the high bits, plus any of the low bits
1772    // demanded by its users.
1773    EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1774    APInt InMask = APInt::getLowBitsSet(BitWidth,
1775                                        VT.getSizeInBits());
1776    if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1777                             KnownZero, KnownOne, TLO, Depth+1))
1778      return true;
1779    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1780
1781    KnownZero |= ~InMask & NewMask;
1782    break;
1783  }
1784  case ISD::BITCAST:
1785    // If this is an FP->Int bitcast and if the sign bit is the only
1786    // thing demanded, turn this into a FGETSIGN.
1787    if (!TLO.LegalOperations() &&
1788        !Op.getValueType().isVector() &&
1789        !Op.getOperand(0).getValueType().isVector() &&
1790        NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1791        Op.getOperand(0).getValueType().isFloatingPoint()) {
1792      bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1793      bool i32Legal  = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1794      if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1795        EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1796        // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1797        // place.  We expect the SHL to be eliminated by other optimizations.
1798        SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1799        unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1800        if (!OpVTLegal && OpVTSizeInBits > 32)
1801          Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1802        unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1803        SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1804        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1805                                                 Op.getValueType(),
1806                                                 Sign, ShAmt));
1807      }
1808    }
1809    break;
1810  case ISD::ADD:
1811  case ISD::MUL:
1812  case ISD::SUB: {
1813    // Add, Sub, and Mul don't demand any bits in positions beyond that
1814    // of the highest bit demanded of them.
1815    APInt LoMask = APInt::getLowBitsSet(BitWidth,
1816                                        BitWidth - NewMask.countLeadingZeros());
1817    if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1818                             KnownOne2, TLO, Depth+1))
1819      return true;
1820    if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1821                             KnownOne2, TLO, Depth+1))
1822      return true;
1823    // See if the operation should be performed at a smaller bit width.
1824    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1825      return true;
1826  }
1827  // FALL THROUGH
1828  default:
1829    // Just use ComputeMaskedBits to compute output bits.
1830    TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1831    break;
1832  }
1833
1834  // If we know the value of all of the demanded bits, return this as a
1835  // constant.
1836  if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1837    return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1838
1839  return false;
1840}
1841
1842/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1843/// in Mask are known to be either zero or one and return them in the
1844/// KnownZero/KnownOne bitsets.
1845void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1846                                                    APInt &KnownZero,
1847                                                    APInt &KnownOne,
1848                                                    const SelectionDAG &DAG,
1849                                                    unsigned Depth) const {
1850  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1851          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1852          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1853          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1854         "Should use MaskedValueIsZero if you don't know whether Op"
1855         " is a target node!");
1856  KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1857}
1858
1859/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1860/// targets that want to expose additional information about sign bits to the
1861/// DAG Combiner.
1862unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1863                                                         unsigned Depth) const {
1864  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1865          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1866          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1867          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1868         "Should use ComputeNumSignBits if you don't know whether Op"
1869         " is a target node!");
1870  return 1;
1871}
1872
1873/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1874/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1875/// determine which bit is set.
1876///
1877static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1878  // A left-shift of a constant one will have exactly one bit set, because
1879  // shifting the bit off the end is undefined.
1880  if (Val.getOpcode() == ISD::SHL)
1881    if (ConstantSDNode *C =
1882         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1883      if (C->getAPIntValue() == 1)
1884        return true;
1885
1886  // Similarly, a right-shift of a constant sign-bit will have exactly
1887  // one bit set.
1888  if (Val.getOpcode() == ISD::SRL)
1889    if (ConstantSDNode *C =
1890         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1891      if (C->getAPIntValue().isSignBit())
1892        return true;
1893
1894  // More could be done here, though the above checks are enough
1895  // to handle some common cases.
1896
1897  // Fall back to ComputeMaskedBits to catch other known cases.
1898  EVT OpVT = Val.getValueType();
1899  unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1900  APInt KnownZero, KnownOne;
1901  DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
1902  return (KnownZero.countPopulation() == BitWidth - 1) &&
1903         (KnownOne.countPopulation() == 1);
1904}
1905
1906/// SimplifySetCC - Try to simplify a setcc built with the specified operands
1907/// and cc. If it is unable to simplify it, return a null SDValue.
1908SDValue
1909TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1910                              ISD::CondCode Cond, bool foldBooleans,
1911                              DAGCombinerInfo &DCI, DebugLoc dl) const {
1912  SelectionDAG &DAG = DCI.DAG;
1913
1914  // These setcc operations always fold.
1915  switch (Cond) {
1916  default: break;
1917  case ISD::SETFALSE:
1918  case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1919  case ISD::SETTRUE:
1920  case ISD::SETTRUE2:  return DAG.getConstant(1, VT);
1921  }
1922
1923  // Ensure that the constant occurs on the RHS, and fold constant
1924  // comparisons.
1925  if (isa<ConstantSDNode>(N0.getNode()))
1926    return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1927
1928  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1929    const APInt &C1 = N1C->getAPIntValue();
1930
1931    // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1932    // equality comparison, then we're just comparing whether X itself is
1933    // zero.
1934    if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1935        N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1936        N0.getOperand(1).getOpcode() == ISD::Constant) {
1937      const APInt &ShAmt
1938        = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1939      if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1940          ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1941        if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1942          // (srl (ctlz x), 5) == 0  -> X != 0
1943          // (srl (ctlz x), 5) != 1  -> X != 0
1944          Cond = ISD::SETNE;
1945        } else {
1946          // (srl (ctlz x), 5) != 0  -> X == 0
1947          // (srl (ctlz x), 5) == 1  -> X == 0
1948          Cond = ISD::SETEQ;
1949        }
1950        SDValue Zero = DAG.getConstant(0, N0.getValueType());
1951        return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1952                            Zero, Cond);
1953      }
1954    }
1955
1956    SDValue CTPOP = N0;
1957    // Look through truncs that don't change the value of a ctpop.
1958    if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1959      CTPOP = N0.getOperand(0);
1960
1961    if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1962        (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1963                        Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1964      EVT CTVT = CTPOP.getValueType();
1965      SDValue CTOp = CTPOP.getOperand(0);
1966
1967      // (ctpop x) u< 2 -> (x & x-1) == 0
1968      // (ctpop x) u> 1 -> (x & x-1) != 0
1969      if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1970        SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1971                                  DAG.getConstant(1, CTVT));
1972        SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1973        ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1974        return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1975      }
1976
1977      // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1978    }
1979
1980    // (zext x) == C --> x == (trunc C)
1981    if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1982        (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1983      unsigned MinBits = N0.getValueSizeInBits();
1984      SDValue PreZExt;
1985      if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1986        // ZExt
1987        MinBits = N0->getOperand(0).getValueSizeInBits();
1988        PreZExt = N0->getOperand(0);
1989      } else if (N0->getOpcode() == ISD::AND) {
1990        // DAGCombine turns costly ZExts into ANDs
1991        if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1992          if ((C->getAPIntValue()+1).isPowerOf2()) {
1993            MinBits = C->getAPIntValue().countTrailingOnes();
1994            PreZExt = N0->getOperand(0);
1995          }
1996      } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1997        // ZEXTLOAD
1998        if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1999          MinBits = LN0->getMemoryVT().getSizeInBits();
2000          PreZExt = N0;
2001        }
2002      }
2003
2004      // Make sure we're not losing bits from the constant.
2005      if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2006        EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2007        if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2008          // Will get folded away.
2009          SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2010          SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2011          return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2012        }
2013      }
2014    }
2015
2016    // If the LHS is '(and load, const)', the RHS is 0,
2017    // the test is for equality or unsigned, and all 1 bits of the const are
2018    // in the same partial word, see if we can shorten the load.
2019    if (DCI.isBeforeLegalize() &&
2020        N0.getOpcode() == ISD::AND && C1 == 0 &&
2021        N0.getNode()->hasOneUse() &&
2022        isa<LoadSDNode>(N0.getOperand(0)) &&
2023        N0.getOperand(0).getNode()->hasOneUse() &&
2024        isa<ConstantSDNode>(N0.getOperand(1))) {
2025      LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
2026      APInt bestMask;
2027      unsigned bestWidth = 0, bestOffset = 0;
2028      if (!Lod->isVolatile() && Lod->isUnindexed()) {
2029        unsigned origWidth = N0.getValueType().getSizeInBits();
2030        unsigned maskWidth = origWidth;
2031        // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
2032        // 8 bits, but have to be careful...
2033        if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2034          origWidth = Lod->getMemoryVT().getSizeInBits();
2035        const APInt &Mask =
2036          cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2037        for (unsigned width = origWidth / 2; width>=8; width /= 2) {
2038          APInt newMask = APInt::getLowBitsSet(maskWidth, width);
2039          for (unsigned offset=0; offset<origWidth/width; offset++) {
2040            if ((newMask & Mask) == Mask) {
2041              if (!TD->isLittleEndian())
2042                bestOffset = (origWidth/width - offset - 1) * (width/8);
2043              else
2044                bestOffset = (uint64_t)offset * (width/8);
2045              bestMask = Mask.lshr(offset * (width/8) * 8);
2046              bestWidth = width;
2047              break;
2048            }
2049            newMask = newMask << width;
2050          }
2051        }
2052      }
2053      if (bestWidth) {
2054        EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
2055        if (newVT.isRound()) {
2056          EVT PtrType = Lod->getOperand(1).getValueType();
2057          SDValue Ptr = Lod->getBasePtr();
2058          if (bestOffset != 0)
2059            Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2060                              DAG.getConstant(bestOffset, PtrType));
2061          unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2062          SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
2063                                Lod->getPointerInfo().getWithOffset(bestOffset),
2064                                        false, false, false, NewAlign);
2065          return DAG.getSetCC(dl, VT,
2066                              DAG.getNode(ISD::AND, dl, newVT, NewLoad,
2067                                      DAG.getConstant(bestMask.trunc(bestWidth),
2068                                                      newVT)),
2069                              DAG.getConstant(0LL, newVT), Cond);
2070        }
2071      }
2072    }
2073
2074    // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2075    if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2076      unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2077
2078      // If the comparison constant has bits in the upper part, the
2079      // zero-extended value could never match.
2080      if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2081                                              C1.getBitWidth() - InSize))) {
2082        switch (Cond) {
2083        case ISD::SETUGT:
2084        case ISD::SETUGE:
2085        case ISD::SETEQ: return DAG.getConstant(0, VT);
2086        case ISD::SETULT:
2087        case ISD::SETULE:
2088        case ISD::SETNE: return DAG.getConstant(1, VT);
2089        case ISD::SETGT:
2090        case ISD::SETGE:
2091          // True if the sign bit of C1 is set.
2092          return DAG.getConstant(C1.isNegative(), VT);
2093        case ISD::SETLT:
2094        case ISD::SETLE:
2095          // True if the sign bit of C1 isn't set.
2096          return DAG.getConstant(C1.isNonNegative(), VT);
2097        default:
2098          break;
2099        }
2100      }
2101
2102      // Otherwise, we can perform the comparison with the low bits.
2103      switch (Cond) {
2104      case ISD::SETEQ:
2105      case ISD::SETNE:
2106      case ISD::SETUGT:
2107      case ISD::SETUGE:
2108      case ISD::SETULT:
2109      case ISD::SETULE: {
2110        EVT newVT = N0.getOperand(0).getValueType();
2111        if (DCI.isBeforeLegalizeOps() ||
2112            (isOperationLegal(ISD::SETCC, newVT) &&
2113              getCondCodeAction(Cond, newVT)==Legal))
2114          return DAG.getSetCC(dl, VT, N0.getOperand(0),
2115                              DAG.getConstant(C1.trunc(InSize), newVT),
2116                              Cond);
2117        break;
2118      }
2119      default:
2120        break;   // todo, be more careful with signed comparisons
2121      }
2122    } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2123               (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2124      EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2125      unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
2126      EVT ExtDstTy = N0.getValueType();
2127      unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2128
2129      // If the constant doesn't fit into the number of bits for the source of
2130      // the sign extension, it is impossible for both sides to be equal.
2131      if (C1.getMinSignedBits() > ExtSrcTyBits)
2132        return DAG.getConstant(Cond == ISD::SETNE, VT);
2133
2134      SDValue ZextOp;
2135      EVT Op0Ty = N0.getOperand(0).getValueType();
2136      if (Op0Ty == ExtSrcTy) {
2137        ZextOp = N0.getOperand(0);
2138      } else {
2139        APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2140        ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2141                              DAG.getConstant(Imm, Op0Ty));
2142      }
2143      if (!DCI.isCalledByLegalizer())
2144        DCI.AddToWorklist(ZextOp.getNode());
2145      // Otherwise, make this a use of a zext.
2146      return DAG.getSetCC(dl, VT, ZextOp,
2147                          DAG.getConstant(C1 & APInt::getLowBitsSet(
2148                                                              ExtDstTyBits,
2149                                                              ExtSrcTyBits),
2150                                          ExtDstTy),
2151                          Cond);
2152    } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2153                (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2154      // SETCC (SETCC), [0|1], [EQ|NE]  -> SETCC
2155      if (N0.getOpcode() == ISD::SETCC &&
2156          isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2157        bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
2158        if (TrueWhenTrue)
2159          return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2160        // Invert the condition.
2161        ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2162        CC = ISD::getSetCCInverse(CC,
2163                                  N0.getOperand(0).getValueType().isInteger());
2164        return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2165      }
2166
2167      if ((N0.getOpcode() == ISD::XOR ||
2168           (N0.getOpcode() == ISD::AND &&
2169            N0.getOperand(0).getOpcode() == ISD::XOR &&
2170            N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2171          isa<ConstantSDNode>(N0.getOperand(1)) &&
2172          cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2173        // If this is (X^1) == 0/1, swap the RHS and eliminate the xor.  We
2174        // can only do this if the top bits are known zero.
2175        unsigned BitWidth = N0.getValueSizeInBits();
2176        if (DAG.MaskedValueIsZero(N0,
2177                                  APInt::getHighBitsSet(BitWidth,
2178                                                        BitWidth-1))) {
2179          // Okay, get the un-inverted input value.
2180          SDValue Val;
2181          if (N0.getOpcode() == ISD::XOR)
2182            Val = N0.getOperand(0);
2183          else {
2184            assert(N0.getOpcode() == ISD::AND &&
2185                    N0.getOperand(0).getOpcode() == ISD::XOR);
2186            // ((X^1)&1)^1 -> X & 1
2187            Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2188                              N0.getOperand(0).getOperand(0),
2189                              N0.getOperand(1));
2190          }
2191
2192          return DAG.getSetCC(dl, VT, Val, N1,
2193                              Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2194        }
2195      } else if (N1C->getAPIntValue() == 1 &&
2196                 (VT == MVT::i1 ||
2197                  getBooleanContents(false) == ZeroOrOneBooleanContent)) {
2198        SDValue Op0 = N0;
2199        if (Op0.getOpcode() == ISD::TRUNCATE)
2200          Op0 = Op0.getOperand(0);
2201
2202        if ((Op0.getOpcode() == ISD::XOR) &&
2203            Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2204            Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2205          // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2206          Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2207          return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2208                              Cond);
2209        } else if (Op0.getOpcode() == ISD::AND &&
2210                isa<ConstantSDNode>(Op0.getOperand(1)) &&
2211                cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2212          // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
2213          if (Op0.getValueType().bitsGT(VT))
2214            Op0 = DAG.getNode(ISD::AND, dl, VT,
2215                          DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2216                          DAG.getConstant(1, VT));
2217          else if (Op0.getValueType().bitsLT(VT))
2218            Op0 = DAG.getNode(ISD::AND, dl, VT,
2219                        DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2220                        DAG.getConstant(1, VT));
2221
2222          return DAG.getSetCC(dl, VT, Op0,
2223                              DAG.getConstant(0, Op0.getValueType()),
2224                              Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2225        }
2226      }
2227    }
2228
2229    APInt MinVal, MaxVal;
2230    unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2231    if (ISD::isSignedIntSetCC(Cond)) {
2232      MinVal = APInt::getSignedMinValue(OperandBitSize);
2233      MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2234    } else {
2235      MinVal = APInt::getMinValue(OperandBitSize);
2236      MaxVal = APInt::getMaxValue(OperandBitSize);
2237    }
2238
2239    // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2240    if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2241      if (C1 == MinVal) return DAG.getConstant(1, VT);   // X >= MIN --> true
2242      // X >= C0 --> X > (C0-1)
2243      return DAG.getSetCC(dl, VT, N0,
2244                          DAG.getConstant(C1-1, N1.getValueType()),
2245                          (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2246    }
2247
2248    if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2249      if (C1 == MaxVal) return DAG.getConstant(1, VT);   // X <= MAX --> true
2250      // X <= C0 --> X < (C0+1)
2251      return DAG.getSetCC(dl, VT, N0,
2252                          DAG.getConstant(C1+1, N1.getValueType()),
2253                          (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2254    }
2255
2256    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2257      return DAG.getConstant(0, VT);      // X < MIN --> false
2258    if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2259      return DAG.getConstant(1, VT);      // X >= MIN --> true
2260    if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2261      return DAG.getConstant(0, VT);      // X > MAX --> false
2262    if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2263      return DAG.getConstant(1, VT);      // X <= MAX --> true
2264
2265    // Canonicalize setgt X, Min --> setne X, Min
2266    if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2267      return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2268    // Canonicalize setlt X, Max --> setne X, Max
2269    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2270      return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2271
2272    // If we have setult X, 1, turn it into seteq X, 0
2273    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2274      return DAG.getSetCC(dl, VT, N0,
2275                          DAG.getConstant(MinVal, N0.getValueType()),
2276                          ISD::SETEQ);
2277    // If we have setugt X, Max-1, turn it into seteq X, Max
2278    else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2279      return DAG.getSetCC(dl, VT, N0,
2280                          DAG.getConstant(MaxVal, N0.getValueType()),
2281                          ISD::SETEQ);
2282
2283    // If we have "setcc X, C0", check to see if we can shrink the immediate
2284    // by changing cc.
2285
2286    // SETUGT X, SINTMAX  -> SETLT X, 0
2287    if (Cond == ISD::SETUGT &&
2288        C1 == APInt::getSignedMaxValue(OperandBitSize))
2289      return DAG.getSetCC(dl, VT, N0,
2290                          DAG.getConstant(0, N1.getValueType()),
2291                          ISD::SETLT);
2292
2293    // SETULT X, SINTMIN  -> SETGT X, -1
2294    if (Cond == ISD::SETULT &&
2295        C1 == APInt::getSignedMinValue(OperandBitSize)) {
2296      SDValue ConstMinusOne =
2297          DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2298                          N1.getValueType());
2299      return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2300    }
2301
2302    // Fold bit comparisons when we can.
2303    if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2304        (VT == N0.getValueType() ||
2305         (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2306        N0.getOpcode() == ISD::AND)
2307      if (ConstantSDNode *AndRHS =
2308                  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2309        EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
2310          getPointerTy() : getShiftAmountTy(N0.getValueType());
2311        if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
2312          // Perform the xform if the AND RHS is a single bit.
2313          if (AndRHS->getAPIntValue().isPowerOf2()) {
2314            return DAG.getNode(ISD::TRUNCATE, dl, VT,
2315                              DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2316                   DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
2317          }
2318        } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2319          // (X & 8) == 8  -->  (X & 8) >> 3
2320          // Perform the xform if C1 is a single bit.
2321          if (C1.isPowerOf2()) {
2322            return DAG.getNode(ISD::TRUNCATE, dl, VT,
2323                               DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2324                                      DAG.getConstant(C1.logBase2(), ShiftTy)));
2325          }
2326        }
2327      }
2328
2329    if (C1.getMinSignedBits() <= 64 &&
2330        !isLegalICmpImmediate(C1.getSExtValue())) {
2331      // (X & -256) == 256 -> (X >> 8) == 1
2332      if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2333          N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
2334        if (ConstantSDNode *AndRHS =
2335            dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2336          const APInt &AndRHSC = AndRHS->getAPIntValue();
2337          if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
2338            unsigned ShiftBits = AndRHSC.countTrailingZeros();
2339            EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
2340              getPointerTy() : getShiftAmountTy(N0.getValueType());
2341            EVT CmpTy = N0.getValueType();
2342            SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
2343                                        DAG.getConstant(ShiftBits, ShiftTy));
2344            SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
2345            return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
2346          }
2347        }
2348      } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
2349                 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
2350        bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
2351        // X <  0x100000000 -> (X >> 32) <  1
2352        // X >= 0x100000000 -> (X >> 32) >= 1
2353        // X <= 0x0ffffffff -> (X >> 32) <  1
2354        // X >  0x0ffffffff -> (X >> 32) >= 1
2355        unsigned ShiftBits;
2356        APInt NewC = C1;
2357        ISD::CondCode NewCond = Cond;
2358        if (AdjOne) {
2359          ShiftBits = C1.countTrailingOnes();
2360          NewC = NewC + 1;
2361          NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2362        } else {
2363          ShiftBits = C1.countTrailingZeros();
2364        }
2365        NewC = NewC.lshr(ShiftBits);
2366        if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
2367          EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
2368            getPointerTy() : getShiftAmountTy(N0.getValueType());
2369          EVT CmpTy = N0.getValueType();
2370          SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
2371                                      DAG.getConstant(ShiftBits, ShiftTy));
2372          SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
2373          return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
2374        }
2375      }
2376    }
2377  }
2378
2379  if (isa<ConstantFPSDNode>(N0.getNode())) {
2380    // Constant fold or commute setcc.
2381    SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2382    if (O.getNode()) return O;
2383  } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2384    // If the RHS of an FP comparison is a constant, simplify it away in
2385    // some cases.
2386    if (CFP->getValueAPF().isNaN()) {
2387      // If an operand is known to be a nan, we can fold it.
2388      switch (ISD::getUnorderedFlavor(Cond)) {
2389      default: llvm_unreachable("Unknown flavor!");
2390      case 0:  // Known false.
2391        return DAG.getConstant(0, VT);
2392      case 1:  // Known true.
2393        return DAG.getConstant(1, VT);
2394      case 2:  // Undefined.
2395        return DAG.getUNDEF(VT);
2396      }
2397    }
2398
2399    // Otherwise, we know the RHS is not a NaN.  Simplify the node to drop the
2400    // constant if knowing that the operand is non-nan is enough.  We prefer to
2401    // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2402    // materialize 0.0.
2403    if (Cond == ISD::SETO || Cond == ISD::SETUO)
2404      return DAG.getSetCC(dl, VT, N0, N0, Cond);
2405
2406    // If the condition is not legal, see if we can find an equivalent one
2407    // which is legal.
2408    if (!isCondCodeLegal(Cond, N0.getValueType())) {
2409      // If the comparison was an awkward floating-point == or != and one of
2410      // the comparison operands is infinity or negative infinity, convert the
2411      // condition to a less-awkward <= or >=.
2412      if (CFP->getValueAPF().isInfinity()) {
2413        if (CFP->getValueAPF().isNegative()) {
2414          if (Cond == ISD::SETOEQ &&
2415              isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2416            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2417          if (Cond == ISD::SETUEQ &&
2418              isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2419            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2420          if (Cond == ISD::SETUNE &&
2421              isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2422            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2423          if (Cond == ISD::SETONE &&
2424              isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2425            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2426        } else {
2427          if (Cond == ISD::SETOEQ &&
2428              isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2429            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2430          if (Cond == ISD::SETUEQ &&
2431              isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2432            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2433          if (Cond == ISD::SETUNE &&
2434              isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2435            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2436          if (Cond == ISD::SETONE &&
2437              isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2438            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2439        }
2440      }
2441    }
2442  }
2443
2444  if (N0 == N1) {
2445    // The sext(setcc()) => setcc() optimization relies on the appropriate
2446    // constant being emitted.
2447    uint64_t EqVal = 0;
2448    switch (getBooleanContents(N0.getValueType().isVector())) {
2449    case UndefinedBooleanContent:
2450    case ZeroOrOneBooleanContent:
2451      EqVal = ISD::isTrueWhenEqual(Cond);
2452      break;
2453    case ZeroOrNegativeOneBooleanContent:
2454      EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
2455      break;
2456    }
2457
2458    // We can always fold X == X for integer setcc's.
2459    if (N0.getValueType().isInteger()) {
2460      return DAG.getConstant(EqVal, VT);
2461    }
2462    unsigned UOF = ISD::getUnorderedFlavor(Cond);
2463    if (UOF == 2)   // FP operators that are undefined on NaNs.
2464      return DAG.getConstant(EqVal, VT);
2465    if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2466      return DAG.getConstant(EqVal, VT);
2467    // Otherwise, we can't fold it.  However, we can simplify it to SETUO/SETO
2468    // if it is not already.
2469    ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2470    if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
2471          getCondCodeAction(NewCond, N0.getValueType()) == Legal))
2472      return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2473  }
2474
2475  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2476      N0.getValueType().isInteger()) {
2477    if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2478        N0.getOpcode() == ISD::XOR) {
2479      // Simplify (X+Y) == (X+Z) -->  Y == Z
2480      if (N0.getOpcode() == N1.getOpcode()) {
2481        if (N0.getOperand(0) == N1.getOperand(0))
2482          return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2483        if (N0.getOperand(1) == N1.getOperand(1))
2484          return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2485        if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2486          // If X op Y == Y op X, try other combinations.
2487          if (N0.getOperand(0) == N1.getOperand(1))
2488            return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2489                                Cond);
2490          if (N0.getOperand(1) == N1.getOperand(0))
2491            return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2492                                Cond);
2493        }
2494      }
2495
2496      // If RHS is a legal immediate value for a compare instruction, we need
2497      // to be careful about increasing register pressure needlessly.
2498      bool LegalRHSImm = false;
2499
2500      if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2501        if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2502          // Turn (X+C1) == C2 --> X == C2-C1
2503          if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2504            return DAG.getSetCC(dl, VT, N0.getOperand(0),
2505                                DAG.getConstant(RHSC->getAPIntValue()-
2506                                                LHSR->getAPIntValue(),
2507                                N0.getValueType()), Cond);
2508          }
2509
2510          // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2511          if (N0.getOpcode() == ISD::XOR)
2512            // If we know that all of the inverted bits are zero, don't bother
2513            // performing the inversion.
2514            if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2515              return
2516                DAG.getSetCC(dl, VT, N0.getOperand(0),
2517                             DAG.getConstant(LHSR->getAPIntValue() ^
2518                                               RHSC->getAPIntValue(),
2519                                             N0.getValueType()),
2520                             Cond);
2521        }
2522
2523        // Turn (C1-X) == C2 --> X == C1-C2
2524        if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2525          if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2526            return
2527              DAG.getSetCC(dl, VT, N0.getOperand(1),
2528                           DAG.getConstant(SUBC->getAPIntValue() -
2529                                             RHSC->getAPIntValue(),
2530                                           N0.getValueType()),
2531                           Cond);
2532          }
2533        }
2534
2535        // Could RHSC fold directly into a compare?
2536        if (RHSC->getValueType(0).getSizeInBits() <= 64)
2537          LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
2538      }
2539
2540      // Simplify (X+Z) == X -->  Z == 0
2541      // Don't do this if X is an immediate that can fold into a cmp
2542      // instruction and X+Z has other uses. It could be an induction variable
2543      // chain, and the transform would increase register pressure.
2544      if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
2545        if (N0.getOperand(0) == N1)
2546          return DAG.getSetCC(dl, VT, N0.getOperand(1),
2547                              DAG.getConstant(0, N0.getValueType()), Cond);
2548        if (N0.getOperand(1) == N1) {
2549          if (DAG.isCommutativeBinOp(N0.getOpcode()))
2550            return DAG.getSetCC(dl, VT, N0.getOperand(0),
2551                                DAG.getConstant(0, N0.getValueType()), Cond);
2552          else if (N0.getNode()->hasOneUse()) {
2553            assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2554            // (Z-X) == X  --> Z == X<<1
2555            SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
2556                       DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
2557            if (!DCI.isCalledByLegalizer())
2558              DCI.AddToWorklist(SH.getNode());
2559            return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2560          }
2561        }
2562      }
2563    }
2564
2565    if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2566        N1.getOpcode() == ISD::XOR) {
2567      // Simplify  X == (X+Z) -->  Z == 0
2568      if (N1.getOperand(0) == N0) {
2569        return DAG.getSetCC(dl, VT, N1.getOperand(1),
2570                        DAG.getConstant(0, N1.getValueType()), Cond);
2571      } else if (N1.getOperand(1) == N0) {
2572        if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2573          return DAG.getSetCC(dl, VT, N1.getOperand(0),
2574                          DAG.getConstant(0, N1.getValueType()), Cond);
2575        } else if (N1.getNode()->hasOneUse()) {
2576          assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2577          // X == (Z-X)  --> X<<1 == Z
2578          SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2579                       DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
2580          if (!DCI.isCalledByLegalizer())
2581            DCI.AddToWorklist(SH.getNode());
2582          return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2583        }
2584      }
2585    }
2586
2587    // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2588    // Note that where y is variable and is known to have at most
2589    // one bit set (for example, if it is z&1) we cannot do this;
2590    // the expressions are not equivalent when y==0.
2591    if (N0.getOpcode() == ISD::AND)
2592      if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2593        if (ValueHasExactlyOneBitSet(N1, DAG)) {
2594          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2595          SDValue Zero = DAG.getConstant(0, N1.getValueType());
2596          return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2597        }
2598      }
2599    if (N1.getOpcode() == ISD::AND)
2600      if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2601        if (ValueHasExactlyOneBitSet(N0, DAG)) {
2602          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2603          SDValue Zero = DAG.getConstant(0, N0.getValueType());
2604          return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2605        }
2606      }
2607  }
2608
2609  // Fold away ALL boolean setcc's.
2610  SDValue Temp;
2611  if (N0.getValueType() == MVT::i1 && foldBooleans) {
2612    switch (Cond) {
2613    default: llvm_unreachable("Unknown integer setcc!");
2614    case ISD::SETEQ:  // X == Y  -> ~(X^Y)
2615      Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2616      N0 = DAG.getNOT(dl, Temp, MVT::i1);
2617      if (!DCI.isCalledByLegalizer())
2618        DCI.AddToWorklist(Temp.getNode());
2619      break;
2620    case ISD::SETNE:  // X != Y   -->  (X^Y)
2621      N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2622      break;
2623    case ISD::SETGT:  // X >s Y   -->  X == 0 & Y == 1  -->  ~X & Y
2624    case ISD::SETULT: // X <u Y   -->  X == 0 & Y == 1  -->  ~X & Y
2625      Temp = DAG.getNOT(dl, N0, MVT::i1);
2626      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2627      if (!DCI.isCalledByLegalizer())
2628        DCI.AddToWorklist(Temp.getNode());
2629      break;
2630    case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  ~Y & X
2631    case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  ~Y & X
2632      Temp = DAG.getNOT(dl, N1, MVT::i1);
2633      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2634      if (!DCI.isCalledByLegalizer())
2635        DCI.AddToWorklist(Temp.getNode());
2636      break;
2637    case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  ~X | Y
2638    case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  ~X | Y
2639      Temp = DAG.getNOT(dl, N0, MVT::i1);
2640      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2641      if (!DCI.isCalledByLegalizer())
2642        DCI.AddToWorklist(Temp.getNode());
2643      break;
2644    case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  ~Y | X
2645    case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  ~Y | X
2646      Temp = DAG.getNOT(dl, N1, MVT::i1);
2647      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2648      break;
2649    }
2650    if (VT != MVT::i1) {
2651      if (!DCI.isCalledByLegalizer())
2652        DCI.AddToWorklist(N0.getNode());
2653      // FIXME: If running after legalize, we probably can't do this.
2654      N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2655    }
2656    return N0;
2657  }
2658
2659  // Could not fold it.
2660  return SDValue();
2661}
2662
2663/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2664/// node is a GlobalAddress + offset.
2665bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2666                                    int64_t &Offset) const {
2667  if (isa<GlobalAddressSDNode>(N)) {
2668    GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2669    GA = GASD->getGlobal();
2670    Offset += GASD->getOffset();
2671    return true;
2672  }
2673
2674  if (N->getOpcode() == ISD::ADD) {
2675    SDValue N1 = N->getOperand(0);
2676    SDValue N2 = N->getOperand(1);
2677    if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2678      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2679      if (V) {
2680        Offset += V->getSExtValue();
2681        return true;
2682      }
2683    } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2684      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2685      if (V) {
2686        Offset += V->getSExtValue();
2687        return true;
2688      }
2689    }
2690  }
2691
2692  return false;
2693}
2694
2695
2696SDValue TargetLowering::
2697PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2698  // Default implementation: no optimization.
2699  return SDValue();
2700}
2701
2702//===----------------------------------------------------------------------===//
2703//  Inline Assembler Implementation Methods
2704//===----------------------------------------------------------------------===//
2705
2706
2707TargetLowering::ConstraintType
2708TargetLowering::getConstraintType(const std::string &Constraint) const {
2709  if (Constraint.size() == 1) {
2710    switch (Constraint[0]) {
2711    default: break;
2712    case 'r': return C_RegisterClass;
2713    case 'm':    // memory
2714    case 'o':    // offsetable
2715    case 'V':    // not offsetable
2716      return C_Memory;
2717    case 'i':    // Simple Integer or Relocatable Constant
2718    case 'n':    // Simple Integer
2719    case 'E':    // Floating Point Constant
2720    case 'F':    // Floating Point Constant
2721    case 's':    // Relocatable Constant
2722    case 'p':    // Address.
2723    case 'X':    // Allow ANY value.
2724    case 'I':    // Target registers.
2725    case 'J':
2726    case 'K':
2727    case 'L':
2728    case 'M':
2729    case 'N':
2730    case 'O':
2731    case 'P':
2732    case '<':
2733    case '>':
2734      return C_Other;
2735    }
2736  }
2737
2738  if (Constraint.size() > 1 && Constraint[0] == '{' &&
2739      Constraint[Constraint.size()-1] == '}')
2740    return C_Register;
2741  return C_Unknown;
2742}
2743
2744/// LowerXConstraint - try to replace an X constraint, which matches anything,
2745/// with another that has more specific requirements based on the type of the
2746/// corresponding operand.
2747const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2748  if (ConstraintVT.isInteger())
2749    return "r";
2750  if (ConstraintVT.isFloatingPoint())
2751    return "f";      // works for many targets
2752  return 0;
2753}
2754
2755/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2756/// vector.  If it is invalid, don't add anything to Ops.
2757void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2758                                                  std::string &Constraint,
2759                                                  std::vector<SDValue> &Ops,
2760                                                  SelectionDAG &DAG) const {
2761
2762  if (Constraint.length() > 1) return;
2763
2764  char ConstraintLetter = Constraint[0];
2765  switch (ConstraintLetter) {
2766  default: break;
2767  case 'X':     // Allows any operand; labels (basic block) use this.
2768    if (Op.getOpcode() == ISD::BasicBlock) {
2769      Ops.push_back(Op);
2770      return;
2771    }
2772    // fall through
2773  case 'i':    // Simple Integer or Relocatable Constant
2774  case 'n':    // Simple Integer
2775  case 's': {  // Relocatable Constant
2776    // These operands are interested in values of the form (GV+C), where C may
2777    // be folded in as an offset of GV, or it may be explicitly added.  Also, it
2778    // is possible and fine if either GV or C are missing.
2779    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2780    GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2781
2782    // If we have "(add GV, C)", pull out GV/C
2783    if (Op.getOpcode() == ISD::ADD) {
2784      C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2785      GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2786      if (C == 0 || GA == 0) {
2787        C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2788        GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2789      }
2790      if (C == 0 || GA == 0)
2791        C = 0, GA = 0;
2792    }
2793
2794    // If we find a valid operand, map to the TargetXXX version so that the
2795    // value itself doesn't get selected.
2796    if (GA) {   // Either &GV   or   &GV+C
2797      if (ConstraintLetter != 'n') {
2798        int64_t Offs = GA->getOffset();
2799        if (C) Offs += C->getZExtValue();
2800        Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2801                                                 C ? C->getDebugLoc() : DebugLoc(),
2802                                                 Op.getValueType(), Offs));
2803        return;
2804      }
2805    }
2806    if (C) {   // just C, no GV.
2807      // Simple constants are not allowed for 's'.
2808      if (ConstraintLetter != 's') {
2809        // gcc prints these as sign extended.  Sign extend value to 64 bits
2810        // now; without this it would get ZExt'd later in
2811        // ScheduleDAGSDNodes::EmitNode, which is very generic.
2812        Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2813                                            MVT::i64));
2814        return;
2815      }
2816    }
2817    break;
2818  }
2819  }
2820}
2821
2822std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2823getRegForInlineAsmConstraint(const std::string &Constraint,
2824                             EVT VT) const {
2825  if (Constraint[0] != '{')
2826    return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
2827  assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2828
2829  // Remove the braces from around the name.
2830  StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2831
2832  // Figure out which register class contains this reg.
2833  const TargetRegisterInfo *RI = TM.getRegisterInfo();
2834  for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2835       E = RI->regclass_end(); RCI != E; ++RCI) {
2836    const TargetRegisterClass *RC = *RCI;
2837
2838    // If none of the value types for this register class are valid, we
2839    // can't use it.  For example, 64-bit reg classes on 32-bit targets.
2840    if (!isLegalRC(RC))
2841      continue;
2842
2843    for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2844         I != E; ++I) {
2845      if (RegName.equals_lower(RI->getName(*I)))
2846        return std::make_pair(*I, RC);
2847    }
2848  }
2849
2850  return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2851}
2852
2853//===----------------------------------------------------------------------===//
2854// Constraint Selection.
2855
2856/// isMatchingInputConstraint - Return true of this is an input operand that is
2857/// a matching constraint like "4".
2858bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2859  assert(!ConstraintCode.empty() && "No known constraint!");
2860  return isdigit(ConstraintCode[0]);
2861}
2862
2863/// getMatchedOperand - If this is an input matching constraint, this method
2864/// returns the output operand it matches.
2865unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2866  assert(!ConstraintCode.empty() && "No known constraint!");
2867  return atoi(ConstraintCode.c_str());
2868}
2869
2870
2871/// ParseConstraints - Split up the constraint string from the inline
2872/// assembly value into the specific constraints and their prefixes,
2873/// and also tie in the associated operand values.
2874/// If this returns an empty vector, and if the constraint string itself
2875/// isn't empty, there was an error parsing.
2876TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2877    ImmutableCallSite CS) const {
2878  /// ConstraintOperands - Information about all of the constraints.
2879  AsmOperandInfoVector ConstraintOperands;
2880  const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2881  unsigned maCount = 0; // Largest number of multiple alternative constraints.
2882
2883  // Do a prepass over the constraints, canonicalizing them, and building up the
2884  // ConstraintOperands list.
2885  InlineAsm::ConstraintInfoVector
2886    ConstraintInfos = IA->ParseConstraints();
2887
2888  unsigned ArgNo = 0;   // ArgNo - The argument of the CallInst.
2889  unsigned ResNo = 0;   // ResNo - The result number of the next output.
2890
2891  for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2892    ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2893    AsmOperandInfo &OpInfo = ConstraintOperands.back();
2894
2895    // Update multiple alternative constraint count.
2896    if (OpInfo.multipleAlternatives.size() > maCount)
2897      maCount = OpInfo.multipleAlternatives.size();
2898
2899    OpInfo.ConstraintVT = MVT::Other;
2900
2901    // Compute the value type for each operand.
2902    switch (OpInfo.Type) {
2903    case InlineAsm::isOutput:
2904      // Indirect outputs just consume an argument.
2905      if (OpInfo.isIndirect) {
2906        OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2907        break;
2908      }
2909
2910      // The return value of the call is this value.  As such, there is no
2911      // corresponding argument.
2912      assert(!CS.getType()->isVoidTy() &&
2913             "Bad inline asm!");
2914      if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2915        OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
2916      } else {
2917        assert(ResNo == 0 && "Asm only has one result!");
2918        OpInfo.ConstraintVT = getValueType(CS.getType());
2919      }
2920      ++ResNo;
2921      break;
2922    case InlineAsm::isInput:
2923      OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2924      break;
2925    case InlineAsm::isClobber:
2926      // Nothing to do.
2927      break;
2928    }
2929
2930    if (OpInfo.CallOperandVal) {
2931      llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2932      if (OpInfo.isIndirect) {
2933        llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2934        if (!PtrTy)
2935          report_fatal_error("Indirect operand for inline asm not a pointer!");
2936        OpTy = PtrTy->getElementType();
2937      }
2938
2939      // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2940      if (StructType *STy = dyn_cast<StructType>(OpTy))
2941        if (STy->getNumElements() == 1)
2942          OpTy = STy->getElementType(0);
2943
2944      // If OpTy is not a single value, it may be a struct/union that we
2945      // can tile with integers.
2946      if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2947        unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2948        switch (BitSize) {
2949        default: break;
2950        case 1:
2951        case 8:
2952        case 16:
2953        case 32:
2954        case 64:
2955        case 128:
2956          OpInfo.ConstraintVT =
2957              EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2958          break;
2959        }
2960      } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2961        OpInfo.ConstraintVT = MVT::getIntegerVT(
2962            8*TD->getPointerSize(PT->getAddressSpace()));
2963      } else {
2964        OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2965      }
2966    }
2967  }
2968
2969  // If we have multiple alternative constraints, select the best alternative.
2970  if (ConstraintInfos.size()) {
2971    if (maCount) {
2972      unsigned bestMAIndex = 0;
2973      int bestWeight = -1;
2974      // weight:  -1 = invalid match, and 0 = so-so match to 5 = good match.
2975      int weight = -1;
2976      unsigned maIndex;
2977      // Compute the sums of the weights for each alternative, keeping track
2978      // of the best (highest weight) one so far.
2979      for (maIndex = 0; maIndex < maCount; ++maIndex) {
2980        int weightSum = 0;
2981        for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2982            cIndex != eIndex; ++cIndex) {
2983          AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2984          if (OpInfo.Type == InlineAsm::isClobber)
2985            continue;
2986
2987          // If this is an output operand with a matching input operand,
2988          // look up the matching input. If their types mismatch, e.g. one
2989          // is an integer, the other is floating point, or their sizes are
2990          // different, flag it as an maCantMatch.
2991          if (OpInfo.hasMatchingInput()) {
2992            AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2993            if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2994              if ((OpInfo.ConstraintVT.isInteger() !=
2995                   Input.ConstraintVT.isInteger()) ||
2996                  (OpInfo.ConstraintVT.getSizeInBits() !=
2997                   Input.ConstraintVT.getSizeInBits())) {
2998                weightSum = -1;  // Can't match.
2999                break;
3000              }
3001            }
3002          }
3003          weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
3004          if (weight == -1) {
3005            weightSum = -1;
3006            break;
3007          }
3008          weightSum += weight;
3009        }
3010        // Update best.
3011        if (weightSum > bestWeight) {
3012          bestWeight = weightSum;
3013          bestMAIndex = maIndex;
3014        }
3015      }
3016
3017      // Now select chosen alternative in each constraint.
3018      for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3019          cIndex != eIndex; ++cIndex) {
3020        AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
3021        if (cInfo.Type == InlineAsm::isClobber)
3022          continue;
3023        cInfo.selectAlternative(bestMAIndex);
3024      }
3025    }
3026  }
3027
3028  // Check and hook up tied operands, choose constraint code to use.
3029  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3030      cIndex != eIndex; ++cIndex) {
3031    AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
3032
3033    // If this is an output operand with a matching input operand, look up the
3034    // matching input. If their types mismatch, e.g. one is an integer, the
3035    // other is floating point, or their sizes are different, flag it as an
3036    // error.
3037    if (OpInfo.hasMatchingInput()) {
3038      AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
3039
3040      if (OpInfo.ConstraintVT != Input.ConstraintVT) {
3041        std::pair<unsigned, const TargetRegisterClass*> MatchRC =
3042          getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3043                                       OpInfo.ConstraintVT);
3044        std::pair<unsigned, const TargetRegisterClass*> InputRC =
3045          getRegForInlineAsmConstraint(Input.ConstraintCode,
3046                                       Input.ConstraintVT);
3047        if ((OpInfo.ConstraintVT.isInteger() !=
3048             Input.ConstraintVT.isInteger()) ||
3049            (MatchRC.second != InputRC.second)) {
3050          report_fatal_error("Unsupported asm: input constraint"
3051                             " with a matching output constraint of"
3052                             " incompatible type!");
3053        }
3054      }
3055
3056    }
3057  }
3058
3059  return ConstraintOperands;
3060}
3061
3062
3063/// getConstraintGenerality - Return an integer indicating how general CT
3064/// is.
3065static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3066  switch (CT) {
3067  case TargetLowering::C_Other:
3068  case TargetLowering::C_Unknown:
3069    return 0;
3070  case TargetLowering::C_Register:
3071    return 1;
3072  case TargetLowering::C_RegisterClass:
3073    return 2;
3074  case TargetLowering::C_Memory:
3075    return 3;
3076  }
3077  llvm_unreachable("Invalid constraint type");
3078}
3079
3080/// Examine constraint type and operand type and determine a weight value.
3081/// This object must already have been set up with the operand type
3082/// and the current alternative constraint selected.
3083TargetLowering::ConstraintWeight
3084  TargetLowering::getMultipleConstraintMatchWeight(
3085    AsmOperandInfo &info, int maIndex) const {
3086  InlineAsm::ConstraintCodeVector *rCodes;
3087  if (maIndex >= (int)info.multipleAlternatives.size())
3088    rCodes = &info.Codes;
3089  else
3090    rCodes = &info.multipleAlternatives[maIndex].Codes;
3091  ConstraintWeight BestWeight = CW_Invalid;
3092
3093  // Loop over the options, keeping track of the most general one.
3094  for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
3095    ConstraintWeight weight =
3096      getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
3097    if (weight > BestWeight)
3098      BestWeight = weight;
3099  }
3100
3101  return BestWeight;
3102}
3103
3104/// Examine constraint type and operand type and determine a weight value.
3105/// This object must already have been set up with the operand type
3106/// and the current alternative constraint selected.
3107TargetLowering::ConstraintWeight
3108  TargetLowering::getSingleConstraintMatchWeight(
3109    AsmOperandInfo &info, const char *constraint) const {
3110  ConstraintWeight weight = CW_Invalid;
3111  Value *CallOperandVal = info.CallOperandVal;
3112    // If we don't have a value, we can't do a match,
3113    // but allow it at the lowest weight.
3114  if (CallOperandVal == NULL)
3115    return CW_Default;
3116  // Look at the constraint type.
3117  switch (*constraint) {
3118    case 'i': // immediate integer.
3119    case 'n': // immediate integer with a known value.
3120      if (isa<ConstantInt>(CallOperandVal))
3121        weight = CW_Constant;
3122      break;
3123    case 's': // non-explicit intregal immediate.
3124      if (isa<GlobalValue>(CallOperandVal))
3125        weight = CW_Constant;
3126      break;
3127    case 'E': // immediate float if host format.
3128    case 'F': // immediate float.
3129      if (isa<ConstantFP>(CallOperandVal))
3130        weight = CW_Constant;
3131      break;
3132    case '<': // memory operand with autodecrement.
3133    case '>': // memory operand with autoincrement.
3134    case 'm': // memory operand.
3135    case 'o': // offsettable memory operand
3136    case 'V': // non-offsettable memory operand
3137      weight = CW_Memory;
3138      break;
3139    case 'r': // general register.
3140    case 'g': // general register, memory operand or immediate integer.
3141              // note: Clang converts "g" to "imr".
3142      if (CallOperandVal->getType()->isIntegerTy())
3143        weight = CW_Register;
3144      break;
3145    case 'X': // any operand.
3146    default:
3147      weight = CW_Default;
3148      break;
3149  }
3150  return weight;
3151}
3152
3153/// ChooseConstraint - If there are multiple different constraints that we
3154/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
3155/// This is somewhat tricky: constraints fall into four classes:
3156///    Other         -> immediates and magic values
3157///    Register      -> one specific register
3158///    RegisterClass -> a group of regs
3159///    Memory        -> memory
3160/// Ideally, we would pick the most specific constraint possible: if we have
3161/// something that fits into a register, we would pick it.  The problem here
3162/// is that if we have something that could either be in a register or in
3163/// memory that use of the register could cause selection of *other*
3164/// operands to fail: they might only succeed if we pick memory.  Because of
3165/// this the heuristic we use is:
3166///
3167///  1) If there is an 'other' constraint, and if the operand is valid for
3168///     that constraint, use it.  This makes us take advantage of 'i'
3169///     constraints when available.
3170///  2) Otherwise, pick the most general constraint present.  This prefers
3171///     'm' over 'r', for example.
3172///
3173static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
3174                             const TargetLowering &TLI,
3175                             SDValue Op, SelectionDAG *DAG) {
3176  assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3177  unsigned BestIdx = 0;
3178  TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3179  int BestGenerality = -1;
3180
3181  // Loop over the options, keeping track of the most general one.
3182  for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3183    TargetLowering::ConstraintType CType =
3184      TLI.getConstraintType(OpInfo.Codes[i]);
3185
3186    // If this is an 'other' constraint, see if the operand is valid for it.
3187    // For example, on X86 we might have an 'rI' constraint.  If the operand
3188    // is an integer in the range [0..31] we want to use I (saving a load
3189    // of a register), otherwise we must use 'r'.
3190    if (CType == TargetLowering::C_Other && Op.getNode()) {
3191      assert(OpInfo.Codes[i].size() == 1 &&
3192             "Unhandled multi-letter 'other' constraint");
3193      std::vector<SDValue> ResultOps;
3194      TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
3195                                       ResultOps, *DAG);
3196      if (!ResultOps.empty()) {
3197        BestType = CType;
3198        BestIdx = i;
3199        break;
3200      }
3201    }
3202
3203    // Things with matching constraints can only be registers, per gcc
3204    // documentation.  This mainly affects "g" constraints.
3205    if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3206      continue;
3207
3208    // This constraint letter is more general than the previous one, use it.
3209    int Generality = getConstraintGenerality(CType);
3210    if (Generality > BestGenerality) {
3211      BestType = CType;
3212      BestIdx = i;
3213      BestGenerality = Generality;
3214    }
3215  }
3216
3217  OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3218  OpInfo.ConstraintType = BestType;
3219}
3220
3221/// ComputeConstraintToUse - Determines the constraint code and constraint
3222/// type to use for the specific AsmOperandInfo, setting
3223/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
3224void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3225                                            SDValue Op,
3226                                            SelectionDAG *DAG) const {
3227  assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
3228
3229  // Single-letter constraints ('r') are very common.
3230  if (OpInfo.Codes.size() == 1) {
3231    OpInfo.ConstraintCode = OpInfo.Codes[0];
3232    OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3233  } else {
3234    ChooseConstraint(OpInfo, *this, Op, DAG);
3235  }
3236
3237  // 'X' matches anything.
3238  if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3239    // Labels and constants are handled elsewhere ('X' is the only thing
3240    // that matches labels).  For Functions, the type here is the type of
3241    // the result, which is not what we want to look at; leave them alone.
3242    Value *v = OpInfo.CallOperandVal;
3243    if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3244      OpInfo.CallOperandVal = v;
3245      return;
3246    }
3247
3248    // Otherwise, try to resolve it to something we know about by looking at
3249    // the actual operand type.
3250    if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3251      OpInfo.ConstraintCode = Repl;
3252      OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3253    }
3254  }
3255}
3256
3257//===----------------------------------------------------------------------===//
3258//  Loop Strength Reduction hooks
3259//===----------------------------------------------------------------------===//
3260
3261/// isLegalAddressingMode - Return true if the addressing mode represented
3262/// by AM is legal for this target, for a load/store of the specified type.
3263bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
3264                                           Type *Ty) const {
3265  // The default implementation of this implements a conservative RISCy, r+r and
3266  // r+i addr mode.
3267
3268  // Allows a sign-extended 16-bit immediate field.
3269  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3270    return false;
3271
3272  // No global is ever allowed as a base.
3273  if (AM.BaseGV)
3274    return false;
3275
3276  // Only support r+r,
3277  switch (AM.Scale) {
3278  case 0:  // "r+i" or just "i", depending on HasBaseReg.
3279    break;
3280  case 1:
3281    if (AM.HasBaseReg && AM.BaseOffs)  // "r+r+i" is not allowed.
3282      return false;
3283    // Otherwise we have r+r or r+i.
3284    break;
3285  case 2:
3286    if (AM.HasBaseReg || AM.BaseOffs)  // 2*r+r  or  2*r+i is not allowed.
3287      return false;
3288    // Allow 2*r as r+r.
3289    break;
3290  }
3291
3292  return true;
3293}
3294
3295/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3296/// with the multiplicative inverse of the constant.
3297SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3298                                       SelectionDAG &DAG) const {
3299  ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3300  APInt d = C->getAPIntValue();
3301  assert(d != 0 && "Division by zero!");
3302
3303  // Shift the value upfront if it is even, so the LSB is one.
3304  unsigned ShAmt = d.countTrailingZeros();
3305  if (ShAmt) {
3306    // TODO: For UDIV use SRL instead of SRA.
3307    SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3308    Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3309    d = d.ashr(ShAmt);
3310  }
3311
3312  // Calculate the multiplicative inverse, using Newton's method.
3313  APInt t, xn = d;
3314  while ((t = d*xn) != 1)
3315    xn *= APInt(d.getBitWidth(), 2) - t;
3316
3317  Op2 = DAG.getConstant(xn, Op1.getValueType());
3318  return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3319}
3320
3321/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3322/// return a DAG expression to select that will generate the same value by
3323/// multiplying by a magic number.  See:
3324/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3325SDValue TargetLowering::
3326BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3327          std::vector<SDNode*> *Created) const {
3328  EVT VT = N->getValueType(0);
3329  DebugLoc dl= N->getDebugLoc();
3330
3331  // Check to see if we can do this.
3332  // FIXME: We should be more aggressive here.
3333  if (!isTypeLegal(VT))
3334    return SDValue();
3335
3336  APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3337  APInt::ms magics = d.magic();
3338
3339  // Multiply the numerator (operand 0) by the magic value
3340  // FIXME: We should support doing a MUL in a wider type
3341  SDValue Q;
3342  if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3343                            isOperationLegalOrCustom(ISD::MULHS, VT))
3344    Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
3345                    DAG.getConstant(magics.m, VT));
3346  else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3347                                 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
3348    Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
3349                              N->getOperand(0),
3350                              DAG.getConstant(magics.m, VT)).getNode(), 1);
3351  else
3352    return SDValue();       // No mulhs or equvialent
3353  // If d > 0 and m < 0, add the numerator
3354  if (d.isStrictlyPositive() && magics.m.isNegative()) {
3355    Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
3356    if (Created)
3357      Created->push_back(Q.getNode());
3358  }
3359  // If d < 0 and m > 0, subtract the numerator.
3360  if (d.isNegative() && magics.m.isStrictlyPositive()) {
3361    Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
3362    if (Created)
3363      Created->push_back(Q.getNode());
3364  }
3365  // Shift right algebraic if shift value is nonzero
3366  if (magics.s > 0) {
3367    Q = DAG.getNode(ISD::SRA, dl, VT, Q,
3368                 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3369    if (Created)
3370      Created->push_back(Q.getNode());
3371  }
3372  // Extract the sign bit and add it to the quotient
3373  SDValue T =
3374    DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
3375                                           getShiftAmountTy(Q.getValueType())));
3376  if (Created)
3377    Created->push_back(T.getNode());
3378  return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3379}
3380
3381/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3382/// return a DAG expression to select that will generate the same value by
3383/// multiplying by a magic number.  See:
3384/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3385SDValue TargetLowering::
3386BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3387          std::vector<SDNode*> *Created) const {
3388  EVT VT = N->getValueType(0);
3389  DebugLoc dl = N->getDebugLoc();
3390
3391  // Check to see if we can do this.
3392  // FIXME: We should be more aggressive here.
3393  if (!isTypeLegal(VT))
3394    return SDValue();
3395
3396  // FIXME: We should use a narrower constant when the upper
3397  // bits are known to be zero.
3398  const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3399  APInt::mu magics = N1C.magicu();
3400
3401  SDValue Q = N->getOperand(0);
3402
3403  // If the divisor is even, we can avoid using the expensive fixup by shifting
3404  // the divided value upfront.
3405  if (magics.a != 0 && !N1C[0]) {
3406    unsigned Shift = N1C.countTrailingZeros();
3407    Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3408                    DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3409    if (Created)
3410      Created->push_back(Q.getNode());
3411
3412    // Get magic number for the shifted divisor.
3413    magics = N1C.lshr(Shift).magicu(Shift);
3414    assert(magics.a == 0 && "Should use cheap fixup now");
3415  }
3416
3417  // Multiply the numerator (operand 0) by the magic value
3418  // FIXME: We should support doing a MUL in a wider type
3419  if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3420                            isOperationLegalOrCustom(ISD::MULHU, VT))
3421    Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
3422  else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3423                                 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
3424    Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3425                            DAG.getConstant(magics.m, VT)).getNode(), 1);
3426  else
3427    return SDValue();       // No mulhu or equvialent
3428  if (Created)
3429    Created->push_back(Q.getNode());
3430
3431  if (magics.a == 0) {
3432    assert(magics.s < N1C.getBitWidth() &&
3433           "We shouldn't generate an undefined shift!");
3434    return DAG.getNode(ISD::SRL, dl, VT, Q,
3435                 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3436  } else {
3437    SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3438    if (Created)
3439      Created->push_back(NPQ.getNode());
3440    NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
3441                      DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
3442    if (Created)
3443      Created->push_back(NPQ.getNode());
3444    NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3445    if (Created)
3446      Created->push_back(NPQ.getNode());
3447    return DAG.getNode(ISD::SRL, dl, VT, NPQ,
3448             DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
3449  }
3450}
3451