TargetLowering.cpp revision 3d83c3fd5cbc8b2268bd2ec46879cd4c04b9d32c
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/Target/TargetSubtarget.h" 16#include "llvm/Target/TargetData.h" 17#include "llvm/Target/TargetMachine.h" 18#include "llvm/Target/MRegisterInfo.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/ADT/StringExtras.h" 22#include "llvm/ADT/STLExtras.h" 23#include "llvm/Support/MathExtras.h" 24#include "llvm/Target/TargetAsmInfo.h" 25#include "llvm/CallingConv.h" 26using namespace llvm; 27 28/// InitLibcallNames - Set default libcall names. 29/// 30static void InitLibcallNames(const char **Names) { 31 Names[RTLIB::SHL_I32] = "__ashlsi3"; 32 Names[RTLIB::SHL_I64] = "__ashldi3"; 33 Names[RTLIB::SRL_I32] = "__lshrsi3"; 34 Names[RTLIB::SRL_I64] = "__lshrdi3"; 35 Names[RTLIB::SRA_I32] = "__ashrsi3"; 36 Names[RTLIB::SRA_I64] = "__ashrdi3"; 37 Names[RTLIB::MUL_I32] = "__mulsi3"; 38 Names[RTLIB::MUL_I64] = "__muldi3"; 39 Names[RTLIB::SDIV_I32] = "__divsi3"; 40 Names[RTLIB::SDIV_I64] = "__divdi3"; 41 Names[RTLIB::UDIV_I32] = "__udivsi3"; 42 Names[RTLIB::UDIV_I64] = "__udivdi3"; 43 Names[RTLIB::SREM_I32] = "__modsi3"; 44 Names[RTLIB::SREM_I64] = "__moddi3"; 45 Names[RTLIB::UREM_I32] = "__umodsi3"; 46 Names[RTLIB::UREM_I64] = "__umoddi3"; 47 Names[RTLIB::NEG_I32] = "__negsi2"; 48 Names[RTLIB::NEG_I64] = "__negdi2"; 49 Names[RTLIB::ADD_F32] = "__addsf3"; 50 Names[RTLIB::ADD_F64] = "__adddf3"; 51 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 52 Names[RTLIB::SUB_F32] = "__subsf3"; 53 Names[RTLIB::SUB_F64] = "__subdf3"; 54 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 55 Names[RTLIB::MUL_F32] = "__mulsf3"; 56 Names[RTLIB::MUL_F64] = "__muldf3"; 57 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 58 Names[RTLIB::DIV_F32] = "__divsf3"; 59 Names[RTLIB::DIV_F64] = "__divdf3"; 60 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 61 Names[RTLIB::REM_F32] = "fmodf"; 62 Names[RTLIB::REM_F64] = "fmod"; 63 Names[RTLIB::REM_PPCF128] = "fmodl"; 64 Names[RTLIB::NEG_F32] = "__negsf2"; 65 Names[RTLIB::NEG_F64] = "__negdf2"; 66 Names[RTLIB::POWI_F32] = "__powisf2"; 67 Names[RTLIB::POWI_F64] = "__powidf2"; 68 Names[RTLIB::POWI_F80] = "__powixf2"; 69 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 70 Names[RTLIB::SQRT_F32] = "sqrtf"; 71 Names[RTLIB::SQRT_F64] = "sqrt"; 72 Names[RTLIB::SQRT_F80] = "sqrtl"; 73 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 74 Names[RTLIB::SIN_F32] = "sinf"; 75 Names[RTLIB::SIN_F64] = "sin"; 76 Names[RTLIB::COS_F32] = "cosf"; 77 Names[RTLIB::COS_F64] = "cos"; 78 Names[RTLIB::POW_F32] = "powf"; 79 Names[RTLIB::POW_F64] = "pow"; 80 Names[RTLIB::POW_F80] = "powl"; 81 Names[RTLIB::POW_PPCF128] = "powl"; 82 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 83 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 84 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 85 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 86 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 87 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 88 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 89 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 90 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 91 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 92 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 93 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 94 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 95 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 96 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 97 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 98 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 99 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 100 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 101 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 102 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 103 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 104 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 105 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 106 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 107 Names[RTLIB::OEQ_F32] = "__eqsf2"; 108 Names[RTLIB::OEQ_F64] = "__eqdf2"; 109 Names[RTLIB::UNE_F32] = "__nesf2"; 110 Names[RTLIB::UNE_F64] = "__nedf2"; 111 Names[RTLIB::OGE_F32] = "__gesf2"; 112 Names[RTLIB::OGE_F64] = "__gedf2"; 113 Names[RTLIB::OLT_F32] = "__ltsf2"; 114 Names[RTLIB::OLT_F64] = "__ltdf2"; 115 Names[RTLIB::OLE_F32] = "__lesf2"; 116 Names[RTLIB::OLE_F64] = "__ledf2"; 117 Names[RTLIB::OGT_F32] = "__gtsf2"; 118 Names[RTLIB::OGT_F64] = "__gtdf2"; 119 Names[RTLIB::UO_F32] = "__unordsf2"; 120 Names[RTLIB::UO_F64] = "__unorddf2"; 121 Names[RTLIB::O_F32] = "__unordsf2"; 122 Names[RTLIB::O_F64] = "__unorddf2"; 123} 124 125/// InitCmpLibcallCCs - Set default comparison libcall CC. 126/// 127static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 128 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 129 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 130 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 131 CCs[RTLIB::UNE_F32] = ISD::SETNE; 132 CCs[RTLIB::UNE_F64] = ISD::SETNE; 133 CCs[RTLIB::OGE_F32] = ISD::SETGE; 134 CCs[RTLIB::OGE_F64] = ISD::SETGE; 135 CCs[RTLIB::OLT_F32] = ISD::SETLT; 136 CCs[RTLIB::OLT_F64] = ISD::SETLT; 137 CCs[RTLIB::OLE_F32] = ISD::SETLE; 138 CCs[RTLIB::OLE_F64] = ISD::SETLE; 139 CCs[RTLIB::OGT_F32] = ISD::SETGT; 140 CCs[RTLIB::OGT_F64] = ISD::SETGT; 141 CCs[RTLIB::UO_F32] = ISD::SETNE; 142 CCs[RTLIB::UO_F64] = ISD::SETNE; 143 CCs[RTLIB::O_F32] = ISD::SETEQ; 144 CCs[RTLIB::O_F64] = ISD::SETEQ; 145} 146 147TargetLowering::TargetLowering(TargetMachine &tm) 148 : TM(tm), TD(TM.getTargetData()) { 149 assert(ISD::BUILTIN_OP_END <= 156 && 150 "Fixed size array in TargetLowering is not large enough!"); 151 // All operations default to being supported. 152 memset(OpActions, 0, sizeof(OpActions)); 153 memset(LoadXActions, 0, sizeof(LoadXActions)); 154 memset(&StoreXActions, 0, sizeof(StoreXActions)); 155 memset(&IndexedModeActions, 0, sizeof(IndexedModeActions)); 156 memset(&ConvertActions, 0, sizeof(ConvertActions)); 157 158 // Set all indexed load / store to expand. 159 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 160 for (unsigned IM = (unsigned)ISD::PRE_INC; 161 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 162 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand); 163 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand); 164 } 165 } 166 167 IsLittleEndian = TD->isLittleEndian(); 168 UsesGlobalOffsetTable = false; 169 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType()); 170 ShiftAmtHandling = Undefined; 171 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 172 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 173 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 174 allowUnalignedMemoryAccesses = false; 175 UseUnderscoreSetJmp = false; 176 UseUnderscoreLongJmp = false; 177 SelectIsExpensive = false; 178 IntDivIsCheap = false; 179 Pow2DivIsCheap = false; 180 StackPointerRegisterToSaveRestore = 0; 181 ExceptionPointerRegister = 0; 182 ExceptionSelectorRegister = 0; 183 SetCCResultContents = UndefinedSetCCResult; 184 SchedPreferenceInfo = SchedulingForLatency; 185 JumpBufSize = 0; 186 JumpBufAlignment = 0; 187 IfCvtBlockSizeLimit = 2; 188 189 InitLibcallNames(LibcallRoutineNames); 190 InitCmpLibcallCCs(CmpLibcallCCs); 191 192 // Tell Legalize whether the assembler supports DEBUG_LOC. 193 if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile()) 194 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 195} 196 197TargetLowering::~TargetLowering() {} 198 199 200SDOperand TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) { 201 assert(getSubtarget() && "Subtarget not defined"); 202 SDOperand ChainOp = Op.getOperand(0); 203 SDOperand DestOp = Op.getOperand(1); 204 SDOperand SourceOp = Op.getOperand(2); 205 SDOperand CountOp = Op.getOperand(3); 206 SDOperand AlignOp = Op.getOperand(4); 207 SDOperand AlwaysInlineOp = Op.getOperand(5); 208 209 bool AlwaysInline = (bool)cast<ConstantSDNode>(AlwaysInlineOp)->getValue(); 210 unsigned Align = (unsigned)cast<ConstantSDNode>(AlignOp)->getValue(); 211 if (Align == 0) Align = 1; 212 213 // If size is unknown, call memcpy. 214 ConstantSDNode *I = dyn_cast<ConstantSDNode>(CountOp); 215 if (!I) { 216 assert(!AlwaysInline && "Cannot inline copy of unknown size"); 217 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG); 218 } 219 220 // If not DWORD aligned or if size is more than threshold, then call memcpy. 221 // The libc version is likely to be faster for the following cases. It can 222 // use the address value and run time information about the CPU. 223 // With glibc 2.6.1 on a core 2, coping an array of 100M longs was 30% faster 224 unsigned Size = I->getValue(); 225 if (AlwaysInline || 226 (Size <= getSubtarget()->getMaxInlineSizeThreshold() && 227 (Align & 3) == 0)) 228 return LowerMEMCPYInline(ChainOp, DestOp, SourceOp, Size, Align, DAG); 229 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG); 230} 231 232 233SDOperand TargetLowering::LowerMEMCPYCall(SDOperand Chain, 234 SDOperand Dest, 235 SDOperand Source, 236 SDOperand Count, 237 SelectionDAG &DAG) { 238 MVT::ValueType IntPtr = getPointerTy(); 239 TargetLowering::ArgListTy Args; 240 TargetLowering::ArgListEntry Entry; 241 Entry.Ty = getTargetData()->getIntPtrType(); 242 Entry.Node = Dest; Args.push_back(Entry); 243 Entry.Node = Source; Args.push_back(Entry); 244 Entry.Node = Count; Args.push_back(Entry); 245 std::pair<SDOperand,SDOperand> CallResult = 246 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false, 247 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG); 248 return CallResult.second; 249} 250 251 252/// computeRegisterProperties - Once all of the register classes are added, 253/// this allows us to compute derived properties we expose. 254void TargetLowering::computeRegisterProperties() { 255 assert(MVT::LAST_VALUETYPE <= 32 && 256 "Too many value types for ValueTypeActions to hold!"); 257 258 // Everything defaults to needing one register. 259 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 260 NumRegistersForVT[i] = 1; 261 RegisterTypeForVT[i] = TransformToType[i] = i; 262 } 263 // ...except isVoid, which doesn't need any registers. 264 NumRegistersForVT[MVT::isVoid] = 0; 265 266 // Find the largest integer register class. 267 unsigned LargestIntReg = MVT::i128; 268 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 269 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 270 271 // Every integer value type larger than this largest register takes twice as 272 // many registers to represent as the previous ValueType. 273 for (MVT::ValueType ExpandedReg = LargestIntReg + 1; 274 MVT::isInteger(ExpandedReg); ++ExpandedReg) { 275 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 276 RegisterTypeForVT[ExpandedReg] = LargestIntReg; 277 TransformToType[ExpandedReg] = ExpandedReg - 1; 278 ValueTypeActions.setTypeAction(ExpandedReg, Expand); 279 } 280 281 // Inspect all of the ValueType's smaller than the largest integer 282 // register to see which ones need promotion. 283 MVT::ValueType LegalIntReg = LargestIntReg; 284 for (MVT::ValueType IntReg = LargestIntReg - 1; 285 IntReg >= MVT::i1; --IntReg) { 286 if (isTypeLegal(IntReg)) { 287 LegalIntReg = IntReg; 288 } else { 289 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg; 290 ValueTypeActions.setTypeAction(IntReg, Promote); 291 } 292 } 293 294 // ppcf128 type is really two f64's. 295 if (!isTypeLegal(MVT::ppcf128)) { 296 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 297 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 298 TransformToType[MVT::ppcf128] = MVT::f64; 299 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 300 } 301 302 // Decide how to handle f64. If the target does not have native f64 support, 303 // expand it to i64 and we will be generating soft float library calls. 304 if (!isTypeLegal(MVT::f64)) { 305 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 306 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 307 TransformToType[MVT::f64] = MVT::i64; 308 ValueTypeActions.setTypeAction(MVT::f64, Expand); 309 } 310 311 // Decide how to handle f32. If the target does not have native support for 312 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 313 if (!isTypeLegal(MVT::f32)) { 314 if (isTypeLegal(MVT::f64)) { 315 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 316 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 317 TransformToType[MVT::f32] = MVT::f64; 318 ValueTypeActions.setTypeAction(MVT::f32, Promote); 319 } else { 320 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 321 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 322 TransformToType[MVT::f32] = MVT::i32; 323 ValueTypeActions.setTypeAction(MVT::f32, Expand); 324 } 325 } 326 327 // Loop over all of the vector value types to see which need transformations. 328 for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE; 329 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 330 if (!isTypeLegal(i)) { 331 MVT::ValueType IntermediateVT, RegisterVT; 332 unsigned NumIntermediates; 333 NumRegistersForVT[i] = 334 getVectorTypeBreakdown(i, 335 IntermediateVT, NumIntermediates, 336 RegisterVT); 337 RegisterTypeForVT[i] = RegisterVT; 338 TransformToType[i] = MVT::Other; // this isn't actually used 339 ValueTypeActions.setTypeAction(i, Expand); 340 } 341 } 342} 343 344const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 345 return NULL; 346} 347 348/// getVectorTypeBreakdown - Vector types are broken down into some number of 349/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 350/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 351/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 352/// 353/// This method returns the number of registers needed, and the VT for each 354/// register. It also returns the VT and quantity of the intermediate values 355/// before they are promoted/expanded. 356/// 357unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT, 358 MVT::ValueType &IntermediateVT, 359 unsigned &NumIntermediates, 360 MVT::ValueType &RegisterVT) const { 361 // Figure out the right, legal destination reg to copy into. 362 unsigned NumElts = MVT::getVectorNumElements(VT); 363 MVT::ValueType EltTy = MVT::getVectorElementType(VT); 364 365 unsigned NumVectorRegs = 1; 366 367 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 368 // could break down into LHS/RHS like LegalizeDAG does. 369 if (!isPowerOf2_32(NumElts)) { 370 NumVectorRegs = NumElts; 371 NumElts = 1; 372 } 373 374 // Divide the input until we get to a supported size. This will always 375 // end with a scalar if the target doesn't support vectors. 376 while (NumElts > 1 && 377 !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) { 378 NumElts >>= 1; 379 NumVectorRegs <<= 1; 380 } 381 382 NumIntermediates = NumVectorRegs; 383 384 MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts); 385 if (!isTypeLegal(NewVT)) 386 NewVT = EltTy; 387 IntermediateVT = NewVT; 388 389 MVT::ValueType DestVT = getTypeToTransformTo(NewVT); 390 RegisterVT = DestVT; 391 if (DestVT < NewVT) { 392 // Value is expanded, e.g. i64 -> i16. 393 return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT)); 394 } else { 395 // Otherwise, promotion or legal types use the same number of registers as 396 // the vector decimated to the appropriate level. 397 return NumVectorRegs; 398 } 399 400 return 1; 401} 402 403SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table, 404 SelectionDAG &DAG) const { 405 if (usesGlobalOffsetTable()) 406 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 407 return Table; 408} 409 410//===----------------------------------------------------------------------===// 411// Optimization Methods 412//===----------------------------------------------------------------------===// 413 414/// ShrinkDemandedConstant - Check to see if the specified operand of the 415/// specified instruction is a constant integer. If so, check to see if there 416/// are any bits set in the constant that are not demanded. If so, shrink the 417/// constant and return true. 418bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, 419 uint64_t Demanded) { 420 // FIXME: ISD::SELECT, ISD::SELECT_CC 421 switch(Op.getOpcode()) { 422 default: break; 423 case ISD::AND: 424 case ISD::OR: 425 case ISD::XOR: 426 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 427 if ((~Demanded & C->getValue()) != 0) { 428 MVT::ValueType VT = Op.getValueType(); 429 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 430 DAG.getConstant(Demanded & C->getValue(), 431 VT)); 432 return CombineTo(Op, New); 433 } 434 break; 435 } 436 return false; 437} 438 439/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 440/// DemandedMask bits of the result of Op are ever used downstream. If we can 441/// use this information to simplify Op, create a new simplified DAG node and 442/// return true, returning the original and new nodes in Old and New. Otherwise, 443/// analyze the expression and return a mask of KnownOne and KnownZero bits for 444/// the expression (used to simplify the caller). The KnownZero/One bits may 445/// only be accurate for those bits in the DemandedMask. 446bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 447 uint64_t &KnownZero, 448 uint64_t &KnownOne, 449 TargetLoweringOpt &TLO, 450 unsigned Depth) const { 451 KnownZero = KnownOne = 0; // Don't know anything. 452 453 // The masks are not wide enough to represent this type! Should use APInt. 454 if (Op.getValueType() == MVT::i128) 455 return false; 456 457 // Other users may use these bits. 458 if (!Op.Val->hasOneUse()) { 459 if (Depth != 0) { 460 // If not at the root, Just compute the KnownZero/KnownOne bits to 461 // simplify things downstream. 462 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 463 return false; 464 } 465 // If this is the root being simplified, allow it to have multiple uses, 466 // just set the DemandedMask to all bits. 467 DemandedMask = MVT::getIntVTBitMask(Op.getValueType()); 468 } else if (DemandedMask == 0) { 469 // Not demanding any bits from Op. 470 if (Op.getOpcode() != ISD::UNDEF) 471 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 472 return false; 473 } else if (Depth == 6) { // Limit search depth. 474 return false; 475 } 476 477 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 478 switch (Op.getOpcode()) { 479 case ISD::Constant: 480 // We know all of the bits for a constant! 481 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask; 482 KnownZero = ~KnownOne & DemandedMask; 483 return false; // Don't fall through, will infinitely loop. 484 case ISD::AND: 485 // If the RHS is a constant, check to see if the LHS would be zero without 486 // using the bits from the RHS. Below, we use knowledge about the RHS to 487 // simplify the LHS, here we're using information from the LHS to simplify 488 // the RHS. 489 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 490 uint64_t LHSZero, LHSOne; 491 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), DemandedMask, 492 LHSZero, LHSOne, Depth+1); 493 // If the LHS already has zeros where RHSC does, this and is dead. 494 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask)) 495 return TLO.CombineTo(Op, Op.getOperand(0)); 496 // If any of the set bits in the RHS are known zero on the LHS, shrink 497 // the constant. 498 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask)) 499 return true; 500 } 501 502 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 503 KnownOne, TLO, Depth+1)) 504 return true; 505 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 506 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero, 507 KnownZero2, KnownOne2, TLO, Depth+1)) 508 return true; 509 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 510 511 // If all of the demanded bits are known one on one side, return the other. 512 // These bits cannot contribute to the result of the 'and'. 513 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2)) 514 return TLO.CombineTo(Op, Op.getOperand(0)); 515 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero)) 516 return TLO.CombineTo(Op, Op.getOperand(1)); 517 // If all of the demanded bits in the inputs are known zeros, return zero. 518 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask) 519 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 520 // If the RHS is a constant, see if we can simplify it. 521 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2)) 522 return true; 523 524 // Output known-1 bits are only known if set in both the LHS & RHS. 525 KnownOne &= KnownOne2; 526 // Output known-0 are known to be clear if zero in either the LHS | RHS. 527 KnownZero |= KnownZero2; 528 break; 529 case ISD::OR: 530 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 531 KnownOne, TLO, Depth+1)) 532 return true; 533 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 534 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne, 535 KnownZero2, KnownOne2, TLO, Depth+1)) 536 return true; 537 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 538 539 // If all of the demanded bits are known zero on one side, return the other. 540 // These bits cannot contribute to the result of the 'or'. 541 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2)) 542 return TLO.CombineTo(Op, Op.getOperand(0)); 543 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne)) 544 return TLO.CombineTo(Op, Op.getOperand(1)); 545 // If all of the potentially set bits on one side are known to be set on 546 // the other side, just use the 'other' side. 547 if ((DemandedMask & (~KnownZero) & KnownOne2) == 548 (DemandedMask & (~KnownZero))) 549 return TLO.CombineTo(Op, Op.getOperand(0)); 550 if ((DemandedMask & (~KnownZero2) & KnownOne) == 551 (DemandedMask & (~KnownZero2))) 552 return TLO.CombineTo(Op, Op.getOperand(1)); 553 // If the RHS is a constant, see if we can simplify it. 554 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 555 return true; 556 557 // Output known-0 bits are only known if clear in both the LHS & RHS. 558 KnownZero &= KnownZero2; 559 // Output known-1 are known to be set if set in either the LHS | RHS. 560 KnownOne |= KnownOne2; 561 break; 562 case ISD::XOR: 563 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 564 KnownOne, TLO, Depth+1)) 565 return true; 566 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 567 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2, 568 KnownOne2, TLO, Depth+1)) 569 return true; 570 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 571 572 // If all of the demanded bits are known zero on one side, return the other. 573 // These bits cannot contribute to the result of the 'xor'. 574 if ((DemandedMask & KnownZero) == DemandedMask) 575 return TLO.CombineTo(Op, Op.getOperand(0)); 576 if ((DemandedMask & KnownZero2) == DemandedMask) 577 return TLO.CombineTo(Op, Op.getOperand(1)); 578 579 // If all of the unknown bits are known to be zero on one side or the other 580 // (but not both) turn this into an *inclusive* or. 581 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 582 if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0) 583 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 584 Op.getOperand(0), 585 Op.getOperand(1))); 586 587 // Output known-0 bits are known if clear or set in both the LHS & RHS. 588 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 589 // Output known-1 are known to be set if set in only one of the LHS, RHS. 590 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 591 592 // If all of the demanded bits on one side are known, and all of the set 593 // bits on that side are also known to be set on the other side, turn this 594 // into an AND, as we know the bits will be cleared. 595 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 596 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known 597 if ((KnownOne & KnownOne2) == KnownOne) { 598 MVT::ValueType VT = Op.getValueType(); 599 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT); 600 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 601 ANDC)); 602 } 603 } 604 605 // If the RHS is a constant, see if we can simplify it. 606 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. 607 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 608 return true; 609 610 KnownZero = KnownZeroOut; 611 KnownOne = KnownOneOut; 612 break; 613 case ISD::SETCC: 614 // If we know the result of a setcc has the top bits zero, use this info. 615 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 616 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 617 break; 618 case ISD::SELECT: 619 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero, 620 KnownOne, TLO, Depth+1)) 621 return true; 622 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2, 623 KnownOne2, TLO, Depth+1)) 624 return true; 625 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 626 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 627 628 // If the operands are constants, see if we can simplify them. 629 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 630 return true; 631 632 // Only known if known in both the LHS and RHS. 633 KnownOne &= KnownOne2; 634 KnownZero &= KnownZero2; 635 break; 636 case ISD::SELECT_CC: 637 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero, 638 KnownOne, TLO, Depth+1)) 639 return true; 640 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2, 641 KnownOne2, TLO, Depth+1)) 642 return true; 643 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 644 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 645 646 // If the operands are constants, see if we can simplify them. 647 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 648 return true; 649 650 // Only known if known in both the LHS and RHS. 651 KnownOne &= KnownOne2; 652 KnownZero &= KnownZero2; 653 break; 654 case ISD::SHL: 655 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 656 unsigned ShAmt = SA->getValue(); 657 SDOperand InOp = Op.getOperand(0); 658 659 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 660 // single shift. We can do this if the bottom bits (which are shifted 661 // out) are never demanded. 662 if (InOp.getOpcode() == ISD::SRL && 663 isa<ConstantSDNode>(InOp.getOperand(1))) { 664 if (ShAmt && (DemandedMask & ((1ULL << ShAmt)-1)) == 0) { 665 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 666 unsigned Opc = ISD::SHL; 667 int Diff = ShAmt-C1; 668 if (Diff < 0) { 669 Diff = -Diff; 670 Opc = ISD::SRL; 671 } 672 673 SDOperand NewSA = 674 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 675 MVT::ValueType VT = Op.getValueType(); 676 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 677 InOp.getOperand(0), NewSA)); 678 } 679 } 680 681 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> ShAmt, 682 KnownZero, KnownOne, TLO, Depth+1)) 683 return true; 684 KnownZero <<= SA->getValue(); 685 KnownOne <<= SA->getValue(); 686 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 687 } 688 break; 689 case ISD::SRL: 690 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 691 MVT::ValueType VT = Op.getValueType(); 692 unsigned ShAmt = SA->getValue(); 693 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 694 unsigned VTSize = MVT::getSizeInBits(VT); 695 SDOperand InOp = Op.getOperand(0); 696 697 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 698 // single shift. We can do this if the top bits (which are shifted out) 699 // are never demanded. 700 if (InOp.getOpcode() == ISD::SHL && 701 isa<ConstantSDNode>(InOp.getOperand(1))) { 702 if (ShAmt && (DemandedMask & (~0ULL << (VTSize-ShAmt))) == 0) { 703 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 704 unsigned Opc = ISD::SRL; 705 int Diff = ShAmt-C1; 706 if (Diff < 0) { 707 Diff = -Diff; 708 Opc = ISD::SHL; 709 } 710 711 SDOperand NewSA = 712 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 713 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 714 InOp.getOperand(0), NewSA)); 715 } 716 } 717 718 // Compute the new bits that are at the top now. 719 if (SimplifyDemandedBits(InOp, (DemandedMask << ShAmt) & TypeMask, 720 KnownZero, KnownOne, TLO, Depth+1)) 721 return true; 722 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 723 KnownZero &= TypeMask; 724 KnownOne &= TypeMask; 725 KnownZero >>= ShAmt; 726 KnownOne >>= ShAmt; 727 728 uint64_t HighBits = (1ULL << ShAmt)-1; 729 HighBits <<= VTSize - ShAmt; 730 KnownZero |= HighBits; // High bits known zero. 731 } 732 break; 733 case ISD::SRA: 734 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 735 MVT::ValueType VT = Op.getValueType(); 736 unsigned ShAmt = SA->getValue(); 737 738 // Compute the new bits that are at the top now. 739 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 740 741 uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask; 742 743 // If any of the demanded bits are produced by the sign extension, we also 744 // demand the input sign bit. 745 uint64_t HighBits = (1ULL << ShAmt)-1; 746 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 747 if (HighBits & DemandedMask) 748 InDemandedMask |= MVT::getIntVTSignBit(VT); 749 750 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 751 KnownZero, KnownOne, TLO, Depth+1)) 752 return true; 753 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 754 KnownZero &= TypeMask; 755 KnownOne &= TypeMask; 756 KnownZero >>= ShAmt; 757 KnownOne >>= ShAmt; 758 759 // Handle the sign bits. 760 uint64_t SignBit = MVT::getIntVTSignBit(VT); 761 SignBit >>= ShAmt; // Adjust to where it is now in the mask. 762 763 // If the input sign bit is known to be zero, or if none of the top bits 764 // are demanded, turn this into an unsigned shift right. 765 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) { 766 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 767 Op.getOperand(1))); 768 } else if (KnownOne & SignBit) { // New bits are known one. 769 KnownOne |= HighBits; 770 } 771 } 772 break; 773 case ISD::SIGN_EXTEND_INREG: { 774 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 775 776 // Sign extension. Compute the demanded bits in the result that are not 777 // present in the input. 778 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask; 779 780 // If none of the extended bits are demanded, eliminate the sextinreg. 781 if (NewBits == 0) 782 return TLO.CombineTo(Op, Op.getOperand(0)); 783 784 uint64_t InSignBit = MVT::getIntVTSignBit(EVT); 785 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT); 786 787 // Since the sign extended bits are demanded, we know that the sign 788 // bit is demanded. 789 InputDemandedBits |= InSignBit; 790 791 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 792 KnownZero, KnownOne, TLO, Depth+1)) 793 return true; 794 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 795 796 // If the sign bit of the input is known set or clear, then we know the 797 // top bits of the result. 798 799 // If the input sign bit is known zero, convert this into a zero extension. 800 if (KnownZero & InSignBit) 801 return TLO.CombineTo(Op, 802 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 803 804 if (KnownOne & InSignBit) { // Input sign bit known set 805 KnownOne |= NewBits; 806 KnownZero &= ~NewBits; 807 } else { // Input sign bit unknown 808 KnownZero &= ~NewBits; 809 KnownOne &= ~NewBits; 810 } 811 break; 812 } 813 case ISD::CTTZ: 814 case ISD::CTLZ: 815 case ISD::CTPOP: { 816 MVT::ValueType VT = Op.getValueType(); 817 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 818 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 819 KnownOne = 0; 820 break; 821 } 822 case ISD::LOAD: { 823 if (ISD::isZEXTLoad(Op.Val)) { 824 LoadSDNode *LD = cast<LoadSDNode>(Op); 825 MVT::ValueType VT = LD->getLoadedVT(); 826 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask; 827 } 828 break; 829 } 830 case ISD::ZERO_EXTEND: { 831 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 832 833 // If none of the top bits are demanded, convert this into an any_extend. 834 uint64_t NewBits = (~InMask) & DemandedMask; 835 if (NewBits == 0) 836 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 837 Op.getValueType(), 838 Op.getOperand(0))); 839 840 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 841 KnownZero, KnownOne, TLO, Depth+1)) 842 return true; 843 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 844 KnownZero |= NewBits; 845 break; 846 } 847 case ISD::SIGN_EXTEND: { 848 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 849 uint64_t InMask = MVT::getIntVTBitMask(InVT); 850 uint64_t InSignBit = MVT::getIntVTSignBit(InVT); 851 uint64_t NewBits = (~InMask) & DemandedMask; 852 853 // If none of the top bits are demanded, convert this into an any_extend. 854 if (NewBits == 0) 855 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 856 Op.getOperand(0))); 857 858 // Since some of the sign extended bits are demanded, we know that the sign 859 // bit is demanded. 860 uint64_t InDemandedBits = DemandedMask & InMask; 861 InDemandedBits |= InSignBit; 862 863 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 864 KnownOne, TLO, Depth+1)) 865 return true; 866 867 // If the sign bit is known zero, convert this to a zero extend. 868 if (KnownZero & InSignBit) 869 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 870 Op.getValueType(), 871 Op.getOperand(0))); 872 873 // If the sign bit is known one, the top bits match. 874 if (KnownOne & InSignBit) { 875 KnownOne |= NewBits; 876 KnownZero &= ~NewBits; 877 } else { // Otherwise, top bits aren't known. 878 KnownOne &= ~NewBits; 879 KnownZero &= ~NewBits; 880 } 881 break; 882 } 883 case ISD::ANY_EXTEND: { 884 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 885 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 886 KnownZero, KnownOne, TLO, Depth+1)) 887 return true; 888 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 889 break; 890 } 891 case ISD::TRUNCATE: { 892 // Simplify the input, using demanded bit information, and compute the known 893 // zero/one bits live out. 894 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, 895 KnownZero, KnownOne, TLO, Depth+1)) 896 return true; 897 898 // If the input is only used by this truncate, see if we can shrink it based 899 // on the known demanded bits. 900 if (Op.getOperand(0).Val->hasOneUse()) { 901 SDOperand In = Op.getOperand(0); 902 switch (In.getOpcode()) { 903 default: break; 904 case ISD::SRL: 905 // Shrink SRL by a constant if none of the high bits shifted in are 906 // demanded. 907 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 908 uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType()); 909 HighBits &= ~MVT::getIntVTBitMask(Op.getValueType()); 910 HighBits >>= ShAmt->getValue(); 911 912 if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) && 913 (DemandedMask & HighBits) == 0) { 914 // None of the shifted in bits are needed. Add a truncate of the 915 // shift input, then shift it. 916 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 917 Op.getValueType(), 918 In.getOperand(0)); 919 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), 920 NewTrunc, In.getOperand(1))); 921 } 922 } 923 break; 924 } 925 } 926 927 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 928 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType()); 929 KnownZero &= OutMask; 930 KnownOne &= OutMask; 931 break; 932 } 933 case ISD::AssertZext: { 934 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 935 uint64_t InMask = MVT::getIntVTBitMask(VT); 936 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 937 KnownZero, KnownOne, TLO, Depth+1)) 938 return true; 939 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 940 KnownZero |= ~InMask & DemandedMask; 941 break; 942 } 943 case ISD::ADD: 944 case ISD::SUB: 945 case ISD::INTRINSIC_WO_CHAIN: 946 case ISD::INTRINSIC_W_CHAIN: 947 case ISD::INTRINSIC_VOID: 948 // Just use ComputeMaskedBits to compute output bits. 949 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 950 break; 951 } 952 953 // If we know the value of all of the demanded bits, return this as a 954 // constant. 955 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) 956 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 957 958 return false; 959} 960 961/// computeMaskedBitsForTargetNode - Determine which of the bits specified 962/// in Mask are known to be either zero or one and return them in the 963/// KnownZero/KnownOne bitsets. 964void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 965 uint64_t Mask, 966 uint64_t &KnownZero, 967 uint64_t &KnownOne, 968 const SelectionDAG &DAG, 969 unsigned Depth) const { 970 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 971 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 972 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 973 Op.getOpcode() == ISD::INTRINSIC_VOID) && 974 "Should use MaskedValueIsZero if you don't know whether Op" 975 " is a target node!"); 976 KnownZero = 0; 977 KnownOne = 0; 978} 979 980/// ComputeNumSignBitsForTargetNode - This method can be implemented by 981/// targets that want to expose additional information about sign bits to the 982/// DAG Combiner. 983unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op, 984 unsigned Depth) const { 985 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 986 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 987 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 988 Op.getOpcode() == ISD::INTRINSIC_VOID) && 989 "Should use ComputeNumSignBits if you don't know whether Op" 990 " is a target node!"); 991 return 1; 992} 993 994 995/// SimplifySetCC - Try to simplify a setcc built with the specified operands 996/// and cc. If it is unable to simplify it, return a null SDOperand. 997SDOperand 998TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 999 ISD::CondCode Cond, bool foldBooleans, 1000 DAGCombinerInfo &DCI) const { 1001 SelectionDAG &DAG = DCI.DAG; 1002 1003 // These setcc operations always fold. 1004 switch (Cond) { 1005 default: break; 1006 case ISD::SETFALSE: 1007 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1008 case ISD::SETTRUE: 1009 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1010 } 1011 1012 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 1013 uint64_t C1 = N1C->getValue(); 1014 if (isa<ConstantSDNode>(N0.Val)) { 1015 return DAG.FoldSetCC(VT, N0, N1, Cond); 1016 } else { 1017 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1018 // equality comparison, then we're just comparing whether X itself is 1019 // zero. 1020 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1021 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1022 N0.getOperand(1).getOpcode() == ISD::Constant) { 1023 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1024 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1025 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) { 1026 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1027 // (srl (ctlz x), 5) == 0 -> X != 0 1028 // (srl (ctlz x), 5) != 1 -> X != 0 1029 Cond = ISD::SETNE; 1030 } else { 1031 // (srl (ctlz x), 5) != 0 -> X == 0 1032 // (srl (ctlz x), 5) == 1 -> X == 0 1033 Cond = ISD::SETEQ; 1034 } 1035 SDOperand Zero = DAG.getConstant(0, N0.getValueType()); 1036 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 1037 Zero, Cond); 1038 } 1039 } 1040 1041 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1042 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1043 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 1044 1045 // If the comparison constant has bits in the upper part, the 1046 // zero-extended value could never match. 1047 if (C1 & (~0ULL << InSize)) { 1048 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 1049 switch (Cond) { 1050 case ISD::SETUGT: 1051 case ISD::SETUGE: 1052 case ISD::SETEQ: return DAG.getConstant(0, VT); 1053 case ISD::SETULT: 1054 case ISD::SETULE: 1055 case ISD::SETNE: return DAG.getConstant(1, VT); 1056 case ISD::SETGT: 1057 case ISD::SETGE: 1058 // True if the sign bit of C1 is set. 1059 return DAG.getConstant((C1 & (1ULL << (VSize-1))) != 0, VT); 1060 case ISD::SETLT: 1061 case ISD::SETLE: 1062 // True if the sign bit of C1 isn't set. 1063 return DAG.getConstant((C1 & (1ULL << (VSize-1))) == 0, VT); 1064 default: 1065 break; 1066 } 1067 } 1068 1069 // Otherwise, we can perform the comparison with the low bits. 1070 switch (Cond) { 1071 case ISD::SETEQ: 1072 case ISD::SETNE: 1073 case ISD::SETUGT: 1074 case ISD::SETUGE: 1075 case ISD::SETULT: 1076 case ISD::SETULE: 1077 return DAG.getSetCC(VT, N0.getOperand(0), 1078 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 1079 Cond); 1080 default: 1081 break; // todo, be more careful with signed comparisons 1082 } 1083 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1084 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1085 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1086 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 1087 MVT::ValueType ExtDstTy = N0.getValueType(); 1088 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 1089 1090 // If the extended part has any inconsistent bits, it cannot ever 1091 // compare equal. In other words, they have to be all ones or all 1092 // zeros. 1093 uint64_t ExtBits = 1094 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 1095 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1096 return DAG.getConstant(Cond == ISD::SETNE, VT); 1097 1098 SDOperand ZextOp; 1099 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 1100 if (Op0Ty == ExtSrcTy) { 1101 ZextOp = N0.getOperand(0); 1102 } else { 1103 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 1104 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1105 DAG.getConstant(Imm, Op0Ty)); 1106 } 1107 if (!DCI.isCalledByLegalizer()) 1108 DCI.AddToWorklist(ZextOp.Val); 1109 // Otherwise, make this a use of a zext. 1110 return DAG.getSetCC(VT, ZextOp, 1111 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 1112 ExtDstTy), 1113 Cond); 1114 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 1115 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1116 1117 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1118 if (N0.getOpcode() == ISD::SETCC) { 1119 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1); 1120 if (TrueWhenTrue) 1121 return N0; 1122 1123 // Invert the condition. 1124 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1125 CC = ISD::getSetCCInverse(CC, 1126 MVT::isInteger(N0.getOperand(0).getValueType())); 1127 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); 1128 } 1129 1130 if ((N0.getOpcode() == ISD::XOR || 1131 (N0.getOpcode() == ISD::AND && 1132 N0.getOperand(0).getOpcode() == ISD::XOR && 1133 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1134 isa<ConstantSDNode>(N0.getOperand(1)) && 1135 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 1136 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1137 // can only do this if the top bits are known zero. 1138 if (DAG.MaskedValueIsZero(N0, 1139 MVT::getIntVTBitMask(N0.getValueType())-1)){ 1140 // Okay, get the un-inverted input value. 1141 SDOperand Val; 1142 if (N0.getOpcode() == ISD::XOR) 1143 Val = N0.getOperand(0); 1144 else { 1145 assert(N0.getOpcode() == ISD::AND && 1146 N0.getOperand(0).getOpcode() == ISD::XOR); 1147 // ((X^1)&1)^1 -> X & 1 1148 Val = DAG.getNode(ISD::AND, N0.getValueType(), 1149 N0.getOperand(0).getOperand(0), 1150 N0.getOperand(1)); 1151 } 1152 return DAG.getSetCC(VT, Val, N1, 1153 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1154 } 1155 } 1156 } 1157 1158 uint64_t MinVal, MaxVal; 1159 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 1160 if (ISD::isSignedIntSetCC(Cond)) { 1161 MinVal = 1ULL << (OperandBitSize-1); 1162 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 1163 MaxVal = ~0ULL >> (65-OperandBitSize); 1164 else 1165 MaxVal = 0; 1166 } else { 1167 MinVal = 0; 1168 MaxVal = ~0ULL >> (64-OperandBitSize); 1169 } 1170 1171 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1172 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1173 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1174 --C1; // X >= C0 --> X > (C0-1) 1175 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 1176 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1177 } 1178 1179 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1180 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1181 ++C1; // X <= C0 --> X < (C0+1) 1182 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 1183 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1184 } 1185 1186 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1187 return DAG.getConstant(0, VT); // X < MIN --> false 1188 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1189 return DAG.getConstant(1, VT); // X >= MIN --> true 1190 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1191 return DAG.getConstant(0, VT); // X > MAX --> false 1192 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1193 return DAG.getConstant(1, VT); // X <= MAX --> true 1194 1195 // Canonicalize setgt X, Min --> setne X, Min 1196 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1197 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1198 // Canonicalize setlt X, Max --> setne X, Max 1199 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1200 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1201 1202 // If we have setult X, 1, turn it into seteq X, 0 1203 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1204 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 1205 ISD::SETEQ); 1206 // If we have setugt X, Max-1, turn it into seteq X, Max 1207 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1208 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 1209 ISD::SETEQ); 1210 1211 // If we have "setcc X, C0", check to see if we can shrink the immediate 1212 // by changing cc. 1213 1214 // SETUGT X, SINTMAX -> SETLT X, 0 1215 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 1216 C1 == (~0ULL >> (65-OperandBitSize))) 1217 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 1218 ISD::SETLT); 1219 1220 // FIXME: Implement the rest of these. 1221 1222 // Fold bit comparisons when we can. 1223 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1224 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1225 if (ConstantSDNode *AndRHS = 1226 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1227 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1228 // Perform the xform if the AND RHS is a single bit. 1229 if (isPowerOf2_64(AndRHS->getValue())) { 1230 return DAG.getNode(ISD::SRL, VT, N0, 1231 DAG.getConstant(Log2_64(AndRHS->getValue()), 1232 getShiftAmountTy())); 1233 } 1234 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 1235 // (X & 8) == 8 --> (X & 8) >> 3 1236 // Perform the xform if C1 is a single bit. 1237 if (isPowerOf2_64(C1)) { 1238 return DAG.getNode(ISD::SRL, VT, N0, 1239 DAG.getConstant(Log2_64(C1), getShiftAmountTy())); 1240 } 1241 } 1242 } 1243 } 1244 } else if (isa<ConstantSDNode>(N0.Val)) { 1245 // Ensure that the constant occurs on the RHS. 1246 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1247 } 1248 1249 if (isa<ConstantFPSDNode>(N0.Val)) { 1250 // Constant fold or commute setcc. 1251 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond); 1252 if (O.Val) return O; 1253 } 1254 1255 if (N0 == N1) { 1256 // We can always fold X == X for integer setcc's. 1257 if (MVT::isInteger(N0.getValueType())) 1258 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1259 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1260 if (UOF == 2) // FP operators that are undefined on NaNs. 1261 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1262 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1263 return DAG.getConstant(UOF, VT); 1264 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1265 // if it is not already. 1266 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1267 if (NewCond != Cond) 1268 return DAG.getSetCC(VT, N0, N1, NewCond); 1269 } 1270 1271 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1272 MVT::isInteger(N0.getValueType())) { 1273 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1274 N0.getOpcode() == ISD::XOR) { 1275 // Simplify (X+Y) == (X+Z) --> Y == Z 1276 if (N0.getOpcode() == N1.getOpcode()) { 1277 if (N0.getOperand(0) == N1.getOperand(0)) 1278 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 1279 if (N0.getOperand(1) == N1.getOperand(1)) 1280 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 1281 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1282 // If X op Y == Y op X, try other combinations. 1283 if (N0.getOperand(0) == N1.getOperand(1)) 1284 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 1285 if (N0.getOperand(1) == N1.getOperand(0)) 1286 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 1287 } 1288 } 1289 1290 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1291 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1292 // Turn (X+C1) == C2 --> X == C2-C1 1293 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 1294 return DAG.getSetCC(VT, N0.getOperand(0), 1295 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 1296 N0.getValueType()), Cond); 1297 } 1298 1299 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1300 if (N0.getOpcode() == ISD::XOR) 1301 // If we know that all of the inverted bits are zero, don't bother 1302 // performing the inversion. 1303 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 1304 return DAG.getSetCC(VT, N0.getOperand(0), 1305 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 1306 N0.getValueType()), Cond); 1307 } 1308 1309 // Turn (C1-X) == C2 --> X == C1-C2 1310 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1311 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 1312 return DAG.getSetCC(VT, N0.getOperand(1), 1313 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 1314 N0.getValueType()), Cond); 1315 } 1316 } 1317 } 1318 1319 // Simplify (X+Z) == X --> Z == 0 1320 if (N0.getOperand(0) == N1) 1321 return DAG.getSetCC(VT, N0.getOperand(1), 1322 DAG.getConstant(0, N0.getValueType()), Cond); 1323 if (N0.getOperand(1) == N1) { 1324 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1325 return DAG.getSetCC(VT, N0.getOperand(0), 1326 DAG.getConstant(0, N0.getValueType()), Cond); 1327 else if (N0.Val->hasOneUse()) { 1328 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1329 // (Z-X) == X --> Z == X<<1 1330 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 1331 N1, 1332 DAG.getConstant(1, getShiftAmountTy())); 1333 if (!DCI.isCalledByLegalizer()) 1334 DCI.AddToWorklist(SH.Val); 1335 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 1336 } 1337 } 1338 } 1339 1340 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1341 N1.getOpcode() == ISD::XOR) { 1342 // Simplify X == (X+Z) --> Z == 0 1343 if (N1.getOperand(0) == N0) { 1344 return DAG.getSetCC(VT, N1.getOperand(1), 1345 DAG.getConstant(0, N1.getValueType()), Cond); 1346 } else if (N1.getOperand(1) == N0) { 1347 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1348 return DAG.getSetCC(VT, N1.getOperand(0), 1349 DAG.getConstant(0, N1.getValueType()), Cond); 1350 } else if (N1.Val->hasOneUse()) { 1351 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1352 // X == (Z-X) --> X<<1 == Z 1353 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 1354 DAG.getConstant(1, getShiftAmountTy())); 1355 if (!DCI.isCalledByLegalizer()) 1356 DCI.AddToWorklist(SH.Val); 1357 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 1358 } 1359 } 1360 } 1361 } 1362 1363 // Fold away ALL boolean setcc's. 1364 SDOperand Temp; 1365 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1366 switch (Cond) { 1367 default: assert(0 && "Unknown integer setcc!"); 1368 case ISD::SETEQ: // X == Y -> (X^Y)^1 1369 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1370 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 1371 if (!DCI.isCalledByLegalizer()) 1372 DCI.AddToWorklist(Temp.Val); 1373 break; 1374 case ISD::SETNE: // X != Y --> (X^Y) 1375 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1376 break; 1377 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 1378 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 1379 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1380 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 1381 if (!DCI.isCalledByLegalizer()) 1382 DCI.AddToWorklist(Temp.Val); 1383 break; 1384 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 1385 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 1386 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1387 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 1388 if (!DCI.isCalledByLegalizer()) 1389 DCI.AddToWorklist(Temp.Val); 1390 break; 1391 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 1392 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 1393 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1394 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 1395 if (!DCI.isCalledByLegalizer()) 1396 DCI.AddToWorklist(Temp.Val); 1397 break; 1398 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 1399 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 1400 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1401 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 1402 break; 1403 } 1404 if (VT != MVT::i1) { 1405 if (!DCI.isCalledByLegalizer()) 1406 DCI.AddToWorklist(N0.Val); 1407 // FIXME: If running after legalize, we probably can't do this. 1408 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1409 } 1410 return N0; 1411 } 1412 1413 // Could not fold it. 1414 return SDOperand(); 1415} 1416 1417SDOperand TargetLowering:: 1418PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1419 // Default implementation: no optimization. 1420 return SDOperand(); 1421} 1422 1423//===----------------------------------------------------------------------===// 1424// Inline Assembler Implementation Methods 1425//===----------------------------------------------------------------------===// 1426 1427TargetLowering::ConstraintType 1428TargetLowering::getConstraintType(const std::string &Constraint) const { 1429 // FIXME: lots more standard ones to handle. 1430 if (Constraint.size() == 1) { 1431 switch (Constraint[0]) { 1432 default: break; 1433 case 'r': return C_RegisterClass; 1434 case 'm': // memory 1435 case 'o': // offsetable 1436 case 'V': // not offsetable 1437 return C_Memory; 1438 case 'i': // Simple Integer or Relocatable Constant 1439 case 'n': // Simple Integer 1440 case 's': // Relocatable Constant 1441 case 'X': // Allow ANY value. 1442 case 'I': // Target registers. 1443 case 'J': 1444 case 'K': 1445 case 'L': 1446 case 'M': 1447 case 'N': 1448 case 'O': 1449 case 'P': 1450 return C_Other; 1451 } 1452 } 1453 1454 if (Constraint.size() > 1 && Constraint[0] == '{' && 1455 Constraint[Constraint.size()-1] == '}') 1456 return C_Register; 1457 return C_Unknown; 1458} 1459 1460/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1461/// vector. If it is invalid, don't add anything to Ops. 1462void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op, 1463 char ConstraintLetter, 1464 std::vector<SDOperand> &Ops, 1465 SelectionDAG &DAG) { 1466 switch (ConstraintLetter) { 1467 default: break; 1468 case 'X': // Allows any operand; labels (basic block) use this. 1469 if (Op.getOpcode() == ISD::BasicBlock) { 1470 Ops.push_back(Op); 1471 return; 1472 } 1473 // fall through 1474 case 'i': // Simple Integer or Relocatable Constant 1475 case 'n': // Simple Integer 1476 case 's': { // Relocatable Constant 1477 // These operands are interested in values of the form (GV+C), where C may 1478 // be folded in as an offset of GV, or it may be explicitly added. Also, it 1479 // is possible and fine if either GV or C are missing. 1480 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1481 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 1482 1483 // If we have "(add GV, C)", pull out GV/C 1484 if (Op.getOpcode() == ISD::ADD) { 1485 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1486 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 1487 if (C == 0 || GA == 0) { 1488 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 1489 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 1490 } 1491 if (C == 0 || GA == 0) 1492 C = 0, GA = 0; 1493 } 1494 1495 // If we find a valid operand, map to the TargetXXX version so that the 1496 // value itself doesn't get selected. 1497 if (GA) { // Either &GV or &GV+C 1498 if (ConstraintLetter != 'n') { 1499 int64_t Offs = GA->getOffset(); 1500 if (C) Offs += C->getValue(); 1501 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 1502 Op.getValueType(), Offs)); 1503 return; 1504 } 1505 } 1506 if (C) { // just C, no GV. 1507 // Simple constants are not allowed for 's'. 1508 if (ConstraintLetter != 's') { 1509 Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType())); 1510 return; 1511 } 1512 } 1513 break; 1514 } 1515 } 1516} 1517 1518std::vector<unsigned> TargetLowering:: 1519getRegClassForInlineAsmConstraint(const std::string &Constraint, 1520 MVT::ValueType VT) const { 1521 return std::vector<unsigned>(); 1522} 1523 1524 1525std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 1526getRegForInlineAsmConstraint(const std::string &Constraint, 1527 MVT::ValueType VT) const { 1528 if (Constraint[0] != '{') 1529 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1530 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 1531 1532 // Remove the braces from around the name. 1533 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 1534 1535 // Figure out which register class contains this reg. 1536 const MRegisterInfo *RI = TM.getRegisterInfo(); 1537 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 1538 E = RI->regclass_end(); RCI != E; ++RCI) { 1539 const TargetRegisterClass *RC = *RCI; 1540 1541 // If none of the the value types for this register class are valid, we 1542 // can't use it. For example, 64-bit reg classes on 32-bit targets. 1543 bool isLegal = false; 1544 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1545 I != E; ++I) { 1546 if (isTypeLegal(*I)) { 1547 isLegal = true; 1548 break; 1549 } 1550 } 1551 1552 if (!isLegal) continue; 1553 1554 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 1555 I != E; ++I) { 1556 if (StringsEqualNoCase(RegName, RI->get(*I).Name)) 1557 return std::make_pair(*I, RC); 1558 } 1559 } 1560 1561 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1562} 1563 1564//===----------------------------------------------------------------------===// 1565// Loop Strength Reduction hooks 1566//===----------------------------------------------------------------------===// 1567 1568/// isLegalAddressingMode - Return true if the addressing mode represented 1569/// by AM is legal for this target, for a load/store of the specified type. 1570bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 1571 const Type *Ty) const { 1572 // The default implementation of this implements a conservative RISCy, r+r and 1573 // r+i addr mode. 1574 1575 // Allows a sign-extended 16-bit immediate field. 1576 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1577 return false; 1578 1579 // No global is ever allowed as a base. 1580 if (AM.BaseGV) 1581 return false; 1582 1583 // Only support r+r, 1584 switch (AM.Scale) { 1585 case 0: // "r+i" or just "i", depending on HasBaseReg. 1586 break; 1587 case 1: 1588 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1589 return false; 1590 // Otherwise we have r+r or r+i. 1591 break; 1592 case 2: 1593 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1594 return false; 1595 // Allow 2*r as r+r. 1596 break; 1597 } 1598 1599 return true; 1600} 1601 1602// Magic for divide replacement 1603 1604struct ms { 1605 int64_t m; // magic number 1606 int64_t s; // shift amount 1607}; 1608 1609struct mu { 1610 uint64_t m; // magic number 1611 int64_t a; // add indicator 1612 int64_t s; // shift amount 1613}; 1614 1615/// magic - calculate the magic numbers required to codegen an integer sdiv as 1616/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1617/// or -1. 1618static ms magic32(int32_t d) { 1619 int32_t p; 1620 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 1621 const uint32_t two31 = 0x80000000U; 1622 struct ms mag; 1623 1624 ad = abs(d); 1625 t = two31 + ((uint32_t)d >> 31); 1626 anc = t - 1 - t%ad; // absolute value of nc 1627 p = 31; // initialize p 1628 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 1629 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1630 q2 = two31/ad; // initialize q2 = 2p/abs(d) 1631 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1632 do { 1633 p = p + 1; 1634 q1 = 2*q1; // update q1 = 2p/abs(nc) 1635 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1636 if (r1 >= anc) { // must be unsigned comparison 1637 q1 = q1 + 1; 1638 r1 = r1 - anc; 1639 } 1640 q2 = 2*q2; // update q2 = 2p/abs(d) 1641 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1642 if (r2 >= ad) { // must be unsigned comparison 1643 q2 = q2 + 1; 1644 r2 = r2 - ad; 1645 } 1646 delta = ad - r2; 1647 } while (q1 < delta || (q1 == delta && r1 == 0)); 1648 1649 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 1650 if (d < 0) mag.m = -mag.m; // resulting magic number 1651 mag.s = p - 32; // resulting shift 1652 return mag; 1653} 1654 1655/// magicu - calculate the magic numbers required to codegen an integer udiv as 1656/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1657static mu magicu32(uint32_t d) { 1658 int32_t p; 1659 uint32_t nc, delta, q1, r1, q2, r2; 1660 struct mu magu; 1661 magu.a = 0; // initialize "add" indicator 1662 nc = - 1 - (-d)%d; 1663 p = 31; // initialize p 1664 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 1665 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 1666 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 1667 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 1668 do { 1669 p = p + 1; 1670 if (r1 >= nc - r1 ) { 1671 q1 = 2*q1 + 1; // update q1 1672 r1 = 2*r1 - nc; // update r1 1673 } 1674 else { 1675 q1 = 2*q1; // update q1 1676 r1 = 2*r1; // update r1 1677 } 1678 if (r2 + 1 >= d - r2) { 1679 if (q2 >= 0x7FFFFFFF) magu.a = 1; 1680 q2 = 2*q2 + 1; // update q2 1681 r2 = 2*r2 + 1 - d; // update r2 1682 } 1683 else { 1684 if (q2 >= 0x80000000) magu.a = 1; 1685 q2 = 2*q2; // update q2 1686 r2 = 2*r2 + 1; // update r2 1687 } 1688 delta = d - 1 - r2; 1689 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 1690 magu.m = q2 + 1; // resulting magic number 1691 magu.s = p - 32; // resulting shift 1692 return magu; 1693} 1694 1695/// magic - calculate the magic numbers required to codegen an integer sdiv as 1696/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1697/// or -1. 1698static ms magic64(int64_t d) { 1699 int64_t p; 1700 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 1701 const uint64_t two63 = 9223372036854775808ULL; // 2^63 1702 struct ms mag; 1703 1704 ad = d >= 0 ? d : -d; 1705 t = two63 + ((uint64_t)d >> 63); 1706 anc = t - 1 - t%ad; // absolute value of nc 1707 p = 63; // initialize p 1708 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 1709 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1710 q2 = two63/ad; // initialize q2 = 2p/abs(d) 1711 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1712 do { 1713 p = p + 1; 1714 q1 = 2*q1; // update q1 = 2p/abs(nc) 1715 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1716 if (r1 >= anc) { // must be unsigned comparison 1717 q1 = q1 + 1; 1718 r1 = r1 - anc; 1719 } 1720 q2 = 2*q2; // update q2 = 2p/abs(d) 1721 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1722 if (r2 >= ad) { // must be unsigned comparison 1723 q2 = q2 + 1; 1724 r2 = r2 - ad; 1725 } 1726 delta = ad - r2; 1727 } while (q1 < delta || (q1 == delta && r1 == 0)); 1728 1729 mag.m = q2 + 1; 1730 if (d < 0) mag.m = -mag.m; // resulting magic number 1731 mag.s = p - 64; // resulting shift 1732 return mag; 1733} 1734 1735/// magicu - calculate the magic numbers required to codegen an integer udiv as 1736/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1737static mu magicu64(uint64_t d) 1738{ 1739 int64_t p; 1740 uint64_t nc, delta, q1, r1, q2, r2; 1741 struct mu magu; 1742 magu.a = 0; // initialize "add" indicator 1743 nc = - 1 - (-d)%d; 1744 p = 63; // initialize p 1745 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 1746 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 1747 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 1748 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 1749 do { 1750 p = p + 1; 1751 if (r1 >= nc - r1 ) { 1752 q1 = 2*q1 + 1; // update q1 1753 r1 = 2*r1 - nc; // update r1 1754 } 1755 else { 1756 q1 = 2*q1; // update q1 1757 r1 = 2*r1; // update r1 1758 } 1759 if (r2 + 1 >= d - r2) { 1760 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 1761 q2 = 2*q2 + 1; // update q2 1762 r2 = 2*r2 + 1 - d; // update r2 1763 } 1764 else { 1765 if (q2 >= 0x8000000000000000ull) magu.a = 1; 1766 q2 = 2*q2; // update q2 1767 r2 = 2*r2 + 1; // update r2 1768 } 1769 delta = d - 1 - r2; 1770 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0))); 1771 magu.m = q2 + 1; // resulting magic number 1772 magu.s = p - 64; // resulting shift 1773 return magu; 1774} 1775 1776/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 1777/// return a DAG expression to select that will generate the same value by 1778/// multiplying by a magic number. See: 1779/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 1780SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 1781 std::vector<SDNode*>* Created) const { 1782 MVT::ValueType VT = N->getValueType(0); 1783 1784 // Check to see if we can do this. 1785 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 1786 return SDOperand(); // BuildSDIV only operates on i32 or i64 1787 1788 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 1789 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 1790 1791 // Multiply the numerator (operand 0) by the magic value 1792 SDOperand Q; 1793 if (isOperationLegal(ISD::MULHS, VT)) 1794 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 1795 DAG.getConstant(magics.m, VT)); 1796 else if (isOperationLegal(ISD::SMUL_LOHI, VT)) 1797 Q = SDOperand(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), 1798 N->getOperand(0), 1799 DAG.getConstant(magics.m, VT)).Val, 1); 1800 else 1801 return SDOperand(); // No mulhs or equvialent 1802 // If d > 0 and m < 0, add the numerator 1803 if (d > 0 && magics.m < 0) { 1804 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 1805 if (Created) 1806 Created->push_back(Q.Val); 1807 } 1808 // If d < 0 and m > 0, subtract the numerator. 1809 if (d < 0 && magics.m > 0) { 1810 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 1811 if (Created) 1812 Created->push_back(Q.Val); 1813 } 1814 // Shift right algebraic if shift value is nonzero 1815 if (magics.s > 0) { 1816 Q = DAG.getNode(ISD::SRA, VT, Q, 1817 DAG.getConstant(magics.s, getShiftAmountTy())); 1818 if (Created) 1819 Created->push_back(Q.Val); 1820 } 1821 // Extract the sign bit and add it to the quotient 1822 SDOperand T = 1823 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 1824 getShiftAmountTy())); 1825 if (Created) 1826 Created->push_back(T.Val); 1827 return DAG.getNode(ISD::ADD, VT, Q, T); 1828} 1829 1830/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 1831/// return a DAG expression to select that will generate the same value by 1832/// multiplying by a magic number. See: 1833/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 1834SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 1835 std::vector<SDNode*>* Created) const { 1836 MVT::ValueType VT = N->getValueType(0); 1837 1838 // Check to see if we can do this. 1839 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 1840 return SDOperand(); // BuildUDIV only operates on i32 or i64 1841 1842 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 1843 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 1844 1845 // Multiply the numerator (operand 0) by the magic value 1846 SDOperand Q; 1847 if (isOperationLegal(ISD::MULHU, VT)) 1848 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 1849 DAG.getConstant(magics.m, VT)); 1850 else if (isOperationLegal(ISD::UMUL_LOHI, VT)) 1851 Q = SDOperand(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), 1852 N->getOperand(0), 1853 DAG.getConstant(magics.m, VT)).Val, 1); 1854 else 1855 return SDOperand(); // No mulhu or equvialent 1856 if (Created) 1857 Created->push_back(Q.Val); 1858 1859 if (magics.a == 0) { 1860 return DAG.getNode(ISD::SRL, VT, Q, 1861 DAG.getConstant(magics.s, getShiftAmountTy())); 1862 } else { 1863 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 1864 if (Created) 1865 Created->push_back(NPQ.Val); 1866 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 1867 DAG.getConstant(1, getShiftAmountTy())); 1868 if (Created) 1869 Created->push_back(NPQ.Val); 1870 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 1871 if (Created) 1872 Created->push_back(NPQ.Val); 1873 return DAG.getNode(ISD::SRL, VT, NPQ, 1874 DAG.getConstant(magics.s-1, getShiftAmountTy())); 1875 } 1876} 1877