TargetLowering.cpp revision 4068673bbea0b6b3716494f7c291d0ebc43aa8e5
15d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 25d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// 35d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// The LLVM Compiler Infrastructure 45d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// 5c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch// This file is distributed under the University of Illinois Open Source 6c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch// License. See LICENSE.TXT for details. 7c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch// 8c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch//===----------------------------------------------------------------------===// 9a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)// 10a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)// This implements the TargetLowering class. 115d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// 125d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)//===----------------------------------------------------------------------===// 135d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 145d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/Target/TargetAsmInfo.h" 155d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/Target/TargetLowering.h" 165d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/Target/TargetSubtarget.h" 175d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/Target/TargetData.h" 185d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/Target/TargetMachine.h" 195d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/Target/TargetRegisterInfo.h" 205d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/GlobalVariable.h" 215c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu#include "llvm/DerivedTypes.h" 225d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/CodeGen/MachineFrameInfo.h" 23c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch#include "llvm/CodeGen/SelectionDAG.h" 245d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/ADT/StringExtras.h" 255d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/ADT/STLExtras.h" 265d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/Support/MathExtras.h" 275d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)using namespace llvm; 285d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 295d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)/// InitLibcallNames - Set default libcall names. 305d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)/// 315d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)static void InitLibcallNames(const char **Names) { 325d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SHL_I32] = "__ashlsi3"; 335d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SHL_I64] = "__ashldi3"; 345d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SHL_I128] = "__ashlti3"; 35c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch Names[RTLIB::SRL_I32] = "__lshrsi3"; 365d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SRL_I64] = "__lshrdi3"; 375d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SRL_I128] = "__lshrti3"; 385d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SRA_I32] = "__ashrsi3"; 395d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SRA_I64] = "__ashrdi3"; 405d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SRA_I128] = "__ashrti3"; 415d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::MUL_I32] = "__mulsi3"; 425d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::MUL_I64] = "__muldi3"; 435d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::MUL_I128] = "__multi3"; 445d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SDIV_I32] = "__divsi3"; 455d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SDIV_I64] = "__divdi3"; 465d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SDIV_I128] = "__divti3"; 475d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::UDIV_I32] = "__udivsi3"; 485d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::UDIV_I64] = "__udivdi3"; 495d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::UDIV_I128] = "__udivti3"; 505d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SREM_I32] = "__modsi3"; 515d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SREM_I64] = "__moddi3"; 525d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SREM_I128] = "__modti3"; 535d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::UREM_I32] = "__umodsi3"; 545d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::UREM_I64] = "__umoddi3"; 555d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::UREM_I128] = "__umodti3"; 565d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::NEG_I32] = "__negsi2"; 575d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::NEG_I64] = "__negdi2"; 585d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::ADD_F32] = "__addsf3"; 595d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::ADD_F64] = "__adddf3"; 605d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::ADD_F80] = "__addxf3"; 615d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 625d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SUB_F32] = "__subsf3"; 63a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::SUB_F64] = "__subdf3"; 645d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SUB_F80] = "__subxf3"; 655d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 665d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::MUL_F32] = "__mulsf3"; 675d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::MUL_F64] = "__muldf3"; 68a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::MUL_F80] = "__mulxf3"; 69a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 705d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::DIV_F32] = "__divsf3"; 715d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::DIV_F64] = "__divdf3"; 725d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::DIV_F80] = "__divxf3"; 735d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 74a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::REM_F32] = "fmodf"; 755d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::REM_F64] = "fmod"; 76c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch Names[RTLIB::REM_F80] = "fmodl"; 775d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::REM_PPCF128] = "fmodl"; 78a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::POWI_F32] = "__powisf2"; 79a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::POWI_F64] = "__powidf2"; 80a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::POWI_F80] = "__powixf2"; 815d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::POWI_PPCF128] = "__powitf2"; 82a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::SQRT_F32] = "sqrtf"; 83a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::SQRT_F64] = "sqrt"; 845d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SQRT_F80] = "sqrtl"; 855d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 865d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::LOG_F32] = "logf"; 875d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::LOG_F64] = "log"; 885d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::LOG_F80] = "logl"; 89a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::LOG_PPCF128] = "logl"; 90a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::LOG2_F32] = "log2f"; 91a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::LOG2_F64] = "log2"; 92a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::LOG2_F80] = "log2l"; 935d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::LOG2_PPCF128] = "log2l"; 945d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::LOG10_F32] = "log10f"; 955d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::LOG10_F64] = "log10"; 96a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::LOG10_F80] = "log10l"; 975d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::LOG10_PPCF128] = "log10l"; 985d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::EXP_F32] = "expf"; 99a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::EXP_F64] = "exp"; 100a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::EXP_F80] = "expl"; 101a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::EXP_PPCF128] = "expl"; 102a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::EXP2_F32] = "exp2f"; 103a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::EXP2_F64] = "exp2"; 104a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::EXP2_F80] = "exp2l"; 105a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::EXP2_PPCF128] = "exp2l"; 1065d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SIN_F32] = "sinf"; 1075d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SIN_F64] = "sin"; 1085d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SIN_F80] = "sinl"; 1095d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::SIN_PPCF128] = "sinl"; 1105d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::COS_F32] = "cosf"; 1115d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::COS_F64] = "cos"; 1125d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::COS_F80] = "cosl"; 1135d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::COS_PPCF128] = "cosl"; 1145d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::POW_F32] = "powf"; 1155d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::POW_F64] = "pow"; 1165d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::POW_F80] = "powl"; 1175d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::POW_PPCF128] = "powl"; 1185d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::CEIL_F32] = "ceilf"; 119a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::CEIL_F64] = "ceil"; 1205d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::CEIL_F80] = "ceill"; 1215d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::CEIL_PPCF128] = "ceill"; 1225d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::TRUNC_F32] = "truncf"; 123a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::TRUNC_F64] = "trunc"; 1245d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::TRUNC_F80] = "truncl"; 125a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::TRUNC_PPCF128] = "truncl"; 126a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::RINT_F32] = "rintf"; 127a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::RINT_F64] = "rint"; 128a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::RINT_F80] = "rintl"; 1295d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::RINT_PPCF128] = "rintl"; 130c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 131c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 132c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 133c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 1345d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FLOOR_F32] = "floorf"; 1355d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FLOOR_F64] = "floor"; 1365d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FLOOR_F80] = "floorl"; 1375d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FLOOR_PPCF128] = "floorl"; 1385d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 1395d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 1405d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 1415d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 1425d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 1435d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 1445d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 1455d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 1465d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 1475d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 1485d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 1495d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 1505d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 1515d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 1525d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 1535d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 1545d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 155c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 156c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 1575d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 158c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 1595d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 160a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 161a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 162a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 163a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 164a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 165a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 166a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 167a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 168a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 169a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 170a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 171c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 172a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 173a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 174a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 175a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 176a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 177a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 178a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 179a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 180a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 181a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 182a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 183a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 184a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 185a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 186c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 187c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 188a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 1895d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 1905d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 1915d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 1925d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::OEQ_F32] = "__eqsf2"; 1935d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::OEQ_F64] = "__eqdf2"; 1945d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::UNE_F32] = "__nesf2"; 1955d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::UNE_F64] = "__nedf2"; 1965d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::OGE_F32] = "__gesf2"; 1975d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::OGE_F64] = "__gedf2"; 1985d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::OLT_F32] = "__ltsf2"; 1995d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::OLT_F64] = "__ltdf2"; 2005d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::OLE_F32] = "__lesf2"; 2015d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::OLE_F64] = "__ledf2"; 2025d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::OGT_F32] = "__gtsf2"; 2035d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::OGT_F64] = "__gtdf2"; 2045d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::UO_F32] = "__unordsf2"; 2055d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::UO_F64] = "__unorddf2"; 2065d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::O_F32] = "__unordsf2"; 2075d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Names[RTLIB::O_F64] = "__unorddf2"; 2085d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)} 2095d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 2105d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)/// getFPEXT - Return the FPEXT_*_* value for the given types, or 2115d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)/// UNKNOWN_LIBCALL if there is none. 212c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen MurdochRTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) { 213c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch if (OpVT == MVT::f32) { 2145d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (RetVT == MVT::f64) 215c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return FPEXT_F32_F64; 216c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch } 217c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return UNKNOWN_LIBCALL; 2185d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)} 2195d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 2205d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)/// getFPROUND - Return the FPROUND_*_* value for the given types, or 2215d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)/// UNKNOWN_LIBCALL if there is none. 2225d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) { 2235d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (RetVT == MVT::f32) { 2245d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (OpVT == MVT::f64) 225a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return FPROUND_F64_F32; 226a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (OpVT == MVT::f80) 227a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return FPROUND_F80_F32; 228a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (OpVT == MVT::ppcf128) 229a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return FPROUND_PPCF128_F32; 230a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) } else if (RetVT == MVT::f64) { 231a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (OpVT == MVT::f80) 232c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return FPROUND_F80_F64; 233c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch if (OpVT == MVT::ppcf128) 234c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return FPROUND_PPCF128_F64; 235c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch } 236c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return UNKNOWN_LIBCALL; 237a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)} 238a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) 239a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 240c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch/// UNKNOWN_LIBCALL if there is none. 241c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen MurdochRTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) { 242a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (OpVT == MVT::f32) { 243c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch if (RetVT == MVT::i32) 244c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return FPTOSINT_F32_I32; 245c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch if (RetVT == MVT::i64) 246c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return FPTOSINT_F32_I64; 247a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (RetVT == MVT::i128) 248a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return FPTOSINT_F32_I128; 249a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) } else if (OpVT == MVT::f64) { 250c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch if (RetVT == MVT::i32) 251a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return FPTOSINT_F64_I32; 252a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (RetVT == MVT::i64) 253a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return FPTOSINT_F64_I64; 254a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (RetVT == MVT::i128) 255c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return FPTOSINT_F64_I128; 256c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch } else if (OpVT == MVT::f80) { 257a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (RetVT == MVT::i32) 258a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return FPTOSINT_F80_I32; 259c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch if (RetVT == MVT::i64) 260c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return FPTOSINT_F80_I64; 261a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (RetVT == MVT::i128) 262c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return FPTOSINT_F80_I128; 263c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch } else if (OpVT == MVT::ppcf128) { 264c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch if (RetVT == MVT::i32) 265c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return FPTOSINT_PPCF128_I32; 266a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (RetVT == MVT::i64) 267a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return FPTOSINT_PPCF128_I64; 268a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (RetVT == MVT::i128) 269c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return FPTOSINT_PPCF128_I128; 270a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) } 271a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return UNKNOWN_LIBCALL; 2725d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)} 2735d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 2745d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 2755d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)/// UNKNOWN_LIBCALL if there is none. 276a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) { 2775d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (OpVT == MVT::f32) { 278a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (RetVT == MVT::i32) 279a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return FPTOUINT_F32_I32; 2805d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (RetVT == MVT::i64) 281c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return FPTOUINT_F32_I64; 2825d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (RetVT == MVT::i128) 2835d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return FPTOUINT_F32_I128; 2845d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } else if (OpVT == MVT::f64) { 2855d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (RetVT == MVT::i32) 2865d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return FPTOUINT_F64_I32; 2875d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (RetVT == MVT::i64) 2885d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return FPTOUINT_F64_I64; 2895d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (RetVT == MVT::i128) 2905d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return FPTOUINT_F64_I128; 2915d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } else if (OpVT == MVT::f80) { 2925d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (RetVT == MVT::i32) 2935d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return FPTOUINT_F80_I32; 2945d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (RetVT == MVT::i64) 295a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return FPTOUINT_F80_I64; 2965d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (RetVT == MVT::i128) 297c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return FPTOUINT_F80_I128; 2985d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } else if (OpVT == MVT::ppcf128) { 299a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (RetVT == MVT::i32) 3005d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return FPTOUINT_PPCF128_I32; 301c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch if (RetVT == MVT::i64) 302c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return FPTOUINT_PPCF128_I64; 303c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch if (RetVT == MVT::i128) 304c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return FPTOUINT_PPCF128_I128; 305c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch } 306c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return UNKNOWN_LIBCALL; 3075d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)} 308c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch 309c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 310c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch/// UNKNOWN_LIBCALL if there is none. 311c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen MurdochRTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) { 3125d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (OpVT == MVT::i32) { 3135d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (RetVT == MVT::f32) 3145d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return SINTTOFP_I32_F32; 3155d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) else if (RetVT == MVT::f64) 3165d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return SINTTOFP_I32_F64; 3175d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) else if (RetVT == MVT::f80) 3185d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return SINTTOFP_I32_F80; 3195d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) else if (RetVT == MVT::ppcf128) 3205d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return SINTTOFP_I32_PPCF128; 3215d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } else if (OpVT == MVT::i64) { 3225d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (RetVT == MVT::f32) 3235d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return SINTTOFP_I64_F32; 3245d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) else if (RetVT == MVT::f64) 3255d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return SINTTOFP_I64_F64; 3265d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) else if (RetVT == MVT::f80) 3275d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return SINTTOFP_I64_F80; 328a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) else if (RetVT == MVT::ppcf128) 3295d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return SINTTOFP_I64_PPCF128; 3305d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } else if (OpVT == MVT::i128) { 3315d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (RetVT == MVT::f32) 3325d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return SINTTOFP_I128_F32; 3335d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) else if (RetVT == MVT::f64) 3345d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return SINTTOFP_I128_F64; 3355d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) else if (RetVT == MVT::f80) 3365d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return SINTTOFP_I128_F80; 3375d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) else if (RetVT == MVT::ppcf128) 3385d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return SINTTOFP_I128_PPCF128; 3395d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 3405d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return UNKNOWN_LIBCALL; 3415d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)} 3425d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 3435d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 3445d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)/// UNKNOWN_LIBCALL if there is none. 345a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) { 346a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (OpVT == MVT::i32) { 347a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (RetVT == MVT::f32) 348a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return UINTTOFP_I32_F32; 349a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) else if (RetVT == MVT::f64) 350a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return UINTTOFP_I32_F64; 351a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) else if (RetVT == MVT::f80) 352a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return UINTTOFP_I32_F80; 3535d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) else if (RetVT == MVT::ppcf128) 354a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return UINTTOFP_I32_PPCF128; 355c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch } else if (OpVT == MVT::i64) { 356c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch if (RetVT == MVT::f32) 357c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return UINTTOFP_I64_F32; 358c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch else if (RetVT == MVT::f64) 359a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return UINTTOFP_I64_F64; 360a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) else if (RetVT == MVT::f80) 361c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return UINTTOFP_I64_F80; 362c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch else if (RetVT == MVT::ppcf128) 363c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch return UINTTOFP_I64_PPCF128; 364c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch } else if (OpVT == MVT::i128) { 3655d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (RetVT == MVT::f32) 3665d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return UINTTOFP_I128_F32; 3675d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) else if (RetVT == MVT::f64) 3685d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return UINTTOFP_I128_F64; 3695d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) else if (RetVT == MVT::f80) 370a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return UINTTOFP_I128_F80; 371a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) else if (RetVT == MVT::ppcf128) 372a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return UINTTOFP_I128_PPCF128; 3735d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 3745d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return UNKNOWN_LIBCALL; 3755d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)} 376c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch 377c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch/// InitCmpLibcallCCs - Set default comparison libcall CC. 378c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch/// 3795d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 3805d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 3815d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 3825d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 383c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch CCs[RTLIB::UNE_F32] = ISD::SETNE; 384c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch CCs[RTLIB::UNE_F64] = ISD::SETNE; 385c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch CCs[RTLIB::OGE_F32] = ISD::SETGE; 386c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch CCs[RTLIB::OGE_F64] = ISD::SETGE; 387c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch CCs[RTLIB::OLT_F32] = ISD::SETLT; 388c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch CCs[RTLIB::OLT_F64] = ISD::SETLT; 389c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch CCs[RTLIB::OLE_F32] = ISD::SETLE; 3905d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) CCs[RTLIB::OLE_F64] = ISD::SETLE; 3915d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) CCs[RTLIB::OGT_F32] = ISD::SETGT; 392a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) CCs[RTLIB::OGT_F64] = ISD::SETGT; 3935d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) CCs[RTLIB::UO_F32] = ISD::SETNE; 3945d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) CCs[RTLIB::UO_F64] = ISD::SETNE; 3955d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) CCs[RTLIB::O_F32] = ISD::SETEQ; 3965d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) CCs[RTLIB::O_F64] = ISD::SETEQ; 3975d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)} 398c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch 3995d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)TargetLowering::TargetLowering(TargetMachine &tm) 400c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch : TM(tm), TD(TM.getTargetData()) { 4015d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) assert(ISD::BUILTIN_OP_END <= OpActionsCapacity && 402c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch "Fixed size array in TargetLowering is not large enough!"); 403a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) // All operations default to being supported. 404c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch memset(OpActions, 0, sizeof(OpActions)); 405a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) memset(LoadXActions, 0, sizeof(LoadXActions)); 406a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 407a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 408a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) memset(ConvertActions, 0, sizeof(ConvertActions)); 409a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) 410a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) // Set default actions for various operations. 4115d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 412a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) // Default all indexed load / store to expand. 413a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) for (unsigned IM = (unsigned)ISD::PRE_INC; 414a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 415a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 416a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 417a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) } 418a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) 419a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) // These operations default to expand. 420a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 421a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) } 422a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) 423a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) // Most targets ignore the @llvm.prefetch intrinsic. 424a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 425a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) 4265d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // ConstantFP nodes default to expand. Targets can either change this to 4275d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 4285d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // to optimize expansions for certain constants. 4295d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 4305d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 4315d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 4325d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 4335d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // These library functions default to expand. 4345d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) setOperationAction(ISD::FLOG , MVT::f64, Expand); 4355d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) setOperationAction(ISD::FLOG2, MVT::f64, Expand); 4365d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) setOperationAction(ISD::FLOG10,MVT::f64, Expand); 4375d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) setOperationAction(ISD::FEXP , MVT::f64, Expand); 438a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) setOperationAction(ISD::FEXP2, MVT::f64, Expand); 4395d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) setOperationAction(ISD::FLOG , MVT::f32, Expand); 4405d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) setOperationAction(ISD::FLOG2, MVT::f32, Expand); 441a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) setOperationAction(ISD::FLOG10,MVT::f32, Expand); 442a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) setOperationAction(ISD::FEXP , MVT::f32, Expand); 4435d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) setOperationAction(ISD::FEXP2, MVT::f32, Expand); 4445d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 445a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) // Default ISD::TRAP to expand (which turns it into abort). 446c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch setOperationAction(ISD::TRAP, MVT::Other, Expand); 447c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch 448c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch IsLittleEndian = TD->isLittleEndian(); 449a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) UsesGlobalOffsetTable = false; 450a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()); 451a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) ShiftAmtHandling = Undefined; 452a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 453a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 454c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 455c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch allowUnalignedMemoryAccesses = false; 456c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch UseUnderscoreSetJmp = false; 457a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) UseUnderscoreLongJmp = false; 458a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) SelectIsExpensive = false; 459c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch IntDivIsCheap = false; 460c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch Pow2DivIsCheap = false; 461c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch StackPointerRegisterToSaveRestore = 0; 462a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) ExceptionPointerRegister = 0; 463c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch ExceptionSelectorRegister = 0; 464c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch SetCCResultContents = UndefinedSetCCResult; 465c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch SchedPreferenceInfo = SchedulingForLatency; 466a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) JumpBufSize = 0; 4675d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) JumpBufAlignment = 0; 4685d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) IfCvtBlockSizeLimit = 2; 4695d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) IfCvtDupBlockSizeLimit = 0; 4705d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) PrefLoopAlignment = 0; 4715d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 4725d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) InitLibcallNames(LibcallRoutineNames); 4735d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) InitCmpLibcallCCs(CmpLibcallCCs); 474a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) 475a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) // Tell Legalize whether the assembler supports DEBUG_LOC. 476a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile()) 477a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 478a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)} 479a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) 480a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)TargetLowering::~TargetLowering() {} 4815d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 4825d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)/// computeRegisterProperties - Once all of the register classes are added, 4835d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)/// this allows us to compute derived properties we expose. 4845d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)void TargetLowering::computeRegisterProperties() { 4855d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) assert(MVT::LAST_VALUETYPE <= 32 && 4865d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) "Too many value types for ValueTypeActions to hold!"); 4875d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 4885d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // Everything defaults to needing one register. 4895d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 4905d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) NumRegistersForVT[i] = 1; 4915d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 4925d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 4935d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // ...except isVoid, which doesn't need any registers. 4945d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) NumRegistersForVT[MVT::isVoid] = 0; 495 496 // Find the largest integer register class. 497 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 498 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 499 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 500 501 // Every integer value type larger than this largest register takes twice as 502 // many registers to represent as the previous ValueType. 503 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 504 MVT EVT = (MVT::SimpleValueType)ExpandedReg; 505 if (!EVT.isInteger()) 506 break; 507 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 508 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 509 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 510 ValueTypeActions.setTypeAction(EVT, Expand); 511 } 512 513 // Inspect all of the ValueType's smaller than the largest integer 514 // register to see which ones need promotion. 515 unsigned LegalIntReg = LargestIntReg; 516 for (unsigned IntReg = LargestIntReg - 1; 517 IntReg >= (unsigned)MVT::i1; --IntReg) { 518 MVT IVT = (MVT::SimpleValueType)IntReg; 519 if (isTypeLegal(IVT)) { 520 LegalIntReg = IntReg; 521 } else { 522 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 523 (MVT::SimpleValueType)LegalIntReg; 524 ValueTypeActions.setTypeAction(IVT, Promote); 525 } 526 } 527 528 // ppcf128 type is really two f64's. 529 if (!isTypeLegal(MVT::ppcf128)) { 530 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 531 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 532 TransformToType[MVT::ppcf128] = MVT::f64; 533 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 534 } 535 536 // Decide how to handle f64. If the target does not have native f64 support, 537 // expand it to i64 and we will be generating soft float library calls. 538 if (!isTypeLegal(MVT::f64)) { 539 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 540 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 541 TransformToType[MVT::f64] = MVT::i64; 542 ValueTypeActions.setTypeAction(MVT::f64, Expand); 543 } 544 545 // Decide how to handle f32. If the target does not have native support for 546 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 547 if (!isTypeLegal(MVT::f32)) { 548 if (isTypeLegal(MVT::f64)) { 549 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 550 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 551 TransformToType[MVT::f32] = MVT::f64; 552 ValueTypeActions.setTypeAction(MVT::f32, Promote); 553 } else { 554 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 555 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 556 TransformToType[MVT::f32] = MVT::i32; 557 ValueTypeActions.setTypeAction(MVT::f32, Expand); 558 } 559 } 560 561 // Loop over all of the vector value types to see which need transformations. 562 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 563 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 564 MVT VT = (MVT::SimpleValueType)i; 565 if (!isTypeLegal(VT)) { 566 MVT IntermediateVT, RegisterVT; 567 unsigned NumIntermediates; 568 NumRegistersForVT[i] = 569 getVectorTypeBreakdown(VT, 570 IntermediateVT, NumIntermediates, 571 RegisterVT); 572 RegisterTypeForVT[i] = RegisterVT; 573 TransformToType[i] = MVT::Other; // this isn't actually used 574 ValueTypeActions.setTypeAction(VT, Expand); 575 } 576 } 577} 578 579const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 580 return NULL; 581} 582 583 584MVT TargetLowering::getSetCCResultType(const SDValue &) const { 585 return getValueType(TD->getIntPtrType()); 586} 587 588 589/// getVectorTypeBreakdown - Vector types are broken down into some number of 590/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 591/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 592/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 593/// 594/// This method returns the number of registers needed, and the VT for each 595/// register. It also returns the VT and quantity of the intermediate values 596/// before they are promoted/expanded. 597/// 598unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, 599 MVT &IntermediateVT, 600 unsigned &NumIntermediates, 601 MVT &RegisterVT) const { 602 // Figure out the right, legal destination reg to copy into. 603 unsigned NumElts = VT.getVectorNumElements(); 604 MVT EltTy = VT.getVectorElementType(); 605 606 unsigned NumVectorRegs = 1; 607 608 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 609 // could break down into LHS/RHS like LegalizeDAG does. 610 if (!isPowerOf2_32(NumElts)) { 611 NumVectorRegs = NumElts; 612 NumElts = 1; 613 } 614 615 // Divide the input until we get to a supported size. This will always 616 // end with a scalar if the target doesn't support vectors. 617 while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 618 NumElts >>= 1; 619 NumVectorRegs <<= 1; 620 } 621 622 NumIntermediates = NumVectorRegs; 623 624 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 625 if (!isTypeLegal(NewVT)) 626 NewVT = EltTy; 627 IntermediateVT = NewVT; 628 629 MVT DestVT = getTypeToTransformTo(NewVT); 630 RegisterVT = DestVT; 631 if (DestVT.bitsLT(NewVT)) { 632 // Value is expanded, e.g. i64 -> i16. 633 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 634 } else { 635 // Otherwise, promotion or legal types use the same number of registers as 636 // the vector decimated to the appropriate level. 637 return NumVectorRegs; 638 } 639 640 return 1; 641} 642 643/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 644/// function arguments in the caller parameter area. This is the actual 645/// alignment, not its logarithm. 646unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 647 return TD->getCallFrameTypeAlignment(Ty); 648} 649 650SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 651 SelectionDAG &DAG) const { 652 if (usesGlobalOffsetTable()) 653 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 654 return Table; 655} 656 657//===----------------------------------------------------------------------===// 658// Optimization Methods 659//===----------------------------------------------------------------------===// 660 661/// ShrinkDemandedConstant - Check to see if the specified operand of the 662/// specified instruction is a constant integer. If so, check to see if there 663/// are any bits set in the constant that are not demanded. If so, shrink the 664/// constant and return true. 665bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 666 const APInt &Demanded) { 667 // FIXME: ISD::SELECT, ISD::SELECT_CC 668 switch(Op.getOpcode()) { 669 default: break; 670 case ISD::AND: 671 case ISD::OR: 672 case ISD::XOR: 673 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 674 if (C->getAPIntValue().intersects(~Demanded)) { 675 MVT VT = Op.getValueType(); 676 SDValue New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 677 DAG.getConstant(Demanded & 678 C->getAPIntValue(), 679 VT)); 680 return CombineTo(Op, New); 681 } 682 break; 683 } 684 return false; 685} 686 687/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 688/// DemandedMask bits of the result of Op are ever used downstream. If we can 689/// use this information to simplify Op, create a new simplified DAG node and 690/// return true, returning the original and new nodes in Old and New. Otherwise, 691/// analyze the expression and return a mask of KnownOne and KnownZero bits for 692/// the expression (used to simplify the caller). The KnownZero/One bits may 693/// only be accurate for those bits in the DemandedMask. 694bool TargetLowering::SimplifyDemandedBits(SDValue Op, 695 const APInt &DemandedMask, 696 APInt &KnownZero, 697 APInt &KnownOne, 698 TargetLoweringOpt &TLO, 699 unsigned Depth) const { 700 unsigned BitWidth = DemandedMask.getBitWidth(); 701 assert(Op.getValueSizeInBits() == BitWidth && 702 "Mask size mismatches value type size!"); 703 APInt NewMask = DemandedMask; 704 705 // Don't know anything. 706 KnownZero = KnownOne = APInt(BitWidth, 0); 707 708 // Other users may use these bits. 709 if (!Op.getNode()->hasOneUse()) { 710 if (Depth != 0) { 711 // If not at the root, Just compute the KnownZero/KnownOne bits to 712 // simplify things downstream. 713 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 714 return false; 715 } 716 // If this is the root being simplified, allow it to have multiple uses, 717 // just set the NewMask to all bits. 718 NewMask = APInt::getAllOnesValue(BitWidth); 719 } else if (DemandedMask == 0) { 720 // Not demanding any bits from Op. 721 if (Op.getOpcode() != ISD::UNDEF) 722 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 723 return false; 724 } else if (Depth == 6) { // Limit search depth. 725 return false; 726 } 727 728 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 729 switch (Op.getOpcode()) { 730 case ISD::Constant: 731 // We know all of the bits for a constant! 732 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 733 KnownZero = ~KnownOne & NewMask; 734 return false; // Don't fall through, will infinitely loop. 735 case ISD::AND: 736 // If the RHS is a constant, check to see if the LHS would be zero without 737 // using the bits from the RHS. Below, we use knowledge about the RHS to 738 // simplify the LHS, here we're using information from the LHS to simplify 739 // the RHS. 740 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 741 APInt LHSZero, LHSOne; 742 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 743 LHSZero, LHSOne, Depth+1); 744 // If the LHS already has zeros where RHSC does, this and is dead. 745 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 746 return TLO.CombineTo(Op, Op.getOperand(0)); 747 // If any of the set bits in the RHS are known zero on the LHS, shrink 748 // the constant. 749 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 750 return true; 751 } 752 753 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 754 KnownOne, TLO, Depth+1)) 755 return true; 756 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 757 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 758 KnownZero2, KnownOne2, TLO, Depth+1)) 759 return true; 760 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 761 762 // If all of the demanded bits are known one on one side, return the other. 763 // These bits cannot contribute to the result of the 'and'. 764 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 765 return TLO.CombineTo(Op, Op.getOperand(0)); 766 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 767 return TLO.CombineTo(Op, Op.getOperand(1)); 768 // If all of the demanded bits in the inputs are known zeros, return zero. 769 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 770 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 771 // If the RHS is a constant, see if we can simplify it. 772 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 773 return true; 774 775 // Output known-1 bits are only known if set in both the LHS & RHS. 776 KnownOne &= KnownOne2; 777 // Output known-0 are known to be clear if zero in either the LHS | RHS. 778 KnownZero |= KnownZero2; 779 break; 780 case ISD::OR: 781 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 782 KnownOne, TLO, Depth+1)) 783 return true; 784 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 785 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 786 KnownZero2, KnownOne2, TLO, Depth+1)) 787 return true; 788 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 789 790 // If all of the demanded bits are known zero on one side, return the other. 791 // These bits cannot contribute to the result of the 'or'. 792 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 793 return TLO.CombineTo(Op, Op.getOperand(0)); 794 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 795 return TLO.CombineTo(Op, Op.getOperand(1)); 796 // If all of the potentially set bits on one side are known to be set on 797 // the other side, just use the 'other' side. 798 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 799 return TLO.CombineTo(Op, Op.getOperand(0)); 800 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 801 return TLO.CombineTo(Op, Op.getOperand(1)); 802 // If the RHS is a constant, see if we can simplify it. 803 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 804 return true; 805 806 // Output known-0 bits are only known if clear in both the LHS & RHS. 807 KnownZero &= KnownZero2; 808 // Output known-1 are known to be set if set in either the LHS | RHS. 809 KnownOne |= KnownOne2; 810 break; 811 case ISD::XOR: 812 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 813 KnownOne, TLO, Depth+1)) 814 return true; 815 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 816 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 817 KnownOne2, TLO, Depth+1)) 818 return true; 819 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 820 821 // If all of the demanded bits are known zero on one side, return the other. 822 // These bits cannot contribute to the result of the 'xor'. 823 if ((KnownZero & NewMask) == NewMask) 824 return TLO.CombineTo(Op, Op.getOperand(0)); 825 if ((KnownZero2 & NewMask) == NewMask) 826 return TLO.CombineTo(Op, Op.getOperand(1)); 827 828 // If all of the unknown bits are known to be zero on one side or the other 829 // (but not both) turn this into an *inclusive* or. 830 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 831 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 832 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 833 Op.getOperand(0), 834 Op.getOperand(1))); 835 836 // Output known-0 bits are known if clear or set in both the LHS & RHS. 837 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 838 // Output known-1 are known to be set if set in only one of the LHS, RHS. 839 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 840 841 // If all of the demanded bits on one side are known, and all of the set 842 // bits on that side are also known to be set on the other side, turn this 843 // into an AND, as we know the bits will be cleared. 844 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 845 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 846 if ((KnownOne & KnownOne2) == KnownOne) { 847 MVT VT = Op.getValueType(); 848 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 849 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 850 ANDC)); 851 } 852 } 853 854 // If the RHS is a constant, see if we can simplify it. 855 // for XOR, we prefer to force bits to 1 if they will make a -1. 856 // if we can't force bits, try to shrink constant 857 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 858 APInt Expanded = C->getAPIntValue() | (~NewMask); 859 // if we can expand it to have all bits set, do it 860 if (Expanded.isAllOnesValue()) { 861 if (Expanded != C->getAPIntValue()) { 862 MVT VT = Op.getValueType(); 863 SDValue New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 864 TLO.DAG.getConstant(Expanded, VT)); 865 return TLO.CombineTo(Op, New); 866 } 867 // if it already has all the bits set, nothing to change 868 // but don't shrink either! 869 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 870 return true; 871 } 872 } 873 874 KnownZero = KnownZeroOut; 875 KnownOne = KnownOneOut; 876 break; 877 case ISD::SELECT: 878 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 879 KnownOne, TLO, Depth+1)) 880 return true; 881 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 882 KnownOne2, TLO, Depth+1)) 883 return true; 884 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 885 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 886 887 // If the operands are constants, see if we can simplify them. 888 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 889 return true; 890 891 // Only known if known in both the LHS and RHS. 892 KnownOne &= KnownOne2; 893 KnownZero &= KnownZero2; 894 break; 895 case ISD::SELECT_CC: 896 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 897 KnownOne, TLO, Depth+1)) 898 return true; 899 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 900 KnownOne2, TLO, Depth+1)) 901 return true; 902 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 903 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 904 905 // If the operands are constants, see if we can simplify them. 906 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 907 return true; 908 909 // Only known if known in both the LHS and RHS. 910 KnownOne &= KnownOne2; 911 KnownZero &= KnownZero2; 912 break; 913 case ISD::SHL: 914 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 915 unsigned ShAmt = SA->getZExtValue(); 916 SDValue InOp = Op.getOperand(0); 917 918 // If the shift count is an invalid immediate, don't do anything. 919 if (ShAmt >= BitWidth) 920 break; 921 922 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 923 // single shift. We can do this if the bottom bits (which are shifted 924 // out) are never demanded. 925 if (InOp.getOpcode() == ISD::SRL && 926 isa<ConstantSDNode>(InOp.getOperand(1))) { 927 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 928 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 929 unsigned Opc = ISD::SHL; 930 int Diff = ShAmt-C1; 931 if (Diff < 0) { 932 Diff = -Diff; 933 Opc = ISD::SRL; 934 } 935 936 SDValue NewSA = 937 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 938 MVT VT = Op.getValueType(); 939 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 940 InOp.getOperand(0), NewSA)); 941 } 942 } 943 944 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 945 KnownZero, KnownOne, TLO, Depth+1)) 946 return true; 947 KnownZero <<= SA->getZExtValue(); 948 KnownOne <<= SA->getZExtValue(); 949 // low bits known zero. 950 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 951 } 952 break; 953 case ISD::SRL: 954 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 955 MVT VT = Op.getValueType(); 956 unsigned ShAmt = SA->getZExtValue(); 957 unsigned VTSize = VT.getSizeInBits(); 958 SDValue InOp = Op.getOperand(0); 959 960 // If the shift count is an invalid immediate, don't do anything. 961 if (ShAmt >= BitWidth) 962 break; 963 964 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 965 // single shift. We can do this if the top bits (which are shifted out) 966 // are never demanded. 967 if (InOp.getOpcode() == ISD::SHL && 968 isa<ConstantSDNode>(InOp.getOperand(1))) { 969 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 970 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 971 unsigned Opc = ISD::SRL; 972 int Diff = ShAmt-C1; 973 if (Diff < 0) { 974 Diff = -Diff; 975 Opc = ISD::SHL; 976 } 977 978 SDValue NewSA = 979 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 980 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 981 InOp.getOperand(0), NewSA)); 982 } 983 } 984 985 // Compute the new bits that are at the top now. 986 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 987 KnownZero, KnownOne, TLO, Depth+1)) 988 return true; 989 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 990 KnownZero = KnownZero.lshr(ShAmt); 991 KnownOne = KnownOne.lshr(ShAmt); 992 993 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 994 KnownZero |= HighBits; // High bits known zero. 995 } 996 break; 997 case ISD::SRA: 998 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 999 MVT VT = Op.getValueType(); 1000 unsigned ShAmt = SA->getZExtValue(); 1001 1002 // If the shift count is an invalid immediate, don't do anything. 1003 if (ShAmt >= BitWidth) 1004 break; 1005 1006 APInt InDemandedMask = (NewMask << ShAmt); 1007 1008 // If any of the demanded bits are produced by the sign extension, we also 1009 // demand the input sign bit. 1010 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1011 if (HighBits.intersects(NewMask)) 1012 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits()); 1013 1014 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1015 KnownZero, KnownOne, TLO, Depth+1)) 1016 return true; 1017 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1018 KnownZero = KnownZero.lshr(ShAmt); 1019 KnownOne = KnownOne.lshr(ShAmt); 1020 1021 // Handle the sign bit, adjusted to where it is now in the mask. 1022 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1023 1024 // If the input sign bit is known to be zero, or if none of the top bits 1025 // are demanded, turn this into an unsigned shift right. 1026 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1027 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 1028 Op.getOperand(1))); 1029 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1030 KnownOne |= HighBits; 1031 } 1032 } 1033 break; 1034 case ISD::SIGN_EXTEND_INREG: { 1035 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1036 1037 // Sign extension. Compute the demanded bits in the result that are not 1038 // present in the input. 1039 APInt NewBits = APInt::getHighBitsSet(BitWidth, 1040 BitWidth - EVT.getSizeInBits()) & 1041 NewMask; 1042 1043 // If none of the extended bits are demanded, eliminate the sextinreg. 1044 if (NewBits == 0) 1045 return TLO.CombineTo(Op, Op.getOperand(0)); 1046 1047 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits()); 1048 InSignBit.zext(BitWidth); 1049 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 1050 EVT.getSizeInBits()) & 1051 NewMask; 1052 1053 // Since the sign extended bits are demanded, we know that the sign 1054 // bit is demanded. 1055 InputDemandedBits |= InSignBit; 1056 1057 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1058 KnownZero, KnownOne, TLO, Depth+1)) 1059 return true; 1060 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1061 1062 // If the sign bit of the input is known set or clear, then we know the 1063 // top bits of the result. 1064 1065 // If the input sign bit is known zero, convert this into a zero extension. 1066 if (KnownZero.intersects(InSignBit)) 1067 return TLO.CombineTo(Op, 1068 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 1069 1070 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1071 KnownOne |= NewBits; 1072 KnownZero &= ~NewBits; 1073 } else { // Input sign bit unknown 1074 KnownZero &= ~NewBits; 1075 KnownOne &= ~NewBits; 1076 } 1077 break; 1078 } 1079 case ISD::ZERO_EXTEND: { 1080 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1081 APInt InMask = NewMask; 1082 InMask.trunc(OperandBitWidth); 1083 1084 // If none of the top bits are demanded, convert this into an any_extend. 1085 APInt NewBits = 1086 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1087 if (!NewBits.intersects(NewMask)) 1088 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 1089 Op.getValueType(), 1090 Op.getOperand(0))); 1091 1092 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1093 KnownZero, KnownOne, TLO, Depth+1)) 1094 return true; 1095 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1096 KnownZero.zext(BitWidth); 1097 KnownOne.zext(BitWidth); 1098 KnownZero |= NewBits; 1099 break; 1100 } 1101 case ISD::SIGN_EXTEND: { 1102 MVT InVT = Op.getOperand(0).getValueType(); 1103 unsigned InBits = InVT.getSizeInBits(); 1104 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1105 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1106 APInt NewBits = ~InMask & NewMask; 1107 1108 // If none of the top bits are demanded, convert this into an any_extend. 1109 if (NewBits == 0) 1110 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 1111 Op.getOperand(0))); 1112 1113 // Since some of the sign extended bits are demanded, we know that the sign 1114 // bit is demanded. 1115 APInt InDemandedBits = InMask & NewMask; 1116 InDemandedBits |= InSignBit; 1117 InDemandedBits.trunc(InBits); 1118 1119 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1120 KnownOne, TLO, Depth+1)) 1121 return true; 1122 KnownZero.zext(BitWidth); 1123 KnownOne.zext(BitWidth); 1124 1125 // If the sign bit is known zero, convert this to a zero extend. 1126 if (KnownZero.intersects(InSignBit)) 1127 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 1128 Op.getValueType(), 1129 Op.getOperand(0))); 1130 1131 // If the sign bit is known one, the top bits match. 1132 if (KnownOne.intersects(InSignBit)) { 1133 KnownOne |= NewBits; 1134 KnownZero &= ~NewBits; 1135 } else { // Otherwise, top bits aren't known. 1136 KnownOne &= ~NewBits; 1137 KnownZero &= ~NewBits; 1138 } 1139 break; 1140 } 1141 case ISD::ANY_EXTEND: { 1142 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1143 APInt InMask = NewMask; 1144 InMask.trunc(OperandBitWidth); 1145 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1146 KnownZero, KnownOne, TLO, Depth+1)) 1147 return true; 1148 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1149 KnownZero.zext(BitWidth); 1150 KnownOne.zext(BitWidth); 1151 break; 1152 } 1153 case ISD::TRUNCATE: { 1154 // Simplify the input, using demanded bit information, and compute the known 1155 // zero/one bits live out. 1156 APInt TruncMask = NewMask; 1157 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 1158 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1159 KnownZero, KnownOne, TLO, Depth+1)) 1160 return true; 1161 KnownZero.trunc(BitWidth); 1162 KnownOne.trunc(BitWidth); 1163 1164 // If the input is only used by this truncate, see if we can shrink it based 1165 // on the known demanded bits. 1166 if (Op.getOperand(0).getNode()->hasOneUse()) { 1167 SDValue In = Op.getOperand(0); 1168 unsigned InBitWidth = In.getValueSizeInBits(); 1169 switch (In.getOpcode()) { 1170 default: break; 1171 case ISD::SRL: 1172 // Shrink SRL by a constant if none of the high bits shifted in are 1173 // demanded. 1174 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 1175 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 1176 InBitWidth - BitWidth); 1177 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1178 HighBits.trunc(BitWidth); 1179 1180 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1181 // None of the shifted in bits are needed. Add a truncate of the 1182 // shift input, then shift it. 1183 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 1184 Op.getValueType(), 1185 In.getOperand(0)); 1186 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), 1187 NewTrunc, In.getOperand(1))); 1188 } 1189 } 1190 break; 1191 } 1192 } 1193 1194 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1195 break; 1196 } 1197 case ISD::AssertZext: { 1198 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1199 APInt InMask = APInt::getLowBitsSet(BitWidth, 1200 VT.getSizeInBits()); 1201 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1202 KnownZero, KnownOne, TLO, Depth+1)) 1203 return true; 1204 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1205 KnownZero |= ~InMask & NewMask; 1206 break; 1207 } 1208 case ISD::BIT_CONVERT: 1209#if 0 1210 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1211 // is demanded, turn this into a FGETSIGN. 1212 if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) && 1213 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1214 !MVT::isVector(Op.getOperand(0).getValueType())) { 1215 // Only do this xform if FGETSIGN is valid or if before legalize. 1216 if (!TLO.AfterLegalize || 1217 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1218 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1219 // place. We expect the SHL to be eliminated by other optimizations. 1220 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1221 Op.getOperand(0)); 1222 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1223 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1224 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1225 Sign, ShAmt)); 1226 } 1227 } 1228#endif 1229 break; 1230 default: 1231 // Just use ComputeMaskedBits to compute output bits. 1232 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1233 break; 1234 } 1235 1236 // If we know the value of all of the demanded bits, return this as a 1237 // constant. 1238 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1239 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1240 1241 return false; 1242} 1243 1244/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1245/// in Mask are known to be either zero or one and return them in the 1246/// KnownZero/KnownOne bitsets. 1247void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1248 const APInt &Mask, 1249 APInt &KnownZero, 1250 APInt &KnownOne, 1251 const SelectionDAG &DAG, 1252 unsigned Depth) const { 1253 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1254 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1255 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1256 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1257 "Should use MaskedValueIsZero if you don't know whether Op" 1258 " is a target node!"); 1259 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1260} 1261 1262/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1263/// targets that want to expose additional information about sign bits to the 1264/// DAG Combiner. 1265unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1266 unsigned Depth) const { 1267 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1268 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1269 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1270 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1271 "Should use ComputeNumSignBits if you don't know whether Op" 1272 " is a target node!"); 1273 return 1; 1274} 1275 1276 1277/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1278/// and cc. If it is unable to simplify it, return a null SDValue. 1279SDValue 1280TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 1281 ISD::CondCode Cond, bool foldBooleans, 1282 DAGCombinerInfo &DCI) const { 1283 SelectionDAG &DAG = DCI.DAG; 1284 1285 // These setcc operations always fold. 1286 switch (Cond) { 1287 default: break; 1288 case ISD::SETFALSE: 1289 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1290 case ISD::SETTRUE: 1291 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1292 } 1293 1294 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1295 const APInt &C1 = N1C->getAPIntValue(); 1296 if (isa<ConstantSDNode>(N0.getNode())) { 1297 return DAG.FoldSetCC(VT, N0, N1, Cond); 1298 } else { 1299 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1300 // equality comparison, then we're just comparing whether X itself is 1301 // zero. 1302 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1303 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1304 N0.getOperand(1).getOpcode() == ISD::Constant) { 1305 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1306 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1307 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1308 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1309 // (srl (ctlz x), 5) == 0 -> X != 0 1310 // (srl (ctlz x), 5) != 1 -> X != 0 1311 Cond = ISD::SETNE; 1312 } else { 1313 // (srl (ctlz x), 5) != 0 -> X == 0 1314 // (srl (ctlz x), 5) == 1 -> X == 0 1315 Cond = ISD::SETEQ; 1316 } 1317 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1318 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 1319 Zero, Cond); 1320 } 1321 } 1322 1323 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1324 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1325 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1326 1327 // If the comparison constant has bits in the upper part, the 1328 // zero-extended value could never match. 1329 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1330 C1.getBitWidth() - InSize))) { 1331 switch (Cond) { 1332 case ISD::SETUGT: 1333 case ISD::SETUGE: 1334 case ISD::SETEQ: return DAG.getConstant(0, VT); 1335 case ISD::SETULT: 1336 case ISD::SETULE: 1337 case ISD::SETNE: return DAG.getConstant(1, VT); 1338 case ISD::SETGT: 1339 case ISD::SETGE: 1340 // True if the sign bit of C1 is set. 1341 return DAG.getConstant(C1.isNegative(), VT); 1342 case ISD::SETLT: 1343 case ISD::SETLE: 1344 // True if the sign bit of C1 isn't set. 1345 return DAG.getConstant(C1.isNonNegative(), VT); 1346 default: 1347 break; 1348 } 1349 } 1350 1351 // Otherwise, we can perform the comparison with the low bits. 1352 switch (Cond) { 1353 case ISD::SETEQ: 1354 case ISD::SETNE: 1355 case ISD::SETUGT: 1356 case ISD::SETUGE: 1357 case ISD::SETULT: 1358 case ISD::SETULE: 1359 return DAG.getSetCC(VT, N0.getOperand(0), 1360 DAG.getConstant(APInt(C1).trunc(InSize), 1361 N0.getOperand(0).getValueType()), 1362 Cond); 1363 default: 1364 break; // todo, be more careful with signed comparisons 1365 } 1366 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1367 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1368 MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1369 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1370 MVT ExtDstTy = N0.getValueType(); 1371 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1372 1373 // If the extended part has any inconsistent bits, it cannot ever 1374 // compare equal. In other words, they have to be all ones or all 1375 // zeros. 1376 APInt ExtBits = 1377 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1378 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1379 return DAG.getConstant(Cond == ISD::SETNE, VT); 1380 1381 SDValue ZextOp; 1382 MVT Op0Ty = N0.getOperand(0).getValueType(); 1383 if (Op0Ty == ExtSrcTy) { 1384 ZextOp = N0.getOperand(0); 1385 } else { 1386 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1387 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1388 DAG.getConstant(Imm, Op0Ty)); 1389 } 1390 if (!DCI.isCalledByLegalizer()) 1391 DCI.AddToWorklist(ZextOp.getNode()); 1392 // Otherwise, make this a use of a zext. 1393 return DAG.getSetCC(VT, ZextOp, 1394 DAG.getConstant(C1 & APInt::getLowBitsSet( 1395 ExtDstTyBits, 1396 ExtSrcTyBits), 1397 ExtDstTy), 1398 Cond); 1399 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1400 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1401 1402 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1403 if (N0.getOpcode() == ISD::SETCC) { 1404 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1); 1405 if (TrueWhenTrue) 1406 return N0; 1407 1408 // Invert the condition. 1409 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1410 CC = ISD::getSetCCInverse(CC, 1411 N0.getOperand(0).getValueType().isInteger()); 1412 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); 1413 } 1414 1415 if ((N0.getOpcode() == ISD::XOR || 1416 (N0.getOpcode() == ISD::AND && 1417 N0.getOperand(0).getOpcode() == ISD::XOR && 1418 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1419 isa<ConstantSDNode>(N0.getOperand(1)) && 1420 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1421 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1422 // can only do this if the top bits are known zero. 1423 unsigned BitWidth = N0.getValueSizeInBits(); 1424 if (DAG.MaskedValueIsZero(N0, 1425 APInt::getHighBitsSet(BitWidth, 1426 BitWidth-1))) { 1427 // Okay, get the un-inverted input value. 1428 SDValue Val; 1429 if (N0.getOpcode() == ISD::XOR) 1430 Val = N0.getOperand(0); 1431 else { 1432 assert(N0.getOpcode() == ISD::AND && 1433 N0.getOperand(0).getOpcode() == ISD::XOR); 1434 // ((X^1)&1)^1 -> X & 1 1435 Val = DAG.getNode(ISD::AND, N0.getValueType(), 1436 N0.getOperand(0).getOperand(0), 1437 N0.getOperand(1)); 1438 } 1439 return DAG.getSetCC(VT, Val, N1, 1440 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1441 } 1442 } 1443 } 1444 1445 APInt MinVal, MaxVal; 1446 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1447 if (ISD::isSignedIntSetCC(Cond)) { 1448 MinVal = APInt::getSignedMinValue(OperandBitSize); 1449 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1450 } else { 1451 MinVal = APInt::getMinValue(OperandBitSize); 1452 MaxVal = APInt::getMaxValue(OperandBitSize); 1453 } 1454 1455 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1456 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1457 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1458 // X >= C0 --> X > (C0-1) 1459 return DAG.getSetCC(VT, N0, DAG.getConstant(C1-1, N1.getValueType()), 1460 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1461 } 1462 1463 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1464 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1465 // X <= C0 --> X < (C0+1) 1466 return DAG.getSetCC(VT, N0, DAG.getConstant(C1+1, N1.getValueType()), 1467 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1468 } 1469 1470 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1471 return DAG.getConstant(0, VT); // X < MIN --> false 1472 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1473 return DAG.getConstant(1, VT); // X >= MIN --> true 1474 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1475 return DAG.getConstant(0, VT); // X > MAX --> false 1476 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1477 return DAG.getConstant(1, VT); // X <= MAX --> true 1478 1479 // Canonicalize setgt X, Min --> setne X, Min 1480 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1481 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1482 // Canonicalize setlt X, Max --> setne X, Max 1483 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1484 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1485 1486 // If we have setult X, 1, turn it into seteq X, 0 1487 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1488 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 1489 ISD::SETEQ); 1490 // If we have setugt X, Max-1, turn it into seteq X, Max 1491 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1492 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 1493 ISD::SETEQ); 1494 1495 // If we have "setcc X, C0", check to see if we can shrink the immediate 1496 // by changing cc. 1497 1498 // SETUGT X, SINTMAX -> SETLT X, 0 1499 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 1500 C1 == (~0ULL >> (65-OperandBitSize))) 1501 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 1502 ISD::SETLT); 1503 1504 // FIXME: Implement the rest of these. 1505 1506 // Fold bit comparisons when we can. 1507 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1508 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1509 if (ConstantSDNode *AndRHS = 1510 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1511 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1512 // Perform the xform if the AND RHS is a single bit. 1513 if (isPowerOf2_64(AndRHS->getZExtValue())) { 1514 return DAG.getNode(ISD::SRL, VT, N0, 1515 DAG.getConstant(Log2_64(AndRHS->getZExtValue()), 1516 getShiftAmountTy())); 1517 } 1518 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) { 1519 // (X & 8) == 8 --> (X & 8) >> 3 1520 // Perform the xform if C1 is a single bit. 1521 if (C1.isPowerOf2()) { 1522 return DAG.getNode(ISD::SRL, VT, N0, 1523 DAG.getConstant(C1.logBase2(), getShiftAmountTy())); 1524 } 1525 } 1526 } 1527 } 1528 } else if (isa<ConstantSDNode>(N0.getNode())) { 1529 // Ensure that the constant occurs on the RHS. 1530 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1531 } 1532 1533 if (isa<ConstantFPSDNode>(N0.getNode())) { 1534 // Constant fold or commute setcc. 1535 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond); 1536 if (O.getNode()) return O; 1537 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1538 // If the RHS of an FP comparison is a constant, simplify it away in 1539 // some cases. 1540 if (CFP->getValueAPF().isNaN()) { 1541 // If an operand is known to be a nan, we can fold it. 1542 switch (ISD::getUnorderedFlavor(Cond)) { 1543 default: assert(0 && "Unknown flavor!"); 1544 case 0: // Known false. 1545 return DAG.getConstant(0, VT); 1546 case 1: // Known true. 1547 return DAG.getConstant(1, VT); 1548 case 2: // Undefined. 1549 return DAG.getNode(ISD::UNDEF, VT); 1550 } 1551 } 1552 1553 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1554 // constant if knowing that the operand is non-nan is enough. We prefer to 1555 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1556 // materialize 0.0. 1557 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1558 return DAG.getSetCC(VT, N0, N0, Cond); 1559 } 1560 1561 if (N0 == N1) { 1562 // We can always fold X == X for integer setcc's. 1563 if (N0.getValueType().isInteger()) 1564 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1565 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1566 if (UOF == 2) // FP operators that are undefined on NaNs. 1567 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1568 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1569 return DAG.getConstant(UOF, VT); 1570 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1571 // if it is not already. 1572 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1573 if (NewCond != Cond) 1574 return DAG.getSetCC(VT, N0, N1, NewCond); 1575 } 1576 1577 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1578 N0.getValueType().isInteger()) { 1579 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1580 N0.getOpcode() == ISD::XOR) { 1581 // Simplify (X+Y) == (X+Z) --> Y == Z 1582 if (N0.getOpcode() == N1.getOpcode()) { 1583 if (N0.getOperand(0) == N1.getOperand(0)) 1584 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 1585 if (N0.getOperand(1) == N1.getOperand(1)) 1586 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 1587 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1588 // If X op Y == Y op X, try other combinations. 1589 if (N0.getOperand(0) == N1.getOperand(1)) 1590 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 1591 if (N0.getOperand(1) == N1.getOperand(0)) 1592 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 1593 } 1594 } 1595 1596 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1597 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1598 // Turn (X+C1) == C2 --> X == C2-C1 1599 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1600 return DAG.getSetCC(VT, N0.getOperand(0), 1601 DAG.getConstant(RHSC->getAPIntValue()- 1602 LHSR->getAPIntValue(), 1603 N0.getValueType()), Cond); 1604 } 1605 1606 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1607 if (N0.getOpcode() == ISD::XOR) 1608 // If we know that all of the inverted bits are zero, don't bother 1609 // performing the inversion. 1610 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1611 return 1612 DAG.getSetCC(VT, N0.getOperand(0), 1613 DAG.getConstant(LHSR->getAPIntValue() ^ 1614 RHSC->getAPIntValue(), 1615 N0.getValueType()), 1616 Cond); 1617 } 1618 1619 // Turn (C1-X) == C2 --> X == C1-C2 1620 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1621 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 1622 return 1623 DAG.getSetCC(VT, N0.getOperand(1), 1624 DAG.getConstant(SUBC->getAPIntValue() - 1625 RHSC->getAPIntValue(), 1626 N0.getValueType()), 1627 Cond); 1628 } 1629 } 1630 } 1631 1632 // Simplify (X+Z) == X --> Z == 0 1633 if (N0.getOperand(0) == N1) 1634 return DAG.getSetCC(VT, N0.getOperand(1), 1635 DAG.getConstant(0, N0.getValueType()), Cond); 1636 if (N0.getOperand(1) == N1) { 1637 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1638 return DAG.getSetCC(VT, N0.getOperand(0), 1639 DAG.getConstant(0, N0.getValueType()), Cond); 1640 else if (N0.getNode()->hasOneUse()) { 1641 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1642 // (Z-X) == X --> Z == X<<1 1643 SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), 1644 N1, 1645 DAG.getConstant(1, getShiftAmountTy())); 1646 if (!DCI.isCalledByLegalizer()) 1647 DCI.AddToWorklist(SH.getNode()); 1648 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 1649 } 1650 } 1651 } 1652 1653 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1654 N1.getOpcode() == ISD::XOR) { 1655 // Simplify X == (X+Z) --> Z == 0 1656 if (N1.getOperand(0) == N0) { 1657 return DAG.getSetCC(VT, N1.getOperand(1), 1658 DAG.getConstant(0, N1.getValueType()), Cond); 1659 } else if (N1.getOperand(1) == N0) { 1660 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1661 return DAG.getSetCC(VT, N1.getOperand(0), 1662 DAG.getConstant(0, N1.getValueType()), Cond); 1663 } else if (N1.getNode()->hasOneUse()) { 1664 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1665 // X == (Z-X) --> X<<1 == Z 1666 SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 1667 DAG.getConstant(1, getShiftAmountTy())); 1668 if (!DCI.isCalledByLegalizer()) 1669 DCI.AddToWorklist(SH.getNode()); 1670 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 1671 } 1672 } 1673 } 1674 } 1675 1676 // Fold away ALL boolean setcc's. 1677 SDValue Temp; 1678 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1679 switch (Cond) { 1680 default: assert(0 && "Unknown integer setcc!"); 1681 case ISD::SETEQ: // X == Y -> (X^Y)^1 1682 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1683 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 1684 if (!DCI.isCalledByLegalizer()) 1685 DCI.AddToWorklist(Temp.getNode()); 1686 break; 1687 case ISD::SETNE: // X != Y --> (X^Y) 1688 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1689 break; 1690 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 1691 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 1692 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1693 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 1694 if (!DCI.isCalledByLegalizer()) 1695 DCI.AddToWorklist(Temp.getNode()); 1696 break; 1697 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 1698 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 1699 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1700 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 1701 if (!DCI.isCalledByLegalizer()) 1702 DCI.AddToWorklist(Temp.getNode()); 1703 break; 1704 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 1705 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 1706 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1707 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 1708 if (!DCI.isCalledByLegalizer()) 1709 DCI.AddToWorklist(Temp.getNode()); 1710 break; 1711 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 1712 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 1713 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1714 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 1715 break; 1716 } 1717 if (VT != MVT::i1) { 1718 if (!DCI.isCalledByLegalizer()) 1719 DCI.AddToWorklist(N0.getNode()); 1720 // FIXME: If running after legalize, we probably can't do this. 1721 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1722 } 1723 return N0; 1724 } 1725 1726 // Could not fold it. 1727 return SDValue(); 1728} 1729 1730/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 1731/// node is a GlobalAddress + offset. 1732bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, 1733 int64_t &Offset) const { 1734 if (isa<GlobalAddressSDNode>(N)) { 1735 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 1736 GA = GASD->getGlobal(); 1737 Offset += GASD->getOffset(); 1738 return true; 1739 } 1740 1741 if (N->getOpcode() == ISD::ADD) { 1742 SDValue N1 = N->getOperand(0); 1743 SDValue N2 = N->getOperand(1); 1744 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 1745 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 1746 if (V) { 1747 Offset += V->getSExtValue(); 1748 return true; 1749 } 1750 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 1751 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 1752 if (V) { 1753 Offset += V->getSExtValue(); 1754 return true; 1755 } 1756 } 1757 } 1758 return false; 1759} 1760 1761 1762/// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is 1763/// loading 'Bytes' bytes from a location that is 'Dist' units away from the 1764/// location that the 'Base' load is loading from. 1765bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base, 1766 unsigned Bytes, int Dist, 1767 const MachineFrameInfo *MFI) const { 1768 if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode()) 1769 return false; 1770 MVT VT = LD->getValueType(0); 1771 if (VT.getSizeInBits() / 8 != Bytes) 1772 return false; 1773 1774 SDValue Loc = LD->getOperand(1); 1775 SDValue BaseLoc = Base->getOperand(1); 1776 if (Loc.getOpcode() == ISD::FrameIndex) { 1777 if (BaseLoc.getOpcode() != ISD::FrameIndex) 1778 return false; 1779 int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); 1780 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 1781 int FS = MFI->getObjectSize(FI); 1782 int BFS = MFI->getObjectSize(BFI); 1783 if (FS != BFS || FS != (int)Bytes) return false; 1784 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes); 1785 } 1786 1787 GlobalValue *GV1 = NULL; 1788 GlobalValue *GV2 = NULL; 1789 int64_t Offset1 = 0; 1790 int64_t Offset2 = 0; 1791 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1); 1792 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); 1793 if (isGA1 && isGA2 && GV1 == GV2) 1794 return Offset1 == (Offset2 + Dist*Bytes); 1795 return false; 1796} 1797 1798 1799SDValue TargetLowering:: 1800PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1801 // Default implementation: no optimization. 1802 return SDValue(); 1803} 1804 1805//===----------------------------------------------------------------------===// 1806// Inline Assembler Implementation Methods 1807//===----------------------------------------------------------------------===// 1808 1809 1810TargetLowering::ConstraintType 1811TargetLowering::getConstraintType(const std::string &Constraint) const { 1812 // FIXME: lots more standard ones to handle. 1813 if (Constraint.size() == 1) { 1814 switch (Constraint[0]) { 1815 default: break; 1816 case 'r': return C_RegisterClass; 1817 case 'm': // memory 1818 case 'o': // offsetable 1819 case 'V': // not offsetable 1820 return C_Memory; 1821 case 'i': // Simple Integer or Relocatable Constant 1822 case 'n': // Simple Integer 1823 case 's': // Relocatable Constant 1824 case 'X': // Allow ANY value. 1825 case 'I': // Target registers. 1826 case 'J': 1827 case 'K': 1828 case 'L': 1829 case 'M': 1830 case 'N': 1831 case 'O': 1832 case 'P': 1833 return C_Other; 1834 } 1835 } 1836 1837 if (Constraint.size() > 1 && Constraint[0] == '{' && 1838 Constraint[Constraint.size()-1] == '}') 1839 return C_Register; 1840 return C_Unknown; 1841} 1842 1843/// LowerXConstraint - try to replace an X constraint, which matches anything, 1844/// with another that has more specific requirements based on the type of the 1845/// corresponding operand. 1846const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ 1847 if (ConstraintVT.isInteger()) 1848 return "r"; 1849 if (ConstraintVT.isFloatingPoint()) 1850 return "f"; // works for many targets 1851 return 0; 1852} 1853 1854/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1855/// vector. If it is invalid, don't add anything to Ops. 1856void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 1857 char ConstraintLetter, 1858 bool hasMemory, 1859 std::vector<SDValue> &Ops, 1860 SelectionDAG &DAG) const { 1861 switch (ConstraintLetter) { 1862 default: break; 1863 case 'X': // Allows any operand; labels (basic block) use this. 1864 if (Op.getOpcode() == ISD::BasicBlock) { 1865 Ops.push_back(Op); 1866 return; 1867 } 1868 // fall through 1869 case 'i': // Simple Integer or Relocatable Constant 1870 case 'n': // Simple Integer 1871 case 's': { // Relocatable Constant 1872 // These operands are interested in values of the form (GV+C), where C may 1873 // be folded in as an offset of GV, or it may be explicitly added. Also, it 1874 // is possible and fine if either GV or C are missing. 1875 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1876 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 1877 1878 // If we have "(add GV, C)", pull out GV/C 1879 if (Op.getOpcode() == ISD::ADD) { 1880 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1881 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 1882 if (C == 0 || GA == 0) { 1883 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 1884 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 1885 } 1886 if (C == 0 || GA == 0) 1887 C = 0, GA = 0; 1888 } 1889 1890 // If we find a valid operand, map to the TargetXXX version so that the 1891 // value itself doesn't get selected. 1892 if (GA) { // Either &GV or &GV+C 1893 if (ConstraintLetter != 'n') { 1894 int64_t Offs = GA->getOffset(); 1895 if (C) Offs += C->getZExtValue(); 1896 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 1897 Op.getValueType(), Offs)); 1898 return; 1899 } 1900 } 1901 if (C) { // just C, no GV. 1902 // Simple constants are not allowed for 's'. 1903 if (ConstraintLetter != 's') { 1904 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue(), 1905 Op.getValueType())); 1906 return; 1907 } 1908 } 1909 break; 1910 } 1911 } 1912} 1913 1914std::vector<unsigned> TargetLowering:: 1915getRegClassForInlineAsmConstraint(const std::string &Constraint, 1916 MVT VT) const { 1917 return std::vector<unsigned>(); 1918} 1919 1920 1921std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 1922getRegForInlineAsmConstraint(const std::string &Constraint, 1923 MVT VT) const { 1924 if (Constraint[0] != '{') 1925 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1926 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 1927 1928 // Remove the braces from around the name. 1929 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 1930 1931 // Figure out which register class contains this reg. 1932 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 1933 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 1934 E = RI->regclass_end(); RCI != E; ++RCI) { 1935 const TargetRegisterClass *RC = *RCI; 1936 1937 // If none of the the value types for this register class are valid, we 1938 // can't use it. For example, 64-bit reg classes on 32-bit targets. 1939 bool isLegal = false; 1940 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1941 I != E; ++I) { 1942 if (isTypeLegal(*I)) { 1943 isLegal = true; 1944 break; 1945 } 1946 } 1947 1948 if (!isLegal) continue; 1949 1950 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 1951 I != E; ++I) { 1952 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName)) 1953 return std::make_pair(*I, RC); 1954 } 1955 } 1956 1957 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1958} 1959 1960//===----------------------------------------------------------------------===// 1961// Constraint Selection. 1962 1963/// getConstraintGenerality - Return an integer indicating how general CT 1964/// is. 1965static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 1966 switch (CT) { 1967 default: assert(0 && "Unknown constraint type!"); 1968 case TargetLowering::C_Other: 1969 case TargetLowering::C_Unknown: 1970 return 0; 1971 case TargetLowering::C_Register: 1972 return 1; 1973 case TargetLowering::C_RegisterClass: 1974 return 2; 1975 case TargetLowering::C_Memory: 1976 return 3; 1977 } 1978} 1979 1980/// ChooseConstraint - If there are multiple different constraints that we 1981/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 1982/// This is somewhat tricky: constraints fall into four classes: 1983/// Other -> immediates and magic values 1984/// Register -> one specific register 1985/// RegisterClass -> a group of regs 1986/// Memory -> memory 1987/// Ideally, we would pick the most specific constraint possible: if we have 1988/// something that fits into a register, we would pick it. The problem here 1989/// is that if we have something that could either be in a register or in 1990/// memory that use of the register could cause selection of *other* 1991/// operands to fail: they might only succeed if we pick memory. Because of 1992/// this the heuristic we use is: 1993/// 1994/// 1) If there is an 'other' constraint, and if the operand is valid for 1995/// that constraint, use it. This makes us take advantage of 'i' 1996/// constraints when available. 1997/// 2) Otherwise, pick the most general constraint present. This prefers 1998/// 'm' over 'r', for example. 1999/// 2000static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2001 bool hasMemory, const TargetLowering &TLI, 2002 SDValue Op, SelectionDAG *DAG) { 2003 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2004 unsigned BestIdx = 0; 2005 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2006 int BestGenerality = -1; 2007 2008 // Loop over the options, keeping track of the most general one. 2009 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2010 TargetLowering::ConstraintType CType = 2011 TLI.getConstraintType(OpInfo.Codes[i]); 2012 2013 // If this is an 'other' constraint, see if the operand is valid for it. 2014 // For example, on X86 we might have an 'rI' constraint. If the operand 2015 // is an integer in the range [0..31] we want to use I (saving a load 2016 // of a register), otherwise we must use 'r'. 2017 if (CType == TargetLowering::C_Other && Op.getNode()) { 2018 assert(OpInfo.Codes[i].size() == 1 && 2019 "Unhandled multi-letter 'other' constraint"); 2020 std::vector<SDValue> ResultOps; 2021 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2022 ResultOps, *DAG); 2023 if (!ResultOps.empty()) { 2024 BestType = CType; 2025 BestIdx = i; 2026 break; 2027 } 2028 } 2029 2030 // This constraint letter is more general than the previous one, use it. 2031 int Generality = getConstraintGenerality(CType); 2032 if (Generality > BestGenerality) { 2033 BestType = CType; 2034 BestIdx = i; 2035 BestGenerality = Generality; 2036 } 2037 } 2038 2039 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2040 OpInfo.ConstraintType = BestType; 2041} 2042 2043/// ComputeConstraintToUse - Determines the constraint code and constraint 2044/// type to use for the specific AsmOperandInfo, setting 2045/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2046void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2047 SDValue Op, 2048 bool hasMemory, 2049 SelectionDAG *DAG) const { 2050 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2051 2052 // Single-letter constraints ('r') are very common. 2053 if (OpInfo.Codes.size() == 1) { 2054 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2055 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2056 } else { 2057 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2058 } 2059 2060 // 'X' matches anything. 2061 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2062 // Labels and constants are handled elsewhere ('X' is the only thing 2063 // that matches labels). 2064 if (isa<BasicBlock>(OpInfo.CallOperandVal) || 2065 isa<ConstantInt>(OpInfo.CallOperandVal)) 2066 return; 2067 2068 // Otherwise, try to resolve it to something we know about by looking at 2069 // the actual operand type. 2070 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2071 OpInfo.ConstraintCode = Repl; 2072 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2073 } 2074 } 2075} 2076 2077//===----------------------------------------------------------------------===// 2078// Loop Strength Reduction hooks 2079//===----------------------------------------------------------------------===// 2080 2081/// isLegalAddressingMode - Return true if the addressing mode represented 2082/// by AM is legal for this target, for a load/store of the specified type. 2083bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2084 const Type *Ty) const { 2085 // The default implementation of this implements a conservative RISCy, r+r and 2086 // r+i addr mode. 2087 2088 // Allows a sign-extended 16-bit immediate field. 2089 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2090 return false; 2091 2092 // No global is ever allowed as a base. 2093 if (AM.BaseGV) 2094 return false; 2095 2096 // Only support r+r, 2097 switch (AM.Scale) { 2098 case 0: // "r+i" or just "i", depending on HasBaseReg. 2099 break; 2100 case 1: 2101 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2102 return false; 2103 // Otherwise we have r+r or r+i. 2104 break; 2105 case 2: 2106 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2107 return false; 2108 // Allow 2*r as r+r. 2109 break; 2110 } 2111 2112 return true; 2113} 2114 2115// Magic for divide replacement 2116 2117struct ms { 2118 int64_t m; // magic number 2119 int64_t s; // shift amount 2120}; 2121 2122struct mu { 2123 uint64_t m; // magic number 2124 int64_t a; // add indicator 2125 int64_t s; // shift amount 2126}; 2127 2128/// magic - calculate the magic numbers required to codegen an integer sdiv as 2129/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 2130/// or -1. 2131static ms magic32(int32_t d) { 2132 int32_t p; 2133 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 2134 const uint32_t two31 = 0x80000000U; 2135 struct ms mag; 2136 2137 ad = abs(d); 2138 t = two31 + ((uint32_t)d >> 31); 2139 anc = t - 1 - t%ad; // absolute value of nc 2140 p = 31; // initialize p 2141 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 2142 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 2143 q2 = two31/ad; // initialize q2 = 2p/abs(d) 2144 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 2145 do { 2146 p = p + 1; 2147 q1 = 2*q1; // update q1 = 2p/abs(nc) 2148 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 2149 if (r1 >= anc) { // must be unsigned comparison 2150 q1 = q1 + 1; 2151 r1 = r1 - anc; 2152 } 2153 q2 = 2*q2; // update q2 = 2p/abs(d) 2154 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 2155 if (r2 >= ad) { // must be unsigned comparison 2156 q2 = q2 + 1; 2157 r2 = r2 - ad; 2158 } 2159 delta = ad - r2; 2160 } while (q1 < delta || (q1 == delta && r1 == 0)); 2161 2162 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 2163 if (d < 0) mag.m = -mag.m; // resulting magic number 2164 mag.s = p - 32; // resulting shift 2165 return mag; 2166} 2167 2168/// magicu - calculate the magic numbers required to codegen an integer udiv as 2169/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 2170static mu magicu32(uint32_t d) { 2171 int32_t p; 2172 uint32_t nc, delta, q1, r1, q2, r2; 2173 struct mu magu; 2174 magu.a = 0; // initialize "add" indicator 2175 nc = - 1 - (-d)%d; 2176 p = 31; // initialize p 2177 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 2178 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 2179 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 2180 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 2181 do { 2182 p = p + 1; 2183 if (r1 >= nc - r1 ) { 2184 q1 = 2*q1 + 1; // update q1 2185 r1 = 2*r1 - nc; // update r1 2186 } 2187 else { 2188 q1 = 2*q1; // update q1 2189 r1 = 2*r1; // update r1 2190 } 2191 if (r2 + 1 >= d - r2) { 2192 if (q2 >= 0x7FFFFFFF) magu.a = 1; 2193 q2 = 2*q2 + 1; // update q2 2194 r2 = 2*r2 + 1 - d; // update r2 2195 } 2196 else { 2197 if (q2 >= 0x80000000) magu.a = 1; 2198 q2 = 2*q2; // update q2 2199 r2 = 2*r2 + 1; // update r2 2200 } 2201 delta = d - 1 - r2; 2202 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 2203 magu.m = q2 + 1; // resulting magic number 2204 magu.s = p - 32; // resulting shift 2205 return magu; 2206} 2207 2208/// magic - calculate the magic numbers required to codegen an integer sdiv as 2209/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 2210/// or -1. 2211static ms magic64(int64_t d) { 2212 int64_t p; 2213 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 2214 const uint64_t two63 = 9223372036854775808ULL; // 2^63 2215 struct ms mag; 2216 2217 ad = d >= 0 ? d : -d; 2218 t = two63 + ((uint64_t)d >> 63); 2219 anc = t - 1 - t%ad; // absolute value of nc 2220 p = 63; // initialize p 2221 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 2222 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 2223 q2 = two63/ad; // initialize q2 = 2p/abs(d) 2224 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 2225 do { 2226 p = p + 1; 2227 q1 = 2*q1; // update q1 = 2p/abs(nc) 2228 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 2229 if (r1 >= anc) { // must be unsigned comparison 2230 q1 = q1 + 1; 2231 r1 = r1 - anc; 2232 } 2233 q2 = 2*q2; // update q2 = 2p/abs(d) 2234 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 2235 if (r2 >= ad) { // must be unsigned comparison 2236 q2 = q2 + 1; 2237 r2 = r2 - ad; 2238 } 2239 delta = ad - r2; 2240 } while (q1 < delta || (q1 == delta && r1 == 0)); 2241 2242 mag.m = q2 + 1; 2243 if (d < 0) mag.m = -mag.m; // resulting magic number 2244 mag.s = p - 64; // resulting shift 2245 return mag; 2246} 2247 2248/// magicu - calculate the magic numbers required to codegen an integer udiv as 2249/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 2250static mu magicu64(uint64_t d) 2251{ 2252 int64_t p; 2253 uint64_t nc, delta, q1, r1, q2, r2; 2254 struct mu magu; 2255 magu.a = 0; // initialize "add" indicator 2256 nc = - 1 - (-d)%d; 2257 p = 63; // initialize p 2258 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 2259 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 2260 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 2261 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 2262 do { 2263 p = p + 1; 2264 if (r1 >= nc - r1 ) { 2265 q1 = 2*q1 + 1; // update q1 2266 r1 = 2*r1 - nc; // update r1 2267 } 2268 else { 2269 q1 = 2*q1; // update q1 2270 r1 = 2*r1; // update r1 2271 } 2272 if (r2 + 1 >= d - r2) { 2273 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 2274 q2 = 2*q2 + 1; // update q2 2275 r2 = 2*r2 + 1 - d; // update r2 2276 } 2277 else { 2278 if (q2 >= 0x8000000000000000ull) magu.a = 1; 2279 q2 = 2*q2; // update q2 2280 r2 = 2*r2 + 1; // update r2 2281 } 2282 delta = d - 1 - r2; 2283 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0))); 2284 magu.m = q2 + 1; // resulting magic number 2285 magu.s = p - 64; // resulting shift 2286 return magu; 2287} 2288 2289/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2290/// return a DAG expression to select that will generate the same value by 2291/// multiplying by a magic number. See: 2292/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2293SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2294 std::vector<SDNode*>* Created) const { 2295 MVT VT = N->getValueType(0); 2296 2297 // Check to see if we can do this. 2298 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2299 return SDValue(); // BuildSDIV only operates on i32 or i64 2300 2301 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSExtValue(); 2302 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 2303 2304 // Multiply the numerator (operand 0) by the magic value 2305 SDValue Q; 2306 if (isOperationLegal(ISD::MULHS, VT)) 2307 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2308 DAG.getConstant(magics.m, VT)); 2309 else if (isOperationLegal(ISD::SMUL_LOHI, VT)) 2310 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), 2311 N->getOperand(0), 2312 DAG.getConstant(magics.m, VT)).getNode(), 1); 2313 else 2314 return SDValue(); // No mulhs or equvialent 2315 // If d > 0 and m < 0, add the numerator 2316 if (d > 0 && magics.m < 0) { 2317 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2318 if (Created) 2319 Created->push_back(Q.getNode()); 2320 } 2321 // If d < 0 and m > 0, subtract the numerator. 2322 if (d < 0 && magics.m > 0) { 2323 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2324 if (Created) 2325 Created->push_back(Q.getNode()); 2326 } 2327 // Shift right algebraic if shift value is nonzero 2328 if (magics.s > 0) { 2329 Q = DAG.getNode(ISD::SRA, VT, Q, 2330 DAG.getConstant(magics.s, getShiftAmountTy())); 2331 if (Created) 2332 Created->push_back(Q.getNode()); 2333 } 2334 // Extract the sign bit and add it to the quotient 2335 SDValue T = 2336 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2337 getShiftAmountTy())); 2338 if (Created) 2339 Created->push_back(T.getNode()); 2340 return DAG.getNode(ISD::ADD, VT, Q, T); 2341} 2342 2343/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2344/// return a DAG expression to select that will generate the same value by 2345/// multiplying by a magic number. See: 2346/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2347SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2348 std::vector<SDNode*>* Created) const { 2349 MVT VT = N->getValueType(0); 2350 2351 // Check to see if we can do this. 2352 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2353 return SDValue(); // BuildUDIV only operates on i32 or i64 2354 2355 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 2356 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2357 2358 // Multiply the numerator (operand 0) by the magic value 2359 SDValue Q; 2360 if (isOperationLegal(ISD::MULHU, VT)) 2361 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2362 DAG.getConstant(magics.m, VT)); 2363 else if (isOperationLegal(ISD::UMUL_LOHI, VT)) 2364 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), 2365 N->getOperand(0), 2366 DAG.getConstant(magics.m, VT)).getNode(), 1); 2367 else 2368 return SDValue(); // No mulhu or equvialent 2369 if (Created) 2370 Created->push_back(Q.getNode()); 2371 2372 if (magics.a == 0) { 2373 return DAG.getNode(ISD::SRL, VT, Q, 2374 DAG.getConstant(magics.s, getShiftAmountTy())); 2375 } else { 2376 SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2377 if (Created) 2378 Created->push_back(NPQ.getNode()); 2379 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2380 DAG.getConstant(1, getShiftAmountTy())); 2381 if (Created) 2382 Created->push_back(NPQ.getNode()); 2383 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2384 if (Created) 2385 Created->push_back(NPQ.getNode()); 2386 return DAG.getNode(ISD::SRL, VT, NPQ, 2387 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2388 } 2389} 2390