TargetLowering.cpp revision 40f8f6264d5af2c38e797e0dc59827cd231e8ff7
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/CodeGen/Analysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineJumpTableInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31using namespace llvm; 32 33namespace llvm { 34TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 35 bool isLocal = GV->hasLocalLinkage(); 36 bool isDeclaration = GV->isDeclaration(); 37 // FIXME: what should we do for protected and internal visibility? 38 // For variables, is internal different from hidden? 39 bool isHidden = GV->hasHiddenVisibility(); 40 41 if (reloc == Reloc::PIC_) { 42 if (isLocal || isHidden) 43 return TLSModel::LocalDynamic; 44 else 45 return TLSModel::GeneralDynamic; 46 } else { 47 if (!isDeclaration || isHidden) 48 return TLSModel::LocalExec; 49 else 50 return TLSModel::InitialExec; 51 } 52} 53} 54 55/// InitLibcallNames - Set default libcall names. 56/// 57static void InitLibcallNames(const char **Names) { 58 Names[RTLIB::SHL_I16] = "__ashlhi3"; 59 Names[RTLIB::SHL_I32] = "__ashlsi3"; 60 Names[RTLIB::SHL_I64] = "__ashldi3"; 61 Names[RTLIB::SHL_I128] = "__ashlti3"; 62 Names[RTLIB::SRL_I16] = "__lshrhi3"; 63 Names[RTLIB::SRL_I32] = "__lshrsi3"; 64 Names[RTLIB::SRL_I64] = "__lshrdi3"; 65 Names[RTLIB::SRL_I128] = "__lshrti3"; 66 Names[RTLIB::SRA_I16] = "__ashrhi3"; 67 Names[RTLIB::SRA_I32] = "__ashrsi3"; 68 Names[RTLIB::SRA_I64] = "__ashrdi3"; 69 Names[RTLIB::SRA_I128] = "__ashrti3"; 70 Names[RTLIB::MUL_I8] = "__mulqi3"; 71 Names[RTLIB::MUL_I16] = "__mulhi3"; 72 Names[RTLIB::MUL_I32] = "__mulsi3"; 73 Names[RTLIB::MUL_I64] = "__muldi3"; 74 Names[RTLIB::MUL_I128] = "__multi3"; 75 Names[RTLIB::SDIV_I8] = "__divqi3"; 76 Names[RTLIB::SDIV_I16] = "__divhi3"; 77 Names[RTLIB::SDIV_I32] = "__divsi3"; 78 Names[RTLIB::SDIV_I64] = "__divdi3"; 79 Names[RTLIB::SDIV_I128] = "__divti3"; 80 Names[RTLIB::UDIV_I8] = "__udivqi3"; 81 Names[RTLIB::UDIV_I16] = "__udivhi3"; 82 Names[RTLIB::UDIV_I32] = "__udivsi3"; 83 Names[RTLIB::UDIV_I64] = "__udivdi3"; 84 Names[RTLIB::UDIV_I128] = "__udivti3"; 85 Names[RTLIB::SREM_I8] = "__modqi3"; 86 Names[RTLIB::SREM_I16] = "__modhi3"; 87 Names[RTLIB::SREM_I32] = "__modsi3"; 88 Names[RTLIB::SREM_I64] = "__moddi3"; 89 Names[RTLIB::SREM_I128] = "__modti3"; 90 Names[RTLIB::UREM_I8] = "__umodqi3"; 91 Names[RTLIB::UREM_I16] = "__umodhi3"; 92 Names[RTLIB::UREM_I32] = "__umodsi3"; 93 Names[RTLIB::UREM_I64] = "__umoddi3"; 94 Names[RTLIB::UREM_I128] = "__umodti3"; 95 Names[RTLIB::NEG_I32] = "__negsi2"; 96 Names[RTLIB::NEG_I64] = "__negdi2"; 97 Names[RTLIB::ADD_F32] = "__addsf3"; 98 Names[RTLIB::ADD_F64] = "__adddf3"; 99 Names[RTLIB::ADD_F80] = "__addxf3"; 100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 101 Names[RTLIB::SUB_F32] = "__subsf3"; 102 Names[RTLIB::SUB_F64] = "__subdf3"; 103 Names[RTLIB::SUB_F80] = "__subxf3"; 104 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 105 Names[RTLIB::MUL_F32] = "__mulsf3"; 106 Names[RTLIB::MUL_F64] = "__muldf3"; 107 Names[RTLIB::MUL_F80] = "__mulxf3"; 108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 109 Names[RTLIB::DIV_F32] = "__divsf3"; 110 Names[RTLIB::DIV_F64] = "__divdf3"; 111 Names[RTLIB::DIV_F80] = "__divxf3"; 112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 113 Names[RTLIB::REM_F32] = "fmodf"; 114 Names[RTLIB::REM_F64] = "fmod"; 115 Names[RTLIB::REM_F80] = "fmodl"; 116 Names[RTLIB::REM_PPCF128] = "fmodl"; 117 Names[RTLIB::POWI_F32] = "__powisf2"; 118 Names[RTLIB::POWI_F64] = "__powidf2"; 119 Names[RTLIB::POWI_F80] = "__powixf2"; 120 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 121 Names[RTLIB::SQRT_F32] = "sqrtf"; 122 Names[RTLIB::SQRT_F64] = "sqrt"; 123 Names[RTLIB::SQRT_F80] = "sqrtl"; 124 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 125 Names[RTLIB::LOG_F32] = "logf"; 126 Names[RTLIB::LOG_F64] = "log"; 127 Names[RTLIB::LOG_F80] = "logl"; 128 Names[RTLIB::LOG_PPCF128] = "logl"; 129 Names[RTLIB::LOG2_F32] = "log2f"; 130 Names[RTLIB::LOG2_F64] = "log2"; 131 Names[RTLIB::LOG2_F80] = "log2l"; 132 Names[RTLIB::LOG2_PPCF128] = "log2l"; 133 Names[RTLIB::LOG10_F32] = "log10f"; 134 Names[RTLIB::LOG10_F64] = "log10"; 135 Names[RTLIB::LOG10_F80] = "log10l"; 136 Names[RTLIB::LOG10_PPCF128] = "log10l"; 137 Names[RTLIB::EXP_F32] = "expf"; 138 Names[RTLIB::EXP_F64] = "exp"; 139 Names[RTLIB::EXP_F80] = "expl"; 140 Names[RTLIB::EXP_PPCF128] = "expl"; 141 Names[RTLIB::EXP2_F32] = "exp2f"; 142 Names[RTLIB::EXP2_F64] = "exp2"; 143 Names[RTLIB::EXP2_F80] = "exp2l"; 144 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 145 Names[RTLIB::SIN_F32] = "sinf"; 146 Names[RTLIB::SIN_F64] = "sin"; 147 Names[RTLIB::SIN_F80] = "sinl"; 148 Names[RTLIB::SIN_PPCF128] = "sinl"; 149 Names[RTLIB::COS_F32] = "cosf"; 150 Names[RTLIB::COS_F64] = "cos"; 151 Names[RTLIB::COS_F80] = "cosl"; 152 Names[RTLIB::COS_PPCF128] = "cosl"; 153 Names[RTLIB::POW_F32] = "powf"; 154 Names[RTLIB::POW_F64] = "pow"; 155 Names[RTLIB::POW_F80] = "powl"; 156 Names[RTLIB::POW_PPCF128] = "powl"; 157 Names[RTLIB::CEIL_F32] = "ceilf"; 158 Names[RTLIB::CEIL_F64] = "ceil"; 159 Names[RTLIB::CEIL_F80] = "ceill"; 160 Names[RTLIB::CEIL_PPCF128] = "ceill"; 161 Names[RTLIB::TRUNC_F32] = "truncf"; 162 Names[RTLIB::TRUNC_F64] = "trunc"; 163 Names[RTLIB::TRUNC_F80] = "truncl"; 164 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 165 Names[RTLIB::RINT_F32] = "rintf"; 166 Names[RTLIB::RINT_F64] = "rint"; 167 Names[RTLIB::RINT_F80] = "rintl"; 168 Names[RTLIB::RINT_PPCF128] = "rintl"; 169 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 170 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 171 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 172 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 173 Names[RTLIB::FLOOR_F32] = "floorf"; 174 Names[RTLIB::FLOOR_F64] = "floor"; 175 Names[RTLIB::FLOOR_F80] = "floorl"; 176 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 177 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 178 Names[RTLIB::COPYSIGN_F64] = "copysign"; 179 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 180 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 181 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 182 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 183 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 184 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 185 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 186 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 187 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 188 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 189 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 190 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 191 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 192 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 193 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 194 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 195 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 196 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 197 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 198 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 199 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 200 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 201 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 202 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 203 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 204 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 205 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 206 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 207 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 208 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 209 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 210 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 211 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 212 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 213 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 214 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 215 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 216 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 217 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 218 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 219 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 220 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 221 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 222 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 223 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 224 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 225 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 226 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 227 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 228 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 229 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 230 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 231 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 232 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 233 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 234 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 235 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 236 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 237 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 238 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 239 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 240 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 241 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 242 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 243 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 244 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 245 Names[RTLIB::OEQ_F32] = "__eqsf2"; 246 Names[RTLIB::OEQ_F64] = "__eqdf2"; 247 Names[RTLIB::UNE_F32] = "__nesf2"; 248 Names[RTLIB::UNE_F64] = "__nedf2"; 249 Names[RTLIB::OGE_F32] = "__gesf2"; 250 Names[RTLIB::OGE_F64] = "__gedf2"; 251 Names[RTLIB::OLT_F32] = "__ltsf2"; 252 Names[RTLIB::OLT_F64] = "__ltdf2"; 253 Names[RTLIB::OLE_F32] = "__lesf2"; 254 Names[RTLIB::OLE_F64] = "__ledf2"; 255 Names[RTLIB::OGT_F32] = "__gtsf2"; 256 Names[RTLIB::OGT_F64] = "__gtdf2"; 257 Names[RTLIB::UO_F32] = "__unordsf2"; 258 Names[RTLIB::UO_F64] = "__unorddf2"; 259 Names[RTLIB::O_F32] = "__unordsf2"; 260 Names[RTLIB::O_F64] = "__unorddf2"; 261 Names[RTLIB::MEMCPY] = "memcpy"; 262 Names[RTLIB::MEMMOVE] = "memmove"; 263 Names[RTLIB::MEMSET] = "memset"; 264 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 265 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 268 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 269 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 272 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 273 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 274 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 275 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 276 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 277 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 278 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 279 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 280 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 281 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 282 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 283 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 284 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 285 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 286 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 287 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 288 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 289 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 290 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 291 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4"; 292 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 293 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 294 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 295 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 296 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 297} 298 299/// InitLibcallCallingConvs - Set default libcall CallingConvs. 300/// 301static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 302 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 303 CCs[i] = CallingConv::C; 304 } 305} 306 307/// getFPEXT - Return the FPEXT_*_* value for the given types, or 308/// UNKNOWN_LIBCALL if there is none. 309RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 310 if (OpVT == MVT::f32) { 311 if (RetVT == MVT::f64) 312 return FPEXT_F32_F64; 313 } 314 315 return UNKNOWN_LIBCALL; 316} 317 318/// getFPROUND - Return the FPROUND_*_* value for the given types, or 319/// UNKNOWN_LIBCALL if there is none. 320RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 321 if (RetVT == MVT::f32) { 322 if (OpVT == MVT::f64) 323 return FPROUND_F64_F32; 324 if (OpVT == MVT::f80) 325 return FPROUND_F80_F32; 326 if (OpVT == MVT::ppcf128) 327 return FPROUND_PPCF128_F32; 328 } else if (RetVT == MVT::f64) { 329 if (OpVT == MVT::f80) 330 return FPROUND_F80_F64; 331 if (OpVT == MVT::ppcf128) 332 return FPROUND_PPCF128_F64; 333 } 334 335 return UNKNOWN_LIBCALL; 336} 337 338/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 339/// UNKNOWN_LIBCALL if there is none. 340RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 341 if (OpVT == MVT::f32) { 342 if (RetVT == MVT::i8) 343 return FPTOSINT_F32_I8; 344 if (RetVT == MVT::i16) 345 return FPTOSINT_F32_I16; 346 if (RetVT == MVT::i32) 347 return FPTOSINT_F32_I32; 348 if (RetVT == MVT::i64) 349 return FPTOSINT_F32_I64; 350 if (RetVT == MVT::i128) 351 return FPTOSINT_F32_I128; 352 } else if (OpVT == MVT::f64) { 353 if (RetVT == MVT::i8) 354 return FPTOSINT_F64_I8; 355 if (RetVT == MVT::i16) 356 return FPTOSINT_F64_I16; 357 if (RetVT == MVT::i32) 358 return FPTOSINT_F64_I32; 359 if (RetVT == MVT::i64) 360 return FPTOSINT_F64_I64; 361 if (RetVT == MVT::i128) 362 return FPTOSINT_F64_I128; 363 } else if (OpVT == MVT::f80) { 364 if (RetVT == MVT::i32) 365 return FPTOSINT_F80_I32; 366 if (RetVT == MVT::i64) 367 return FPTOSINT_F80_I64; 368 if (RetVT == MVT::i128) 369 return FPTOSINT_F80_I128; 370 } else if (OpVT == MVT::ppcf128) { 371 if (RetVT == MVT::i32) 372 return FPTOSINT_PPCF128_I32; 373 if (RetVT == MVT::i64) 374 return FPTOSINT_PPCF128_I64; 375 if (RetVT == MVT::i128) 376 return FPTOSINT_PPCF128_I128; 377 } 378 return UNKNOWN_LIBCALL; 379} 380 381/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 382/// UNKNOWN_LIBCALL if there is none. 383RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 384 if (OpVT == MVT::f32) { 385 if (RetVT == MVT::i8) 386 return FPTOUINT_F32_I8; 387 if (RetVT == MVT::i16) 388 return FPTOUINT_F32_I16; 389 if (RetVT == MVT::i32) 390 return FPTOUINT_F32_I32; 391 if (RetVT == MVT::i64) 392 return FPTOUINT_F32_I64; 393 if (RetVT == MVT::i128) 394 return FPTOUINT_F32_I128; 395 } else if (OpVT == MVT::f64) { 396 if (RetVT == MVT::i8) 397 return FPTOUINT_F64_I8; 398 if (RetVT == MVT::i16) 399 return FPTOUINT_F64_I16; 400 if (RetVT == MVT::i32) 401 return FPTOUINT_F64_I32; 402 if (RetVT == MVT::i64) 403 return FPTOUINT_F64_I64; 404 if (RetVT == MVT::i128) 405 return FPTOUINT_F64_I128; 406 } else if (OpVT == MVT::f80) { 407 if (RetVT == MVT::i32) 408 return FPTOUINT_F80_I32; 409 if (RetVT == MVT::i64) 410 return FPTOUINT_F80_I64; 411 if (RetVT == MVT::i128) 412 return FPTOUINT_F80_I128; 413 } else if (OpVT == MVT::ppcf128) { 414 if (RetVT == MVT::i32) 415 return FPTOUINT_PPCF128_I32; 416 if (RetVT == MVT::i64) 417 return FPTOUINT_PPCF128_I64; 418 if (RetVT == MVT::i128) 419 return FPTOUINT_PPCF128_I128; 420 } 421 return UNKNOWN_LIBCALL; 422} 423 424/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 425/// UNKNOWN_LIBCALL if there is none. 426RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 427 if (OpVT == MVT::i32) { 428 if (RetVT == MVT::f32) 429 return SINTTOFP_I32_F32; 430 else if (RetVT == MVT::f64) 431 return SINTTOFP_I32_F64; 432 else if (RetVT == MVT::f80) 433 return SINTTOFP_I32_F80; 434 else if (RetVT == MVT::ppcf128) 435 return SINTTOFP_I32_PPCF128; 436 } else if (OpVT == MVT::i64) { 437 if (RetVT == MVT::f32) 438 return SINTTOFP_I64_F32; 439 else if (RetVT == MVT::f64) 440 return SINTTOFP_I64_F64; 441 else if (RetVT == MVT::f80) 442 return SINTTOFP_I64_F80; 443 else if (RetVT == MVT::ppcf128) 444 return SINTTOFP_I64_PPCF128; 445 } else if (OpVT == MVT::i128) { 446 if (RetVT == MVT::f32) 447 return SINTTOFP_I128_F32; 448 else if (RetVT == MVT::f64) 449 return SINTTOFP_I128_F64; 450 else if (RetVT == MVT::f80) 451 return SINTTOFP_I128_F80; 452 else if (RetVT == MVT::ppcf128) 453 return SINTTOFP_I128_PPCF128; 454 } 455 return UNKNOWN_LIBCALL; 456} 457 458/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 459/// UNKNOWN_LIBCALL if there is none. 460RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 461 if (OpVT == MVT::i32) { 462 if (RetVT == MVT::f32) 463 return UINTTOFP_I32_F32; 464 else if (RetVT == MVT::f64) 465 return UINTTOFP_I32_F64; 466 else if (RetVT == MVT::f80) 467 return UINTTOFP_I32_F80; 468 else if (RetVT == MVT::ppcf128) 469 return UINTTOFP_I32_PPCF128; 470 } else if (OpVT == MVT::i64) { 471 if (RetVT == MVT::f32) 472 return UINTTOFP_I64_F32; 473 else if (RetVT == MVT::f64) 474 return UINTTOFP_I64_F64; 475 else if (RetVT == MVT::f80) 476 return UINTTOFP_I64_F80; 477 else if (RetVT == MVT::ppcf128) 478 return UINTTOFP_I64_PPCF128; 479 } else if (OpVT == MVT::i128) { 480 if (RetVT == MVT::f32) 481 return UINTTOFP_I128_F32; 482 else if (RetVT == MVT::f64) 483 return UINTTOFP_I128_F64; 484 else if (RetVT == MVT::f80) 485 return UINTTOFP_I128_F80; 486 else if (RetVT == MVT::ppcf128) 487 return UINTTOFP_I128_PPCF128; 488 } 489 return UNKNOWN_LIBCALL; 490} 491 492/// InitCmpLibcallCCs - Set default comparison libcall CC. 493/// 494static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 495 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 496 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 497 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 498 CCs[RTLIB::UNE_F32] = ISD::SETNE; 499 CCs[RTLIB::UNE_F64] = ISD::SETNE; 500 CCs[RTLIB::OGE_F32] = ISD::SETGE; 501 CCs[RTLIB::OGE_F64] = ISD::SETGE; 502 CCs[RTLIB::OLT_F32] = ISD::SETLT; 503 CCs[RTLIB::OLT_F64] = ISD::SETLT; 504 CCs[RTLIB::OLE_F32] = ISD::SETLE; 505 CCs[RTLIB::OLE_F64] = ISD::SETLE; 506 CCs[RTLIB::OGT_F32] = ISD::SETGT; 507 CCs[RTLIB::OGT_F64] = ISD::SETGT; 508 CCs[RTLIB::UO_F32] = ISD::SETNE; 509 CCs[RTLIB::UO_F64] = ISD::SETNE; 510 CCs[RTLIB::O_F32] = ISD::SETEQ; 511 CCs[RTLIB::O_F64] = ISD::SETEQ; 512} 513 514/// NOTE: The constructor takes ownership of TLOF. 515TargetLowering::TargetLowering(const TargetMachine &tm, 516 const TargetLoweringObjectFile *tlof) 517 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 518 // All operations default to being supported. 519 memset(OpActions, 0, sizeof(OpActions)); 520 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 521 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 522 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 523 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 524 525 // Set default actions for various operations. 526 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 527 // Default all indexed load / store to expand. 528 for (unsigned IM = (unsigned)ISD::PRE_INC; 529 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 530 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 531 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 532 } 533 534 // These operations default to expand. 535 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 536 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 537 } 538 539 // Most targets ignore the @llvm.prefetch intrinsic. 540 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 541 542 // ConstantFP nodes default to expand. Targets can either change this to 543 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 544 // to optimize expansions for certain constants. 545 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 546 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 547 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 548 549 // These library functions default to expand. 550 setOperationAction(ISD::FLOG , MVT::f64, Expand); 551 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 552 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 553 setOperationAction(ISD::FEXP , MVT::f64, Expand); 554 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 555 setOperationAction(ISD::FLOG , MVT::f32, Expand); 556 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 557 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 558 setOperationAction(ISD::FEXP , MVT::f32, Expand); 559 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 560 561 // Default ISD::TRAP to expand (which turns it into abort). 562 setOperationAction(ISD::TRAP, MVT::Other, Expand); 563 564 IsLittleEndian = TD->isLittleEndian(); 565 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 566 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 567 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 568 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 569 benefitFromCodePlacementOpt = false; 570 UseUnderscoreSetJmp = false; 571 UseUnderscoreLongJmp = false; 572 SelectIsExpensive = false; 573 IntDivIsCheap = false; 574 Pow2DivIsCheap = false; 575 JumpIsExpensive = false; 576 StackPointerRegisterToSaveRestore = 0; 577 ExceptionPointerRegister = 0; 578 ExceptionSelectorRegister = 0; 579 BooleanContents = UndefinedBooleanContent; 580 SchedPreferenceInfo = Sched::Latency; 581 JumpBufSize = 0; 582 JumpBufAlignment = 0; 583 PrefLoopAlignment = 0; 584 MinStackArgumentAlignment = 1; 585 ShouldFoldAtomicFences = false; 586 587 InitLibcallNames(LibcallRoutineNames); 588 InitCmpLibcallCCs(CmpLibcallCCs); 589 InitLibcallCallingConvs(LibcallCallingConvs); 590} 591 592TargetLowering::~TargetLowering() { 593 delete &TLOF; 594} 595 596/// canOpTrap - Returns true if the operation can trap for the value type. 597/// VT must be a legal type. 598bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 599 assert(isTypeLegal(VT)); 600 switch (Op) { 601 default: 602 return false; 603 case ISD::FDIV: 604 case ISD::FREM: 605 case ISD::SDIV: 606 case ISD::UDIV: 607 case ISD::SREM: 608 case ISD::UREM: 609 return true; 610 } 611} 612 613 614static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 615 unsigned &NumIntermediates, 616 EVT &RegisterVT, 617 TargetLowering *TLI) { 618 // Figure out the right, legal destination reg to copy into. 619 unsigned NumElts = VT.getVectorNumElements(); 620 MVT EltTy = VT.getVectorElementType(); 621 622 unsigned NumVectorRegs = 1; 623 624 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 625 // could break down into LHS/RHS like LegalizeDAG does. 626 if (!isPowerOf2_32(NumElts)) { 627 NumVectorRegs = NumElts; 628 NumElts = 1; 629 } 630 631 // Divide the input until we get to a supported size. This will always 632 // end with a scalar if the target doesn't support vectors. 633 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 634 NumElts >>= 1; 635 NumVectorRegs <<= 1; 636 } 637 638 NumIntermediates = NumVectorRegs; 639 640 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 641 if (!TLI->isTypeLegal(NewVT)) 642 NewVT = EltTy; 643 IntermediateVT = NewVT; 644 645 EVT DestVT = TLI->getRegisterType(NewVT); 646 RegisterVT = DestVT; 647 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 648 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 649 650 // Otherwise, promotion or legal types use the same number of registers as 651 // the vector decimated to the appropriate level. 652 return NumVectorRegs; 653} 654 655/// isLegalRC - Return true if the value types that can be represented by the 656/// specified register class are all legal. 657bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const { 658 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 659 I != E; ++I) { 660 if (isTypeLegal(*I)) 661 return true; 662 } 663 return false; 664} 665 666/// hasLegalSuperRegRegClasses - Return true if the specified register class 667/// has one or more super-reg register classes that are legal. 668bool 669TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{ 670 if (*RC->superregclasses_begin() == 0) 671 return false; 672 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 673 E = RC->superregclasses_end(); I != E; ++I) { 674 const TargetRegisterClass *RRC = *I; 675 if (isLegalRC(RRC)) 676 return true; 677 } 678 return false; 679} 680 681/// findRepresentativeClass - Return the largest legal super-reg register class 682/// of the register class for the specified type and its associated "cost". 683std::pair<const TargetRegisterClass*, uint8_t> 684TargetLowering::findRepresentativeClass(EVT VT) const { 685 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 686 if (!RC) 687 return std::make_pair(RC, 0); 688 const TargetRegisterClass *BestRC = RC; 689 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 690 E = RC->superregclasses_end(); I != E; ++I) { 691 const TargetRegisterClass *RRC = *I; 692 if (RRC->isASubClass() || !isLegalRC(RRC)) 693 continue; 694 if (!hasLegalSuperRegRegClasses(RRC)) 695 return std::make_pair(RRC, 1); 696 BestRC = RRC; 697 } 698 return std::make_pair(BestRC, 1); 699} 700 701 702/// computeRegisterProperties - Once all of the register classes are added, 703/// this allows us to compute derived properties we expose. 704void TargetLowering::computeRegisterProperties() { 705 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 706 "Too many value types for ValueTypeActions to hold!"); 707 708 // Everything defaults to needing one register. 709 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 710 NumRegistersForVT[i] = 1; 711 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 712 } 713 // ...except isVoid, which doesn't need any registers. 714 NumRegistersForVT[MVT::isVoid] = 0; 715 716 // Find the largest integer register class. 717 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 718 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 719 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 720 721 // Every integer value type larger than this largest register takes twice as 722 // many registers to represent as the previous ValueType. 723 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 724 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 725 if (!ExpandedVT.isInteger()) 726 break; 727 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 728 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 729 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 730 ValueTypeActions.setTypeAction(ExpandedVT, Expand); 731 } 732 733 // Inspect all of the ValueType's smaller than the largest integer 734 // register to see which ones need promotion. 735 unsigned LegalIntReg = LargestIntReg; 736 for (unsigned IntReg = LargestIntReg - 1; 737 IntReg >= (unsigned)MVT::i1; --IntReg) { 738 EVT IVT = (MVT::SimpleValueType)IntReg; 739 if (isTypeLegal(IVT)) { 740 LegalIntReg = IntReg; 741 } else { 742 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 743 (MVT::SimpleValueType)LegalIntReg; 744 ValueTypeActions.setTypeAction(IVT, Promote); 745 } 746 } 747 748 // ppcf128 type is really two f64's. 749 if (!isTypeLegal(MVT::ppcf128)) { 750 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 751 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 752 TransformToType[MVT::ppcf128] = MVT::f64; 753 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 754 } 755 756 // Decide how to handle f64. If the target does not have native f64 support, 757 // expand it to i64 and we will be generating soft float library calls. 758 if (!isTypeLegal(MVT::f64)) { 759 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 760 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 761 TransformToType[MVT::f64] = MVT::i64; 762 ValueTypeActions.setTypeAction(MVT::f64, Expand); 763 } 764 765 // Decide how to handle f32. If the target does not have native support for 766 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 767 if (!isTypeLegal(MVT::f32)) { 768 if (isTypeLegal(MVT::f64)) { 769 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 770 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 771 TransformToType[MVT::f32] = MVT::f64; 772 ValueTypeActions.setTypeAction(MVT::f32, Promote); 773 } else { 774 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 775 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 776 TransformToType[MVT::f32] = MVT::i32; 777 ValueTypeActions.setTypeAction(MVT::f32, Expand); 778 } 779 } 780 781 // Loop over all of the vector value types to see which need transformations. 782 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 783 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 784 MVT VT = (MVT::SimpleValueType)i; 785 if (isTypeLegal(VT)) continue; 786 787 // Determine if there is a legal wider type. If so, we should promote to 788 // that wider vector type. 789 EVT EltVT = VT.getVectorElementType(); 790 unsigned NElts = VT.getVectorNumElements(); 791 if (NElts != 1) { 792 bool IsLegalWiderType = false; 793 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 794 EVT SVT = (MVT::SimpleValueType)nVT; 795 if (SVT.getVectorElementType() == EltVT && 796 SVT.getVectorNumElements() > NElts && 797 isTypeLegal(SVT)) { 798 TransformToType[i] = SVT; 799 RegisterTypeForVT[i] = SVT; 800 NumRegistersForVT[i] = 1; 801 ValueTypeActions.setTypeAction(VT, Promote); 802 IsLegalWiderType = true; 803 break; 804 } 805 } 806 if (IsLegalWiderType) continue; 807 } 808 809 MVT IntermediateVT; 810 EVT RegisterVT; 811 unsigned NumIntermediates; 812 NumRegistersForVT[i] = 813 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 814 RegisterVT, this); 815 RegisterTypeForVT[i] = RegisterVT; 816 817 EVT NVT = VT.getPow2VectorType(); 818 if (NVT == VT) { 819 // Type is already a power of 2. The default action is to split. 820 TransformToType[i] = MVT::Other; 821 ValueTypeActions.setTypeAction(VT, Expand); 822 } else { 823 TransformToType[i] = NVT; 824 ValueTypeActions.setTypeAction(VT, Promote); 825 } 826 } 827 828 // Determine the 'representative' register class for each value type. 829 // An representative register class is the largest (meaning one which is 830 // not a sub-register class / subreg register class) legal register class for 831 // a group of value types. For example, on i386, i8, i16, and i32 832 // representative would be GR32; while on x86_64 it's GR64. 833 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 834 const TargetRegisterClass* RRC; 835 uint8_t Cost; 836 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 837 RepRegClassForVT[i] = RRC; 838 RepRegClassCostForVT[i] = Cost; 839 } 840} 841 842const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 843 return NULL; 844} 845 846 847MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 848 return PointerTy.SimpleTy; 849} 850 851MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 852 return MVT::i32; // return the default value 853} 854 855/// getVectorTypeBreakdown - Vector types are broken down into some number of 856/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 857/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 858/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 859/// 860/// This method returns the number of registers needed, and the VT for each 861/// register. It also returns the VT and quantity of the intermediate values 862/// before they are promoted/expanded. 863/// 864unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 865 EVT &IntermediateVT, 866 unsigned &NumIntermediates, 867 EVT &RegisterVT) const { 868 unsigned NumElts = VT.getVectorNumElements(); 869 870 // If there is a wider vector type with the same element type as this one, 871 // we should widen to that legal vector type. This handles things like 872 // <2 x float> -> <4 x float>. 873 if (NumElts != 1 && getTypeAction(VT) == Promote) { 874 RegisterVT = getTypeToTransformTo(Context, VT); 875 if (isTypeLegal(RegisterVT)) { 876 IntermediateVT = RegisterVT; 877 NumIntermediates = 1; 878 return 1; 879 } 880 } 881 882 // Figure out the right, legal destination reg to copy into. 883 EVT EltTy = VT.getVectorElementType(); 884 885 unsigned NumVectorRegs = 1; 886 887 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 888 // could break down into LHS/RHS like LegalizeDAG does. 889 if (!isPowerOf2_32(NumElts)) { 890 NumVectorRegs = NumElts; 891 NumElts = 1; 892 } 893 894 // Divide the input until we get to a supported size. This will always 895 // end with a scalar if the target doesn't support vectors. 896 while (NumElts > 1 && !isTypeLegal( 897 EVT::getVectorVT(Context, EltTy, NumElts))) { 898 NumElts >>= 1; 899 NumVectorRegs <<= 1; 900 } 901 902 NumIntermediates = NumVectorRegs; 903 904 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 905 if (!isTypeLegal(NewVT)) 906 NewVT = EltTy; 907 IntermediateVT = NewVT; 908 909 EVT DestVT = getRegisterType(Context, NewVT); 910 RegisterVT = DestVT; 911 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 912 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 913 914 // Otherwise, promotion or legal types use the same number of registers as 915 // the vector decimated to the appropriate level. 916 return NumVectorRegs; 917} 918 919/// Get the EVTs and ArgFlags collections that represent the legalized return 920/// type of the given function. This does not require a DAG or a return value, 921/// and is suitable for use before any DAGs for the function are constructed. 922/// TODO: Move this out of TargetLowering.cpp. 923void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr, 924 SmallVectorImpl<ISD::OutputArg> &Outs, 925 const TargetLowering &TLI, 926 SmallVectorImpl<uint64_t> *Offsets) { 927 SmallVector<EVT, 4> ValueVTs; 928 ComputeValueVTs(TLI, ReturnType, ValueVTs); 929 unsigned NumValues = ValueVTs.size(); 930 if (NumValues == 0) return; 931 unsigned Offset = 0; 932 933 for (unsigned j = 0, f = NumValues; j != f; ++j) { 934 EVT VT = ValueVTs[j]; 935 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 936 937 if (attr & Attribute::SExt) 938 ExtendKind = ISD::SIGN_EXTEND; 939 else if (attr & Attribute::ZExt) 940 ExtendKind = ISD::ZERO_EXTEND; 941 942 // FIXME: C calling convention requires the return type to be promoted to 943 // at least 32-bit. But this is not necessary for non-C calling 944 // conventions. The frontend should mark functions whose return values 945 // require promoting with signext or zeroext attributes. 946 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 947 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 948 if (VT.bitsLT(MinVT)) 949 VT = MinVT; 950 } 951 952 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 953 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 954 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 955 PartVT.getTypeForEVT(ReturnType->getContext())); 956 957 // 'inreg' on function refers to return value 958 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 959 if (attr & Attribute::InReg) 960 Flags.setInReg(); 961 962 // Propagate extension type if any 963 if (attr & Attribute::SExt) 964 Flags.setSExt(); 965 else if (attr & Attribute::ZExt) 966 Flags.setZExt(); 967 968 for (unsigned i = 0; i < NumParts; ++i) { 969 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true)); 970 if (Offsets) { 971 Offsets->push_back(Offset); 972 Offset += PartSize; 973 } 974 } 975 } 976} 977 978/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 979/// function arguments in the caller parameter area. This is the actual 980/// alignment, not its logarithm. 981unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 982 return TD->getCallFrameTypeAlignment(Ty); 983} 984 985/// getJumpTableEncoding - Return the entry encoding for a jump table in the 986/// current function. The returned value is a member of the 987/// MachineJumpTableInfo::JTEntryKind enum. 988unsigned TargetLowering::getJumpTableEncoding() const { 989 // In non-pic modes, just use the address of a block. 990 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 991 return MachineJumpTableInfo::EK_BlockAddress; 992 993 // In PIC mode, if the target supports a GPRel32 directive, use it. 994 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 995 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 996 997 // Otherwise, use a label difference. 998 return MachineJumpTableInfo::EK_LabelDifference32; 999} 1000 1001SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1002 SelectionDAG &DAG) const { 1003 // If our PIC model is GP relative, use the global offset table as the base. 1004 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 1005 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 1006 return Table; 1007} 1008 1009/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1010/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1011/// MCExpr. 1012const MCExpr * 1013TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1014 unsigned JTI,MCContext &Ctx) const{ 1015 // The normal PIC reloc base is the label at the start of the jump table. 1016 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 1017} 1018 1019bool 1020TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1021 // Assume that everything is safe in static mode. 1022 if (getTargetMachine().getRelocationModel() == Reloc::Static) 1023 return true; 1024 1025 // In dynamic-no-pic mode, assume that known defined values are safe. 1026 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 1027 GA && 1028 !GA->getGlobal()->isDeclaration() && 1029 !GA->getGlobal()->isWeakForLinker()) 1030 return true; 1031 1032 // Otherwise assume nothing is safe. 1033 return false; 1034} 1035 1036//===----------------------------------------------------------------------===// 1037// Optimization Methods 1038//===----------------------------------------------------------------------===// 1039 1040/// ShrinkDemandedConstant - Check to see if the specified operand of the 1041/// specified instruction is a constant integer. If so, check to see if there 1042/// are any bits set in the constant that are not demanded. If so, shrink the 1043/// constant and return true. 1044bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 1045 const APInt &Demanded) { 1046 DebugLoc dl = Op.getDebugLoc(); 1047 1048 // FIXME: ISD::SELECT, ISD::SELECT_CC 1049 switch (Op.getOpcode()) { 1050 default: break; 1051 case ISD::XOR: 1052 case ISD::AND: 1053 case ISD::OR: { 1054 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1055 if (!C) return false; 1056 1057 if (Op.getOpcode() == ISD::XOR && 1058 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 1059 return false; 1060 1061 // if we can expand it to have all bits set, do it 1062 if (C->getAPIntValue().intersects(~Demanded)) { 1063 EVT VT = Op.getValueType(); 1064 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 1065 DAG.getConstant(Demanded & 1066 C->getAPIntValue(), 1067 VT)); 1068 return CombineTo(Op, New); 1069 } 1070 1071 break; 1072 } 1073 } 1074 1075 return false; 1076} 1077 1078/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1079/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1080/// cast, but it could be generalized for targets with other types of 1081/// implicit widening casts. 1082bool 1083TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 1084 unsigned BitWidth, 1085 const APInt &Demanded, 1086 DebugLoc dl) { 1087 assert(Op.getNumOperands() == 2 && 1088 "ShrinkDemandedOp only supports binary operators!"); 1089 assert(Op.getNode()->getNumValues() == 1 && 1090 "ShrinkDemandedOp only supports nodes with one result!"); 1091 1092 // Don't do this if the node has another user, which may require the 1093 // full value. 1094 if (!Op.getNode()->hasOneUse()) 1095 return false; 1096 1097 // Search for the smallest integer type with free casts to and from 1098 // Op's type. For expedience, just check power-of-2 integer types. 1099 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1100 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 1101 if (!isPowerOf2_32(SmallVTBits)) 1102 SmallVTBits = NextPowerOf2(SmallVTBits); 1103 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 1104 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 1105 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 1106 TLI.isZExtFree(SmallVT, Op.getValueType())) { 1107 // We found a type with free casts. 1108 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 1109 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1110 Op.getNode()->getOperand(0)), 1111 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1112 Op.getNode()->getOperand(1))); 1113 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 1114 return CombineTo(Op, Z); 1115 } 1116 } 1117 return false; 1118} 1119 1120/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1121/// DemandedMask bits of the result of Op are ever used downstream. If we can 1122/// use this information to simplify Op, create a new simplified DAG node and 1123/// return true, returning the original and new nodes in Old and New. Otherwise, 1124/// analyze the expression and return a mask of KnownOne and KnownZero bits for 1125/// the expression (used to simplify the caller). The KnownZero/One bits may 1126/// only be accurate for those bits in the DemandedMask. 1127bool TargetLowering::SimplifyDemandedBits(SDValue Op, 1128 const APInt &DemandedMask, 1129 APInt &KnownZero, 1130 APInt &KnownOne, 1131 TargetLoweringOpt &TLO, 1132 unsigned Depth) const { 1133 unsigned BitWidth = DemandedMask.getBitWidth(); 1134 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1135 "Mask size mismatches value type size!"); 1136 APInt NewMask = DemandedMask; 1137 DebugLoc dl = Op.getDebugLoc(); 1138 1139 // Don't know anything. 1140 KnownZero = KnownOne = APInt(BitWidth, 0); 1141 1142 // Other users may use these bits. 1143 if (!Op.getNode()->hasOneUse()) { 1144 if (Depth != 0) { 1145 // If not at the root, Just compute the KnownZero/KnownOne bits to 1146 // simplify things downstream. 1147 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 1148 return false; 1149 } 1150 // If this is the root being simplified, allow it to have multiple uses, 1151 // just set the NewMask to all bits. 1152 NewMask = APInt::getAllOnesValue(BitWidth); 1153 } else if (DemandedMask == 0) { 1154 // Not demanding any bits from Op. 1155 if (Op.getOpcode() != ISD::UNDEF) 1156 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1157 return false; 1158 } else if (Depth == 6) { // Limit search depth. 1159 return false; 1160 } 1161 1162 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1163 switch (Op.getOpcode()) { 1164 case ISD::Constant: 1165 // We know all of the bits for a constant! 1166 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 1167 KnownZero = ~KnownOne & NewMask; 1168 return false; // Don't fall through, will infinitely loop. 1169 case ISD::AND: 1170 // If the RHS is a constant, check to see if the LHS would be zero without 1171 // using the bits from the RHS. Below, we use knowledge about the RHS to 1172 // simplify the LHS, here we're using information from the LHS to simplify 1173 // the RHS. 1174 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1175 APInt LHSZero, LHSOne; 1176 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1177 LHSZero, LHSOne, Depth+1); 1178 // If the LHS already has zeros where RHSC does, this and is dead. 1179 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1180 return TLO.CombineTo(Op, Op.getOperand(0)); 1181 // If any of the set bits in the RHS are known zero on the LHS, shrink 1182 // the constant. 1183 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1184 return true; 1185 } 1186 1187 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1188 KnownOne, TLO, Depth+1)) 1189 return true; 1190 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1191 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1192 KnownZero2, KnownOne2, TLO, Depth+1)) 1193 return true; 1194 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1195 1196 // If all of the demanded bits are known one on one side, return the other. 1197 // These bits cannot contribute to the result of the 'and'. 1198 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1199 return TLO.CombineTo(Op, Op.getOperand(0)); 1200 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1201 return TLO.CombineTo(Op, Op.getOperand(1)); 1202 // If all of the demanded bits in the inputs are known zeros, return zero. 1203 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1204 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1205 // If the RHS is a constant, see if we can simplify it. 1206 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1207 return true; 1208 // If the operation can be done in a smaller type, do so. 1209 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1210 return true; 1211 1212 // Output known-1 bits are only known if set in both the LHS & RHS. 1213 KnownOne &= KnownOne2; 1214 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1215 KnownZero |= KnownZero2; 1216 break; 1217 case ISD::OR: 1218 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1219 KnownOne, TLO, Depth+1)) 1220 return true; 1221 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1222 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1223 KnownZero2, KnownOne2, TLO, Depth+1)) 1224 return true; 1225 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1226 1227 // If all of the demanded bits are known zero on one side, return the other. 1228 // These bits cannot contribute to the result of the 'or'. 1229 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1230 return TLO.CombineTo(Op, Op.getOperand(0)); 1231 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1232 return TLO.CombineTo(Op, Op.getOperand(1)); 1233 // If all of the potentially set bits on one side are known to be set on 1234 // the other side, just use the 'other' side. 1235 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1236 return TLO.CombineTo(Op, Op.getOperand(0)); 1237 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1238 return TLO.CombineTo(Op, Op.getOperand(1)); 1239 // If the RHS is a constant, see if we can simplify it. 1240 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1241 return true; 1242 // If the operation can be done in a smaller type, do so. 1243 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1244 return true; 1245 1246 // Output known-0 bits are only known if clear in both the LHS & RHS. 1247 KnownZero &= KnownZero2; 1248 // Output known-1 are known to be set if set in either the LHS | RHS. 1249 KnownOne |= KnownOne2; 1250 break; 1251 case ISD::XOR: 1252 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1253 KnownOne, TLO, Depth+1)) 1254 return true; 1255 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1256 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1257 KnownOne2, TLO, Depth+1)) 1258 return true; 1259 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1260 1261 // If all of the demanded bits are known zero on one side, return the other. 1262 // These bits cannot contribute to the result of the 'xor'. 1263 if ((KnownZero & NewMask) == NewMask) 1264 return TLO.CombineTo(Op, Op.getOperand(0)); 1265 if ((KnownZero2 & NewMask) == NewMask) 1266 return TLO.CombineTo(Op, Op.getOperand(1)); 1267 // If the operation can be done in a smaller type, do so. 1268 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1269 return true; 1270 1271 // If all of the unknown bits are known to be zero on one side or the other 1272 // (but not both) turn this into an *inclusive* or. 1273 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1274 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1275 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1276 Op.getOperand(0), 1277 Op.getOperand(1))); 1278 1279 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1280 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1281 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1282 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1283 1284 // If all of the demanded bits on one side are known, and all of the set 1285 // bits on that side are also known to be set on the other side, turn this 1286 // into an AND, as we know the bits will be cleared. 1287 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1288 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1289 if ((KnownOne & KnownOne2) == KnownOne) { 1290 EVT VT = Op.getValueType(); 1291 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1292 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1293 Op.getOperand(0), ANDC)); 1294 } 1295 } 1296 1297 // If the RHS is a constant, see if we can simplify it. 1298 // for XOR, we prefer to force bits to 1 if they will make a -1. 1299 // if we can't force bits, try to shrink constant 1300 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1301 APInt Expanded = C->getAPIntValue() | (~NewMask); 1302 // if we can expand it to have all bits set, do it 1303 if (Expanded.isAllOnesValue()) { 1304 if (Expanded != C->getAPIntValue()) { 1305 EVT VT = Op.getValueType(); 1306 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1307 TLO.DAG.getConstant(Expanded, VT)); 1308 return TLO.CombineTo(Op, New); 1309 } 1310 // if it already has all the bits set, nothing to change 1311 // but don't shrink either! 1312 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1313 return true; 1314 } 1315 } 1316 1317 KnownZero = KnownZeroOut; 1318 KnownOne = KnownOneOut; 1319 break; 1320 case ISD::SELECT: 1321 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1322 KnownOne, TLO, Depth+1)) 1323 return true; 1324 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1325 KnownOne2, TLO, Depth+1)) 1326 return true; 1327 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1328 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1329 1330 // If the operands are constants, see if we can simplify them. 1331 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1332 return true; 1333 1334 // Only known if known in both the LHS and RHS. 1335 KnownOne &= KnownOne2; 1336 KnownZero &= KnownZero2; 1337 break; 1338 case ISD::SELECT_CC: 1339 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1340 KnownOne, TLO, Depth+1)) 1341 return true; 1342 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1343 KnownOne2, TLO, Depth+1)) 1344 return true; 1345 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1346 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1347 1348 // If the operands are constants, see if we can simplify them. 1349 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1350 return true; 1351 1352 // Only known if known in both the LHS and RHS. 1353 KnownOne &= KnownOne2; 1354 KnownZero &= KnownZero2; 1355 break; 1356 case ISD::SHL: 1357 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1358 unsigned ShAmt = SA->getZExtValue(); 1359 SDValue InOp = Op.getOperand(0); 1360 1361 // If the shift count is an invalid immediate, don't do anything. 1362 if (ShAmt >= BitWidth) 1363 break; 1364 1365 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1366 // single shift. We can do this if the bottom bits (which are shifted 1367 // out) are never demanded. 1368 if (InOp.getOpcode() == ISD::SRL && 1369 isa<ConstantSDNode>(InOp.getOperand(1))) { 1370 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1371 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1372 unsigned Opc = ISD::SHL; 1373 int Diff = ShAmt-C1; 1374 if (Diff < 0) { 1375 Diff = -Diff; 1376 Opc = ISD::SRL; 1377 } 1378 1379 SDValue NewSA = 1380 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1381 EVT VT = Op.getValueType(); 1382 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1383 InOp.getOperand(0), NewSA)); 1384 } 1385 } 1386 1387 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 1388 KnownZero, KnownOne, TLO, Depth+1)) 1389 return true; 1390 1391 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 1392 // are not demanded. This will likely allow the anyext to be folded away. 1393 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 1394 SDValue InnerOp = InOp.getNode()->getOperand(0); 1395 EVT InnerVT = InnerOp.getValueType(); 1396 if ((APInt::getHighBitsSet(BitWidth, 1397 BitWidth - InnerVT.getSizeInBits()) & 1398 DemandedMask) == 0 && 1399 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 1400 EVT ShTy = getShiftAmountTy(); 1401 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 1402 ShTy = InnerVT; 1403 SDValue NarrowShl = 1404 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 1405 TLO.DAG.getConstant(ShAmt, ShTy)); 1406 return 1407 TLO.CombineTo(Op, 1408 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 1409 NarrowShl)); 1410 } 1411 } 1412 1413 KnownZero <<= SA->getZExtValue(); 1414 KnownOne <<= SA->getZExtValue(); 1415 // low bits known zero. 1416 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1417 } 1418 break; 1419 case ISD::SRL: 1420 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1421 EVT VT = Op.getValueType(); 1422 unsigned ShAmt = SA->getZExtValue(); 1423 unsigned VTSize = VT.getSizeInBits(); 1424 SDValue InOp = Op.getOperand(0); 1425 1426 // If the shift count is an invalid immediate, don't do anything. 1427 if (ShAmt >= BitWidth) 1428 break; 1429 1430 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1431 // single shift. We can do this if the top bits (which are shifted out) 1432 // are never demanded. 1433 if (InOp.getOpcode() == ISD::SHL && 1434 isa<ConstantSDNode>(InOp.getOperand(1))) { 1435 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1436 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1437 unsigned Opc = ISD::SRL; 1438 int Diff = ShAmt-C1; 1439 if (Diff < 0) { 1440 Diff = -Diff; 1441 Opc = ISD::SHL; 1442 } 1443 1444 SDValue NewSA = 1445 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1446 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1447 InOp.getOperand(0), NewSA)); 1448 } 1449 } 1450 1451 // Compute the new bits that are at the top now. 1452 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1453 KnownZero, KnownOne, TLO, Depth+1)) 1454 return true; 1455 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1456 KnownZero = KnownZero.lshr(ShAmt); 1457 KnownOne = KnownOne.lshr(ShAmt); 1458 1459 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1460 KnownZero |= HighBits; // High bits known zero. 1461 } 1462 break; 1463 case ISD::SRA: 1464 // If this is an arithmetic shift right and only the low-bit is set, we can 1465 // always convert this into a logical shr, even if the shift amount is 1466 // variable. The low bit of the shift cannot be an input sign bit unless 1467 // the shift amount is >= the size of the datatype, which is undefined. 1468 if (DemandedMask == 1) 1469 return TLO.CombineTo(Op, 1470 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1471 Op.getOperand(0), Op.getOperand(1))); 1472 1473 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1474 EVT VT = Op.getValueType(); 1475 unsigned ShAmt = SA->getZExtValue(); 1476 1477 // If the shift count is an invalid immediate, don't do anything. 1478 if (ShAmt >= BitWidth) 1479 break; 1480 1481 APInt InDemandedMask = (NewMask << ShAmt); 1482 1483 // If any of the demanded bits are produced by the sign extension, we also 1484 // demand the input sign bit. 1485 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1486 if (HighBits.intersects(NewMask)) 1487 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1488 1489 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1490 KnownZero, KnownOne, TLO, Depth+1)) 1491 return true; 1492 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1493 KnownZero = KnownZero.lshr(ShAmt); 1494 KnownOne = KnownOne.lshr(ShAmt); 1495 1496 // Handle the sign bit, adjusted to where it is now in the mask. 1497 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1498 1499 // If the input sign bit is known to be zero, or if none of the top bits 1500 // are demanded, turn this into an unsigned shift right. 1501 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1502 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1503 Op.getOperand(0), 1504 Op.getOperand(1))); 1505 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1506 KnownOne |= HighBits; 1507 } 1508 } 1509 break; 1510 case ISD::SIGN_EXTEND_INREG: { 1511 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1512 1513 // Sign extension. Compute the demanded bits in the result that are not 1514 // present in the input. 1515 APInt NewBits = 1516 APInt::getHighBitsSet(BitWidth, 1517 BitWidth - EVT.getScalarType().getSizeInBits()); 1518 1519 // If none of the extended bits are demanded, eliminate the sextinreg. 1520 if ((NewBits & NewMask) == 0) 1521 return TLO.CombineTo(Op, Op.getOperand(0)); 1522 1523 APInt InSignBit = 1524 APInt::getSignBit(EVT.getScalarType().getSizeInBits()).zext(BitWidth); 1525 APInt InputDemandedBits = 1526 APInt::getLowBitsSet(BitWidth, 1527 EVT.getScalarType().getSizeInBits()) & 1528 NewMask; 1529 1530 // Since the sign extended bits are demanded, we know that the sign 1531 // bit is demanded. 1532 InputDemandedBits |= InSignBit; 1533 1534 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1535 KnownZero, KnownOne, TLO, Depth+1)) 1536 return true; 1537 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1538 1539 // If the sign bit of the input is known set or clear, then we know the 1540 // top bits of the result. 1541 1542 // If the input sign bit is known zero, convert this into a zero extension. 1543 if (KnownZero.intersects(InSignBit)) 1544 return TLO.CombineTo(Op, 1545 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1546 1547 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1548 KnownOne |= NewBits; 1549 KnownZero &= ~NewBits; 1550 } else { // Input sign bit unknown 1551 KnownZero &= ~NewBits; 1552 KnownOne &= ~NewBits; 1553 } 1554 break; 1555 } 1556 case ISD::ZERO_EXTEND: { 1557 unsigned OperandBitWidth = 1558 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1559 APInt InMask = NewMask.trunc(OperandBitWidth); 1560 1561 // If none of the top bits are demanded, convert this into an any_extend. 1562 APInt NewBits = 1563 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1564 if (!NewBits.intersects(NewMask)) 1565 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1566 Op.getValueType(), 1567 Op.getOperand(0))); 1568 1569 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1570 KnownZero, KnownOne, TLO, Depth+1)) 1571 return true; 1572 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1573 KnownZero = KnownZero.zext(BitWidth); 1574 KnownOne = KnownOne.zext(BitWidth); 1575 KnownZero |= NewBits; 1576 break; 1577 } 1578 case ISD::SIGN_EXTEND: { 1579 EVT InVT = Op.getOperand(0).getValueType(); 1580 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1581 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1582 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1583 APInt NewBits = ~InMask & NewMask; 1584 1585 // If none of the top bits are demanded, convert this into an any_extend. 1586 if (NewBits == 0) 1587 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1588 Op.getValueType(), 1589 Op.getOperand(0))); 1590 1591 // Since some of the sign extended bits are demanded, we know that the sign 1592 // bit is demanded. 1593 APInt InDemandedBits = InMask & NewMask; 1594 InDemandedBits |= InSignBit; 1595 InDemandedBits = InDemandedBits.trunc(InBits); 1596 1597 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1598 KnownOne, TLO, Depth+1)) 1599 return true; 1600 KnownZero = KnownZero.zext(BitWidth); 1601 KnownOne = KnownOne.zext(BitWidth); 1602 1603 // If the sign bit is known zero, convert this to a zero extend. 1604 if (KnownZero.intersects(InSignBit)) 1605 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1606 Op.getValueType(), 1607 Op.getOperand(0))); 1608 1609 // If the sign bit is known one, the top bits match. 1610 if (KnownOne.intersects(InSignBit)) { 1611 KnownOne |= NewBits; 1612 KnownZero &= ~NewBits; 1613 } else { // Otherwise, top bits aren't known. 1614 KnownOne &= ~NewBits; 1615 KnownZero &= ~NewBits; 1616 } 1617 break; 1618 } 1619 case ISD::ANY_EXTEND: { 1620 unsigned OperandBitWidth = 1621 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1622 APInt InMask = NewMask.trunc(OperandBitWidth); 1623 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1624 KnownZero, KnownOne, TLO, Depth+1)) 1625 return true; 1626 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1627 KnownZero = KnownZero.zext(BitWidth); 1628 KnownOne = KnownOne.zext(BitWidth); 1629 break; 1630 } 1631 case ISD::TRUNCATE: { 1632 // Simplify the input, using demanded bit information, and compute the known 1633 // zero/one bits live out. 1634 unsigned OperandBitWidth = 1635 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1636 APInt TruncMask = NewMask.zext(OperandBitWidth); 1637 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1638 KnownZero, KnownOne, TLO, Depth+1)) 1639 return true; 1640 KnownZero = KnownZero.trunc(BitWidth); 1641 KnownOne = KnownOne.trunc(BitWidth); 1642 1643 // If the input is only used by this truncate, see if we can shrink it based 1644 // on the known demanded bits. 1645 if (Op.getOperand(0).getNode()->hasOneUse()) { 1646 SDValue In = Op.getOperand(0); 1647 switch (In.getOpcode()) { 1648 default: break; 1649 case ISD::SRL: 1650 // Shrink SRL by a constant if none of the high bits shifted in are 1651 // demanded. 1652 if (TLO.LegalTypes() && 1653 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1654 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1655 // undesirable. 1656 break; 1657 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1658 if (!ShAmt) 1659 break; 1660 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1661 OperandBitWidth - BitWidth); 1662 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 1663 1664 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1665 // None of the shifted in bits are needed. Add a truncate of the 1666 // shift input, then shift it. 1667 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1668 Op.getValueType(), 1669 In.getOperand(0)); 1670 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1671 Op.getValueType(), 1672 NewTrunc, 1673 In.getOperand(1))); 1674 } 1675 break; 1676 } 1677 } 1678 1679 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1680 break; 1681 } 1682 case ISD::AssertZext: { 1683 // Demand all the bits of the input that are demanded in the output. 1684 // The low bits are obvious; the high bits are demanded because we're 1685 // asserting that they're zero here. 1686 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, 1687 KnownZero, KnownOne, TLO, Depth+1)) 1688 return true; 1689 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1690 1691 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1692 APInt InMask = APInt::getLowBitsSet(BitWidth, 1693 VT.getSizeInBits()); 1694 KnownZero |= ~InMask & NewMask; 1695 break; 1696 } 1697 case ISD::BITCAST: 1698#if 0 1699 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1700 // is demanded, turn this into a FGETSIGN. 1701 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) && 1702 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1703 !MVT::isVector(Op.getOperand(0).getValueType())) { 1704 // Only do this xform if FGETSIGN is valid or if before legalize. 1705 if (!TLO.AfterLegalize || 1706 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1707 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1708 // place. We expect the SHL to be eliminated by other optimizations. 1709 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1710 Op.getOperand(0)); 1711 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1712 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1713 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1714 Sign, ShAmt)); 1715 } 1716 } 1717#endif 1718 break; 1719 case ISD::ADD: 1720 case ISD::MUL: 1721 case ISD::SUB: { 1722 // Add, Sub, and Mul don't demand any bits in positions beyond that 1723 // of the highest bit demanded of them. 1724 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1725 BitWidth - NewMask.countLeadingZeros()); 1726 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1727 KnownOne2, TLO, Depth+1)) 1728 return true; 1729 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1730 KnownOne2, TLO, Depth+1)) 1731 return true; 1732 // See if the operation should be performed at a smaller bit width. 1733 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1734 return true; 1735 } 1736 // FALL THROUGH 1737 default: 1738 // Just use ComputeMaskedBits to compute output bits. 1739 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1740 break; 1741 } 1742 1743 // If we know the value of all of the demanded bits, return this as a 1744 // constant. 1745 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1746 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1747 1748 return false; 1749} 1750 1751/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1752/// in Mask are known to be either zero or one and return them in the 1753/// KnownZero/KnownOne bitsets. 1754void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1755 const APInt &Mask, 1756 APInt &KnownZero, 1757 APInt &KnownOne, 1758 const SelectionDAG &DAG, 1759 unsigned Depth) const { 1760 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1761 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1762 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1763 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1764 "Should use MaskedValueIsZero if you don't know whether Op" 1765 " is a target node!"); 1766 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1767} 1768 1769/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1770/// targets that want to expose additional information about sign bits to the 1771/// DAG Combiner. 1772unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1773 unsigned Depth) const { 1774 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1775 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1776 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1777 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1778 "Should use ComputeNumSignBits if you don't know whether Op" 1779 " is a target node!"); 1780 return 1; 1781} 1782 1783/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1784/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1785/// determine which bit is set. 1786/// 1787static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1788 // A left-shift of a constant one will have exactly one bit set, because 1789 // shifting the bit off the end is undefined. 1790 if (Val.getOpcode() == ISD::SHL) 1791 if (ConstantSDNode *C = 1792 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1793 if (C->getAPIntValue() == 1) 1794 return true; 1795 1796 // Similarly, a right-shift of a constant sign-bit will have exactly 1797 // one bit set. 1798 if (Val.getOpcode() == ISD::SRL) 1799 if (ConstantSDNode *C = 1800 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1801 if (C->getAPIntValue().isSignBit()) 1802 return true; 1803 1804 // More could be done here, though the above checks are enough 1805 // to handle some common cases. 1806 1807 // Fall back to ComputeMaskedBits to catch other known cases. 1808 EVT OpVT = Val.getValueType(); 1809 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1810 APInt Mask = APInt::getAllOnesValue(BitWidth); 1811 APInt KnownZero, KnownOne; 1812 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1813 return (KnownZero.countPopulation() == BitWidth - 1) && 1814 (KnownOne.countPopulation() == 1); 1815} 1816 1817/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1818/// and cc. If it is unable to simplify it, return a null SDValue. 1819SDValue 1820TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1821 ISD::CondCode Cond, bool foldBooleans, 1822 DAGCombinerInfo &DCI, DebugLoc dl) const { 1823 SelectionDAG &DAG = DCI.DAG; 1824 LLVMContext &Context = *DAG.getContext(); 1825 1826 // These setcc operations always fold. 1827 switch (Cond) { 1828 default: break; 1829 case ISD::SETFALSE: 1830 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1831 case ISD::SETTRUE: 1832 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1833 } 1834 1835 if (isa<ConstantSDNode>(N0.getNode())) { 1836 // Ensure that the constant occurs on the RHS, and fold constant 1837 // comparisons. 1838 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1839 } 1840 1841 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1842 const APInt &C1 = N1C->getAPIntValue(); 1843 1844 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1845 // equality comparison, then we're just comparing whether X itself is 1846 // zero. 1847 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1848 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1849 N0.getOperand(1).getOpcode() == ISD::Constant) { 1850 const APInt &ShAmt 1851 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1852 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1853 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1854 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1855 // (srl (ctlz x), 5) == 0 -> X != 0 1856 // (srl (ctlz x), 5) != 1 -> X != 0 1857 Cond = ISD::SETNE; 1858 } else { 1859 // (srl (ctlz x), 5) != 0 -> X == 0 1860 // (srl (ctlz x), 5) == 1 -> X == 0 1861 Cond = ISD::SETEQ; 1862 } 1863 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1864 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1865 Zero, Cond); 1866 } 1867 } 1868 1869 // If the LHS is '(and load, const)', the RHS is 0, 1870 // the test is for equality or unsigned, and all 1 bits of the const are 1871 // in the same partial word, see if we can shorten the load. 1872 if (DCI.isBeforeLegalize() && 1873 N0.getOpcode() == ISD::AND && C1 == 0 && 1874 N0.getNode()->hasOneUse() && 1875 isa<LoadSDNode>(N0.getOperand(0)) && 1876 N0.getOperand(0).getNode()->hasOneUse() && 1877 isa<ConstantSDNode>(N0.getOperand(1))) { 1878 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1879 APInt bestMask; 1880 unsigned bestWidth = 0, bestOffset = 0; 1881 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1882 unsigned origWidth = N0.getValueType().getSizeInBits(); 1883 unsigned maskWidth = origWidth; 1884 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1885 // 8 bits, but have to be careful... 1886 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1887 origWidth = Lod->getMemoryVT().getSizeInBits(); 1888 const APInt &Mask = 1889 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1890 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1891 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1892 for (unsigned offset=0; offset<origWidth/width; offset++) { 1893 if ((newMask & Mask) == Mask) { 1894 if (!TD->isLittleEndian()) 1895 bestOffset = (origWidth/width - offset - 1) * (width/8); 1896 else 1897 bestOffset = (uint64_t)offset * (width/8); 1898 bestMask = Mask.lshr(offset * (width/8) * 8); 1899 bestWidth = width; 1900 break; 1901 } 1902 newMask = newMask << width; 1903 } 1904 } 1905 } 1906 if (bestWidth) { 1907 EVT newVT = EVT::getIntegerVT(Context, bestWidth); 1908 if (newVT.isRound()) { 1909 EVT PtrType = Lod->getOperand(1).getValueType(); 1910 SDValue Ptr = Lod->getBasePtr(); 1911 if (bestOffset != 0) 1912 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1913 DAG.getConstant(bestOffset, PtrType)); 1914 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1915 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1916 Lod->getPointerInfo().getWithOffset(bestOffset), 1917 false, false, NewAlign); 1918 return DAG.getSetCC(dl, VT, 1919 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1920 DAG.getConstant(bestMask.trunc(bestWidth), 1921 newVT)), 1922 DAG.getConstant(0LL, newVT), Cond); 1923 } 1924 } 1925 } 1926 1927 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1928 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1929 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1930 1931 // If the comparison constant has bits in the upper part, the 1932 // zero-extended value could never match. 1933 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1934 C1.getBitWidth() - InSize))) { 1935 switch (Cond) { 1936 case ISD::SETUGT: 1937 case ISD::SETUGE: 1938 case ISD::SETEQ: return DAG.getConstant(0, VT); 1939 case ISD::SETULT: 1940 case ISD::SETULE: 1941 case ISD::SETNE: return DAG.getConstant(1, VT); 1942 case ISD::SETGT: 1943 case ISD::SETGE: 1944 // True if the sign bit of C1 is set. 1945 return DAG.getConstant(C1.isNegative(), VT); 1946 case ISD::SETLT: 1947 case ISD::SETLE: 1948 // True if the sign bit of C1 isn't set. 1949 return DAG.getConstant(C1.isNonNegative(), VT); 1950 default: 1951 break; 1952 } 1953 } 1954 1955 // Otherwise, we can perform the comparison with the low bits. 1956 switch (Cond) { 1957 case ISD::SETEQ: 1958 case ISD::SETNE: 1959 case ISD::SETUGT: 1960 case ISD::SETUGE: 1961 case ISD::SETULT: 1962 case ISD::SETULE: { 1963 EVT newVT = N0.getOperand(0).getValueType(); 1964 if (DCI.isBeforeLegalizeOps() || 1965 (isOperationLegal(ISD::SETCC, newVT) && 1966 getCondCodeAction(Cond, newVT)==Legal)) 1967 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1968 DAG.getConstant(C1.trunc(InSize), newVT), 1969 Cond); 1970 break; 1971 } 1972 default: 1973 break; // todo, be more careful with signed comparisons 1974 } 1975 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1976 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1977 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1978 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1979 EVT ExtDstTy = N0.getValueType(); 1980 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1981 1982 // If the constant doesn't fit into the number of bits for the source of 1983 // the sign extension, it is impossible for both sides to be equal. 1984 if (C1.getMinSignedBits() > ExtSrcTyBits) 1985 return DAG.getConstant(Cond == ISD::SETNE, VT); 1986 1987 SDValue ZextOp; 1988 EVT Op0Ty = N0.getOperand(0).getValueType(); 1989 if (Op0Ty == ExtSrcTy) { 1990 ZextOp = N0.getOperand(0); 1991 } else { 1992 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1993 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1994 DAG.getConstant(Imm, Op0Ty)); 1995 } 1996 if (!DCI.isCalledByLegalizer()) 1997 DCI.AddToWorklist(ZextOp.getNode()); 1998 // Otherwise, make this a use of a zext. 1999 return DAG.getSetCC(dl, VT, ZextOp, 2000 DAG.getConstant(C1 & APInt::getLowBitsSet( 2001 ExtDstTyBits, 2002 ExtSrcTyBits), 2003 ExtDstTy), 2004 Cond); 2005 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 2006 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2007 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 2008 if (N0.getOpcode() == ISD::SETCC && 2009 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 2010 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 2011 if (TrueWhenTrue) 2012 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 2013 // Invert the condition. 2014 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 2015 CC = ISD::getSetCCInverse(CC, 2016 N0.getOperand(0).getValueType().isInteger()); 2017 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 2018 } 2019 2020 if ((N0.getOpcode() == ISD::XOR || 2021 (N0.getOpcode() == ISD::AND && 2022 N0.getOperand(0).getOpcode() == ISD::XOR && 2023 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2024 isa<ConstantSDNode>(N0.getOperand(1)) && 2025 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 2026 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 2027 // can only do this if the top bits are known zero. 2028 unsigned BitWidth = N0.getValueSizeInBits(); 2029 if (DAG.MaskedValueIsZero(N0, 2030 APInt::getHighBitsSet(BitWidth, 2031 BitWidth-1))) { 2032 // Okay, get the un-inverted input value. 2033 SDValue Val; 2034 if (N0.getOpcode() == ISD::XOR) 2035 Val = N0.getOperand(0); 2036 else { 2037 assert(N0.getOpcode() == ISD::AND && 2038 N0.getOperand(0).getOpcode() == ISD::XOR); 2039 // ((X^1)&1)^1 -> X & 1 2040 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 2041 N0.getOperand(0).getOperand(0), 2042 N0.getOperand(1)); 2043 } 2044 2045 return DAG.getSetCC(dl, VT, Val, N1, 2046 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2047 } 2048 } else if (N1C->getAPIntValue() == 1 && 2049 (VT == MVT::i1 || 2050 getBooleanContents() == ZeroOrOneBooleanContent)) { 2051 SDValue Op0 = N0; 2052 if (Op0.getOpcode() == ISD::TRUNCATE) 2053 Op0 = Op0.getOperand(0); 2054 2055 if ((Op0.getOpcode() == ISD::XOR) && 2056 Op0.getOperand(0).getOpcode() == ISD::SETCC && 2057 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 2058 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 2059 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 2060 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 2061 Cond); 2062 } else if (Op0.getOpcode() == ISD::AND && 2063 isa<ConstantSDNode>(Op0.getOperand(1)) && 2064 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 2065 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 2066 if (Op0.getValueType().bitsGT(VT)) 2067 Op0 = DAG.getNode(ISD::AND, dl, VT, 2068 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 2069 DAG.getConstant(1, VT)); 2070 else if (Op0.getValueType().bitsLT(VT)) 2071 Op0 = DAG.getNode(ISD::AND, dl, VT, 2072 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 2073 DAG.getConstant(1, VT)); 2074 2075 return DAG.getSetCC(dl, VT, Op0, 2076 DAG.getConstant(0, Op0.getValueType()), 2077 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2078 } 2079 } 2080 } 2081 2082 APInt MinVal, MaxVal; 2083 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 2084 if (ISD::isSignedIntSetCC(Cond)) { 2085 MinVal = APInt::getSignedMinValue(OperandBitSize); 2086 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 2087 } else { 2088 MinVal = APInt::getMinValue(OperandBitSize); 2089 MaxVal = APInt::getMaxValue(OperandBitSize); 2090 } 2091 2092 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2093 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2094 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2095 // X >= C0 --> X > (C0-1) 2096 return DAG.getSetCC(dl, VT, N0, 2097 DAG.getConstant(C1-1, N1.getValueType()), 2098 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2099 } 2100 2101 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2102 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2103 // X <= C0 --> X < (C0+1) 2104 return DAG.getSetCC(dl, VT, N0, 2105 DAG.getConstant(C1+1, N1.getValueType()), 2106 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2107 } 2108 2109 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2110 return DAG.getConstant(0, VT); // X < MIN --> false 2111 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 2112 return DAG.getConstant(1, VT); // X >= MIN --> true 2113 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 2114 return DAG.getConstant(0, VT); // X > MAX --> false 2115 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 2116 return DAG.getConstant(1, VT); // X <= MAX --> true 2117 2118 // Canonicalize setgt X, Min --> setne X, Min 2119 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2120 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2121 // Canonicalize setlt X, Max --> setne X, Max 2122 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2123 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2124 2125 // If we have setult X, 1, turn it into seteq X, 0 2126 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2127 return DAG.getSetCC(dl, VT, N0, 2128 DAG.getConstant(MinVal, N0.getValueType()), 2129 ISD::SETEQ); 2130 // If we have setugt X, Max-1, turn it into seteq X, Max 2131 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2132 return DAG.getSetCC(dl, VT, N0, 2133 DAG.getConstant(MaxVal, N0.getValueType()), 2134 ISD::SETEQ); 2135 2136 // If we have "setcc X, C0", check to see if we can shrink the immediate 2137 // by changing cc. 2138 2139 // SETUGT X, SINTMAX -> SETLT X, 0 2140 if (Cond == ISD::SETUGT && 2141 C1 == APInt::getSignedMaxValue(OperandBitSize)) 2142 return DAG.getSetCC(dl, VT, N0, 2143 DAG.getConstant(0, N1.getValueType()), 2144 ISD::SETLT); 2145 2146 // SETULT X, SINTMIN -> SETGT X, -1 2147 if (Cond == ISD::SETULT && 2148 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2149 SDValue ConstMinusOne = 2150 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2151 N1.getValueType()); 2152 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2153 } 2154 2155 // Fold bit comparisons when we can. 2156 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2157 (VT == N0.getValueType() || 2158 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2159 N0.getOpcode() == ISD::AND) 2160 if (ConstantSDNode *AndRHS = 2161 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2162 EVT ShiftTy = DCI.isBeforeLegalize() ? 2163 getPointerTy() : getShiftAmountTy(); 2164 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2165 // Perform the xform if the AND RHS is a single bit. 2166 if (AndRHS->getAPIntValue().isPowerOf2()) { 2167 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2168 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2169 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2170 } 2171 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2172 // (X & 8) == 8 --> (X & 8) >> 3 2173 // Perform the xform if C1 is a single bit. 2174 if (C1.isPowerOf2()) { 2175 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2176 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2177 DAG.getConstant(C1.logBase2(), ShiftTy))); 2178 } 2179 } 2180 } 2181 } 2182 2183 if (isa<ConstantFPSDNode>(N0.getNode())) { 2184 // Constant fold or commute setcc. 2185 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2186 if (O.getNode()) return O; 2187 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2188 // If the RHS of an FP comparison is a constant, simplify it away in 2189 // some cases. 2190 if (CFP->getValueAPF().isNaN()) { 2191 // If an operand is known to be a nan, we can fold it. 2192 switch (ISD::getUnorderedFlavor(Cond)) { 2193 default: llvm_unreachable("Unknown flavor!"); 2194 case 0: // Known false. 2195 return DAG.getConstant(0, VT); 2196 case 1: // Known true. 2197 return DAG.getConstant(1, VT); 2198 case 2: // Undefined. 2199 return DAG.getUNDEF(VT); 2200 } 2201 } 2202 2203 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2204 // constant if knowing that the operand is non-nan is enough. We prefer to 2205 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2206 // materialize 0.0. 2207 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2208 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2209 2210 // If the condition is not legal, see if we can find an equivalent one 2211 // which is legal. 2212 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2213 // If the comparison was an awkward floating-point == or != and one of 2214 // the comparison operands is infinity or negative infinity, convert the 2215 // condition to a less-awkward <= or >=. 2216 if (CFP->getValueAPF().isInfinity()) { 2217 if (CFP->getValueAPF().isNegative()) { 2218 if (Cond == ISD::SETOEQ && 2219 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2220 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2221 if (Cond == ISD::SETUEQ && 2222 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2223 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2224 if (Cond == ISD::SETUNE && 2225 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2226 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2227 if (Cond == ISD::SETONE && 2228 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2229 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2230 } else { 2231 if (Cond == ISD::SETOEQ && 2232 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2233 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2234 if (Cond == ISD::SETUEQ && 2235 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2236 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2237 if (Cond == ISD::SETUNE && 2238 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2239 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2240 if (Cond == ISD::SETONE && 2241 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2242 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2243 } 2244 } 2245 } 2246 } 2247 2248 if (N0 == N1) { 2249 // We can always fold X == X for integer setcc's. 2250 if (N0.getValueType().isInteger()) 2251 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2252 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2253 if (UOF == 2) // FP operators that are undefined on NaNs. 2254 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2255 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2256 return DAG.getConstant(UOF, VT); 2257 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2258 // if it is not already. 2259 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2260 if (NewCond != Cond) 2261 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2262 } 2263 2264 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2265 N0.getValueType().isInteger()) { 2266 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2267 N0.getOpcode() == ISD::XOR) { 2268 // Simplify (X+Y) == (X+Z) --> Y == Z 2269 if (N0.getOpcode() == N1.getOpcode()) { 2270 if (N0.getOperand(0) == N1.getOperand(0)) 2271 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2272 if (N0.getOperand(1) == N1.getOperand(1)) 2273 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2274 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2275 // If X op Y == Y op X, try other combinations. 2276 if (N0.getOperand(0) == N1.getOperand(1)) 2277 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2278 Cond); 2279 if (N0.getOperand(1) == N1.getOperand(0)) 2280 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2281 Cond); 2282 } 2283 } 2284 2285 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2286 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2287 // Turn (X+C1) == C2 --> X == C2-C1 2288 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2289 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2290 DAG.getConstant(RHSC->getAPIntValue()- 2291 LHSR->getAPIntValue(), 2292 N0.getValueType()), Cond); 2293 } 2294 2295 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2296 if (N0.getOpcode() == ISD::XOR) 2297 // If we know that all of the inverted bits are zero, don't bother 2298 // performing the inversion. 2299 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2300 return 2301 DAG.getSetCC(dl, VT, N0.getOperand(0), 2302 DAG.getConstant(LHSR->getAPIntValue() ^ 2303 RHSC->getAPIntValue(), 2304 N0.getValueType()), 2305 Cond); 2306 } 2307 2308 // Turn (C1-X) == C2 --> X == C1-C2 2309 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2310 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2311 return 2312 DAG.getSetCC(dl, VT, N0.getOperand(1), 2313 DAG.getConstant(SUBC->getAPIntValue() - 2314 RHSC->getAPIntValue(), 2315 N0.getValueType()), 2316 Cond); 2317 } 2318 } 2319 } 2320 2321 // Simplify (X+Z) == X --> Z == 0 2322 if (N0.getOperand(0) == N1) 2323 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2324 DAG.getConstant(0, N0.getValueType()), Cond); 2325 if (N0.getOperand(1) == N1) { 2326 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2327 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2328 DAG.getConstant(0, N0.getValueType()), Cond); 2329 else if (N0.getNode()->hasOneUse()) { 2330 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2331 // (Z-X) == X --> Z == X<<1 2332 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2333 N1, 2334 DAG.getConstant(1, getShiftAmountTy())); 2335 if (!DCI.isCalledByLegalizer()) 2336 DCI.AddToWorklist(SH.getNode()); 2337 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2338 } 2339 } 2340 } 2341 2342 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2343 N1.getOpcode() == ISD::XOR) { 2344 // Simplify X == (X+Z) --> Z == 0 2345 if (N1.getOperand(0) == N0) { 2346 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2347 DAG.getConstant(0, N1.getValueType()), Cond); 2348 } else if (N1.getOperand(1) == N0) { 2349 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2350 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2351 DAG.getConstant(0, N1.getValueType()), Cond); 2352 } else if (N1.getNode()->hasOneUse()) { 2353 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2354 // X == (Z-X) --> X<<1 == Z 2355 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2356 DAG.getConstant(1, getShiftAmountTy())); 2357 if (!DCI.isCalledByLegalizer()) 2358 DCI.AddToWorklist(SH.getNode()); 2359 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2360 } 2361 } 2362 } 2363 2364 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2365 // Note that where y is variable and is known to have at most 2366 // one bit set (for example, if it is z&1) we cannot do this; 2367 // the expressions are not equivalent when y==0. 2368 if (N0.getOpcode() == ISD::AND) 2369 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2370 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2371 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2372 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2373 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2374 } 2375 } 2376 if (N1.getOpcode() == ISD::AND) 2377 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2378 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2379 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2380 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2381 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2382 } 2383 } 2384 } 2385 2386 // Fold away ALL boolean setcc's. 2387 SDValue Temp; 2388 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2389 switch (Cond) { 2390 default: llvm_unreachable("Unknown integer setcc!"); 2391 case ISD::SETEQ: // X == Y -> ~(X^Y) 2392 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2393 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2394 if (!DCI.isCalledByLegalizer()) 2395 DCI.AddToWorklist(Temp.getNode()); 2396 break; 2397 case ISD::SETNE: // X != Y --> (X^Y) 2398 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2399 break; 2400 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2401 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2402 Temp = DAG.getNOT(dl, N0, MVT::i1); 2403 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2404 if (!DCI.isCalledByLegalizer()) 2405 DCI.AddToWorklist(Temp.getNode()); 2406 break; 2407 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2408 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2409 Temp = DAG.getNOT(dl, N1, MVT::i1); 2410 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2411 if (!DCI.isCalledByLegalizer()) 2412 DCI.AddToWorklist(Temp.getNode()); 2413 break; 2414 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2415 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2416 Temp = DAG.getNOT(dl, N0, MVT::i1); 2417 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2418 if (!DCI.isCalledByLegalizer()) 2419 DCI.AddToWorklist(Temp.getNode()); 2420 break; 2421 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2422 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2423 Temp = DAG.getNOT(dl, N1, MVT::i1); 2424 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2425 break; 2426 } 2427 if (VT != MVT::i1) { 2428 if (!DCI.isCalledByLegalizer()) 2429 DCI.AddToWorklist(N0.getNode()); 2430 // FIXME: If running after legalize, we probably can't do this. 2431 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2432 } 2433 return N0; 2434 } 2435 2436 // Could not fold it. 2437 return SDValue(); 2438} 2439 2440/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2441/// node is a GlobalAddress + offset. 2442bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA, 2443 int64_t &Offset) const { 2444 if (isa<GlobalAddressSDNode>(N)) { 2445 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2446 GA = GASD->getGlobal(); 2447 Offset += GASD->getOffset(); 2448 return true; 2449 } 2450 2451 if (N->getOpcode() == ISD::ADD) { 2452 SDValue N1 = N->getOperand(0); 2453 SDValue N2 = N->getOperand(1); 2454 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2455 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2456 if (V) { 2457 Offset += V->getSExtValue(); 2458 return true; 2459 } 2460 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2461 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2462 if (V) { 2463 Offset += V->getSExtValue(); 2464 return true; 2465 } 2466 } 2467 } 2468 return false; 2469} 2470 2471 2472SDValue TargetLowering:: 2473PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2474 // Default implementation: no optimization. 2475 return SDValue(); 2476} 2477 2478//===----------------------------------------------------------------------===// 2479// Inline Assembler Implementation Methods 2480//===----------------------------------------------------------------------===// 2481 2482 2483TargetLowering::ConstraintType 2484TargetLowering::getConstraintType(const std::string &Constraint) const { 2485 // FIXME: lots more standard ones to handle. 2486 if (Constraint.size() == 1) { 2487 switch (Constraint[0]) { 2488 default: break; 2489 case 'r': return C_RegisterClass; 2490 case 'm': // memory 2491 case 'o': // offsetable 2492 case 'V': // not offsetable 2493 return C_Memory; 2494 case 'i': // Simple Integer or Relocatable Constant 2495 case 'n': // Simple Integer 2496 case 'E': // Floating Point Constant 2497 case 'F': // Floating Point Constant 2498 case 's': // Relocatable Constant 2499 case 'p': // Address. 2500 case 'X': // Allow ANY value. 2501 case 'I': // Target registers. 2502 case 'J': 2503 case 'K': 2504 case 'L': 2505 case 'M': 2506 case 'N': 2507 case 'O': 2508 case 'P': 2509 case '<': 2510 case '>': 2511 return C_Other; 2512 } 2513 } 2514 2515 if (Constraint.size() > 1 && Constraint[0] == '{' && 2516 Constraint[Constraint.size()-1] == '}') 2517 return C_Register; 2518 return C_Unknown; 2519} 2520 2521/// LowerXConstraint - try to replace an X constraint, which matches anything, 2522/// with another that has more specific requirements based on the type of the 2523/// corresponding operand. 2524const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2525 if (ConstraintVT.isInteger()) 2526 return "r"; 2527 if (ConstraintVT.isFloatingPoint()) 2528 return "f"; // works for many targets 2529 return 0; 2530} 2531 2532/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2533/// vector. If it is invalid, don't add anything to Ops. 2534void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2535 char ConstraintLetter, 2536 std::vector<SDValue> &Ops, 2537 SelectionDAG &DAG) const { 2538 switch (ConstraintLetter) { 2539 default: break; 2540 case 'X': // Allows any operand; labels (basic block) use this. 2541 if (Op.getOpcode() == ISD::BasicBlock) { 2542 Ops.push_back(Op); 2543 return; 2544 } 2545 // fall through 2546 case 'i': // Simple Integer or Relocatable Constant 2547 case 'n': // Simple Integer 2548 case 's': { // Relocatable Constant 2549 // These operands are interested in values of the form (GV+C), where C may 2550 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2551 // is possible and fine if either GV or C are missing. 2552 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2553 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2554 2555 // If we have "(add GV, C)", pull out GV/C 2556 if (Op.getOpcode() == ISD::ADD) { 2557 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2558 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2559 if (C == 0 || GA == 0) { 2560 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2561 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2562 } 2563 if (C == 0 || GA == 0) 2564 C = 0, GA = 0; 2565 } 2566 2567 // If we find a valid operand, map to the TargetXXX version so that the 2568 // value itself doesn't get selected. 2569 if (GA) { // Either &GV or &GV+C 2570 if (ConstraintLetter != 'n') { 2571 int64_t Offs = GA->getOffset(); 2572 if (C) Offs += C->getZExtValue(); 2573 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2574 C ? C->getDebugLoc() : DebugLoc(), 2575 Op.getValueType(), Offs)); 2576 return; 2577 } 2578 } 2579 if (C) { // just C, no GV. 2580 // Simple constants are not allowed for 's'. 2581 if (ConstraintLetter != 's') { 2582 // gcc prints these as sign extended. Sign extend value to 64 bits 2583 // now; without this it would get ZExt'd later in 2584 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2585 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2586 MVT::i64)); 2587 return; 2588 } 2589 } 2590 break; 2591 } 2592 } 2593} 2594 2595std::vector<unsigned> TargetLowering:: 2596getRegClassForInlineAsmConstraint(const std::string &Constraint, 2597 EVT VT) const { 2598 return std::vector<unsigned>(); 2599} 2600 2601 2602std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2603getRegForInlineAsmConstraint(const std::string &Constraint, 2604 EVT VT) const { 2605 if (Constraint[0] != '{') 2606 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2607 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2608 2609 // Remove the braces from around the name. 2610 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2611 2612 // Figure out which register class contains this reg. 2613 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2614 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2615 E = RI->regclass_end(); RCI != E; ++RCI) { 2616 const TargetRegisterClass *RC = *RCI; 2617 2618 // If none of the value types for this register class are valid, we 2619 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2620 bool isLegal = false; 2621 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2622 I != E; ++I) { 2623 if (isTypeLegal(*I)) { 2624 isLegal = true; 2625 break; 2626 } 2627 } 2628 2629 if (!isLegal) continue; 2630 2631 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2632 I != E; ++I) { 2633 if (RegName.equals_lower(RI->getName(*I))) 2634 return std::make_pair(*I, RC); 2635 } 2636 } 2637 2638 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2639} 2640 2641//===----------------------------------------------------------------------===// 2642// Constraint Selection. 2643 2644/// isMatchingInputConstraint - Return true of this is an input operand that is 2645/// a matching constraint like "4". 2646bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2647 assert(!ConstraintCode.empty() && "No known constraint!"); 2648 return isdigit(ConstraintCode[0]); 2649} 2650 2651/// getMatchedOperand - If this is an input matching constraint, this method 2652/// returns the output operand it matches. 2653unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2654 assert(!ConstraintCode.empty() && "No known constraint!"); 2655 return atoi(ConstraintCode.c_str()); 2656} 2657 2658 2659/// ParseConstraints - Split up the constraint string from the inline 2660/// assembly value into the specific constraints and their prefixes, 2661/// and also tie in the associated operand values. 2662/// If this returns an empty vector, and if the constraint string itself 2663/// isn't empty, there was an error parsing. 2664TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2665 ImmutableCallSite CS) const { 2666 /// ConstraintOperands - Information about all of the constraints. 2667 AsmOperandInfoVector ConstraintOperands; 2668 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2669 unsigned maCount = 0; // Largest number of multiple alternative constraints. 2670 2671 // Do a prepass over the constraints, canonicalizing them, and building up the 2672 // ConstraintOperands list. 2673 InlineAsm::ConstraintInfoVector 2674 ConstraintInfos = IA->ParseConstraints(); 2675 2676 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2677 unsigned ResNo = 0; // ResNo - The result number of the next output. 2678 2679 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 2680 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 2681 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2682 2683 // Update multiple alternative constraint count. 2684 if (OpInfo.multipleAlternatives.size() > maCount) 2685 maCount = OpInfo.multipleAlternatives.size(); 2686 2687 OpInfo.ConstraintVT = MVT::Other; 2688 2689 // Compute the value type for each operand. 2690 switch (OpInfo.Type) { 2691 case InlineAsm::isOutput: 2692 // Indirect outputs just consume an argument. 2693 if (OpInfo.isIndirect) { 2694 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2695 break; 2696 } 2697 2698 // The return value of the call is this value. As such, there is no 2699 // corresponding argument. 2700 assert(!CS.getType()->isVoidTy() && 2701 "Bad inline asm!"); 2702 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 2703 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo)); 2704 } else { 2705 assert(ResNo == 0 && "Asm only has one result!"); 2706 OpInfo.ConstraintVT = getValueType(CS.getType()); 2707 } 2708 ++ResNo; 2709 break; 2710 case InlineAsm::isInput: 2711 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2712 break; 2713 case InlineAsm::isClobber: 2714 // Nothing to do. 2715 break; 2716 } 2717 2718 if (OpInfo.CallOperandVal) { 2719 const llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2720 if (OpInfo.isIndirect) { 2721 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2722 if (!PtrTy) 2723 report_fatal_error("Indirect operand for inline asm not a pointer!"); 2724 OpTy = PtrTy->getElementType(); 2725 } 2726 // If OpTy is not a single value, it may be a struct/union that we 2727 // can tile with integers. 2728 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2729 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 2730 switch (BitSize) { 2731 default: break; 2732 case 1: 2733 case 8: 2734 case 16: 2735 case 32: 2736 case 64: 2737 case 128: 2738 OpInfo.ConstraintVT = 2739 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true); 2740 break; 2741 } 2742 } else if (dyn_cast<PointerType>(OpTy)) { 2743 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize()); 2744 } else { 2745 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true); 2746 } 2747 } 2748 } 2749 2750 // If we have multiple alternative constraints, select the best alternative. 2751 if (ConstraintInfos.size()) { 2752 if (maCount) { 2753 unsigned bestMAIndex = 0; 2754 int bestWeight = -1; 2755 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2756 int weight = -1; 2757 unsigned maIndex; 2758 // Compute the sums of the weights for each alternative, keeping track 2759 // of the best (highest weight) one so far. 2760 for (maIndex = 0; maIndex < maCount; ++maIndex) { 2761 int weightSum = 0; 2762 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2763 cIndex != eIndex; ++cIndex) { 2764 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2765 if (OpInfo.Type == InlineAsm::isClobber) 2766 continue; 2767 2768 // If this is an output operand with a matching input operand, 2769 // look up the matching input. If their types mismatch, e.g. one 2770 // is an integer, the other is floating point, or their sizes are 2771 // different, flag it as an maCantMatch. 2772 if (OpInfo.hasMatchingInput()) { 2773 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2774 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2775 if ((OpInfo.ConstraintVT.isInteger() != 2776 Input.ConstraintVT.isInteger()) || 2777 (OpInfo.ConstraintVT.getSizeInBits() != 2778 Input.ConstraintVT.getSizeInBits())) { 2779 weightSum = -1; // Can't match. 2780 break; 2781 } 2782 } 2783 } 2784 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 2785 if (weight == -1) { 2786 weightSum = -1; 2787 break; 2788 } 2789 weightSum += weight; 2790 } 2791 // Update best. 2792 if (weightSum > bestWeight) { 2793 bestWeight = weightSum; 2794 bestMAIndex = maIndex; 2795 } 2796 } 2797 2798 // Now select chosen alternative in each constraint. 2799 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2800 cIndex != eIndex; ++cIndex) { 2801 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 2802 if (cInfo.Type == InlineAsm::isClobber) 2803 continue; 2804 cInfo.selectAlternative(bestMAIndex); 2805 } 2806 } 2807 } 2808 2809 // Check and hook up tied operands, choose constraint code to use. 2810 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2811 cIndex != eIndex; ++cIndex) { 2812 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2813 2814 // If this is an output operand with a matching input operand, look up the 2815 // matching input. If their types mismatch, e.g. one is an integer, the 2816 // other is floating point, or their sizes are different, flag it as an 2817 // error. 2818 if (OpInfo.hasMatchingInput()) { 2819 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2820 2821 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2822 if ((OpInfo.ConstraintVT.isInteger() != 2823 Input.ConstraintVT.isInteger()) || 2824 (OpInfo.ConstraintVT.getSizeInBits() != 2825 Input.ConstraintVT.getSizeInBits())) { 2826 report_fatal_error("Unsupported asm: input constraint" 2827 " with a matching output constraint of" 2828 " incompatible type!"); 2829 } 2830 } 2831 2832 } 2833 } 2834 2835 return ConstraintOperands; 2836} 2837 2838 2839/// getConstraintGenerality - Return an integer indicating how general CT 2840/// is. 2841static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2842 switch (CT) { 2843 default: llvm_unreachable("Unknown constraint type!"); 2844 case TargetLowering::C_Other: 2845 case TargetLowering::C_Unknown: 2846 return 0; 2847 case TargetLowering::C_Register: 2848 return 1; 2849 case TargetLowering::C_RegisterClass: 2850 return 2; 2851 case TargetLowering::C_Memory: 2852 return 3; 2853 } 2854} 2855 2856/// Examine constraint type and operand type and determine a weight value. 2857/// This object must already have been set up with the operand type 2858/// and the current alternative constraint selected. 2859TargetLowering::ConstraintWeight 2860 TargetLowering::getMultipleConstraintMatchWeight( 2861 AsmOperandInfo &info, int maIndex) const { 2862 InlineAsm::ConstraintCodeVector *rCodes; 2863 if (maIndex >= (int)info.multipleAlternatives.size()) 2864 rCodes = &info.Codes; 2865 else 2866 rCodes = &info.multipleAlternatives[maIndex].Codes; 2867 ConstraintWeight BestWeight = CW_Invalid; 2868 2869 // Loop over the options, keeping track of the most general one. 2870 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 2871 ConstraintWeight weight = 2872 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 2873 if (weight > BestWeight) 2874 BestWeight = weight; 2875 } 2876 2877 return BestWeight; 2878} 2879 2880/// Examine constraint type and operand type and determine a weight value. 2881/// This object must already have been set up with the operand type 2882/// and the current alternative constraint selected. 2883TargetLowering::ConstraintWeight 2884 TargetLowering::getSingleConstraintMatchWeight( 2885 AsmOperandInfo &info, const char *constraint) const { 2886 ConstraintWeight weight = CW_Invalid; 2887 Value *CallOperandVal = info.CallOperandVal; 2888 // If we don't have a value, we can't do a match, 2889 // but allow it at the lowest weight. 2890 if (CallOperandVal == NULL) 2891 return CW_Default; 2892 // Look at the constraint type. 2893 switch (*constraint) { 2894 case 'i': // immediate integer. 2895 case 'n': // immediate integer with a known value. 2896 if (isa<ConstantInt>(CallOperandVal)) 2897 weight = CW_Constant; 2898 break; 2899 case 's': // non-explicit intregal immediate. 2900 if (isa<GlobalValue>(CallOperandVal)) 2901 weight = CW_Constant; 2902 break; 2903 case 'E': // immediate float if host format. 2904 case 'F': // immediate float. 2905 if (isa<ConstantFP>(CallOperandVal)) 2906 weight = CW_Constant; 2907 break; 2908 case '<': // memory operand with autodecrement. 2909 case '>': // memory operand with autoincrement. 2910 case 'm': // memory operand. 2911 case 'o': // offsettable memory operand 2912 case 'V': // non-offsettable memory operand 2913 weight = CW_Memory; 2914 break; 2915 case 'r': // general register. 2916 case 'g': // general register, memory operand or immediate integer. 2917 // note: Clang converts "g" to "imr". 2918 if (CallOperandVal->getType()->isIntegerTy()) 2919 weight = CW_Register; 2920 break; 2921 case 'X': // any operand. 2922 default: 2923 weight = CW_Default; 2924 break; 2925 } 2926 return weight; 2927} 2928 2929/// ChooseConstraint - If there are multiple different constraints that we 2930/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2931/// This is somewhat tricky: constraints fall into four classes: 2932/// Other -> immediates and magic values 2933/// Register -> one specific register 2934/// RegisterClass -> a group of regs 2935/// Memory -> memory 2936/// Ideally, we would pick the most specific constraint possible: if we have 2937/// something that fits into a register, we would pick it. The problem here 2938/// is that if we have something that could either be in a register or in 2939/// memory that use of the register could cause selection of *other* 2940/// operands to fail: they might only succeed if we pick memory. Because of 2941/// this the heuristic we use is: 2942/// 2943/// 1) If there is an 'other' constraint, and if the operand is valid for 2944/// that constraint, use it. This makes us take advantage of 'i' 2945/// constraints when available. 2946/// 2) Otherwise, pick the most general constraint present. This prefers 2947/// 'm' over 'r', for example. 2948/// 2949static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2950 const TargetLowering &TLI, 2951 SDValue Op, SelectionDAG *DAG) { 2952 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2953 unsigned BestIdx = 0; 2954 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2955 int BestGenerality = -1; 2956 2957 // Loop over the options, keeping track of the most general one. 2958 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2959 TargetLowering::ConstraintType CType = 2960 TLI.getConstraintType(OpInfo.Codes[i]); 2961 2962 // If this is an 'other' constraint, see if the operand is valid for it. 2963 // For example, on X86 we might have an 'rI' constraint. If the operand 2964 // is an integer in the range [0..31] we want to use I (saving a load 2965 // of a register), otherwise we must use 'r'. 2966 if (CType == TargetLowering::C_Other && Op.getNode()) { 2967 assert(OpInfo.Codes[i].size() == 1 && 2968 "Unhandled multi-letter 'other' constraint"); 2969 std::vector<SDValue> ResultOps; 2970 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], 2971 ResultOps, *DAG); 2972 if (!ResultOps.empty()) { 2973 BestType = CType; 2974 BestIdx = i; 2975 break; 2976 } 2977 } 2978 2979 // Things with matching constraints can only be registers, per gcc 2980 // documentation. This mainly affects "g" constraints. 2981 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 2982 continue; 2983 2984 // This constraint letter is more general than the previous one, use it. 2985 int Generality = getConstraintGenerality(CType); 2986 if (Generality > BestGenerality) { 2987 BestType = CType; 2988 BestIdx = i; 2989 BestGenerality = Generality; 2990 } 2991 } 2992 2993 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2994 OpInfo.ConstraintType = BestType; 2995} 2996 2997/// ComputeConstraintToUse - Determines the constraint code and constraint 2998/// type to use for the specific AsmOperandInfo, setting 2999/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 3000void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 3001 SDValue Op, 3002 SelectionDAG *DAG) const { 3003 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 3004 3005 // Single-letter constraints ('r') are very common. 3006 if (OpInfo.Codes.size() == 1) { 3007 OpInfo.ConstraintCode = OpInfo.Codes[0]; 3008 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3009 } else { 3010 ChooseConstraint(OpInfo, *this, Op, DAG); 3011 } 3012 3013 // 'X' matches anything. 3014 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 3015 // Labels and constants are handled elsewhere ('X' is the only thing 3016 // that matches labels). For Functions, the type here is the type of 3017 // the result, which is not what we want to look at; leave them alone. 3018 Value *v = OpInfo.CallOperandVal; 3019 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 3020 OpInfo.CallOperandVal = v; 3021 return; 3022 } 3023 3024 // Otherwise, try to resolve it to something we know about by looking at 3025 // the actual operand type. 3026 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 3027 OpInfo.ConstraintCode = Repl; 3028 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3029 } 3030 } 3031} 3032 3033//===----------------------------------------------------------------------===// 3034// Loop Strength Reduction hooks 3035//===----------------------------------------------------------------------===// 3036 3037/// isLegalAddressingMode - Return true if the addressing mode represented 3038/// by AM is legal for this target, for a load/store of the specified type. 3039bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 3040 const Type *Ty) const { 3041 // The default implementation of this implements a conservative RISCy, r+r and 3042 // r+i addr mode. 3043 3044 // Allows a sign-extended 16-bit immediate field. 3045 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3046 return false; 3047 3048 // No global is ever allowed as a base. 3049 if (AM.BaseGV) 3050 return false; 3051 3052 // Only support r+r, 3053 switch (AM.Scale) { 3054 case 0: // "r+i" or just "i", depending on HasBaseReg. 3055 break; 3056 case 1: 3057 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3058 return false; 3059 // Otherwise we have r+r or r+i. 3060 break; 3061 case 2: 3062 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3063 return false; 3064 // Allow 2*r as r+r. 3065 break; 3066 } 3067 3068 return true; 3069} 3070 3071/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3072/// return a DAG expression to select that will generate the same value by 3073/// multiplying by a magic number. See: 3074/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3075SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 3076 std::vector<SDNode*>* Created) const { 3077 EVT VT = N->getValueType(0); 3078 DebugLoc dl= N->getDebugLoc(); 3079 3080 // Check to see if we can do this. 3081 // FIXME: We should be more aggressive here. 3082 if (!isTypeLegal(VT)) 3083 return SDValue(); 3084 3085 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3086 APInt::ms magics = d.magic(); 3087 3088 // Multiply the numerator (operand 0) by the magic value 3089 // FIXME: We should support doing a MUL in a wider type 3090 SDValue Q; 3091 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 3092 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 3093 DAG.getConstant(magics.m, VT)); 3094 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 3095 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 3096 N->getOperand(0), 3097 DAG.getConstant(magics.m, VT)).getNode(), 1); 3098 else 3099 return SDValue(); // No mulhs or equvialent 3100 // If d > 0 and m < 0, add the numerator 3101 if (d.isStrictlyPositive() && magics.m.isNegative()) { 3102 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 3103 if (Created) 3104 Created->push_back(Q.getNode()); 3105 } 3106 // If d < 0 and m > 0, subtract the numerator. 3107 if (d.isNegative() && magics.m.isStrictlyPositive()) { 3108 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 3109 if (Created) 3110 Created->push_back(Q.getNode()); 3111 } 3112 // Shift right algebraic if shift value is nonzero 3113 if (magics.s > 0) { 3114 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 3115 DAG.getConstant(magics.s, getShiftAmountTy())); 3116 if (Created) 3117 Created->push_back(Q.getNode()); 3118 } 3119 // Extract the sign bit and add it to the quotient 3120 SDValue T = 3121 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 3122 getShiftAmountTy())); 3123 if (Created) 3124 Created->push_back(T.getNode()); 3125 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 3126} 3127 3128/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3129/// return a DAG expression to select that will generate the same value by 3130/// multiplying by a magic number. See: 3131/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3132SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 3133 std::vector<SDNode*>* Created) const { 3134 EVT VT = N->getValueType(0); 3135 DebugLoc dl = N->getDebugLoc(); 3136 3137 // Check to see if we can do this. 3138 // FIXME: We should be more aggressive here. 3139 if (!isTypeLegal(VT)) 3140 return SDValue(); 3141 3142 // FIXME: We should use a narrower constant when the upper 3143 // bits are known to be zero. 3144 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 3145 APInt::mu magics = N1C->getAPIntValue().magicu(); 3146 3147 // Multiply the numerator (operand 0) by the magic value 3148 // FIXME: We should support doing a MUL in a wider type 3149 SDValue Q; 3150 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 3151 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 3152 DAG.getConstant(magics.m, VT)); 3153 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 3154 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 3155 N->getOperand(0), 3156 DAG.getConstant(magics.m, VT)).getNode(), 1); 3157 else 3158 return SDValue(); // No mulhu or equvialent 3159 if (Created) 3160 Created->push_back(Q.getNode()); 3161 3162 if (magics.a == 0) { 3163 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 3164 "We shouldn't generate an undefined shift!"); 3165 return DAG.getNode(ISD::SRL, dl, VT, Q, 3166 DAG.getConstant(magics.s, getShiftAmountTy())); 3167 } else { 3168 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 3169 if (Created) 3170 Created->push_back(NPQ.getNode()); 3171 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 3172 DAG.getConstant(1, getShiftAmountTy())); 3173 if (Created) 3174 Created->push_back(NPQ.getNode()); 3175 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 3176 if (Created) 3177 Created->push_back(NPQ.getNode()); 3178 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 3179 DAG.getConstant(magics.s-1, getShiftAmountTy())); 3180 } 3181} 3182