TargetLowering.cpp revision 44ab89eb376af838d1123293a79975aede501464
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/CodeGen/Analysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineJumpTableInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31using namespace llvm; 32 33namespace llvm { 34TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 35 bool isLocal = GV->hasLocalLinkage(); 36 bool isDeclaration = GV->isDeclaration(); 37 // FIXME: what should we do for protected and internal visibility? 38 // For variables, is internal different from hidden? 39 bool isHidden = GV->hasHiddenVisibility(); 40 41 if (reloc == Reloc::PIC_) { 42 if (isLocal || isHidden) 43 return TLSModel::LocalDynamic; 44 else 45 return TLSModel::GeneralDynamic; 46 } else { 47 if (!isDeclaration || isHidden) 48 return TLSModel::LocalExec; 49 else 50 return TLSModel::InitialExec; 51 } 52} 53} 54 55/// InitLibcallNames - Set default libcall names. 56/// 57static void InitLibcallNames(const char **Names) { 58 Names[RTLIB::SHL_I16] = "__ashlhi3"; 59 Names[RTLIB::SHL_I32] = "__ashlsi3"; 60 Names[RTLIB::SHL_I64] = "__ashldi3"; 61 Names[RTLIB::SHL_I128] = "__ashlti3"; 62 Names[RTLIB::SRL_I16] = "__lshrhi3"; 63 Names[RTLIB::SRL_I32] = "__lshrsi3"; 64 Names[RTLIB::SRL_I64] = "__lshrdi3"; 65 Names[RTLIB::SRL_I128] = "__lshrti3"; 66 Names[RTLIB::SRA_I16] = "__ashrhi3"; 67 Names[RTLIB::SRA_I32] = "__ashrsi3"; 68 Names[RTLIB::SRA_I64] = "__ashrdi3"; 69 Names[RTLIB::SRA_I128] = "__ashrti3"; 70 Names[RTLIB::MUL_I8] = "__mulqi3"; 71 Names[RTLIB::MUL_I16] = "__mulhi3"; 72 Names[RTLIB::MUL_I32] = "__mulsi3"; 73 Names[RTLIB::MUL_I64] = "__muldi3"; 74 Names[RTLIB::MUL_I128] = "__multi3"; 75 Names[RTLIB::SDIV_I8] = "__divqi3"; 76 Names[RTLIB::SDIV_I16] = "__divhi3"; 77 Names[RTLIB::SDIV_I32] = "__divsi3"; 78 Names[RTLIB::SDIV_I64] = "__divdi3"; 79 Names[RTLIB::SDIV_I128] = "__divti3"; 80 Names[RTLIB::UDIV_I8] = "__udivqi3"; 81 Names[RTLIB::UDIV_I16] = "__udivhi3"; 82 Names[RTLIB::UDIV_I32] = "__udivsi3"; 83 Names[RTLIB::UDIV_I64] = "__udivdi3"; 84 Names[RTLIB::UDIV_I128] = "__udivti3"; 85 Names[RTLIB::SREM_I8] = "__modqi3"; 86 Names[RTLIB::SREM_I16] = "__modhi3"; 87 Names[RTLIB::SREM_I32] = "__modsi3"; 88 Names[RTLIB::SREM_I64] = "__moddi3"; 89 Names[RTLIB::SREM_I128] = "__modti3"; 90 Names[RTLIB::UREM_I8] = "__umodqi3"; 91 Names[RTLIB::UREM_I16] = "__umodhi3"; 92 Names[RTLIB::UREM_I32] = "__umodsi3"; 93 Names[RTLIB::UREM_I64] = "__umoddi3"; 94 Names[RTLIB::UREM_I128] = "__umodti3"; 95 Names[RTLIB::NEG_I32] = "__negsi2"; 96 Names[RTLIB::NEG_I64] = "__negdi2"; 97 Names[RTLIB::ADD_F32] = "__addsf3"; 98 Names[RTLIB::ADD_F64] = "__adddf3"; 99 Names[RTLIB::ADD_F80] = "__addxf3"; 100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 101 Names[RTLIB::SUB_F32] = "__subsf3"; 102 Names[RTLIB::SUB_F64] = "__subdf3"; 103 Names[RTLIB::SUB_F80] = "__subxf3"; 104 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 105 Names[RTLIB::MUL_F32] = "__mulsf3"; 106 Names[RTLIB::MUL_F64] = "__muldf3"; 107 Names[RTLIB::MUL_F80] = "__mulxf3"; 108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 109 Names[RTLIB::DIV_F32] = "__divsf3"; 110 Names[RTLIB::DIV_F64] = "__divdf3"; 111 Names[RTLIB::DIV_F80] = "__divxf3"; 112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 113 Names[RTLIB::REM_F32] = "fmodf"; 114 Names[RTLIB::REM_F64] = "fmod"; 115 Names[RTLIB::REM_F80] = "fmodl"; 116 Names[RTLIB::REM_PPCF128] = "fmodl"; 117 Names[RTLIB::POWI_F32] = "__powisf2"; 118 Names[RTLIB::POWI_F64] = "__powidf2"; 119 Names[RTLIB::POWI_F80] = "__powixf2"; 120 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 121 Names[RTLIB::SQRT_F32] = "sqrtf"; 122 Names[RTLIB::SQRT_F64] = "sqrt"; 123 Names[RTLIB::SQRT_F80] = "sqrtl"; 124 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 125 Names[RTLIB::LOG_F32] = "logf"; 126 Names[RTLIB::LOG_F64] = "log"; 127 Names[RTLIB::LOG_F80] = "logl"; 128 Names[RTLIB::LOG_PPCF128] = "logl"; 129 Names[RTLIB::LOG2_F32] = "log2f"; 130 Names[RTLIB::LOG2_F64] = "log2"; 131 Names[RTLIB::LOG2_F80] = "log2l"; 132 Names[RTLIB::LOG2_PPCF128] = "log2l"; 133 Names[RTLIB::LOG10_F32] = "log10f"; 134 Names[RTLIB::LOG10_F64] = "log10"; 135 Names[RTLIB::LOG10_F80] = "log10l"; 136 Names[RTLIB::LOG10_PPCF128] = "log10l"; 137 Names[RTLIB::EXP_F32] = "expf"; 138 Names[RTLIB::EXP_F64] = "exp"; 139 Names[RTLIB::EXP_F80] = "expl"; 140 Names[RTLIB::EXP_PPCF128] = "expl"; 141 Names[RTLIB::EXP2_F32] = "exp2f"; 142 Names[RTLIB::EXP2_F64] = "exp2"; 143 Names[RTLIB::EXP2_F80] = "exp2l"; 144 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 145 Names[RTLIB::SIN_F32] = "sinf"; 146 Names[RTLIB::SIN_F64] = "sin"; 147 Names[RTLIB::SIN_F80] = "sinl"; 148 Names[RTLIB::SIN_PPCF128] = "sinl"; 149 Names[RTLIB::COS_F32] = "cosf"; 150 Names[RTLIB::COS_F64] = "cos"; 151 Names[RTLIB::COS_F80] = "cosl"; 152 Names[RTLIB::COS_PPCF128] = "cosl"; 153 Names[RTLIB::POW_F32] = "powf"; 154 Names[RTLIB::POW_F64] = "pow"; 155 Names[RTLIB::POW_F80] = "powl"; 156 Names[RTLIB::POW_PPCF128] = "powl"; 157 Names[RTLIB::CEIL_F32] = "ceilf"; 158 Names[RTLIB::CEIL_F64] = "ceil"; 159 Names[RTLIB::CEIL_F80] = "ceill"; 160 Names[RTLIB::CEIL_PPCF128] = "ceill"; 161 Names[RTLIB::TRUNC_F32] = "truncf"; 162 Names[RTLIB::TRUNC_F64] = "trunc"; 163 Names[RTLIB::TRUNC_F80] = "truncl"; 164 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 165 Names[RTLIB::RINT_F32] = "rintf"; 166 Names[RTLIB::RINT_F64] = "rint"; 167 Names[RTLIB::RINT_F80] = "rintl"; 168 Names[RTLIB::RINT_PPCF128] = "rintl"; 169 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 170 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 171 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 172 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 173 Names[RTLIB::FLOOR_F32] = "floorf"; 174 Names[RTLIB::FLOOR_F64] = "floor"; 175 Names[RTLIB::FLOOR_F80] = "floorl"; 176 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 177 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 178 Names[RTLIB::COPYSIGN_F64] = "copysign"; 179 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 180 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 181 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 182 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 183 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 184 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 185 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 186 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 187 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 188 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 189 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 190 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 191 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 192 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 193 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 194 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 195 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 196 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 197 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 198 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 199 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 200 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 201 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 202 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 203 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 204 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 205 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 206 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 207 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 208 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 209 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 210 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 211 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 212 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 213 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 214 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 215 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 216 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 217 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 218 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 219 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 220 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 221 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 222 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 223 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 224 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 225 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 226 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 227 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 228 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 229 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 230 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 231 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 232 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 233 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 234 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 235 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 236 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 237 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 238 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 239 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 240 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 241 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 242 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 243 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 244 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 245 Names[RTLIB::OEQ_F32] = "__eqsf2"; 246 Names[RTLIB::OEQ_F64] = "__eqdf2"; 247 Names[RTLIB::UNE_F32] = "__nesf2"; 248 Names[RTLIB::UNE_F64] = "__nedf2"; 249 Names[RTLIB::OGE_F32] = "__gesf2"; 250 Names[RTLIB::OGE_F64] = "__gedf2"; 251 Names[RTLIB::OLT_F32] = "__ltsf2"; 252 Names[RTLIB::OLT_F64] = "__ltdf2"; 253 Names[RTLIB::OLE_F32] = "__lesf2"; 254 Names[RTLIB::OLE_F64] = "__ledf2"; 255 Names[RTLIB::OGT_F32] = "__gtsf2"; 256 Names[RTLIB::OGT_F64] = "__gtdf2"; 257 Names[RTLIB::UO_F32] = "__unordsf2"; 258 Names[RTLIB::UO_F64] = "__unorddf2"; 259 Names[RTLIB::O_F32] = "__unordsf2"; 260 Names[RTLIB::O_F64] = "__unorddf2"; 261 Names[RTLIB::MEMCPY] = "memcpy"; 262 Names[RTLIB::MEMMOVE] = "memmove"; 263 Names[RTLIB::MEMSET] = "memset"; 264 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 265 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 268 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 269 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 272 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 273 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 274 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 275 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 276 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 277 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 278 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 279 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 280 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 281 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 282 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 283 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 284 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 285 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 286 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 287 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 288 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 289 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 290 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 291 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4"; 292 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 293 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 294 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 295 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 296 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 297} 298 299/// InitLibcallCallingConvs - Set default libcall CallingConvs. 300/// 301static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 302 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 303 CCs[i] = CallingConv::C; 304 } 305} 306 307/// getFPEXT - Return the FPEXT_*_* value for the given types, or 308/// UNKNOWN_LIBCALL if there is none. 309RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 310 if (OpVT == MVT::f32) { 311 if (RetVT == MVT::f64) 312 return FPEXT_F32_F64; 313 } 314 315 return UNKNOWN_LIBCALL; 316} 317 318/// getFPROUND - Return the FPROUND_*_* value for the given types, or 319/// UNKNOWN_LIBCALL if there is none. 320RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 321 if (RetVT == MVT::f32) { 322 if (OpVT == MVT::f64) 323 return FPROUND_F64_F32; 324 if (OpVT == MVT::f80) 325 return FPROUND_F80_F32; 326 if (OpVT == MVT::ppcf128) 327 return FPROUND_PPCF128_F32; 328 } else if (RetVT == MVT::f64) { 329 if (OpVT == MVT::f80) 330 return FPROUND_F80_F64; 331 if (OpVT == MVT::ppcf128) 332 return FPROUND_PPCF128_F64; 333 } 334 335 return UNKNOWN_LIBCALL; 336} 337 338/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 339/// UNKNOWN_LIBCALL if there is none. 340RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 341 if (OpVT == MVT::f32) { 342 if (RetVT == MVT::i8) 343 return FPTOSINT_F32_I8; 344 if (RetVT == MVT::i16) 345 return FPTOSINT_F32_I16; 346 if (RetVT == MVT::i32) 347 return FPTOSINT_F32_I32; 348 if (RetVT == MVT::i64) 349 return FPTOSINT_F32_I64; 350 if (RetVT == MVT::i128) 351 return FPTOSINT_F32_I128; 352 } else if (OpVT == MVT::f64) { 353 if (RetVT == MVT::i8) 354 return FPTOSINT_F64_I8; 355 if (RetVT == MVT::i16) 356 return FPTOSINT_F64_I16; 357 if (RetVT == MVT::i32) 358 return FPTOSINT_F64_I32; 359 if (RetVT == MVT::i64) 360 return FPTOSINT_F64_I64; 361 if (RetVT == MVT::i128) 362 return FPTOSINT_F64_I128; 363 } else if (OpVT == MVT::f80) { 364 if (RetVT == MVT::i32) 365 return FPTOSINT_F80_I32; 366 if (RetVT == MVT::i64) 367 return FPTOSINT_F80_I64; 368 if (RetVT == MVT::i128) 369 return FPTOSINT_F80_I128; 370 } else if (OpVT == MVT::ppcf128) { 371 if (RetVT == MVT::i32) 372 return FPTOSINT_PPCF128_I32; 373 if (RetVT == MVT::i64) 374 return FPTOSINT_PPCF128_I64; 375 if (RetVT == MVT::i128) 376 return FPTOSINT_PPCF128_I128; 377 } 378 return UNKNOWN_LIBCALL; 379} 380 381/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 382/// UNKNOWN_LIBCALL if there is none. 383RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 384 if (OpVT == MVT::f32) { 385 if (RetVT == MVT::i8) 386 return FPTOUINT_F32_I8; 387 if (RetVT == MVT::i16) 388 return FPTOUINT_F32_I16; 389 if (RetVT == MVT::i32) 390 return FPTOUINT_F32_I32; 391 if (RetVT == MVT::i64) 392 return FPTOUINT_F32_I64; 393 if (RetVT == MVT::i128) 394 return FPTOUINT_F32_I128; 395 } else if (OpVT == MVT::f64) { 396 if (RetVT == MVT::i8) 397 return FPTOUINT_F64_I8; 398 if (RetVT == MVT::i16) 399 return FPTOUINT_F64_I16; 400 if (RetVT == MVT::i32) 401 return FPTOUINT_F64_I32; 402 if (RetVT == MVT::i64) 403 return FPTOUINT_F64_I64; 404 if (RetVT == MVT::i128) 405 return FPTOUINT_F64_I128; 406 } else if (OpVT == MVT::f80) { 407 if (RetVT == MVT::i32) 408 return FPTOUINT_F80_I32; 409 if (RetVT == MVT::i64) 410 return FPTOUINT_F80_I64; 411 if (RetVT == MVT::i128) 412 return FPTOUINT_F80_I128; 413 } else if (OpVT == MVT::ppcf128) { 414 if (RetVT == MVT::i32) 415 return FPTOUINT_PPCF128_I32; 416 if (RetVT == MVT::i64) 417 return FPTOUINT_PPCF128_I64; 418 if (RetVT == MVT::i128) 419 return FPTOUINT_PPCF128_I128; 420 } 421 return UNKNOWN_LIBCALL; 422} 423 424/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 425/// UNKNOWN_LIBCALL if there is none. 426RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 427 if (OpVT == MVT::i32) { 428 if (RetVT == MVT::f32) 429 return SINTTOFP_I32_F32; 430 else if (RetVT == MVT::f64) 431 return SINTTOFP_I32_F64; 432 else if (RetVT == MVT::f80) 433 return SINTTOFP_I32_F80; 434 else if (RetVT == MVT::ppcf128) 435 return SINTTOFP_I32_PPCF128; 436 } else if (OpVT == MVT::i64) { 437 if (RetVT == MVT::f32) 438 return SINTTOFP_I64_F32; 439 else if (RetVT == MVT::f64) 440 return SINTTOFP_I64_F64; 441 else if (RetVT == MVT::f80) 442 return SINTTOFP_I64_F80; 443 else if (RetVT == MVT::ppcf128) 444 return SINTTOFP_I64_PPCF128; 445 } else if (OpVT == MVT::i128) { 446 if (RetVT == MVT::f32) 447 return SINTTOFP_I128_F32; 448 else if (RetVT == MVT::f64) 449 return SINTTOFP_I128_F64; 450 else if (RetVT == MVT::f80) 451 return SINTTOFP_I128_F80; 452 else if (RetVT == MVT::ppcf128) 453 return SINTTOFP_I128_PPCF128; 454 } 455 return UNKNOWN_LIBCALL; 456} 457 458/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 459/// UNKNOWN_LIBCALL if there is none. 460RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 461 if (OpVT == MVT::i32) { 462 if (RetVT == MVT::f32) 463 return UINTTOFP_I32_F32; 464 else if (RetVT == MVT::f64) 465 return UINTTOFP_I32_F64; 466 else if (RetVT == MVT::f80) 467 return UINTTOFP_I32_F80; 468 else if (RetVT == MVT::ppcf128) 469 return UINTTOFP_I32_PPCF128; 470 } else if (OpVT == MVT::i64) { 471 if (RetVT == MVT::f32) 472 return UINTTOFP_I64_F32; 473 else if (RetVT == MVT::f64) 474 return UINTTOFP_I64_F64; 475 else if (RetVT == MVT::f80) 476 return UINTTOFP_I64_F80; 477 else if (RetVT == MVT::ppcf128) 478 return UINTTOFP_I64_PPCF128; 479 } else if (OpVT == MVT::i128) { 480 if (RetVT == MVT::f32) 481 return UINTTOFP_I128_F32; 482 else if (RetVT == MVT::f64) 483 return UINTTOFP_I128_F64; 484 else if (RetVT == MVT::f80) 485 return UINTTOFP_I128_F80; 486 else if (RetVT == MVT::ppcf128) 487 return UINTTOFP_I128_PPCF128; 488 } 489 return UNKNOWN_LIBCALL; 490} 491 492/// InitCmpLibcallCCs - Set default comparison libcall CC. 493/// 494static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 495 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 496 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 497 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 498 CCs[RTLIB::UNE_F32] = ISD::SETNE; 499 CCs[RTLIB::UNE_F64] = ISD::SETNE; 500 CCs[RTLIB::OGE_F32] = ISD::SETGE; 501 CCs[RTLIB::OGE_F64] = ISD::SETGE; 502 CCs[RTLIB::OLT_F32] = ISD::SETLT; 503 CCs[RTLIB::OLT_F64] = ISD::SETLT; 504 CCs[RTLIB::OLE_F32] = ISD::SETLE; 505 CCs[RTLIB::OLE_F64] = ISD::SETLE; 506 CCs[RTLIB::OGT_F32] = ISD::SETGT; 507 CCs[RTLIB::OGT_F64] = ISD::SETGT; 508 CCs[RTLIB::UO_F32] = ISD::SETNE; 509 CCs[RTLIB::UO_F64] = ISD::SETNE; 510 CCs[RTLIB::O_F32] = ISD::SETEQ; 511 CCs[RTLIB::O_F64] = ISD::SETEQ; 512} 513 514/// NOTE: The constructor takes ownership of TLOF. 515TargetLowering::TargetLowering(const TargetMachine &tm, 516 const TargetLoweringObjectFile *tlof) 517 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 518 // All operations default to being supported. 519 memset(OpActions, 0, sizeof(OpActions)); 520 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 521 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 522 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 523 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 524 525 // Set default actions for various operations. 526 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 527 // Default all indexed load / store to expand. 528 for (unsigned IM = (unsigned)ISD::PRE_INC; 529 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 530 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 531 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 532 } 533 534 // These operations default to expand. 535 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 536 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 537 } 538 539 // Most targets ignore the @llvm.prefetch intrinsic. 540 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 541 542 // ConstantFP nodes default to expand. Targets can either change this to 543 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 544 // to optimize expansions for certain constants. 545 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 546 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 547 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 548 549 // These library functions default to expand. 550 setOperationAction(ISD::FLOG , MVT::f64, Expand); 551 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 552 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 553 setOperationAction(ISD::FEXP , MVT::f64, Expand); 554 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 555 setOperationAction(ISD::FLOG , MVT::f32, Expand); 556 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 557 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 558 setOperationAction(ISD::FEXP , MVT::f32, Expand); 559 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 560 561 // Default ISD::TRAP to expand (which turns it into abort). 562 setOperationAction(ISD::TRAP, MVT::Other, Expand); 563 564 IsLittleEndian = TD->isLittleEndian(); 565 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 566 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 567 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 568 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 569 benefitFromCodePlacementOpt = false; 570 UseUnderscoreSetJmp = false; 571 UseUnderscoreLongJmp = false; 572 SelectIsExpensive = false; 573 IntDivIsCheap = false; 574 Pow2DivIsCheap = false; 575 StackPointerRegisterToSaveRestore = 0; 576 ExceptionPointerRegister = 0; 577 ExceptionSelectorRegister = 0; 578 BooleanContents = UndefinedBooleanContent; 579 SchedPreferenceInfo = Sched::Latency; 580 JumpBufSize = 0; 581 JumpBufAlignment = 0; 582 PrefLoopAlignment = 0; 583 MinStackArgumentAlignment = 1; 584 ShouldFoldAtomicFences = false; 585 586 InitLibcallNames(LibcallRoutineNames); 587 InitCmpLibcallCCs(CmpLibcallCCs); 588 InitLibcallCallingConvs(LibcallCallingConvs); 589} 590 591TargetLowering::~TargetLowering() { 592 delete &TLOF; 593} 594 595/// canOpTrap - Returns true if the operation can trap for the value type. 596/// VT must be a legal type. 597bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 598 assert(isTypeLegal(VT)); 599 switch (Op) { 600 default: 601 return false; 602 case ISD::FDIV: 603 case ISD::FREM: 604 case ISD::SDIV: 605 case ISD::UDIV: 606 case ISD::SREM: 607 case ISD::UREM: 608 return true; 609 } 610} 611 612 613static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 614 unsigned &NumIntermediates, 615 EVT &RegisterVT, 616 TargetLowering *TLI) { 617 // Figure out the right, legal destination reg to copy into. 618 unsigned NumElts = VT.getVectorNumElements(); 619 MVT EltTy = VT.getVectorElementType(); 620 621 unsigned NumVectorRegs = 1; 622 623 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 624 // could break down into LHS/RHS like LegalizeDAG does. 625 if (!isPowerOf2_32(NumElts)) { 626 NumVectorRegs = NumElts; 627 NumElts = 1; 628 } 629 630 // Divide the input until we get to a supported size. This will always 631 // end with a scalar if the target doesn't support vectors. 632 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 633 NumElts >>= 1; 634 NumVectorRegs <<= 1; 635 } 636 637 NumIntermediates = NumVectorRegs; 638 639 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 640 if (!TLI->isTypeLegal(NewVT)) 641 NewVT = EltTy; 642 IntermediateVT = NewVT; 643 644 EVT DestVT = TLI->getRegisterType(NewVT); 645 RegisterVT = DestVT; 646 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 647 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 648 649 // Otherwise, promotion or legal types use the same number of registers as 650 // the vector decimated to the appropriate level. 651 return NumVectorRegs; 652} 653 654/// isLegalRC - Return true if the value types that can be represented by the 655/// specified register class are all legal. 656bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const { 657 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 658 I != E; ++I) { 659 if (isTypeLegal(*I)) 660 return true; 661 } 662 return false; 663} 664 665/// hasLegalSuperRegRegClasses - Return true if the specified register class 666/// has one or more super-reg register classes that are legal. 667bool 668TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{ 669 if (*RC->superregclasses_begin() == 0) 670 return false; 671 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 672 E = RC->superregclasses_end(); I != E; ++I) { 673 const TargetRegisterClass *RRC = *I; 674 if (isLegalRC(RRC)) 675 return true; 676 } 677 return false; 678} 679 680/// findRepresentativeClass - Return the largest legal super-reg register class 681/// of the register class for the specified type and its associated "cost". 682std::pair<const TargetRegisterClass*, uint8_t> 683TargetLowering::findRepresentativeClass(EVT VT) const { 684 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 685 if (!RC) 686 return std::make_pair(RC, 0); 687 const TargetRegisterClass *BestRC = RC; 688 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 689 E = RC->superregclasses_end(); I != E; ++I) { 690 const TargetRegisterClass *RRC = *I; 691 if (RRC->isASubClass() || !isLegalRC(RRC)) 692 continue; 693 if (!hasLegalSuperRegRegClasses(RRC)) 694 return std::make_pair(RRC, 1); 695 BestRC = RRC; 696 } 697 return std::make_pair(BestRC, 1); 698} 699 700 701/// computeRegisterProperties - Once all of the register classes are added, 702/// this allows us to compute derived properties we expose. 703void TargetLowering::computeRegisterProperties() { 704 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 705 "Too many value types for ValueTypeActions to hold!"); 706 707 // Everything defaults to needing one register. 708 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 709 NumRegistersForVT[i] = 1; 710 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 711 } 712 // ...except isVoid, which doesn't need any registers. 713 NumRegistersForVT[MVT::isVoid] = 0; 714 715 // Find the largest integer register class. 716 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 717 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 718 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 719 720 // Every integer value type larger than this largest register takes twice as 721 // many registers to represent as the previous ValueType. 722 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 723 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 724 if (!ExpandedVT.isInteger()) 725 break; 726 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 727 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 728 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 729 ValueTypeActions.setTypeAction(ExpandedVT, Expand); 730 } 731 732 // Inspect all of the ValueType's smaller than the largest integer 733 // register to see which ones need promotion. 734 unsigned LegalIntReg = LargestIntReg; 735 for (unsigned IntReg = LargestIntReg - 1; 736 IntReg >= (unsigned)MVT::i1; --IntReg) { 737 EVT IVT = (MVT::SimpleValueType)IntReg; 738 if (isTypeLegal(IVT)) { 739 LegalIntReg = IntReg; 740 } else { 741 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 742 (MVT::SimpleValueType)LegalIntReg; 743 ValueTypeActions.setTypeAction(IVT, Promote); 744 } 745 } 746 747 // ppcf128 type is really two f64's. 748 if (!isTypeLegal(MVT::ppcf128)) { 749 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 750 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 751 TransformToType[MVT::ppcf128] = MVT::f64; 752 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 753 } 754 755 // Decide how to handle f64. If the target does not have native f64 support, 756 // expand it to i64 and we will be generating soft float library calls. 757 if (!isTypeLegal(MVT::f64)) { 758 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 759 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 760 TransformToType[MVT::f64] = MVT::i64; 761 ValueTypeActions.setTypeAction(MVT::f64, Expand); 762 } 763 764 // Decide how to handle f32. If the target does not have native support for 765 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 766 if (!isTypeLegal(MVT::f32)) { 767 if (isTypeLegal(MVT::f64)) { 768 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 769 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 770 TransformToType[MVT::f32] = MVT::f64; 771 ValueTypeActions.setTypeAction(MVT::f32, Promote); 772 } else { 773 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 774 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 775 TransformToType[MVT::f32] = MVT::i32; 776 ValueTypeActions.setTypeAction(MVT::f32, Expand); 777 } 778 } 779 780 // Loop over all of the vector value types to see which need transformations. 781 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 782 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 783 MVT VT = (MVT::SimpleValueType)i; 784 if (isTypeLegal(VT)) continue; 785 786 // Determine if there is a legal wider type. If so, we should promote to 787 // that wider vector type. 788 EVT EltVT = VT.getVectorElementType(); 789 unsigned NElts = VT.getVectorNumElements(); 790 if (NElts != 1) { 791 bool IsLegalWiderType = false; 792 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 793 EVT SVT = (MVT::SimpleValueType)nVT; 794 if (SVT.getVectorElementType() == EltVT && 795 SVT.getVectorNumElements() > NElts && 796 isTypeLegal(SVT)) { 797 TransformToType[i] = SVT; 798 RegisterTypeForVT[i] = SVT; 799 NumRegistersForVT[i] = 1; 800 ValueTypeActions.setTypeAction(VT, Promote); 801 IsLegalWiderType = true; 802 break; 803 } 804 } 805 if (IsLegalWiderType) continue; 806 } 807 808 MVT IntermediateVT; 809 EVT RegisterVT; 810 unsigned NumIntermediates; 811 NumRegistersForVT[i] = 812 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 813 RegisterVT, this); 814 RegisterTypeForVT[i] = RegisterVT; 815 816 EVT NVT = VT.getPow2VectorType(); 817 if (NVT == VT) { 818 // Type is already a power of 2. The default action is to split. 819 TransformToType[i] = MVT::Other; 820 ValueTypeActions.setTypeAction(VT, Expand); 821 } else { 822 TransformToType[i] = NVT; 823 ValueTypeActions.setTypeAction(VT, Promote); 824 } 825 } 826 827 // Determine the 'representative' register class for each value type. 828 // An representative register class is the largest (meaning one which is 829 // not a sub-register class / subreg register class) legal register class for 830 // a group of value types. For example, on i386, i8, i16, and i32 831 // representative would be GR32; while on x86_64 it's GR64. 832 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 833 const TargetRegisterClass* RRC; 834 uint8_t Cost; 835 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 836 RepRegClassForVT[i] = RRC; 837 RepRegClassCostForVT[i] = Cost; 838 } 839} 840 841const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 842 return NULL; 843} 844 845 846MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 847 return PointerTy.SimpleTy; 848} 849 850MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 851 return MVT::i32; // return the default value 852} 853 854/// getVectorTypeBreakdown - Vector types are broken down into some number of 855/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 856/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 857/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 858/// 859/// This method returns the number of registers needed, and the VT for each 860/// register. It also returns the VT and quantity of the intermediate values 861/// before they are promoted/expanded. 862/// 863unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 864 EVT &IntermediateVT, 865 unsigned &NumIntermediates, 866 EVT &RegisterVT) const { 867 unsigned NumElts = VT.getVectorNumElements(); 868 869 // If there is a wider vector type with the same element type as this one, 870 // we should widen to that legal vector type. This handles things like 871 // <2 x float> -> <4 x float>. 872 if (NumElts != 1 && getTypeAction(VT) == Promote) { 873 RegisterVT = getTypeToTransformTo(Context, VT); 874 if (isTypeLegal(RegisterVT)) { 875 IntermediateVT = RegisterVT; 876 NumIntermediates = 1; 877 return 1; 878 } 879 } 880 881 // Figure out the right, legal destination reg to copy into. 882 EVT EltTy = VT.getVectorElementType(); 883 884 unsigned NumVectorRegs = 1; 885 886 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 887 // could break down into LHS/RHS like LegalizeDAG does. 888 if (!isPowerOf2_32(NumElts)) { 889 NumVectorRegs = NumElts; 890 NumElts = 1; 891 } 892 893 // Divide the input until we get to a supported size. This will always 894 // end with a scalar if the target doesn't support vectors. 895 while (NumElts > 1 && !isTypeLegal( 896 EVT::getVectorVT(Context, EltTy, NumElts))) { 897 NumElts >>= 1; 898 NumVectorRegs <<= 1; 899 } 900 901 NumIntermediates = NumVectorRegs; 902 903 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 904 if (!isTypeLegal(NewVT)) 905 NewVT = EltTy; 906 IntermediateVT = NewVT; 907 908 EVT DestVT = getRegisterType(Context, NewVT); 909 RegisterVT = DestVT; 910 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 911 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 912 913 // Otherwise, promotion or legal types use the same number of registers as 914 // the vector decimated to the appropriate level. 915 return NumVectorRegs; 916} 917 918/// Get the EVTs and ArgFlags collections that represent the legalized return 919/// type of the given function. This does not require a DAG or a return value, 920/// and is suitable for use before any DAGs for the function are constructed. 921/// TODO: Move this out of TargetLowering.cpp. 922void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr, 923 SmallVectorImpl<ISD::OutputArg> &Outs, 924 const TargetLowering &TLI, 925 SmallVectorImpl<uint64_t> *Offsets) { 926 SmallVector<EVT, 4> ValueVTs; 927 ComputeValueVTs(TLI, ReturnType, ValueVTs); 928 unsigned NumValues = ValueVTs.size(); 929 if (NumValues == 0) return; 930 unsigned Offset = 0; 931 932 for (unsigned j = 0, f = NumValues; j != f; ++j) { 933 EVT VT = ValueVTs[j]; 934 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 935 936 if (attr & Attribute::SExt) 937 ExtendKind = ISD::SIGN_EXTEND; 938 else if (attr & Attribute::ZExt) 939 ExtendKind = ISD::ZERO_EXTEND; 940 941 // FIXME: C calling convention requires the return type to be promoted to 942 // at least 32-bit. But this is not necessary for non-C calling 943 // conventions. The frontend should mark functions whose return values 944 // require promoting with signext or zeroext attributes. 945 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 946 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 947 if (VT.bitsLT(MinVT)) 948 VT = MinVT; 949 } 950 951 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 952 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 953 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 954 PartVT.getTypeForEVT(ReturnType->getContext())); 955 956 // 'inreg' on function refers to return value 957 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 958 if (attr & Attribute::InReg) 959 Flags.setInReg(); 960 961 // Propagate extension type if any 962 if (attr & Attribute::SExt) 963 Flags.setSExt(); 964 else if (attr & Attribute::ZExt) 965 Flags.setZExt(); 966 967 for (unsigned i = 0; i < NumParts; ++i) { 968 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true)); 969 if (Offsets) { 970 Offsets->push_back(Offset); 971 Offset += PartSize; 972 } 973 } 974 } 975} 976 977/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 978/// function arguments in the caller parameter area. This is the actual 979/// alignment, not its logarithm. 980unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 981 return TD->getCallFrameTypeAlignment(Ty); 982} 983 984/// getJumpTableEncoding - Return the entry encoding for a jump table in the 985/// current function. The returned value is a member of the 986/// MachineJumpTableInfo::JTEntryKind enum. 987unsigned TargetLowering::getJumpTableEncoding() const { 988 // In non-pic modes, just use the address of a block. 989 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 990 return MachineJumpTableInfo::EK_BlockAddress; 991 992 // In PIC mode, if the target supports a GPRel32 directive, use it. 993 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 994 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 995 996 // Otherwise, use a label difference. 997 return MachineJumpTableInfo::EK_LabelDifference32; 998} 999 1000SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1001 SelectionDAG &DAG) const { 1002 // If our PIC model is GP relative, use the global offset table as the base. 1003 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 1004 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 1005 return Table; 1006} 1007 1008/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1009/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1010/// MCExpr. 1011const MCExpr * 1012TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1013 unsigned JTI,MCContext &Ctx) const{ 1014 // The normal PIC reloc base is the label at the start of the jump table. 1015 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 1016} 1017 1018bool 1019TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1020 // Assume that everything is safe in static mode. 1021 if (getTargetMachine().getRelocationModel() == Reloc::Static) 1022 return true; 1023 1024 // In dynamic-no-pic mode, assume that known defined values are safe. 1025 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 1026 GA && 1027 !GA->getGlobal()->isDeclaration() && 1028 !GA->getGlobal()->isWeakForLinker()) 1029 return true; 1030 1031 // Otherwise assume nothing is safe. 1032 return false; 1033} 1034 1035//===----------------------------------------------------------------------===// 1036// Optimization Methods 1037//===----------------------------------------------------------------------===// 1038 1039/// ShrinkDemandedConstant - Check to see if the specified operand of the 1040/// specified instruction is a constant integer. If so, check to see if there 1041/// are any bits set in the constant that are not demanded. If so, shrink the 1042/// constant and return true. 1043bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 1044 const APInt &Demanded) { 1045 DebugLoc dl = Op.getDebugLoc(); 1046 1047 // FIXME: ISD::SELECT, ISD::SELECT_CC 1048 switch (Op.getOpcode()) { 1049 default: break; 1050 case ISD::XOR: 1051 case ISD::AND: 1052 case ISD::OR: { 1053 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1054 if (!C) return false; 1055 1056 if (Op.getOpcode() == ISD::XOR && 1057 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 1058 return false; 1059 1060 // if we can expand it to have all bits set, do it 1061 if (C->getAPIntValue().intersects(~Demanded)) { 1062 EVT VT = Op.getValueType(); 1063 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 1064 DAG.getConstant(Demanded & 1065 C->getAPIntValue(), 1066 VT)); 1067 return CombineTo(Op, New); 1068 } 1069 1070 break; 1071 } 1072 } 1073 1074 return false; 1075} 1076 1077/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1078/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1079/// cast, but it could be generalized for targets with other types of 1080/// implicit widening casts. 1081bool 1082TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 1083 unsigned BitWidth, 1084 const APInt &Demanded, 1085 DebugLoc dl) { 1086 assert(Op.getNumOperands() == 2 && 1087 "ShrinkDemandedOp only supports binary operators!"); 1088 assert(Op.getNode()->getNumValues() == 1 && 1089 "ShrinkDemandedOp only supports nodes with one result!"); 1090 1091 // Don't do this if the node has another user, which may require the 1092 // full value. 1093 if (!Op.getNode()->hasOneUse()) 1094 return false; 1095 1096 // Search for the smallest integer type with free casts to and from 1097 // Op's type. For expedience, just check power-of-2 integer types. 1098 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1099 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 1100 if (!isPowerOf2_32(SmallVTBits)) 1101 SmallVTBits = NextPowerOf2(SmallVTBits); 1102 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 1103 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 1104 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 1105 TLI.isZExtFree(SmallVT, Op.getValueType())) { 1106 // We found a type with free casts. 1107 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 1108 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1109 Op.getNode()->getOperand(0)), 1110 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1111 Op.getNode()->getOperand(1))); 1112 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 1113 return CombineTo(Op, Z); 1114 } 1115 } 1116 return false; 1117} 1118 1119/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1120/// DemandedMask bits of the result of Op are ever used downstream. If we can 1121/// use this information to simplify Op, create a new simplified DAG node and 1122/// return true, returning the original and new nodes in Old and New. Otherwise, 1123/// analyze the expression and return a mask of KnownOne and KnownZero bits for 1124/// the expression (used to simplify the caller). The KnownZero/One bits may 1125/// only be accurate for those bits in the DemandedMask. 1126bool TargetLowering::SimplifyDemandedBits(SDValue Op, 1127 const APInt &DemandedMask, 1128 APInt &KnownZero, 1129 APInt &KnownOne, 1130 TargetLoweringOpt &TLO, 1131 unsigned Depth) const { 1132 unsigned BitWidth = DemandedMask.getBitWidth(); 1133 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1134 "Mask size mismatches value type size!"); 1135 APInt NewMask = DemandedMask; 1136 DebugLoc dl = Op.getDebugLoc(); 1137 1138 // Don't know anything. 1139 KnownZero = KnownOne = APInt(BitWidth, 0); 1140 1141 // Other users may use these bits. 1142 if (!Op.getNode()->hasOneUse()) { 1143 if (Depth != 0) { 1144 // If not at the root, Just compute the KnownZero/KnownOne bits to 1145 // simplify things downstream. 1146 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 1147 return false; 1148 } 1149 // If this is the root being simplified, allow it to have multiple uses, 1150 // just set the NewMask to all bits. 1151 NewMask = APInt::getAllOnesValue(BitWidth); 1152 } else if (DemandedMask == 0) { 1153 // Not demanding any bits from Op. 1154 if (Op.getOpcode() != ISD::UNDEF) 1155 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1156 return false; 1157 } else if (Depth == 6) { // Limit search depth. 1158 return false; 1159 } 1160 1161 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1162 switch (Op.getOpcode()) { 1163 case ISD::Constant: 1164 // We know all of the bits for a constant! 1165 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 1166 KnownZero = ~KnownOne & NewMask; 1167 return false; // Don't fall through, will infinitely loop. 1168 case ISD::AND: 1169 // If the RHS is a constant, check to see if the LHS would be zero without 1170 // using the bits from the RHS. Below, we use knowledge about the RHS to 1171 // simplify the LHS, here we're using information from the LHS to simplify 1172 // the RHS. 1173 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1174 APInt LHSZero, LHSOne; 1175 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1176 LHSZero, LHSOne, Depth+1); 1177 // If the LHS already has zeros where RHSC does, this and is dead. 1178 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1179 return TLO.CombineTo(Op, Op.getOperand(0)); 1180 // If any of the set bits in the RHS are known zero on the LHS, shrink 1181 // the constant. 1182 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1183 return true; 1184 } 1185 1186 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1187 KnownOne, TLO, Depth+1)) 1188 return true; 1189 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1190 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1191 KnownZero2, KnownOne2, TLO, Depth+1)) 1192 return true; 1193 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1194 1195 // If all of the demanded bits are known one on one side, return the other. 1196 // These bits cannot contribute to the result of the 'and'. 1197 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1198 return TLO.CombineTo(Op, Op.getOperand(0)); 1199 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1200 return TLO.CombineTo(Op, Op.getOperand(1)); 1201 // If all of the demanded bits in the inputs are known zeros, return zero. 1202 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1203 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1204 // If the RHS is a constant, see if we can simplify it. 1205 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1206 return true; 1207 // If the operation can be done in a smaller type, do so. 1208 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1209 return true; 1210 1211 // Output known-1 bits are only known if set in both the LHS & RHS. 1212 KnownOne &= KnownOne2; 1213 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1214 KnownZero |= KnownZero2; 1215 break; 1216 case ISD::OR: 1217 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1218 KnownOne, TLO, Depth+1)) 1219 return true; 1220 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1221 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1222 KnownZero2, KnownOne2, TLO, Depth+1)) 1223 return true; 1224 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1225 1226 // If all of the demanded bits are known zero on one side, return the other. 1227 // These bits cannot contribute to the result of the 'or'. 1228 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1229 return TLO.CombineTo(Op, Op.getOperand(0)); 1230 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1231 return TLO.CombineTo(Op, Op.getOperand(1)); 1232 // If all of the potentially set bits on one side are known to be set on 1233 // the other side, just use the 'other' side. 1234 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1235 return TLO.CombineTo(Op, Op.getOperand(0)); 1236 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1237 return TLO.CombineTo(Op, Op.getOperand(1)); 1238 // If the RHS is a constant, see if we can simplify it. 1239 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1240 return true; 1241 // If the operation can be done in a smaller type, do so. 1242 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1243 return true; 1244 1245 // Output known-0 bits are only known if clear in both the LHS & RHS. 1246 KnownZero &= KnownZero2; 1247 // Output known-1 are known to be set if set in either the LHS | RHS. 1248 KnownOne |= KnownOne2; 1249 break; 1250 case ISD::XOR: 1251 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1252 KnownOne, TLO, Depth+1)) 1253 return true; 1254 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1255 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1256 KnownOne2, TLO, Depth+1)) 1257 return true; 1258 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1259 1260 // If all of the demanded bits are known zero on one side, return the other. 1261 // These bits cannot contribute to the result of the 'xor'. 1262 if ((KnownZero & NewMask) == NewMask) 1263 return TLO.CombineTo(Op, Op.getOperand(0)); 1264 if ((KnownZero2 & NewMask) == NewMask) 1265 return TLO.CombineTo(Op, Op.getOperand(1)); 1266 // If the operation can be done in a smaller type, do so. 1267 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1268 return true; 1269 1270 // If all of the unknown bits are known to be zero on one side or the other 1271 // (but not both) turn this into an *inclusive* or. 1272 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1273 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1274 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1275 Op.getOperand(0), 1276 Op.getOperand(1))); 1277 1278 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1279 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1280 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1281 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1282 1283 // If all of the demanded bits on one side are known, and all of the set 1284 // bits on that side are also known to be set on the other side, turn this 1285 // into an AND, as we know the bits will be cleared. 1286 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1287 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1288 if ((KnownOne & KnownOne2) == KnownOne) { 1289 EVT VT = Op.getValueType(); 1290 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1291 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1292 Op.getOperand(0), ANDC)); 1293 } 1294 } 1295 1296 // If the RHS is a constant, see if we can simplify it. 1297 // for XOR, we prefer to force bits to 1 if they will make a -1. 1298 // if we can't force bits, try to shrink constant 1299 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1300 APInt Expanded = C->getAPIntValue() | (~NewMask); 1301 // if we can expand it to have all bits set, do it 1302 if (Expanded.isAllOnesValue()) { 1303 if (Expanded != C->getAPIntValue()) { 1304 EVT VT = Op.getValueType(); 1305 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1306 TLO.DAG.getConstant(Expanded, VT)); 1307 return TLO.CombineTo(Op, New); 1308 } 1309 // if it already has all the bits set, nothing to change 1310 // but don't shrink either! 1311 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1312 return true; 1313 } 1314 } 1315 1316 KnownZero = KnownZeroOut; 1317 KnownOne = KnownOneOut; 1318 break; 1319 case ISD::SELECT: 1320 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1321 KnownOne, TLO, Depth+1)) 1322 return true; 1323 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1324 KnownOne2, TLO, Depth+1)) 1325 return true; 1326 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1327 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1328 1329 // If the operands are constants, see if we can simplify them. 1330 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1331 return true; 1332 1333 // Only known if known in both the LHS and RHS. 1334 KnownOne &= KnownOne2; 1335 KnownZero &= KnownZero2; 1336 break; 1337 case ISD::SELECT_CC: 1338 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1339 KnownOne, TLO, Depth+1)) 1340 return true; 1341 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1342 KnownOne2, TLO, Depth+1)) 1343 return true; 1344 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1345 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1346 1347 // If the operands are constants, see if we can simplify them. 1348 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1349 return true; 1350 1351 // Only known if known in both the LHS and RHS. 1352 KnownOne &= KnownOne2; 1353 KnownZero &= KnownZero2; 1354 break; 1355 case ISD::SHL: 1356 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1357 unsigned ShAmt = SA->getZExtValue(); 1358 SDValue InOp = Op.getOperand(0); 1359 1360 // If the shift count is an invalid immediate, don't do anything. 1361 if (ShAmt >= BitWidth) 1362 break; 1363 1364 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1365 // single shift. We can do this if the bottom bits (which are shifted 1366 // out) are never demanded. 1367 if (InOp.getOpcode() == ISD::SRL && 1368 isa<ConstantSDNode>(InOp.getOperand(1))) { 1369 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1370 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1371 unsigned Opc = ISD::SHL; 1372 int Diff = ShAmt-C1; 1373 if (Diff < 0) { 1374 Diff = -Diff; 1375 Opc = ISD::SRL; 1376 } 1377 1378 SDValue NewSA = 1379 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1380 EVT VT = Op.getValueType(); 1381 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1382 InOp.getOperand(0), NewSA)); 1383 } 1384 } 1385 1386 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 1387 KnownZero, KnownOne, TLO, Depth+1)) 1388 return true; 1389 1390 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 1391 // are not demanded. This will likely allow the anyext to be folded away. 1392 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 1393 SDValue InnerOp = InOp.getNode()->getOperand(0); 1394 EVT InnerVT = InnerOp.getValueType(); 1395 if ((APInt::getHighBitsSet(BitWidth, 1396 BitWidth - InnerVT.getSizeInBits()) & 1397 DemandedMask) == 0 && 1398 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 1399 EVT ShTy = getShiftAmountTy(); 1400 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 1401 ShTy = InnerVT; 1402 SDValue NarrowShl = 1403 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 1404 TLO.DAG.getConstant(ShAmt, ShTy)); 1405 return 1406 TLO.CombineTo(Op, 1407 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 1408 NarrowShl)); 1409 } 1410 } 1411 1412 KnownZero <<= SA->getZExtValue(); 1413 KnownOne <<= SA->getZExtValue(); 1414 // low bits known zero. 1415 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1416 } 1417 break; 1418 case ISD::SRL: 1419 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1420 EVT VT = Op.getValueType(); 1421 unsigned ShAmt = SA->getZExtValue(); 1422 unsigned VTSize = VT.getSizeInBits(); 1423 SDValue InOp = Op.getOperand(0); 1424 1425 // If the shift count is an invalid immediate, don't do anything. 1426 if (ShAmt >= BitWidth) 1427 break; 1428 1429 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1430 // single shift. We can do this if the top bits (which are shifted out) 1431 // are never demanded. 1432 if (InOp.getOpcode() == ISD::SHL && 1433 isa<ConstantSDNode>(InOp.getOperand(1))) { 1434 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1435 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1436 unsigned Opc = ISD::SRL; 1437 int Diff = ShAmt-C1; 1438 if (Diff < 0) { 1439 Diff = -Diff; 1440 Opc = ISD::SHL; 1441 } 1442 1443 SDValue NewSA = 1444 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1445 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1446 InOp.getOperand(0), NewSA)); 1447 } 1448 } 1449 1450 // Compute the new bits that are at the top now. 1451 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1452 KnownZero, KnownOne, TLO, Depth+1)) 1453 return true; 1454 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1455 KnownZero = KnownZero.lshr(ShAmt); 1456 KnownOne = KnownOne.lshr(ShAmt); 1457 1458 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1459 KnownZero |= HighBits; // High bits known zero. 1460 } 1461 break; 1462 case ISD::SRA: 1463 // If this is an arithmetic shift right and only the low-bit is set, we can 1464 // always convert this into a logical shr, even if the shift amount is 1465 // variable. The low bit of the shift cannot be an input sign bit unless 1466 // the shift amount is >= the size of the datatype, which is undefined. 1467 if (DemandedMask == 1) 1468 return TLO.CombineTo(Op, 1469 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1470 Op.getOperand(0), Op.getOperand(1))); 1471 1472 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1473 EVT VT = Op.getValueType(); 1474 unsigned ShAmt = SA->getZExtValue(); 1475 1476 // If the shift count is an invalid immediate, don't do anything. 1477 if (ShAmt >= BitWidth) 1478 break; 1479 1480 APInt InDemandedMask = (NewMask << ShAmt); 1481 1482 // If any of the demanded bits are produced by the sign extension, we also 1483 // demand the input sign bit. 1484 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1485 if (HighBits.intersects(NewMask)) 1486 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1487 1488 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1489 KnownZero, KnownOne, TLO, Depth+1)) 1490 return true; 1491 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1492 KnownZero = KnownZero.lshr(ShAmt); 1493 KnownOne = KnownOne.lshr(ShAmt); 1494 1495 // Handle the sign bit, adjusted to where it is now in the mask. 1496 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1497 1498 // If the input sign bit is known to be zero, or if none of the top bits 1499 // are demanded, turn this into an unsigned shift right. 1500 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1501 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1502 Op.getOperand(0), 1503 Op.getOperand(1))); 1504 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1505 KnownOne |= HighBits; 1506 } 1507 } 1508 break; 1509 case ISD::SIGN_EXTEND_INREG: { 1510 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1511 1512 // Sign extension. Compute the demanded bits in the result that are not 1513 // present in the input. 1514 APInt NewBits = 1515 APInt::getHighBitsSet(BitWidth, 1516 BitWidth - EVT.getScalarType().getSizeInBits()); 1517 1518 // If none of the extended bits are demanded, eliminate the sextinreg. 1519 if ((NewBits & NewMask) == 0) 1520 return TLO.CombineTo(Op, Op.getOperand(0)); 1521 1522 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits()); 1523 InSignBit.zext(BitWidth); 1524 APInt InputDemandedBits = 1525 APInt::getLowBitsSet(BitWidth, 1526 EVT.getScalarType().getSizeInBits()) & 1527 NewMask; 1528 1529 // Since the sign extended bits are demanded, we know that the sign 1530 // bit is demanded. 1531 InputDemandedBits |= InSignBit; 1532 1533 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1534 KnownZero, KnownOne, TLO, Depth+1)) 1535 return true; 1536 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1537 1538 // If the sign bit of the input is known set or clear, then we know the 1539 // top bits of the result. 1540 1541 // If the input sign bit is known zero, convert this into a zero extension. 1542 if (KnownZero.intersects(InSignBit)) 1543 return TLO.CombineTo(Op, 1544 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1545 1546 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1547 KnownOne |= NewBits; 1548 KnownZero &= ~NewBits; 1549 } else { // Input sign bit unknown 1550 KnownZero &= ~NewBits; 1551 KnownOne &= ~NewBits; 1552 } 1553 break; 1554 } 1555 case ISD::ZERO_EXTEND: { 1556 unsigned OperandBitWidth = 1557 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1558 APInt InMask = NewMask; 1559 InMask.trunc(OperandBitWidth); 1560 1561 // If none of the top bits are demanded, convert this into an any_extend. 1562 APInt NewBits = 1563 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1564 if (!NewBits.intersects(NewMask)) 1565 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1566 Op.getValueType(), 1567 Op.getOperand(0))); 1568 1569 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1570 KnownZero, KnownOne, TLO, Depth+1)) 1571 return true; 1572 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1573 KnownZero.zext(BitWidth); 1574 KnownOne.zext(BitWidth); 1575 KnownZero |= NewBits; 1576 break; 1577 } 1578 case ISD::SIGN_EXTEND: { 1579 EVT InVT = Op.getOperand(0).getValueType(); 1580 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1581 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1582 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1583 APInt NewBits = ~InMask & NewMask; 1584 1585 // If none of the top bits are demanded, convert this into an any_extend. 1586 if (NewBits == 0) 1587 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1588 Op.getValueType(), 1589 Op.getOperand(0))); 1590 1591 // Since some of the sign extended bits are demanded, we know that the sign 1592 // bit is demanded. 1593 APInt InDemandedBits = InMask & NewMask; 1594 InDemandedBits |= InSignBit; 1595 InDemandedBits.trunc(InBits); 1596 1597 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1598 KnownOne, TLO, Depth+1)) 1599 return true; 1600 KnownZero.zext(BitWidth); 1601 KnownOne.zext(BitWidth); 1602 1603 // If the sign bit is known zero, convert this to a zero extend. 1604 if (KnownZero.intersects(InSignBit)) 1605 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1606 Op.getValueType(), 1607 Op.getOperand(0))); 1608 1609 // If the sign bit is known one, the top bits match. 1610 if (KnownOne.intersects(InSignBit)) { 1611 KnownOne |= NewBits; 1612 KnownZero &= ~NewBits; 1613 } else { // Otherwise, top bits aren't known. 1614 KnownOne &= ~NewBits; 1615 KnownZero &= ~NewBits; 1616 } 1617 break; 1618 } 1619 case ISD::ANY_EXTEND: { 1620 unsigned OperandBitWidth = 1621 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1622 APInt InMask = NewMask; 1623 InMask.trunc(OperandBitWidth); 1624 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1625 KnownZero, KnownOne, TLO, Depth+1)) 1626 return true; 1627 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1628 KnownZero.zext(BitWidth); 1629 KnownOne.zext(BitWidth); 1630 break; 1631 } 1632 case ISD::TRUNCATE: { 1633 // Simplify the input, using demanded bit information, and compute the known 1634 // zero/one bits live out. 1635 unsigned OperandBitWidth = 1636 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1637 APInt TruncMask = NewMask; 1638 TruncMask.zext(OperandBitWidth); 1639 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1640 KnownZero, KnownOne, TLO, Depth+1)) 1641 return true; 1642 KnownZero.trunc(BitWidth); 1643 KnownOne.trunc(BitWidth); 1644 1645 // If the input is only used by this truncate, see if we can shrink it based 1646 // on the known demanded bits. 1647 if (Op.getOperand(0).getNode()->hasOneUse()) { 1648 SDValue In = Op.getOperand(0); 1649 switch (In.getOpcode()) { 1650 default: break; 1651 case ISD::SRL: 1652 // Shrink SRL by a constant if none of the high bits shifted in are 1653 // demanded. 1654 if (TLO.LegalTypes() && 1655 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1656 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1657 // undesirable. 1658 break; 1659 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1660 if (!ShAmt) 1661 break; 1662 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1663 OperandBitWidth - BitWidth); 1664 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1665 HighBits.trunc(BitWidth); 1666 1667 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1668 // None of the shifted in bits are needed. Add a truncate of the 1669 // shift input, then shift it. 1670 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1671 Op.getValueType(), 1672 In.getOperand(0)); 1673 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1674 Op.getValueType(), 1675 NewTrunc, 1676 In.getOperand(1))); 1677 } 1678 break; 1679 } 1680 } 1681 1682 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1683 break; 1684 } 1685 case ISD::AssertZext: { 1686 // Demand all the bits of the input that are demanded in the output. 1687 // The low bits are obvious; the high bits are demanded because we're 1688 // asserting that they're zero here. 1689 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, 1690 KnownZero, KnownOne, TLO, Depth+1)) 1691 return true; 1692 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1693 1694 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1695 APInt InMask = APInt::getLowBitsSet(BitWidth, 1696 VT.getSizeInBits()); 1697 KnownZero |= ~InMask & NewMask; 1698 break; 1699 } 1700 case ISD::BIT_CONVERT: 1701#if 0 1702 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1703 // is demanded, turn this into a FGETSIGN. 1704 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) && 1705 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1706 !MVT::isVector(Op.getOperand(0).getValueType())) { 1707 // Only do this xform if FGETSIGN is valid or if before legalize. 1708 if (!TLO.AfterLegalize || 1709 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1710 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1711 // place. We expect the SHL to be eliminated by other optimizations. 1712 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1713 Op.getOperand(0)); 1714 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1715 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1716 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1717 Sign, ShAmt)); 1718 } 1719 } 1720#endif 1721 break; 1722 case ISD::ADD: 1723 case ISD::MUL: 1724 case ISD::SUB: { 1725 // Add, Sub, and Mul don't demand any bits in positions beyond that 1726 // of the highest bit demanded of them. 1727 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1728 BitWidth - NewMask.countLeadingZeros()); 1729 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1730 KnownOne2, TLO, Depth+1)) 1731 return true; 1732 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1733 KnownOne2, TLO, Depth+1)) 1734 return true; 1735 // See if the operation should be performed at a smaller bit width. 1736 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1737 return true; 1738 } 1739 // FALL THROUGH 1740 default: 1741 // Just use ComputeMaskedBits to compute output bits. 1742 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1743 break; 1744 } 1745 1746 // If we know the value of all of the demanded bits, return this as a 1747 // constant. 1748 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1749 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1750 1751 return false; 1752} 1753 1754/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1755/// in Mask are known to be either zero or one and return them in the 1756/// KnownZero/KnownOne bitsets. 1757void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1758 const APInt &Mask, 1759 APInt &KnownZero, 1760 APInt &KnownOne, 1761 const SelectionDAG &DAG, 1762 unsigned Depth) const { 1763 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1764 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1765 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1766 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1767 "Should use MaskedValueIsZero if you don't know whether Op" 1768 " is a target node!"); 1769 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1770} 1771 1772/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1773/// targets that want to expose additional information about sign bits to the 1774/// DAG Combiner. 1775unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1776 unsigned Depth) const { 1777 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1778 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1779 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1780 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1781 "Should use ComputeNumSignBits if you don't know whether Op" 1782 " is a target node!"); 1783 return 1; 1784} 1785 1786/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1787/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1788/// determine which bit is set. 1789/// 1790static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1791 // A left-shift of a constant one will have exactly one bit set, because 1792 // shifting the bit off the end is undefined. 1793 if (Val.getOpcode() == ISD::SHL) 1794 if (ConstantSDNode *C = 1795 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1796 if (C->getAPIntValue() == 1) 1797 return true; 1798 1799 // Similarly, a right-shift of a constant sign-bit will have exactly 1800 // one bit set. 1801 if (Val.getOpcode() == ISD::SRL) 1802 if (ConstantSDNode *C = 1803 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1804 if (C->getAPIntValue().isSignBit()) 1805 return true; 1806 1807 // More could be done here, though the above checks are enough 1808 // to handle some common cases. 1809 1810 // Fall back to ComputeMaskedBits to catch other known cases. 1811 EVT OpVT = Val.getValueType(); 1812 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1813 APInt Mask = APInt::getAllOnesValue(BitWidth); 1814 APInt KnownZero, KnownOne; 1815 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1816 return (KnownZero.countPopulation() == BitWidth - 1) && 1817 (KnownOne.countPopulation() == 1); 1818} 1819 1820/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1821/// and cc. If it is unable to simplify it, return a null SDValue. 1822SDValue 1823TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1824 ISD::CondCode Cond, bool foldBooleans, 1825 DAGCombinerInfo &DCI, DebugLoc dl) const { 1826 SelectionDAG &DAG = DCI.DAG; 1827 LLVMContext &Context = *DAG.getContext(); 1828 1829 // These setcc operations always fold. 1830 switch (Cond) { 1831 default: break; 1832 case ISD::SETFALSE: 1833 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1834 case ISD::SETTRUE: 1835 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1836 } 1837 1838 if (isa<ConstantSDNode>(N0.getNode())) { 1839 // Ensure that the constant occurs on the RHS, and fold constant 1840 // comparisons. 1841 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1842 } 1843 1844 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1845 const APInt &C1 = N1C->getAPIntValue(); 1846 1847 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1848 // equality comparison, then we're just comparing whether X itself is 1849 // zero. 1850 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1851 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1852 N0.getOperand(1).getOpcode() == ISD::Constant) { 1853 const APInt &ShAmt 1854 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1855 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1856 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1857 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1858 // (srl (ctlz x), 5) == 0 -> X != 0 1859 // (srl (ctlz x), 5) != 1 -> X != 0 1860 Cond = ISD::SETNE; 1861 } else { 1862 // (srl (ctlz x), 5) != 0 -> X == 0 1863 // (srl (ctlz x), 5) == 1 -> X == 0 1864 Cond = ISD::SETEQ; 1865 } 1866 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1867 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1868 Zero, Cond); 1869 } 1870 } 1871 1872 // If the LHS is '(and load, const)', the RHS is 0, 1873 // the test is for equality or unsigned, and all 1 bits of the const are 1874 // in the same partial word, see if we can shorten the load. 1875 if (DCI.isBeforeLegalize() && 1876 N0.getOpcode() == ISD::AND && C1 == 0 && 1877 N0.getNode()->hasOneUse() && 1878 isa<LoadSDNode>(N0.getOperand(0)) && 1879 N0.getOperand(0).getNode()->hasOneUse() && 1880 isa<ConstantSDNode>(N0.getOperand(1))) { 1881 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1882 APInt bestMask; 1883 unsigned bestWidth = 0, bestOffset = 0; 1884 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1885 unsigned origWidth = N0.getValueType().getSizeInBits(); 1886 unsigned maskWidth = origWidth; 1887 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1888 // 8 bits, but have to be careful... 1889 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1890 origWidth = Lod->getMemoryVT().getSizeInBits(); 1891 const APInt &Mask = 1892 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1893 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1894 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1895 for (unsigned offset=0; offset<origWidth/width; offset++) { 1896 if ((newMask & Mask) == Mask) { 1897 if (!TD->isLittleEndian()) 1898 bestOffset = (origWidth/width - offset - 1) * (width/8); 1899 else 1900 bestOffset = (uint64_t)offset * (width/8); 1901 bestMask = Mask.lshr(offset * (width/8) * 8); 1902 bestWidth = width; 1903 break; 1904 } 1905 newMask = newMask << width; 1906 } 1907 } 1908 } 1909 if (bestWidth) { 1910 EVT newVT = EVT::getIntegerVT(Context, bestWidth); 1911 if (newVT.isRound()) { 1912 EVT PtrType = Lod->getOperand(1).getValueType(); 1913 SDValue Ptr = Lod->getBasePtr(); 1914 if (bestOffset != 0) 1915 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1916 DAG.getConstant(bestOffset, PtrType)); 1917 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1918 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1919 Lod->getPointerInfo().getWithOffset(bestOffset), 1920 false, false, NewAlign); 1921 return DAG.getSetCC(dl, VT, 1922 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1923 DAG.getConstant(bestMask.trunc(bestWidth), 1924 newVT)), 1925 DAG.getConstant(0LL, newVT), Cond); 1926 } 1927 } 1928 } 1929 1930 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1931 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1932 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1933 1934 // If the comparison constant has bits in the upper part, the 1935 // zero-extended value could never match. 1936 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1937 C1.getBitWidth() - InSize))) { 1938 switch (Cond) { 1939 case ISD::SETUGT: 1940 case ISD::SETUGE: 1941 case ISD::SETEQ: return DAG.getConstant(0, VT); 1942 case ISD::SETULT: 1943 case ISD::SETULE: 1944 case ISD::SETNE: return DAG.getConstant(1, VT); 1945 case ISD::SETGT: 1946 case ISD::SETGE: 1947 // True if the sign bit of C1 is set. 1948 return DAG.getConstant(C1.isNegative(), VT); 1949 case ISD::SETLT: 1950 case ISD::SETLE: 1951 // True if the sign bit of C1 isn't set. 1952 return DAG.getConstant(C1.isNonNegative(), VT); 1953 default: 1954 break; 1955 } 1956 } 1957 1958 // Otherwise, we can perform the comparison with the low bits. 1959 switch (Cond) { 1960 case ISD::SETEQ: 1961 case ISD::SETNE: 1962 case ISD::SETUGT: 1963 case ISD::SETUGE: 1964 case ISD::SETULT: 1965 case ISD::SETULE: { 1966 EVT newVT = N0.getOperand(0).getValueType(); 1967 if (DCI.isBeforeLegalizeOps() || 1968 (isOperationLegal(ISD::SETCC, newVT) && 1969 getCondCodeAction(Cond, newVT)==Legal)) 1970 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1971 DAG.getConstant(APInt(C1).trunc(InSize), newVT), 1972 Cond); 1973 break; 1974 } 1975 default: 1976 break; // todo, be more careful with signed comparisons 1977 } 1978 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1979 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1980 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1981 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1982 EVT ExtDstTy = N0.getValueType(); 1983 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1984 1985 // If the constant doesn't fit into the number of bits for the source of 1986 // the sign extension, it is impossible for both sides to be equal. 1987 if (C1.getMinSignedBits() > ExtSrcTyBits) 1988 return DAG.getConstant(Cond == ISD::SETNE, VT); 1989 1990 SDValue ZextOp; 1991 EVT Op0Ty = N0.getOperand(0).getValueType(); 1992 if (Op0Ty == ExtSrcTy) { 1993 ZextOp = N0.getOperand(0); 1994 } else { 1995 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1996 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1997 DAG.getConstant(Imm, Op0Ty)); 1998 } 1999 if (!DCI.isCalledByLegalizer()) 2000 DCI.AddToWorklist(ZextOp.getNode()); 2001 // Otherwise, make this a use of a zext. 2002 return DAG.getSetCC(dl, VT, ZextOp, 2003 DAG.getConstant(C1 & APInt::getLowBitsSet( 2004 ExtDstTyBits, 2005 ExtSrcTyBits), 2006 ExtDstTy), 2007 Cond); 2008 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 2009 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2010 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 2011 if (N0.getOpcode() == ISD::SETCC && 2012 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 2013 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 2014 if (TrueWhenTrue) 2015 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 2016 // Invert the condition. 2017 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 2018 CC = ISD::getSetCCInverse(CC, 2019 N0.getOperand(0).getValueType().isInteger()); 2020 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 2021 } 2022 2023 if ((N0.getOpcode() == ISD::XOR || 2024 (N0.getOpcode() == ISD::AND && 2025 N0.getOperand(0).getOpcode() == ISD::XOR && 2026 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2027 isa<ConstantSDNode>(N0.getOperand(1)) && 2028 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 2029 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 2030 // can only do this if the top bits are known zero. 2031 unsigned BitWidth = N0.getValueSizeInBits(); 2032 if (DAG.MaskedValueIsZero(N0, 2033 APInt::getHighBitsSet(BitWidth, 2034 BitWidth-1))) { 2035 // Okay, get the un-inverted input value. 2036 SDValue Val; 2037 if (N0.getOpcode() == ISD::XOR) 2038 Val = N0.getOperand(0); 2039 else { 2040 assert(N0.getOpcode() == ISD::AND && 2041 N0.getOperand(0).getOpcode() == ISD::XOR); 2042 // ((X^1)&1)^1 -> X & 1 2043 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 2044 N0.getOperand(0).getOperand(0), 2045 N0.getOperand(1)); 2046 } 2047 2048 return DAG.getSetCC(dl, VT, Val, N1, 2049 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2050 } 2051 } else if (N1C->getAPIntValue() == 1 && 2052 (VT == MVT::i1 || 2053 getBooleanContents() == ZeroOrOneBooleanContent)) { 2054 SDValue Op0 = N0; 2055 if (Op0.getOpcode() == ISD::TRUNCATE) 2056 Op0 = Op0.getOperand(0); 2057 2058 if ((Op0.getOpcode() == ISD::XOR) && 2059 Op0.getOperand(0).getOpcode() == ISD::SETCC && 2060 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 2061 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 2062 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 2063 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 2064 Cond); 2065 } else if (Op0.getOpcode() == ISD::AND && 2066 isa<ConstantSDNode>(Op0.getOperand(1)) && 2067 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 2068 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 2069 if (Op0.getValueType().bitsGT(VT)) 2070 Op0 = DAG.getNode(ISD::AND, dl, VT, 2071 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 2072 DAG.getConstant(1, VT)); 2073 else if (Op0.getValueType().bitsLT(VT)) 2074 Op0 = DAG.getNode(ISD::AND, dl, VT, 2075 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 2076 DAG.getConstant(1, VT)); 2077 2078 return DAG.getSetCC(dl, VT, Op0, 2079 DAG.getConstant(0, Op0.getValueType()), 2080 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2081 } 2082 } 2083 } 2084 2085 APInt MinVal, MaxVal; 2086 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 2087 if (ISD::isSignedIntSetCC(Cond)) { 2088 MinVal = APInt::getSignedMinValue(OperandBitSize); 2089 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 2090 } else { 2091 MinVal = APInt::getMinValue(OperandBitSize); 2092 MaxVal = APInt::getMaxValue(OperandBitSize); 2093 } 2094 2095 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2096 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2097 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2098 // X >= C0 --> X > (C0-1) 2099 return DAG.getSetCC(dl, VT, N0, 2100 DAG.getConstant(C1-1, N1.getValueType()), 2101 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2102 } 2103 2104 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2105 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2106 // X <= C0 --> X < (C0+1) 2107 return DAG.getSetCC(dl, VT, N0, 2108 DAG.getConstant(C1+1, N1.getValueType()), 2109 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2110 } 2111 2112 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2113 return DAG.getConstant(0, VT); // X < MIN --> false 2114 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 2115 return DAG.getConstant(1, VT); // X >= MIN --> true 2116 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 2117 return DAG.getConstant(0, VT); // X > MAX --> false 2118 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 2119 return DAG.getConstant(1, VT); // X <= MAX --> true 2120 2121 // Canonicalize setgt X, Min --> setne X, Min 2122 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2123 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2124 // Canonicalize setlt X, Max --> setne X, Max 2125 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2126 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2127 2128 // If we have setult X, 1, turn it into seteq X, 0 2129 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2130 return DAG.getSetCC(dl, VT, N0, 2131 DAG.getConstant(MinVal, N0.getValueType()), 2132 ISD::SETEQ); 2133 // If we have setugt X, Max-1, turn it into seteq X, Max 2134 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2135 return DAG.getSetCC(dl, VT, N0, 2136 DAG.getConstant(MaxVal, N0.getValueType()), 2137 ISD::SETEQ); 2138 2139 // If we have "setcc X, C0", check to see if we can shrink the immediate 2140 // by changing cc. 2141 2142 // SETUGT X, SINTMAX -> SETLT X, 0 2143 if (Cond == ISD::SETUGT && 2144 C1 == APInt::getSignedMaxValue(OperandBitSize)) 2145 return DAG.getSetCC(dl, VT, N0, 2146 DAG.getConstant(0, N1.getValueType()), 2147 ISD::SETLT); 2148 2149 // SETULT X, SINTMIN -> SETGT X, -1 2150 if (Cond == ISD::SETULT && 2151 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2152 SDValue ConstMinusOne = 2153 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2154 N1.getValueType()); 2155 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2156 } 2157 2158 // Fold bit comparisons when we can. 2159 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2160 (VT == N0.getValueType() || 2161 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2162 N0.getOpcode() == ISD::AND) 2163 if (ConstantSDNode *AndRHS = 2164 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2165 EVT ShiftTy = DCI.isBeforeLegalize() ? 2166 getPointerTy() : getShiftAmountTy(); 2167 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2168 // Perform the xform if the AND RHS is a single bit. 2169 if (AndRHS->getAPIntValue().isPowerOf2()) { 2170 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2171 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2172 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2173 } 2174 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2175 // (X & 8) == 8 --> (X & 8) >> 3 2176 // Perform the xform if C1 is a single bit. 2177 if (C1.isPowerOf2()) { 2178 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2179 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2180 DAG.getConstant(C1.logBase2(), ShiftTy))); 2181 } 2182 } 2183 } 2184 } 2185 2186 if (isa<ConstantFPSDNode>(N0.getNode())) { 2187 // Constant fold or commute setcc. 2188 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2189 if (O.getNode()) return O; 2190 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2191 // If the RHS of an FP comparison is a constant, simplify it away in 2192 // some cases. 2193 if (CFP->getValueAPF().isNaN()) { 2194 // If an operand is known to be a nan, we can fold it. 2195 switch (ISD::getUnorderedFlavor(Cond)) { 2196 default: llvm_unreachable("Unknown flavor!"); 2197 case 0: // Known false. 2198 return DAG.getConstant(0, VT); 2199 case 1: // Known true. 2200 return DAG.getConstant(1, VT); 2201 case 2: // Undefined. 2202 return DAG.getUNDEF(VT); 2203 } 2204 } 2205 2206 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2207 // constant if knowing that the operand is non-nan is enough. We prefer to 2208 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2209 // materialize 0.0. 2210 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2211 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2212 2213 // If the condition is not legal, see if we can find an equivalent one 2214 // which is legal. 2215 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2216 // If the comparison was an awkward floating-point == or != and one of 2217 // the comparison operands is infinity or negative infinity, convert the 2218 // condition to a less-awkward <= or >=. 2219 if (CFP->getValueAPF().isInfinity()) { 2220 if (CFP->getValueAPF().isNegative()) { 2221 if (Cond == ISD::SETOEQ && 2222 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2223 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2224 if (Cond == ISD::SETUEQ && 2225 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2226 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2227 if (Cond == ISD::SETUNE && 2228 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2229 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2230 if (Cond == ISD::SETONE && 2231 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2232 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2233 } else { 2234 if (Cond == ISD::SETOEQ && 2235 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2236 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2237 if (Cond == ISD::SETUEQ && 2238 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2239 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2240 if (Cond == ISD::SETUNE && 2241 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2242 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2243 if (Cond == ISD::SETONE && 2244 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2245 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2246 } 2247 } 2248 } 2249 } 2250 2251 if (N0 == N1) { 2252 // We can always fold X == X for integer setcc's. 2253 if (N0.getValueType().isInteger()) 2254 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2255 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2256 if (UOF == 2) // FP operators that are undefined on NaNs. 2257 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2258 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2259 return DAG.getConstant(UOF, VT); 2260 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2261 // if it is not already. 2262 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2263 if (NewCond != Cond) 2264 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2265 } 2266 2267 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2268 N0.getValueType().isInteger()) { 2269 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2270 N0.getOpcode() == ISD::XOR) { 2271 // Simplify (X+Y) == (X+Z) --> Y == Z 2272 if (N0.getOpcode() == N1.getOpcode()) { 2273 if (N0.getOperand(0) == N1.getOperand(0)) 2274 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2275 if (N0.getOperand(1) == N1.getOperand(1)) 2276 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2277 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2278 // If X op Y == Y op X, try other combinations. 2279 if (N0.getOperand(0) == N1.getOperand(1)) 2280 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2281 Cond); 2282 if (N0.getOperand(1) == N1.getOperand(0)) 2283 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2284 Cond); 2285 } 2286 } 2287 2288 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2289 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2290 // Turn (X+C1) == C2 --> X == C2-C1 2291 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2292 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2293 DAG.getConstant(RHSC->getAPIntValue()- 2294 LHSR->getAPIntValue(), 2295 N0.getValueType()), Cond); 2296 } 2297 2298 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2299 if (N0.getOpcode() == ISD::XOR) 2300 // If we know that all of the inverted bits are zero, don't bother 2301 // performing the inversion. 2302 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2303 return 2304 DAG.getSetCC(dl, VT, N0.getOperand(0), 2305 DAG.getConstant(LHSR->getAPIntValue() ^ 2306 RHSC->getAPIntValue(), 2307 N0.getValueType()), 2308 Cond); 2309 } 2310 2311 // Turn (C1-X) == C2 --> X == C1-C2 2312 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2313 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2314 return 2315 DAG.getSetCC(dl, VT, N0.getOperand(1), 2316 DAG.getConstant(SUBC->getAPIntValue() - 2317 RHSC->getAPIntValue(), 2318 N0.getValueType()), 2319 Cond); 2320 } 2321 } 2322 } 2323 2324 // Simplify (X+Z) == X --> Z == 0 2325 if (N0.getOperand(0) == N1) 2326 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2327 DAG.getConstant(0, N0.getValueType()), Cond); 2328 if (N0.getOperand(1) == N1) { 2329 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2330 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2331 DAG.getConstant(0, N0.getValueType()), Cond); 2332 else if (N0.getNode()->hasOneUse()) { 2333 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2334 // (Z-X) == X --> Z == X<<1 2335 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2336 N1, 2337 DAG.getConstant(1, getShiftAmountTy())); 2338 if (!DCI.isCalledByLegalizer()) 2339 DCI.AddToWorklist(SH.getNode()); 2340 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2341 } 2342 } 2343 } 2344 2345 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2346 N1.getOpcode() == ISD::XOR) { 2347 // Simplify X == (X+Z) --> Z == 0 2348 if (N1.getOperand(0) == N0) { 2349 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2350 DAG.getConstant(0, N1.getValueType()), Cond); 2351 } else if (N1.getOperand(1) == N0) { 2352 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2353 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2354 DAG.getConstant(0, N1.getValueType()), Cond); 2355 } else if (N1.getNode()->hasOneUse()) { 2356 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2357 // X == (Z-X) --> X<<1 == Z 2358 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2359 DAG.getConstant(1, getShiftAmountTy())); 2360 if (!DCI.isCalledByLegalizer()) 2361 DCI.AddToWorklist(SH.getNode()); 2362 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2363 } 2364 } 2365 } 2366 2367 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2368 // Note that where y is variable and is known to have at most 2369 // one bit set (for example, if it is z&1) we cannot do this; 2370 // the expressions are not equivalent when y==0. 2371 if (N0.getOpcode() == ISD::AND) 2372 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2373 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2374 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2375 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2376 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2377 } 2378 } 2379 if (N1.getOpcode() == ISD::AND) 2380 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2381 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2382 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2383 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2384 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2385 } 2386 } 2387 } 2388 2389 // Fold away ALL boolean setcc's. 2390 SDValue Temp; 2391 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2392 switch (Cond) { 2393 default: llvm_unreachable("Unknown integer setcc!"); 2394 case ISD::SETEQ: // X == Y -> ~(X^Y) 2395 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2396 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2397 if (!DCI.isCalledByLegalizer()) 2398 DCI.AddToWorklist(Temp.getNode()); 2399 break; 2400 case ISD::SETNE: // X != Y --> (X^Y) 2401 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2402 break; 2403 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2404 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2405 Temp = DAG.getNOT(dl, N0, MVT::i1); 2406 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2407 if (!DCI.isCalledByLegalizer()) 2408 DCI.AddToWorklist(Temp.getNode()); 2409 break; 2410 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2411 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2412 Temp = DAG.getNOT(dl, N1, MVT::i1); 2413 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2414 if (!DCI.isCalledByLegalizer()) 2415 DCI.AddToWorklist(Temp.getNode()); 2416 break; 2417 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2418 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2419 Temp = DAG.getNOT(dl, N0, MVT::i1); 2420 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2421 if (!DCI.isCalledByLegalizer()) 2422 DCI.AddToWorklist(Temp.getNode()); 2423 break; 2424 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2425 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2426 Temp = DAG.getNOT(dl, N1, MVT::i1); 2427 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2428 break; 2429 } 2430 if (VT != MVT::i1) { 2431 if (!DCI.isCalledByLegalizer()) 2432 DCI.AddToWorklist(N0.getNode()); 2433 // FIXME: If running after legalize, we probably can't do this. 2434 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2435 } 2436 return N0; 2437 } 2438 2439 // Could not fold it. 2440 return SDValue(); 2441} 2442 2443/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2444/// node is a GlobalAddress + offset. 2445bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA, 2446 int64_t &Offset) const { 2447 if (isa<GlobalAddressSDNode>(N)) { 2448 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2449 GA = GASD->getGlobal(); 2450 Offset += GASD->getOffset(); 2451 return true; 2452 } 2453 2454 if (N->getOpcode() == ISD::ADD) { 2455 SDValue N1 = N->getOperand(0); 2456 SDValue N2 = N->getOperand(1); 2457 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2458 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2459 if (V) { 2460 Offset += V->getSExtValue(); 2461 return true; 2462 } 2463 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2464 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2465 if (V) { 2466 Offset += V->getSExtValue(); 2467 return true; 2468 } 2469 } 2470 } 2471 return false; 2472} 2473 2474 2475SDValue TargetLowering:: 2476PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2477 // Default implementation: no optimization. 2478 return SDValue(); 2479} 2480 2481//===----------------------------------------------------------------------===// 2482// Inline Assembler Implementation Methods 2483//===----------------------------------------------------------------------===// 2484 2485 2486TargetLowering::ConstraintType 2487TargetLowering::getConstraintType(const std::string &Constraint) const { 2488 // FIXME: lots more standard ones to handle. 2489 if (Constraint.size() == 1) { 2490 switch (Constraint[0]) { 2491 default: break; 2492 case 'r': return C_RegisterClass; 2493 case 'm': // memory 2494 case 'o': // offsetable 2495 case 'V': // not offsetable 2496 return C_Memory; 2497 case 'i': // Simple Integer or Relocatable Constant 2498 case 'n': // Simple Integer 2499 case 'E': // Floating Point Constant 2500 case 'F': // Floating Point Constant 2501 case 's': // Relocatable Constant 2502 case 'p': // Address. 2503 case 'X': // Allow ANY value. 2504 case 'I': // Target registers. 2505 case 'J': 2506 case 'K': 2507 case 'L': 2508 case 'M': 2509 case 'N': 2510 case 'O': 2511 case 'P': 2512 case '<': 2513 case '>': 2514 return C_Other; 2515 } 2516 } 2517 2518 if (Constraint.size() > 1 && Constraint[0] == '{' && 2519 Constraint[Constraint.size()-1] == '}') 2520 return C_Register; 2521 return C_Unknown; 2522} 2523 2524/// LowerXConstraint - try to replace an X constraint, which matches anything, 2525/// with another that has more specific requirements based on the type of the 2526/// corresponding operand. 2527const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2528 if (ConstraintVT.isInteger()) 2529 return "r"; 2530 if (ConstraintVT.isFloatingPoint()) 2531 return "f"; // works for many targets 2532 return 0; 2533} 2534 2535/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2536/// vector. If it is invalid, don't add anything to Ops. 2537void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2538 char ConstraintLetter, 2539 std::vector<SDValue> &Ops, 2540 SelectionDAG &DAG) const { 2541 switch (ConstraintLetter) { 2542 default: break; 2543 case 'X': // Allows any operand; labels (basic block) use this. 2544 if (Op.getOpcode() == ISD::BasicBlock) { 2545 Ops.push_back(Op); 2546 return; 2547 } 2548 // fall through 2549 case 'i': // Simple Integer or Relocatable Constant 2550 case 'n': // Simple Integer 2551 case 's': { // Relocatable Constant 2552 // These operands are interested in values of the form (GV+C), where C may 2553 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2554 // is possible and fine if either GV or C are missing. 2555 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2556 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2557 2558 // If we have "(add GV, C)", pull out GV/C 2559 if (Op.getOpcode() == ISD::ADD) { 2560 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2561 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2562 if (C == 0 || GA == 0) { 2563 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2564 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2565 } 2566 if (C == 0 || GA == 0) 2567 C = 0, GA = 0; 2568 } 2569 2570 // If we find a valid operand, map to the TargetXXX version so that the 2571 // value itself doesn't get selected. 2572 if (GA) { // Either &GV or &GV+C 2573 if (ConstraintLetter != 'n') { 2574 int64_t Offs = GA->getOffset(); 2575 if (C) Offs += C->getZExtValue(); 2576 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2577 C ? C->getDebugLoc() : DebugLoc(), 2578 Op.getValueType(), Offs)); 2579 return; 2580 } 2581 } 2582 if (C) { // just C, no GV. 2583 // Simple constants are not allowed for 's'. 2584 if (ConstraintLetter != 's') { 2585 // gcc prints these as sign extended. Sign extend value to 64 bits 2586 // now; without this it would get ZExt'd later in 2587 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2588 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2589 MVT::i64)); 2590 return; 2591 } 2592 } 2593 break; 2594 } 2595 } 2596} 2597 2598std::vector<unsigned> TargetLowering:: 2599getRegClassForInlineAsmConstraint(const std::string &Constraint, 2600 EVT VT) const { 2601 return std::vector<unsigned>(); 2602} 2603 2604 2605std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2606getRegForInlineAsmConstraint(const std::string &Constraint, 2607 EVT VT) const { 2608 if (Constraint[0] != '{') 2609 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2610 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2611 2612 // Remove the braces from around the name. 2613 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2614 2615 // Figure out which register class contains this reg. 2616 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2617 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2618 E = RI->regclass_end(); RCI != E; ++RCI) { 2619 const TargetRegisterClass *RC = *RCI; 2620 2621 // If none of the value types for this register class are valid, we 2622 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2623 bool isLegal = false; 2624 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2625 I != E; ++I) { 2626 if (isTypeLegal(*I)) { 2627 isLegal = true; 2628 break; 2629 } 2630 } 2631 2632 if (!isLegal) continue; 2633 2634 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2635 I != E; ++I) { 2636 if (RegName.equals_lower(RI->getName(*I))) 2637 return std::make_pair(*I, RC); 2638 } 2639 } 2640 2641 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2642} 2643 2644//===----------------------------------------------------------------------===// 2645// Constraint Selection. 2646 2647/// isMatchingInputConstraint - Return true of this is an input operand that is 2648/// a matching constraint like "4". 2649bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2650 assert(!ConstraintCode.empty() && "No known constraint!"); 2651 return isdigit(ConstraintCode[0]); 2652} 2653 2654/// getMatchedOperand - If this is an input matching constraint, this method 2655/// returns the output operand it matches. 2656unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2657 assert(!ConstraintCode.empty() && "No known constraint!"); 2658 return atoi(ConstraintCode.c_str()); 2659} 2660 2661 2662/// ParseConstraints - Split up the constraint string from the inline 2663/// assembly value into the specific constraints and their prefixes, 2664/// and also tie in the associated operand values. 2665/// If this returns an empty vector, and if the constraint string itself 2666/// isn't empty, there was an error parsing. 2667TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2668 ImmutableCallSite CS) const { 2669 /// ConstraintOperands - Information about all of the constraints. 2670 AsmOperandInfoVector ConstraintOperands; 2671 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2672 unsigned maCount = 0; // Largest number of multiple alternative constraints. 2673 2674 // Do a prepass over the constraints, canonicalizing them, and building up the 2675 // ConstraintOperands list. 2676 InlineAsm::ConstraintInfoVector 2677 ConstraintInfos = IA->ParseConstraints(); 2678 2679 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2680 unsigned ResNo = 0; // ResNo - The result number of the next output. 2681 2682 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 2683 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 2684 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2685 2686 // Update multiple alternative constraint count. 2687 if (OpInfo.multipleAlternatives.size() > maCount) 2688 maCount = OpInfo.multipleAlternatives.size(); 2689 2690 OpInfo.ConstraintVT = MVT::Other; 2691 2692 // Compute the value type for each operand. 2693 switch (OpInfo.Type) { 2694 case InlineAsm::isOutput: 2695 // Indirect outputs just consume an argument. 2696 if (OpInfo.isIndirect) { 2697 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2698 break; 2699 } 2700 2701 // The return value of the call is this value. As such, there is no 2702 // corresponding argument. 2703 assert(!CS.getType()->isVoidTy() && 2704 "Bad inline asm!"); 2705 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 2706 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo)); 2707 } else { 2708 assert(ResNo == 0 && "Asm only has one result!"); 2709 OpInfo.ConstraintVT = getValueType(CS.getType()); 2710 } 2711 ++ResNo; 2712 break; 2713 case InlineAsm::isInput: 2714 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2715 break; 2716 case InlineAsm::isClobber: 2717 // Nothing to do. 2718 break; 2719 } 2720 2721 if (OpInfo.CallOperandVal) { 2722 const llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2723 if (OpInfo.isIndirect) { 2724 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2725 if (!PtrTy) 2726 report_fatal_error("Indirect operand for inline asm not a pointer!"); 2727 OpTy = PtrTy->getElementType(); 2728 } 2729 // If OpTy is not a single value, it may be a struct/union that we 2730 // can tile with integers. 2731 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2732 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 2733 switch (BitSize) { 2734 default: break; 2735 case 1: 2736 case 8: 2737 case 16: 2738 case 32: 2739 case 64: 2740 case 128: 2741 OpTy = IntegerType::get(OpTy->getContext(), BitSize); 2742 break; 2743 } 2744 } else if (dyn_cast<PointerType>(OpTy)) { 2745 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize()); 2746 } else { 2747 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true); 2748 } 2749 } 2750 } 2751 2752 // If we have multiple alternative constraints, select the best alternative. 2753 if (ConstraintInfos.size()) { 2754 if (maCount) { 2755 unsigned bestMAIndex = 0; 2756 int bestWeight = -1; 2757 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2758 int weight = -1; 2759 unsigned maIndex; 2760 // Compute the sums of the weights for each alternative, keeping track 2761 // of the best (highest weight) one so far. 2762 for (maIndex = 0; maIndex < maCount; ++maIndex) { 2763 int weightSum = 0; 2764 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2765 cIndex != eIndex; ++cIndex) { 2766 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2767 if (OpInfo.Type == InlineAsm::isClobber) 2768 continue; 2769 2770 // If this is an output operand with a matching input operand, 2771 // look up the matching input. If their types mismatch, e.g. one 2772 // is an integer, the other is floating point, or their sizes are 2773 // different, flag it as an maCantMatch. 2774 if (OpInfo.hasMatchingInput()) { 2775 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2776 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2777 if ((OpInfo.ConstraintVT.isInteger() != 2778 Input.ConstraintVT.isInteger()) || 2779 (OpInfo.ConstraintVT.getSizeInBits() != 2780 Input.ConstraintVT.getSizeInBits())) { 2781 weightSum = -1; // Can't match. 2782 break; 2783 } 2784 } 2785 } 2786 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 2787 if (weight == -1) { 2788 weightSum = -1; 2789 break; 2790 } 2791 weightSum += weight; 2792 } 2793 // Update best. 2794 if (weightSum > bestWeight) { 2795 bestWeight = weightSum; 2796 bestMAIndex = maIndex; 2797 } 2798 } 2799 2800 // Now select chosen alternative in each constraint. 2801 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2802 cIndex != eIndex; ++cIndex) { 2803 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 2804 if (cInfo.Type == InlineAsm::isClobber) 2805 continue; 2806 cInfo.selectAlternative(bestMAIndex); 2807 } 2808 } 2809 } 2810 2811 // Check and hook up tied operands, choose constraint code to use. 2812 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2813 cIndex != eIndex; ++cIndex) { 2814 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2815 2816 // If this is an output operand with a matching input operand, look up the 2817 // matching input. If their types mismatch, e.g. one is an integer, the 2818 // other is floating point, or their sizes are different, flag it as an 2819 // error. 2820 if (OpInfo.hasMatchingInput()) { 2821 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2822 2823 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2824 if ((OpInfo.ConstraintVT.isInteger() != 2825 Input.ConstraintVT.isInteger()) || 2826 (OpInfo.ConstraintVT.getSizeInBits() != 2827 Input.ConstraintVT.getSizeInBits())) { 2828 report_fatal_error("Unsupported asm: input constraint" 2829 " with a matching output constraint of" 2830 " incompatible type!"); 2831 } 2832 } 2833 2834 } 2835 } 2836 2837 return ConstraintOperands; 2838} 2839 2840 2841/// getConstraintGenerality - Return an integer indicating how general CT 2842/// is. 2843static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2844 switch (CT) { 2845 default: llvm_unreachable("Unknown constraint type!"); 2846 case TargetLowering::C_Other: 2847 case TargetLowering::C_Unknown: 2848 return 0; 2849 case TargetLowering::C_Register: 2850 return 1; 2851 case TargetLowering::C_RegisterClass: 2852 return 2; 2853 case TargetLowering::C_Memory: 2854 return 3; 2855 } 2856} 2857 2858/// Examine constraint type and operand type and determine a weight value. 2859/// This object must already have been set up with the operand type 2860/// and the current alternative constraint selected. 2861TargetLowering::ConstraintWeight 2862 TargetLowering::getMultipleConstraintMatchWeight( 2863 AsmOperandInfo &info, int maIndex) const { 2864 InlineAsm::ConstraintCodeVector *rCodes; 2865 if (maIndex >= (int)info.multipleAlternatives.size()) 2866 rCodes = &info.Codes; 2867 else 2868 rCodes = &info.multipleAlternatives[maIndex].Codes; 2869 ConstraintWeight BestWeight = CW_Invalid; 2870 2871 // Loop over the options, keeping track of the most general one. 2872 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 2873 ConstraintWeight weight = 2874 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 2875 if (weight > BestWeight) 2876 BestWeight = weight; 2877 } 2878 2879 return BestWeight; 2880} 2881 2882/// Examine constraint type and operand type and determine a weight value. 2883/// This object must already have been set up with the operand type 2884/// and the current alternative constraint selected. 2885TargetLowering::ConstraintWeight 2886 TargetLowering::getSingleConstraintMatchWeight( 2887 AsmOperandInfo &info, const char *constraint) const { 2888 ConstraintWeight weight = CW_Invalid; 2889 Value *CallOperandVal = info.CallOperandVal; 2890 // If we don't have a value, we can't do a match, 2891 // but allow it at the lowest weight. 2892 if (CallOperandVal == NULL) 2893 return CW_Default; 2894 // Look at the constraint type. 2895 switch (*constraint) { 2896 case 'i': // immediate integer. 2897 case 'n': // immediate integer with a known value. 2898 if (isa<ConstantInt>(CallOperandVal)) 2899 weight = CW_Constant; 2900 break; 2901 case 's': // non-explicit intregal immediate. 2902 if (isa<GlobalValue>(CallOperandVal)) 2903 weight = CW_Constant; 2904 break; 2905 case 'E': // immediate float if host format. 2906 case 'F': // immediate float. 2907 if (isa<ConstantFP>(CallOperandVal)) 2908 weight = CW_Constant; 2909 break; 2910 case '<': // memory operand with autodecrement. 2911 case '>': // memory operand with autoincrement. 2912 case 'm': // memory operand. 2913 case 'o': // offsettable memory operand 2914 case 'V': // non-offsettable memory operand 2915 weight = CW_Memory; 2916 break; 2917 case 'r': // general register. 2918 case 'g': // general register, memory operand or immediate integer. 2919 // note: Clang converts "g" to "imr". 2920 if (CallOperandVal->getType()->isIntegerTy()) 2921 weight = CW_Register; 2922 break; 2923 case 'X': // any operand. 2924 default: 2925 weight = CW_Default; 2926 break; 2927 } 2928 return weight; 2929} 2930 2931/// ChooseConstraint - If there are multiple different constraints that we 2932/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2933/// This is somewhat tricky: constraints fall into four classes: 2934/// Other -> immediates and magic values 2935/// Register -> one specific register 2936/// RegisterClass -> a group of regs 2937/// Memory -> memory 2938/// Ideally, we would pick the most specific constraint possible: if we have 2939/// something that fits into a register, we would pick it. The problem here 2940/// is that if we have something that could either be in a register or in 2941/// memory that use of the register could cause selection of *other* 2942/// operands to fail: they might only succeed if we pick memory. Because of 2943/// this the heuristic we use is: 2944/// 2945/// 1) If there is an 'other' constraint, and if the operand is valid for 2946/// that constraint, use it. This makes us take advantage of 'i' 2947/// constraints when available. 2948/// 2) Otherwise, pick the most general constraint present. This prefers 2949/// 'm' over 'r', for example. 2950/// 2951static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2952 const TargetLowering &TLI, 2953 SDValue Op, SelectionDAG *DAG) { 2954 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2955 unsigned BestIdx = 0; 2956 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2957 int BestGenerality = -1; 2958 2959 // Loop over the options, keeping track of the most general one. 2960 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2961 TargetLowering::ConstraintType CType = 2962 TLI.getConstraintType(OpInfo.Codes[i]); 2963 2964 // If this is an 'other' constraint, see if the operand is valid for it. 2965 // For example, on X86 we might have an 'rI' constraint. If the operand 2966 // is an integer in the range [0..31] we want to use I (saving a load 2967 // of a register), otherwise we must use 'r'. 2968 if (CType == TargetLowering::C_Other && Op.getNode()) { 2969 assert(OpInfo.Codes[i].size() == 1 && 2970 "Unhandled multi-letter 'other' constraint"); 2971 std::vector<SDValue> ResultOps; 2972 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], 2973 ResultOps, *DAG); 2974 if (!ResultOps.empty()) { 2975 BestType = CType; 2976 BestIdx = i; 2977 break; 2978 } 2979 } 2980 2981 // Things with matching constraints can only be registers, per gcc 2982 // documentation. This mainly affects "g" constraints. 2983 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 2984 continue; 2985 2986 // This constraint letter is more general than the previous one, use it. 2987 int Generality = getConstraintGenerality(CType); 2988 if (Generality > BestGenerality) { 2989 BestType = CType; 2990 BestIdx = i; 2991 BestGenerality = Generality; 2992 } 2993 } 2994 2995 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2996 OpInfo.ConstraintType = BestType; 2997} 2998 2999/// ComputeConstraintToUse - Determines the constraint code and constraint 3000/// type to use for the specific AsmOperandInfo, setting 3001/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 3002void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 3003 SDValue Op, 3004 SelectionDAG *DAG) const { 3005 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 3006 3007 // Single-letter constraints ('r') are very common. 3008 if (OpInfo.Codes.size() == 1) { 3009 OpInfo.ConstraintCode = OpInfo.Codes[0]; 3010 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3011 } else { 3012 ChooseConstraint(OpInfo, *this, Op, DAG); 3013 } 3014 3015 // 'X' matches anything. 3016 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 3017 // Labels and constants are handled elsewhere ('X' is the only thing 3018 // that matches labels). For Functions, the type here is the type of 3019 // the result, which is not what we want to look at; leave them alone. 3020 Value *v = OpInfo.CallOperandVal; 3021 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 3022 OpInfo.CallOperandVal = v; 3023 return; 3024 } 3025 3026 // Otherwise, try to resolve it to something we know about by looking at 3027 // the actual operand type. 3028 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 3029 OpInfo.ConstraintCode = Repl; 3030 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3031 } 3032 } 3033} 3034 3035//===----------------------------------------------------------------------===// 3036// Loop Strength Reduction hooks 3037//===----------------------------------------------------------------------===// 3038 3039/// isLegalAddressingMode - Return true if the addressing mode represented 3040/// by AM is legal for this target, for a load/store of the specified type. 3041bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 3042 const Type *Ty) const { 3043 // The default implementation of this implements a conservative RISCy, r+r and 3044 // r+i addr mode. 3045 3046 // Allows a sign-extended 16-bit immediate field. 3047 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3048 return false; 3049 3050 // No global is ever allowed as a base. 3051 if (AM.BaseGV) 3052 return false; 3053 3054 // Only support r+r, 3055 switch (AM.Scale) { 3056 case 0: // "r+i" or just "i", depending on HasBaseReg. 3057 break; 3058 case 1: 3059 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3060 return false; 3061 // Otherwise we have r+r or r+i. 3062 break; 3063 case 2: 3064 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3065 return false; 3066 // Allow 2*r as r+r. 3067 break; 3068 } 3069 3070 return true; 3071} 3072 3073/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3074/// return a DAG expression to select that will generate the same value by 3075/// multiplying by a magic number. See: 3076/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3077SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 3078 std::vector<SDNode*>* Created) const { 3079 EVT VT = N->getValueType(0); 3080 DebugLoc dl= N->getDebugLoc(); 3081 3082 // Check to see if we can do this. 3083 // FIXME: We should be more aggressive here. 3084 if (!isTypeLegal(VT)) 3085 return SDValue(); 3086 3087 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3088 APInt::ms magics = d.magic(); 3089 3090 // Multiply the numerator (operand 0) by the magic value 3091 // FIXME: We should support doing a MUL in a wider type 3092 SDValue Q; 3093 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 3094 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 3095 DAG.getConstant(magics.m, VT)); 3096 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 3097 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 3098 N->getOperand(0), 3099 DAG.getConstant(magics.m, VT)).getNode(), 1); 3100 else 3101 return SDValue(); // No mulhs or equvialent 3102 // If d > 0 and m < 0, add the numerator 3103 if (d.isStrictlyPositive() && magics.m.isNegative()) { 3104 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 3105 if (Created) 3106 Created->push_back(Q.getNode()); 3107 } 3108 // If d < 0 and m > 0, subtract the numerator. 3109 if (d.isNegative() && magics.m.isStrictlyPositive()) { 3110 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 3111 if (Created) 3112 Created->push_back(Q.getNode()); 3113 } 3114 // Shift right algebraic if shift value is nonzero 3115 if (magics.s > 0) { 3116 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 3117 DAG.getConstant(magics.s, getShiftAmountTy())); 3118 if (Created) 3119 Created->push_back(Q.getNode()); 3120 } 3121 // Extract the sign bit and add it to the quotient 3122 SDValue T = 3123 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 3124 getShiftAmountTy())); 3125 if (Created) 3126 Created->push_back(T.getNode()); 3127 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 3128} 3129 3130/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3131/// return a DAG expression to select that will generate the same value by 3132/// multiplying by a magic number. See: 3133/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3134SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 3135 std::vector<SDNode*>* Created) const { 3136 EVT VT = N->getValueType(0); 3137 DebugLoc dl = N->getDebugLoc(); 3138 3139 // Check to see if we can do this. 3140 // FIXME: We should be more aggressive here. 3141 if (!isTypeLegal(VT)) 3142 return SDValue(); 3143 3144 // FIXME: We should use a narrower constant when the upper 3145 // bits are known to be zero. 3146 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 3147 APInt::mu magics = N1C->getAPIntValue().magicu(); 3148 3149 // Multiply the numerator (operand 0) by the magic value 3150 // FIXME: We should support doing a MUL in a wider type 3151 SDValue Q; 3152 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 3153 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 3154 DAG.getConstant(magics.m, VT)); 3155 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 3156 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 3157 N->getOperand(0), 3158 DAG.getConstant(magics.m, VT)).getNode(), 1); 3159 else 3160 return SDValue(); // No mulhu or equvialent 3161 if (Created) 3162 Created->push_back(Q.getNode()); 3163 3164 if (magics.a == 0) { 3165 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 3166 "We shouldn't generate an undefined shift!"); 3167 return DAG.getNode(ISD::SRL, dl, VT, Q, 3168 DAG.getConstant(magics.s, getShiftAmountTy())); 3169 } else { 3170 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 3171 if (Created) 3172 Created->push_back(NPQ.getNode()); 3173 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 3174 DAG.getConstant(1, getShiftAmountTy())); 3175 if (Created) 3176 Created->push_back(NPQ.getNode()); 3177 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 3178 if (Created) 3179 Created->push_back(NPQ.getNode()); 3180 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 3181 DAG.getConstant(magics.s-1, getShiftAmountTy())); 3182 } 3183} 3184