TargetLowering.cpp revision 47f1ffe0789ece734d58f5c476db7513e559a30c
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/CodeGen/Analysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineJumpTableInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/ErrorHandling.h" 31#include "llvm/Support/MathExtras.h" 32#include <cctype> 33using namespace llvm; 34 35/// We are in the process of implementing a new TypeLegalization action 36/// - the promotion of vector elements. This feature is disabled by default 37/// and only enabled using this flag. 38static cl::opt<bool> 39AllowPromoteIntElem("promote-elements", cl::Hidden, cl::init(false), 40 cl::desc("Allow promotion of integer vector element types")); 41 42namespace llvm { 43TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 44 bool isLocal = GV->hasLocalLinkage(); 45 bool isDeclaration = GV->isDeclaration(); 46 // FIXME: what should we do for protected and internal visibility? 47 // For variables, is internal different from hidden? 48 bool isHidden = GV->hasHiddenVisibility(); 49 50 if (reloc == Reloc::PIC_) { 51 if (isLocal || isHidden) 52 return TLSModel::LocalDynamic; 53 else 54 return TLSModel::GeneralDynamic; 55 } else { 56 if (!isDeclaration || isHidden) 57 return TLSModel::LocalExec; 58 else 59 return TLSModel::InitialExec; 60 } 61} 62} 63 64/// InitLibcallNames - Set default libcall names. 65/// 66static void InitLibcallNames(const char **Names) { 67 Names[RTLIB::SHL_I16] = "__ashlhi3"; 68 Names[RTLIB::SHL_I32] = "__ashlsi3"; 69 Names[RTLIB::SHL_I64] = "__ashldi3"; 70 Names[RTLIB::SHL_I128] = "__ashlti3"; 71 Names[RTLIB::SRL_I16] = "__lshrhi3"; 72 Names[RTLIB::SRL_I32] = "__lshrsi3"; 73 Names[RTLIB::SRL_I64] = "__lshrdi3"; 74 Names[RTLIB::SRL_I128] = "__lshrti3"; 75 Names[RTLIB::SRA_I16] = "__ashrhi3"; 76 Names[RTLIB::SRA_I32] = "__ashrsi3"; 77 Names[RTLIB::SRA_I64] = "__ashrdi3"; 78 Names[RTLIB::SRA_I128] = "__ashrti3"; 79 Names[RTLIB::MUL_I8] = "__mulqi3"; 80 Names[RTLIB::MUL_I16] = "__mulhi3"; 81 Names[RTLIB::MUL_I32] = "__mulsi3"; 82 Names[RTLIB::MUL_I64] = "__muldi3"; 83 Names[RTLIB::MUL_I128] = "__multi3"; 84 Names[RTLIB::MULO_I32] = "__mulosi4"; 85 Names[RTLIB::MULO_I64] = "__mulodi4"; 86 Names[RTLIB::MULO_I128] = "__muloti4"; 87 Names[RTLIB::SDIV_I8] = "__divqi3"; 88 Names[RTLIB::SDIV_I16] = "__divhi3"; 89 Names[RTLIB::SDIV_I32] = "__divsi3"; 90 Names[RTLIB::SDIV_I64] = "__divdi3"; 91 Names[RTLIB::SDIV_I128] = "__divti3"; 92 Names[RTLIB::UDIV_I8] = "__udivqi3"; 93 Names[RTLIB::UDIV_I16] = "__udivhi3"; 94 Names[RTLIB::UDIV_I32] = "__udivsi3"; 95 Names[RTLIB::UDIV_I64] = "__udivdi3"; 96 Names[RTLIB::UDIV_I128] = "__udivti3"; 97 Names[RTLIB::SREM_I8] = "__modqi3"; 98 Names[RTLIB::SREM_I16] = "__modhi3"; 99 Names[RTLIB::SREM_I32] = "__modsi3"; 100 Names[RTLIB::SREM_I64] = "__moddi3"; 101 Names[RTLIB::SREM_I128] = "__modti3"; 102 Names[RTLIB::UREM_I8] = "__umodqi3"; 103 Names[RTLIB::UREM_I16] = "__umodhi3"; 104 Names[RTLIB::UREM_I32] = "__umodsi3"; 105 Names[RTLIB::UREM_I64] = "__umoddi3"; 106 Names[RTLIB::UREM_I128] = "__umodti3"; 107 108 // These are generally not available. 109 Names[RTLIB::SDIVREM_I8] = 0; 110 Names[RTLIB::SDIVREM_I16] = 0; 111 Names[RTLIB::SDIVREM_I32] = 0; 112 Names[RTLIB::SDIVREM_I64] = 0; 113 Names[RTLIB::SDIVREM_I128] = 0; 114 Names[RTLIB::UDIVREM_I8] = 0; 115 Names[RTLIB::UDIVREM_I16] = 0; 116 Names[RTLIB::UDIVREM_I32] = 0; 117 Names[RTLIB::UDIVREM_I64] = 0; 118 Names[RTLIB::UDIVREM_I128] = 0; 119 120 Names[RTLIB::NEG_I32] = "__negsi2"; 121 Names[RTLIB::NEG_I64] = "__negdi2"; 122 Names[RTLIB::ADD_F32] = "__addsf3"; 123 Names[RTLIB::ADD_F64] = "__adddf3"; 124 Names[RTLIB::ADD_F80] = "__addxf3"; 125 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 126 Names[RTLIB::SUB_F32] = "__subsf3"; 127 Names[RTLIB::SUB_F64] = "__subdf3"; 128 Names[RTLIB::SUB_F80] = "__subxf3"; 129 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 130 Names[RTLIB::MUL_F32] = "__mulsf3"; 131 Names[RTLIB::MUL_F64] = "__muldf3"; 132 Names[RTLIB::MUL_F80] = "__mulxf3"; 133 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 134 Names[RTLIB::DIV_F32] = "__divsf3"; 135 Names[RTLIB::DIV_F64] = "__divdf3"; 136 Names[RTLIB::DIV_F80] = "__divxf3"; 137 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 138 Names[RTLIB::REM_F32] = "fmodf"; 139 Names[RTLIB::REM_F64] = "fmod"; 140 Names[RTLIB::REM_F80] = "fmodl"; 141 Names[RTLIB::REM_PPCF128] = "fmodl"; 142 Names[RTLIB::FMA_F32] = "fmaf"; 143 Names[RTLIB::FMA_F64] = "fma"; 144 Names[RTLIB::FMA_F80] = "fmal"; 145 Names[RTLIB::FMA_PPCF128] = "fmal"; 146 Names[RTLIB::POWI_F32] = "__powisf2"; 147 Names[RTLIB::POWI_F64] = "__powidf2"; 148 Names[RTLIB::POWI_F80] = "__powixf2"; 149 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 150 Names[RTLIB::SQRT_F32] = "sqrtf"; 151 Names[RTLIB::SQRT_F64] = "sqrt"; 152 Names[RTLIB::SQRT_F80] = "sqrtl"; 153 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 154 Names[RTLIB::LOG_F32] = "logf"; 155 Names[RTLIB::LOG_F64] = "log"; 156 Names[RTLIB::LOG_F80] = "logl"; 157 Names[RTLIB::LOG_PPCF128] = "logl"; 158 Names[RTLIB::LOG2_F32] = "log2f"; 159 Names[RTLIB::LOG2_F64] = "log2"; 160 Names[RTLIB::LOG2_F80] = "log2l"; 161 Names[RTLIB::LOG2_PPCF128] = "log2l"; 162 Names[RTLIB::LOG10_F32] = "log10f"; 163 Names[RTLIB::LOG10_F64] = "log10"; 164 Names[RTLIB::LOG10_F80] = "log10l"; 165 Names[RTLIB::LOG10_PPCF128] = "log10l"; 166 Names[RTLIB::EXP_F32] = "expf"; 167 Names[RTLIB::EXP_F64] = "exp"; 168 Names[RTLIB::EXP_F80] = "expl"; 169 Names[RTLIB::EXP_PPCF128] = "expl"; 170 Names[RTLIB::EXP2_F32] = "exp2f"; 171 Names[RTLIB::EXP2_F64] = "exp2"; 172 Names[RTLIB::EXP2_F80] = "exp2l"; 173 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 174 Names[RTLIB::SIN_F32] = "sinf"; 175 Names[RTLIB::SIN_F64] = "sin"; 176 Names[RTLIB::SIN_F80] = "sinl"; 177 Names[RTLIB::SIN_PPCF128] = "sinl"; 178 Names[RTLIB::COS_F32] = "cosf"; 179 Names[RTLIB::COS_F64] = "cos"; 180 Names[RTLIB::COS_F80] = "cosl"; 181 Names[RTLIB::COS_PPCF128] = "cosl"; 182 Names[RTLIB::POW_F32] = "powf"; 183 Names[RTLIB::POW_F64] = "pow"; 184 Names[RTLIB::POW_F80] = "powl"; 185 Names[RTLIB::POW_PPCF128] = "powl"; 186 Names[RTLIB::CEIL_F32] = "ceilf"; 187 Names[RTLIB::CEIL_F64] = "ceil"; 188 Names[RTLIB::CEIL_F80] = "ceill"; 189 Names[RTLIB::CEIL_PPCF128] = "ceill"; 190 Names[RTLIB::TRUNC_F32] = "truncf"; 191 Names[RTLIB::TRUNC_F64] = "trunc"; 192 Names[RTLIB::TRUNC_F80] = "truncl"; 193 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 194 Names[RTLIB::RINT_F32] = "rintf"; 195 Names[RTLIB::RINT_F64] = "rint"; 196 Names[RTLIB::RINT_F80] = "rintl"; 197 Names[RTLIB::RINT_PPCF128] = "rintl"; 198 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 199 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 200 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 201 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 202 Names[RTLIB::FLOOR_F32] = "floorf"; 203 Names[RTLIB::FLOOR_F64] = "floor"; 204 Names[RTLIB::FLOOR_F80] = "floorl"; 205 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 206 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 207 Names[RTLIB::COPYSIGN_F64] = "copysign"; 208 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 209 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 210 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 211 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 212 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 213 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 214 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 215 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 216 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 217 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 218 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 219 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 220 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 221 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 222 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 223 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 224 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 225 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 226 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 227 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 228 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 229 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 230 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 231 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 232 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 233 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 234 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 235 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 236 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 237 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 238 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 239 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 240 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 241 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 242 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 243 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 244 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 245 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 246 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 247 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 248 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 249 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 250 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 251 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 252 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 253 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 254 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 255 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 256 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 257 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 258 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 259 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 260 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 261 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 262 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 263 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 264 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 265 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 266 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 267 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 268 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 269 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 270 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 271 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 272 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 273 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 274 Names[RTLIB::OEQ_F32] = "__eqsf2"; 275 Names[RTLIB::OEQ_F64] = "__eqdf2"; 276 Names[RTLIB::UNE_F32] = "__nesf2"; 277 Names[RTLIB::UNE_F64] = "__nedf2"; 278 Names[RTLIB::OGE_F32] = "__gesf2"; 279 Names[RTLIB::OGE_F64] = "__gedf2"; 280 Names[RTLIB::OLT_F32] = "__ltsf2"; 281 Names[RTLIB::OLT_F64] = "__ltdf2"; 282 Names[RTLIB::OLE_F32] = "__lesf2"; 283 Names[RTLIB::OLE_F64] = "__ledf2"; 284 Names[RTLIB::OGT_F32] = "__gtsf2"; 285 Names[RTLIB::OGT_F64] = "__gtdf2"; 286 Names[RTLIB::UO_F32] = "__unordsf2"; 287 Names[RTLIB::UO_F64] = "__unorddf2"; 288 Names[RTLIB::O_F32] = "__unordsf2"; 289 Names[RTLIB::O_F64] = "__unorddf2"; 290 Names[RTLIB::MEMCPY] = "memcpy"; 291 Names[RTLIB::MEMMOVE] = "memmove"; 292 Names[RTLIB::MEMSET] = "memset"; 293 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 294 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 295 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 296 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 297 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 298 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 299 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 300 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 301 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 302 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 303 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 304 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 305 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 306 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 307 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 308 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 309 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 310 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 311 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 312 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 313 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 314 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 315 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 316 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 317 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 318 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 319 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 320 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 321 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 322 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 323 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 324 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 325 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 326} 327 328/// InitLibcallCallingConvs - Set default libcall CallingConvs. 329/// 330static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 331 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 332 CCs[i] = CallingConv::C; 333 } 334} 335 336/// getFPEXT - Return the FPEXT_*_* value for the given types, or 337/// UNKNOWN_LIBCALL if there is none. 338RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 339 if (OpVT == MVT::f32) { 340 if (RetVT == MVT::f64) 341 return FPEXT_F32_F64; 342 } 343 344 return UNKNOWN_LIBCALL; 345} 346 347/// getFPROUND - Return the FPROUND_*_* value for the given types, or 348/// UNKNOWN_LIBCALL if there is none. 349RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 350 if (RetVT == MVT::f32) { 351 if (OpVT == MVT::f64) 352 return FPROUND_F64_F32; 353 if (OpVT == MVT::f80) 354 return FPROUND_F80_F32; 355 if (OpVT == MVT::ppcf128) 356 return FPROUND_PPCF128_F32; 357 } else if (RetVT == MVT::f64) { 358 if (OpVT == MVT::f80) 359 return FPROUND_F80_F64; 360 if (OpVT == MVT::ppcf128) 361 return FPROUND_PPCF128_F64; 362 } 363 364 return UNKNOWN_LIBCALL; 365} 366 367/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 368/// UNKNOWN_LIBCALL if there is none. 369RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 370 if (OpVT == MVT::f32) { 371 if (RetVT == MVT::i8) 372 return FPTOSINT_F32_I8; 373 if (RetVT == MVT::i16) 374 return FPTOSINT_F32_I16; 375 if (RetVT == MVT::i32) 376 return FPTOSINT_F32_I32; 377 if (RetVT == MVT::i64) 378 return FPTOSINT_F32_I64; 379 if (RetVT == MVT::i128) 380 return FPTOSINT_F32_I128; 381 } else if (OpVT == MVT::f64) { 382 if (RetVT == MVT::i8) 383 return FPTOSINT_F64_I8; 384 if (RetVT == MVT::i16) 385 return FPTOSINT_F64_I16; 386 if (RetVT == MVT::i32) 387 return FPTOSINT_F64_I32; 388 if (RetVT == MVT::i64) 389 return FPTOSINT_F64_I64; 390 if (RetVT == MVT::i128) 391 return FPTOSINT_F64_I128; 392 } else if (OpVT == MVT::f80) { 393 if (RetVT == MVT::i32) 394 return FPTOSINT_F80_I32; 395 if (RetVT == MVT::i64) 396 return FPTOSINT_F80_I64; 397 if (RetVT == MVT::i128) 398 return FPTOSINT_F80_I128; 399 } else if (OpVT == MVT::ppcf128) { 400 if (RetVT == MVT::i32) 401 return FPTOSINT_PPCF128_I32; 402 if (RetVT == MVT::i64) 403 return FPTOSINT_PPCF128_I64; 404 if (RetVT == MVT::i128) 405 return FPTOSINT_PPCF128_I128; 406 } 407 return UNKNOWN_LIBCALL; 408} 409 410/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 411/// UNKNOWN_LIBCALL if there is none. 412RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 413 if (OpVT == MVT::f32) { 414 if (RetVT == MVT::i8) 415 return FPTOUINT_F32_I8; 416 if (RetVT == MVT::i16) 417 return FPTOUINT_F32_I16; 418 if (RetVT == MVT::i32) 419 return FPTOUINT_F32_I32; 420 if (RetVT == MVT::i64) 421 return FPTOUINT_F32_I64; 422 if (RetVT == MVT::i128) 423 return FPTOUINT_F32_I128; 424 } else if (OpVT == MVT::f64) { 425 if (RetVT == MVT::i8) 426 return FPTOUINT_F64_I8; 427 if (RetVT == MVT::i16) 428 return FPTOUINT_F64_I16; 429 if (RetVT == MVT::i32) 430 return FPTOUINT_F64_I32; 431 if (RetVT == MVT::i64) 432 return FPTOUINT_F64_I64; 433 if (RetVT == MVT::i128) 434 return FPTOUINT_F64_I128; 435 } else if (OpVT == MVT::f80) { 436 if (RetVT == MVT::i32) 437 return FPTOUINT_F80_I32; 438 if (RetVT == MVT::i64) 439 return FPTOUINT_F80_I64; 440 if (RetVT == MVT::i128) 441 return FPTOUINT_F80_I128; 442 } else if (OpVT == MVT::ppcf128) { 443 if (RetVT == MVT::i32) 444 return FPTOUINT_PPCF128_I32; 445 if (RetVT == MVT::i64) 446 return FPTOUINT_PPCF128_I64; 447 if (RetVT == MVT::i128) 448 return FPTOUINT_PPCF128_I128; 449 } 450 return UNKNOWN_LIBCALL; 451} 452 453/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 454/// UNKNOWN_LIBCALL if there is none. 455RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 456 if (OpVT == MVT::i32) { 457 if (RetVT == MVT::f32) 458 return SINTTOFP_I32_F32; 459 else if (RetVT == MVT::f64) 460 return SINTTOFP_I32_F64; 461 else if (RetVT == MVT::f80) 462 return SINTTOFP_I32_F80; 463 else if (RetVT == MVT::ppcf128) 464 return SINTTOFP_I32_PPCF128; 465 } else if (OpVT == MVT::i64) { 466 if (RetVT == MVT::f32) 467 return SINTTOFP_I64_F32; 468 else if (RetVT == MVT::f64) 469 return SINTTOFP_I64_F64; 470 else if (RetVT == MVT::f80) 471 return SINTTOFP_I64_F80; 472 else if (RetVT == MVT::ppcf128) 473 return SINTTOFP_I64_PPCF128; 474 } else if (OpVT == MVT::i128) { 475 if (RetVT == MVT::f32) 476 return SINTTOFP_I128_F32; 477 else if (RetVT == MVT::f64) 478 return SINTTOFP_I128_F64; 479 else if (RetVT == MVT::f80) 480 return SINTTOFP_I128_F80; 481 else if (RetVT == MVT::ppcf128) 482 return SINTTOFP_I128_PPCF128; 483 } 484 return UNKNOWN_LIBCALL; 485} 486 487/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 488/// UNKNOWN_LIBCALL if there is none. 489RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 490 if (OpVT == MVT::i32) { 491 if (RetVT == MVT::f32) 492 return UINTTOFP_I32_F32; 493 else if (RetVT == MVT::f64) 494 return UINTTOFP_I32_F64; 495 else if (RetVT == MVT::f80) 496 return UINTTOFP_I32_F80; 497 else if (RetVT == MVT::ppcf128) 498 return UINTTOFP_I32_PPCF128; 499 } else if (OpVT == MVT::i64) { 500 if (RetVT == MVT::f32) 501 return UINTTOFP_I64_F32; 502 else if (RetVT == MVT::f64) 503 return UINTTOFP_I64_F64; 504 else if (RetVT == MVT::f80) 505 return UINTTOFP_I64_F80; 506 else if (RetVT == MVT::ppcf128) 507 return UINTTOFP_I64_PPCF128; 508 } else if (OpVT == MVT::i128) { 509 if (RetVT == MVT::f32) 510 return UINTTOFP_I128_F32; 511 else if (RetVT == MVT::f64) 512 return UINTTOFP_I128_F64; 513 else if (RetVT == MVT::f80) 514 return UINTTOFP_I128_F80; 515 else if (RetVT == MVT::ppcf128) 516 return UINTTOFP_I128_PPCF128; 517 } 518 return UNKNOWN_LIBCALL; 519} 520 521/// InitCmpLibcallCCs - Set default comparison libcall CC. 522/// 523static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 524 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 525 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 526 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 527 CCs[RTLIB::UNE_F32] = ISD::SETNE; 528 CCs[RTLIB::UNE_F64] = ISD::SETNE; 529 CCs[RTLIB::OGE_F32] = ISD::SETGE; 530 CCs[RTLIB::OGE_F64] = ISD::SETGE; 531 CCs[RTLIB::OLT_F32] = ISD::SETLT; 532 CCs[RTLIB::OLT_F64] = ISD::SETLT; 533 CCs[RTLIB::OLE_F32] = ISD::SETLE; 534 CCs[RTLIB::OLE_F64] = ISD::SETLE; 535 CCs[RTLIB::OGT_F32] = ISD::SETGT; 536 CCs[RTLIB::OGT_F64] = ISD::SETGT; 537 CCs[RTLIB::UO_F32] = ISD::SETNE; 538 CCs[RTLIB::UO_F64] = ISD::SETNE; 539 CCs[RTLIB::O_F32] = ISD::SETEQ; 540 CCs[RTLIB::O_F64] = ISD::SETEQ; 541} 542 543/// NOTE: The constructor takes ownership of TLOF. 544TargetLowering::TargetLowering(const TargetMachine &tm, 545 const TargetLoweringObjectFile *tlof) 546 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof), 547 mayPromoteElements(AllowPromoteIntElem) { 548 // All operations default to being supported. 549 memset(OpActions, 0, sizeof(OpActions)); 550 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 551 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 552 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 553 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 554 555 // Set default actions for various operations. 556 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 557 // Default all indexed load / store to expand. 558 for (unsigned IM = (unsigned)ISD::PRE_INC; 559 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 560 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 561 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 562 } 563 564 // These operations default to expand. 565 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 566 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 567 } 568 569 // Most targets ignore the @llvm.prefetch intrinsic. 570 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 571 572 // ConstantFP nodes default to expand. Targets can either change this to 573 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 574 // to optimize expansions for certain constants. 575 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 576 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 577 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 578 579 // These library functions default to expand. 580 setOperationAction(ISD::FLOG , MVT::f64, Expand); 581 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 582 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 583 setOperationAction(ISD::FEXP , MVT::f64, Expand); 584 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 585 setOperationAction(ISD::FLOG , MVT::f32, Expand); 586 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 587 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 588 setOperationAction(ISD::FEXP , MVT::f32, Expand); 589 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 590 591 // Default ISD::TRAP to expand (which turns it into abort). 592 setOperationAction(ISD::TRAP, MVT::Other, Expand); 593 594 IsLittleEndian = TD->isLittleEndian(); 595 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 596 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 597 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 598 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 599 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize 600 = maxStoresPerMemmoveOptSize = 4; 601 benefitFromCodePlacementOpt = false; 602 UseUnderscoreSetJmp = false; 603 UseUnderscoreLongJmp = false; 604 SelectIsExpensive = false; 605 IntDivIsCheap = false; 606 Pow2DivIsCheap = false; 607 JumpIsExpensive = false; 608 StackPointerRegisterToSaveRestore = 0; 609 ExceptionPointerRegister = 0; 610 ExceptionSelectorRegister = 0; 611 BooleanContents = UndefinedBooleanContent; 612 BooleanVectorContents = UndefinedBooleanContent; 613 SchedPreferenceInfo = Sched::ILP; 614 JumpBufSize = 0; 615 JumpBufAlignment = 0; 616 MinFunctionAlignment = 0; 617 PrefFunctionAlignment = 0; 618 PrefLoopAlignment = 0; 619 MinStackArgumentAlignment = 1; 620 ShouldFoldAtomicFences = false; 621 InsertFencesForAtomic = false; 622 623 InitLibcallNames(LibcallRoutineNames); 624 InitCmpLibcallCCs(CmpLibcallCCs); 625 InitLibcallCallingConvs(LibcallCallingConvs); 626} 627 628TargetLowering::~TargetLowering() { 629 delete &TLOF; 630} 631 632MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const { 633 return MVT::getIntegerVT(8*TD->getPointerSize()); 634} 635 636/// canOpTrap - Returns true if the operation can trap for the value type. 637/// VT must be a legal type. 638bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 639 assert(isTypeLegal(VT)); 640 switch (Op) { 641 default: 642 return false; 643 case ISD::FDIV: 644 case ISD::FREM: 645 case ISD::SDIV: 646 case ISD::UDIV: 647 case ISD::SREM: 648 case ISD::UREM: 649 return true; 650 } 651} 652 653 654static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 655 unsigned &NumIntermediates, 656 EVT &RegisterVT, 657 TargetLowering *TLI) { 658 // Figure out the right, legal destination reg to copy into. 659 unsigned NumElts = VT.getVectorNumElements(); 660 MVT EltTy = VT.getVectorElementType(); 661 662 unsigned NumVectorRegs = 1; 663 664 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 665 // could break down into LHS/RHS like LegalizeDAG does. 666 if (!isPowerOf2_32(NumElts)) { 667 NumVectorRegs = NumElts; 668 NumElts = 1; 669 } 670 671 // Divide the input until we get to a supported size. This will always 672 // end with a scalar if the target doesn't support vectors. 673 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 674 NumElts >>= 1; 675 NumVectorRegs <<= 1; 676 } 677 678 NumIntermediates = NumVectorRegs; 679 680 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 681 if (!TLI->isTypeLegal(NewVT)) 682 NewVT = EltTy; 683 IntermediateVT = NewVT; 684 685 unsigned NewVTSize = NewVT.getSizeInBits(); 686 687 // Convert sizes such as i33 to i64. 688 if (!isPowerOf2_32(NewVTSize)) 689 NewVTSize = NextPowerOf2(NewVTSize); 690 691 EVT DestVT = TLI->getRegisterType(NewVT); 692 RegisterVT = DestVT; 693 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 694 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 695 696 // Otherwise, promotion or legal types use the same number of registers as 697 // the vector decimated to the appropriate level. 698 return NumVectorRegs; 699} 700 701/// isLegalRC - Return true if the value types that can be represented by the 702/// specified register class are all legal. 703bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const { 704 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 705 I != E; ++I) { 706 if (isTypeLegal(*I)) 707 return true; 708 } 709 return false; 710} 711 712/// hasLegalSuperRegRegClasses - Return true if the specified register class 713/// has one or more super-reg register classes that are legal. 714bool 715TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{ 716 if (*RC->superregclasses_begin() == 0) 717 return false; 718 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 719 E = RC->superregclasses_end(); I != E; ++I) { 720 const TargetRegisterClass *RRC = *I; 721 if (isLegalRC(RRC)) 722 return true; 723 } 724 return false; 725} 726 727/// findRepresentativeClass - Return the largest legal super-reg register class 728/// of the register class for the specified type and its associated "cost". 729std::pair<const TargetRegisterClass*, uint8_t> 730TargetLowering::findRepresentativeClass(EVT VT) const { 731 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 732 if (!RC) 733 return std::make_pair(RC, 0); 734 const TargetRegisterClass *BestRC = RC; 735 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 736 E = RC->superregclasses_end(); I != E; ++I) { 737 const TargetRegisterClass *RRC = *I; 738 if (RRC->isASubClass() || !isLegalRC(RRC)) 739 continue; 740 if (!hasLegalSuperRegRegClasses(RRC)) 741 return std::make_pair(RRC, 1); 742 BestRC = RRC; 743 } 744 return std::make_pair(BestRC, 1); 745} 746 747 748/// computeRegisterProperties - Once all of the register classes are added, 749/// this allows us to compute derived properties we expose. 750void TargetLowering::computeRegisterProperties() { 751 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 752 "Too many value types for ValueTypeActions to hold!"); 753 754 // Everything defaults to needing one register. 755 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 756 NumRegistersForVT[i] = 1; 757 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 758 } 759 // ...except isVoid, which doesn't need any registers. 760 NumRegistersForVT[MVT::isVoid] = 0; 761 762 // Find the largest integer register class. 763 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 764 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 765 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 766 767 // Every integer value type larger than this largest register takes twice as 768 // many registers to represent as the previous ValueType. 769 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 770 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 771 if (!ExpandedVT.isInteger()) 772 break; 773 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 774 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 775 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 776 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger); 777 } 778 779 // Inspect all of the ValueType's smaller than the largest integer 780 // register to see which ones need promotion. 781 unsigned LegalIntReg = LargestIntReg; 782 for (unsigned IntReg = LargestIntReg - 1; 783 IntReg >= (unsigned)MVT::i1; --IntReg) { 784 EVT IVT = (MVT::SimpleValueType)IntReg; 785 if (isTypeLegal(IVT)) { 786 LegalIntReg = IntReg; 787 } else { 788 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 789 (MVT::SimpleValueType)LegalIntReg; 790 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 791 } 792 } 793 794 // ppcf128 type is really two f64's. 795 if (!isTypeLegal(MVT::ppcf128)) { 796 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 797 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 798 TransformToType[MVT::ppcf128] = MVT::f64; 799 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 800 } 801 802 // Decide how to handle f64. If the target does not have native f64 support, 803 // expand it to i64 and we will be generating soft float library calls. 804 if (!isTypeLegal(MVT::f64)) { 805 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 806 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 807 TransformToType[MVT::f64] = MVT::i64; 808 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 809 } 810 811 // Decide how to handle f32. If the target does not have native support for 812 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 813 if (!isTypeLegal(MVT::f32)) { 814 if (isTypeLegal(MVT::f64)) { 815 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 816 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 817 TransformToType[MVT::f32] = MVT::f64; 818 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 819 } else { 820 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 821 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 822 TransformToType[MVT::f32] = MVT::i32; 823 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 824 } 825 } 826 827 // Loop over all of the vector value types to see which need transformations. 828 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 829 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 830 MVT VT = (MVT::SimpleValueType)i; 831 if (isTypeLegal(VT)) continue; 832 833 // Determine if there is a legal wider type. If so, we should promote to 834 // that wider vector type. 835 EVT EltVT = VT.getVectorElementType(); 836 unsigned NElts = VT.getVectorNumElements(); 837 if (NElts != 1) { 838 bool IsLegalWiderType = false; 839 // If we allow the promotion of vector elements using a flag, 840 // then return TypePromoteInteger on vector elements. 841 // First try to promote the elements of integer vectors. If no legal 842 // promotion was found, fallback to the widen-vector method. 843 if (mayPromoteElements) 844 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 845 EVT SVT = (MVT::SimpleValueType)nVT; 846 // Promote vectors of integers to vectors with the same number 847 // of elements, with a wider element type. 848 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 849 && SVT.getVectorNumElements() == NElts && 850 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { 851 TransformToType[i] = SVT; 852 RegisterTypeForVT[i] = SVT; 853 NumRegistersForVT[i] = 1; 854 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 855 IsLegalWiderType = true; 856 break; 857 } 858 } 859 860 if (IsLegalWiderType) continue; 861 862 // Try to widen the vector. 863 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 864 EVT SVT = (MVT::SimpleValueType)nVT; 865 if (SVT.getVectorElementType() == EltVT && 866 SVT.getVectorNumElements() > NElts && 867 isTypeLegal(SVT)) { 868 TransformToType[i] = SVT; 869 RegisterTypeForVT[i] = SVT; 870 NumRegistersForVT[i] = 1; 871 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 872 IsLegalWiderType = true; 873 break; 874 } 875 } 876 if (IsLegalWiderType) continue; 877 } 878 879 MVT IntermediateVT; 880 EVT RegisterVT; 881 unsigned NumIntermediates; 882 NumRegistersForVT[i] = 883 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 884 RegisterVT, this); 885 RegisterTypeForVT[i] = RegisterVT; 886 887 EVT NVT = VT.getPow2VectorType(); 888 if (NVT == VT) { 889 // Type is already a power of 2. The default action is to split. 890 TransformToType[i] = MVT::Other; 891 unsigned NumElts = VT.getVectorNumElements(); 892 ValueTypeActions.setTypeAction(VT, 893 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector); 894 } else { 895 TransformToType[i] = NVT; 896 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 897 } 898 } 899 900 // Determine the 'representative' register class for each value type. 901 // An representative register class is the largest (meaning one which is 902 // not a sub-register class / subreg register class) legal register class for 903 // a group of value types. For example, on i386, i8, i16, and i32 904 // representative would be GR32; while on x86_64 it's GR64. 905 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 906 const TargetRegisterClass* RRC; 907 uint8_t Cost; 908 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 909 RepRegClassForVT[i] = RRC; 910 RepRegClassCostForVT[i] = Cost; 911 } 912} 913 914const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 915 return NULL; 916} 917 918 919EVT TargetLowering::getSetCCResultType(EVT VT) const { 920 assert(!VT.isVector() && "No default SetCC type for vectors!"); 921 return PointerTy.SimpleTy; 922} 923 924MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 925 return MVT::i32; // return the default value 926} 927 928/// getVectorTypeBreakdown - Vector types are broken down into some number of 929/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 930/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 931/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 932/// 933/// This method returns the number of registers needed, and the VT for each 934/// register. It also returns the VT and quantity of the intermediate values 935/// before they are promoted/expanded. 936/// 937unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 938 EVT &IntermediateVT, 939 unsigned &NumIntermediates, 940 EVT &RegisterVT) const { 941 unsigned NumElts = VT.getVectorNumElements(); 942 943 // If there is a wider vector type with the same element type as this one, 944 // we should widen to that legal vector type. This handles things like 945 // <2 x float> -> <4 x float>. 946 if (NumElts != 1 && getTypeAction(Context, VT) == TypeWidenVector) { 947 RegisterVT = getTypeToTransformTo(Context, VT); 948 if (isTypeLegal(RegisterVT)) { 949 IntermediateVT = RegisterVT; 950 NumIntermediates = 1; 951 return 1; 952 } 953 } 954 955 // Figure out the right, legal destination reg to copy into. 956 EVT EltTy = VT.getVectorElementType(); 957 958 unsigned NumVectorRegs = 1; 959 960 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 961 // could break down into LHS/RHS like LegalizeDAG does. 962 if (!isPowerOf2_32(NumElts)) { 963 NumVectorRegs = NumElts; 964 NumElts = 1; 965 } 966 967 // Divide the input until we get to a supported size. This will always 968 // end with a scalar if the target doesn't support vectors. 969 while (NumElts > 1 && !isTypeLegal( 970 EVT::getVectorVT(Context, EltTy, NumElts))) { 971 NumElts >>= 1; 972 NumVectorRegs <<= 1; 973 } 974 975 NumIntermediates = NumVectorRegs; 976 977 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 978 if (!isTypeLegal(NewVT)) 979 NewVT = EltTy; 980 IntermediateVT = NewVT; 981 982 EVT DestVT = getRegisterType(Context, NewVT); 983 RegisterVT = DestVT; 984 unsigned NewVTSize = NewVT.getSizeInBits(); 985 986 // Convert sizes such as i33 to i64. 987 if (!isPowerOf2_32(NewVTSize)) 988 NewVTSize = NextPowerOf2(NewVTSize); 989 990 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 991 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 992 993 // Otherwise, promotion or legal types use the same number of registers as 994 // the vector decimated to the appropriate level. 995 return NumVectorRegs; 996} 997 998/// Get the EVTs and ArgFlags collections that represent the legalized return 999/// type of the given function. This does not require a DAG or a return value, 1000/// and is suitable for use before any DAGs for the function are constructed. 1001/// TODO: Move this out of TargetLowering.cpp. 1002void llvm::GetReturnInfo(Type* ReturnType, Attributes attr, 1003 SmallVectorImpl<ISD::OutputArg> &Outs, 1004 const TargetLowering &TLI, 1005 SmallVectorImpl<uint64_t> *Offsets) { 1006 SmallVector<EVT, 4> ValueVTs; 1007 ComputeValueVTs(TLI, ReturnType, ValueVTs); 1008 unsigned NumValues = ValueVTs.size(); 1009 if (NumValues == 0) return; 1010 unsigned Offset = 0; 1011 1012 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1013 EVT VT = ValueVTs[j]; 1014 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1015 1016 if (attr & Attribute::SExt) 1017 ExtendKind = ISD::SIGN_EXTEND; 1018 else if (attr & Attribute::ZExt) 1019 ExtendKind = ISD::ZERO_EXTEND; 1020 1021 // FIXME: C calling convention requires the return type to be promoted to 1022 // at least 32-bit. But this is not necessary for non-C calling 1023 // conventions. The frontend should mark functions whose return values 1024 // require promoting with signext or zeroext attributes. 1025 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1026 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1027 if (VT.bitsLT(MinVT)) 1028 VT = MinVT; 1029 } 1030 1031 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1032 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1033 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 1034 PartVT.getTypeForEVT(ReturnType->getContext())); 1035 1036 // 'inreg' on function refers to return value 1037 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1038 if (attr & Attribute::InReg) 1039 Flags.setInReg(); 1040 1041 // Propagate extension type if any 1042 if (attr & Attribute::SExt) 1043 Flags.setSExt(); 1044 else if (attr & Attribute::ZExt) 1045 Flags.setZExt(); 1046 1047 for (unsigned i = 0; i < NumParts; ++i) { 1048 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true)); 1049 if (Offsets) { 1050 Offsets->push_back(Offset); 1051 Offset += PartSize; 1052 } 1053 } 1054 } 1055} 1056 1057/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1058/// function arguments in the caller parameter area. This is the actual 1059/// alignment, not its logarithm. 1060unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const { 1061 return TD->getCallFrameTypeAlignment(Ty); 1062} 1063 1064/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1065/// current function. The returned value is a member of the 1066/// MachineJumpTableInfo::JTEntryKind enum. 1067unsigned TargetLowering::getJumpTableEncoding() const { 1068 // In non-pic modes, just use the address of a block. 1069 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 1070 return MachineJumpTableInfo::EK_BlockAddress; 1071 1072 // In PIC mode, if the target supports a GPRel32 directive, use it. 1073 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 1074 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 1075 1076 // Otherwise, use a label difference. 1077 return MachineJumpTableInfo::EK_LabelDifference32; 1078} 1079 1080SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1081 SelectionDAG &DAG) const { 1082 // If our PIC model is GP relative, use the global offset table as the base. 1083 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 1084 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 1085 return Table; 1086} 1087 1088/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1089/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1090/// MCExpr. 1091const MCExpr * 1092TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1093 unsigned JTI,MCContext &Ctx) const{ 1094 // The normal PIC reloc base is the label at the start of the jump table. 1095 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 1096} 1097 1098bool 1099TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1100 // Assume that everything is safe in static mode. 1101 if (getTargetMachine().getRelocationModel() == Reloc::Static) 1102 return true; 1103 1104 // In dynamic-no-pic mode, assume that known defined values are safe. 1105 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 1106 GA && 1107 !GA->getGlobal()->isDeclaration() && 1108 !GA->getGlobal()->isWeakForLinker()) 1109 return true; 1110 1111 // Otherwise assume nothing is safe. 1112 return false; 1113} 1114 1115//===----------------------------------------------------------------------===// 1116// Optimization Methods 1117//===----------------------------------------------------------------------===// 1118 1119/// ShrinkDemandedConstant - Check to see if the specified operand of the 1120/// specified instruction is a constant integer. If so, check to see if there 1121/// are any bits set in the constant that are not demanded. If so, shrink the 1122/// constant and return true. 1123bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 1124 const APInt &Demanded) { 1125 DebugLoc dl = Op.getDebugLoc(); 1126 1127 // FIXME: ISD::SELECT, ISD::SELECT_CC 1128 switch (Op.getOpcode()) { 1129 default: break; 1130 case ISD::XOR: 1131 case ISD::AND: 1132 case ISD::OR: { 1133 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1134 if (!C) return false; 1135 1136 if (Op.getOpcode() == ISD::XOR && 1137 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 1138 return false; 1139 1140 // if we can expand it to have all bits set, do it 1141 if (C->getAPIntValue().intersects(~Demanded)) { 1142 EVT VT = Op.getValueType(); 1143 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 1144 DAG.getConstant(Demanded & 1145 C->getAPIntValue(), 1146 VT)); 1147 return CombineTo(Op, New); 1148 } 1149 1150 break; 1151 } 1152 } 1153 1154 return false; 1155} 1156 1157/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1158/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1159/// cast, but it could be generalized for targets with other types of 1160/// implicit widening casts. 1161bool 1162TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 1163 unsigned BitWidth, 1164 const APInt &Demanded, 1165 DebugLoc dl) { 1166 assert(Op.getNumOperands() == 2 && 1167 "ShrinkDemandedOp only supports binary operators!"); 1168 assert(Op.getNode()->getNumValues() == 1 && 1169 "ShrinkDemandedOp only supports nodes with one result!"); 1170 1171 // Don't do this if the node has another user, which may require the 1172 // full value. 1173 if (!Op.getNode()->hasOneUse()) 1174 return false; 1175 1176 // Search for the smallest integer type with free casts to and from 1177 // Op's type. For expedience, just check power-of-2 integer types. 1178 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1179 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 1180 if (!isPowerOf2_32(SmallVTBits)) 1181 SmallVTBits = NextPowerOf2(SmallVTBits); 1182 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 1183 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 1184 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 1185 TLI.isZExtFree(SmallVT, Op.getValueType())) { 1186 // We found a type with free casts. 1187 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 1188 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1189 Op.getNode()->getOperand(0)), 1190 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1191 Op.getNode()->getOperand(1))); 1192 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 1193 return CombineTo(Op, Z); 1194 } 1195 } 1196 return false; 1197} 1198 1199/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1200/// DemandedMask bits of the result of Op are ever used downstream. If we can 1201/// use this information to simplify Op, create a new simplified DAG node and 1202/// return true, returning the original and new nodes in Old and New. Otherwise, 1203/// analyze the expression and return a mask of KnownOne and KnownZero bits for 1204/// the expression (used to simplify the caller). The KnownZero/One bits may 1205/// only be accurate for those bits in the DemandedMask. 1206bool TargetLowering::SimplifyDemandedBits(SDValue Op, 1207 const APInt &DemandedMask, 1208 APInt &KnownZero, 1209 APInt &KnownOne, 1210 TargetLoweringOpt &TLO, 1211 unsigned Depth) const { 1212 unsigned BitWidth = DemandedMask.getBitWidth(); 1213 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1214 "Mask size mismatches value type size!"); 1215 APInt NewMask = DemandedMask; 1216 DebugLoc dl = Op.getDebugLoc(); 1217 1218 // Don't know anything. 1219 KnownZero = KnownOne = APInt(BitWidth, 0); 1220 1221 // Other users may use these bits. 1222 if (!Op.getNode()->hasOneUse()) { 1223 if (Depth != 0) { 1224 // If not at the root, Just compute the KnownZero/KnownOne bits to 1225 // simplify things downstream. 1226 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 1227 return false; 1228 } 1229 // If this is the root being simplified, allow it to have multiple uses, 1230 // just set the NewMask to all bits. 1231 NewMask = APInt::getAllOnesValue(BitWidth); 1232 } else if (DemandedMask == 0) { 1233 // Not demanding any bits from Op. 1234 if (Op.getOpcode() != ISD::UNDEF) 1235 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1236 return false; 1237 } else if (Depth == 6) { // Limit search depth. 1238 return false; 1239 } 1240 1241 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1242 switch (Op.getOpcode()) { 1243 case ISD::Constant: 1244 // We know all of the bits for a constant! 1245 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 1246 KnownZero = ~KnownOne & NewMask; 1247 return false; // Don't fall through, will infinitely loop. 1248 case ISD::AND: 1249 // If the RHS is a constant, check to see if the LHS would be zero without 1250 // using the bits from the RHS. Below, we use knowledge about the RHS to 1251 // simplify the LHS, here we're using information from the LHS to simplify 1252 // the RHS. 1253 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1254 APInt LHSZero, LHSOne; 1255 // Do not increment Depth here; that can cause an infinite loop. 1256 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1257 LHSZero, LHSOne, Depth); 1258 // If the LHS already has zeros where RHSC does, this and is dead. 1259 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1260 return TLO.CombineTo(Op, Op.getOperand(0)); 1261 // If any of the set bits in the RHS are known zero on the LHS, shrink 1262 // the constant. 1263 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1264 return true; 1265 } 1266 1267 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1268 KnownOne, TLO, Depth+1)) 1269 return true; 1270 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1271 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1272 KnownZero2, KnownOne2, TLO, Depth+1)) 1273 return true; 1274 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1275 1276 // If all of the demanded bits are known one on one side, return the other. 1277 // These bits cannot contribute to the result of the 'and'. 1278 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1279 return TLO.CombineTo(Op, Op.getOperand(0)); 1280 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1281 return TLO.CombineTo(Op, Op.getOperand(1)); 1282 // If all of the demanded bits in the inputs are known zeros, return zero. 1283 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1284 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1285 // If the RHS is a constant, see if we can simplify it. 1286 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1287 return true; 1288 // If the operation can be done in a smaller type, do so. 1289 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1290 return true; 1291 1292 // Output known-1 bits are only known if set in both the LHS & RHS. 1293 KnownOne &= KnownOne2; 1294 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1295 KnownZero |= KnownZero2; 1296 break; 1297 case ISD::OR: 1298 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1299 KnownOne, TLO, Depth+1)) 1300 return true; 1301 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1302 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1303 KnownZero2, KnownOne2, TLO, Depth+1)) 1304 return true; 1305 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1306 1307 // If all of the demanded bits are known zero on one side, return the other. 1308 // These bits cannot contribute to the result of the 'or'. 1309 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1310 return TLO.CombineTo(Op, Op.getOperand(0)); 1311 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1312 return TLO.CombineTo(Op, Op.getOperand(1)); 1313 // If all of the potentially set bits on one side are known to be set on 1314 // the other side, just use the 'other' side. 1315 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1316 return TLO.CombineTo(Op, Op.getOperand(0)); 1317 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1318 return TLO.CombineTo(Op, Op.getOperand(1)); 1319 // If the RHS is a constant, see if we can simplify it. 1320 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1321 return true; 1322 // If the operation can be done in a smaller type, do so. 1323 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1324 return true; 1325 1326 // Output known-0 bits are only known if clear in both the LHS & RHS. 1327 KnownZero &= KnownZero2; 1328 // Output known-1 are known to be set if set in either the LHS | RHS. 1329 KnownOne |= KnownOne2; 1330 break; 1331 case ISD::XOR: 1332 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1333 KnownOne, TLO, Depth+1)) 1334 return true; 1335 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1336 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1337 KnownOne2, TLO, Depth+1)) 1338 return true; 1339 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1340 1341 // If all of the demanded bits are known zero on one side, return the other. 1342 // These bits cannot contribute to the result of the 'xor'. 1343 if ((KnownZero & NewMask) == NewMask) 1344 return TLO.CombineTo(Op, Op.getOperand(0)); 1345 if ((KnownZero2 & NewMask) == NewMask) 1346 return TLO.CombineTo(Op, Op.getOperand(1)); 1347 // If the operation can be done in a smaller type, do so. 1348 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1349 return true; 1350 1351 // If all of the unknown bits are known to be zero on one side or the other 1352 // (but not both) turn this into an *inclusive* or. 1353 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1354 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1355 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1356 Op.getOperand(0), 1357 Op.getOperand(1))); 1358 1359 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1360 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1361 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1362 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1363 1364 // If all of the demanded bits on one side are known, and all of the set 1365 // bits on that side are also known to be set on the other side, turn this 1366 // into an AND, as we know the bits will be cleared. 1367 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1368 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1369 if ((KnownOne & KnownOne2) == KnownOne) { 1370 EVT VT = Op.getValueType(); 1371 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1372 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1373 Op.getOperand(0), ANDC)); 1374 } 1375 } 1376 1377 // If the RHS is a constant, see if we can simplify it. 1378 // for XOR, we prefer to force bits to 1 if they will make a -1. 1379 // if we can't force bits, try to shrink constant 1380 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1381 APInt Expanded = C->getAPIntValue() | (~NewMask); 1382 // if we can expand it to have all bits set, do it 1383 if (Expanded.isAllOnesValue()) { 1384 if (Expanded != C->getAPIntValue()) { 1385 EVT VT = Op.getValueType(); 1386 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1387 TLO.DAG.getConstant(Expanded, VT)); 1388 return TLO.CombineTo(Op, New); 1389 } 1390 // if it already has all the bits set, nothing to change 1391 // but don't shrink either! 1392 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1393 return true; 1394 } 1395 } 1396 1397 KnownZero = KnownZeroOut; 1398 KnownOne = KnownOneOut; 1399 break; 1400 case ISD::SELECT: 1401 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1402 KnownOne, TLO, Depth+1)) 1403 return true; 1404 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1405 KnownOne2, TLO, Depth+1)) 1406 return true; 1407 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1408 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1409 1410 // If the operands are constants, see if we can simplify them. 1411 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1412 return true; 1413 1414 // Only known if known in both the LHS and RHS. 1415 KnownOne &= KnownOne2; 1416 KnownZero &= KnownZero2; 1417 break; 1418 case ISD::SELECT_CC: 1419 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1420 KnownOne, TLO, Depth+1)) 1421 return true; 1422 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1423 KnownOne2, TLO, Depth+1)) 1424 return true; 1425 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1426 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1427 1428 // If the operands are constants, see if we can simplify them. 1429 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1430 return true; 1431 1432 // Only known if known in both the LHS and RHS. 1433 KnownOne &= KnownOne2; 1434 KnownZero &= KnownZero2; 1435 break; 1436 case ISD::SHL: 1437 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1438 unsigned ShAmt = SA->getZExtValue(); 1439 SDValue InOp = Op.getOperand(0); 1440 1441 // If the shift count is an invalid immediate, don't do anything. 1442 if (ShAmt >= BitWidth) 1443 break; 1444 1445 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1446 // single shift. We can do this if the bottom bits (which are shifted 1447 // out) are never demanded. 1448 if (InOp.getOpcode() == ISD::SRL && 1449 isa<ConstantSDNode>(InOp.getOperand(1))) { 1450 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1451 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1452 unsigned Opc = ISD::SHL; 1453 int Diff = ShAmt-C1; 1454 if (Diff < 0) { 1455 Diff = -Diff; 1456 Opc = ISD::SRL; 1457 } 1458 1459 SDValue NewSA = 1460 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1461 EVT VT = Op.getValueType(); 1462 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1463 InOp.getOperand(0), NewSA)); 1464 } 1465 } 1466 1467 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 1468 KnownZero, KnownOne, TLO, Depth+1)) 1469 return true; 1470 1471 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 1472 // are not demanded. This will likely allow the anyext to be folded away. 1473 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 1474 SDValue InnerOp = InOp.getNode()->getOperand(0); 1475 EVT InnerVT = InnerOp.getValueType(); 1476 if ((APInt::getHighBitsSet(BitWidth, 1477 BitWidth - InnerVT.getSizeInBits()) & 1478 DemandedMask) == 0 && 1479 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 1480 EVT ShTy = getShiftAmountTy(InnerVT); 1481 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 1482 ShTy = InnerVT; 1483 SDValue NarrowShl = 1484 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 1485 TLO.DAG.getConstant(ShAmt, ShTy)); 1486 return 1487 TLO.CombineTo(Op, 1488 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 1489 NarrowShl)); 1490 } 1491 } 1492 1493 KnownZero <<= SA->getZExtValue(); 1494 KnownOne <<= SA->getZExtValue(); 1495 // low bits known zero. 1496 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1497 } 1498 break; 1499 case ISD::SRL: 1500 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1501 EVT VT = Op.getValueType(); 1502 unsigned ShAmt = SA->getZExtValue(); 1503 unsigned VTSize = VT.getSizeInBits(); 1504 SDValue InOp = Op.getOperand(0); 1505 1506 // If the shift count is an invalid immediate, don't do anything. 1507 if (ShAmt >= BitWidth) 1508 break; 1509 1510 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1511 // single shift. We can do this if the top bits (which are shifted out) 1512 // are never demanded. 1513 if (InOp.getOpcode() == ISD::SHL && 1514 isa<ConstantSDNode>(InOp.getOperand(1))) { 1515 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1516 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1517 unsigned Opc = ISD::SRL; 1518 int Diff = ShAmt-C1; 1519 if (Diff < 0) { 1520 Diff = -Diff; 1521 Opc = ISD::SHL; 1522 } 1523 1524 SDValue NewSA = 1525 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1526 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1527 InOp.getOperand(0), NewSA)); 1528 } 1529 } 1530 1531 // Compute the new bits that are at the top now. 1532 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1533 KnownZero, KnownOne, TLO, Depth+1)) 1534 return true; 1535 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1536 KnownZero = KnownZero.lshr(ShAmt); 1537 KnownOne = KnownOne.lshr(ShAmt); 1538 1539 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1540 KnownZero |= HighBits; // High bits known zero. 1541 } 1542 break; 1543 case ISD::SRA: 1544 // If this is an arithmetic shift right and only the low-bit is set, we can 1545 // always convert this into a logical shr, even if the shift amount is 1546 // variable. The low bit of the shift cannot be an input sign bit unless 1547 // the shift amount is >= the size of the datatype, which is undefined. 1548 if (DemandedMask == 1) 1549 return TLO.CombineTo(Op, 1550 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1551 Op.getOperand(0), Op.getOperand(1))); 1552 1553 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1554 EVT VT = Op.getValueType(); 1555 unsigned ShAmt = SA->getZExtValue(); 1556 1557 // If the shift count is an invalid immediate, don't do anything. 1558 if (ShAmt >= BitWidth) 1559 break; 1560 1561 APInt InDemandedMask = (NewMask << ShAmt); 1562 1563 // If any of the demanded bits are produced by the sign extension, we also 1564 // demand the input sign bit. 1565 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1566 if (HighBits.intersects(NewMask)) 1567 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1568 1569 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1570 KnownZero, KnownOne, TLO, Depth+1)) 1571 return true; 1572 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1573 KnownZero = KnownZero.lshr(ShAmt); 1574 KnownOne = KnownOne.lshr(ShAmt); 1575 1576 // Handle the sign bit, adjusted to where it is now in the mask. 1577 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1578 1579 // If the input sign bit is known to be zero, or if none of the top bits 1580 // are demanded, turn this into an unsigned shift right. 1581 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1582 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1583 Op.getOperand(0), 1584 Op.getOperand(1))); 1585 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1586 KnownOne |= HighBits; 1587 } 1588 } 1589 break; 1590 case ISD::SIGN_EXTEND_INREG: { 1591 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1592 1593 // Sign extension. Compute the demanded bits in the result that are not 1594 // present in the input. 1595 APInt NewBits = 1596 APInt::getHighBitsSet(BitWidth, 1597 BitWidth - EVT.getScalarType().getSizeInBits()); 1598 1599 // If none of the extended bits are demanded, eliminate the sextinreg. 1600 if ((NewBits & NewMask) == 0) 1601 return TLO.CombineTo(Op, Op.getOperand(0)); 1602 1603 APInt InSignBit = 1604 APInt::getSignBit(EVT.getScalarType().getSizeInBits()).zext(BitWidth); 1605 APInt InputDemandedBits = 1606 APInt::getLowBitsSet(BitWidth, 1607 EVT.getScalarType().getSizeInBits()) & 1608 NewMask; 1609 1610 // Since the sign extended bits are demanded, we know that the sign 1611 // bit is demanded. 1612 InputDemandedBits |= InSignBit; 1613 1614 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1615 KnownZero, KnownOne, TLO, Depth+1)) 1616 return true; 1617 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1618 1619 // If the sign bit of the input is known set or clear, then we know the 1620 // top bits of the result. 1621 1622 // If the input sign bit is known zero, convert this into a zero extension. 1623 if (KnownZero.intersects(InSignBit)) 1624 return TLO.CombineTo(Op, 1625 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1626 1627 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1628 KnownOne |= NewBits; 1629 KnownZero &= ~NewBits; 1630 } else { // Input sign bit unknown 1631 KnownZero &= ~NewBits; 1632 KnownOne &= ~NewBits; 1633 } 1634 break; 1635 } 1636 case ISD::ZERO_EXTEND: { 1637 unsigned OperandBitWidth = 1638 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1639 APInt InMask = NewMask.trunc(OperandBitWidth); 1640 1641 // If none of the top bits are demanded, convert this into an any_extend. 1642 APInt NewBits = 1643 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1644 if (!NewBits.intersects(NewMask)) 1645 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1646 Op.getValueType(), 1647 Op.getOperand(0))); 1648 1649 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1650 KnownZero, KnownOne, TLO, Depth+1)) 1651 return true; 1652 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1653 KnownZero = KnownZero.zext(BitWidth); 1654 KnownOne = KnownOne.zext(BitWidth); 1655 KnownZero |= NewBits; 1656 break; 1657 } 1658 case ISD::SIGN_EXTEND: { 1659 EVT InVT = Op.getOperand(0).getValueType(); 1660 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1661 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1662 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1663 APInt NewBits = ~InMask & NewMask; 1664 1665 // If none of the top bits are demanded, convert this into an any_extend. 1666 if (NewBits == 0) 1667 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1668 Op.getValueType(), 1669 Op.getOperand(0))); 1670 1671 // Since some of the sign extended bits are demanded, we know that the sign 1672 // bit is demanded. 1673 APInt InDemandedBits = InMask & NewMask; 1674 InDemandedBits |= InSignBit; 1675 InDemandedBits = InDemandedBits.trunc(InBits); 1676 1677 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1678 KnownOne, TLO, Depth+1)) 1679 return true; 1680 KnownZero = KnownZero.zext(BitWidth); 1681 KnownOne = KnownOne.zext(BitWidth); 1682 1683 // If the sign bit is known zero, convert this to a zero extend. 1684 if (KnownZero.intersects(InSignBit)) 1685 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1686 Op.getValueType(), 1687 Op.getOperand(0))); 1688 1689 // If the sign bit is known one, the top bits match. 1690 if (KnownOne.intersects(InSignBit)) { 1691 KnownOne |= NewBits; 1692 KnownZero &= ~NewBits; 1693 } else { // Otherwise, top bits aren't known. 1694 KnownOne &= ~NewBits; 1695 KnownZero &= ~NewBits; 1696 } 1697 break; 1698 } 1699 case ISD::ANY_EXTEND: { 1700 unsigned OperandBitWidth = 1701 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1702 APInt InMask = NewMask.trunc(OperandBitWidth); 1703 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1704 KnownZero, KnownOne, TLO, Depth+1)) 1705 return true; 1706 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1707 KnownZero = KnownZero.zext(BitWidth); 1708 KnownOne = KnownOne.zext(BitWidth); 1709 break; 1710 } 1711 case ISD::TRUNCATE: { 1712 // Simplify the input, using demanded bit information, and compute the known 1713 // zero/one bits live out. 1714 unsigned OperandBitWidth = 1715 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1716 APInt TruncMask = NewMask.zext(OperandBitWidth); 1717 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1718 KnownZero, KnownOne, TLO, Depth+1)) 1719 return true; 1720 KnownZero = KnownZero.trunc(BitWidth); 1721 KnownOne = KnownOne.trunc(BitWidth); 1722 1723 // If the input is only used by this truncate, see if we can shrink it based 1724 // on the known demanded bits. 1725 if (Op.getOperand(0).getNode()->hasOneUse()) { 1726 SDValue In = Op.getOperand(0); 1727 switch (In.getOpcode()) { 1728 default: break; 1729 case ISD::SRL: 1730 // Shrink SRL by a constant if none of the high bits shifted in are 1731 // demanded. 1732 if (TLO.LegalTypes() && 1733 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1734 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1735 // undesirable. 1736 break; 1737 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1738 if (!ShAmt) 1739 break; 1740 SDValue Shift = In.getOperand(1); 1741 if (TLO.LegalTypes()) { 1742 uint64_t ShVal = ShAmt->getZExtValue(); 1743 Shift = 1744 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType())); 1745 } 1746 1747 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1748 OperandBitWidth - BitWidth); 1749 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 1750 1751 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1752 // None of the shifted in bits are needed. Add a truncate of the 1753 // shift input, then shift it. 1754 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1755 Op.getValueType(), 1756 In.getOperand(0)); 1757 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1758 Op.getValueType(), 1759 NewTrunc, 1760 Shift)); 1761 } 1762 break; 1763 } 1764 } 1765 1766 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1767 break; 1768 } 1769 case ISD::AssertZext: { 1770 // AssertZext demands all of the high bits, plus any of the low bits 1771 // demanded by its users. 1772 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1773 APInt InMask = APInt::getLowBitsSet(BitWidth, 1774 VT.getSizeInBits()); 1775 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask, 1776 KnownZero, KnownOne, TLO, Depth+1)) 1777 return true; 1778 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1779 1780 KnownZero |= ~InMask & NewMask; 1781 break; 1782 } 1783 case ISD::BITCAST: 1784 // If this is an FP->Int bitcast and if the sign bit is the only 1785 // thing demanded, turn this into a FGETSIGN. 1786 if (!Op.getOperand(0).getValueType().isVector() && 1787 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && 1788 Op.getOperand(0).getValueType().isFloatingPoint()) { 1789 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); 1790 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); 1791 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) { 1792 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; 1793 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1794 // place. We expect the SHL to be eliminated by other optimizations. 1795 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); 1796 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits(); 1797 if (!OpVTLegal && OpVTSizeInBits > 32) 1798 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); 1799 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1800 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); 1801 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1802 Op.getValueType(), 1803 Sign, ShAmt)); 1804 } 1805 } 1806 break; 1807 case ISD::ADD: 1808 case ISD::MUL: 1809 case ISD::SUB: { 1810 // Add, Sub, and Mul don't demand any bits in positions beyond that 1811 // of the highest bit demanded of them. 1812 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1813 BitWidth - NewMask.countLeadingZeros()); 1814 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1815 KnownOne2, TLO, Depth+1)) 1816 return true; 1817 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1818 KnownOne2, TLO, Depth+1)) 1819 return true; 1820 // See if the operation should be performed at a smaller bit width. 1821 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1822 return true; 1823 } 1824 // FALL THROUGH 1825 default: 1826 // Just use ComputeMaskedBits to compute output bits. 1827 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1828 break; 1829 } 1830 1831 // If we know the value of all of the demanded bits, return this as a 1832 // constant. 1833 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1834 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1835 1836 return false; 1837} 1838 1839/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1840/// in Mask are known to be either zero or one and return them in the 1841/// KnownZero/KnownOne bitsets. 1842void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1843 const APInt &Mask, 1844 APInt &KnownZero, 1845 APInt &KnownOne, 1846 const SelectionDAG &DAG, 1847 unsigned Depth) const { 1848 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1849 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1850 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1851 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1852 "Should use MaskedValueIsZero if you don't know whether Op" 1853 " is a target node!"); 1854 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1855} 1856 1857/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1858/// targets that want to expose additional information about sign bits to the 1859/// DAG Combiner. 1860unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1861 unsigned Depth) const { 1862 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1863 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1864 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1865 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1866 "Should use ComputeNumSignBits if you don't know whether Op" 1867 " is a target node!"); 1868 return 1; 1869} 1870 1871/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1872/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1873/// determine which bit is set. 1874/// 1875static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1876 // A left-shift of a constant one will have exactly one bit set, because 1877 // shifting the bit off the end is undefined. 1878 if (Val.getOpcode() == ISD::SHL) 1879 if (ConstantSDNode *C = 1880 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1881 if (C->getAPIntValue() == 1) 1882 return true; 1883 1884 // Similarly, a right-shift of a constant sign-bit will have exactly 1885 // one bit set. 1886 if (Val.getOpcode() == ISD::SRL) 1887 if (ConstantSDNode *C = 1888 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1889 if (C->getAPIntValue().isSignBit()) 1890 return true; 1891 1892 // More could be done here, though the above checks are enough 1893 // to handle some common cases. 1894 1895 // Fall back to ComputeMaskedBits to catch other known cases. 1896 EVT OpVT = Val.getValueType(); 1897 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1898 APInt Mask = APInt::getAllOnesValue(BitWidth); 1899 APInt KnownZero, KnownOne; 1900 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1901 return (KnownZero.countPopulation() == BitWidth - 1) && 1902 (KnownOne.countPopulation() == 1); 1903} 1904 1905/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1906/// and cc. If it is unable to simplify it, return a null SDValue. 1907SDValue 1908TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1909 ISD::CondCode Cond, bool foldBooleans, 1910 DAGCombinerInfo &DCI, DebugLoc dl) const { 1911 SelectionDAG &DAG = DCI.DAG; 1912 1913 // These setcc operations always fold. 1914 switch (Cond) { 1915 default: break; 1916 case ISD::SETFALSE: 1917 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1918 case ISD::SETTRUE: 1919 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1920 } 1921 1922 // Ensure that the constant occurs on the RHS, and fold constant 1923 // comparisons. 1924 if (isa<ConstantSDNode>(N0.getNode())) 1925 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1926 1927 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1928 const APInt &C1 = N1C->getAPIntValue(); 1929 1930 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1931 // equality comparison, then we're just comparing whether X itself is 1932 // zero. 1933 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1934 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1935 N0.getOperand(1).getOpcode() == ISD::Constant) { 1936 const APInt &ShAmt 1937 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1938 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1939 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1940 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1941 // (srl (ctlz x), 5) == 0 -> X != 0 1942 // (srl (ctlz x), 5) != 1 -> X != 0 1943 Cond = ISD::SETNE; 1944 } else { 1945 // (srl (ctlz x), 5) != 0 -> X == 0 1946 // (srl (ctlz x), 5) == 1 -> X == 0 1947 Cond = ISD::SETEQ; 1948 } 1949 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1950 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1951 Zero, Cond); 1952 } 1953 } 1954 1955 SDValue CTPOP = N0; 1956 // Look through truncs that don't change the value of a ctpop. 1957 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) 1958 CTPOP = N0.getOperand(0); 1959 1960 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && 1961 (N0 == CTPOP || N0.getValueType().getSizeInBits() > 1962 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { 1963 EVT CTVT = CTPOP.getValueType(); 1964 SDValue CTOp = CTPOP.getOperand(0); 1965 1966 // (ctpop x) u< 2 -> (x & x-1) == 0 1967 // (ctpop x) u> 1 -> (x & x-1) != 0 1968 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 1969 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 1970 DAG.getConstant(1, CTVT)); 1971 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); 1972 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1973 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC); 1974 } 1975 1976 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal. 1977 } 1978 1979 // (zext x) == C --> x == (trunc C) 1980 if (DCI.isBeforeLegalize() && N0->hasOneUse() && 1981 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1982 unsigned MinBits = N0.getValueSizeInBits(); 1983 SDValue PreZExt; 1984 if (N0->getOpcode() == ISD::ZERO_EXTEND) { 1985 // ZExt 1986 MinBits = N0->getOperand(0).getValueSizeInBits(); 1987 PreZExt = N0->getOperand(0); 1988 } else if (N0->getOpcode() == ISD::AND) { 1989 // DAGCombine turns costly ZExts into ANDs 1990 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) 1991 if ((C->getAPIntValue()+1).isPowerOf2()) { 1992 MinBits = C->getAPIntValue().countTrailingOnes(); 1993 PreZExt = N0->getOperand(0); 1994 } 1995 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) { 1996 // ZEXTLOAD 1997 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { 1998 MinBits = LN0->getMemoryVT().getSizeInBits(); 1999 PreZExt = N0; 2000 } 2001 } 2002 2003 // Make sure we're not loosing bits from the constant. 2004 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) { 2005 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); 2006 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { 2007 // Will get folded away. 2008 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt); 2009 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT); 2010 return DAG.getSetCC(dl, VT, Trunc, C, Cond); 2011 } 2012 } 2013 } 2014 2015 // If the LHS is '(and load, const)', the RHS is 0, 2016 // the test is for equality or unsigned, and all 1 bits of the const are 2017 // in the same partial word, see if we can shorten the load. 2018 if (DCI.isBeforeLegalize() && 2019 N0.getOpcode() == ISD::AND && C1 == 0 && 2020 N0.getNode()->hasOneUse() && 2021 isa<LoadSDNode>(N0.getOperand(0)) && 2022 N0.getOperand(0).getNode()->hasOneUse() && 2023 isa<ConstantSDNode>(N0.getOperand(1))) { 2024 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 2025 APInt bestMask; 2026 unsigned bestWidth = 0, bestOffset = 0; 2027 if (!Lod->isVolatile() && Lod->isUnindexed()) { 2028 unsigned origWidth = N0.getValueType().getSizeInBits(); 2029 unsigned maskWidth = origWidth; 2030 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 2031 // 8 bits, but have to be careful... 2032 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 2033 origWidth = Lod->getMemoryVT().getSizeInBits(); 2034 const APInt &Mask = 2035 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2036 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 2037 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 2038 for (unsigned offset=0; offset<origWidth/width; offset++) { 2039 if ((newMask & Mask) == Mask) { 2040 if (!TD->isLittleEndian()) 2041 bestOffset = (origWidth/width - offset - 1) * (width/8); 2042 else 2043 bestOffset = (uint64_t)offset * (width/8); 2044 bestMask = Mask.lshr(offset * (width/8) * 8); 2045 bestWidth = width; 2046 break; 2047 } 2048 newMask = newMask << width; 2049 } 2050 } 2051 } 2052 if (bestWidth) { 2053 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); 2054 if (newVT.isRound()) { 2055 EVT PtrType = Lod->getOperand(1).getValueType(); 2056 SDValue Ptr = Lod->getBasePtr(); 2057 if (bestOffset != 0) 2058 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 2059 DAG.getConstant(bestOffset, PtrType)); 2060 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 2061 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 2062 Lod->getPointerInfo().getWithOffset(bestOffset), 2063 false, false, NewAlign); 2064 return DAG.getSetCC(dl, VT, 2065 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 2066 DAG.getConstant(bestMask.trunc(bestWidth), 2067 newVT)), 2068 DAG.getConstant(0LL, newVT), Cond); 2069 } 2070 } 2071 } 2072 2073 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2074 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2075 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 2076 2077 // If the comparison constant has bits in the upper part, the 2078 // zero-extended value could never match. 2079 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 2080 C1.getBitWidth() - InSize))) { 2081 switch (Cond) { 2082 case ISD::SETUGT: 2083 case ISD::SETUGE: 2084 case ISD::SETEQ: return DAG.getConstant(0, VT); 2085 case ISD::SETULT: 2086 case ISD::SETULE: 2087 case ISD::SETNE: return DAG.getConstant(1, VT); 2088 case ISD::SETGT: 2089 case ISD::SETGE: 2090 // True if the sign bit of C1 is set. 2091 return DAG.getConstant(C1.isNegative(), VT); 2092 case ISD::SETLT: 2093 case ISD::SETLE: 2094 // True if the sign bit of C1 isn't set. 2095 return DAG.getConstant(C1.isNonNegative(), VT); 2096 default: 2097 break; 2098 } 2099 } 2100 2101 // Otherwise, we can perform the comparison with the low bits. 2102 switch (Cond) { 2103 case ISD::SETEQ: 2104 case ISD::SETNE: 2105 case ISD::SETUGT: 2106 case ISD::SETUGE: 2107 case ISD::SETULT: 2108 case ISD::SETULE: { 2109 EVT newVT = N0.getOperand(0).getValueType(); 2110 if (DCI.isBeforeLegalizeOps() || 2111 (isOperationLegal(ISD::SETCC, newVT) && 2112 getCondCodeAction(Cond, newVT)==Legal)) 2113 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2114 DAG.getConstant(C1.trunc(InSize), newVT), 2115 Cond); 2116 break; 2117 } 2118 default: 2119 break; // todo, be more careful with signed comparisons 2120 } 2121 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2122 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2123 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2124 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 2125 EVT ExtDstTy = N0.getValueType(); 2126 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 2127 2128 // If the constant doesn't fit into the number of bits for the source of 2129 // the sign extension, it is impossible for both sides to be equal. 2130 if (C1.getMinSignedBits() > ExtSrcTyBits) 2131 return DAG.getConstant(Cond == ISD::SETNE, VT); 2132 2133 SDValue ZextOp; 2134 EVT Op0Ty = N0.getOperand(0).getValueType(); 2135 if (Op0Ty == ExtSrcTy) { 2136 ZextOp = N0.getOperand(0); 2137 } else { 2138 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 2139 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 2140 DAG.getConstant(Imm, Op0Ty)); 2141 } 2142 if (!DCI.isCalledByLegalizer()) 2143 DCI.AddToWorklist(ZextOp.getNode()); 2144 // Otherwise, make this a use of a zext. 2145 return DAG.getSetCC(dl, VT, ZextOp, 2146 DAG.getConstant(C1 & APInt::getLowBitsSet( 2147 ExtDstTyBits, 2148 ExtSrcTyBits), 2149 ExtDstTy), 2150 Cond); 2151 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 2152 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2153 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 2154 if (N0.getOpcode() == ISD::SETCC && 2155 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 2156 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 2157 if (TrueWhenTrue) 2158 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 2159 // Invert the condition. 2160 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 2161 CC = ISD::getSetCCInverse(CC, 2162 N0.getOperand(0).getValueType().isInteger()); 2163 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 2164 } 2165 2166 if ((N0.getOpcode() == ISD::XOR || 2167 (N0.getOpcode() == ISD::AND && 2168 N0.getOperand(0).getOpcode() == ISD::XOR && 2169 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2170 isa<ConstantSDNode>(N0.getOperand(1)) && 2171 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 2172 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 2173 // can only do this if the top bits are known zero. 2174 unsigned BitWidth = N0.getValueSizeInBits(); 2175 if (DAG.MaskedValueIsZero(N0, 2176 APInt::getHighBitsSet(BitWidth, 2177 BitWidth-1))) { 2178 // Okay, get the un-inverted input value. 2179 SDValue Val; 2180 if (N0.getOpcode() == ISD::XOR) 2181 Val = N0.getOperand(0); 2182 else { 2183 assert(N0.getOpcode() == ISD::AND && 2184 N0.getOperand(0).getOpcode() == ISD::XOR); 2185 // ((X^1)&1)^1 -> X & 1 2186 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 2187 N0.getOperand(0).getOperand(0), 2188 N0.getOperand(1)); 2189 } 2190 2191 return DAG.getSetCC(dl, VT, Val, N1, 2192 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2193 } 2194 } else if (N1C->getAPIntValue() == 1 && 2195 (VT == MVT::i1 || 2196 getBooleanContents(false) == ZeroOrOneBooleanContent)) { 2197 SDValue Op0 = N0; 2198 if (Op0.getOpcode() == ISD::TRUNCATE) 2199 Op0 = Op0.getOperand(0); 2200 2201 if ((Op0.getOpcode() == ISD::XOR) && 2202 Op0.getOperand(0).getOpcode() == ISD::SETCC && 2203 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 2204 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 2205 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 2206 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 2207 Cond); 2208 } else if (Op0.getOpcode() == ISD::AND && 2209 isa<ConstantSDNode>(Op0.getOperand(1)) && 2210 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 2211 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 2212 if (Op0.getValueType().bitsGT(VT)) 2213 Op0 = DAG.getNode(ISD::AND, dl, VT, 2214 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 2215 DAG.getConstant(1, VT)); 2216 else if (Op0.getValueType().bitsLT(VT)) 2217 Op0 = DAG.getNode(ISD::AND, dl, VT, 2218 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 2219 DAG.getConstant(1, VT)); 2220 2221 return DAG.getSetCC(dl, VT, Op0, 2222 DAG.getConstant(0, Op0.getValueType()), 2223 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2224 } 2225 } 2226 } 2227 2228 APInt MinVal, MaxVal; 2229 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 2230 if (ISD::isSignedIntSetCC(Cond)) { 2231 MinVal = APInt::getSignedMinValue(OperandBitSize); 2232 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 2233 } else { 2234 MinVal = APInt::getMinValue(OperandBitSize); 2235 MaxVal = APInt::getMaxValue(OperandBitSize); 2236 } 2237 2238 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2239 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2240 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2241 // X >= C0 --> X > (C0-1) 2242 return DAG.getSetCC(dl, VT, N0, 2243 DAG.getConstant(C1-1, N1.getValueType()), 2244 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2245 } 2246 2247 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2248 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2249 // X <= C0 --> X < (C0+1) 2250 return DAG.getSetCC(dl, VT, N0, 2251 DAG.getConstant(C1+1, N1.getValueType()), 2252 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2253 } 2254 2255 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2256 return DAG.getConstant(0, VT); // X < MIN --> false 2257 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 2258 return DAG.getConstant(1, VT); // X >= MIN --> true 2259 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 2260 return DAG.getConstant(0, VT); // X > MAX --> false 2261 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 2262 return DAG.getConstant(1, VT); // X <= MAX --> true 2263 2264 // Canonicalize setgt X, Min --> setne X, Min 2265 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2266 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2267 // Canonicalize setlt X, Max --> setne X, Max 2268 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2269 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2270 2271 // If we have setult X, 1, turn it into seteq X, 0 2272 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2273 return DAG.getSetCC(dl, VT, N0, 2274 DAG.getConstant(MinVal, N0.getValueType()), 2275 ISD::SETEQ); 2276 // If we have setugt X, Max-1, turn it into seteq X, Max 2277 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2278 return DAG.getSetCC(dl, VT, N0, 2279 DAG.getConstant(MaxVal, N0.getValueType()), 2280 ISD::SETEQ); 2281 2282 // If we have "setcc X, C0", check to see if we can shrink the immediate 2283 // by changing cc. 2284 2285 // SETUGT X, SINTMAX -> SETLT X, 0 2286 if (Cond == ISD::SETUGT && 2287 C1 == APInt::getSignedMaxValue(OperandBitSize)) 2288 return DAG.getSetCC(dl, VT, N0, 2289 DAG.getConstant(0, N1.getValueType()), 2290 ISD::SETLT); 2291 2292 // SETULT X, SINTMIN -> SETGT X, -1 2293 if (Cond == ISD::SETULT && 2294 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2295 SDValue ConstMinusOne = 2296 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2297 N1.getValueType()); 2298 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2299 } 2300 2301 // Fold bit comparisons when we can. 2302 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2303 (VT == N0.getValueType() || 2304 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2305 N0.getOpcode() == ISD::AND) 2306 if (ConstantSDNode *AndRHS = 2307 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2308 EVT ShiftTy = DCI.isBeforeLegalize() ? 2309 getPointerTy() : getShiftAmountTy(N0.getValueType()); 2310 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2311 // Perform the xform if the AND RHS is a single bit. 2312 if (AndRHS->getAPIntValue().isPowerOf2()) { 2313 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2314 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2315 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2316 } 2317 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2318 // (X & 8) == 8 --> (X & 8) >> 3 2319 // Perform the xform if C1 is a single bit. 2320 if (C1.isPowerOf2()) { 2321 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2322 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2323 DAG.getConstant(C1.logBase2(), ShiftTy))); 2324 } 2325 } 2326 } 2327 } 2328 2329 if (isa<ConstantFPSDNode>(N0.getNode())) { 2330 // Constant fold or commute setcc. 2331 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2332 if (O.getNode()) return O; 2333 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2334 // If the RHS of an FP comparison is a constant, simplify it away in 2335 // some cases. 2336 if (CFP->getValueAPF().isNaN()) { 2337 // If an operand is known to be a nan, we can fold it. 2338 switch (ISD::getUnorderedFlavor(Cond)) { 2339 default: llvm_unreachable("Unknown flavor!"); 2340 case 0: // Known false. 2341 return DAG.getConstant(0, VT); 2342 case 1: // Known true. 2343 return DAG.getConstant(1, VT); 2344 case 2: // Undefined. 2345 return DAG.getUNDEF(VT); 2346 } 2347 } 2348 2349 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2350 // constant if knowing that the operand is non-nan is enough. We prefer to 2351 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2352 // materialize 0.0. 2353 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2354 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2355 2356 // If the condition is not legal, see if we can find an equivalent one 2357 // which is legal. 2358 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2359 // If the comparison was an awkward floating-point == or != and one of 2360 // the comparison operands is infinity or negative infinity, convert the 2361 // condition to a less-awkward <= or >=. 2362 if (CFP->getValueAPF().isInfinity()) { 2363 if (CFP->getValueAPF().isNegative()) { 2364 if (Cond == ISD::SETOEQ && 2365 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2366 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2367 if (Cond == ISD::SETUEQ && 2368 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2369 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2370 if (Cond == ISD::SETUNE && 2371 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2372 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2373 if (Cond == ISD::SETONE && 2374 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2375 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2376 } else { 2377 if (Cond == ISD::SETOEQ && 2378 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2379 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2380 if (Cond == ISD::SETUEQ && 2381 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2382 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2383 if (Cond == ISD::SETUNE && 2384 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2385 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2386 if (Cond == ISD::SETONE && 2387 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2388 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2389 } 2390 } 2391 } 2392 } 2393 2394 if (N0 == N1) { 2395 // We can always fold X == X for integer setcc's. 2396 if (N0.getValueType().isInteger()) 2397 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2398 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2399 if (UOF == 2) // FP operators that are undefined on NaNs. 2400 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2401 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2402 return DAG.getConstant(UOF, VT); 2403 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2404 // if it is not already. 2405 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2406 if (NewCond != Cond) 2407 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2408 } 2409 2410 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2411 N0.getValueType().isInteger()) { 2412 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2413 N0.getOpcode() == ISD::XOR) { 2414 // Simplify (X+Y) == (X+Z) --> Y == Z 2415 if (N0.getOpcode() == N1.getOpcode()) { 2416 if (N0.getOperand(0) == N1.getOperand(0)) 2417 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2418 if (N0.getOperand(1) == N1.getOperand(1)) 2419 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2420 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2421 // If X op Y == Y op X, try other combinations. 2422 if (N0.getOperand(0) == N1.getOperand(1)) 2423 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2424 Cond); 2425 if (N0.getOperand(1) == N1.getOperand(0)) 2426 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2427 Cond); 2428 } 2429 } 2430 2431 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2432 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2433 // Turn (X+C1) == C2 --> X == C2-C1 2434 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2435 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2436 DAG.getConstant(RHSC->getAPIntValue()- 2437 LHSR->getAPIntValue(), 2438 N0.getValueType()), Cond); 2439 } 2440 2441 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2442 if (N0.getOpcode() == ISD::XOR) 2443 // If we know that all of the inverted bits are zero, don't bother 2444 // performing the inversion. 2445 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2446 return 2447 DAG.getSetCC(dl, VT, N0.getOperand(0), 2448 DAG.getConstant(LHSR->getAPIntValue() ^ 2449 RHSC->getAPIntValue(), 2450 N0.getValueType()), 2451 Cond); 2452 } 2453 2454 // Turn (C1-X) == C2 --> X == C1-C2 2455 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2456 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2457 return 2458 DAG.getSetCC(dl, VT, N0.getOperand(1), 2459 DAG.getConstant(SUBC->getAPIntValue() - 2460 RHSC->getAPIntValue(), 2461 N0.getValueType()), 2462 Cond); 2463 } 2464 } 2465 } 2466 2467 // Simplify (X+Z) == X --> Z == 0 2468 if (N0.getOperand(0) == N1) 2469 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2470 DAG.getConstant(0, N0.getValueType()), Cond); 2471 if (N0.getOperand(1) == N1) { 2472 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2473 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2474 DAG.getConstant(0, N0.getValueType()), Cond); 2475 else if (N0.getNode()->hasOneUse()) { 2476 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2477 // (Z-X) == X --> Z == X<<1 2478 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2479 N1, 2480 DAG.getConstant(1, getShiftAmountTy(N1.getValueType()))); 2481 if (!DCI.isCalledByLegalizer()) 2482 DCI.AddToWorklist(SH.getNode()); 2483 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2484 } 2485 } 2486 } 2487 2488 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2489 N1.getOpcode() == ISD::XOR) { 2490 // Simplify X == (X+Z) --> Z == 0 2491 if (N1.getOperand(0) == N0) { 2492 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2493 DAG.getConstant(0, N1.getValueType()), Cond); 2494 } else if (N1.getOperand(1) == N0) { 2495 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2496 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2497 DAG.getConstant(0, N1.getValueType()), Cond); 2498 } else if (N1.getNode()->hasOneUse()) { 2499 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2500 // X == (Z-X) --> X<<1 == Z 2501 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2502 DAG.getConstant(1, getShiftAmountTy(N0.getValueType()))); 2503 if (!DCI.isCalledByLegalizer()) 2504 DCI.AddToWorklist(SH.getNode()); 2505 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2506 } 2507 } 2508 } 2509 2510 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2511 // Note that where y is variable and is known to have at most 2512 // one bit set (for example, if it is z&1) we cannot do this; 2513 // the expressions are not equivalent when y==0. 2514 if (N0.getOpcode() == ISD::AND) 2515 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2516 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2517 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2518 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2519 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2520 } 2521 } 2522 if (N1.getOpcode() == ISD::AND) 2523 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2524 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2525 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2526 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2527 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2528 } 2529 } 2530 } 2531 2532 // Fold away ALL boolean setcc's. 2533 SDValue Temp; 2534 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2535 switch (Cond) { 2536 default: llvm_unreachable("Unknown integer setcc!"); 2537 case ISD::SETEQ: // X == Y -> ~(X^Y) 2538 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2539 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2540 if (!DCI.isCalledByLegalizer()) 2541 DCI.AddToWorklist(Temp.getNode()); 2542 break; 2543 case ISD::SETNE: // X != Y --> (X^Y) 2544 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2545 break; 2546 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2547 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2548 Temp = DAG.getNOT(dl, N0, MVT::i1); 2549 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2550 if (!DCI.isCalledByLegalizer()) 2551 DCI.AddToWorklist(Temp.getNode()); 2552 break; 2553 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2554 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2555 Temp = DAG.getNOT(dl, N1, MVT::i1); 2556 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2557 if (!DCI.isCalledByLegalizer()) 2558 DCI.AddToWorklist(Temp.getNode()); 2559 break; 2560 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2561 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2562 Temp = DAG.getNOT(dl, N0, MVT::i1); 2563 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2564 if (!DCI.isCalledByLegalizer()) 2565 DCI.AddToWorklist(Temp.getNode()); 2566 break; 2567 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2568 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2569 Temp = DAG.getNOT(dl, N1, MVT::i1); 2570 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2571 break; 2572 } 2573 if (VT != MVT::i1) { 2574 if (!DCI.isCalledByLegalizer()) 2575 DCI.AddToWorklist(N0.getNode()); 2576 // FIXME: If running after legalize, we probably can't do this. 2577 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2578 } 2579 return N0; 2580 } 2581 2582 // Could not fold it. 2583 return SDValue(); 2584} 2585 2586/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2587/// node is a GlobalAddress + offset. 2588bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA, 2589 int64_t &Offset) const { 2590 if (isa<GlobalAddressSDNode>(N)) { 2591 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2592 GA = GASD->getGlobal(); 2593 Offset += GASD->getOffset(); 2594 return true; 2595 } 2596 2597 if (N->getOpcode() == ISD::ADD) { 2598 SDValue N1 = N->getOperand(0); 2599 SDValue N2 = N->getOperand(1); 2600 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2601 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2602 if (V) { 2603 Offset += V->getSExtValue(); 2604 return true; 2605 } 2606 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2607 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2608 if (V) { 2609 Offset += V->getSExtValue(); 2610 return true; 2611 } 2612 } 2613 } 2614 2615 return false; 2616} 2617 2618 2619SDValue TargetLowering:: 2620PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2621 // Default implementation: no optimization. 2622 return SDValue(); 2623} 2624 2625//===----------------------------------------------------------------------===// 2626// Inline Assembler Implementation Methods 2627//===----------------------------------------------------------------------===// 2628 2629 2630TargetLowering::ConstraintType 2631TargetLowering::getConstraintType(const std::string &Constraint) const { 2632 if (Constraint.size() == 1) { 2633 switch (Constraint[0]) { 2634 default: break; 2635 case 'r': return C_RegisterClass; 2636 case 'm': // memory 2637 case 'o': // offsetable 2638 case 'V': // not offsetable 2639 return C_Memory; 2640 case 'i': // Simple Integer or Relocatable Constant 2641 case 'n': // Simple Integer 2642 case 'E': // Floating Point Constant 2643 case 'F': // Floating Point Constant 2644 case 's': // Relocatable Constant 2645 case 'p': // Address. 2646 case 'X': // Allow ANY value. 2647 case 'I': // Target registers. 2648 case 'J': 2649 case 'K': 2650 case 'L': 2651 case 'M': 2652 case 'N': 2653 case 'O': 2654 case 'P': 2655 case '<': 2656 case '>': 2657 return C_Other; 2658 } 2659 } 2660 2661 if (Constraint.size() > 1 && Constraint[0] == '{' && 2662 Constraint[Constraint.size()-1] == '}') 2663 return C_Register; 2664 return C_Unknown; 2665} 2666 2667/// LowerXConstraint - try to replace an X constraint, which matches anything, 2668/// with another that has more specific requirements based on the type of the 2669/// corresponding operand. 2670const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2671 if (ConstraintVT.isInteger()) 2672 return "r"; 2673 if (ConstraintVT.isFloatingPoint()) 2674 return "f"; // works for many targets 2675 return 0; 2676} 2677 2678/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2679/// vector. If it is invalid, don't add anything to Ops. 2680void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2681 std::string &Constraint, 2682 std::vector<SDValue> &Ops, 2683 SelectionDAG &DAG) const { 2684 2685 if (Constraint.length() > 1) return; 2686 2687 char ConstraintLetter = Constraint[0]; 2688 switch (ConstraintLetter) { 2689 default: break; 2690 case 'X': // Allows any operand; labels (basic block) use this. 2691 if (Op.getOpcode() == ISD::BasicBlock) { 2692 Ops.push_back(Op); 2693 return; 2694 } 2695 // fall through 2696 case 'i': // Simple Integer or Relocatable Constant 2697 case 'n': // Simple Integer 2698 case 's': { // Relocatable Constant 2699 // These operands are interested in values of the form (GV+C), where C may 2700 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2701 // is possible and fine if either GV or C are missing. 2702 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2703 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2704 2705 // If we have "(add GV, C)", pull out GV/C 2706 if (Op.getOpcode() == ISD::ADD) { 2707 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2708 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2709 if (C == 0 || GA == 0) { 2710 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2711 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2712 } 2713 if (C == 0 || GA == 0) 2714 C = 0, GA = 0; 2715 } 2716 2717 // If we find a valid operand, map to the TargetXXX version so that the 2718 // value itself doesn't get selected. 2719 if (GA) { // Either &GV or &GV+C 2720 if (ConstraintLetter != 'n') { 2721 int64_t Offs = GA->getOffset(); 2722 if (C) Offs += C->getZExtValue(); 2723 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2724 C ? C->getDebugLoc() : DebugLoc(), 2725 Op.getValueType(), Offs)); 2726 return; 2727 } 2728 } 2729 if (C) { // just C, no GV. 2730 // Simple constants are not allowed for 's'. 2731 if (ConstraintLetter != 's') { 2732 // gcc prints these as sign extended. Sign extend value to 64 bits 2733 // now; without this it would get ZExt'd later in 2734 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2735 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2736 MVT::i64)); 2737 return; 2738 } 2739 } 2740 break; 2741 } 2742 } 2743} 2744 2745std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2746getRegForInlineAsmConstraint(const std::string &Constraint, 2747 EVT VT) const { 2748 if (Constraint[0] != '{') 2749 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2750 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2751 2752 // Remove the braces from around the name. 2753 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2754 2755 // Figure out which register class contains this reg. 2756 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2757 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2758 E = RI->regclass_end(); RCI != E; ++RCI) { 2759 const TargetRegisterClass *RC = *RCI; 2760 2761 // If none of the value types for this register class are valid, we 2762 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2763 if (!isLegalRC(RC)) 2764 continue; 2765 2766 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2767 I != E; ++I) { 2768 if (RegName.equals_lower(RI->getName(*I))) 2769 return std::make_pair(*I, RC); 2770 } 2771 } 2772 2773 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2774} 2775 2776//===----------------------------------------------------------------------===// 2777// Constraint Selection. 2778 2779/// isMatchingInputConstraint - Return true of this is an input operand that is 2780/// a matching constraint like "4". 2781bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2782 assert(!ConstraintCode.empty() && "No known constraint!"); 2783 return isdigit(ConstraintCode[0]); 2784} 2785 2786/// getMatchedOperand - If this is an input matching constraint, this method 2787/// returns the output operand it matches. 2788unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2789 assert(!ConstraintCode.empty() && "No known constraint!"); 2790 return atoi(ConstraintCode.c_str()); 2791} 2792 2793 2794/// ParseConstraints - Split up the constraint string from the inline 2795/// assembly value into the specific constraints and their prefixes, 2796/// and also tie in the associated operand values. 2797/// If this returns an empty vector, and if the constraint string itself 2798/// isn't empty, there was an error parsing. 2799TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2800 ImmutableCallSite CS) const { 2801 /// ConstraintOperands - Information about all of the constraints. 2802 AsmOperandInfoVector ConstraintOperands; 2803 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2804 unsigned maCount = 0; // Largest number of multiple alternative constraints. 2805 2806 // Do a prepass over the constraints, canonicalizing them, and building up the 2807 // ConstraintOperands list. 2808 InlineAsm::ConstraintInfoVector 2809 ConstraintInfos = IA->ParseConstraints(); 2810 2811 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2812 unsigned ResNo = 0; // ResNo - The result number of the next output. 2813 2814 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 2815 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 2816 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2817 2818 // Update multiple alternative constraint count. 2819 if (OpInfo.multipleAlternatives.size() > maCount) 2820 maCount = OpInfo.multipleAlternatives.size(); 2821 2822 OpInfo.ConstraintVT = MVT::Other; 2823 2824 // Compute the value type for each operand. 2825 switch (OpInfo.Type) { 2826 case InlineAsm::isOutput: 2827 // Indirect outputs just consume an argument. 2828 if (OpInfo.isIndirect) { 2829 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2830 break; 2831 } 2832 2833 // The return value of the call is this value. As such, there is no 2834 // corresponding argument. 2835 assert(!CS.getType()->isVoidTy() && 2836 "Bad inline asm!"); 2837 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 2838 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo)); 2839 } else { 2840 assert(ResNo == 0 && "Asm only has one result!"); 2841 OpInfo.ConstraintVT = getValueType(CS.getType()); 2842 } 2843 ++ResNo; 2844 break; 2845 case InlineAsm::isInput: 2846 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2847 break; 2848 case InlineAsm::isClobber: 2849 // Nothing to do. 2850 break; 2851 } 2852 2853 if (OpInfo.CallOperandVal) { 2854 llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2855 if (OpInfo.isIndirect) { 2856 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2857 if (!PtrTy) 2858 report_fatal_error("Indirect operand for inline asm not a pointer!"); 2859 OpTy = PtrTy->getElementType(); 2860 } 2861 2862 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 2863 if (StructType *STy = dyn_cast<StructType>(OpTy)) 2864 if (STy->getNumElements() == 1) 2865 OpTy = STy->getElementType(0); 2866 2867 // If OpTy is not a single value, it may be a struct/union that we 2868 // can tile with integers. 2869 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2870 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 2871 switch (BitSize) { 2872 default: break; 2873 case 1: 2874 case 8: 2875 case 16: 2876 case 32: 2877 case 64: 2878 case 128: 2879 OpInfo.ConstraintVT = 2880 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true); 2881 break; 2882 } 2883 } else if (dyn_cast<PointerType>(OpTy)) { 2884 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize()); 2885 } else { 2886 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true); 2887 } 2888 } 2889 } 2890 2891 // If we have multiple alternative constraints, select the best alternative. 2892 if (ConstraintInfos.size()) { 2893 if (maCount) { 2894 unsigned bestMAIndex = 0; 2895 int bestWeight = -1; 2896 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2897 int weight = -1; 2898 unsigned maIndex; 2899 // Compute the sums of the weights for each alternative, keeping track 2900 // of the best (highest weight) one so far. 2901 for (maIndex = 0; maIndex < maCount; ++maIndex) { 2902 int weightSum = 0; 2903 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2904 cIndex != eIndex; ++cIndex) { 2905 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2906 if (OpInfo.Type == InlineAsm::isClobber) 2907 continue; 2908 2909 // If this is an output operand with a matching input operand, 2910 // look up the matching input. If their types mismatch, e.g. one 2911 // is an integer, the other is floating point, or their sizes are 2912 // different, flag it as an maCantMatch. 2913 if (OpInfo.hasMatchingInput()) { 2914 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2915 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2916 if ((OpInfo.ConstraintVT.isInteger() != 2917 Input.ConstraintVT.isInteger()) || 2918 (OpInfo.ConstraintVT.getSizeInBits() != 2919 Input.ConstraintVT.getSizeInBits())) { 2920 weightSum = -1; // Can't match. 2921 break; 2922 } 2923 } 2924 } 2925 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 2926 if (weight == -1) { 2927 weightSum = -1; 2928 break; 2929 } 2930 weightSum += weight; 2931 } 2932 // Update best. 2933 if (weightSum > bestWeight) { 2934 bestWeight = weightSum; 2935 bestMAIndex = maIndex; 2936 } 2937 } 2938 2939 // Now select chosen alternative in each constraint. 2940 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2941 cIndex != eIndex; ++cIndex) { 2942 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 2943 if (cInfo.Type == InlineAsm::isClobber) 2944 continue; 2945 cInfo.selectAlternative(bestMAIndex); 2946 } 2947 } 2948 } 2949 2950 // Check and hook up tied operands, choose constraint code to use. 2951 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2952 cIndex != eIndex; ++cIndex) { 2953 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2954 2955 // If this is an output operand with a matching input operand, look up the 2956 // matching input. If their types mismatch, e.g. one is an integer, the 2957 // other is floating point, or their sizes are different, flag it as an 2958 // error. 2959 if (OpInfo.hasMatchingInput()) { 2960 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2961 2962 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2963 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 2964 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT); 2965 std::pair<unsigned, const TargetRegisterClass*> InputRC = 2966 getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT); 2967 if ((OpInfo.ConstraintVT.isInteger() != 2968 Input.ConstraintVT.isInteger()) || 2969 (MatchRC.second != InputRC.second)) { 2970 report_fatal_error("Unsupported asm: input constraint" 2971 " with a matching output constraint of" 2972 " incompatible type!"); 2973 } 2974 } 2975 2976 } 2977 } 2978 2979 return ConstraintOperands; 2980} 2981 2982 2983/// getConstraintGenerality - Return an integer indicating how general CT 2984/// is. 2985static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2986 switch (CT) { 2987 default: llvm_unreachable("Unknown constraint type!"); 2988 case TargetLowering::C_Other: 2989 case TargetLowering::C_Unknown: 2990 return 0; 2991 case TargetLowering::C_Register: 2992 return 1; 2993 case TargetLowering::C_RegisterClass: 2994 return 2; 2995 case TargetLowering::C_Memory: 2996 return 3; 2997 } 2998} 2999 3000/// Examine constraint type and operand type and determine a weight value. 3001/// This object must already have been set up with the operand type 3002/// and the current alternative constraint selected. 3003TargetLowering::ConstraintWeight 3004 TargetLowering::getMultipleConstraintMatchWeight( 3005 AsmOperandInfo &info, int maIndex) const { 3006 InlineAsm::ConstraintCodeVector *rCodes; 3007 if (maIndex >= (int)info.multipleAlternatives.size()) 3008 rCodes = &info.Codes; 3009 else 3010 rCodes = &info.multipleAlternatives[maIndex].Codes; 3011 ConstraintWeight BestWeight = CW_Invalid; 3012 3013 // Loop over the options, keeping track of the most general one. 3014 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 3015 ConstraintWeight weight = 3016 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 3017 if (weight > BestWeight) 3018 BestWeight = weight; 3019 } 3020 3021 return BestWeight; 3022} 3023 3024/// Examine constraint type and operand type and determine a weight value. 3025/// This object must already have been set up with the operand type 3026/// and the current alternative constraint selected. 3027TargetLowering::ConstraintWeight 3028 TargetLowering::getSingleConstraintMatchWeight( 3029 AsmOperandInfo &info, const char *constraint) const { 3030 ConstraintWeight weight = CW_Invalid; 3031 Value *CallOperandVal = info.CallOperandVal; 3032 // If we don't have a value, we can't do a match, 3033 // but allow it at the lowest weight. 3034 if (CallOperandVal == NULL) 3035 return CW_Default; 3036 // Look at the constraint type. 3037 switch (*constraint) { 3038 case 'i': // immediate integer. 3039 case 'n': // immediate integer with a known value. 3040 if (isa<ConstantInt>(CallOperandVal)) 3041 weight = CW_Constant; 3042 break; 3043 case 's': // non-explicit intregal immediate. 3044 if (isa<GlobalValue>(CallOperandVal)) 3045 weight = CW_Constant; 3046 break; 3047 case 'E': // immediate float if host format. 3048 case 'F': // immediate float. 3049 if (isa<ConstantFP>(CallOperandVal)) 3050 weight = CW_Constant; 3051 break; 3052 case '<': // memory operand with autodecrement. 3053 case '>': // memory operand with autoincrement. 3054 case 'm': // memory operand. 3055 case 'o': // offsettable memory operand 3056 case 'V': // non-offsettable memory operand 3057 weight = CW_Memory; 3058 break; 3059 case 'r': // general register. 3060 case 'g': // general register, memory operand or immediate integer. 3061 // note: Clang converts "g" to "imr". 3062 if (CallOperandVal->getType()->isIntegerTy()) 3063 weight = CW_Register; 3064 break; 3065 case 'X': // any operand. 3066 default: 3067 weight = CW_Default; 3068 break; 3069 } 3070 return weight; 3071} 3072 3073/// ChooseConstraint - If there are multiple different constraints that we 3074/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 3075/// This is somewhat tricky: constraints fall into four classes: 3076/// Other -> immediates and magic values 3077/// Register -> one specific register 3078/// RegisterClass -> a group of regs 3079/// Memory -> memory 3080/// Ideally, we would pick the most specific constraint possible: if we have 3081/// something that fits into a register, we would pick it. The problem here 3082/// is that if we have something that could either be in a register or in 3083/// memory that use of the register could cause selection of *other* 3084/// operands to fail: they might only succeed if we pick memory. Because of 3085/// this the heuristic we use is: 3086/// 3087/// 1) If there is an 'other' constraint, and if the operand is valid for 3088/// that constraint, use it. This makes us take advantage of 'i' 3089/// constraints when available. 3090/// 2) Otherwise, pick the most general constraint present. This prefers 3091/// 'm' over 'r', for example. 3092/// 3093static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 3094 const TargetLowering &TLI, 3095 SDValue Op, SelectionDAG *DAG) { 3096 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 3097 unsigned BestIdx = 0; 3098 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 3099 int BestGenerality = -1; 3100 3101 // Loop over the options, keeping track of the most general one. 3102 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 3103 TargetLowering::ConstraintType CType = 3104 TLI.getConstraintType(OpInfo.Codes[i]); 3105 3106 // If this is an 'other' constraint, see if the operand is valid for it. 3107 // For example, on X86 we might have an 'rI' constraint. If the operand 3108 // is an integer in the range [0..31] we want to use I (saving a load 3109 // of a register), otherwise we must use 'r'. 3110 if (CType == TargetLowering::C_Other && Op.getNode()) { 3111 assert(OpInfo.Codes[i].size() == 1 && 3112 "Unhandled multi-letter 'other' constraint"); 3113 std::vector<SDValue> ResultOps; 3114 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], 3115 ResultOps, *DAG); 3116 if (!ResultOps.empty()) { 3117 BestType = CType; 3118 BestIdx = i; 3119 break; 3120 } 3121 } 3122 3123 // Things with matching constraints can only be registers, per gcc 3124 // documentation. This mainly affects "g" constraints. 3125 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 3126 continue; 3127 3128 // This constraint letter is more general than the previous one, use it. 3129 int Generality = getConstraintGenerality(CType); 3130 if (Generality > BestGenerality) { 3131 BestType = CType; 3132 BestIdx = i; 3133 BestGenerality = Generality; 3134 } 3135 } 3136 3137 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 3138 OpInfo.ConstraintType = BestType; 3139} 3140 3141/// ComputeConstraintToUse - Determines the constraint code and constraint 3142/// type to use for the specific AsmOperandInfo, setting 3143/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 3144void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 3145 SDValue Op, 3146 SelectionDAG *DAG) const { 3147 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 3148 3149 // Single-letter constraints ('r') are very common. 3150 if (OpInfo.Codes.size() == 1) { 3151 OpInfo.ConstraintCode = OpInfo.Codes[0]; 3152 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3153 } else { 3154 ChooseConstraint(OpInfo, *this, Op, DAG); 3155 } 3156 3157 // 'X' matches anything. 3158 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 3159 // Labels and constants are handled elsewhere ('X' is the only thing 3160 // that matches labels). For Functions, the type here is the type of 3161 // the result, which is not what we want to look at; leave them alone. 3162 Value *v = OpInfo.CallOperandVal; 3163 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 3164 OpInfo.CallOperandVal = v; 3165 return; 3166 } 3167 3168 // Otherwise, try to resolve it to something we know about by looking at 3169 // the actual operand type. 3170 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 3171 OpInfo.ConstraintCode = Repl; 3172 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3173 } 3174 } 3175} 3176 3177//===----------------------------------------------------------------------===// 3178// Loop Strength Reduction hooks 3179//===----------------------------------------------------------------------===// 3180 3181/// isLegalAddressingMode - Return true if the addressing mode represented 3182/// by AM is legal for this target, for a load/store of the specified type. 3183bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 3184 Type *Ty) const { 3185 // The default implementation of this implements a conservative RISCy, r+r and 3186 // r+i addr mode. 3187 3188 // Allows a sign-extended 16-bit immediate field. 3189 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3190 return false; 3191 3192 // No global is ever allowed as a base. 3193 if (AM.BaseGV) 3194 return false; 3195 3196 // Only support r+r, 3197 switch (AM.Scale) { 3198 case 0: // "r+i" or just "i", depending on HasBaseReg. 3199 break; 3200 case 1: 3201 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3202 return false; 3203 // Otherwise we have r+r or r+i. 3204 break; 3205 case 2: 3206 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3207 return false; 3208 // Allow 2*r as r+r. 3209 break; 3210 } 3211 3212 return true; 3213} 3214 3215/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication 3216/// with the multiplicative inverse of the constant. 3217SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, 3218 SelectionDAG &DAG) const { 3219 ConstantSDNode *C = cast<ConstantSDNode>(Op2); 3220 APInt d = C->getAPIntValue(); 3221 assert(d != 0 && "Division by zero!"); 3222 3223 // Shift the value upfront if it is even, so the LSB is one. 3224 unsigned ShAmt = d.countTrailingZeros(); 3225 if (ShAmt) { 3226 // TODO: For UDIV use SRL instead of SRA. 3227 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType())); 3228 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt); 3229 d = d.ashr(ShAmt); 3230 } 3231 3232 // Calculate the multiplicative inverse, using Newton's method. 3233 APInt t, xn = d; 3234 while ((t = d*xn) != 1) 3235 xn *= APInt(d.getBitWidth(), 2) - t; 3236 3237 Op2 = DAG.getConstant(xn, Op1.getValueType()); 3238 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2); 3239} 3240 3241/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3242/// return a DAG expression to select that will generate the same value by 3243/// multiplying by a magic number. See: 3244/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3245SDValue TargetLowering:: 3246BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 3247 std::vector<SDNode*>* Created) const { 3248 EVT VT = N->getValueType(0); 3249 DebugLoc dl= N->getDebugLoc(); 3250 3251 // Check to see if we can do this. 3252 // FIXME: We should be more aggressive here. 3253 if (!isTypeLegal(VT)) 3254 return SDValue(); 3255 3256 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3257 APInt::ms magics = d.magic(); 3258 3259 // Multiply the numerator (operand 0) by the magic value 3260 // FIXME: We should support doing a MUL in a wider type 3261 SDValue Q; 3262 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : 3263 isOperationLegalOrCustom(ISD::MULHS, VT)) 3264 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 3265 DAG.getConstant(magics.m, VT)); 3266 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : 3267 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 3268 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 3269 N->getOperand(0), 3270 DAG.getConstant(magics.m, VT)).getNode(), 1); 3271 else 3272 return SDValue(); // No mulhs or equvialent 3273 // If d > 0 and m < 0, add the numerator 3274 if (d.isStrictlyPositive() && magics.m.isNegative()) { 3275 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 3276 if (Created) 3277 Created->push_back(Q.getNode()); 3278 } 3279 // If d < 0 and m > 0, subtract the numerator. 3280 if (d.isNegative() && magics.m.isStrictlyPositive()) { 3281 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 3282 if (Created) 3283 Created->push_back(Q.getNode()); 3284 } 3285 // Shift right algebraic if shift value is nonzero 3286 if (magics.s > 0) { 3287 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 3288 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3289 if (Created) 3290 Created->push_back(Q.getNode()); 3291 } 3292 // Extract the sign bit and add it to the quotient 3293 SDValue T = 3294 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 3295 getShiftAmountTy(Q.getValueType()))); 3296 if (Created) 3297 Created->push_back(T.getNode()); 3298 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 3299} 3300 3301/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3302/// return a DAG expression to select that will generate the same value by 3303/// multiplying by a magic number. See: 3304/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3305SDValue TargetLowering:: 3306BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 3307 std::vector<SDNode*>* Created) const { 3308 EVT VT = N->getValueType(0); 3309 DebugLoc dl = N->getDebugLoc(); 3310 3311 // Check to see if we can do this. 3312 // FIXME: We should be more aggressive here. 3313 if (!isTypeLegal(VT)) 3314 return SDValue(); 3315 3316 // FIXME: We should use a narrower constant when the upper 3317 // bits are known to be zero. 3318 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3319 APInt::mu magics = N1C.magicu(); 3320 3321 SDValue Q = N->getOperand(0); 3322 3323 // If the divisor is even, we can avoid using the expensive fixup by shifting 3324 // the divided value upfront. 3325 if (magics.a != 0 && !N1C[0]) { 3326 unsigned Shift = N1C.countTrailingZeros(); 3327 Q = DAG.getNode(ISD::SRL, dl, VT, Q, 3328 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType()))); 3329 if (Created) 3330 Created->push_back(Q.getNode()); 3331 3332 // Get magic number for the shifted divisor. 3333 magics = N1C.lshr(Shift).magicu(Shift); 3334 assert(magics.a == 0 && "Should use cheap fixup now"); 3335 } 3336 3337 // Multiply the numerator (operand 0) by the magic value 3338 // FIXME: We should support doing a MUL in a wider type 3339 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : 3340 isOperationLegalOrCustom(ISD::MULHU, VT)) 3341 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); 3342 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : 3343 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 3344 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, 3345 DAG.getConstant(magics.m, VT)).getNode(), 1); 3346 else 3347 return SDValue(); // No mulhu or equvialent 3348 if (Created) 3349 Created->push_back(Q.getNode()); 3350 3351 if (magics.a == 0) { 3352 assert(magics.s < N1C.getBitWidth() && 3353 "We shouldn't generate an undefined shift!"); 3354 return DAG.getNode(ISD::SRL, dl, VT, Q, 3355 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3356 } else { 3357 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 3358 if (Created) 3359 Created->push_back(NPQ.getNode()); 3360 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 3361 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType()))); 3362 if (Created) 3363 Created->push_back(NPQ.getNode()); 3364 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 3365 if (Created) 3366 Created->push_back(NPQ.getNode()); 3367 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 3368 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType()))); 3369 } 3370} 3371