TargetLowering.cpp revision 4ccb070f158b0f331c68de800c6bab8c31c2ecb6
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/Target/TargetMachine.h" 16#include "llvm/Target/MRegisterInfo.h" 17#include "llvm/CodeGen/SelectionDAG.h" 18#include "llvm/ADT/StringExtras.h" 19using namespace llvm; 20 21TargetLowering::TargetLowering(TargetMachine &tm) 22 : TM(tm), TD(TM.getTargetData()), ValueTypeActions(0) { 23 assert(ISD::BUILTIN_OP_END <= 128 && 24 "Fixed size array in TargetLowering is not large enough!"); 25 // All operations default to being supported. 26 memset(OpActions, 0, sizeof(OpActions)); 27 28 IsLittleEndian = TD.isLittleEndian(); 29 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType()); 30 ShiftAmtHandling = Undefined; 31 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 32 maxStoresPerMemSet = maxStoresPerMemCpy = maxStoresPerMemMove = 8; 33 allowUnalignedMemoryAccesses = false; 34 UseUnderscoreSetJmpLongJmp = false; 35 IntDivIsCheap = false; 36 Pow2DivIsCheap = false; 37 StackPointerRegisterToSaveRestore = 0; 38 SchedPreferenceInfo = SchedulingForLatency; 39} 40 41TargetLowering::~TargetLowering() {} 42 43/// setValueTypeAction - Set the action for a particular value type. This 44/// assumes an action has not already been set for this value type. 45static void SetValueTypeAction(MVT::ValueType VT, 46 TargetLowering::LegalizeAction Action, 47 TargetLowering &TLI, 48 MVT::ValueType *TransformToType, 49 unsigned long long &ValueTypeActions) { 50 ValueTypeActions |= (unsigned long long)Action << (VT*2); 51 if (Action == TargetLowering::Promote) { 52 MVT::ValueType PromoteTo; 53 if (VT == MVT::f32) 54 PromoteTo = MVT::f64; 55 else { 56 unsigned LargerReg = VT+1; 57 while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) { 58 ++LargerReg; 59 assert(MVT::isInteger((MVT::ValueType)LargerReg) && 60 "Nothing to promote to??"); 61 } 62 PromoteTo = (MVT::ValueType)LargerReg; 63 } 64 65 assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) && 66 MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) && 67 "Can only promote from int->int or fp->fp!"); 68 assert(VT < PromoteTo && "Must promote to a larger type!"); 69 TransformToType[VT] = PromoteTo; 70 } else if (Action == TargetLowering::Expand) { 71 assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 && 72 "Cannot expand this type: target must support SOME integer reg!"); 73 // Expand to the next smaller integer type! 74 TransformToType[VT] = (MVT::ValueType)(VT-1); 75 } 76} 77 78 79/// computeRegisterProperties - Once all of the register classes are added, 80/// this allows us to compute derived properties we expose. 81void TargetLowering::computeRegisterProperties() { 82 assert(MVT::LAST_VALUETYPE <= 32 && 83 "Too many value types for ValueTypeActions to hold!"); 84 85 // Everything defaults to one. 86 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) 87 NumElementsForVT[i] = 1; 88 89 // Find the largest integer register class. 90 unsigned LargestIntReg = MVT::i128; 91 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 92 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 93 94 // Every integer value type larger than this largest register takes twice as 95 // many registers to represent as the previous ValueType. 96 unsigned ExpandedReg = LargestIntReg; ++LargestIntReg; 97 for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg) 98 NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1]; 99 100 // Inspect all of the ValueType's possible, deciding how to process them. 101 for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg) 102 // If we are expanding this type, expand it! 103 if (getNumElements((MVT::ValueType)IntReg) != 1) 104 SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType, 105 ValueTypeActions); 106 else if (!isTypeLegal((MVT::ValueType)IntReg)) 107 // Otherwise, if we don't have native support, we must promote to a 108 // larger type. 109 SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this, 110 TransformToType, ValueTypeActions); 111 else 112 TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg; 113 114 // If the target does not have native support for F32, promote it to F64. 115 if (!isTypeLegal(MVT::f32)) 116 SetValueTypeAction(MVT::f32, Promote, *this, 117 TransformToType, ValueTypeActions); 118 else 119 TransformToType[MVT::f32] = MVT::f32; 120 121 // Set MVT::Vector to always be Expanded 122 SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType, 123 ValueTypeActions); 124 125 assert(isTypeLegal(MVT::f64) && "Target does not support FP?"); 126 TransformToType[MVT::f64] = MVT::f64; 127} 128 129const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 130 return NULL; 131} 132 133bool TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op, 134 uint64_t Mask) const { 135 return false; 136} 137 138std::vector<unsigned> TargetLowering:: 139getRegForInlineAsmConstraint(const std::string &Constraint) const { 140 // Scan to see if this constraint is a register name. 141 const MRegisterInfo *RI = TM.getRegisterInfo(); 142 for (unsigned i = 1, e = RI->getNumRegs(); i != e; ++i) { 143 if (const char *Name = RI->get(i).Name) 144 if (StringsEqualNoCase(Constraint, Name)) 145 return std::vector<unsigned>(1, i); 146 } 147 148 // Not a physreg, must not be a register reference or something. 149 return std::vector<unsigned>(); 150} 151 152